[mips] zeroext and logical 'and' mask optimizations

[sdardis]

Summary

This patch teaches the MIPS backend to use shifts and bitwise extract and
inserts when a solid mask of the form 0...1 or 1...0 rather than synthesising
the corresponding mask into a register and performing a logical and.

For MIPSR2, (d)ins(u) and (d)ext along with the zero register can be used to
implement masking operations that would be use logical and with a large
constant.

This reduces all such masking operations to a maximum of 2 instructions (shift
left+shift right or vice versa) or a minimum of one (bitwise extract or bitwise
insert with zero) in some cases.

As part of this, use the same trick to optimize zeroext for MIPS64R2.

[dsanders]

LGTM with some nits fixed

lib/Target/Mips/Mips64InstrInfo.td

600

indentation (align to the 'ZERO_64')

lib/Target/Mips/MipsInstrInfo.td

1093

I read this only being true for 0xffffffffffffffff but I know that's not what you're trying to say. It might be best to describe it in terms of leading ones and trailing zeros:

A mask where all bits are either leading ones or trailing zeros where there are at most 32 leading ones.

1096–1113

I think this could be simplified to:

bool Isi32 = N->getValueType(0) == MVT::i32;

uint64_t Value = N->getZExtValue();
if (Isi32)
  Value <<= 32;

unsigned TrailingZeros = countTrailingZeros(Value);
unsigned LeadingOnes = countLeadingOnes(Value);

return (LeadingOnes + TrailingZeros) == 64;

or alternatively:

if (N->getValueType(0) == MVT::i32) {
  uint32_t Value = N->getZExtValue();
  return countLeadingOnes(Value) + countTrailingZeros(Value) == 32;
}

uint64_t Value = N->getZExtValue();
return countLeadingOnes(Value) + countTrailingZeros(Value) == 64 && countLeadingOnes(Value) < 32;

Similarly for the others

1113

double semi-colon

2638–2645

This is for another patch, but we're not limited to leading or trailing ones. For example:

0x00ffff00

can be done with:

ext $rd, $rs, 8, 16

and:

0xff0000ff

can be done with:

ins $rd, $zero, 8, 16

2659

indentation (align to the 'RT')

2663

indentation (align to the 'RT')

test/CodeGen/Mips/fcopysign-f32-f64.ll

16–17

Why change the regex from {{[0-9]+}} to {{[0-9a-z]+}}? The register should always be numeric.

41–44

I believe the {{.*}} can only be 'f12'.

test/CodeGen/Mips/fcopysign.ll

9–17

This should be:

mfc1 $[[MFC:[0-9]+]], $f13
srl $[[R0:[0-9]+]], $[[MFC]], 32

11

I believe the {{.*}} can only be 'f12'. Likewise for the similar tests below.

test/CodeGen/Mips/llvm-ir/and-opts.ll

14

Could you handle the registers like fcopysign.ll does (i.e. with [[FOO:[0-9]+]] and [[FOO]])? This is important for the multi-instruction cases below.

Also, why is [a-z] permitted in the register numbers?

24

The '20' is missing on this line

37

The '24' is missing on this line

83

I believe the second operand must be $zero. Likewise for the other dinsu's below

[sdardis]

Would you mind taking a second look at this?

Addressed review comments, added DEXT64_32_MM64R6 as llvm-mc would match dext in microMIPS64R6 to MIPS64R2's dext which has a different encoding.

[sdardis]

lib/Target/Mips/MipsInstrInfo.td

2638–2645

I was considering that but judged to a bit too specific do do in the first round of this potential patch series. I mostly wanted to hit the bad cases of zext.

[sdardis]

Ping.

[vkalintiris]

Can you take a look at CodeGen/Mips/cconv/arguments-varargs.ll because it fails for me (and rebase the patch while at it :))?

[vkalintiris]

Marking this with "Request Changes" based on my last comment.

lib/Target/Mips/MicroMips64r6InstrInfo.td

class DAHI_DATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
   dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
   string Constraints = "$rs = $rt";
 }
 class DAHI_MMR6_DESC : DAHI_DATI_DESC_BASE<"dahi", GPR64Opnd>;
 class DATI_MMR6_DESC : DAHI_DATI_DESC_BASE<"dati", GPR64Opnd>;
 
 class EXTBITS_DESC_BASE<string instr_asm, RegisterOperand RO, Operand PosOpnd,
-                        Operand SizeOpnd, SDPatternOperator Op = null_frag>
+                        Operand SizeOpnd, SDPatternOperator Op = null_frag,
+                        RegisterOperand RT = RO>
     : MMR6Arch<instr_asm>, MipsR6Inst {
-  dag OutOperandList = (outs RO:$rt);
+  dag OutOperandList = (outs RT:$rt);
   dag InOperandList = (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size);
   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $pos, $size");
-  list<dag> Pattern = [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))];
+  list<dag> Pattern = [(set RT:$rt, (Op RO:$rs, imm:$pos, imm:$size))];
   InstrItinClass Itinerary = II_EXT;
   Format Form = FrmR;
   string BaseOpcode = instr_asm;
 }
 // TODO: Add 'pos + size' constraint check to dext* instructions
 //       DEXT: 0 < pos + size <= 63
 //       DEXTM, DEXTU: 32 < pos + size <= 64
 class DEXT_MMR6_DESC : EXTBITS_DESC_BASE<"dext", GPR64Opnd, uimm5_report_uimm6,
                                          uimm5_plus1, MipsExt>;
 class DEXTM_MMR6_DESC : EXTBITS_DESC_BASE<"dextm", GPR64Opnd, uimm5,
                                           uimm5_plus33, MipsExt>;
 class DEXTU_MMR6_DESC : EXTBITS_DESC_BASE<"dextu", GPR64Opnd, uimm5_plus32,
                                           uimm5_plus1, MipsExt>;
 
+class DEXT64_32_MMR6_DESC : EXTBITS_DESC_BASE<"dext", GPR32Opnd, uimm5_plus32,
+                                          uimm5_plus1, null_frag, GPR64Opnd>;
+
 class DALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
                       Operand ImmOpnd> : MMR6Arch<instr_asm>, MipsR6Inst {
   dag OutOperandList = (outs GPROpnd:$rd);
   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
   list<dag> Pattern = [];
 }
 
let DecoderNamespace = "MicroMipsR6" in {
   def DSRL_MM64R6 : StdMMR6Rel, DSRL_MM64R6_ENC, DSRL_MM64R6_DESC,
                     ISA_MICROMIPS64R6;
   def DSRL32_MM64R6 : StdMMR6Rel, DSRL32_MM64R6_ENC, DSRL32_MM64R6_DESC,
                       ISA_MICROMIPS64R6;
   def DSRLV_MM64R6 : StdMMR6Rel, DSRLV_MM64R6_ENC, DSRLV_MM64R6_DESC,
                      ISA_MICROMIPS64R6;
 }
 
+let DecoderNamespace = "MicroMips64R6_32",
+    AdditionalPredicates = [InMicroMips] in
+def DEXT64_32_MM64R6 : StdMMR6Rel, DEXT64_32_MMR6_DESC, DEXT_MMR6_ENC,
+                       ISA_MICROMIPS64R6;
+
 let AdditionalPredicates = [InMicroMips] in
 defm : MaterializeImms<i64, ZERO_64, DADDIU_MM64R6, LUi64, ORi64>;
 
 //===----------------------------------------------------------------------===//
 //
 // Arbitrary patterns that map to one or more instructions
 //
 //===----------------------------------------------------------------------===//

 def : WrapperPat<tglobaltlsaddr, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
 
 // Carry pattern
 def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs),
               (DSUBU_MM64R6 GPR64:$lhs, GPR64:$rhs)>, ISA_MICROMIPS64R6;
 
 def : MipsPat<(atomic_load_64 addr:$a), (LD_MM64R6 addr:$a)>, ISA_MICROMIPS64R6;
 
+def : MipsPat<(i64 (zext GPR32:$src)), (DEXT64_32_MM64R6 GPR32:$src, 0, 32)>,
+              ISA_MICROMIPS64R6;
+
 //===----------------------------------------------------------------------===//
 //
 // Instruction aliases
 //
 //===----------------------------------------------------------------------===//
 
 def : MipsInstAlias<"dmtc0 $rt, $rd",
                     (DMTC0_MM64R6 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>;

lib/Target/Mips/Mips64InstrInfo.td

let AdditionalPredicates = [NotInMicroMips] in {
   def DINS : InsBase<"dins", GPR64Opnd, uimm6, uimm5_inssize_plus1, MipsIns>,
              EXT_FM<7>, ISA_MIPS64R2;
   def DINSU : InsBase<"dinsu", GPR64Opnd, uimm5_plus32, uimm5_inssize_plus1>,
               EXT_FM<6>, ISA_MIPS64R2;
   def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5, uimm5_inssize_plus1>,
               EXT_FM<5>, ISA_MIPS64R2;
 }
 
+// Pseudo instructions for performing sign/zero extensions
 let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
   def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt),
                      "dsll\t$rd, $rt, 32", [], II_DSLL>;
   def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt),
                     "sll\t$rd, $rt, 0", [], II_SLL>;
   def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt),
                     "sll\t$rd, $rt, 0", [], II_SLL>;
 }
 
+let DecoderNamespace = "Mips64_32",
+    AdditionalPredicates = [NotInMicroMips] in {
+  def DEXT64_32 : ExtBase<"dext", GPR32Opnd, uimm5_report_uimm6, uimm5_plus1,
+                     immZExt5, immZExt5Plus1, null_frag, GPR64Opnd>,
+                     EXT_FM<3>, ISA_MIPS64R2;
+}
+
 // We need the following pseudo instruction to avoid offset calculation for
 // long branches.  See the comment in file MipsLongBranch.cpp for detailed
 // explanation.
 
 // Expands to: daddiu $dst, $src, %PART($tgt - $baltgt)
 // where %PART may be %hi or %lo, depending on the relocation kind
 // that $tgt is annotated with.
 def LONG_BRANCH_DADDiu : PseudoSE<(outs GPR64Opnd:$dst),

 // For our case, this means that we can't issue an extract_subreg for nodes
 // such as (trunc:i32 (assertzext:i64 X, i32)), because the sign-bit of the
 // lower subreg would not be replicated into the upper half.
 def : MipsPat<(trunc (assertzext_lt_i32 GPR64:$src)),
               (EXTRACT_SUBREG GPR64:$src, sub_32)>;
 def : MipsPat<(i32 (trunc GPR64:$src)),
               (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>;
 
+// Solid mask optimizations
+defm : MaskPatternsExtIns<i64, GPR64Opnd, ZERO_64, DEXT, DINS>, ISA_MIPS64R2;
+
+// Mask with leading zeros and N trailing ones, where N has least 33 bits
+// to avoid potential ordering problems with the pattern above.
+def : MipsPat<(i64 (and GPR64:$src, immLO64Mask:$imm)),
+              (DINSU ZERO_64, (immLO64MaskSize $imm), (immLO64MaskPos $imm),
+                     GPR64:$src)>, ISA_MIPS64R2;
+
+// Generic fallback patterns.
+defm : MaskPatternsShift<i64, GPR64Opnd, DSLL, DSRL>, ISA_MIPS3;
+
 // variable shift instructions patterns
 def : MipsPat<(shl GPR64:$rt, (i32 (trunc GPR64:$rs))),
               (DSLLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
 def : MipsPat<(srl GPR64:$rt, (i32 (trunc GPR64:$rs))),
               (DSRLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
 def : MipsPat<(sra GPR64:$rt, (i32 (trunc GPR64:$rs))),
               (DSRAV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
 let AdditionalPredicates = [NotInMicroMips] in {
   def : MipsPat<(rotr GPR64:$rt, (i32 (trunc GPR64:$rs))),
                 (DROTRV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
 }
 
 // 32-to-64-bit extension
 def : MipsPat<(i64 (anyext GPR32:$src)),
               (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
+def : MipsPat<(i64 (zext GPR32:$src)), (DEXT64_32 GPR32:$src, 0, 32)>,
+               ISA_MIPS64R2;
 def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
 def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>;
 
 // Sign extend in register
 def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)),
               (SLL64_64 GPR64:$src)>;
 
 // bswap MipsPattern

lib/Target/Mips/MipsInstrInfo.td

def immZExt5Plus33 : PatLeaf<(imm), [{
   return isUInt<5>(N->getZExtValue() - 33);
 }]>;
 
 // True if (N + 1) fits in 16-bit field.
 def immSExt16Plus1 : PatLeaf<(imm), [{
   return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
 }]>;
 
+// Predicates and transformations for masking operations.
+//
+// The first 2 are for matching cases up 32 bits for ext/ins cases,
+// but are also used with dext/dins.
+//
+// A mask of N leading ones and trailing zeros, where N is >= 32 for
+// dins/ins matching.
+def immHIMask32 : PatLeaf<(imm), [{
+
+  if (N->getValueType(0) == MVT::i32) {
+    uint32_t Value = N->getZExtValue();
+    return countLeadingOnes(Value) + countTrailingZeros(Value) == 32;
+  }
+
+  uint64_t Value = N->getZExtValue();
+  return countLeadingOnes(Value) + countTrailingZeros(Value) == 64 &&
+         countLeadingOnes(Value) >= 32;
+}]>;
+
+// A mask with leading zeros and N trailing ones where 33 > N > 16,
+// for matching dext/ext cases. We ignore N <= 16 as that case can be directly
+// handled by andi.
+def immLOMask32 : PatLeaf<(imm), [{
+
+  if (N->getValueType(0) == MVT::i32) {
+    uint32_t Value = N->getZExtValue();
+    return countLeadingZeros(Value) + countTrailingOnes(Value) == 32 &&
+           countTrailingOnes(Value) > 16;
+  }
+
+  uint64_t Value = N->getZExtValue();
+  return countLeadingZeros(Value) + countTrailingOnes(Value) == 64 &&
+         countTrailingOnes(Value) < 33 && countTrailingOnes(Value) > 16;
+}]>;
+
+// A mask of leading ones and trailing zeros, for srl+sll matching.
+def immHIMask : PatLeaf<(imm), [{
+
+  if (N->getValueType(0) == MVT::i32) {
+    uint32_t Value = N->getZExtValue();
+    return countLeadingOnes(Value) + countTrailingZeros(Value) == 32;
+  }
+
+  uint64_t Value = N->getZExtValue();
+  return countLeadingOnes(Value) + countTrailingZeros(Value) == 64;
+}]>;
+
+// A mask with leading zeros and trailing ones, to match sll+srl.
+def immLOMask : PatLeaf<(imm), [{
+
+  if (N->getValueType(0) == MVT::i32) {
+    uint32_t Value = N->getZExtValue();
+    return countLeadingZeros(Value) + countTrailingOnes(Value) == 32;
+  }
+
+  uint64_t Value = N->getZExtValue();
+  return countLeadingZeros(Value) + countTrailingOnes(Value) == 64;
+}]>;
+
+// A mask of leading zeros and N trailing ones where N >= 32 to match dinsu.
+def immLO64Mask : PatLeaf<(imm), [{
+  unsigned TrailingOnes = countTrailingOnes(N->getZExtValue());
+  return (countLeadingZeros(N->getZExtValue()) + TrailingOnes == 64) &&
+          TrailingOnes >= 32;
+}]>;
+
+def immInvMaskSize : SDNodeXForm<imm, [{
+  return getImm(N, ((N->getValueType(0) == MVT::i32 ? 32 : 64)  -
+                    countPopulation((uint64_t)N->getZExtValue())));
+}]>;
+
+def immHIMaskSize : SDNodeXForm<imm, [{
+  return getImm(N, countTrailingZeros(N->getZExtValue()));
+}]>;
+
+def immLOMaskSize : SDNodeXForm<imm, [{
+  return getImm(N, countTrailingOnes(N->getZExtValue()));
+}]>;
+
+def immLO64MaskSize : SDNodeXForm<imm, [{
+  return getImm(N, countTrailingOnes(N->getZExtValue()) - 32);
+}]>;
+
+def immLO64MaskPos : SDNodeXForm<imm, [{
+  return getImm(N, 32 - (countTrailingOnes(N->getZExtValue()) - 32));
+}]>;
+
 // Mips Address Mode! SDNode frameindex could possibily be a match
 // since load and store instructions from stack used it.
 def addr :
   ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
 
 def addrRegImm :
   ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
 

 // Read Hardware
 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
   InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
          II_RDHWR, FrmR, "rdhwr">;
 
 // Ext and Ins
 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
               Operand SizeOpnd, PatFrag PosImm, PatFrag SizeImm,
-              SDPatternOperator Op = null_frag> :
-  InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size),
+              SDPatternOperator Op = null_frag, RegisterOperand RT = RO> :
+  InstSE<(outs RT:$rt), (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size),
          !strconcat(opstr, " $rt, $rs, $pos, $size"),
-         [(set RO:$rt, (Op RO:$rs, PosImm:$pos, SizeImm:$size))], II_EXT,
+         [(set RT:$rt, (Op RO:$rs, PosImm:$pos, SizeImm:$size))], II_EXT,
          FrmR, opstr>, ISA_MIPS32R2;
 
 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
               Operand SizeOpnd, SDPatternOperator Op = null_frag>:
   InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size, RO:$src),
          !strconcat(opstr, " $rt, $rs, $pos, $size"),
          [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
          II_INS, FrmR, opstr>, ISA_MIPS32R2 {

 //def : MipsPat<(MipsJmpLink GPR32:$dst),
 //              (JALR GPR32:$dst)>;
 
 // Tail call
 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
               (TAILCALL tglobaladdr:$dst)>;
 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
               (TAILCALL texternalsym:$dst)>;
+
+// Solid mask optimizations.
+multiclass MaskPatternsExtIns<ValueType VT, RegisterOperand RT,
+                              Register ZEROReg, Instruction EXTOP,
+                              Instruction INSOP> {
+
+// A mask with leading zeros and trailing ones, greater than 16 bits in size
+// (as andi can already do it).
+def : MipsPat<(VT (and RT:$src, immLOMask32:$imm)),
+                       (EXTOP RT:$src, 0, (immLOMaskSize $imm))>;
+
+// A mask with leading ones and trailing zeros, 32 bits in size.
+def : MipsPat<(VT (and RT:$src, immHIMask32:$imm)),
+                  (INSOP ZEROReg, 0, (immInvMaskSize $imm), RT:$src)>;
+}
+
+defm : MaskPatternsExtIns<i32, GPR32Opnd, ZERO, EXT, INS>, ISA_MIPS32R2;
+
+// Fallback for other cases and Mips64/Mips32
+// It relies on the encoder switching out DSLL x, x, 34 to DSLL32 x, x, 2.
+//
+// Some of the other cases can be done with dextm+dinsu but they require >2
+// instructions to achieve their goal.
+multiclass MaskPatternsShift<ValueType VT, RegisterOperand RT,
+                             Instruction SLLOP, Instruction SRLOP> {
+def : MipsPat<(VT (and RT:$src, immLOMask:$imm)),
+              (SRLOP (SLLOP RT:$src, (immInvMaskSize $imm)),
+                     (immInvMaskSize $imm))>;
+
+def : MipsPat<(VT (and RT:$src, immHIMask:$imm)),
+              (SLLOP (SRLOP RT:$src, (immInvMaskSize $imm)),
+                     (immInvMaskSize $imm))>;
+}
+
+defm : MaskPatternsShift<i32, GPR32Opnd, SLL, SRL>;
+
 // hi/lo relocs
 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
 

lib/Target/Mips/MipsSEISelDAGToDAG.cpp

 #include "llvm/CodeGen/SelectionDAGNodes.h"
 #include "llvm/IR/CFG.h"
 #include "llvm/IR/GlobalValue.h"
 #include "llvm/IR/Instructions.h"
 #include "llvm/IR/Intrinsics.h"
 #include "llvm/IR/Type.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetMachine.h"
 using namespace llvm;
 
 #define DEBUG_TYPE "mips-isel"
 
 bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
   Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());

test/CodeGen/Mips/cconv/arguments-varargs.ll

 ; Store [[VA]]
 ; O32-DAG:       sw [[VA]], 0([[SP]])
 
 ; ALL: teqi $zero, 1
 
 ; Increment [[VA]] (and realign pointer for O32)
 ; O32:           lw [[VA:\$[0-9]+]], 0([[SP]])
 ; O32-DAG:       addiu [[VA_TMP0:\$[0-9]+]], [[VA]], 7
-; O32-DAG:       addiu [[VA_TMP1:\$[0-9]+]], $zero, -8
-; O32-DAG:       and   [[VA_TMP2:\$[0-9]+]], [[VA_TMP0]], [[VA_TMP1]]
+; O32-DAG:       srl   [[VA_TMP1:\$[0-9]+]], [[VA_TMP0]], 3
+; O32-DAG:       sll   [[VA_TMP2:\$[0-9]+]], [[VA_TMP1]], 3
 ; O32-DAG:       ori   [[VA2:\$[0-9]+]], [[VA_TMP2]], 4
 ; O32-DAG:       sw [[VA2]], 0([[SP]])
 
 ; N32-DAG:       lw [[VA:\$[0-9]+]], 0([[SP]])
 ; N32-DAG:       addiu [[VA2:\$[0-9]+]], [[VA]], 8
 ; N32-DAG:       sw [[VA2]], 0([[SP]])
 
 ; N64-DAG:       ld [[VA:\$[0-9]+]], 0([[SP]])

 ; NEW-DAG:       sd [[ARG1]], 8([[GV]])
 
 ; ALL: teqi $zero, 2
 
 ; Increment [[VA]] again.
 ; FIXME: We're still aligned from the last one but CodeGen doesn't spot that.
 ; O32:           lw [[VA:\$[0-9]+]], 0([[SP]])
 ; O32-DAG:       addiu [[VA_TMP0:\$[0-9]+]], [[VA]], 7
-; O32-DAG:       and   [[VA_TMP2:\$[0-9]+]], [[VA_TMP0]], [[VA_TMP1]]
+; O32-DAG:       srl   [[VA_TMP1:\$[0-9]+]], [[VA_TMP0]], 3
+; O32-DAG:       sll   [[VA_TMP2:\$[0-9]+]], [[VA_TMP1]], 3
 ; O32-DAG:       ori   [[VA2:\$[0-9]+]], [[VA_TMP2]], 4
 ; O32-DAG:       sw [[VA2]], 0([[SP]])
 
 ; N32-DAG:       lw [[VA2:\$[0-9]+]], 0([[SP]])
 ; N32-DAG:       addiu [[VA3:\$[0-9]+]], [[VA2]], 8
 ; N32-DAG:       sw [[VA3]], 0([[SP]])
 
 ; N64-DAG:       ld [[VA2:\$[0-9]+]], 0([[SP]])

 ; Store [[VA]]
 ; O32-DAG:       sw [[VA]], 0([[SP]])
 
 ; ALL: teqi $zero, 1
 
 ; Increment [[VA]] (and realign pointer for O32)
 ; O32:           lw [[VA:\$[0-9]+]], 0([[SP]])
 ; O32-DAG:       addiu [[VA_TMP0:\$[0-9]+]], [[VA]], 7
-; O32-DAG:       addiu [[VA_TMP1:\$[0-9]+]], $zero, -8
-; O32-DAG:       and   [[VA_TMP2:\$[0-9]+]], [[VA_TMP0]], [[VA_TMP1]]
+; O32-DAG:       srl   [[VA_TMP1:\$[0-9]+]], [[VA_TMP0]], 3
+; O32-DAG:       sll   [[VA_TMP2:\$[0-9]+]], [[VA_TMP1]], 3
 ; O32-DAG:       ori   [[VA2:\$[0-9]+]], [[VA_TMP2]], 4
 ; O32-DAG:       sw [[VA2]], 0([[SP]])
 
 ; N32-DAG:       lw [[VA:\$[0-9]+]], 0([[SP]])
 ; N32-DAG:       addiu [[VA2:\$[0-9]+]], [[VA]], 8
 ; N32-DAG:       sw [[VA2]], 0([[SP]])
 
 ; N64-DAG:       ld [[VA:\$[0-9]+]], 0([[SP]])

 ; NEW-DAG:       sd [[ARG1]], 8([[GV]])
 
 ; ALL: teqi $zero, 2
 
 ; Increment [[VA]] again.
 ; FIXME: We're still aligned from the last one but CodeGen doesn't spot that.
 ; O32:           lw [[VA:\$[0-9]+]], 0([[SP]])
 ; O32-DAG:       addiu [[VA_TMP0:\$[0-9]+]], [[VA]], 7
-; O32-DAG:       and   [[VA_TMP2:\$[0-9]+]], [[VA_TMP0]], [[VA_TMP1]]
+; O32-DAG:       srl   [[VA_TMP1:\$[0-9]+]], [[VA_TMP0]], 3
+; O32-DAG:       sll   [[VA_TMP2:\$[0-9]+]], [[VA_TMP1]], 3
 ; O32-DAG:       ori   [[VA2:\$[0-9]+]], [[VA_TMP2]], 4
 ; O32-DAG:       sw [[VA2]], 0([[SP]])
 
 ; N32-DAG:       lw [[VA2:\$[0-9]+]], 0([[SP]])
 ; N32-DAG:       addiu [[VA3:\$[0-9]+]], [[VA2]], 8
 ; N32-DAG:       sw [[VA3]], 0([[SP]])
 
 ; N64-DAG:       ld [[VA2:\$[0-9]+]], 0([[SP]])

 ; Store [[VA]]
 ; O32-DAG:       sw [[VA]], 0([[SP]])
 
 ; ALL: teqi $zero, 1
 
 ; Increment [[VA]] (and realign pointer for O32)
 ; O32:           lw [[VA:\$[0-9]+]], 0([[SP]])
 ; O32-DAG:       addiu [[VA_TMP0:\$[0-9]+]], [[VA]], 7
-; O32-DAG:       addiu [[VA_TMP1:\$[0-9]+]], $zero, -8
-; O32-DAG:       and   [[VA_TMP2:\$[0-9]+]], [[VA_TMP0]], [[VA_TMP1]]
+; O32-DAG:       srl   [[VA_TMP1:\$[0-9]+]], [[VA_TMP0]], 3
+; O32-DAG:       sll   [[VA_TMP2:\$[0-9]+]], [[VA_TMP1]], 3
 ; O32-DAG:       ori   [[VA2:\$[0-9]+]], [[VA_TMP2]], 4
 ; O32-DAG:       sw [[VA2]], 0([[SP]])
 
 ; N32-DAG:       lw [[VA:\$[0-9]+]], 0([[SP]])
 ; N32-DAG:       addiu [[VA2:\$[0-9]+]], [[VA]], 8
 ; N32-DAG:       sw [[VA2]], 0([[SP]])
 
 ; N64-DAG:       ld [[VA:\$[0-9]+]], 0([[SP]])

 ; NEW-DAG:       sd [[ARG1]], 8([[GV]])
 
 ; ALL: teqi $zero, 2
 
 ; Increment [[VA]] again.
 ; FIXME: We're still aligned from the last one but CodeGen doesn't spot that.
 ; O32:           lw [[VA:\$[0-9]+]], 0([[SP]])
 ; O32-DAG:       addiu [[VA_TMP0:\$[0-9]+]], [[VA]], 7
-; O32-DAG:       and   [[VA_TMP2:\$[0-9]+]], [[VA_TMP0]], [[VA_TMP1]]
+; O32-DAG:       srl   [[VA_TMP1:\$[0-9]+]], [[VA_TMP0]], 3
+; O32-DAG:       sll   [[VA_TMP2:\$[0-9]+]], [[VA_TMP1]], 3
 ; O32-DAG:       ori   [[VA2:\$[0-9]+]], [[VA_TMP2]], 4
 ; O32-DAG:       sw [[VA2]], 0([[SP]])
 
 ; N32-DAG:       lw [[VA2:\$[0-9]+]], 0([[SP]])
 ; N32-DAG:       addiu [[VA3:\$[0-9]+]], [[VA2]], 8
 ; N32-DAG:       sw [[VA3]], 0([[SP]])
 
 ; N64-DAG:       ld [[VA2:\$[0-9]+]], 0([[SP]])

test/CodeGen/Mips/fcopysign-f32-f64.ll

 ; RUN: llc  < %s -march=mips64el -mcpu=mips4 -target-abi=n64 | \
 ; RUN:    FileCheck %s -check-prefixes=ALL,64
 ; RUN: llc  < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | \
 ; RUN:    FileCheck %s -check-prefixes=ALL,64
 ; RUN: llc  < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | \
 ; RUN:    FileCheck %s -check-prefixes=ALL,64R2
 
 declare double @copysign(double, double) nounwind readnone
 
 declare float @copysignf(float, float) nounwind readnone
 
 define float @func2(float %d, double %f) nounwind readnone {
 entry:
 ; ALL-LABEL: func2:
 
-; 64-DAG: lui  $[[T0:[0-9]+]], 32767
-; 64-DAG: ori  $[[MSK0:[0-9]+]], $[[T0]], 65535
-; 64-DAG: and  $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
+; 64-DAG: sll  $[[T0:[0-9]+]], ${{[0-9]+}}, 1
+; 64-DAG: srl  $[[T1:[0-9]+]], $[[T0]], 1
 ; 64-DAG: dsrl $[[DSRL:[0-9]+]], ${{[0-9]+}}, 63
 ; 64-DAG: sll  $[[SLL0:[0-9]+]], $[[DSRL]], 0
 ; 64-DAG: sll  $[[SLL1:[0-9]+]], $[[SLL0]], 31
-; 64:     or   $[[OR:[0-9]+]], $[[AND0]], $[[SLL1]]
+; 64:     or   $[[OR:[0-9]+]], $[[T1]], $[[SLL1]]
 ; 64:     mtc1 $[[OR]], $f0
 
 ; 64R2: dextu ${{[0-9]+}}, ${{[0-9]+}}, 63, 1
 ; 64R2: ins  $[[INS:[0-9]+]], ${{[0-9]+}}, 31, 1
 ; 64R2: mtc1 $[[INS]], $f0
 
   %add = fadd float %d, 1.000000e+00
   %conv = fptrunc double %f to float
   %call = tail call float @copysignf(float %add, float %conv) nounwind readnone
   ret float %call
 }
 
 define double @func3(double %d, float %f) nounwind readnone {
 entry:
 ; ALL-LABEL: func3:
 
 ; 64-DAG: mfc1    $[[MFC:[0-9]+]], $f13
 ; 64-DAG: srl     $[[SRL:[0-9]+]], $[[MFC:[0-9]+]], 31
 ; 64:     dsll    $[[DSLL:[0-9]+]], $[[SRL]], 63
-; 64-DAG: daddiu  $[[R1:[0-9]+]], $zero, 1
-; 64-DAG: dsll    $[[R2:[0-9]+]], $[[R1]], 63
-; 64-DAG: daddiu  $[[R3:[0-9]+]], $[[R2]], -1
-; 64-DAG: dmfc1   $[[R0:[0-9]+]], ${{.*}}
-; 64:     and     $[[AND0:[0-9]+]], $[[R0]], $[[R3]]
-; 64:     or      $[[OR:[0-9]+]], $[[AND0]], $[[DSLL]]
+; 64:     dmfc1   $[[R0:[0-9]+]], $f0
+; 64:     dsll    $[[R1:[0-9]+]], $[[R0]], 1
+; 64:     dsrl    $[[R2:[0-9]+]], $[[R1]], 1
+; 64:     or      $[[OR:[0-9]+]], $[[R2]], $[[DSLL]]
 ; 64:     dmtc1   $[[OR]], $f0
 
 ; 64R2: ext   ${{[0-9]+}}, ${{[0-9]+}}, 31, 1
 ; 64R2: dins  $[[INS:[0-9]+]], ${{[0-9]+}}, 63, 1
 ; 64R2: dmtc1 $[[INS]], $f0
 
   %add = fadd double %d, 1.000000e+00
   %conv = fpext float %f to double
   %call = tail call double @copysign(double %add, double %conv) nounwind readnone
   ret double %call
 }

test/CodeGen/Mips/fcopysign.ll

 ; RUN: llc  < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=32
 ; RUN: llc  < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=32R2
 ; RUN: llc  < %s -march=mips64el -mcpu=mips4 -target-abi=n64 | FileCheck %s -check-prefix=64
 ; RUN: llc  < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s -check-prefix=64
 ; RUN: llc  < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s -check-prefix=64R2
 
 define double @func0(double %d0, double %d1) nounwind readnone {
 entry:
-;
-; 32: lui  $[[MSK1:[0-9]+]], 32768
-; 32: and  $[[AND1:[0-9]+]], ${{[0-9]+}}, $[[MSK1]]
-; 32: lui  $[[T0:[0-9]+]], 32767
-; 32: ori  $[[MSK0:[0-9]+]], $[[T0]], 65535
-; 32: and  $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
-; 32: or   $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
-; 32: mtc1 $[[OR]], $f1
+
+; 32: mfc1 $[[MFC:[0-9]+]], $f15
+; 32: srl  $[[R0:[0-9]+]], $[[MFC]], 31
+; 32: sll  $[[R1:[0-9]+]], $[[R0]], 31
+; 32: mfc1 $[[R2:[0-9]+]], $f13
+; 32: sll  $[[R3:[0-9]+]], $[[R2]], 1
+; 32: srl  $[[R4:[0-9]+]], $[[R3]], 1
+; 32: or   $[[R5:[0-9]+]], $[[R4]], $[[R1]]
+; 32: mtc1 $[[R5]], $f1
 
 ; 32R2: ext  $[[EXT:[0-9]+]], ${{[0-9]+}}, 31, 1
 ; 32R2: ins  $[[INS:[0-9]+]], $[[EXT]], 31, 1
 ; 32R2: mthc1 $[[INS]], $f0
 
-; 64: daddiu $[[T0:[0-9]+]], $zero, 1
-; 64: dsll   $[[MSK1:[0-9]+]], $[[T0]], 63
-; 64: and    $[[AND1:[0-9]+]], ${{[0-9]+}}, $[[MSK1]]
-; 64: daddiu $[[MSK0:[0-9]+]], $[[MSK1]], -1
-; 64: and    $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
-; 64: or     $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
+; 64: dmfc1  $[[MFC:[0-9]+]], $f13
+; 64: dsrl   $[[MSK1:[0-9]+]], $[[MSK1]], 63
+; 64: dsll   $[[MSK1]], $[[MSK1]], 63
+; 64: dmfc1  $[[R2:[0-9]+]], $f12
+; 64: dsll   $[[R3:[0-9]+]], $[[R2]], 1
+; 64: dsrl   $[[R4:[0-9]+]], $[[R3]], 1
+; 64: or     $[[OR:[0-9]+]], $[[R4]], $[[MSK1]]
 ; 64: dmtc1  $[[OR]], $f0
 
 ; 64R2: dextu  $[[EXT:[0-9]+]], ${{[0-9]+}}, 63, 1
 ; 64R2: dins  $[[INS:[0-9]+]], $[[EXT]], 63, 1
 ; 64R2: dmtc1 $[[INS]], $f0
 
   %call = tail call double @copysign(double %d0, double %d1) nounwind readnone
   ret double %call
 }
 
 declare double @copysign(double, double) nounwind readnone
 
 define float @func1(float %f0, float %f1) nounwind readnone {
 entry:
 
-; 32: lui  $[[MSK1:[0-9]+]], 32768
-; 32: and  $[[AND1:[0-9]+]], ${{[0-9]+}}, $[[MSK1]]
-; 32: lui  $[[T0:[0-9]+]], 32767
-; 32: ori  $[[MSK0:[0-9]+]], $[[T0]], 65535
-; 32: and  $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
-; 32: or   $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
-; 32: mtc1 $[[OR]], $f0
+; 32: mfc1 $[[MFC:[0-9]+]], $f14
+; 32: srl  $[[R0:[0-9]+]], $[[MFC]], 31
+; 32: sll  $[[R1:[0-9]+]], $[[R0]], 31
+; 32: mfc1 $[[R2:[0-9]+]], $f12
+; 32: sll  $[[R3:[0-9]+]], $[[R2]], 1
+; 32: srl  $[[R4:[0-9]+]], $[[R3]], 1
+; 32: or   $[[R5:[0-9]+]], $[[R4]], $[[R1]]
+; 32: mtc1 $[[R5]], $f0
 
 ; 32R2: ext  $[[EXT:[0-9]+]], ${{[0-9]+}}, 31, 1
 ; 32R2: ins  $[[INS:[0-9]+]], $[[EXT]], 31, 1
 ; 32R2: mtc1 $[[INS]], $f0
 
+; 64: mfc1 $[[MFC:[0-9]+]], $f13
+; 64: srl  $[[R0:[0-9]+]], $[[MFC]], 31
+; 64: sll  $[[R1:[0-9]+]], $[[R0]], 31
+; 64: mfc1 $[[R2:[0-9]+]], $f12
+; 64: sll  $[[R3:[0-9]+]], $[[R2]], 1
+; 64: srl  $[[R4:[0-9]+]], $[[R3]], 1
+; 64: or   $[[R5:[0-9]+]], $[[R4]], $[[R1]]
+; 64: mtc1 $[[R5]], $f0
+
   %call = tail call float @copysignf(float %f0, float %f1) nounwind readnone
   ret float %call
 }
 
 declare float @copysignf(float, float) nounwind readnone
 

test/CodeGen/Mips/llvm-ir/and-opts.ll

+; RUN: llc -march=mips < %s | FileCheck %s -check-prefixes=ALL,MIPS32
+; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=ALL,MIPS32R2
+; RUN: llc -march=mips64 < %s | FileCheck %s -check-prefixes=ALL,MIPS64
+; RUN: llc -march=mips64 -mcpu=mips64r2 < %s | FileCheck %s -check-prefixes=ALL,MIPS64R2
+
+; and masking optimizations, also covers zext.
+; Test that masks of the form 0...1 which don't have holes in them are
+; optimized to shifts, (d)ext, ins, dinsu.
+
+define i64 @f(i64 zeroext %a) {
+entry:
+; ALL-LABEL: f:
+; ALL:      andi $[[RES:[0-9]+]], $[[ARG:[0-9]]], 65535
+  %and = and i64 %a, 65535
+  ret i64 %and
+}
+
+define i64 @f2(i64 zeroext %a) {
+entry:
+; ALL-LABEL: f2:
+; MIPS:     sll  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 12
+; MIPS:     srl  $[[RES2:[0-9]+]], $[[RES]], 12
+; MIPS32R2: ext  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 0, 20
+; MIPS64:   dsll $[[RES:[0-9]+]], $[[ARG:[0-9]]], 44
+; MIPS64:   dsrl $[[RES2:[0-9]+]], $[[RES]], 44
+; MIPS64R2: dext $[[RES:[0-9]+]], $[[ARG:[0-9]]], 0, 20
+  %and = and i64 %a, 1048575
+  ret i64 %and
+}
+
+define i64 @f3(i64 zeroext %a) {
+entry:
+; ALL-LABEL: f3:
+; MIPS:     sll  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 8
+; MIPS:     srl  $[[RES2:[0-9]+]], $[[RES]], 8
+; MIPS32R2: ext  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 0, 24
+; MIPS64:   dsll $[[RES:[0-9]+]], $[[ARG:[0-9]]], 40
+; MIPS64:   dsrl $[[RES2:[0-9]+]], $[[RES]], 40
+; MIPS64R2: dext $[[RES:[0-9]+]], $[[ARG:[0-9]]], 0, 24
+  %and = and i64 %a, 16777215
+  ret i64 %and
+}
+
+define i64 @f4(i64 zeroext %a) {
+entry:
+; ALL-LABEL: f4:
+; MIPS:     sll  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 4
+; MIPS:     srl  $[[RES2:[0-9]+]], $[[RES]], 4
+; MIPS32R2: ext  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 0, 28
+; MIPS64:   dsll $[[RES:[0-9]+]], $[[ARG:[0-9]]], 36
+; MIPS64:   dsrl $[[RES2:[0-9]+]], $[[RES]], 36
+; MIPS64R2: dext $[[RES:[0-9]+]], $[[ARG:[0-9]]], 0, 28
+  %and = and i64 %a, 268435455
+  ret i64 %and
+}
+
+; This case covers %a = zext i32 %b to i64
+
+define i64 @f5(i64 zeroext %a) {
+entry:
+; ALL-LABEL: f5:
+; MIPS-DAG:     addiu $2, $zero, 0
+; MIPS-DAG:     move  $3, $5
+; MIPS32R2-DAG: addiu $2, $zero, 0
+; MIPS32R2-DAG: move  $3, $5
+; MIPS64:       dsll  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 32
+; MIPS64:       dsrl  $[[RES2:[0-9]+]], $[[RES]], 32
+; MIPS64R2:     dext  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 0, 32
+  %and = and i64 %a, 4294967295
+  ret i64 %and
+}
+
+define i64 @f6(i64 zeroext %a) {
+entry:
+; ALL-LABEL: f6:
+; MIPS-DAG:     andi  $2, $[[ARG:[0-9]]], 15
+; MIPS-DAG:     move  $3, $5
+; MIPS32R2-DAG: andi  $2, $[[ARG:[0-9]]], 15
+; MIPS32R2-DAG: move  $3, $5
+; MIPS64:       dsll  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 28
+; MIPS64:       dsrl  $[[RES2:[0-9]+]], $[[RES]], 28
+; MIPS64R2:     dinsu $[[ARG:[0-9]]], $zero, 36, 28
+  %and = and i64 %a, 68719476735
+  ret i64 %and
+}
+
+define i64 @f7(i64 zeroext %a) {
+entry:
+; ALL-LABEL: f7:
+; MIPS-DAG:     andi  $2, $[[ARG:[0-9]]], 255
+; MIPS-DAG:     move  $3, $5
+; MIPS32R2-DAG: andi  $2, $[[ARG:[0-9]]], 255
+; MIPS32R2-DAG: move  $3, $5
+; MIPS64:       dsll  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 24
+; MIPS64:       dsrl  $[[RES2:[0-9]+]], $[[RES]], 24
+; MIPS64R2:     dinsu $[[ARG:[0-9]]], $zero, 40, 24
+  %and = and i64 %a, 1099511627775
+  ret i64 %and
+}
+
+define i64 @f8(i64 zeroext %a) {
+entry:
+; ALL-LABEL: f8:
+; MIPS-DAG:     andi  $2, $[[ARG:[0-9]]], 4095
+; MIPS-DAG:     move  $3, $5
+; MIPS32R2-DAG: andi  $2, $[[ARG:[0-9]]], 4095
+; MIPS32R2-DAG: move  $3, $5
+; MIPS64:       dsll  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 20
+; MIPS64:       dsrl  $[[RES2:[0-9]+]], $[[RES]], 20
+; MIPS64R2:     dinsu $[[ARG:[0-9]]], $zero, 44, 20
+  %and = and i64 %a, 17592186044415
+  ret i64 %and
+}
+
+define i64 @f9(i64 zeroext %a) {
+entry:
+; ALL-LABEL: f9:
+; MIPS-DAG:     andi  $2, $[[ARG:[0-9]]], 65535
+; MIPS-DAG:     move  $3, $5
+; MIPS32R2-DAG: andi  $2, $[[ARG:[0-9]]], 65535
+; MIPS32R2-DAG: move  $3, $5
+; MIPS64:       dsll  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 16
+; MIPS64:       dsrl  $[[RES2:[0-9]+]], $[[RES]], 16
+; MIPS64R2:     dinsu $[[ARG:[0-9]]], $zero, 48, 16
+  %and = and i64 %a, 281474976710655
+  ret i64 %and
+}
+
+define i64 @f10(i64 zeroext %a) {
+entry:
+; ALL-LABEL: f10:
+; MIPS:     sll   $[[RES:[0-9]+]], $[[ARG:[0-9]]], 12
+; MIPS:     srl   $[[RES2:[0-9]+]], $[[RES]], 12
+; MIPS32R2: ext   $[[RES:[0-9]+]], $[[ARG:[0-9]]], 0,
+; MIPS64:   dsll  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 12
+; MIPS64:   dsrl  $[[RES2:[0-9]+]], $[[RES]], 12
+; MIPS64R2: dinsu $[[ARG:[0-9]]], $zero, 52, 12
+  %and = and i64 %a, 4503599627370495
+  ret i64 %and
+}
+
+define i64 @f11(i64 zeroext %a) {
+entry:
+; ALL-LABEL: f11:
+; MIPS:     sll   $[[RES:[0-9]+]], $[[ARG:[0-9]]], 8
+; MIPS:     srl   $[[RES2:[0-9]+]], $[[RES]], 8
+; MIPS32R2: ext   $[[RES:[0-9]+]], $[[ARG:[0-9]]], 0,
+; MIPS64:   dsll  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 8
+; MIPS64:   dsrl  $[[RES2:[0-9]+]], $[[RES]], 8
+; MIPS64R2: dinsu $[[ARG:[0-9]]], $zero, 56, 8
+  %and = and i64 %a, 72057594037927935
+  ret i64 %and
+}
+
+define i64 @f12(i64 zeroext %a) {
+entry:
+; ALL-LABEL: f12:
+; MIPS:     sll   $[[RES:[0-9]+]], $[[ARG:[0-9]]], 4
+; MIPS:     srl   $[[RES2:[0-9]+]], $[[RES]], 4
+; MIPS32R2: ext   $[[RES:[0-9]+]], $[[ARG:[0-9]]], 0,
+; MIPS64:   dsll  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 4
+; MIPS64:   dsrl  $[[RES2:[0-9]+]], $[[RES]], 4
+; MIPS64R2: dinsu $[[ARG:[0-9]]], $zero, 60, 4
+  %and = and i64 %a, 1152921504606846975
+  ret i64 %and
+}
+
+define i64 @g(i64 zeroext %a) {
+entry:
+; ALL-LABEL: g:
+; MIPS:     srl  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 16
+; MIPS:     sll  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 16
+; MIPS32R2: ins  $[[ARG:[0-9]]], $zero, 0, 16
+; MIPS64:   dsrl $[[RES:[0-9]+]], $[[ARG:[0-9]]], 48
+; MIPS64:   dsll $[[RES:[0-9]+]], $[[ARG:[0-9]]], 48
+; MIPS64R2: dsrl $[[RES:[0-9]+]], $[[ARG:[0-9]]], 48
+; MIPS64R2: dsll $[[RES:[0-9]+]], $[[ARG:[0-9]]], 48
+  %and = and i64 %a, -281474976710656
+  ret i64 %and
+}
+
+define i64 @g2(i64 zeroext %a) {
+entry:
+; ALL-LABEL: g2:
+; MIPS:     srl  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 12
+; MIPS:     sll  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 12
+; MIPS32R2: ins  $[[ARG:[0-9]]], $zero, 0, 12
+; MIPS64:   dsrl $[[RES:[0-9]+]], $[[ARG:[0-9]]], 44
+; MIPS64:   dsll $[[RES:[0-9]+]], $[[ARG:[0-9]]], 44
+; MIPS64R2: dsrl $[[RES:[0-9]+]], $[[ARG:[0-9]]], 44
+; MIPS64R2: dsll $[[RES:[0-9]+]], $[[ARG:[0-9]]], 44
+  %and = and i64 %a, -17592186044416
+  ret i64 %and
+}
+
+define i64 @g3(i64 zeroext %a) {
+entry:
+; ALL-LABEL: g3:
+; MIPS:     srl  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 8
+; MIPS:     sll  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 8
+; MIPS32R2: ins  $[[ARG:[0-9]]], $zero, 0, 8
+; MIPS64:   dsrl $[[RES:[0-9]+]], $[[ARG:[0-9]]], 40
+; MIPS64:   dsll $[[RES:[0-9]+]], $[[ARG:[0-9]]], 40
+; MIPS64R2: dsrl $[[RES:[0-9]+]], $[[ARG:[0-9]]], 40
+; MIPS64R2: dsll $[[RES:[0-9]+]], $[[ARG:[0-9]]], 40
+  %and = and i64 %a, -1099511627776
+  ret i64 %and
+}
+
+define i64 @g4(i64 zeroext %a) {
+entry:
+; ALL-LABEL: g4:
+; MIPS:     srl  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 4
+; MIPS:     sll  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 4
+; MIPS32R2: addiu $[[RES:[0-9]+]], $zero, 0
+; MIPS64:   dsrl  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 36
+; MIPS64:   dsll  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 36
+; MIPS64R2: dsrl  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 36
+; MIPS64R2: dsll  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 36
+  %and = and i64 %a, -68719476736
+  ret i64 %and
+}
+
+define i64 @g5(i64 zeroext %a) {
+entry:
+; ALL-LABEL: g5:
+; MIPS:     srl   $[[RES:[0-9]+]], $[[ARG:[0-9]]], 28
+; MIPS:     sll   $[[RES:[0-9]+]], $[[ARG:[0-9]]], 28
+; MIPS32R2: addiu $[[RES:[0-9]+]], $zero, 0
+; MIPS64:   dsrl  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 32
+; MIPS64:   dsll  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 32
+; MIPS64R2: dins  $[[ARG:[0-9]]], $zero, 0, 32
+  %and = and i64 %a, -4294967296
+  ret i64 %and
+}
+
+define i64 @g6(i64 zeroext %a) {
+entry:
+; ALL-LABEL: g6:
+; MIPS:     srl  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 24
+; MIPS:     sll  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 24
+; MIPS32R2: ins  $[[ARG:[0-9]]], $zero, 0, 28
+; MIPS64:   dsrl $[[RES:[0-9]+]], $[[ARG:[0-9]]], 28
+; MIPS64:   dsll $[[RES:[0-9]+]], $[[ARG:[0-9]]], 28
+; MIPS64R2: dins $[[ARG:[0-9]]], $zero, 0, 28
+  %and = and i64 %a, -268435456
+  ret i64 %and
+}
+
+define i64 @g7(i64 zeroext %a) {
+entry:
+; ALL-LABEL: g7:
+; MIPS:     srl  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 24
+; MIPS:     sll  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 24
+; MIPS32R2: ins  $[[ARG:[0-9]]], $zero, 0, 24
+; MIPS64:   dsrl $[[RES:[0-9]+]], $[[ARG:[0-9]]], 24
+; MIPS64:   dsll $[[RES:[0-9]+]], $[[ARG:[0-9]]], 24
+; MIPS64R2: dins $[[ARG:[0-9]]], $zero, 0, 24
+  %and = and i64 %a, -16777216
+  ret i64 %and
+}
+
+define i64 @g8(i64 zeroext %a) {
+entry:
+; ALL-LABEL: g8:
+; MIPS:     srl  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 20
+; MIPS:     sll  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 20
+; MIPS32R2: ins  $[[ARG:[0-9]]], $zero, 0, 20
+; MIPS64:   dsrl $[[RES:[0-9]+]], $[[ARG:[0-9]]], 20
+; MIPS64:   dsll $[[RES:[0-9]+]], $[[ARG:[0-9]]], 20
+; MIPS64R2: dins $[[ARG:[0-9]]], $zero, 0, 20
+  %and = and i64 %a, -1048576
+  ret i64 %and
+}
+
+define i64 @g9(i64 zeroext %a) {
+entry:
+; ALL-LABEL: g9:
+; MIPS:     srl  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 16
+; MIPS:     sll  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 16
+; MIPS32R2: ins  $[[ARG:[0-9]]], $zero, 0, 16
+; MIPS64:   dsrl $[[RES:[0-9]+]], $[[ARG:[0-9]]], 16
+; MIPS64:   dsll $[[RES:[0-9]+]], $[[ARG:[0-9]]], 16
+; MIPS64R2: dins $[[ARG:[0-9]]], $zero, 0, 16
+  %and = and i64 %a, -65536
+  ret i64 %and
+}
+
+define i64 @g10(i64 zeroext %a) {
+entry:
+; ALL-LABEL: g10:
+; MIPS:     srl  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 12
+; MIPS:     sll  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 12
+; MIPS32R2: ins  $[[ARG:[0-9]]], $zero, 0, 12
+; MIPS64:   dsrl $[[RES:[0-9]+]], $[[ARG:[0-9]]], 12
+; MIPS64:   dsll $[[RES:[0-9]+]], $[[ARG:[0-9]]], 12
+; MIPS64R2: dins $[[ARG:[0-9]]], $zero, 0, 12
+  %and = and i64 %a, -4096
+  ret i64 %and
+}
+
+define i64 @g11(i64 zeroext %a) {
+entry:
+; ALL-LABEL: g11:
+; MIPS:     srl  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 8
+; MIPS:     sll  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 8
+; MIPS32R2: ins  $[[ARG:[0-9]]], $zero, 0, 8
+; MIPS64:   dsrl $[[RES:[0-9]+]], $[[ARG:[0-9]]], 8
+; MIPS64:   dsll $[[RES:[0-9]+]], $[[ARG:[0-9]]], 8
+; MIPS64R2: dins $[[ARG:[0-9]]], $zero, 0, 8
+  %and = and i64 %a, -256
+  ret i64 %and
+}
+
+define i64 @g12(i64 zeroext %a) {
+entry:
+; ALL-LABEL: g12:
+; MIPS:     srl  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 4
+; MIPS:     sll  $[[RES:[0-9]+]], $[[ARG:[0-9]]], 4
+; MIPS32R2: ins  $[[ARG:[0-9]]], $zero, 0, 4
+; MIPS64:   dsrl $[[RES:[0-9]+]], $[[ARG:[0-9]]], 4
+; MIPS64:   dsll $[[RES:[0-9]+]], $[[ARG:[0-9]]], 4
+; MIPS64R2: dins $[[ARG:[0-9]]], $zero, 0, 4
+  %and = and i64 %a, -16
+  ret i64 %and
+}

test/CodeGen/Mips/llvm-ir/and.ll

 ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
-; RUN:    -check-prefixes=ALL,GP32
+; RUN:    -check-prefixes=ALL,GP32,PREMIPSR2
 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
-; RUN:    -check-prefixes=ALL,GP32
+; RUN:    -check-prefixes=ALL,GP32,PREMIPSR2
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
-; RUN:    -check-prefixes=ALL,GP32
+; RUN:    -check-prefixes=ALL,GP32,MIPSR2
 ; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
-; RUN:    -check-prefixes=ALL,GP32
+; RUN:    -check-prefixes=ALL,GP32,MIPSR2
 ; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
-; RUN:    -check-prefixes=ALL,GP32
+; RUN:    -check-prefixes=ALL,GP32,MIPSR2
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
-; RUN:    -check-prefixes=ALL,GP32
+; RUN:    -check-prefixes=ALL,GP32,MIPSR2
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
-; RUN:    -check-prefixes=ALL,GP64
+; RUN:    -check-prefixes=ALL,GP64,PREMIPSR2
 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
-; RUN:    -check-prefixes=ALL,GP64
+; RUN:    -check-prefixes=ALL,GP64,PREMIPSR2
 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
-; RUN:    -check-prefixes=ALL,GP64
+; RUN:    -check-prefixes=ALL,GP64,PREMIPSR2
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
-; RUN:    -check-prefixes=ALL,GP64
+; RUN:    -check-prefixes=ALL,GP64,MIPSR2
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
-; RUN:    -check-prefixes=ALL,GP64
+; RUN:    -check-prefixes=ALL,GP64,MIPSR2
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
-; RUN:    -check-prefixes=ALL,GP64
+; RUN:    -check-prefixes=ALL,GP64,MIPSR2
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
-; RUN:    -check-prefixes=ALL,GP64
+; RUN:    -check-prefixes=ALL,GP64,MIPSR2
 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MM,MM32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MM,MM32
 ; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MM,MM64
 
 define signext i1 @and_i1(i1 signext %a, i1 signext %b) {
; ALL-LABEL: and_i8_32768:
   %r = and i8 32768, %b
   ret i8 %r
 }
 
 define signext i16 @and_i16_32768(i16 signext %b) {
 entry:
 ; ALL-LABEL: and_i16_32768:
 
-  ; GP32:         addiu  $[[T0:[0-9]+]], $zero, -32768
-  ; GP32:         and    $2, $4, $[[T0]]
+  ; PREMIPSR2:    srl  $[[T0:[0-9]+]], $4, 15
+  ; PREMIPSR2:    sll  $2, $[[T0]], 15
 
-  ; GP64:         addiu  $[[T0:[0-9]+]], $zero, -32768
-  ; GP64:         and    $2, $4, $[[T0]]
+  ; MIPSR2:       ins $4, $zero, 0, 15
 
-  ; MM:           addiu  $2, $zero, -32768
-  ; MM:           and16  $2, $4
+  ; MM:           ins  $4, $zero, 0, 15
 
   %r = and i16 32768, %b
   ret i16 %r
 }
 
 define signext i32 @and_i32_32768(i32 signext %b) {
 entry:
 ; ALL-LABEL: and_i32_32768:

test/CodeGen/Mips/llvm-ir/zext.ll

+; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefixes=ALL,MIPS2
+; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s -check-prefixes=ALL,64ALL,MIPS3
+; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,64ALL,MIPS64R2
+
+define zeroext i32 @zext_i1_i32(i1 signext %a) {
+entry:
+; ALL-LABEL: zext_i1_i32:
+; ALL: andi $2, $4, 1
+
+  %r = zext i1 %a to i32
+  ret i32 %r
+}
+
+define zeroext i32 @zext_i2_i32(i2 signext %a) {
+entry:
+; ALL-LABEL: zext_i2_i32:
+; ALL: andi $2, $4, 3
+
+  %r = zext i2 %a to i32
+  ret i32 %r
+}
+
+define zeroext i32 @zext_i17_i32(i17 signext %a) {
+entry:
+; ALL-LABEL: zext_i17_i32:
+; MIPS2:    sll $[[T0:[0-9]+]], $4, 15
+; MIPS2:    srl $2, $[[T0]], 15
+
+; MIPS64R2: ext $2, $4, 0, 17
+  %r = zext i17 %a to i32
+  ret i32 %r
+}
+
+define zeroext i64 @zext_i1_i64(i1 signext %a) {
+entry:
+; ALL-LABEL: zext_i1_i64:
+
+; 64ALL: andi $[[T0:[0-9]+]], $4, 1
+
+; MIPS3: dsll $[[T1:[0-9]+]], $[[T0]], 32
+; MIPS3: dsrl $2, $[[T1]], 32
+
+; MIPS64R2: dext $2, $[[T0]], 0, 32
+
+  %r = zext i1 %a to i64
+  ret i64 %r
+}
+
+define zeroext i64 @zext_i2_i64(i2 signext %a) {
+entry:
+; ALL-LABEL: zext_i2_i64:
+
+; 64ALL: andi $[[T0:[0-9]+]], $4, 3
+
+; MIPS3: dsll $[[T1:[0-9]+]], $[[T0]], 32
+; MIPS3: dsrl $2, $[[T1]], 32
+
+; MIPS64R2: dext $2, $[[T0]], 0, 32
+
+  %r = zext i2 %a to i64
+  ret i64 %r
+}
+
+define zeroext i64 @zext_i17_i64(i17 signext %a) {
+entry:
+; ALL-LABEL: zext_i17_i64:
+
+; MIPS3: sll $[[T0:[0-9]+]], $4, 15
+; MIPS3: srl $[[T1:[0-9]+]], $[[T0]], 15
+
+; MIPS3:    dsll $[[T2:[0-9]+]], $[[T1]], 32
+; MIPS3:    dsrl $2, $[[T2]], 32
+
+; MIPS64R2: ext $[[T0:[0-9]+]], $4, 0, 17
+; MIPS64R2: dext $2, $[[T0]], 0, 32
+
+  %r = zext i17 %a to i64
+  ret i64 %r
+}
+
+define zeroext i64 @zext_i32_i64(i32 signext %a) {
+entry:
+; ALL-LABEL: zext_i32_i64:
+
+; MIPS3: dsll $[[T0:[0-9]+]], $4, 32
+; MIPS3: dsrl $2, $[[T0]], 32
+
+; MIPS64R2: dext $2, $4, 0, 32
+
+  %r = zext i32 %a to i64
+  ret i64 %r
+}

test/CodeGen/Mips/load-store-left-right.ll

 ; RUN: llc -march=mipsel   -mcpu=mips32              -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS32,MIPS32-EL %s
 ; RUN: llc -march=mips     -mcpu=mips32              -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS32,MIPS32-EB %s
 ; RUN: llc -march=mipsel   -mcpu=mips32r2            -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS32,MIPS32-EL %s
 ; RUN: llc -march=mips     -mcpu=mips32r2            -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS32,MIPS32-EB %s
 ; RUN: llc -march=mipsel   -mcpu=mips32r6            -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS32R6,MIPS32R6-EL %s
 ; RUN: llc -march=mips     -mcpu=mips32r6            -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS32R6,MIPS32R6-EB %s
-; RUN: llc -march=mips64el -mcpu=mips4    -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EL %s
+; RUN: llc -march=mips64el -mcpu=mips4    -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EL,MIPS64R1-EL %s
 ; RUN: llc -march=mips64   -mcpu=mips4    -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EB %s
-; RUN: llc -march=mips64el -mcpu=mips64   -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EL %s
+; RUN: llc -march=mips64el -mcpu=mips64   -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EL,MIPS64R1-EL %s
 ; RUN: llc -march=mips64   -mcpu=mips64   -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EB %s
-; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EL %s
+; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EL,MIPS64R2-EL %s
 ; RUN: llc -march=mips64   -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EB %s
 ; RUN: llc -march=mips64el -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64R6,MIPS64R6-EL %s
 ; RUN: llc -march=mips64   -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64R6,MIPS64R6-EB %s
 
 %struct.SLL = type { i64 }
 %struct.SI = type { i32 }
 %struct.SUI = type { i32 }
 

 ; MIPS32R6:        lw $[[PTR:[0-9]+]], %got(sui)(
 ; MIPS32R6-EL-DAG: lw $2, 0($[[PTR]])
 ; MIPS32R6-EL-DAG: addiu $3, $zero, 0
 ; MIPS32R6-EB-DAG: lw $3, 0($[[PTR]])
 ; MIPS32R6-EB-DAG: addiu $2, $zero, 0
 
 ; MIPS64-EL-DAG: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
 ; MIPS64-EL-DAG: lwr $[[R0]], 0($[[R1]])
-; MIPS64-EL-DAG: daddiu $[[R2:[0-9]+]], $zero, 1
-; MIPS64-EL-DAG: dsll   $[[R3:[0-9]+]], $[[R2]], 32
-; MIPS64-EL-DAG: daddiu $[[R4:[0-9]+]], $[[R3]], -1
-; MIPS64-EL-DAG: and    ${{[0-9]+}}, $[[R0]], $[[R4]]
+; MIPS64R1-EL-DAG: dsll   $[[R3:[0-9]+]], $[[R0]], 32
+; MIPS64R1-EL-DAG: dsrl   $[[R4:[0-9]+]], $[[R3]], 32
+; MIPS64R2-EL-DAG: dext   $[[R0]], $[[R0]], 0, 32
 
 ; MIPS64-EB:     lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
 ; MIPS64-EB:     lwr $[[R0]], 3($[[R1]])
 
 ; MIPS64R6:      ld $[[PTR:[0-9]+]], %got_disp(sui)(
 ; MIPS64R6:      lwu $2, 0($[[PTR]])
 
   %0 = load i32, i32* getelementptr inbounds (%struct.SUI, %struct.SUI* @sui, i64 0, i32 0), align 1

test/CodeGen/Mips/mips64-f128.ll

 ; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips4 -mattr=+soft-float -O1 \
-; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,C_CC_FMT,PRER6
+; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,C_CC_FMT,PRER6,P64
 ; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips64 -mattr=+soft-float -O1 \
-; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,C_CC_FMT,PRER6
+; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,C_CC_FMT,PRER6,P64
 ; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips64r2 -mattr=+soft-float -O1 \
-; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,C_CC_FMT,PRER6
+; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,C_CC_FMT,PRER6,64R2PLUS
 ; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips64r6 -mattr=+soft-float -O1 \
-; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,CMP_CC_FMT,R6
+; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,CMP_CC_FMT,R6,64R2PLUS
 
 @gld0 = external global fp128
 @gld1 = external global fp128
 @gld2 = external global fp128
 @gf1 = external global float
 @gd1 = external global double
 
 ; ALL-LABEL: addLD:

 
 define double @conv_double_LD(fp128 %a) {
 entry:
   %conv = fptrunc fp128 %a to double
   ret double %conv
 }
 
 ; ALL-LABEL:             libcall1_fabsl:
-; ALL-DAG: ld      $[[R0:[0-9]+]], 8($[[R4:[0-9]+]])
-; ALL-DAG: daddiu  $[[R1:[0-9]+]], $zero, 1
-; ALL-DAG: dsll    $[[R2:[0-9]+]], $[[R1]], 63
-; ALL-DAG: daddiu  $[[R3:[0-9]+]], $[[R2]], -1
-; ALL-DAG: and     $4, $[[R0]], $[[R3]]
-; ALL-DAG: ld      $2, 0($[[R4]])
+; P64-DAG: ld      $[[R0:[0-9]+]], 8($[[R4:[0-9]+]])
+; P64-DAG: dsll    $[[R1:[0-9]+]], $[[R0]], 1
+; P64-DAG: dsrl    $4, $[[R1]], 1
+; P64-DAG: ld      $2, 0($[[R4]])
+
+; 64R2PLUS-DAG: ld      $[[R0:[0-9]+]], 8($[[R4:[0-9]+]])
+; 64R2PLUS-DAG: dinsu   $4, $zero, 63, 1
+; 64R2PLUS-DAG: ld      $2, 0($[[R4]])
+
+
 
 define fp128 @libcall1_fabsl() {
 entry:
   %0 = load fp128, fp128* @gld0, align 16
   %call = tail call fp128 @fabsl(fp128 %0) nounwind readnone
   ret fp128 %call
 }
 

 entry:
   %0 = tail call fp128 @llvm.powi.f128(fp128 %a, i32 %b)
   ret fp128 %0
 }
 
 declare fp128 @llvm.powi.f128(fp128, i32) #3
 
 ; ALL-LABEL:     libcall2_copysignl:
-; ALL-DAG: daddiu $[[R2:[0-9]+]], $zero, 1
-; ALL-DAG: dsll   $[[R3:[0-9]+]], $[[R2]], 63
-; ALL-DAG: ld     $[[R0:[0-9]+]], %got_disp(gld1)
-; ALL-DAG: ld     $[[R1:[0-9]+]], 8($[[R0]])
-; ALL-DAG: and    $[[R4:[0-9]+]], $[[R1]], $[[R3]]
-; ALL-DAG: ld     $[[R5:[0-9]+]], %got_disp(gld0)
-; ALL-DAG: ld     $[[R6:[0-9]+]], 8($[[R5]])
-; ALL-DAG: daddiu $[[R7:[0-9]+]], $[[R3]], -1
-; ALL-DAG: and    $[[R8:[0-9]+]], $[[R6]], $[[R7]]
-; ALL-DAG: or     $4, $[[R8]], $[[R4]]
-; ALL-DAG: ld     $2, 0($[[R5]])
+; ALL-DAG: ld      $[[R0:[0-9]+]], %got_disp(gld1)
+; ALL-DAG: ld      $[[R1:[0-9]+]], 8($[[R0]])
+
+; ALL-DAG: dsrl     $[[R2:[0-9]+]], $[[R1]], 63
+; ALL-DAG: dsll     $[[R3:[0-9]+]], $[[R2]], 63
+; ALL-DAG: ld      $[[R4:[0-9]+]], %got_disp(gld0)
+; ALL-DAG: ld      $[[R5:[0-9]+]], 8($[[R4]])
+
+; P64-DAG: dsll    $[[R5]], $[[R5]], 1
+; P64-DAG: dsrl    $[[R5]], $[[R5]], 1
+
+; 64R2PLUS-DAG: dinsu $[[R5]], $zero, 63, 1
+
+; ALL-DAG: or      $4, $[[R5]]
+
+; ALL-DAG: ld      $2, 0($[[R4]])
 
 define fp128 @libcall2_copysignl() {
 entry:
   %0 = load fp128, fp128* @gld0, align 16
   %1 = load fp128, fp128* @gld1, align 16
   %call = tail call fp128 @copysignl(fp128 %0, fp128 %1) nounwind readnone
   ret fp128 %call
 }

test/CodeGen/Mips/o32_cc_vararg.ll

 
 ; CHECK-LABEL: va2:
 ; CHECK: addiu   $sp, $sp, -16
 ; CHECK: sw      $7, 28($sp)
 ; CHECK: sw      $6, 24($sp)
 ; CHECK: sw      $5, 20($sp)
 ; CHECK: addiu   $[[R0:[0-9]+]], $sp, 20
 ; CHECK: addiu   $[[R1:[0-9]+]], $[[R0]], 7
-; CHECK: addiu   $[[R2:[0-9]+]], $zero, -8
-; CHECK: and     $[[R3:[0-9]+]], $[[R1]], $[[R2]]
+; CHECK: srl     $[[R2:[0-9]+]], $[[R1]], 3
+; CHECK: sll     $[[R3:[0-9]+]], $[[R2]], 3
 ; CHECK: ldc1    $f0, 0($[[R3]])
 }
 
 ; int
 define i32 @va3(double %a, ...) nounwind {
 entry:
   %a.addr = alloca double, align 8
   %ap = alloca i8*, align 4
entry:
   %tmp = load double, double* %d, align 8
   ret double %tmp
 
 ; CHECK-LABEL: va6:
 ; CHECK: addiu   $sp, $sp, -24
 ; CHECK: sw      $7, 36($sp)
 ; CHECK: addiu   $[[R0:[0-9]+]], $sp, 36
 ; CHECK: addiu   $[[R1:[0-9]+]], $[[R0]], 7
-; CHECK: addiu   $[[R2:[0-9]+]], $zero, -8
-; CHECK: and     $[[R3:[0-9]+]], $[[R1]], $[[R2]]
+; CHECK: srl     $[[R2:[0-9]+]], $[[R1]], 3
+; CHECK: sll     $[[R3:[0-9]+]], $[[R2]], 3
 ; CHECK: ldc1    $f0, 0($[[R3]])
 }
 
 ; int
 define i32 @va7(i32 %a, double %b, ...) nounwind {
 entry:
   %a.addr = alloca i32, align 4
   %b.addr = alloca double, align 8
entry:
   call void @llvm.va_end(i8* %ap2)
   %tmp = load double, double* %d, align 8
   ret double %tmp
 
 ; CHECK-LABEL: va10:
 ; CHECK: addiu   $sp, $sp, -32
 ; CHECK: addiu   $[[R0:[0-9]+]], $sp, 52
 ; CHECK: addiu   $[[R1:[0-9]+]], $[[R0]], 7
-; CHECK: addiu   $[[R2:[0-9]+]], $zero, -8
-; CHECK: and     $[[R3:[0-9]+]], $[[R1]], $[[R2]]
+; CHECK: srl     $[[R2:[0-9]+]], $[[R1]], 3
+; CHECK: sll     $[[R3:[0-9]+]], $[[R2]], 3
 ; CHECK: ldc1    $f0, 0($[[R3]])
 }

test/MC/Mips/sext_64_32.ll

 ; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 %s -o - | \
 ; RUN:   llvm-objdump -disassemble - | FileCheck %s
 
 ; Sign extend from 32 to 64 was creating nonsense opcodes
 
 ; CHECK: sll ${{[a-z0-9]+}}, ${{[a-z0-9]+}}, 0
 
 define i64 @foo(i32 %ival) nounwind readnone {
 entry:
   %conv = sext i32 %ival to i64
   ret i64 %conv
 }
 
-; CHECK: dsll32 ${{[a-z0-9]+}}, ${{[a-z0-9]+}}, 0
+; CHECK: dext ${{[a-z0-9]+}}, ${{[a-z0-9]+}}, 0, 32
 
 define i64 @foo_2(i32 %ival_2) nounwind readnone {
 entry:
   %conv_2 = zext i32 %ival_2 to i64
   ret i64 %conv_2
 }