Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -4565,6 +4565,9 @@
     return SDValue();
 
   EVT VT = Operand.getValueType();
+  if (VT != MVT::f32 && VT != MVT::v2f32 && VT != MVT::v4f32 &&
+      VT != MVT::f64 && VT != MVT::v2f64)
+    return (SDValue());
 
   std::string RecipOp;
   RecipOp = Opcode == (AArch64ISD::FRECPE) ? "div": "sqrt";
@@ -4573,7 +4576,7 @@
 
   TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
   if (!Recips.isEnabled(RecipOp))
-    return SDValue();
+    return (SDValue());
 
   ExtraSteps = Recips.getRefinementSteps(RecipOp);
   return DCI.DAG.getNode(Opcode, SDLoc(Operand), VT, Operand);