Index: lib/Target/AMDGPU/SISchedule.td
===================================================================
--- lib/Target/AMDGPU/SISchedule.td
+++ lib/Target/AMDGPU/SISchedule.td
@@ -105,6 +105,8 @@
 def : HWVALUWriteRes<WriteDouble,     4>;
 def : HWVALUWriteRes<WriteDoubleAdd,  2>;
 
+def : InstRW<[WriteSALU], (instrs COPY)>;
+
 } // End SchedModel = SIFullSpeedModel
 
 let SchedModel = SIQuarterSpeedModel in {
@@ -115,4 +117,6 @@
 def : HWVALUWriteRes<WriteDouble,   16>;
 def : HWVALUWriteRes<WriteDoubleAdd, 8>;
 
+def : InstRW<[WriteSALU], (instrs COPY)>;
+
 }  // End SchedModel = SIQuarterSpeedModel