Index: ELF/Target.cpp
===================================================================
--- ELF/Target.cpp
+++ ELF/Target.cpp
@@ -1254,17 +1254,25 @@
   write32le(Loc, NewInst);
 }
 
-// Implementing relocations for AMDGPU is low priority since most
-// programs don't use relocations now. Thus, this function is not
-// actually called (relocateOne is called for each relocation).
-// That's why the AMDGPU port works without implementing this function.
 void AMDGPUTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type,
                                    uint64_t Val) const {
-  llvm_unreachable("not implemented");
+  switch (Type) {
+  case R_AMDGPU_32_LOW:
+    write32le(Loc, Val);
+    break;
+  case R_AMDGPU_32_HIGH:
+    write32le(Loc, (Val >> 32) & 0xFFFFFFFF);
+    break;
+  case R_AMDGPU_64:
+    write64le(Loc, Val);
+    break;
+  default:
+    fatal("unrecognized reloc " + Twine(Type));
+  }
 }
 
 RelExpr AMDGPUTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const {
-  llvm_unreachable("not implemented");
+  return R_ABS;
 }
 
 template <class ELFT> MipsTargetInfo<ELFT>::MipsTargetInfo() {
Index: test/ELF/amdgpu-relocs.test
===================================================================
--- test/ELF/amdgpu-relocs.test
+++ test/ELF/amdgpu-relocs.test
@@ -0,0 +1,51 @@
+# RUN: yaml2obj -format=elf  %s > %t
+# RUN: ld.lld %t -shared -o %t.so
+# RUN: llvm-objdump -s %t.so | FileCheck %s
+
+# CHECK: Contents of section .target.section:
+# CHECK-NEXT: 0000 ffffffff aaaa0000 ffffffff bbbb0000
+
+FileHeader:
+  Class:           ELFCLASS64
+  Data:            ELFDATA2LSB
+  Type:            ET_REL
+  Machine:         EM_AMDGPU
+Sections:
+  - Type:            SHT_PROGBITS
+    Name:            .symbol.data
+    Flags:           [ ]
+    AddressAlign:    0x08
+    Content:         00000000000000000000000000000000
+  - Type:            SHT_PROGBITS
+    Name:            .target.section
+    Flags:           [ ]
+    AddressAlign:    0x08
+    Content:         00000000000000000000000000000000
+  - Type:            SHT_RELA
+    Name:            .rela.target.section
+    Link:            .symtab
+    Info:            .target.section
+    AddressAlign:    0x08
+    Relocations:
+      - Offset:          0x0
+        Symbol:          a
+        Type:            R_AMDGPU_32_LOW
+      - Offset:          0x4
+        Symbol:          a
+        Type:            R_AMDGPU_32_HIGH
+      - Offset:          0x8
+        Symbol:          b
+        Type:            R_AMDGPU_64
+
+Symbols:
+  Global:
+    - Name:            a
+      Type:            STT_OBJECT
+      Section:         .symbol.data
+      Size:            0x08
+      Value:           0xAAAAFFFFFFFF
+    - Name:            b
+      Type:            STT_OBJECT
+      Section:         .symbol.data
+      Size:            0x08
+      Value:           0xBBBBFFFFFFFF