Index: lib/Target/AMDGPU/SIInstrInfo.h
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.h
+++ lib/Target/AMDGPU/SIInstrInfo.h
@@ -30,7 +30,11 @@
   enum BranchPredicate {
     INVALID_BR = 0,
     SCC_TRUE = 1,
-    SCC_FALSE = -1
+    SCC_FALSE = -1,
+    VCCNZ = 2,
+    VCCZ = -2,
+    EXECNZ = -3,
+    EXECZ = 3
   };
 
   static unsigned getBranchOpcode(BranchPredicate Cond);
Index: lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.cpp
+++ lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -1063,6 +1063,14 @@
     return AMDGPU::S_CBRANCH_SCC1;
   case SIInstrInfo::SCC_FALSE:
     return AMDGPU::S_CBRANCH_SCC0;
+  case SIInstrInfo::VCCNZ:
+    return AMDGPU::S_CBRANCH_VCCNZ;
+  case SIInstrInfo::VCCZ:
+    return AMDGPU::S_CBRANCH_VCCZ;
+  case SIInstrInfo::EXECNZ:
+    return AMDGPU::S_CBRANCH_EXECNZ;
+  case SIInstrInfo::EXECZ:
+    return AMDGPU::S_CBRANCH_EXECZ;
   default:
     llvm_unreachable("invalid branch predicate");
   }
@@ -1074,6 +1082,14 @@
     return SCC_FALSE;
   case AMDGPU::S_CBRANCH_SCC1:
     return SCC_TRUE;
+  case AMDGPU::S_CBRANCH_VCCNZ:
+    return VCCNZ;
+  case AMDGPU::S_CBRANCH_VCCZ:
+    return VCCZ;
+  case AMDGPU::S_CBRANCH_EXECNZ:
+    return EXECNZ;
+  case AMDGPU::S_CBRANCH_EXECZ:
+    return EXECZ;
   default:
     return INVALID_BR;
   }
Index: test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll
===================================================================
--- test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll
+++ test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll
@@ -12,8 +12,7 @@
 ; GCN: ds_read_b32
 ; GCN: buffer_store_dword
 
-; GCN: s_cbranch_vccnz BB0_3
-; GCN: s_branch BB0_2
+; GCN: s_cbranch_vccz BB0_2
 
 ; GCN: BB0_3:
 ; GCN-NEXT: s_endpgm
Index: test/CodeGen/AMDGPU/uniform-loop-inside-nonuniform.ll
===================================================================
--- test/CodeGen/AMDGPU/uniform-loop-inside-nonuniform.ll
+++ test/CodeGen/AMDGPU/uniform-loop-inside-nonuniform.ll
@@ -1,10 +1,16 @@
-;RUN: llc -march=amdgcn -mcpu=verde < %s | FileCheck %s
+; RUN: llc -march=amdgcn -mcpu=verde < %s | FileCheck %s
 
 ; Test a simple uniform loop that lives inside non-uniform control flow.
 
-;CHECK-LABEL: {{^}}test1:
-;CHECK: s_cbranch_execz
-;CHECK: %loop_body
+; CHECK-LABEL: {{^}}test1:
+; CHECK: v_cmp_ne_i32_e32 vcc, 0
+; CHECK: s_and_saveexec_b64
+
+; CHECK: [[LOOP_BODY_LABEL:BB[0-9]+_[0-9]+]]:
+; CHECK: s_and_b64 vcc, exec, vcc
+; CHECK: s_cbranch_vccz [[LOOP_BODY_LABEL]]
+
+; CHECK: s_endpgm
 define amdgpu_ps void @test1(<8 x i32> inreg %rsrc, <2 x i32> %addr.base, i32 %y, i32 %p) {
 main_body:
   %cc = icmp eq i32 %p, 0
Index: test/CodeGen/AMDGPU/valu-i1.ll
===================================================================
--- test/CodeGen/AMDGPU/valu-i1.ll
+++ test/CodeGen/AMDGPU/valu-i1.ll
@@ -81,8 +81,7 @@
 ; SI-DAG: buffer_store_dword
 ; SI-DAG: v_cmp_eq_i32_e32 vcc,
 ; SI-DAG: s_and_b64 vcc, exec, vcc
-; SI: s_cbranch_vccnz [[LABEL_EXIT]]
-; SI: s_branch [[LABEL_LOOP]]
+; SI: s_cbranch_vccz [[LABEL_LOOP]]
 ; SI: [[LABEL_EXIT]]:
 ; SI: s_endpgm