Index: include/llvm/Target/Target.td =================================================================== --- include/llvm/Target/Target.td +++ include/llvm/Target/Target.td @@ -954,15 +954,6 @@ let hasSideEffects = 1; let isReturn = 1; } -def PATCHABLE_TAIL_CALL : Instruction { - let OutOperandList = (outs); - let InOperandList = (ins); - let AsmString = "# XRay Tail Call Exit."; - let usesCustomInserter = 1; - let hasSideEffects = 0; - let isTerminator = 1; - let isReturn = 1; -} // Generic opcodes used in GlobalISel. include "llvm/Target/GenericOpcodes.td" Index: include/llvm/Target/TargetOpcodes.def =================================================================== --- include/llvm/Target/TargetOpcodes.def +++ include/llvm/Target/TargetOpcodes.def @@ -148,19 +148,16 @@ /// PATCHABLE_RET - a marker for XRay function exit blocks. HANDLE_TARGET_OPCODE(PATCHABLE_RET, 25) -/// PATCHABLE_TAIL_CALL - a marker for XRay tail call exits. -HANDLE_TARGET_OPCODE(PATCHABLE_TAIL_CALL, 26) - /// The following generic opcodes are not supposed to appear after ISel. /// This is something we might want to relax, but for now, this is convenient /// to produce diagnostics. /// Generic ADD instruction. This is an integer add. -HANDLE_TARGET_OPCODE(G_ADD, 27) +HANDLE_TARGET_OPCODE(G_ADD, 26) HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_START, G_ADD) /// Generic BRANCH instruction. This is an unconditional branch. -HANDLE_TARGET_OPCODE(G_BR, 28) +HANDLE_TARGET_OPCODE(G_BR, 27) // TODO: Add more generic opcodes as we move along. Index: lib/CodeGen/XRayInstrumentation.cpp =================================================================== --- lib/CodeGen/XRayInstrumentation.cpp +++ lib/CodeGen/XRayInstrumentation.cpp @@ -21,6 +21,7 @@ #include "llvm/CodeGen/Passes.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetSubtargetInfo.h" +#include "llvm/Support/TargetRegistry.h" using namespace llvm; @@ -69,16 +70,17 @@ for (auto &MBB : MF) { for (auto &Terminator : MBB.terminators()) { // FIXME: Handle tail calls here too? - if (Terminator.isReturn()) { + if (Terminator.isReturn() && + (Terminator.getOpcode() != ISD::CATCHRET || + Terminator.getOpcode() != ISD::CLEANUPRET || + Terminator.getOpcode() != ISD::EH_RETURN)) { // Replace return instructions with: // PATCHABLE_RET , ... auto MIB = BuildMI(MBB, Terminator, Terminator.getDebugLoc(), TII->get(TargetOpcode::PATCHABLE_RET)) .addImm(Terminator.getOpcode()); - for (auto &MO : Terminator.operands()) { - if (MO.isReg()) - MIB.addReg(MO.getReg(), RegState::Implicit); - } + for (auto &MO : Terminator.operands()) + MIB.addReg(MO.getReg(), RegState::Implicit); Terminators.push_back(&Terminator); } } Index: lib/Target/X86/X86MCInstLower.cpp =================================================================== --- lib/Target/X86/X86MCInstLower.cpp +++ lib/Target/X86/X86MCInstLower.cpp @@ -1065,12 +1065,11 @@ void X86AsmPrinter::recordSled(MCSymbol *Sled, const MachineInstr &MI) { auto Fn = MI.getParent()->getParent()->getFunction(); auto Attr = Fn->getFnAttribute("function-instrument"); - bool AlwaysInstrument = false; - if (!Attr.hasAttribute(Attribute::None) && Attr.isStringAttribute() && - Attr.getValueAsString() == "xray-always") - AlwaysInstrument = true; - Sleds.push_back( - {Sled, CurrentFnSym, SledKind::FUNCTION_ENTER, AlwaysInstrument}); + bool AlwaysInstrument = + Attr.isStringAttribute() && Attr.getValueAsString() == "xray-always"; + AlwaysInstrument = true; + Sleds.emplace_back(XRayFunctionEntry{ + Sled, CurrentFnSym, SledKind::FUNCTION_ENTER, AlwaysInstrument}); } void X86AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI, @@ -1097,7 +1096,7 @@ } void X86AsmPrinter::LowerPATCHABLE_RET(const MachineInstr &MI, - X86MCInstLower &MCIL) { + X86MCInstLower &MCIL) { // Since PATCHABLE_RET takes the opcode of the return statement as an // argument, we use that to emit the correct form of the RET that we want. // i.e. when we see this: @@ -1124,11 +1123,6 @@ recordSled(CurSled, MI); } -void X86AsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI, - X86MCInstLower &MCIL) { - // FIXME: Do something later. -} - void X86AsmPrinter::EmitXRayTable() { // Do not emit the XRay section if there were no sleds encountered. if (Sleds.empty()) return; @@ -1401,9 +1395,6 @@ case TargetOpcode::PATCHABLE_RET: return LowerPATCHABLE_RET(*MI, MCInstLowering); - case TargetOpcode::PATCHABLE_TAIL_CALL: - return LowerPATCHABLE_TAIL_CALL(*MI, MCInstLowering); - case X86::MORESTACK_RET: EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget))); return; Index: test/TableGen/trydecode-emission.td =================================================================== --- test/TableGen/trydecode-emission.td +++ test/TableGen/trydecode-emission.td @@ -36,8 +36,8 @@ // CHECK: /* 0 */ MCD::OPC_ExtractField, 4, 4, // Inst{7-4} ... // CHECK-NEXT: /* 3 */ MCD::OPC_FilterValue, 0, 14, 0, // Skip to: 21 // CHECK-NEXT: /* 7 */ MCD::OPC_CheckField, 2, 2, 0, 5, 0, // Skip to: 18 -// CHECK-NEXT: /* 13 */ MCD::OPC_TryDecode, 30, 0, 0, 0, // Opcode: InstB, skip to: 18 -// CHECK-NEXT: /* 18 */ MCD::OPC_Decode, 29, 1, // Opcode: InstA +// CHECK-NEXT: /* 13 */ MCD::OPC_TryDecode, 29, 0, 0, 0, // Opcode: InstB, skip to: 18 +// CHECK-NEXT: /* 18 */ MCD::OPC_Decode, 28, 1, // Opcode: InstA // CHECK-NEXT: /* 21 */ MCD::OPC_Fail, // CHECK: if (DecodeInstB(MI, insn, Address, Decoder) == MCDisassembler::Fail) { DecodeComplete = false; return MCDisassembler::Fail; } Index: test/TableGen/trydecode-emission2.td =================================================================== --- test/TableGen/trydecode-emission2.td +++ test/TableGen/trydecode-emission2.td @@ -35,9 +35,9 @@ // CHECK-NEXT: /* 7 */ MCD::OPC_ExtractField, 5, 3, // Inst{7-5} ... // CHECK-NEXT: /* 10 */ MCD::OPC_FilterValue, 0, 22, 0, // Skip to: 36 // CHECK-NEXT: /* 14 */ MCD::OPC_CheckField, 0, 2, 3, 5, 0, // Skip to: 25 -// CHECK-NEXT: /* 20 */ MCD::OPC_TryDecode, 30, 0, 0, 0, // Opcode: InstB, skip to: 25 +// CHECK-NEXT: /* 20 */ MCD::OPC_TryDecode, 29, 0, 0, 0, // Opcode: InstB, skip to: 25 // CHECK-NEXT: /* 25 */ MCD::OPC_CheckField, 3, 2, 0, 5, 0, // Skip to: 36 -// CHECK-NEXT: /* 31 */ MCD::OPC_TryDecode, 29, 1, 0, 0, // Opcode: InstA, skip to: 36 +// CHECK-NEXT: /* 31 */ MCD::OPC_TryDecode, 28, 1, 0, 0, // Opcode: InstA, skip to: 36 // CHECK-NEXT: /* 36 */ MCD::OPC_Fail, // CHECK: if (DecodeInstB(MI, insn, Address, Decoder) == MCDisassembler::Fail) { DecodeComplete = false; return MCDisassembler::Fail; } Index: test/TableGen/trydecode-emission3.td =================================================================== --- test/TableGen/trydecode-emission3.td +++ test/TableGen/trydecode-emission3.td @@ -37,8 +37,8 @@ // CHECK: /* 0 */ MCD::OPC_ExtractField, 4, 4, // Inst{7-4} ... // CHECK-NEXT: /* 3 */ MCD::OPC_FilterValue, 0, 14, 0, // Skip to: 21 // CHECK-NEXT: /* 7 */ MCD::OPC_CheckField, 2, 2, 0, 5, 0, // Skip to: 18 -// CHECK-NEXT: /* 13 */ MCD::OPC_TryDecode, 30, 0, 0, 0, // Opcode: InstB, skip to: 18 -// CHECK-NEXT: /* 18 */ MCD::OPC_Decode, 29, 1, // Opcode: InstA +// CHECK-NEXT: /* 13 */ MCD::OPC_TryDecode, 29, 0, 0, 0, // Opcode: InstB, skip to: 18 +// CHECK-NEXT: /* 18 */ MCD::OPC_Decode, 28, 1, // Opcode: InstA // CHECK-NEXT: /* 21 */ MCD::OPC_Fail, // CHECK: if (DecodeInstBOp(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { DecodeComplete = false; return MCDisassembler::Fail; }