Index: lib/Target/Mips/AsmParser/MipsAsmParser.cpp =================================================================== --- lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -175,80 +175,80 @@ }; // Expands assembly pseudo instructions. - MacroExpanderResultTy - tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl &Instructions); + MacroExpanderResultTy tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, + MCStreamer &Out, + const MCSubtargetInfo *STI); - bool expandJalWithRegs(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl &Instructions); + bool expandJalWithRegs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI); bool loadImmediate(int64_t ImmValue, unsigned DstReg, unsigned SrcReg, bool Is32BitImm, bool IsAddress, SMLoc IDLoc, - SmallVectorImpl &Instructions); + MCStreamer &Out, const MCSubtargetInfo *STI); bool loadAndAddSymbolAddress(const MCExpr *SymExpr, unsigned DstReg, unsigned SrcReg, bool Is32BitSym, SMLoc IDLoc, - SmallVectorImpl &Instructions); + MCStreamer &Out, const MCSubtargetInfo *STI); bool expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc, - SmallVectorImpl &Instructions); + MCStreamer &Out, const MCSubtargetInfo *STI); bool expandLoadAddress(unsigned DstReg, unsigned BaseReg, const MCOperand &Offset, bool Is32BitAddress, - SMLoc IDLoc, SmallVectorImpl &Instructions); + SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI); - bool expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl &Instructions); + bool expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI); - void expandMemInst(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl &Instructions, bool isLoad, - bool isImmOpnd); + void expandMemInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI, bool isLoad, bool isImmOpnd); - bool expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl &Instructions); + bool expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI); - bool expandAliasImmediate(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl &Instructions); + bool expandAliasImmediate(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI); - bool expandBranchImm(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl &Instructions); + bool expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI); - bool expandCondBranches(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl &Instructions); + bool expandCondBranches(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI); - bool expandDiv(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl &Instructions, const bool IsMips64, + bool expandDiv(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI, const bool IsMips64, const bool Signed); bool expandTrunc(MCInst &Inst, bool IsDouble, bool Is64FPU, SMLoc IDLoc, - SmallVectorImpl &Instructions); + MCStreamer &Out, const MCSubtargetInfo *STI); - bool expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc, - SmallVectorImpl &Instructions); + bool expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI); - bool expandUlw(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl &Instructions); + bool expandUlw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI); bool expandRotation(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl &Instructions); - bool expandRotationImm(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl &Instructions); - bool expandDRotation(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl &Instructions); - bool expandDRotationImm(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl &Instructions); + MCStreamer &Out, const MCSubtargetInfo *STI); + bool expandRotationImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI); + bool expandDRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI); + bool expandDRotationImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI); - bool expandAbs(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl &Instructions); + bool expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI); - void createNop(bool hasShortDelaySlot, SMLoc IDLoc, - SmallVectorImpl &Instructions); + void createNop(bool hasShortDelaySlot, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI); void createAddu(unsigned DstReg, unsigned SrcReg, unsigned TrgReg, - bool Is64Bit, SmallVectorImpl &Instructions); + bool Is64Bit, MCStreamer &Out, const MCSubtargetInfo *STI); void createCpRestoreMemOp(bool IsLoad, int StackOffset, SMLoc IDLoc, - SmallVectorImpl &Instructions); + MCStreamer &Out, const MCSubtargetInfo *STI); bool reportParseError(Twine ErrorMsg); bool reportParseError(SMLoc Loc, Twine ErrorMsg); @@ -333,8 +333,8 @@ /// This should be used in pseudo-instruction expansions which need AT. unsigned getATReg(SMLoc Loc); - bool processInstruction(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl &Instructions); + bool processInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI); // Helper function that checks if the value of a vector index is within the // boundaries of accepted values for each RegisterKind @@ -1495,81 +1495,80 @@ namespace { void emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, SMLoc IDLoc, - SmallVectorImpl &Instructions) { + MCStreamer &Out, const MCSubtargetInfo *STI) { MCInst tmpInst; tmpInst.setOpcode(Opcode); tmpInst.addOperand(MCOperand::createReg(Reg0)); tmpInst.addOperand(Op1); tmpInst.setLoc(IDLoc); - Instructions.push_back(tmpInst); + Out.EmitInstruction(tmpInst, *STI); } void emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, SMLoc IDLoc, - SmallVectorImpl &Instructions) { - emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, Instructions); + MCStreamer &Out, const MCSubtargetInfo *STI) { + emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, Out, STI); } void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc, - SmallVectorImpl &Instructions) { - emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, Instructions); + MCStreamer &Out, const MCSubtargetInfo *STI) { + emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, Out, STI); } void emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2, SMLoc IDLoc, - SmallVectorImpl &Instructions) { + MCStreamer &Out, const MCSubtargetInfo *STI) { MCInst tmpInst; tmpInst.setOpcode(Opcode); tmpInst.addOperand(MCOperand::createImm(Imm1)); tmpInst.addOperand(MCOperand::createImm(Imm2)); tmpInst.setLoc(IDLoc); - Instructions.push_back(tmpInst); + Out.EmitInstruction(tmpInst, *STI); } void emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, - SmallVectorImpl &Instructions) { + MCStreamer &Out, const MCSubtargetInfo *STI) { MCInst tmpInst; tmpInst.setOpcode(Opcode); tmpInst.addOperand(MCOperand::createReg(Reg0)); tmpInst.setLoc(IDLoc); - Instructions.push_back(tmpInst); + Out.EmitInstruction(tmpInst, *STI); } void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2, - SMLoc IDLoc, SmallVectorImpl &Instructions) { + SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { MCInst tmpInst; tmpInst.setOpcode(Opcode); tmpInst.addOperand(MCOperand::createReg(Reg0)); tmpInst.addOperand(MCOperand::createReg(Reg1)); tmpInst.addOperand(Op2); tmpInst.setLoc(IDLoc); - Instructions.push_back(tmpInst); + Out.EmitInstruction(tmpInst, *STI); } void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2, - SMLoc IDLoc, SmallVectorImpl &Instructions) { - emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, - Instructions); + SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { + emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, Out, STI); } void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm, - SMLoc IDLoc, SmallVectorImpl &Instructions) { - emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, - Instructions); + SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { + emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, Out, STI); } void emitAppropriateDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount, - SMLoc IDLoc, SmallVectorImpl &Instructions) { + SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI) { if (ShiftAmount >= 32) { - emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, - Instructions); + emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, Out, STI); return; } - emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, Instructions); + emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, Out, STI); } } // end anonymous namespace. bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl &Instructions) { + MCStreamer &Out, + const MCSubtargetInfo *STI) { const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode()); bool ExpandedJalSym = false; @@ -1729,9 +1728,9 @@ const MCExpr *Lo16RelocExpr = evaluateRelocExpr(JalExpr, "lo"); emitRRX(Mips::LW, Mips::T9, Mips::GP, - MCOperand::createExpr(Got16RelocExpr), IDLoc, Instructions); + MCOperand::createExpr(Got16RelocExpr), IDLoc, Out, STI); emitRRX(Mips::ADDiu, Mips::T9, Mips::T9, - MCOperand::createExpr(Lo16RelocExpr), IDLoc, Instructions); + MCOperand::createExpr(Lo16RelocExpr), IDLoc, Out, STI); } else if (isABI_N32() || isABI_N64()) { // If it's a local symbol and the N32/N64 ABIs are being used, // we expand to: @@ -1741,7 +1740,7 @@ const MCExpr *GotDispRelocExpr = evaluateRelocExpr(JalExpr, "got_disp"); emitRRX(ABI.ArePtrs64bit() ? Mips::LD : Mips::LW, Mips::T9, Mips::GP, - MCOperand::createExpr(GotDispRelocExpr), IDLoc, Instructions); + MCOperand::createExpr(GotDispRelocExpr), IDLoc, Out, STI); } } else { // If it's an external/weak symbol, we expand to: @@ -1751,7 +1750,7 @@ const MCExpr *Call16RelocExpr = evaluateRelocExpr(JalExpr, "call16"); emitRRX(ABI.ArePtrs64bit() ? Mips::LD : Mips::LW, Mips::T9, Mips::GP, - MCOperand::createExpr(Call16RelocExpr), IDLoc, Instructions); + MCOperand::createExpr(Call16RelocExpr), IDLoc, Out, STI); } MCInst JalrInst; @@ -1782,7 +1781,7 @@ int MemOffset = Op.getImm(); if (MemOffset < -32768 || MemOffset > 32767) { // Offset can't exceed 16bit value. - expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), true); + expandMemInst(Inst, IDLoc, Out, STI, MCID.mayLoad(), true); return false; } } else if (Op.isExpr()) { @@ -1792,11 +1791,11 @@ static_cast(Expr); if (SR->getKind() == MCSymbolRefExpr::VK_None) { // Expand symbol. - expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false); + expandMemInst(Inst, IDLoc, Out, STI, MCID.mayLoad(), false); return false; } } else if (!isEvaluated(Expr)) { - expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false); + expandMemInst(Inst, IDLoc, Out, STI, MCID.mayLoad(), false); return false; } } @@ -1823,7 +1822,7 @@ BaseReg.getReg() == Mips::GP_64)) { emitRRI(Mips::LWGP_MM, DstReg.getReg(), Mips::GP, MemOffset, - IDLoc, Instructions); + IDLoc, Out, STI); return false; } } @@ -1933,10 +1932,10 @@ } MacroExpanderResultTy ExpandResult = - tryExpandInstruction(Inst, IDLoc, Instructions); + tryExpandInstruction(Inst, IDLoc, Out, STI); switch (ExpandResult) { case MER_NotAMacro: - Instructions.push_back(Inst); + Out.EmitInstruction(Inst, *STI); break; case MER_Success: break; @@ -1947,7 +1946,7 @@ // If this instruction has a delay slot and .set reorder is active, // emit a NOP after it. if (MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder()) - createNop(hasShortDelaySlot(Inst.getOpcode()), IDLoc, Instructions); + createNop(hasShortDelaySlot(Inst.getOpcode()), IDLoc, Out, STI); if ((Inst.getOpcode() == Mips::JalOneReg || Inst.getOpcode() == Mips::JalTwoReg || ExpandedJalSym) && @@ -1957,16 +1956,11 @@ // If .set reorder has been used, we've already emitted a NOP. // If .set noreorder has been used, we need to emit a NOP at this point. if (!AssemblerOptions.back()->isReorder()) - createNop(hasShortDelaySlot(Inst.getOpcode()), IDLoc, Instructions); + createNop(hasShortDelaySlot(Inst.getOpcode()), IDLoc, Out, STI); // Load the $gp from the stack. - SmallVector LoadInsts; createCpRestoreMemOp(true /*IsLoad*/, CpRestoreOffset /*StackOffset*/, - IDLoc, LoadInsts); - - for (const MCInst &Inst : LoadInsts) - Instructions.push_back(Inst); - + IDLoc, Out, STI); } else Warning(IDLoc, "no .cprestore used in PIC mode"); } @@ -1975,17 +1969,15 @@ } MipsAsmParser::MacroExpanderResultTy -MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl &Instructions) { +MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI) { switch (Inst.getOpcode()) { default: return MER_NotAMacro; case Mips::LoadImm32: - return expandLoadImm(Inst, true, IDLoc, Instructions) ? MER_Fail - : MER_Success; + return expandLoadImm(Inst, true, IDLoc, Out, STI) ? MER_Fail : MER_Success; case Mips::LoadImm64: - return expandLoadImm(Inst, false, IDLoc, Instructions) ? MER_Fail - : MER_Success; + return expandLoadImm(Inst, false, IDLoc, Out, STI) ? MER_Fail : MER_Success; case Mips::LoadAddrImm32: case Mips::LoadAddrImm64: assert(Inst.getOperand(0).isReg() && "expected register operand kind"); @@ -1995,7 +1987,7 @@ return expandLoadAddress(Inst.getOperand(0).getReg(), Mips::NoRegister, Inst.getOperand(1), Inst.getOpcode() == Mips::LoadAddrImm32, IDLoc, - Instructions) + Out, STI) ? MER_Fail : MER_Success; case Mips::LoadAddrReg32: @@ -2008,24 +2000,23 @@ return expandLoadAddress(Inst.getOperand(0).getReg(), Inst.getOperand(1).getReg(), Inst.getOperand(2), Inst.getOpcode() == Mips::LoadAddrReg32, IDLoc, - Instructions) + Out, STI) ? MER_Fail : MER_Success; case Mips::B_MM_Pseudo: case Mips::B_MMR6_Pseudo: - return expandUncondBranchMMPseudo(Inst, IDLoc, Instructions) ? MER_Fail - : MER_Success; + return expandUncondBranchMMPseudo(Inst, IDLoc, Out, STI) ? MER_Fail + : MER_Success; case Mips::SWM_MM: case Mips::LWM_MM: - return expandLoadStoreMultiple(Inst, IDLoc, Instructions) ? MER_Fail - : MER_Success; + return expandLoadStoreMultiple(Inst, IDLoc, Out, STI) ? MER_Fail + : MER_Success; case Mips::JalOneReg: case Mips::JalTwoReg: - return expandJalWithRegs(Inst, IDLoc, Instructions) ? MER_Fail - : MER_Success; + return expandJalWithRegs(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; case Mips::BneImm: case Mips::BeqImm: - return expandBranchImm(Inst, IDLoc, Instructions) ? MER_Fail : MER_Success; + return expandBranchImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; case Mips::BLT: case Mips::BLE: case Mips::BGE: @@ -2058,38 +2049,36 @@ case Mips::BLEULImmMacro: case Mips::BGEULImmMacro: case Mips::BGTULImmMacro: - return expandCondBranches(Inst, IDLoc, Instructions) ? MER_Fail - : MER_Success; + return expandCondBranches(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; case Mips::SDivMacro: - return expandDiv(Inst, IDLoc, Instructions, false, true) ? MER_Fail - : MER_Success; + return expandDiv(Inst, IDLoc, Out, STI, false, true) ? MER_Fail + : MER_Success; case Mips::DSDivMacro: - return expandDiv(Inst, IDLoc, Instructions, true, true) ? MER_Fail - : MER_Success; + return expandDiv(Inst, IDLoc, Out, STI, true, true) ? MER_Fail + : MER_Success; case Mips::UDivMacro: - return expandDiv(Inst, IDLoc, Instructions, false, false) ? MER_Fail - : MER_Success; + return expandDiv(Inst, IDLoc, Out, STI, false, false) ? MER_Fail + : MER_Success; case Mips::DUDivMacro: - return expandDiv(Inst, IDLoc, Instructions, true, false) ? MER_Fail - : MER_Success; + return expandDiv(Inst, IDLoc, Out, STI, true, false) ? MER_Fail + : MER_Success; case Mips::PseudoTRUNC_W_S: - return expandTrunc(Inst, false, false, IDLoc, Instructions) ? MER_Fail - : MER_Success; + return expandTrunc(Inst, false, false, IDLoc, Out, STI) ? MER_Fail + : MER_Success; case Mips::PseudoTRUNC_W_D32: - return expandTrunc(Inst, true, false, IDLoc, Instructions) ? MER_Fail - : MER_Success; + return expandTrunc(Inst, true, false, IDLoc, Out, STI) ? MER_Fail + : MER_Success; case Mips::PseudoTRUNC_W_D: - return expandTrunc(Inst, true, true, IDLoc, Instructions) ? MER_Fail - : MER_Success; + return expandTrunc(Inst, true, true, IDLoc, Out, STI) ? MER_Fail + : MER_Success; case Mips::Ulh: - return expandUlh(Inst, true, IDLoc, Instructions) ? MER_Fail : MER_Success; + return expandUlh(Inst, true, IDLoc, Out, STI) ? MER_Fail : MER_Success; case Mips::Ulhu: - return expandUlh(Inst, false, IDLoc, Instructions) ? MER_Fail : MER_Success; + return expandUlh(Inst, false, IDLoc, Out, STI) ? MER_Fail : MER_Success; case Mips::Ulw: - return expandUlw(Inst, IDLoc, Instructions) ? MER_Fail : MER_Success; + return expandUlw(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; case Mips::NORImm: - return expandAliasImmediate(Inst, IDLoc, Instructions) ? MER_Fail - : MER_Success; + return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; case Mips::ADDi: case Mips::ADDiu: case Mips::SLTi: @@ -2099,8 +2088,8 @@ int64_t ImmValue = Inst.getOperand(2).getImm(); if (isInt<16>(ImmValue)) return MER_NotAMacro; - return expandAliasImmediate(Inst, IDLoc, Instructions) ? MER_Fail - : MER_Success; + return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail + : MER_Success; } return MER_NotAMacro; case Mips::ANDi: @@ -2111,34 +2100,30 @@ int64_t ImmValue = Inst.getOperand(2).getImm(); if (isUInt<16>(ImmValue)) return MER_NotAMacro; - return expandAliasImmediate(Inst, IDLoc, Instructions) ? MER_Fail - : MER_Success; + return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail + : MER_Success; } return MER_NotAMacro; case Mips::ROL: case Mips::ROR: - return expandRotation(Inst, IDLoc, Instructions) ? MER_Fail - : MER_Success; + return expandRotation(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; case Mips::ROLImm: case Mips::RORImm: - return expandRotationImm(Inst, IDLoc, Instructions) ? MER_Fail - : MER_Success; + return expandRotationImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; case Mips::DROL: case Mips::DROR: - return expandDRotation(Inst, IDLoc, Instructions) ? MER_Fail - : MER_Success; + return expandDRotation(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; case Mips::DROLImm: case Mips::DRORImm: - return expandDRotationImm(Inst, IDLoc, Instructions) ? MER_Fail - : MER_Success; + return expandDRotationImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; case Mips::ABSMacro: - return expandAbs(Inst, IDLoc, Instructions) ? MER_Fail - : MER_Success; + return expandAbs(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; } } bool MipsAsmParser::expandJalWithRegs(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl &Instructions) { + MCStreamer &Out, + const MCSubtargetInfo *STI) { // Create a JALR instruction which is going to replace the pseudo-JAL. MCInst JalrInst; JalrInst.setLoc(IDLoc); @@ -2168,13 +2153,13 @@ const MCOperand SecondRegOp = Inst.getOperand(1); JalrInst.addOperand(SecondRegOp); } - Instructions.push_back(JalrInst); + Out.EmitInstruction(JalrInst, *STI); // If .set reorder is active and branch instruction has a delay slot, // emit a NOP after it. const MCInstrDesc &MCID = getInstDesc(JalrInst.getOpcode()); if (MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder()) { - createNop(hasShortDelaySlot(JalrInst.getOpcode()), IDLoc, Instructions); + createNop(hasShortDelaySlot(JalrInst.getOpcode()), IDLoc, Out, STI); } return false; @@ -2200,8 +2185,8 @@ /// @param Instructions The instructions emitted by this expansion. bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg, unsigned SrcReg, bool Is32BitImm, - bool IsAddress, SMLoc IDLoc, - SmallVectorImpl &Instructions) { + bool IsAddress, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI) { if (!Is32BitImm && !isGP64bit()) { Error(IDLoc, "instruction requires a 64-bit architecture"); return true; @@ -2245,11 +2230,11 @@ // traditional assembler behaviour. N32 would normally use addiu for both // integers and addresses. if (IsAddress && !Is32BitImm) { - emitRRI(Mips::DADDiu, DstReg, SrcReg, ImmValue, IDLoc, Instructions); + emitRRI(Mips::DADDiu, DstReg, SrcReg, ImmValue, IDLoc, Out, STI); return false; } - emitRRI(Mips::ADDiu, DstReg, SrcReg, ImmValue, IDLoc, Instructions); + emitRRI(Mips::ADDiu, DstReg, SrcReg, ImmValue, IDLoc, Out, STI); return false; } @@ -2261,9 +2246,9 @@ return true; } - emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, Instructions); + emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, Out, STI); if (UseSrcReg) - emitRRR(ABI.GetPtrAdduOp(), DstReg, TmpReg, SrcReg, IDLoc, Instructions); + emitRRR(ABI.GetPtrAdduOp(), DstReg, TmpReg, SrcReg, IDLoc, Out, STI); return false; } @@ -2277,29 +2262,29 @@ // Traditional behaviour seems to special case this particular value. It's // not clear why other masks are handled differently. if (ImmValue == 0xffffffff) { - emitRI(Mips::LUi, TmpReg, 0xffff, IDLoc, Instructions); - emitRRI(Mips::DSRL32, TmpReg, TmpReg, 0, IDLoc, Instructions); + emitRI(Mips::LUi, TmpReg, 0xffff, IDLoc, Out, STI); + emitRRI(Mips::DSRL32, TmpReg, TmpReg, 0, IDLoc, Out, STI); if (UseSrcReg) - emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, Instructions); + emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, Out, STI); return false; } // Expand to an ORi instead of a LUi to avoid sign-extending into the // upper 32 bits. - emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits31To16, IDLoc, Instructions); - emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, Instructions); + emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits31To16, IDLoc, Out, STI); + emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, Out, STI); if (Bits15To0) - emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, Instructions); + emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, Out, STI); if (UseSrcReg) - emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, Instructions); + emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, Out, STI); return false; } - emitRI(Mips::LUi, TmpReg, Bits31To16, IDLoc, Instructions); + emitRI(Mips::LUi, TmpReg, Bits31To16, IDLoc, Out, STI); if (Bits15To0) - emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, Instructions); + emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, Out, STI); if (UseSrcReg) - emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, Instructions); + emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, Out, STI); return false; } @@ -2315,11 +2300,11 @@ unsigned LastSet = findLastSet((uint64_t)ImmValue); unsigned ShiftAmount = FirstSet - (15 - (LastSet - FirstSet)); uint16_t Bits = (ImmValue >> ShiftAmount) & 0xffff; - emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits, IDLoc, Instructions); - emitRRI(Mips::DSLL, TmpReg, TmpReg, ShiftAmount, IDLoc, Instructions); + emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits, IDLoc, Out, STI); + emitRRI(Mips::DSLL, TmpReg, TmpReg, ShiftAmount, IDLoc, Out, STI); if (UseSrcReg) - emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, Instructions); + emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, Out, STI); return false; } @@ -2332,7 +2317,7 @@ // Load bits 32-63 of ImmValue into bits 0-31 of the temporary register. if (loadImmediate(ImmValue >> 32, TmpReg, Mips::NoRegister, true, false, - IDLoc, Instructions)) + IDLoc, Out, STI)) return false; // Shift and accumulate into the register. If a 16-bit chunk is zero, then @@ -2343,8 +2328,8 @@ if (ImmChunk != 0) { emitAppropriateDSLL(TmpReg, TmpReg, ShiftCarriedForwards, IDLoc, - Instructions); - emitRRI(Mips::ORi, TmpReg, TmpReg, ImmChunk, IDLoc, Instructions); + Out, STI); + emitRRI(Mips::ORi, TmpReg, TmpReg, ImmChunk, IDLoc, Out, STI); ShiftCarriedForwards = 0; } @@ -2355,23 +2340,23 @@ // Finish any remaining shifts left by trailing zeros. if (ShiftCarriedForwards) emitAppropriateDSLL(TmpReg, TmpReg, ShiftCarriedForwards, IDLoc, - Instructions); + Out, STI); if (UseSrcReg) - emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, Instructions); + emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, Out, STI); return false; } bool MipsAsmParser::expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc, - SmallVectorImpl &Instructions) { + MCStreamer &Out, const MCSubtargetInfo *STI) { const MCOperand &ImmOp = Inst.getOperand(1); assert(ImmOp.isImm() && "expected immediate operand kind"); const MCOperand &DstRegOp = Inst.getOperand(0); assert(DstRegOp.isReg() && "expected register operand kind"); if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister, - Is32BitImm, false, IDLoc, Instructions)) + Is32BitImm, false, IDLoc, Out, STI)) return true; return false; @@ -2380,7 +2365,8 @@ bool MipsAsmParser::expandLoadAddress(unsigned DstReg, unsigned BaseReg, const MCOperand &Offset, bool Is32BitAddress, SMLoc IDLoc, - SmallVectorImpl &Instructions) { + MCStreamer &Out, + const MCSubtargetInfo *STI) { // la can't produce a usable address when addresses are 64-bit. if (Is32BitAddress && ABI.ArePtrs64bit()) { // FIXME: Demote this to a warning and continue as if we had 'dla' instead. @@ -2399,7 +2385,7 @@ if (!Offset.isImm()) return loadAndAddSymbolAddress(Offset.getExpr(), DstReg, BaseReg, - Is32BitAddress, IDLoc, Instructions); + Is32BitAddress, IDLoc, Out, STI); if (!ABI.ArePtrs64bit()) { // Continue as if we had 'la' whether we had 'la' or 'dla'. @@ -2407,12 +2393,14 @@ } return loadImmediate(Offset.getImm(), DstReg, BaseReg, Is32BitAddress, true, - IDLoc, Instructions); + IDLoc, Out, STI); } -bool MipsAsmParser::loadAndAddSymbolAddress( - const MCExpr *SymExpr, unsigned DstReg, unsigned SrcReg, bool Is32BitSym, - SMLoc IDLoc, SmallVectorImpl &Instructions) { +bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr, + unsigned DstReg, unsigned SrcReg, + bool Is32BitSym, SMLoc IDLoc, + MCStreamer &Out, + const MCSubtargetInfo *STI) { warnIfNoMacro(IDLoc); const MCExpr *Symbol = cast(SymExpr); @@ -2447,17 +2435,17 @@ // dsll $at, $at, 16 // daddiu $at, $at, %lo(sym) // daddu $rd, $at, $rd - emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HighestExpr), IDLoc, - Instructions); + emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HighestExpr), IDLoc, Out, + STI); emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(HigherExpr), - IDLoc, Instructions); - emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, Instructions); + IDLoc, Out, STI); + emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, Out, STI); emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(HiExpr), IDLoc, - Instructions); - emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, Instructions); + Out, STI); + emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, Out, STI); emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(LoExpr), IDLoc, - Instructions); - emitRRR(Mips::DADDu, DstReg, ATReg, SrcReg, IDLoc, Instructions); + Out, STI); + emitRRR(Mips::DADDu, DstReg, ATReg, SrcReg, IDLoc, Out, STI); return false; } @@ -2470,18 +2458,17 @@ // dsll32 $rd, $rd, 0 // daddu $rd, $rd, $at // (daddu $rd, $rd, $rs) - emitRX(Mips::LUi, DstReg, MCOperand::createExpr(HighestExpr), IDLoc, - Instructions); - emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HiExpr), IDLoc, - Instructions); + emitRX(Mips::LUi, DstReg, MCOperand::createExpr(HighestExpr), IDLoc, Out, + STI); + emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HiExpr), IDLoc, Out, STI); emitRRX(Mips::DADDiu, DstReg, DstReg, MCOperand::createExpr(HigherExpr), - IDLoc, Instructions); + IDLoc, Out, STI); emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(LoExpr), IDLoc, - Instructions); - emitRRI(Mips::DSLL32, DstReg, DstReg, 0, IDLoc, Instructions); - emitRRR(Mips::DADDu, DstReg, DstReg, ATReg, IDLoc, Instructions); + Out, STI); + emitRRI(Mips::DSLL32, DstReg, DstReg, 0, IDLoc, Out, STI); + emitRRR(Mips::DADDu, DstReg, DstReg, ATReg, IDLoc, Out, STI); if (UseSrcReg) - emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, Instructions); + emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, Out, STI); return false; } @@ -2506,12 +2493,12 @@ TmpReg = ATReg; } - emitRX(Mips::LUi, TmpReg, MCOperand::createExpr(HiExpr), IDLoc, Instructions); + emitRX(Mips::LUi, TmpReg, MCOperand::createExpr(HiExpr), IDLoc, Out, STI); emitRRX(Mips::ADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr), IDLoc, - Instructions); + Out, STI); if (UseSrcReg) - emitRRR(Mips::ADDu, DstReg, TmpReg, SrcReg, IDLoc, Instructions); + emitRRR(Mips::ADDu, DstReg, TmpReg, SrcReg, IDLoc, Out, STI); else assert( getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, TmpReg)); @@ -2519,8 +2506,9 @@ return false; } -bool MipsAsmParser::expandUncondBranchMMPseudo( - MCInst &Inst, SMLoc IDLoc, SmallVectorImpl &Instructions) { +bool MipsAsmParser::expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc, + MCStreamer &Out, + const MCSubtargetInfo *STI) { assert(getInstDesc(Inst.getOpcode()).getNumOperands() == 1 && "unexpected number of operands"); @@ -2550,19 +2538,19 @@ Inst.addOperand(MCOperand::createImm(Offset.getImm())); } } - Instructions.push_back(Inst); + Out.EmitInstruction(Inst, *STI); // If .set reorder is active and branch instruction has a delay slot, // emit a NOP after it. const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode()); if (MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder()) - createNop(true, IDLoc, Instructions); + createNop(true, IDLoc, Out, STI); return false; } -bool MipsAsmParser::expandBranchImm(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl &Instructions) { +bool MipsAsmParser::expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI) { const MCOperand &DstRegOp = Inst.getOperand(0); assert(DstRegOp.isReg() && "expected register operand kind"); @@ -2588,8 +2576,8 @@ int64_t ImmValue = ImmOp.getImm(); if (ImmValue == 0) - emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, MemOffsetOp, IDLoc, - Instructions); + emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, MemOffsetOp, IDLoc, Out, + STI); else { warnIfNoMacro(IDLoc); @@ -2598,17 +2586,17 @@ return true; if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, !isGP64bit(), true, - IDLoc, Instructions)) + IDLoc, Out, STI)) return true; - emitRRX(OpCode, DstRegOp.getReg(), ATReg, MemOffsetOp, IDLoc, Instructions); + emitRRX(OpCode, DstRegOp.getReg(), ATReg, MemOffsetOp, IDLoc, Out, STI); } return false; } -void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl &Instructions, - bool isLoad, bool isImmOpnd) { +void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI, bool isLoad, + bool isImmOpnd) { MCOperand HiOperand, LoOperand; unsigned TmpRegNum; // 1st operand is either the source or destination register. @@ -2671,18 +2659,18 @@ return; } - emitRX(Mips::LUi, TmpRegNum, HiOperand, IDLoc, Instructions); + emitRX(Mips::LUi, TmpRegNum, HiOperand, IDLoc, Out, STI); // Add temp register to base. if (BaseRegNum != Mips::ZERO) - emitRRR(Mips::ADDu, TmpRegNum, TmpRegNum, BaseRegNum, IDLoc, Instructions); + emitRRR(Mips::ADDu, TmpRegNum, TmpRegNum, BaseRegNum, IDLoc, Out, STI); // And finally, create original instruction with low part // of offset and new base. - emitRRX(Inst.getOpcode(), RegOpNum, TmpRegNum, LoOperand, IDLoc, Instructions); + emitRRX(Inst.getOpcode(), RegOpNum, TmpRegNum, LoOperand, IDLoc, Out, STI); } -bool -MipsAsmParser::expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl &Instructions) { +bool MipsAsmParser::expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc, + MCStreamer &Out, + const MCSubtargetInfo *STI) { unsigned OpNum = Inst.getNumOperands(); unsigned Opcode = Inst.getOpcode(); unsigned NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM32_MM : Mips::LWM32_MM; @@ -2705,12 +2693,13 @@ } Inst.setOpcode(NewOpcode); - Instructions.push_back(Inst); + Out.EmitInstruction(Inst, *STI); return false; } bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl &Instructions) { + MCStreamer &Out, + const MCSubtargetInfo *STI) { bool EmittedNoMacroWarning = false; unsigned PseudoOpcode = Inst.getOpcode(); unsigned SrcReg = Inst.getOperand(0).getReg(); @@ -2785,7 +2774,7 @@ } if (loadImmediate(TrgOp.getImm(), TrgReg, Mips::NoRegister, !isGP64bit(), - false, IDLoc, Instructions)) + false, IDLoc, Out, STI)) return true; } @@ -2846,36 +2835,36 @@ // code in some circumstances. if (PseudoOpcode == Mips::BLT) { emitRX(Mips::BLTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr), IDLoc, - Instructions); + Out, STI); return false; } if (PseudoOpcode == Mips::BLE) { emitRX(Mips::BLEZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr), IDLoc, - Instructions); + Out, STI); Warning(IDLoc, "branch is always taken"); return false; } if (PseudoOpcode == Mips::BGE) { emitRX(Mips::BGEZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr), IDLoc, - Instructions); + Out, STI); Warning(IDLoc, "branch is always taken"); return false; } if (PseudoOpcode == Mips::BGT) { emitRX(Mips::BGTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr), IDLoc, - Instructions); + Out, STI); return false; } if (PseudoOpcode == Mips::BGTU) { emitRRX(Mips::BNE, Mips::ZERO, Mips::ZERO, - MCOperand::createExpr(OffsetExpr), IDLoc, Instructions); + MCOperand::createExpr(OffsetExpr), IDLoc, Out, STI); return false; } if (AcceptsEquality) { // If both registers are $0 and the pseudo-branch accepts equality, it // will always be taken, so we emit an unconditional branch. emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO, - MCOperand::createExpr(OffsetExpr), IDLoc, Instructions); + MCOperand::createExpr(OffsetExpr), IDLoc, Out, STI); Warning(IDLoc, "branch is always taken"); return false; } @@ -2900,7 +2889,7 @@ // branch. // This only applies to unsigned pseudo-branches. emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO, - MCOperand::createExpr(OffsetExpr), IDLoc, Instructions); + MCOperand::createExpr(OffsetExpr), IDLoc, Out, STI); Warning(IDLoc, "branch is always taken"); return false; } @@ -2919,7 +2908,7 @@ // AcceptsEquality variable to decide when to emit the BEQZ. emitRRX(AcceptsEquality ? Mips::BEQ : Mips::BNE, IsSrcRegZero ? TrgReg : SrcReg, Mips::ZERO, - MCOperand::createExpr(OffsetExpr), IDLoc, Instructions); + MCOperand::createExpr(OffsetExpr), IDLoc, Out, STI); return false; } // If we have a signed pseudo-branch and one of the registers is $0, @@ -2927,7 +2916,7 @@ // to use in the switch statement above. emitRX(IsSrcRegZero ? ZeroSrcOpcode : ZeroTrgOpcode, IsSrcRegZero ? TrgReg : SrcReg, MCOperand::createExpr(OffsetExpr), - IDLoc, Instructions); + IDLoc, Out, STI); return false; } @@ -2957,18 +2946,18 @@ // instead of SLT. emitRRR(IsUnsigned ? Mips::SLTu : Mips::SLT, ATRegNum, ReverseOrderSLT ? TrgReg : SrcReg, ReverseOrderSLT ? SrcReg : TrgReg, - IDLoc, Instructions); + IDLoc, Out, STI); emitRRX(IsLikely ? (AcceptsEquality ? Mips::BEQL : Mips::BNEL) : (AcceptsEquality ? Mips::BEQ : Mips::BNE), ATRegNum, Mips::ZERO, MCOperand::createExpr(OffsetExpr), IDLoc, - Instructions); + Out, STI); return false; } -bool MipsAsmParser::expandDiv(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl &Instructions, - const bool IsMips64, const bool Signed) { +bool MipsAsmParser::expandDiv(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI, const bool IsMips64, + const bool Signed) { if (hasMips32r6()) { Error(IDLoc, "instruction not supported on mips32r6 or mips64r6"); return false; @@ -3002,15 +2991,15 @@ if (IsMips64) { if (Signed && (RtReg == Mips::ZERO || RtReg == Mips::ZERO_64)) { if (UseTraps) { - emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, Instructions); + emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, Out, STI); return false; } - emitII(Mips::BREAK, 0x7, 0, IDLoc, Instructions); + emitII(Mips::BREAK, 0x7, 0, IDLoc, Out, STI); return false; } } else { - emitRR(DivOp, RsReg, RtReg, IDLoc, Instructions); + emitRR(DivOp, RsReg, RtReg, IDLoc, Out, STI); return false; } } @@ -3019,11 +3008,11 @@ Warning(IDLoc, "division by zero"); if (Signed) { if (UseTraps) { - emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, Instructions); + emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, Out, STI); return false; } - emitII(Mips::BREAK, 0x7, 0, IDLoc, Instructions); + emitII(Mips::BREAK, 0x7, 0, IDLoc, Out, STI); return false; } } @@ -3035,22 +3024,21 @@ if (UseTraps) { BranchTarget = IsMips64 ? 12 : 8; - emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, Instructions); + emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, Out, STI); } else { BranchTarget = IsMips64 ? 20 : 16; BranchTargetNoTraps = 8; // Branch to the li instruction. - emitRRI(Mips::BNE, RtReg, ZeroReg, BranchTargetNoTraps, IDLoc, - Instructions); + emitRRI(Mips::BNE, RtReg, ZeroReg, BranchTargetNoTraps, IDLoc, Out, STI); } - emitRR(DivOp, RsReg, RtReg, IDLoc, Instructions); + emitRR(DivOp, RsReg, RtReg, IDLoc, Out, STI); if (!UseTraps) - emitII(Mips::BREAK, 0x7, 0, IDLoc, Instructions); + emitII(Mips::BREAK, 0x7, 0, IDLoc, Out, STI); if (!Signed) { - emitR(Mips::MFLO, RsReg, IDLoc, Instructions); + emitR(Mips::MFLO, RsReg, IDLoc, Out, STI); return false; } @@ -3058,33 +3046,33 @@ if (!ATReg) return true; - emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, Instructions); + emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, Out, STI); if (IsMips64) { // Branch to the mflo instruction. - emitRRI(Mips::BNE, RtReg, ATReg, BranchTarget, IDLoc, Instructions); - emitRRI(Mips::ADDiu, ATReg, ZeroReg, 1, IDLoc, Instructions); - emitRRI(Mips::DSLL32, ATReg, ATReg, 0x1f, IDLoc, Instructions); + emitRRI(Mips::BNE, RtReg, ATReg, BranchTarget, IDLoc, Out, STI); + emitRRI(Mips::ADDiu, ATReg, ZeroReg, 1, IDLoc, Out, STI); + emitRRI(Mips::DSLL32, ATReg, ATReg, 0x1f, IDLoc, Out, STI); } else { // Branch to the mflo instruction. - emitRRI(Mips::BNE, RtReg, ATReg, BranchTarget, IDLoc, Instructions); - emitRI(Mips::LUi, ATReg, (uint16_t)0x8000, IDLoc, Instructions); + emitRRI(Mips::BNE, RtReg, ATReg, BranchTarget, IDLoc, Out, STI); + emitRI(Mips::LUi, ATReg, (uint16_t)0x8000, IDLoc, Out, STI); } if (UseTraps) - emitRRI(Mips::TEQ, RsReg, ATReg, 0x6, IDLoc, Instructions); + emitRRI(Mips::TEQ, RsReg, ATReg, 0x6, IDLoc, Out, STI); else { // Branch to the mflo instruction. - emitRRI(Mips::BNE, RsReg, ATReg, BranchTargetNoTraps, IDLoc, Instructions); - emitRRI(Mips::SLL, ZeroReg, ZeroReg, 0, IDLoc, Instructions); - emitII(Mips::BREAK, 0x6, 0, IDLoc, Instructions); + emitRRI(Mips::BNE, RsReg, ATReg, BranchTargetNoTraps, IDLoc, Out, STI); + emitRRI(Mips::SLL, ZeroReg, ZeroReg, 0, IDLoc, Out, STI); + emitII(Mips::BREAK, 0x6, 0, IDLoc, Out, STI); } - emitR(Mips::MFLO, RsReg, IDLoc, Instructions); + emitR(Mips::MFLO, RsReg, IDLoc, Out, STI); return false; } bool MipsAsmParser::expandTrunc(MCInst &Inst, bool IsDouble, bool Is64FPU, - SMLoc IDLoc, - SmallVectorImpl &Instructions) { + SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI) { assert(Inst.getNumOperands() == 3 && "Invalid operand count"); assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && @@ -3098,30 +3086,30 @@ unsigned ATReg = getATReg(IDLoc); if (!ATReg) return true; - emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, Instructions); - emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, Instructions); - createNop(false, IDLoc, Instructions); - emitRRI(Mips::ORi, ATReg, ThirdReg, 0x3, IDLoc, Instructions); - emitRRI(Mips::XORi, ATReg, ATReg, 0x2, IDLoc, Instructions); - emitRR(Mips::CTC1, Mips::RA, ATReg, IDLoc, Instructions); - createNop(false, IDLoc, Instructions); + emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, Out, STI); + emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, Out, STI); + createNop(false, IDLoc, Out, STI); + emitRRI(Mips::ORi, ATReg, ThirdReg, 0x3, IDLoc, Out, STI); + emitRRI(Mips::XORi, ATReg, ATReg, 0x2, IDLoc, Out, STI); + emitRR(Mips::CTC1, Mips::RA, ATReg, IDLoc, Out, STI); + createNop(false, IDLoc, Out, STI); emitRR(IsDouble ? (Is64FPU ? Mips::CVT_W_D64 : Mips::CVT_W_D32) : Mips::CVT_W_S, - FirstReg, SecondReg, IDLoc, Instructions); - emitRR(Mips::CTC1, Mips::RA, ThirdReg, IDLoc, Instructions); - createNop(false, IDLoc, Instructions); + FirstReg, SecondReg, IDLoc, Out, STI); + emitRR(Mips::CTC1, Mips::RA, ThirdReg, IDLoc, Out, STI); + createNop(false, IDLoc, Out, STI); return false; } emitRR(IsDouble ? (Is64FPU ? Mips::TRUNC_W_D64 : Mips::TRUNC_W_D32) : Mips::TRUNC_W_S, - FirstReg, SecondReg, IDLoc, Instructions); + FirstReg, SecondReg, IDLoc, Out, STI); return false; } bool MipsAsmParser::expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc, - SmallVectorImpl &Instructions) { + MCStreamer &Out, const MCSubtargetInfo *STI) { if (hasMips32r6() || hasMips64r6()) { Error(IDLoc, "instruction not supported on mips32r6 or mips64r6"); return false; @@ -3156,7 +3144,7 @@ LoadedOffsetInAT = true; if (loadImmediate(OffsetValue, ATReg, Mips::NoRegister, !ABI.ArePtrs64bit(), - true, IDLoc, Instructions)) + true, IDLoc, Out, STI)) return true; // NOTE: We do this (D)ADDu here instead of doing it in loadImmediate() @@ -3166,7 +3154,7 @@ // NOTE: If there is no source register specified in the ULHU, the parser // will interpret it as $0. if (SrcReg != Mips::ZERO && SrcReg != Mips::ZERO_64) - createAddu(ATReg, ATReg, SrcReg, ABI.ArePtrs64bit(), Instructions); + createAddu(ATReg, ATReg, SrcReg, ABI.ArePtrs64bit(), Out, STI); } unsigned FirstLbuDstReg = LoadedOffsetInAT ? DstReg : ATReg; @@ -3185,20 +3173,20 @@ unsigned SllReg = LoadedOffsetInAT ? DstReg : ATReg; emitRRI(Signed ? Mips::LB : Mips::LBu, FirstLbuDstReg, LbuSrcReg, - FirstLbuOffset, IDLoc, Instructions); + FirstLbuOffset, IDLoc, Out, STI); - emitRRI(Mips::LBu, SecondLbuDstReg, LbuSrcReg, SecondLbuOffset, IDLoc, - Instructions); + emitRRI(Mips::LBu, SecondLbuDstReg, LbuSrcReg, SecondLbuOffset, IDLoc, Out, + STI); - emitRRI(Mips::SLL, SllReg, SllReg, 8, IDLoc, Instructions); + emitRRI(Mips::SLL, SllReg, SllReg, 8, IDLoc, Out, STI); - emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, Instructions); + emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, Out, STI); return false; } -bool MipsAsmParser::expandUlw(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl &Instructions) { +bool MipsAsmParser::expandUlw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI) { if (hasMips32r6() || hasMips64r6()) { Error(IDLoc, "instruction not supported on mips32r6 or mips64r6"); return false; @@ -3230,7 +3218,7 @@ warnIfNoMacro(IDLoc); if (loadImmediate(OffsetValue, ATReg, Mips::NoRegister, !ABI.ArePtrs64bit(), - true, IDLoc, Instructions)) + true, IDLoc, Out, STI)) return true; // NOTE: We do this (D)ADDu here instead of doing it in loadImmediate() @@ -3240,7 +3228,7 @@ // NOTE: If there is no source register specified in the ULW, the parser // will interpret it as $0. if (SrcReg != Mips::ZERO && SrcReg != Mips::ZERO_64) - createAddu(ATReg, ATReg, SrcReg, ABI.ArePtrs64bit(), Instructions); + createAddu(ATReg, ATReg, SrcReg, ABI.ArePtrs64bit(), Out, STI); } unsigned FinalSrcReg = LoadedOffsetInAT ? ATReg : SrcReg; @@ -3253,17 +3241,18 @@ RightLoadOffset = LoadedOffsetInAT ? 3 : (OffsetValue + 3); } - emitRRI(Mips::LWL, DstRegOp.getReg(), FinalSrcReg, LeftLoadOffset, IDLoc, - Instructions); + emitRRI(Mips::LWL, DstRegOp.getReg(), FinalSrcReg, LeftLoadOffset, IDLoc, Out, + STI); emitRRI(Mips::LWR, DstRegOp.getReg(), FinalSrcReg, RightLoadOffset, IDLoc, - Instructions); + Out, STI); return false; } bool MipsAsmParser::expandAliasImmediate(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl &Instructions) { + MCStreamer &Out, + const MCSubtargetInfo *STI) { assert (Inst.getNumOperands() == 3 && "Invalid operand count"); assert (Inst.getOperand(0).isReg() && @@ -3288,7 +3277,7 @@ DstReg = ATReg; } - if (!loadImmediate(ImmValue, DstReg, Mips::NoRegister, Is32Bit, false, Inst.getLoc(), Instructions)) { + if (!loadImmediate(ImmValue, DstReg, Mips::NoRegister, Is32Bit, false, Inst.getLoc(), Out, STI)) { switch (FinalOpcode) { default: llvm_unreachable("unimplemented expansion"); @@ -3319,17 +3308,16 @@ } if (FinalDstReg == Mips::NoRegister) - emitRRR(FinalOpcode, DstReg, DstReg, SrcReg, IDLoc, Instructions); + emitRRR(FinalOpcode, DstReg, DstReg, SrcReg, IDLoc, Out, STI); else - emitRRR(FinalOpcode, FinalDstReg, FinalDstReg, DstReg, IDLoc, - Instructions); + emitRRR(FinalOpcode, FinalDstReg, FinalDstReg, DstReg, IDLoc, Out, STI); return false; } return true; } -bool MipsAsmParser::expandRotation(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl &Instructions) { +bool MipsAsmParser::expandRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI) { unsigned ATReg = Mips::NoRegister; unsigned DReg = Inst.getOperand(0).getReg(); unsigned SReg = Inst.getOperand(1).getReg(); @@ -3348,13 +3336,13 @@ } if (Inst.getOpcode() == Mips::ROL) { - emitRRR(Mips::SUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), Instructions); - emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), Instructions); + emitRRR(Mips::SUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), Out, STI); + emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), Out, STI); return false; } if (Inst.getOpcode() == Mips::ROR) { - emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), Instructions); + emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), Out, STI); return false; } @@ -3380,10 +3368,10 @@ if (!ATReg) return true; - emitRRR(Mips::SUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), Instructions); - emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), Instructions); - emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), Instructions); - emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), Instructions); + emitRRR(Mips::SUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), Out, STI); + emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), Out, STI); + emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), Out, STI); + emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), Out, STI); return false; } @@ -3392,7 +3380,8 @@ } bool MipsAsmParser::expandRotationImm(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl &Instructions) { + MCStreamer &Out, + const MCSubtargetInfo *STI) { unsigned ATReg = Mips::NoRegister; unsigned DReg = Inst.getOperand(0).getReg(); @@ -3409,12 +3398,12 @@ uint64_t ShiftValue = ImmValue; if (ImmValue != 0) ShiftValue = MaxShift - ImmValue; - emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), Instructions); + emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), Out, STI); return false; } if (Inst.getOpcode() == Mips::RORImm) { - emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), Instructions); + emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), Out, STI); return false; } @@ -3424,7 +3413,7 @@ if (hasMips32()) { if (ImmValue == 0) { - emitRRI(Mips::SRL, DReg, SReg, 0, Inst.getLoc(), Instructions); + emitRRI(Mips::SRL, DReg, SReg, 0, Inst.getLoc(), Out, STI); return false; } @@ -3445,9 +3434,9 @@ if (!ATReg) return true; - emitRRI(FirstShift, ATReg, SReg, ImmValue, Inst.getLoc(), Instructions); - emitRRI(SecondShift, DReg, SReg, 32 - ImmValue, Inst.getLoc(), Instructions); - emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), Instructions); + emitRRI(FirstShift, ATReg, SReg, ImmValue, Inst.getLoc(), Out, STI); + emitRRI(SecondShift, DReg, SReg, 32 - ImmValue, Inst.getLoc(), Out, STI); + emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), Out, STI); return false; } @@ -3455,8 +3444,8 @@ return true; } -bool MipsAsmParser::expandDRotation(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl &Instructions) { +bool MipsAsmParser::expandDRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI) { unsigned ATReg = Mips::NoRegister; unsigned DReg = Inst.getOperand(0).getReg(); @@ -3476,13 +3465,13 @@ } if (Inst.getOpcode() == Mips::DROL) { - emitRRR(Mips::DSUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), Instructions); - emitRRR(Mips::DROTRV, DReg, SReg, TmpReg, Inst.getLoc(), Instructions); + emitRRR(Mips::DSUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), Out, STI); + emitRRR(Mips::DROTRV, DReg, SReg, TmpReg, Inst.getLoc(), Out, STI); return false; } if (Inst.getOpcode() == Mips::DROR) { - emitRRR(Mips::DROTRV, DReg, SReg, TReg, Inst.getLoc(), Instructions); + emitRRR(Mips::DROTRV, DReg, SReg, TReg, Inst.getLoc(), Out, STI); return false; } @@ -3508,10 +3497,10 @@ if (!ATReg) return true; - emitRRR(Mips::DSUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), Instructions); - emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), Instructions); - emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), Instructions); - emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), Instructions); + emitRRR(Mips::DSUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), Out, STI); + emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), Out, STI); + emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), Out, STI); + emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), Out, STI); return false; } @@ -3520,7 +3509,8 @@ } bool MipsAsmParser::expandDRotationImm(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl &Instructions) { + MCStreamer &Out, + const MCSubtargetInfo *STI) { unsigned ATReg = Mips::NoRegister; unsigned DReg = Inst.getOperand(0).getReg(); @@ -3555,7 +3545,7 @@ if (Inst.getOpcode() == Mips::DROLImm) ShiftValue = (32 - ImmValue % 32) % 32; - emitRRI(FinalOpcode, DReg, SReg, ShiftValue, Inst.getLoc(), Instructions); + emitRRI(FinalOpcode, DReg, SReg, ShiftValue, Inst.getLoc(), Out, STI); return false; } @@ -3563,7 +3553,7 @@ if (hasMips64()) { if (ImmValue == 0) { - emitRRI(Mips::DSRL, DReg, SReg, 0, Inst.getLoc(), Instructions); + emitRRI(Mips::DSRL, DReg, SReg, 0, Inst.getLoc(), Out, STI); return false; } @@ -3604,9 +3594,9 @@ if (!ATReg) return true; - emitRRI(FirstShift, ATReg, SReg, ImmValue % 32, Inst.getLoc(), Instructions); - emitRRI(SecondShift, DReg, SReg, (32 - ImmValue % 32) % 32, Inst.getLoc(), Instructions); - emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), Instructions); + emitRRI(FirstShift, ATReg, SReg, ImmValue % 32, Inst.getLoc(), Out, STI); + emitRRI(SecondShift, DReg, SReg, (32 - ImmValue % 32) % 32, Inst.getLoc(), Out, STI); + emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), Out, STI); return false; } @@ -3614,40 +3604,40 @@ return true; } -bool MipsAsmParser::expandAbs(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl &Instructions) { +bool MipsAsmParser::expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI) { unsigned FirstRegOp = Inst.getOperand(0).getReg(); unsigned SecondRegOp = Inst.getOperand(1).getReg(); - emitRI(Mips::BGEZ, SecondRegOp, 8, IDLoc, Instructions); + emitRI(Mips::BGEZ, SecondRegOp, 8, IDLoc, Out, STI); if (FirstRegOp != SecondRegOp) - emitRRR(Mips::ADDu, FirstRegOp, SecondRegOp, Mips::ZERO, IDLoc, Instructions); + emitRRR(Mips::ADDu, FirstRegOp, SecondRegOp, Mips::ZERO, IDLoc, Out, STI); else - createNop(false, IDLoc, Instructions); - emitRRR(Mips::SUB, FirstRegOp, Mips::ZERO, SecondRegOp, IDLoc, Instructions); + createNop(false, IDLoc, Out, STI); + emitRRR(Mips::SUB, FirstRegOp, Mips::ZERO, SecondRegOp, IDLoc, Out, STI); return false; } void MipsAsmParser::createNop(bool hasShortDelaySlot, SMLoc IDLoc, - SmallVectorImpl &Instructions) { + MCStreamer &Out, const MCSubtargetInfo *STI) { if (hasShortDelaySlot) - emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, Instructions); + emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, Out, STI); else - emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, Instructions); + emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, Out, STI); } void MipsAsmParser::createAddu(unsigned DstReg, unsigned SrcReg, - unsigned TrgReg, bool Is64Bit, - SmallVectorImpl &Instructions) { + unsigned TrgReg, bool Is64Bit, MCStreamer &Out, + const MCSubtargetInfo *STI) { emitRRR(Is64Bit ? Mips::DADDu : Mips::ADDu, DstReg, SrcReg, TrgReg, SMLoc(), - Instructions); + Out, STI); } -void MipsAsmParser::createCpRestoreMemOp( - bool IsLoad, int StackOffset, SMLoc IDLoc, - SmallVectorImpl &Instructions) { +void MipsAsmParser::createCpRestoreMemOp(bool IsLoad, int StackOffset, + SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI) { // If the offset can not fit into 16 bits, we need to expand. if (!isInt<16>(StackOffset)) { MCInst MemInst; @@ -3655,12 +3645,12 @@ MemInst.addOperand(MCOperand::createReg(Mips::GP)); MemInst.addOperand(MCOperand::createReg(Mips::SP)); MemInst.addOperand(MCOperand::createImm(StackOffset)); - expandMemInst(MemInst, IDLoc, Instructions, IsLoad, true /*HasImmOpnd*/); + expandMemInst(MemInst, IDLoc, Out, STI, IsLoad, true /*HasImmOpnd*/); return; } emitRRI(IsLoad ? Mips::LW : Mips::SW, Mips::GP, Mips::SP, StackOffset, IDLoc, - Instructions); + Out, STI); } unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) { @@ -3693,16 +3683,13 @@ bool MatchingInlineAsm) { MCInst Inst; - SmallVector Instructions; unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm); switch (MatchResult) { case Match_Success: { - if (processInstruction(Inst, IDLoc, Instructions)) + if (processInstruction(Inst, IDLoc, Out, STI)) return true; - for (unsigned i = 0; i < Instructions.size(); i++) - Out.EmitInstruction(Instructions[i], getSTI()); return false; } case Match_MissingFeature: @@ -5533,11 +5520,13 @@ } // Store the $gp on the stack. - SmallVector StoreInsts; - createCpRestoreMemOp(false /*IsLoad*/, CpRestoreOffset /*StackOffset*/, Loc, - StoreInsts); + if (getStreamer().isIntegratedAssemblerRequired()) { + const MCSubtargetInfo &STI = getSTI(); + createCpRestoreMemOp(false /*IsLoad*/, CpRestoreOffset /*StackOffset*/, Loc, + getStreamer(), &STI); + } - getTargetStreamer().emitDirectiveCpRestore(StoreInsts, CpRestoreOffset); + getTargetStreamer().emitDirectiveCpRestore(CpRestoreOffset); Parser.Lex(); // Consume the EndOfStatement. return false; } Index: lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp +++ lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp @@ -89,8 +89,7 @@ void MipsTargetStreamer::emitDirectiveSetDsp() { forbidModuleDirective(); } void MipsTargetStreamer::emitDirectiveSetNoDsp() { forbidModuleDirective(); } void MipsTargetStreamer::emitDirectiveCpLoad(unsigned RegNo) {} -void MipsTargetStreamer::emitDirectiveCpRestore( - SmallVector &StoreInsts, int Offset) { +void MipsTargetStreamer::emitDirectiveCpRestore(int Offset) { forbidModuleDirective(); } void MipsTargetStreamer::emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset, @@ -364,9 +363,8 @@ forbidModuleDirective(); } -void MipsTargetAsmStreamer::emitDirectiveCpRestore( - SmallVector &StoreInsts, int Offset) { - MipsTargetStreamer::emitDirectiveCpRestore(StoreInsts, Offset); +void MipsTargetAsmStreamer::emitDirectiveCpRestore(int Offset) { + MipsTargetStreamer::emitDirectiveCpRestore(Offset); OS << "\t.cprestore\t" << Offset << "\n"; } @@ -800,9 +798,8 @@ forbidModuleDirective(); } -void MipsTargetELFStreamer::emitDirectiveCpRestore( - SmallVector &StoreInsts, int Offset) { - MipsTargetStreamer::emitDirectiveCpRestore(StoreInsts, Offset); +void MipsTargetELFStreamer::emitDirectiveCpRestore(int Offset) { + MipsTargetStreamer::emitDirectiveCpRestore(Offset); // .cprestore offset // When PIC mode is enabled and the O32 ABI is used, this directive expands // to: @@ -814,8 +811,10 @@ if (!Pic || (getABI().IsN32() || getABI().IsN64())) return; +#if 0 for (const MCInst &Inst : StoreInsts) getStreamer().EmitInstruction(Inst, STI); +#endif } void MipsTargetELFStreamer::emitDirectiveCpsetup(unsigned RegNo, Index: lib/Target/Mips/MipsTargetStreamer.h =================================================================== --- lib/Target/Mips/MipsTargetStreamer.h +++ lib/Target/Mips/MipsTargetStreamer.h @@ -78,8 +78,7 @@ // PIC support virtual void emitDirectiveCpLoad(unsigned RegNo); - virtual void emitDirectiveCpRestore(SmallVector &StoreInsts, - int Offset); + virtual void emitDirectiveCpRestore(int Offset); virtual void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset, const MCSymbol &Sym, bool IsReg); virtual void emitDirectiveCpreturn(unsigned SaveLocation, @@ -193,8 +192,7 @@ // PIC support void emitDirectiveCpLoad(unsigned RegNo) override; - void emitDirectiveCpRestore(SmallVector &StoreInsts, - int Offset) override; + void emitDirectiveCpRestore(int Offset) override; void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset, const MCSymbol &Sym, bool IsReg) override; void emitDirectiveCpreturn(unsigned SaveLocation, @@ -246,8 +244,7 @@ // PIC support void emitDirectiveCpLoad(unsigned RegNo) override; - void emitDirectiveCpRestore(SmallVector &StoreInsts, - int Offset) override; + void emitDirectiveCpRestore(int Offset) override; void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset, const MCSymbol &Sym, bool IsReg) override; void emitDirectiveCpreturn(unsigned SaveLocation,