Index: lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -30,6 +30,7 @@
 #include "SIMachineFunctionInfo.h"
 #include "SIInstrInfo.h"
 #include "SIRegisterInfo.h"
+#include "SIInstrInfo.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/IR/DiagnosticInfo.h"
 #include "llvm/MC/MCContext.h"
@@ -326,7 +327,8 @@
       if (MI.isDebugValue())
         continue;
 
-      CodeSize += TII->getInstSizeInBytes(MI);
+      if (isVerbose())
+        CodeSize += TII->getInstSizeInBytes(MI);
 
       unsigned numOperands = MI.getNumOperands();
       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
Index: lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
===================================================================
--- lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
+++ lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
@@ -196,6 +196,11 @@
   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
   unsigned bytes = Desc.getSize();
 
+  // Instructions sizes that can't just be determined by the opcode have a base
+  // size of 4, and then the following 4 byte literal.
+  if (bytes == 0)
+    bytes = 4;
+
   for (unsigned i = 0; i < bytes; i++) {
     OS.write((uint8_t) ((Encoding >> (8 * i)) & 0xff));
   }
@@ -284,7 +289,7 @@
     const MCRegisterClass &RC = MRI.getRegClass(RCID);
 
     uint32_t Enc = getLitEncoding(MO, RC.getSize());
-    if (Enc != ~0U && (Enc != 255 || Desc.getSize() == 4))
+    if (Enc != ~0U && (Enc != 255 || Desc.getSize() != 8))
       return Enc;
 
   } else if (MO.isImm())
Index: lib/Target/AMDGPU/SIInstrFormats.td
===================================================================
--- lib/Target/AMDGPU/SIInstrFormats.td
+++ lib/Target/AMDGPU/SIInstrFormats.td
@@ -86,16 +86,19 @@
   field bits<1> DisableDecoder = 0;
 
   let isAsmParserOnly = !if(!eq(DisableDecoder{0}, {0}), 0, 1);
+
+  // Similar to Size field. Get encoding size for the format ignoring
+  // 32-bit literals that could really make the full instruction
+  // encoding be 8 bytes.
+  int BaseSize = 4;
 }
 
 class Enc32 {
   field bits<32> Inst;
-  int Size = 4;
 }
 
 class Enc64 {
   field bits<64> Inst;
-  int Size = 8;
 }
 
 class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">;
@@ -124,14 +127,12 @@
     VOPAnyCommon <outs, ins, asm, pattern> {
 
   let VOP1 = 1;
-  let Size = 4;
 }
 
 class VOP2Common <dag outs, dag ins, string asm, list<dag> pattern> :
     VOPAnyCommon <outs, ins, asm, pattern> {
 
   let VOP2 = 1;
-  let Size = 4;
 }
 
 class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern, bit HasMods = 0, bit VOP3Only = 0> :
@@ -153,7 +154,8 @@
 
   let isCodeGenOnly = 0;
 
-  int Size = 8;
+  let Size = 8;
+  let BaseSize = 8;
 
   // Because SGPRs may be allowed if there are multiple operands, we
   // need a post-isel hook to insert copies in order to avoid
@@ -325,6 +327,7 @@
   let hasSideEffects = 0;
   let SALU = 1;
   let SOPP = 1;
+  let Size = 4;
 
   let UseNamedOperandTable = 1;
 }
@@ -336,6 +339,7 @@
 
   let LGKM_CNT = 1;
   let SMRD = 1;
+
   let mayStore = 0;
   let mayLoad = 1;
   let hasSideEffects = 0;
@@ -647,6 +651,7 @@
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
+  let Size = 4;
 }
 
 } // End Uses = [EXEC]
@@ -660,6 +665,8 @@
 
   let LGKM_CNT = 1;
   let DS = 1;
+  let Size = 8;
+  let BaseSize = 8;
   let UseNamedOperandTable = 1;
   let Uses = [M0, EXEC];
 
@@ -678,6 +685,8 @@
   let VM_CNT = 1;
   let EXP_CNT = 1;
   let MUBUF = 1;
+  let Size = 8;
+  let BaseSize = 8;
   let Uses = [EXEC];
 
   let hasSideEffects = 0;
@@ -692,6 +701,8 @@
   let VM_CNT = 1;
   let EXP_CNT = 1;
   let MTBUF = 1;
+  let Size = 8;
+  let BaseSize = 8;
   let Uses = [EXEC];
 
   let hasSideEffects = 0;
@@ -707,6 +718,8 @@
   // and are not considered done until both have been decremented.
   let VM_CNT = 1;
   let LGKM_CNT = 1;
+  let Size = 8;
+  let BaseSize = 8;
 
   let Uses = [EXEC, FLAT_SCR]; // M0
 
@@ -721,6 +734,8 @@
   let VM_CNT = 1;
   let EXP_CNT = 1;
   let MIMG = 1;
+  let Size = 8;
+  let BaseSize = 8;
   let Uses = [EXEC];
 
   let UseNamedOperandTable = 1;
Index: lib/Target/AMDGPU/SIInstrInfo.td
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.td
+++ lib/Target/AMDGPU/SIInstrInfo.td
@@ -674,6 +674,7 @@
   [] > {
 
   let EXP_CNT = 1;
+  let Size = 8;
   let Uses = [EXEC];
   let SchedRW = [WriteExport];
 }
@@ -794,7 +795,6 @@
   SIMCInstr<opName, SIEncodingFamily.NONE> {
   let isPseudo = 1;
   let isCodeGenOnly = 1;
-  let Size = 4;
 
   // Pseudo instructions have no encodings, but adding this field here allows
   // us to do:
@@ -956,6 +956,7 @@
               let DecoderNamespace = "SICI";
               let DisableDecoder = DisableSIDecoder;
               let isCodeGenOnly = 0;
+              let Size = 8;
             }
 
   def _vi : SOPK <outs, ins, asm, []>,
@@ -965,6 +966,7 @@
               let DecoderNamespace = "VI";
               let DisableDecoder = DisableVIDecoder;
               let isCodeGenOnly = 0;
+              let Size = 8;
             }
 }
 //===----------------------------------------------------------------------===//
@@ -986,6 +988,7 @@
   let AssemblerPredicates = [isSICI];
   let DecoderNamespace = "SICI";
   let DisableDecoder = DisableSIDecoder;
+  let Size = 4;
 }
 
 class SMRD_SOFF_Real_si <bits<5> op, string opName, dag outs, dag ins,
@@ -996,6 +999,7 @@
   let AssemblerPredicates = [isSICI];
   let DecoderNamespace = "SICI";
   let DisableDecoder = DisableSIDecoder;
+  let Size = 4;
 }
 
 
@@ -1007,6 +1011,7 @@
   let AssemblerPredicates = [isVI];
   let DecoderNamespace = "VI";
   let DisableDecoder = DisableVIDecoder;
+  let Size = 8;
 }
 
 class SMRD_SOFF_Real_vi <bits<8> op, string opName, dag outs, dag ins,
@@ -1017,6 +1022,7 @@
   let AssemblerPredicates = [isVI];
   let DecoderNamespace = "VI";
   let DisableDecoder = DisableVIDecoder;
+  let Size = 8;
 }
 
 
@@ -1106,6 +1112,7 @@
     opName#" $sdst, $sbase, $offset", []>, SMRD_IMMe_ci <op.SI> {
     let AssemblerPredicates = [isCIOnly];
     let DecoderNamespace = "CI";
+    let Size = 8;
   }
 
   defm _SGPR : SMRD_SOFF_m <
@@ -2226,6 +2233,7 @@
             let AssemblerPredicates = [isSICI];
             let DecoderNamespace = "SICI";
             let DisableDecoder = DisableSIDecoder;
+            let Size = 8;
             }
 
   def _vi : VOP2Common <P.Outs, P.Ins32,
@@ -2235,6 +2243,7 @@
             let AssemblerPredicates = [isVI];
             let DecoderNamespace = "VI";
             let DisableDecoder = DisableVIDecoder;
+            let Size = 8;
             }
 } // End isCodeGenOnly = 0
 }
@@ -3511,7 +3520,7 @@
 def getVOPe64 : InstrMapping {
   let FilterClass = "VOP";
   let RowFields = ["OpName"];
-  let ColFields = ["Size"];
+  let ColFields = ["BaseSize"];
   let KeyCol = ["4"];
   let ValueCols = [["8"]];
 }
@@ -3520,7 +3529,7 @@
 def getVOPe32 : InstrMapping {
   let FilterClass = "VOP";
   let RowFields = ["OpName"];
-  let ColFields = ["Size"];
+  let ColFields = ["BaseSize"];
   let KeyCol = ["8"];
   let ValueCols = [["4"]];
 }
Index: test/CodeGen/AMDGPU/hsa.ll
===================================================================
--- test/CodeGen/AMDGPU/hsa.ll
+++ test/CodeGen/AMDGPU/hsa.ll
@@ -53,6 +53,8 @@
 ; HSA: .Lfunc_end0:
 ; HSA: .size   simple, .Lfunc_end0-simple
 
+; HSA-CI: codeLenInByte = 32{{$}}
+; HSA-VI: codeLenInByte = 36{{$}}
 define amdgpu_kernel void @simple(i32 addrspace(1)* %out) {
 entry:
   store i32 0, i32 addrspace(1)* %out