Index: llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp
===================================================================
--- llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp
+++ llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp
@@ -562,6 +562,12 @@
   bool InMicroMipsMode = STI.inMicroMipsMode();
   const MipsInstrInfo *TII = STI.getInstrInfo();
 
+  if (InMicroMipsMode && STI.hasMips32r6()) {
+    // This is microMIPS32r6 or microMIPS64r6 processor. Delay slot for
+    // branching instructions is not needed.
+    return Changed;
+  }
+
   for (Iter I = MBB.begin(); I != MBB.end(); ++I) {
     if (!hasUnoccupiedSlot(&*I))
       continue;
Index: llvm/trunk/test/CodeGen/Mips/micromips-delay-slot.ll
===================================================================
--- llvm/trunk/test/CodeGen/Mips/micromips-delay-slot.ll
+++ llvm/trunk/test/CodeGen/Mips/micromips-delay-slot.ll
@@ -1,5 +1,7 @@
 ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
 ; RUN:   -relocation-model=static -O2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=+micromips \
+; RUN:   -relocation-model=static -O2 < %s | FileCheck %s -check-prefix=CHECK-MMR6
 
 ; Function Attrs: nounwind
 define i32 @foo(i32 signext %a) #0 {
@@ -16,3 +18,5 @@
 
 ; CHECK:      jals
 ; CHECK-NEXT: sll16
+; CHECK-MMR6: jal
+; CHECK-MMR6-NOT: sll16