Index: lib/Basic/Targets.cpp =================================================================== --- lib/Basic/Targets.cpp +++ lib/Basic/Targets.cpp @@ -1234,12 +1234,6 @@ if (HasHTM) Builder.defineMacro("__HTM__"); - Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); - Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); - Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); - if (PointerWidth == 64) - Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); - // FIXME: The following are not yet generated here by Clang, but are // generated by GCC: // @@ -2462,6 +2456,7 @@ } bool setCPU(const std::string &Name) override { CPU = getCPUKind(Name); + setAtomic(); // Perform any per-CPU checks necessary to determine if this CPU is // acceptable. @@ -2566,6 +2561,18 @@ bool hasSjLjLowering() const override { return true; } + void setAtomic() { + MaxAtomicInlineWidth = 0; + if (CPU >= CK_i486) + MaxAtomicInlineWidth = 32; + if (CPU >= CK_i586) + MaxAtomicInlineWidth = 64; + if (getTriple().getArch() == llvm::Triple::x86_64) { + MaxAtomicInlineWidth = 64; + if (HasCX16) + MaxAtomicInlineWidth = 128; + } + } }; bool X86TargetInfo::setFPMath(StringRef Name) { @@ -3148,6 +3155,9 @@ SimdDefaultAlign = hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; + + setAtomic(); + return true; } @@ -3412,8 +3422,6 @@ Builder.defineMacro("__XSAVES__"); if (HasPKU) Builder.defineMacro("__PKU__"); - if (HasCX16) - Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); // Each case falls through to the previous one here. switch (SSELevel) { @@ -3472,14 +3480,6 @@ case NoMMX3DNow: break; } - - if (CPU >= CK_i486) { - Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); - Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); - Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); - } - if (CPU >= CK_i586) - Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); } bool X86TargetInfo::hasFeature(StringRef Feature) const { @@ -3744,10 +3744,9 @@ (1 << TargetInfo::Double) | (1 << TargetInfo::LongDouble)); - // x86-32 has atomics up to 8 bytes - // FIXME: Check that we actually have cmpxchg8b before setting - // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) - MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; + // x86-32 has atomics up to 8 bytes, depending on CPU. + MaxAtomicPromoteWidth = 64; + setAtomic(); } BuiltinVaListKind getBuiltinVaListKind() const override { return TargetInfo::CharPtrBuiltinVaList; @@ -4080,9 +4079,10 @@ // Make __builtin_ms_va_list available. HasBuiltinMSVaList = true; - // x86-64 has atomics up to 16 bytes. + // x86-64 has atomics up to 16 bytes, when the HasCX16 target + // feature is enabled, 8 otherwise. MaxAtomicPromoteWidth = 128; - MaxAtomicInlineWidth = 128; + setAtomic(); } BuiltinVaListKind getBuiltinVaListKind() const override { return TargetInfo::X86_64ABIBuiltinVaList; @@ -4493,6 +4493,8 @@ (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); // Cortex M does not support 8 byte atomics, while general Thumb2 does. + if (!ShouldUseInlineAtomic) + MaxAtomicInlineWidth = 0; if (ArchProfile == llvm::ARM::PK_M) { MaxAtomicPromoteWidth = 32; if (ShouldUseInlineAtomic) @@ -4962,13 +4964,6 @@ Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", Opts.ShortEnums ? "1" : "4"); - if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { - Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); - Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); - Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); - Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); - } - // ACLE 6.4.7 DSP instructions if (DSP) { Builder.defineMacro("__ARM_FEATURE_DSP", "1"); @@ -5504,11 +5499,6 @@ if (V8_1A) Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); - // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. - Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); - Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); - Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); - Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); } ArrayRef getTargetBuiltins() const override { @@ -6401,11 +6391,6 @@ Builder.defineMacro("__zarch__"); Builder.defineMacro("__LONG_DOUBLE_128__"); - Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); - Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); - Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); - Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); - if (HasTransactionalExecution) Builder.defineMacro("__HTM__"); if (Opts.ZVector) @@ -6868,12 +6853,6 @@ Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); - - // These shouldn't be defined for MIPS-I but there's no need to check - // for that since MIPS-I isn't supported. - Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); - Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); - Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); } ArrayRef getTargetBuiltins() const override { @@ -7058,6 +7037,8 @@ PtrDiffType = SignedInt; Int64Type = SignedLongLong; IntMaxType = Int64Type; + // Atomics aren't supported for MIPS-I, but there's no need to + // check for that since MIPS-I isn't supported. MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; } bool setABI(const std::string &Name) override { @@ -7249,8 +7230,6 @@ } else llvm_unreachable("Invalid ABI for Mips64."); - - Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); } ArrayRef getGCCRegAliases() const override { static const TargetInfo::GCCRegAlias GCCRegAliases[] = { Index: lib/Frontend/InitPreprocessor.cpp =================================================================== --- lib/Frontend/InitPreprocessor.cpp +++ lib/Frontend/InitPreprocessor.cpp @@ -812,12 +812,12 @@ Builder.defineMacro("__GCC_ATOMIC_TEST_AND_SET_TRUEVAL", "1"); // Used by libc++ and libstdc++ to implement ATOMIC__LOCK_FREE. - unsigned InlineWidthBits = TI.getMaxAtomicInlineWidth(); -#define DEFINE_LOCK_FREE_MACRO(TYPE, Type) \ - Builder.defineMacro("__GCC_ATOMIC_" #TYPE "_LOCK_FREE", \ - getLockFreeValue(TI.get##Type##Width(), \ - TI.get##Type##Align(), \ - InlineWidthBits)); + unsigned AtomicInlineWidthBits = TI.getMaxAtomicInlineWidth(); +#define DEFINE_LOCK_FREE_MACRO(TYPE, Type) \ + Builder.defineMacro("__GCC_ATOMIC_" #TYPE "_LOCK_FREE", \ + getLockFreeValue(TI.get##Type##Width(), \ + TI.get##Type##Align(), \ + AtomicInlineWidthBits)); DEFINE_LOCK_FREE_MACRO(BOOL, Bool); DEFINE_LOCK_FREE_MACRO(CHAR, Char); DEFINE_LOCK_FREE_MACRO(CHAR16_T, Char16); @@ -830,8 +830,19 @@ Builder.defineMacro("__GCC_ATOMIC_POINTER_LOCK_FREE", getLockFreeValue(TI.getPointerWidth(0), TI.getPointerAlign(0), - InlineWidthBits)); + AtomicInlineWidthBits)); #undef DEFINE_LOCK_FREE_MACRO + + if (AtomicInlineWidthBits >= 8) + Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); + if (AtomicInlineWidthBits >= 16) + Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); + if (AtomicInlineWidthBits >= 32) + Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); + if (AtomicInlineWidthBits >= 64) + Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); + if (AtomicInlineWidthBits >= 128) + Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); } if (LangOpts.NoInlineDefine) Index: test/CodeGen/atomic-ops.c =================================================================== --- test/CodeGen/atomic-ops.c +++ test/CodeGen/atomic-ops.c @@ -1,10 +1,10 @@ -// RUN: %clang_cc1 %s -emit-llvm -o - -ffreestanding -ffake-address-space-map -triple=i686-apple-darwin9 | FileCheck %s +// RUN: %clang_cc1 %s -emit-llvm -o - -ffreestanding -ffake-address-space-map -triple=i686-apple-darwin9 -target-cpu i686 | FileCheck %s // REQUIRES: x86-registered-target // Also test serialization of atomic operations here, to avoid duplicating the // test. -// RUN: %clang_cc1 %s -emit-pch -o %t -ffreestanding -ffake-address-space-map -triple=i686-apple-darwin9 -// RUN: %clang_cc1 %s -include-pch %t -ffreestanding -ffake-address-space-map -triple=i686-apple-darwin9 -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 %s -emit-pch -o %t -ffreestanding -ffake-address-space-map -triple=i686-apple-darwin9 -target-cpu i686 +// RUN: %clang_cc1 %s -include-pch %t -ffreestanding -ffake-address-space-map -triple=i686-apple-darwin9 -target-cpu i686 -emit-llvm -o - | FileCheck %s #ifndef ALREADY_INCLUDED #define ALREADY_INCLUDED Index: test/CodeGen/ms-volatile.c =================================================================== --- test/CodeGen/ms-volatile.c +++ test/CodeGen/ms-volatile.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple i386-pc-win32 -fms-extensions -emit-llvm -fms-volatile -o - < %s | FileCheck %s +// RUN: %clang_cc1 -triple i686-pc-win32 -target-cpu i686 -fms-extensions -emit-llvm -fms-volatile -o - < %s | FileCheck %s struct foo { volatile int x; }; Index: test/CodeGenCXX/atomicinit.cpp =================================================================== --- test/CodeGenCXX/atomicinit.cpp +++ test/CodeGenCXX/atomicinit.cpp @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 %s -emit-llvm -O1 -o - -triple=i686-apple-darwin9 -std=c++11 | FileCheck %s +// RUN: %clang_cc1 %s -emit-llvm -O1 -o - -triple=i686-apple-darwin9 -target-cpu i686 -std=c++11 | FileCheck %s // CHECK-DAG: @PR22043 = global i32 0, align 4 typedef _Atomic(int) AtomicInt; Index: test/OpenMP/atomic_capture_codegen.cpp =================================================================== --- test/OpenMP/atomic_capture_codegen.cpp +++ test/OpenMP/atomic_capture_codegen.cpp @@ -1,6 +1,6 @@ -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -x c -emit-llvm %s -o - | FileCheck %s -// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -target-cpu core2 -fopenmp -x c -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -target-cpu core2 -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -target-cpu core2 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s // expected-no-diagnostics // REQUIRES: x86-registered-target #ifndef HEADER Index: test/OpenMP/atomic_read_codegen.c =================================================================== --- test/OpenMP/atomic_read_codegen.c +++ test/OpenMP/atomic_read_codegen.c @@ -1,6 +1,6 @@ -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -x c -emit-llvm %s -o - | FileCheck %s -// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -target-cpu core2 -fopenmp -x c -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -target-cpu core2 -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -target-cpu core2 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s // expected-no-diagnostics // REQUIRES: x86-registered-target #ifndef HEADER Index: test/OpenMP/atomic_update_codegen.cpp =================================================================== --- test/OpenMP/atomic_update_codegen.cpp +++ test/OpenMP/atomic_update_codegen.cpp @@ -1,6 +1,6 @@ -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -x c -emit-llvm %s -o - | FileCheck %s -// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -target-cpu core2 -fopenmp -x c -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -target-cpu core2 -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -target-cpu core2 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s // expected-no-diagnostics // REQUIRES: x86-registered-target #ifndef HEADER Index: test/OpenMP/atomic_write_codegen.c =================================================================== --- test/OpenMP/atomic_write_codegen.c +++ test/OpenMP/atomic_write_codegen.c @@ -1,6 +1,6 @@ -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -x c -emit-llvm %s -o - | FileCheck %s -// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -target-cpu core2 -fopenmp -x c -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -target-cpu core2 -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -target-cpu core2 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s // expected-no-diagnostics // REQUIRES: x86-registered-target #ifndef HEADER Index: test/Preprocessor/arm-target-features.c =================================================================== --- test/Preprocessor/arm-target-features.c +++ test/Preprocessor/arm-target-features.c @@ -84,7 +84,22 @@ // V8M_BASELINE-NOT: __ARM_FEATURE_CRC32 // V8M_BASELINE-NOT: __ARM_FEATURE_DSP // V8M_BASELINE-NOT: __ARM_FP 0x{{.*}} -// V8M_BASELINE-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 +// V8M_BASELINE: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2 +// V8M_BASELINE: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2 +// V8M_BASELINE: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2 +// V8M_BASELINE: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2 +// V8M_BASELINE: #define __GCC_ATOMIC_INT_LOCK_FREE 2 +// V8M_BASELINE: #define __GCC_ATOMIC_LLONG_LOCK_FREE 1 +// V8M_BASELINE: #define __GCC_ATOMIC_LONG_LOCK_FREE 2 +// V8M_BASELINE: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2 +// V8M_BASELINE: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2 +// V8M_BASELINE: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1 +// V8M_BASELINE: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2 +// V8M_BASELINE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 +// V8M_BASELINE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 +// V8M_BASELINE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 +// V8M_BASELINE-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 +// V8M_BASELINE-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 // RUN: %clang -target armv8m.main-none-linux-gnu -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=V8M_MAINLINE %s // V8M_MAINLINE: #define __ARM_ARCH 8 @@ -96,7 +111,22 @@ // V8M_MAINLINE-NOT: __ARM_FEATURE_CRC32 // V8M_MAINLINE-NOT: __ARM_FEATURE_DSP // V8M_MAINLINE: #define __ARM_FP 0xE +// V8M_MAINLINE: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2 +// V8M_MAINLINE: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2 +// V8M_MAINLINE: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2 +// V8M_MAINLINE: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2 +// V8M_MAINLINE: #define __GCC_ATOMIC_INT_LOCK_FREE 2 +// V8M_MAINLINE: #define __GCC_ATOMIC_LLONG_LOCK_FREE 1 +// V8M_MAINLINE: #define __GCC_ATOMIC_LONG_LOCK_FREE 2 +// V8M_MAINLINE: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2 +// V8M_MAINLINE: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2 +// V8M_MAINLINE: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1 +// V8M_MAINLINE: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2 // V8M_MAINLINE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 +// V8M_MAINLINE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 +// V8M_MAINLINE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 +// V8M_MAINLINE-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 +// V8M_MAINLINE-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 // RUN: %clang -target arm-none-linux-gnu -march=armv8-m.main+dsp -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=V8M_MAINLINE_DSP %s // V8M_MAINLINE_DSP: #define __ARM_ARCH 8 @@ -108,7 +138,22 @@ // V8M_MAINLINE_DSP-NOT: __ARM_FEATURE_CRC32 // V8M_MAINLINE_DSP: #define __ARM_FEATURE_DSP 1 // V8M_MAINLINE_DSP: #define __ARM_FP 0xE +// V8M_MAINLINE_DSP: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2 +// V8M_MAINLINE_DSP: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2 +// V8M_MAINLINE_DSP: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2 +// V8M_MAINLINE_DSP: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2 +// V8M_MAINLINE_DSP: #define __GCC_ATOMIC_INT_LOCK_FREE 2 +// V8M_MAINLINE_DSP: #define __GCC_ATOMIC_LLONG_LOCK_FREE 1 +// V8M_MAINLINE_DSP: #define __GCC_ATOMIC_LONG_LOCK_FREE 2 +// V8M_MAINLINE_DSP: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2 +// V8M_MAINLINE_DSP: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2 +// V8M_MAINLINE_DSP: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1 +// V8M_MAINLINE_DSP: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2 // V8M_MAINLINE_DSP: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 +// V8M_MAINLINE_DSP: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 +// V8M_MAINLINE_DSP: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 +// V8M_MAINLINE_DSP-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 +// V8M_MAINLINE_DSP-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 // RUN: %clang -target arm-none-linux-gnu -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-DEFS %s // CHECK-DEFS:#define __ARM_PCS 1 Index: test/Preprocessor/init.c =================================================================== --- test/Preprocessor/init.c +++ test/Preprocessor/init.c @@ -2854,6 +2854,22 @@ // MIPS32BE:#define __FLT_MIN_EXP__ (-125) // MIPS32BE:#define __FLT_MIN__ 1.17549435e-38F // MIPS32BE:#define __FLT_RADIX__ 2 +// MIPS32BE:#define __GCC_ATOMIC_BOOL_LOCK_FREE 2 +// MIPS32BE:#define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2 +// MIPS32BE:#define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2 +// MIPS32BE:#define __GCC_ATOMIC_CHAR_LOCK_FREE 2 +// MIPS32BE:#define __GCC_ATOMIC_INT_LOCK_FREE 2 +// MIPS32BE:#define __GCC_ATOMIC_LLONG_LOCK_FREE 1 +// MIPS32BE:#define __GCC_ATOMIC_LONG_LOCK_FREE 2 +// MIPS32BE:#define __GCC_ATOMIC_POINTER_LOCK_FREE 2 +// MIPS32BE:#define __GCC_ATOMIC_SHORT_LOCK_FREE 2 +// MIPS32BE:#define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1 +// MIPS32BE:#define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2 +// MIPS32BE:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 +// MIPS32BE:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 +// MIPS32BE:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 +// MIPS32BE-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 +// MIPS32BE-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 // MIPS32BE:#define __INT16_C_SUFFIX__ // MIPS32BE:#define __INT16_FMTd__ "hd" // MIPS32BE:#define __INT16_FMTi__ "hi" @@ -3062,6 +3078,22 @@ // MIPS32EL:#define __FLT_MIN_EXP__ (-125) // MIPS32EL:#define __FLT_MIN__ 1.17549435e-38F // MIPS32EL:#define __FLT_RADIX__ 2 +// MIPS32EL:#define __GCC_ATOMIC_BOOL_LOCK_FREE 2 +// MIPS32EL:#define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2 +// MIPS32EL:#define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2 +// MIPS32EL:#define __GCC_ATOMIC_CHAR_LOCK_FREE 2 +// MIPS32EL:#define __GCC_ATOMIC_INT_LOCK_FREE 2 +// MIPS32EL:#define __GCC_ATOMIC_LLONG_LOCK_FREE 1 +// MIPS32EL:#define __GCC_ATOMIC_LONG_LOCK_FREE 2 +// MIPS32EL:#define __GCC_ATOMIC_POINTER_LOCK_FREE 2 +// MIPS32EL:#define __GCC_ATOMIC_SHORT_LOCK_FREE 2 +// MIPS32EL:#define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1 +// MIPS32EL:#define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2 +// MIPS32EL:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 +// MIPS32EL:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 +// MIPS32EL:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 +// MIPS32EL-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 +// MIPS32EL-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 // MIPS32EL:#define __INT16_C_SUFFIX__ // MIPS32EL:#define __INT16_FMTd__ "hd" // MIPS32EL:#define __INT16_FMTi__ "hi" @@ -3289,6 +3321,11 @@ // MIPSN32BE: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2 // MIPSN32BE: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1 // MIPSN32BE: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2 +// MIPSN32BE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 +// MIPSN32BE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 +// MIPSN32BE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 +// MIPSN32BE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1 +// MIPSN32BE-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 // MIPSN32BE: #define __GNUC_MINOR__ 2 // MIPSN32BE: #define __GNUC_PATCHLEVEL__ 1 // MIPSN32BE: #define __GNUC_STDC_INLINE__ 1 @@ -3594,6 +3631,11 @@ // MIPSN32EL: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2 // MIPSN32EL: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1 // MIPSN32EL: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2 +// MIPSN32EL: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 +// MIPSN32EL: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 +// MIPSN32EL: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 +// MIPSN32EL: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1 +// MIPSN32EL-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 // MIPSN32EL: #define __GNUC_MINOR__ 2 // MIPSN32EL: #define __GNUC_PATCHLEVEL__ 1 // MIPSN32EL: #define __GNUC_STDC_INLINE__ 1 @@ -7621,6 +7663,11 @@ // X86_64-CLOUDABI:#define __GCC_ATOMIC_SHORT_LOCK_FREE 2 // X86_64-CLOUDABI:#define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1 // X86_64-CLOUDABI:#define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2 +// X86_64-CLOUDABI:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 +// X86_64-CLOUDABI:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 +// X86_64-CLOUDABI:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 +// X86_64-CLOUDABI:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1 +// X86_64-CLOUDABI-NOT:__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 // X86_64-CLOUDABI:#define __GNUC_MINOR__ 2 // X86_64-CLOUDABI:#define __GNUC_PATCHLEVEL__ 1 // X86_64-CLOUDABI:#define __GNUC_STDC_INLINE__ 1 @@ -8488,6 +8535,11 @@ // WEBASSEMBLY32-NEXT:#define __GCC_ATOMIC_SHORT_LOCK_FREE 2 // WEBASSEMBLY32-NEXT:#define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1 // WEBASSEMBLY32-NEXT:#define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2 +// WEBASSEMBLY32-NEXT:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 +// WEBASSEMBLY32-NEXT:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 +// WEBASSEMBLY32-NEXT:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 +// WEBASSEMBLY32-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 +// WEBASSEMBLY32-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 // WEBASSEMBLY32-NEXT:#define __GNUC_MINOR__ {{.*}} // WEBASSEMBLY32-NEXT:#define __GNUC_PATCHLEVEL__ {{.*}} // WEBASSEMBLY32-NEXT:#define __GNUC_STDC_INLINE__ 1 @@ -8803,6 +8855,11 @@ // WEBASSEMBLY64-NEXT:#define __GCC_ATOMIC_SHORT_LOCK_FREE 2 // WEBASSEMBLY64-NEXT:#define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1 // WEBASSEMBLY64-NEXT:#define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2 +// WEBASSEMBLY64-NEXT:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 +// WEBASSEMBLY64-NEXT:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 +// WEBASSEMBLY64-NEXT:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 +// WEBASSEMBLY64-NEXT:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1 +// WEBASSEMBLY64-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 // WEBASSEMBLY64-NEXT:#define __GNUC_MINOR__ {{.*}} // WEBASSEMBLY64-NEXT:#define __GNUC_PATCHLEVEL__ {{.*}} // WEBASSEMBLY64-NEXT:#define __GNUC_STDC_INLINE__ 1 @@ -9060,4 +9117,3 @@ // RUN: %clang_cc1 -E -dM -ffreestanding -triple x86_64-windows-cygnus < /dev/null | FileCheck -match-full-lines -check-prefix CYGWIN-X64 %s // CYGWIN-X64: #define __USER_LABEL_PREFIX__ - Index: test/Preprocessor/predefined-arch-macros.c =================================================================== --- test/Preprocessor/predefined-arch-macros.c +++ test/Preprocessor/predefined-arch-macros.c @@ -1869,10 +1869,22 @@ // RUN: -target powerpc64le-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PPC_GCC_ATOMICS // +// CHECK_PPC_GCC_ATOMICS: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2 +// CHECK_PPC_GCC_ATOMICS: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2 +// CHECK_PPC_GCC_ATOMICS: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2 +// CHECK_PPC_GCC_ATOMICS: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2 +// CHECK_PPC_GCC_ATOMICS: #define __GCC_ATOMIC_INT_LOCK_FREE 2 +// CHECK_PPC_GCC_ATOMICS: #define __GCC_ATOMIC_LLONG_LOCK_FREE 2 +// CHECK_PPC_GCC_ATOMICS: #define __GCC_ATOMIC_LONG_LOCK_FREE 2 +// CHECK_PPC_GCC_ATOMICS: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2 +// CHECK_PPC_GCC_ATOMICS: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2 +// CHECK_PPC_GCC_ATOMICS: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1 +// CHECK_PPC_GCC_ATOMICS: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2 // CHECK_PPC_GCC_ATOMICS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 // CHECK_PPC_GCC_ATOMICS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 // CHECK_PPC_GCC_ATOMICS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 // CHECK_PPC_GCC_ATOMICS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1 +// CHECK_PPC_GCC_ATOMICS-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 // // End PPC/GCC/Linux tests ------------------ @@ -1936,10 +1948,22 @@ // RUN: -target s390x-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_Z10 // +// CHECK_SYSTEMZ_Z10: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2 +// CHECK_SYSTEMZ_Z10: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2 +// CHECK_SYSTEMZ_Z10: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2 +// CHECK_SYSTEMZ_Z10: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2 +// CHECK_SYSTEMZ_Z10: #define __GCC_ATOMIC_INT_LOCK_FREE 2 +// CHECK_SYSTEMZ_Z10: #define __GCC_ATOMIC_LLONG_LOCK_FREE 2 +// CHECK_SYSTEMZ_Z10: #define __GCC_ATOMIC_LONG_LOCK_FREE 2 +// CHECK_SYSTEMZ_Z10: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2 +// CHECK_SYSTEMZ_Z10: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2 +// CHECK_SYSTEMZ_Z10: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1 +// CHECK_SYSTEMZ_Z10: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2 // CHECK_SYSTEMZ_Z10: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 // CHECK_SYSTEMZ_Z10: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 // CHECK_SYSTEMZ_Z10: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 // CHECK_SYSTEMZ_Z10: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1 +// CHECK_SYSTEMZ_Z10-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 // CHECK_SYSTEMZ_Z10: #define __LONG_DOUBLE_128__ 1 // CHECK_SYSTEMZ_Z10: #define __s390__ 1 // CHECK_SYSTEMZ_Z10: #define __s390x__ 1 @@ -1949,10 +1973,22 @@ // RUN: -target s390x-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ZEC12 // +// CHECK_SYSTEMZ_ZEC12: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2 +// CHECK_SYSTEMZ_ZEC12: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2 +// CHECK_SYSTEMZ_ZEC12: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2 +// CHECK_SYSTEMZ_ZEC12: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2 +// CHECK_SYSTEMZ_ZEC12: #define __GCC_ATOMIC_INT_LOCK_FREE 2 +// CHECK_SYSTEMZ_ZEC12: #define __GCC_ATOMIC_LLONG_LOCK_FREE 2 +// CHECK_SYSTEMZ_ZEC12: #define __GCC_ATOMIC_LONG_LOCK_FREE 2 +// CHECK_SYSTEMZ_ZEC12: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2 +// CHECK_SYSTEMZ_ZEC12: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2 +// CHECK_SYSTEMZ_ZEC12: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1 +// CHECK_SYSTEMZ_ZEC12: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2 // CHECK_SYSTEMZ_ZEC12: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 // CHECK_SYSTEMZ_ZEC12: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 // CHECK_SYSTEMZ_ZEC12: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 // CHECK_SYSTEMZ_ZEC12: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1 +// CHECK_SYSTEMZ_ZEC12-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 // CHECK_SYSTEMZ_ZEC12: #define __HTM__ 1 // CHECK_SYSTEMZ_ZEC12: #define __LONG_DOUBLE_128__ 1 // CHECK_SYSTEMZ_ZEC12: #define __s390__ 1 Index: test/Preprocessor/predefined-macros.c =================================================================== --- test/Preprocessor/predefined-macros.c +++ test/Preprocessor/predefined-macros.c @@ -102,38 +102,95 @@ // RUN: %clang_cc1 %s -E -dM -o - -triple i686 -target-cpu i386 \ // RUN: | FileCheck -match-full-lines %s --check-prefix=CHECK-SYNC_CAS_I386 // CHECK-SYNC_CAS_I386-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP +// CHECK-SYNC_CAS_I386-NOT: __GCC_ATOMIC_{{.*}}_LOCK_FREE 2 // // RUN: %clang_cc1 %s -E -dM -o - -triple i686 -target-cpu i486 \ // RUN: | FileCheck -match-full-lines %s --check-prefix=CHECK-SYNC_CAS_I486 +// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2 +// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2 +// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2 +// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2 +// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_INT_LOCK_FREE 2 +// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_LLONG_LOCK_FREE 1 +// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_LONG_LOCK_FREE 2 +// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2 +// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2 +// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1 +// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2 // CHECK-SYNC_CAS_I486: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 // CHECK-SYNC_CAS_I486: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 // CHECK-SYNC_CAS_I486: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 // CHECK-SYNC_CAS_I486-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 +// CHECK-SYNC_CAS_I486-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 // + +// FIXME: The value of LLONG_LOCK_FREE on i586 is wrong: clang is +// using the alignment of "long long" (only 32bit for a 64bit value) +// to disqualify it from being lock free. But the semantics of this +// define are supposed to tell you if "_Atomic long long" is lock free +// -- and it is. + // RUN: %clang_cc1 %s -E -dM -o - -triple i686 -target-cpu i586 \ // RUN: | FileCheck -match-full-lines %s --check-prefix=CHECK-SYNC_CAS_I586 +// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2 +// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2 +// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2 +// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2 +// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_INT_LOCK_FREE 2 +// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_LLONG_LOCK_FREE 1 +// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_LONG_LOCK_FREE 2 +// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2 +// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2 +// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1 +// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2 // CHECK-SYNC_CAS_I586: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 // CHECK-SYNC_CAS_I586: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 // CHECK-SYNC_CAS_I586: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 // CHECK-SYNC_CAS_I586: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1 +// CHECK-SYNC_CAS_I586-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 // // RUN: %clang_cc1 %s -E -dM -o - -triple armv6 -target-cpu arm1136j-s \ // RUN: | FileCheck -match-full-lines %s --check-prefix=CHECK-SYNC_CAS_ARM +// CHECK-SYNC_CAS_ARM: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2 +// CHECK-SYNC_CAS_ARM: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2 +// CHECK-SYNC_CAS_ARM: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2 +// CHECK-SYNC_CAS_ARM: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2 +// CHECK-SYNC_CAS_ARM: #define __GCC_ATOMIC_INT_LOCK_FREE 2 +// CHECK-SYNC_CAS_ARM: #define __GCC_ATOMIC_LLONG_LOCK_FREE 2 +// CHECK-SYNC_CAS_ARM: #define __GCC_ATOMIC_LONG_LOCK_FREE 2 +// CHECK-SYNC_CAS_ARM: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2 +// CHECK-SYNC_CAS_ARM: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2 +// CHECK-SYNC_CAS_ARM: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1 +// CHECK-SYNC_CAS_ARM: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2 // CHECK-SYNC_CAS_ARM: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 // CHECK-SYNC_CAS_ARM: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 // CHECK-SYNC_CAS_ARM: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 // CHECK-SYNC_CAS_ARM: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1 +// CHECK-SYNC_CAS_ARM-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 // // RUN: %clang_cc1 %s -E -dM -o - -triple armv7 -target-cpu cortex-a8 \ // RUN: | FileCheck -match-full-lines %s --check-prefix=CHECK-SYNC_CAS_ARMv7 +// CHECK-SYNC_CAS_ARMV7: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2 +// CHECK-SYNC_CAS_ARMV7: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2 +// CHECK-SYNC_CAS_ARMV7: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2 +// CHECK-SYNC_CAS_ARMV7: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2 +// CHECK-SYNC_CAS_ARMV7: #define __GCC_ATOMIC_INT_LOCK_FREE 2 +// CHECK-SYNC_CAS_ARMV7: #define __GCC_ATOMIC_LLONG_LOCK_FREE 2 +// CHECK-SYNC_CAS_ARMV7: #define __GCC_ATOMIC_LONG_LOCK_FREE 2 +// CHECK-SYNC_CAS_ARMV7: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2 +// CHECK-SYNC_CAS_ARMV7: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2 +// CHECK-SYNC_CAS_ARMV7: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1 +// CHECK-SYNC_CAS_ARMV7: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2 // CHECK-SYNC_CAS_ARMv7: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 // CHECK-SYNC_CAS_ARMv7: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 // CHECK-SYNC_CAS_ARMv7: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 // CHECK-SYNC_CAS_ARMv7: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1 +// CHECK-SYNC_CAS_ARMv7-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 // -// RUN: %clang_cc1 %s -E -dM -o - -triple armv6 -target-cpu cortex-m0 \ +// RUN: %clang_cc1 %s -E -dM -o - -triple thumbv6m-- -target-cpu cortex-m0 \ // RUN: | FileCheck -match-full-lines %s --check-prefix=CHECK-SYNC_CAS_ARMv6 // CHECK-SYNC_CAS_ARMv6-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP +// CHECK-SYNC_CAS_ARMv6-NOT: __GCC_ATOMIC_{{.*}}_LOCK_FREE 2 // // RUN: %clang_cc1 %s -E -dM -o - -triple mips -target-cpu mips2 \ // RUN: | FileCheck -match-full-lines %s --check-prefix=CHECK-SYNC_CAS_MIPS \ @@ -141,8 +198,21 @@ // RUN: %clang_cc1 %s -E -dM -o - -triple mips64 -target-cpu mips3 \ // RUN: | FileCheck -match-full-lines %s --check-prefix=CHECK-SYNC_CAS_MIPS \ // RUN: --check-prefix=CHECK-SYNC_CAS_MIPS64 +// CHECK-SYNC_CAS_MIPS: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2 +// CHECK-SYNC_CAS_MIPS: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2 +// CHECK-SYNC_CAS_MIPS: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2 +// CHECK-SYNC_CAS_MIPS: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2 +// CHECK-SYNC_CAS_MIPS: #define __GCC_ATOMIC_INT_LOCK_FREE 2 +// CHECK-SYNC_CAS_MIPS32: #define __GCC_ATOMIC_LLONG_LOCK_FREE 1 +// CHECK-SYNC_CAS_MIPS64: #define __GCC_ATOMIC_LLONG_LOCK_FREE 2 +// CHECK-SYNC_CAS_MIPS: #define __GCC_ATOMIC_LONG_LOCK_FREE 2 +// CHECK-SYNC_CAS_MIPS: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2 +// CHECK-SYNC_CAS_MIPS: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2 +// CHECK-SYNC_CAS_MIPS: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1 +// CHECK-SYNC_CAS_MIPS: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2 // CHECK-SYNC_CAS_MIPS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 // CHECK-SYNC_CAS_MIPS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 // CHECK-SYNC_CAS_MIPS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 // CHECK-SYNC_CAS_MIPS32-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 // CHECK-SYNC_CAS_MIPS64: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1 +// CHECK-SYNC_CAS_MIPS-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 Index: test/Preprocessor/x86_target_features.c =================================================================== --- test/Preprocessor/x86_target_features.c +++ test/Preprocessor/x86_target_features.c @@ -291,8 +291,13 @@ // NOTBM-NOT: #define __TBM__ 1 -// RUN: %clang -target i386-unknown-unknown -march=pentiumpro -mcx16 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=MCX16 %s +// RUN: %clang -target i386-unknown-unknown -march=pentiumpro -mcx16 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=MCX16-386 %s +// MCX16-386-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 + +// RUN: %clang -target x86_64-unknown-unknown -mcx16 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=MCX16 %s + +// MCX16: #define __GCC_ATOMIC_LLONG_LOCK_FREE 2 // MCX16: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 1 // RUN: %clang -target i386-unknown-unknown -march=atom -mprfchw -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=PRFCHW %s Index: test/Sema/atomic-ops.c =================================================================== --- test/Sema/atomic-ops.c +++ test/Sema/atomic-ops.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 %s -verify -ffreestanding -fsyntax-only -triple=i686-linux-gnu -std=c11 +// RUN: %clang_cc1 %s -verify -ffreestanding -fsyntax-only -triple=i686-linux-gnu -target-cpu i686 -std=c11 // Basic parsing/Sema tests for __c11_atomic_* @@ -502,5 +502,3 @@ (void)__atomic_compare_exchange_n(p, p, val, 0, memory_order_acq_rel, memory_order_relaxed); (void)__atomic_compare_exchange_n(p, p, val, 0, memory_order_seq_cst, memory_order_relaxed); } - -