Index: lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- lib/Target/PowerPC/PPCISelLowering.cpp
+++ lib/Target/PowerPC/PPCISelLowering.cpp
@@ -557,7 +557,7 @@
         setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
         setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);
       }
-      if (Subtarget.hasDirectMove()) {
+      if (Subtarget.hasDirectMove() && Subtarget.use64BitRegs()) {
         setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal);
         setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal);
         setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal);
Index: test/CodeGen/PowerPC/pr26617.ll
===================================================================
--- test/CodeGen/PowerPC/pr26617.ll
+++ test/CodeGen/PowerPC/pr26617.ll
@@ -0,0 +1,8 @@
+; RUN: llc -mcpu=pwr8 -mtriple=powerpc-unknown-unknown < %s | FileCheck %s
+define i32 @test(<4 x i32> %v, i32 %elem) #0 {
+entry:
+  %vecext = extractelement <4 x i32> %v, i32 %elem
+  ret i32 %vecext
+}
+; CHECK: stxvw4x 34,
+; CHECK: lwzx 3,