Index: lib/Target/AArch64/AArch64FrameLowering.cpp =================================================================== --- lib/Target/AArch64/AArch64FrameLowering.cpp +++ lib/Target/AArch64/AArch64FrameLowering.cpp @@ -856,6 +856,9 @@ .addReg(AArch64::SP) .addImm(Offset) // [sp, #offset * 8], where factor * 8 is implicit .setMIFlag(MachineInstr::FrameSetup); + MIB.addMemOperand(MF.getMachineMemOperand( + MachinePointerInfo::getFixedStack(MF, RPI.FrameIdx + 1), + MachineMemOperand::MOStore, 8, 8)); } else { MBB.addLiveIn(Reg1); MIB.addReg(Reg1, getPrologueDeath(MF, Reg1)) @@ -863,6 +866,9 @@ .addImm(BumpSP ? Offset * 8 : Offset) // pre-inc version is unscaled .setMIFlag(MachineInstr::FrameSetup); } + MIB.addMemOperand(MF.getMachineMemOperand( + MachinePointerInfo::getFixedStack(MF, RPI.FrameIdx), + MachineMemOperand::MOStore, 8, 8)); } return true; } @@ -920,18 +926,25 @@ if (BumpSP) MIB.addReg(AArch64::SP, RegState::Define); - if (RPI.isPaired()) + if (RPI.isPaired()) { MIB.addReg(Reg2, getDefRegState(true)) .addReg(Reg1, getDefRegState(true)) .addReg(AArch64::SP) .addImm(Offset) // [sp], #offset * 8 or [sp, #offset * 8] // where the factor * 8 is implicit .setMIFlag(MachineInstr::FrameDestroy); - else + MIB.addMemOperand(MF.getMachineMemOperand( + MachinePointerInfo::getFixedStack(MF, RPI.FrameIdx + 1), + MachineMemOperand::MOLoad, 8, 8)); + } else { MIB.addReg(Reg1, getDefRegState(true)) .addReg(AArch64::SP) .addImm(BumpSP ? Offset * 8 : Offset) // post-dec version is unscaled .setMIFlag(MachineInstr::FrameDestroy); + } + MIB.addMemOperand(MF.getMachineMemOperand( + MachinePointerInfo::getFixedStack(MF, RPI.FrameIdx), + MachineMemOperand::MOLoad, 8, 8)); } return true; } Index: test/CodeGen/AArch64/arm64-csldst-mmo.ll =================================================================== --- /dev/null +++ test/CodeGen/AArch64/arm64-csldst-mmo.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched=0 -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s + +@G = external global [0 x i32], align 4 + +; Check that MMOs are added to epilogue calle-save restore loads so +; that the store to G is not considered dependant on the callee-save +; loads. +; +; CHECK: Before post-MI-sched: +; CHECK-LABEL: # Machine code for function test1: +; CHECK: SU(2): STRWui %WZR +; CHECK: SU(3): %X21, %X20 = LDPXi %SP +; CHECK: Predecessors: +; CHECK-NEXT: out SU(0) +; CHECK-NEXT: out SU(0) +; CHECK-NEXT: ch SU(0) +; CHECK-NEXT: Successors: +define void @test1() { +entry: + tail call void asm sideeffect "nop", "~{x20},~{x21},~{x22},~{x23}"() nounwind + store i32 0, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @G, i64 0, i64 0), align 4 + ret void +}