Fix Sparc 32bit Lowering to rebundle up v2i32 values.

[niravd]

Summary

Fix LowerCall to rebundle v2i32 values after lowering and add testcase

[jyknight]

All reviews must have either cfe-commits or llvm-commits set as a subscriber so it gets sent to the mailing list.

lib/Target/Sparc/SparcISelLowering.cpp

1002 ↗

(On Diff #49086)

Please run the diff through clang-format. E.g.
git config --global clangformat.style file
git clang-format HEAD~1

test/CodeGen/SPARC/vector-call.ll

2 ↗

(On Diff #49086)

Add a comment as to why this test is here, what it's intended to be testing.

[niravd]

Applied clang-format
Added test case and explanitory comment

[niravd]

Update commit message

[jyknight]

test/CodeGen/SPARC/vector-call.ll

14 ↗

(On Diff #49106)

I'd move the CHECKs immediately above the function it's checking rather than below; that's the more common way. Also, space after ";".

[niravd]

Change placement of CHECK commands in test

llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp

SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
   SmallVector<CCValAssign, 16> RVLocs;
   CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
                  *DAG.getContext());
 
   RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32);
 
   // Copy all of the result registers out of their specified physreg.
   for (unsigned i = 0; i != RVLocs.size(); ++i) {
-    Chain = DAG.getCopyFromReg(Chain, dl, toCallerWindow(RVLocs[i].getLocReg()),
-                               RVLocs[i].getValVT(), InFlag).getValue(1);
+    if (RVLocs[i].getLocVT() == MVT::v2i32) {
+      SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2i32);
+      SDValue Lo = DAG.getCopyFromReg(
+          Chain, dl, toCallerWindow(RVLocs[i++].getLocReg()), MVT::i32, InFlag);
+      Chain = Lo.getValue(1);
+      InFlag = Lo.getValue(2);
+      Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Lo,
+                        DAG.getConstant(0, dl, MVT::i32));
+      SDValue Hi = DAG.getCopyFromReg(
+          Chain, dl, toCallerWindow(RVLocs[i].getLocReg()), MVT::i32, InFlag);
+      Chain = Hi.getValue(1);
+      InFlag = Hi.getValue(2);
+      Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Hi,
+                        DAG.getConstant(1, dl, MVT::i32));
+      InVals.push_back(Vec);
+    } else {
+      Chain =
+          DAG.getCopyFromReg(Chain, dl, toCallerWindow(RVLocs[i].getLocReg()),
+                             RVLocs[i].getValVT(), InFlag)
+              .getValue(1);
       InFlag = Chain.getValue(2);
       InVals.push_back(Chain.getValue(0));
     }
+  }
 
   return Chain;
 }
 
 // This functions returns true if CalleeName is a ABI function that returns
 // a long double (fp128).
 static bool isFP128ABICall(const char *CalleeName)
 {

llvm/trunk/test/CodeGen/SPARC/vector-call.ll

+; RUN: llc < %s -march=sparc | FileCheck %s
+
+; Verify that we correctly handle vector types that appear directly
+; during call lowering. These may cause issue as v2i32 is a legal type
+; for the implementation of LDD
+
+; CHECK-LABEL: fun16v:
+; CHECK: foo1_16v
+; CHECK: foo2_16v
+
+define <2 x i16> @fun16v() #0 {
+  %1 = tail call <2 x i16> @foo1_16v()
+  %2 = tail call <2 x i16> @foo2_16v()
+  %3 = and <2 x i16> %2, %1
+  ret <2 x i16> %3
+}
+
+declare <2 x i16> @foo1_16v() #0
+declare <2 x i16> @foo2_16v() #0
+
+; CHECK-LABEL: fun32v:
+; CHECK: foo1_32v
+; CHECK: foo2_32v
+
+define <2 x i32> @fun32v() #0 {
+  %1 = tail call <2 x i32> @foo1_32v()
+  %2 = tail call <2 x i32> @foo2_32v()
+  %3 = and <2 x i32> %2, %1
+  ret <2 x i32> %3
+}
+
+declare <2 x i32> @foo1_32v() #0
+declare <2 x i32> @foo2_32v() #0