Index: lib/Target/Mips/MicroMips64r6InstrFormats.td =================================================================== --- lib/Target/Mips/MicroMips64r6InstrFormats.td +++ lib/Target/Mips/MicroMips64r6InstrFormats.td @@ -84,3 +84,48 @@ let Inst{10-9} = 0b00; let Inst{8-0} = funct; } + +class POOL32S_2R_FM_MMR6 funct> + : MMR6Arch { + bits<5> rd; + bits<5> rs; + + bits<32> Inst; + + let Inst{31-26} = 0b010110; + let Inst{25-21} = rd; + let Inst{20-16} = rs; + let Inst{15-6} = funct; + let Inst{5-0} = 0b111100; +} + +class POOL32S_3R_FM_MMR6 funct> + : MMR6Arch { + bits<5> rt; + bits<5> rs; + bits<5> rd; + + bits<32> Inst; + + let Inst{31-26} = 0b010110; + let Inst{25-21} = rt; + let Inst{20-16} = rs; + let Inst{15-11} = rd; + let Inst{10-9} = 0b00; + let Inst{8-0} = funct; +} + +class POOL32S_2RSA5_FM_MMR6 funct> { + bits<5> rt; + bits<5> rs; + bits<5> sa; + + bits<32> Inst; + + let Inst{31-26} = 0b010110; + let Inst{25-21} = rt; + let Inst{20-16} = rs; + let Inst{15-11} = sa; + let Inst{10-9} = 0b00; + let Inst{8-0} = funct; +} Index: lib/Target/Mips/MicroMips64r6InstrInfo.td =================================================================== --- lib/Target/Mips/MicroMips64r6InstrInfo.td +++ lib/Target/Mips/MicroMips64r6InstrInfo.td @@ -28,6 +28,11 @@ class DMOD_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"dmod", 0b101011000>; class DDIVU_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"ddivu", 0b110011000>; class DMODU_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"dmodu", 0b111011000>; +class DCLO_MM64R6_ENC : POOL32S_2R_FM_MMR6<"dclo", 0b0100101100>; +class DCLZ_MM64R6_ENC : POOL32S_2R_FM_MMR6<"dclz", 0b0101101100>; +class DROTR_MM64R6_ENC : POOL32S_2RSA5_FM_MMR6<"drotr", 0b011000000>; +class DROTR32_MM64R6_ENC : POOL32S_2RSA5_FM_MMR6<"drotr32", 0b011001000>; +class DROTRV_MM64R6_ENC : POOL32S_3R_FM_MMR6<"drotrv", 0b011010000>; //===----------------------------------------------------------------------===// // @@ -89,6 +94,29 @@ class DMOD_MM64R6_DESC : ArithLogicR<"dmod", GPR32Opnd>; class DDIVU_MM64R6_DESC : ArithLogicR<"ddivu", GPR32Opnd>; class DMODU_MM64R6_DESC : ArithLogicR<"dmodu", GPR32Opnd>; +class DCLO_MM64R6_DESC : CountLeading1<"dclo", GPR64Opnd>; +class DCLZ_MM64R6_DESC : CountLeading0<"dclz", GPR64Opnd>; + +class SHIFT_ROTATE_IMM_MM64R6 + : MMR6Arch, MipsR6Inst { + dag OutOperandList = (outs RO:$rt); + dag InOperandList = (ins RO:$rs, ImmOpnd:$sa); + string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa"); + list Pattern = [(set RO:$rt, (OpNode RO:$rs, PF:$sa))]; + InstrItinClass Itinerary = itin; + Format Form = FrmR; + string BaseOpcode = instr_asm; +} + +class DROTR_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"drotr", uimm5, GPR64Opnd, + II_DROTR, rotr, immZExt5>; +class DROTR32_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"drotr32", uimm5, GPR64Opnd, + II_DROTR32>; +class DROTRV_MM64R6_DESC : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, + rotr>; //===----------------------------------------------------------------------===// // @@ -116,4 +144,14 @@ ISA_MICROMIPS64R6; def DMODU_MM64R6 : R6MMR6Rel, DMODU_MM64R6_DESC, DMODU_MM64R6_ENC, ISA_MICROMIPS64R6; + def DCLO_MM64R6 : StdMMR6Rel, DCLO_MM64R6_DESC, DCLO_MM64R6_ENC, + ISA_MICROMIPS64R6; + def DCLZ_MM64R6 : StdMMR6Rel, DCLZ_MM64R6_DESC, DCLZ_MM64R6_ENC, + ISA_MICROMIPS64R6; + def DROTR_MM64R6 : StdMMR6Rel, DROTR_MM64R6_DESC, DROTR_MM64R6_ENC, + ISA_MICROMIPS64R6; + def DROTR32_MM64R6 : StdMMR6Rel, DROTR32_MM64R6_DESC, DROTR32_MM64R6_ENC, + ISA_MICROMIPS64R6; + def DROTRV_MM64R6 : StdMMR6Rel, DROTRV_MM64R6_DESC, DROTRV_MM64R6_ENC, + ISA_MICROMIPS64R6; } Index: lib/Target/Mips/Mips64InstrInfo.td =================================================================== --- lib/Target/Mips/Mips64InstrInfo.td +++ lib/Target/Mips/Mips64InstrInfo.td @@ -151,13 +151,15 @@ SRA_FM<0x3f, 0>, ISA_MIPS3; // Rotate Instructions -def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr, - immZExt6>, - SRA_FM<0x3a, 1>, ISA_MIPS64R2; -def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>, - SRLV_FM<0x16, 1>, ISA_MIPS64R2; -def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>, - SRA_FM<0x3e, 1>, ISA_MIPS64R2; +let AdditionalPredicates = [NotInMicroMips] in { + def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr, + immZExt6>, + SRA_FM<0x3a, 1>, ISA_MIPS64R2; + def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>, + SRLV_FM<0x16, 1>, ISA_MIPS64R2; + def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>, + SRA_FM<0x3e, 1>, ISA_MIPS64R2; +} /// Load and Store Instructions /// aligned Index: test/MC/Disassembler/Mips/micromips64r6/valid.txt =================================================================== --- test/MC/Disassembler/Mips/micromips64r6/valid.txt +++ test/MC/Disassembler/Mips/micromips64r6/valid.txt @@ -169,3 +169,8 @@ 0x00 0x00 0xe3 0x7c # CHECK: deret 0x00 0x00 0x47 0x7c # CHECK: di 0x00 0x0f 0x47 0x7c # CHECK: di $15 +0x58 0x22 0x4b 0x3c # CHECK: dclo $1, $2 +0x58 0x22 0x5b 0x3c # CHECK: dclz $1, $2 +0x58 0xaa 0x40 0xc0 # CHECK: drotr $5, $10, 8 +0x58 0x22 0x20 0xc8 # CHECK: drotr32 $1, $2, 4 +0x58 0xc4 0x18 0xd0 # CHECK: drotrv $3, $6, $4 Index: test/MC/Mips/micromips64r6/invalid.s =================================================================== --- test/MC/Mips/micromips64r6/invalid.s +++ test/MC/Mips/micromips64r6/invalid.s @@ -131,3 +131,7 @@ swm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swm16 $16, $17, $ra, 8($fp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + drotr $5, $10, 64 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate + drotr $5, $10, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate + drotr32 $1, $2, 32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate + drotr32 $1, $2, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate Index: test/MC/Mips/micromips64r6/valid.s =================================================================== --- test/MC/Mips/micromips64r6/valid.s +++ test/MC/Mips/micromips64r6/valid.s @@ -150,5 +150,9 @@ di # CHECK: di # encoding: [0x00,0x00,0x47,0x7c] di $0 # CHECK: di # encoding: [0x00,0x00,0x47,0x7c] di $15 # CHECK: di $15 # encoding: [0x00,0x0f,0x47,0x7c] - + dclo $1, $2 # CHECK: dclo $1, $2 # encoding: [0x58,0x22,0x4b,0x3c] + dclz $1, $2 # CHECK: dclz $1, $2 # encoding: [0x58,0x22,0x5b,0x3c] + drotr $5, $10, 8 # CHECK: drotr $5, $10, 8 # encoding: [0x58,0xaa,0x40,0xc0] + drotr32 $1, $2, 4 # CHECK: drotr32 $1, $2, 4 # encoding: [0x58,0x22,0x20,0xc8] + drotrv $3, $6, $4 # CHECK: drotrv $3, $6, $4 # encoding: [0x58,0xc4,0x18,0xd0] 1: