Index: lib/Target/Mips/MicroMips64r6InstrFormats.td =================================================================== --- lib/Target/Mips/MicroMips64r6InstrFormats.td +++ lib/Target/Mips/MicroMips64r6InstrFormats.td @@ -84,3 +84,74 @@ let Inst{10-9} = 0b00; let Inst{8-0} = funct; } + +class POOL32A_2R_FM_MM64R6 { + bits<5> rt; + bits<5> rd; + + bits<32> Inst; + + let Inst{31-26} = 0b010110; + let Inst{25-21} = rt; + let Inst{20-16} = rd; + let Inst{15-12} = 0b0000; + let Inst{11-6} = 0b101100; + let Inst{5-0} = 0b111100; +} + +class PCREL_1RIMM18_FM_MMR6 { + bits<5> rt; + bits<18> offset; + + bits<32> Inst; + + let Inst{31-26} = 0b011110; + let Inst{25-21} = rt; + let Inst{20-18} = 0b110; + let Inst{17-0} = offset; +} + +class POOL32C_2ROFFSET9_FM_MMR6 funct> { + bits<5> rt; + bits<21> addr; + bits<5> base = addr{20-16}; + bits<9> offset = addr{8-0}; + + bits<32> Inst; + + let Inst{31-26} = 0b011000; + let Inst{25-21} = rt; + let Inst{20-16} = base; + let Inst{15-12} = funct; + let Inst{11-9} = 0b000; + let Inst{8-0} = offset; +} + +class POOL32S_3RSA_FM_MMR6 { + bits<5> rs; + bits<5> rt; + bits<5> rd; + bits<2> imm; + + bits<32> Inst; + + let Inst{31-26} = 0b010110; + let Inst{25-21} = rs; + let Inst{20-16} = rt; + let Inst{15-11} = rd; + let Inst{10-9} = imm; + let Inst{8-6} = 0b100; + let Inst{5-0} = 0b000100; +} + +class PCREL_1ROFFSET19_FM_MMR6 { + bits<5> rs; + bits<19> offset; + + bits<32> Inst; + + let Inst{31-26} = 0b011110; + let Inst{25-21} = rs; + let Inst{20-19} = 0b10; + let Inst{18-0} = offset; +} Index: lib/Target/Mips/MicroMips64r6InstrInfo.td =================================================================== --- lib/Target/Mips/MicroMips64r6InstrInfo.td +++ lib/Target/Mips/MicroMips64r6InstrInfo.td @@ -28,6 +28,12 @@ class DMOD_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"dmod", 0b101011000>; class DDIVU_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"ddivu", 0b110011000>; class DMODU_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"dmodu", 0b111011000>; +class DBITSWAP_MM64R6_ENC : POOL32A_2R_FM_MM64R6; +class LDPC_MM64R6_ENC : PCREL_1RIMM18_FM_MMR6; +class LLDX_MM64R6_ENC : POOL32C_2ROFFSET9_FM_MMR6<0b0101>; +class DLSA_MM64R6_ENC : POOL32S_3RSA_FM_MMR6; +class LWUPC_MM64R6_ENC : PCREL_1ROFFSET19_FM_MMR6; +class SCDX_MM64R6_ENC : POOL32C_2ROFFSET9_FM_MMR6<0b1101>; //===----------------------------------------------------------------------===// // @@ -90,6 +96,53 @@ class DDIVU_MM64R6_DESC : ArithLogicR<"ddivu", GPR32Opnd>; class DMODU_MM64R6_DESC : ArithLogicR<"dmodu", GPR32Opnd>; +class DBITSWAP_MM64R6_DESC : MMR6Arch<"dbitswap">, MipsR6Inst { + dag OutOperandList = (outs GPR64Opnd:$rd); + dag InOperandList = (ins GPR64Opnd:$rt); + string AsmString = !strconcat("dbitswap", "\t$rd, $rt"); + list Pattern = []; +} + +class LDPC_MM64R6_DESC : MMR6Arch<"ldpc">, MipsR6Inst { + dag OutOperandList = (outs GPR64Opnd:$rt); + dag InOperandList = (ins simm18_lsl3:$offset); + string AsmString = !strconcat("ldpc", "\t$rt, $offset"); + list Pattern = []; +} + +class DLSA_MM64R6_DESC : MMR6Arch<"dlsa">, MipsR6Inst { + dag OutOperandList = (outs GPR64Opnd:$rd); + dag InOperandList = (ins GPR64Opnd:$rs, GPR64Opnd:$rt, uimm2_plus1:$imm); + string AsmString = "dlsa\t$rt, $rs, $rd, $imm"; + list Pattern = []; +} + +class LWUPC_MM64R6_DESC : MMR6Arch<"lwupc">, MipsR6Inst { + dag OutOperandList = (outs GPR64Opnd:$rs); + dag InOperandList = (ins simm19_lsl2:$offset); + string AsmString = "lwupc\t$rs, $offset"; + list Pattern = []; +} + +class LOAD_STORE_MM64R6_DESC_BASE + : MMR6Arch, MipsR6Inst { + dag OutOperandList = (outs GPROpnd:$rt); + dag InOperandList = (ins ImmOpnd:$addr); + string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); + let DecoderMethod = "DecodeMemMMImm9"; +} + +class LLDX_MM64R6_DESC : LOAD_STORE_MM64R6_DESC_BASE<"lldx", GPR64Opnd, + mem_simm9gpr> { + let mayLoad = 1; +} + +class SCDX_MM64R6_DESC : LOAD_STORE_MM64R6_DESC_BASE<"scdx", GPR64Opnd, + mem_simm9gpr> { + let mayStore = 1; +} + //===----------------------------------------------------------------------===// // // Instruction Definitions @@ -116,4 +169,16 @@ ISA_MICROMIPS64R6; def DMODU_MM64R6 : R6MMR6Rel, DMODU_MM64R6_DESC, DMODU_MM64R6_ENC, ISA_MICROMIPS64R6; + def DBITSWAP_MM64R6 : R6MMR6Rel, DBITSWAP_MM64R6_DESC, DBITSWAP_MM64R6_ENC, + ISA_MICROMIPS64R6; + def LDPC_MM64R6 : R6MMR6Rel, LDPC_MM64R6_DESC, LDPC_MM64R6_ENC, + ISA_MICROMIPS64R6; + def LLDX_MM64R6 : R6MMR6Rel, LLDX_MM64R6_DESC, LLDX_MM64R6_ENC, + ISA_MICROMIPS64R6; + def DLSA_MM64R6 : R6MMR6Rel, DLSA_MM64R6_DESC, DLSA_MM64R6_ENC, + ISA_MICROMIPS64R6; + def LWUPC_MM64R6 : R6MMR6Rel, LWUPC_MM64R6_DESC, LWUPC_MM64R6_ENC, + ISA_MICROMIPS64R6; + def SCDX_MM64R6 : R6MMR6Rel, SCDX_MM64R6_DESC, SCDX_MM64R6_ENC, + ISA_MICROMIPS64R6; } Index: lib/Target/Mips/Mips32r6InstrInfo.td =================================================================== --- lib/Target/Mips/Mips32r6InstrInfo.td +++ lib/Target/Mips/Mips32r6InstrInfo.td @@ -705,7 +705,9 @@ def LSA_R6 : R6MMR6Rel, LSA_R6_ENC, LSA_R6_DESC, ISA_MIPS32R6; def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6; def LWPC : R6MMR6Rel, LWPC_ENC, LWPC_DESC, ISA_MIPS32R6; -def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6; +let AdditionalPredicates = [NotInMicroMips] in { + def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6; +} let AdditionalPredicates = [NotInMicroMips] in { def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6, HARDFLOAT; def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6, HARDFLOAT; Index: lib/Target/Mips/Mips64r6InstrInfo.td =================================================================== --- lib/Target/Mips/Mips64r6InstrInfo.td +++ lib/Target/Mips/Mips64r6InstrInfo.td @@ -86,8 +86,9 @@ def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6; def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6; def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6; + def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6; + def LDPC: LDPC_ENC, LDPC_DESC, ISA_MIPS64R6; } -def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6; def DCLO_R6 : DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6; def DCLZ_R6 : DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6; def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6; @@ -99,7 +100,6 @@ def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6; def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6; def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6; -def LDPC: LDPC_ENC, LDPC_DESC, ISA_MIPS64R6; def LLD_R6 : LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS32R6; def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6; let DecoderNamespace = "Mips32r6_64r6_GP64" in { Index: test/MC/Disassembler/Mips/micromips64r6/valid.txt =================================================================== --- test/MC/Disassembler/Mips/micromips64r6/valid.txt +++ test/MC/Disassembler/Mips/micromips64r6/valid.txt @@ -169,3 +169,10 @@ 0x00 0x00 0xe3 0x7c # CHECK: deret 0x00 0x00 0x47 0x7c # CHECK: di 0x00 0x0f 0x47 0x7c # CHECK: di $15 +0x10 0x64 0x01 0x00 # CHECK: aui $3, $4, 256 +0x58 0x83 0x0b 0x3c # CHECK: dbitswap $3, $4 +0x78 0x98 0x00 0x20 # CHECK: ldpc $4, 256 +0x60 0x64 0x50 0x08 # CHECK: lldx $3, 8($4) +0x58 0x83 0x2d 0x04 # CHECK: dlsa $3, $4, $5, 3 +0x78 0x50 0x00 0x43 # CHECK: lwupc $2, 268 +0x60 0x64 0xd0 0x08 # CHECK: scdx $3, 8($4) Index: test/MC/Mips/micromips64r6/invalid.s =================================================================== --- test/MC/Mips/micromips64r6/invalid.s +++ test/MC/Mips/micromips64r6/invalid.s @@ -143,3 +143,14 @@ swm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swm16 $16, $17, $ra, 8($fp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + scdx $33, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + scdx $3, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + scdx $3, 256($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + scdx $3, -257($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lldx $33, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lldx $3, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lldx $3, 256($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lldx $3, -257($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + dlsa $3, $4, $5, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected immediate in range 1 .. 4 + dlsa $3, $4, $5, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected immediate in range 1 .. 4 + dlsa $3, $4, $5, 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected immediate in range 1 .. 4 Index: test/MC/Mips/micromips64r6/valid.s =================================================================== --- test/MC/Mips/micromips64r6/valid.s +++ test/MC/Mips/micromips64r6/valid.s @@ -150,5 +150,12 @@ di # CHECK: di # encoding: [0x00,0x00,0x47,0x7c] di $0 # CHECK: di # encoding: [0x00,0x00,0x47,0x7c] di $15 # CHECK: di $15 # encoding: [0x00,0x0f,0x47,0x7c] + aui $3, $4, 256 # CHECK: aui $3, $4, 256 # encoding: [0x10,0x64,0x01,0x00] + dbitswap $3, $4 # CHECK: dbitswap $3, $4 # encoding: [0x58,0x83,0x0b,0x3c] + ldpc $4, 256 # CHECK: ldpc $4, 256 # encoding: [0x78,0x98,0x00,0x20] + lldx $3, 8($4) # CHECK: lldx $3, 8($4) # encoding: [0x60,0x64,0x50,0x08] + dlsa $3, $4, $5, 3 # CHECK: dlsa $3, $4, $5, 3 # encoding: [0x58,0x83,0x2d,0x04] + lwupc $2, 268 # CHECK: lwupc $2, 268 # encoding: [0x78,0x50,0x00,0x43] + scdx $3, 8($4) # CHECK: scdx $3, 8($4) # encoding: [0x60,0x64,0xd0,0x08] 1: