Index: lib/Target/PowerPC/PPC.td =================================================================== --- lib/Target/PowerPC/PPC.td +++ lib/Target/PowerPC/PPC.td @@ -124,6 +124,12 @@ def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true", "Enable POWER8 vector instructions", [FeatureVSX, FeatureP8Altivec]>; +def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true", + "Enable POWER9 Altivec instructions", + [FeatureP8Altivec]>; +def FeatureP9Vector : SubtargetFeature<"power9-vector", "HasP9Vector", "true", + "Enable POWER9 vector instructions", + [FeatureP8Vector, FeatureP9Altivec]>; def FeatureDirectMove : SubtargetFeature<"direct-move", "HasDirectMove", "true", "Enable Power8 direct move instructions", Index: lib/Target/PowerPC/PPCInstrFormats.td =================================================================== --- lib/Target/PowerPC/PPCInstrFormats.td +++ lib/Target/PowerPC/PPCInstrFormats.td @@ -747,6 +747,13 @@ let Inst{31} = RC; } +// e.g. [PO VRT XO VRB XO /] or [PO VRT XO VRB XO RC] +class X_RD5_XO5_RS5 opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL, + string asmstr, InstrItinClass itin, list pattern> + : XForm_base_r3xo { + let A = xo2; +} + // XX*-Form (VSX) class XX1Form opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list pattern> Index: lib/Target/PowerPC/PPCInstrVSX.td =================================================================== --- lib/Target/PowerPC/PPCInstrVSX.td +++ lib/Target/PowerPC/PPCInstrVSX.td @@ -1759,3 +1759,64 @@ def : Pat<(i64 (vector_extract v2i64:$S, i64:$Idx)), (i64 VectorExtractions.LE_VARIABLE_DWORD)>; } // IsLittleEndian, HasDirectMove + +// The following VSX instructions were introduced in Power ISA 3.0 +def HasP9Vector : Predicate<"PPCSubTarget->hasP9Vector()">; +let Predicates = [HasP9Vector] in { + + class X_VT5_XO5_VB5 opcode, bits<5> xo2, bits<10> xo, string opc, + list pattern> + : X_RD5_XO5_RS5; + + //---------------------------------------------------------------------------- + // Quad-Precision Scalar Move Instructions: + + // Copy Sign + def XSCPSGNQP : XForm_18<63, 100, + (outs vrrc:$vT), (ins vrrc:$vA, vrrc:$vB), + "xscpsgnqp $vT, $vA, $vB", IIC_VecFP, + []>; + + // Absolute/Negative Absolute/Negate + def XSABSQP : X_VT5_XO5_VB5<63, 0, 804, "xsabsqp" , []>; + def XSNABSQP : X_VT5_XO5_VB5<63, 8, 804, "xsnabsqp", []>; + def XSNEGQP : X_VT5_XO5_VB5<63, 16, 804, "xsnegqp" , []>; + + //---------------------------------------------------------------------------- + // Quad-Precision Scalar Floating-Point Arithmetic Instructions: + + class X1_VT5_VA5_VB5 opcode, bits<10> xo, string opc, + list pattern> + : XForm_1; + + class X1_VT5_VA5_VB5_Ro opcode, bits<10> xo, string opc, + list pattern> + : XForm_1 { + let RC = 1; + } + + // Add/Divide/Multiply/Square-Root/Subtract + def XSADDQP : X1_VT5_VA5_VB5 <63, 4, "xsaddqp" , []>; + def XSADDQPO : X1_VT5_VA5_VB5_Ro<63, 4, "xsaddqpo" , []>; + def XSDIVQP : X1_VT5_VA5_VB5 <63, 548, "xsdivqp" , []>; + def XSDIVQPO : X1_VT5_VA5_VB5_Ro<63, 548, "xsdivqpo" , []>; + def XSMULQP : X1_VT5_VA5_VB5 <63, 36, "xsmulqp" , []>; + def XSMULQPO : X1_VT5_VA5_VB5_Ro<63, 36, "xsmulqpo" , []>; + def XSSQRTQP : X1_VT5_VA5_VB5 <63, 804, "xssqrtqp" , []>; + def XSSQRTQPO : X1_VT5_VA5_VB5_Ro<63, 804, "xssqrtqpo" , []>; + def XSSUBQP : X1_VT5_VA5_VB5 <63, 516, "xssubqp" , []>; + def XSSUBQPO : X1_VT5_VA5_VB5_Ro<63, 516, "xssubqpo" , []>; + + // (Negative) Multiply-Add/Subtract + def XSMADDQP : X1_VT5_VA5_VB5 <63, 388, "xsmaddqp" , []>; + def XSMADDQPO : X1_VT5_VA5_VB5_Ro<63, 388, "xsmaddqpo" , []>; + def XSMSUBQP : X1_VT5_VA5_VB5 <63, 420, "xsmsubqp" , []>; + def XSMSUBQPO : X1_VT5_VA5_VB5_Ro<63, 420, "xsmsubqpo" , []>; + def XSNMADDQP : X1_VT5_VA5_VB5 <63, 452, "xsnmaddqp" , []>; + def XSNMADDQPO: X1_VT5_VA5_VB5_Ro<63, 452, "xsnmaddqpo", []>; + def XSNMSUBQP : X1_VT5_VA5_VB5 <63, 484, "xsnmsubqp" , []>; + def XSNMSUBQPO: X1_VT5_VA5_VB5_Ro<63, 484, "xsnmsubqpo", []>; +} // end HasP9Vector Index: lib/Target/PowerPC/PPCSubtarget.h =================================================================== --- lib/Target/PowerPC/PPCSubtarget.h +++ lib/Target/PowerPC/PPCSubtarget.h @@ -92,6 +92,8 @@ bool HasP8Vector; bool HasP8Altivec; bool HasP8Crypto; + bool HasP9Vector; + bool HasP9Altivec; bool HasFCPSGN; bool HasFSQRT; bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES; @@ -229,6 +231,8 @@ bool hasP8Vector() const { return HasP8Vector; } bool hasP8Altivec() const { return HasP8Altivec; } bool hasP8Crypto() const { return HasP8Crypto; } + bool hasP9Vector() const { return HasP9Vector; } + bool hasP9Altivec() const { return HasP9Altivec; } bool hasMFOCRF() const { return HasMFOCRF; } bool hasISEL() const { return HasISEL; } bool hasPOPCNTD() const { return HasPOPCNTD; } Index: lib/Target/PowerPC/PPCSubtarget.cpp =================================================================== --- lib/Target/PowerPC/PPCSubtarget.cpp +++ lib/Target/PowerPC/PPCSubtarget.cpp @@ -70,6 +70,8 @@ HasP8Vector = false; HasP8Altivec = false; HasP8Crypto = false; + HasP9Vector = false; + HasP9Altivec = false; HasFCPSGN = false; HasFSQRT = false; HasFRE = false; Index: lib/Target/PowerPC/README_P9.txt =================================================================== --- /dev/null +++ lib/Target/PowerPC/README_P9.txt @@ -0,0 +1,24 @@ +//===- README_P9.txt - Notes for improving Power9 code gen ----------------===// + +TODO: Instructions Need Implement Instrinstics or Map to LLVM IR + +Altivec: + +VSX: +- Copy Sign: xscpsgnqp + map to llvm fcopysign? + +- xsabsqp xsnabsqp xsnegqp + use intrinsic (like "class VX1_Int_Ty" in PPCInstrAltivec.td)? + +- xsaddqp xsdivqp xsmulqp xssqrtqp xssubqp: + - map to the following llvm ir: + fadd fdiv fmul fsqrt fsub + + - rounding version has no pattern match? + +- xsmaddqp xsmsubqp xsnmaddqp xsnmsubqp + - map to the following llvm ir: + fma fma+fneg fneg+fma fneg+fma+fneg + + - rounding version has no pattern match? Index: test/MC/Disassembler/PowerPC/vsx.txt =================================================================== --- test/MC/Disassembler/PowerPC/vsx.txt +++ test/MC/Disassembler/PowerPC/vsx.txt @@ -539,3 +539,71 @@ # CHECK: mtvsrwz 0, 3 0x7c 0x03 0x01 0xe6 + +# Power9 Instructions: + +# CHECK: xscpsgnqp 7, 31, 27 +0xfc 0xff 0xd8 0xc8 + +# CHECK: xsabsqp 7, 27 +0xfc 0xe0 0xde 0x48 + +# CHECK: xsnegqp 7, 27 +0xfc 0xf0 0xde 0x48 + +# CHECK: xsnabsqp 7, 27 +0xfc 0xe8 0xde 0x48 + +# CHECK: xsaddqp 7, 31, 27 +0xfc 0xff 0xd8 0x08 + +# CHECK: xsaddqpo 7, 31, 27 +0xfc 0xff 0xd8 0x09 + +# CHECK: xsdivqp 7, 31, 27 +0xfc 0xff 0xdc 0x48 + +# CHECK: xsdivqpo 7, 31, 27 +0xfc 0xff 0xdc 0x49 + +# CHECK: xsmulqp 7, 31, 27 +0xfc 0xff 0xd8 0x48 + +# CHECK: xsmulqpo 7, 31, 27 +0xfc 0xff 0xd8 0x49 + +# CHECK: xssqrtqp 7, 31, 27 +0xfc 0xff 0xde 0x48 + +# CHECK: xssqrtqpo 7, 31, 27 +0xfc 0xff 0xde 0x49 + +# CHECK: xssubqp 7, 31, 27 +0xfc 0xff 0xdc 0x08 + +# CHECK: xssubqpo 7, 31, 27 +0xfc 0xff 0xdc 0x09 + +# CHECK: xsmaddqp 7, 31, 27 +0xfc 0xff 0xdb 0x08 + +# CHECK: xsmaddqpo 7, 31, 27 +0xfc 0xff 0xdb 0x09 + +# CHECK: xsmsubqp 7, 31, 27 +0xfc 0xff 0xdb 0x48 + +# CHECK: xsmsubqpo 7, 31, 27 +0xfc 0xff 0xdb 0x49 + +# CHECK: xsnmaddqp 7, 31, 27 +0xfc 0xff 0xdb 0x88 + +# CHECK: xsnmaddqpo 7, 31, 27 +0xfc 0xff 0xdb 0x89 + +# CHECK: xsnmsubqp 7, 31, 27 +0xfc 0xff 0xdb 0xc8 + +# CHECK: xsnmsubqpo 7, 31, 27 +0xfc 0xff 0xdb 0xc9 Index: test/MC/PowerPC/vsx.s =================================================================== --- test/MC/PowerPC/vsx.s +++ test/MC/PowerPC/vsx.s @@ -547,3 +547,79 @@ # CHECK-BE: mtvsrwz 0, 3 # encoding: [0x7c,0x03,0x01,0xe6] # CHECK-LE: mtvsrwz 0, 3 # encoding: [0xe6,0x01,0x03,0x7c] mtvsrwz 0, 3 + +# Power9 Instructions: + +# Copy Sign +# CHECK-BE: xscpsgnqp 7, 31, 27 # encoding: [0xfc,0xff,0xd8,0xc8] +# CHECK-LE: xscpsgnqp 7, 31, 27 # encoding: [0xc8,0xd8,0xff,0xfc] + xscpsgnqp 7, 31, 27 + +# Absolute/Negative Absolute/Negate +# CHECK-BE: xsabsqp 7, 27 # encoding: [0xfc,0xe0,0xde,0x48] +# CHECK-LE: xsabsqp 7, 27 # encoding: [0x48,0xde,0xe0,0xfc] + xsabsqp 7, 27 +# CHECK-BE: xsnegqp 7, 27 # encoding: [0xfc,0xf0,0xde,0x48] +# CHECK-LE: xsnegqp 7, 27 # encoding: [0x48,0xde,0xf0,0xfc] + xsnegqp 7, 27 +# CHECK-BE: xsnabsqp 7, 27 # encoding: [0xfc,0xe8,0xde,0x48] +# CHECK-LE: xsnabsqp 7, 27 # encoding: [0x48,0xde,0xe8,0xfc] + xsnabsqp 7, 27 + +# Add/Divide/Multiply/Square-Root/Subtract +# CHECK-BE: xsaddqp 7, 31, 27 # encoding: [0xfc,0xff,0xd8,0x08] +# CHECK-LE: xsaddqp 7, 31, 27 # encoding: [0x08,0xd8,0xff,0xfc] + xsaddqp 7, 31, 27 +# CHECK-BE: xsaddqpo 7, 31, 27 # encoding: [0xfc,0xff,0xd8,0x09] +# CHECK-LE: xsaddqpo 7, 31, 27 # encoding: [0x09,0xd8,0xff,0xfc] + xsaddqpo 7, 31, 27 +# CHECK-BE: xsdivqp 7, 31, 27 # encoding: [0xfc,0xff,0xdc,0x48] +# CHECK-LE: xsdivqp 7, 31, 27 # encoding: [0x48,0xdc,0xff,0xfc] + xsdivqp 7, 31, 27 +# CHECK-BE: xsdivqpo 7, 31, 27 # encoding: [0xfc,0xff,0xdc,0x49] +# CHECK-LE: xsdivqpo 7, 31, 27 # encoding: [0x49,0xdc,0xff,0xfc] + xsdivqpo 7, 31, 27 +# CHECK-BE: xsmulqp 7, 31, 27 # encoding: [0xfc,0xff,0xd8,0x48] +# CHECK-LE: xsmulqp 7, 31, 27 # encoding: [0x48,0xd8,0xff,0xfc] + xsmulqp 7, 31, 27 +# CHECK-BE: xsmulqpo 7, 31, 27 # encoding: [0xfc,0xff,0xd8,0x49] +# CHECK-LE: xsmulqpo 7, 31, 27 # encoding: [0x49,0xd8,0xff,0xfc] + xsmulqpo 7, 31, 27 +# CHECK-BE: xssqrtqp 7, 31, 27 # encoding: [0xfc,0xff,0xde,0x48] +# CHECK-LE: xssqrtqp 7, 31, 27 # encoding: [0x48,0xde,0xff,0xfc] + xssqrtqp 7, 31, 27 +# CHECK-BE: xssqrtqpo 7, 31, 27 # encoding: [0xfc,0xff,0xde,0x49] +# CHECK-LE: xssqrtqpo 7, 31, 27 # encoding: [0x49,0xde,0xff,0xfc] + xssqrtqpo 7, 31, 27 +# CHECK-BE: xssubqp 7, 31, 27 # encoding: [0xfc,0xff,0xdc,0x08] +# CHECK-LE: xssubqp 7, 31, 27 # encoding: [0x08,0xdc,0xff,0xfc] + xssubqp 7, 31, 27 +# CHECK-BE: xssubqpo 7, 31, 27 # encoding: [0xfc,0xff,0xdc,0x09] +# CHECK-LE: xssubqpo 7, 31, 27 # encoding: [0x09,0xdc,0xff,0xfc] + xssubqpo 7, 31, 27 + +# (Negative) Multiply-Add/Subtract +# CHECK-BE: xsmaddqp 7, 31, 27 # encoding: [0xfc,0xff,0xdb,0x08] +# CHECK-LE: xsmaddqp 7, 31, 27 # encoding: [0x08,0xdb,0xff,0xfc] + xsmaddqp 7, 31, 27 +# CHECK-BE: xsmaddqpo 7, 31, 27 # encoding: [0xfc,0xff,0xdb,0x09] +# CHECK-LE: xsmaddqpo 7, 31, 27 # encoding: [0x09,0xdb,0xff,0xfc] + xsmaddqpo 7, 31, 27 +# CHECK-BE: xsmsubqp 7, 31, 27 # encoding: [0xfc,0xff,0xdb,0x48] +# CHECK-LE: xsmsubqp 7, 31, 27 # encoding: [0x48,0xdb,0xff,0xfc] + xsmsubqp 7, 31, 27 +# CHECK-BE: xsmsubqpo 7, 31, 27 # encoding: [0xfc,0xff,0xdb,0x49] +# CHECK-LE: xsmsubqpo 7, 31, 27 # encoding: [0x49,0xdb,0xff,0xfc] + xsmsubqpo 7, 31, 27 +# CHECK-BE: xsnmaddqp 7, 31, 27 # encoding: [0xfc,0xff,0xdb,0x88] +# CHECK-LE: xsnmaddqp 7, 31, 27 # encoding: [0x88,0xdb,0xff,0xfc] + xsnmaddqp 7, 31, 27 +# CHECK-BE: xsnmaddqpo 7, 31, 27 # encoding: [0xfc,0xff,0xdb,0x89] +# CHECK-LE: xsnmaddqpo 7, 31, 27 # encoding: [0x89,0xdb,0xff,0xfc] + xsnmaddqpo 7, 31, 27 +# CHECK-BE: xsnmsubqp 7, 31, 27 # encoding: [0xfc,0xff,0xdb,0xc8] +# CHECK-LE: xsnmsubqp 7, 31, 27 # encoding: [0xc8,0xdb,0xff,0xfc] + xsnmsubqp 7, 31, 27 +# CHECK-BE: xsnmsubqpo 7, 31, 27 # encoding: [0xfc,0xff,0xdb,0xc9] +# CHECK-LE: xsnmsubqpo 7, 31, 27 # encoding: [0xc9,0xdb,0xff,0xfc] + xsnmsubqpo 7, 31, 27