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Differential D16051

[LLDB][MIPS] Merge emulation of similar instructions for MIPS64
ClosedPublic

Authored by bhushan on Jan 11 2016, 1:37 AM.

Details

Reviewers
clayborg
Summary

Currently there is a separate emulation function for each branch instruction, however the emulation logic is almost identical for many of these instructions.
This patch merges emulation of similar instructions into a single function (wherever possible) to remove code duplication.

Diff Detail

Repository
rL LLVM

Event Timeline

bhushan updated this revision to Diff 44440.Jan 11 2016, 1:37 AM
bhushan retitled this revision from to [LLDB][MIPS] Merge emulation of similar instructions for MIPS64.
bhushan updated this object.
bhushan added a reviewer: clayborg.
bhushan set the repository for this revision to rL LLVM.
bhushan added subscribers: lldb-commits, nitesh.jain, mohit.bhakkad and 2 others.
clayborg accepted this revision.Jan 11 2016, 10:52 AM
clayborg edited edge metadata.

Looks good.

This revision is now accepted and ready to land.Jan 11 2016, 10:52 AM
bhushan closed this revision.Jan 12 2016, 7:39 PM

Closed by commit http://reviews.llvm.org/rL257442

Revision Contents

PathSize
source/
Plugins/
Instruction/
MIPS64/
130 lines
2086 lines

Diff 44440

source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h

Show First 20 Lines • Show All 127 Lines • ▼ Show 20 Linesprotected:
bool bool
Emulate_LDST_Imm (llvm::MCInst& insn); Emulate_LDST_Imm (llvm::MCInst& insn);
bool bool
Emulate_LDST_Reg (llvm::MCInst& insn); Emulate_LDST_Reg (llvm::MCInst& insn);
bool bool
Emulate_BEQ (llvm::MCInst& insn); Emulate_BXX_3ops (llvm::MCInst& insn);
bool bool
Emulate_BNE (llvm::MCInst& insn); Emulate_BXX_3ops_C (llvm::MCInst& insn);
bool bool
Emulate_BEQL (llvm::MCInst& insn); Emulate_BXX_2ops (llvm::MCInst& insn);
bool bool
Emulate_BNEL (llvm::MCInst& insn); Emulate_BXX_2ops_C (llvm::MCInst& insn);
bool bool
Emulate_BGEZALL (llvm::MCInst& insn); Emulate_Bcond_Link_C (llvm::MCInst& insn);
bool bool
Emulate_BAL (llvm::MCInst& insn); Emulate_Bcond_Link (llvm::MCInst& insn);
bool
Emulate_BGEZAL (llvm::MCInst& insn);
bool
Emulate_BALC (llvm::MCInst& insn);
bool
Emulate_BC (llvm::MCInst& insn);
bool
Emulate_BGEZ (llvm::MCInst& insn);
bool
Emulate_BLEZALC (llvm::MCInst& insn);
bool
Emulate_BGEZALC (llvm::MCInst& insn);
bool
Emulate_BLTZALC (llvm::MCInst& insn);
bool
Emulate_BGTZALC (llvm::MCInst& insn);
bool
Emulate_BEQZALC (llvm::MCInst& insn);
bool
Emulate_BNEZALC (llvm::MCInst& insn);
bool
Emulate_BEQC (llvm::MCInst& insn);
bool
Emulate_BNEC (llvm::MCInst& insn);
bool
Emulate_BLTC (llvm::MCInst& insn);
bool
Emulate_BGEC (llvm::MCInst& insn);
bool
Emulate_BLTUC (llvm::MCInst& insn);
bool
Emulate_BGEUC (llvm::MCInst& insn);
bool
Emulate_BLTZC (llvm::MCInst& insn);
bool
Emulate_BLEZC (llvm::MCInst& insn);
bool bool
Emulate_BGEZC (llvm::MCInst& insn); Emulate_FP_branch (llvm::MCInst& insn);
bool bool
Emulate_BGTZC (llvm::MCInst& insn); Emulate_3D_branch (llvm::MCInst& insn);
bool bool
Emulate_BEQZC (llvm::MCInst& insn); Emulate_BAL (llvm::MCInst& insn);
bool
Emulate_BNEZC (llvm::MCInst& insn);
bool
Emulate_BGEZL (llvm::MCInst& insn);
bool
Emulate_BGTZ (llvm::MCInst& insn);
bool
Emulate_BGTZL (llvm::MCInst& insn);
bool
Emulate_BLEZ (llvm::MCInst& insn);
bool
Emulate_BLEZL (llvm::MCInst& insn);
bool
Emulate_BLTZ (llvm::MCInst& insn);
bool
Emulate_BLTZAL (llvm::MCInst& insn);
bool
Emulate_BLTZALL (llvm::MCInst& insn);
bool
Emulate_BLTZL (llvm::MCInst& insn);
bool bool
Emulate_BOVC (llvm::MCInst& insn); Emulate_BALC (llvm::MCInst& insn);
bool bool
Emulate_BNVC (llvm::MCInst& insn); Emulate_BC (llvm::MCInst& insn);
bool bool
Emulate_J (llvm::MCInst& insn); Emulate_J (llvm::MCInst& insn);
bool bool
Emulate_JAL (llvm::MCInst& insn); Emulate_JAL (llvm::MCInst& insn);
bool bool
Emulate_JALR (llvm::MCInst& insn); Emulate_JALR (llvm::MCInst& insn);
bool bool
Emulate_JIALC (llvm::MCInst& insn); Emulate_JIALC (llvm::MCInst& insn);
bool bool
Emulate_JIC (llvm::MCInst& insn); Emulate_JIC (llvm::MCInst& insn);
bool bool
Emulate_JR (llvm::MCInst& insn); Emulate_JR (llvm::MCInst& insn);
bool bool
Emulate_BC1F (llvm::MCInst& insn);
bool
Emulate_BC1T (llvm::MCInst& insn);
bool
Emulate_BC1FL (llvm::MCInst& insn);
bool
Emulate_BC1TL (llvm::MCInst& insn);
bool
Emulate_BC1EQZ (llvm::MCInst& insn); Emulate_BC1EQZ (llvm::MCInst& insn);
bool bool
Emulate_BC1NEZ (llvm::MCInst& insn); Emulate_BC1NEZ (llvm::MCInst& insn);
bool bool
Emulate_BC1ANY2F (llvm::MCInst& insn);
bool
Emulate_BC1ANY2T (llvm::MCInst& insn);
bool
Emulate_BC1ANY4F (llvm::MCInst& insn);
bool
Emulate_BC1ANY4T (llvm::MCInst& insn);
bool
Emulate_BNZB (llvm::MCInst& insn); Emulate_BNZB (llvm::MCInst& insn);
bool bool
Emulate_BNZH (llvm::MCInst& insn); Emulate_BNZH (llvm::MCInst& insn);
bool bool
Emulate_BNZW (llvm::MCInst& insn); Emulate_BNZW (llvm::MCInst& insn);
▲ Show 20 Lines • Show All 43 Lines • Show Last 20 Lines

source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp

Show First 20 Lines • Show All 543 Lines • ▼ Show 20 Lines g_opcodes[] =
{ "SWLE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SWLE rt, offset(base)" }, { "SWLE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SWLE rt, offset(base)" },
{ "SWR", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SWR rt, offset(base)" }, { "SWR", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SWR rt, offset(base)" },
{ "SWRE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SWRE rt, offset(base)" }, { "SWRE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SWRE rt, offset(base)" },
{ "SWXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg, "SWXC1 fs, index (base)" }, { "SWXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg, "SWXC1 fs, index (base)" },
//---------------------------------------------------------------------- //----------------------------------------------------------------------
// Branch instructions // Branch instructions
//---------------------------------------------------------------------- //----------------------------------------------------------------------
{ "BEQ", &EmulateInstructionMIPS64::Emulate_BEQ, "BEQ rs,rt,offset" }, { "BEQ", &EmulateInstructionMIPS64::Emulate_BXX_3ops, "BEQ rs,rt,offset" },
{ "BNE", &EmulateInstructionMIPS64::Emulate_BNE, "BNE rs,rt,offset" }, { "BNE", &EmulateInstructionMIPS64::Emulate_BXX_3ops, "BNE rs,rt,offset" },
{ "BEQL", &EmulateInstructionMIPS64::Emulate_BEQL, "BEQL rs,rt,offset" }, { "BEQL", &EmulateInstructionMIPS64::Emulate_BXX_3ops, "BEQL rs,rt,offset" },
{ "BNEL", &EmulateInstructionMIPS64::Emulate_BNEL, "BNEL rs,rt,offset" }, { "BNEL", &EmulateInstructionMIPS64::Emulate_BXX_3ops, "BNEL rs,rt,offset" },
{ "BGEZALL", &EmulateInstructionMIPS64::Emulate_BGEZALL, "BGEZALL rt,offset" }, { "BGEZALL", &EmulateInstructionMIPS64::Emulate_Bcond_Link, "BGEZALL rt,offset" },
{ "BAL", &EmulateInstructionMIPS64::Emulate_BAL, "BAL offset" }, { "BAL", &EmulateInstructionMIPS64::Emulate_BAL, "BAL offset" },
{ "BGEZAL", &EmulateInstructionMIPS64::Emulate_BGEZAL, "BGEZAL rs,offset" }, { "BGEZAL", &EmulateInstructionMIPS64::Emulate_Bcond_Link, "BGEZAL rs,offset" },
{ "BALC", &EmulateInstructionMIPS64::Emulate_BALC, "BALC offset" }, { "BALC", &EmulateInstructionMIPS64::Emulate_BALC, "BALC offset" },
{ "BC", &EmulateInstructionMIPS64::Emulate_BC, "BC offset" }, { "BC", &EmulateInstructionMIPS64::Emulate_BC, "BC offset" },
{ "BGEZ", &EmulateInstructionMIPS64::Emulate_BGEZ, "BGEZ rs,offset" }, { "BGEZ", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BGEZ rs,offset" },
{ "BLEZALC", &EmulateInstructionMIPS64::Emulate_BLEZALC, "BLEZALC rs,offset" }, { "BLEZALC", &EmulateInstructionMIPS64::Emulate_Bcond_Link_C,"BLEZALC rs,offset" },
{ "BGEZALC", &EmulateInstructionMIPS64::Emulate_BGEZALC, "BGEZALC rs,offset" }, { "BGEZALC", &EmulateInstructionMIPS64::Emulate_Bcond_Link_C,"BGEZALC rs,offset" },
{ "BLTZALC", &EmulateInstructionMIPS64::Emulate_BLTZALC, "BLTZALC rs,offset" }, { "BLTZALC", &EmulateInstructionMIPS64::Emulate_Bcond_Link_C,"BLTZALC rs,offset" },
{ "BGTZALC", &EmulateInstructionMIPS64::Emulate_BGTZALC, "BGTZALC rs,offset" }, { "BGTZALC", &EmulateInstructionMIPS64::Emulate_Bcond_Link_C,"BGTZALC rs,offset" },
{ "BEQZALC", &EmulateInstructionMIPS64::Emulate_BEQZALC, "BEQZALC rs,offset" }, { "BEQZALC", &EmulateInstructionMIPS64::Emulate_Bcond_Link_C,"BEQZALC rs,offset" },
{ "BNEZALC", &EmulateInstructionMIPS64::Emulate_BNEZALC, "BNEZALC rs,offset" }, { "BNEZALC", &EmulateInstructionMIPS64::Emulate_Bcond_Link_C,"BNEZALC rs,offset" },
{ "BEQC", &EmulateInstructionMIPS64::Emulate_BEQC, "BEQC rs,rt,offset" }, { "BEQC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C, "BEQC rs,rt,offset" },
{ "BNEC", &EmulateInstructionMIPS64::Emulate_BNEC, "BNEC rs,rt,offset" }, { "BNEC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C, "BNEC rs,rt,offset" },
{ "BLTC", &EmulateInstructionMIPS64::Emulate_BLTC, "BLTC rs,rt,offset" }, { "BLTC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C, "BLTC rs,rt,offset" },
{ "BGEC", &EmulateInstructionMIPS64::Emulate_BGEC, "BGEC rs,rt,offset" }, { "BGEC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C, "BGEC rs,rt,offset" },
{ "BLTUC", &EmulateInstructionMIPS64::Emulate_BLTUC, "BLTUC rs,rt,offset" }, { "BLTUC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C, "BLTUC rs,rt,offset" },
{ "BGEUC", &EmulateInstructionMIPS64::Emulate_BGEUC, "BGEUC rs,rt,offset" }, { "BGEUC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C, "BGEUC rs,rt,offset" },
{ "BLTZC", &EmulateInstructionMIPS64::Emulate_BLTZC, "BLTZC rt,offset" }, { "BLTZC", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C, "BLTZC rt,offset" },
{ "BLEZC", &EmulateInstructionMIPS64::Emulate_BLEZC, "BLEZC rt,offset" }, { "BLEZC", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C, "BLEZC rt,offset" },
{ "BGEZC", &EmulateInstructionMIPS64::Emulate_BGEZC, "BGEZC rt,offset" }, { "BGEZC", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C, "BGEZC rt,offset" },
{ "BGTZC", &EmulateInstructionMIPS64::Emulate_BGTZC, "BGTZC rt,offset" }, { "BGTZC", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C, "BGTZC rt,offset" },
{ "BEQZC", &EmulateInstructionMIPS64::Emulate_BEQZC, "BEQZC rt,offset" }, { "BEQZC", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C, "BEQZC rt,offset" },
{ "BNEZC", &EmulateInstructionMIPS64::Emulate_BNEZC, "BNEZC rt,offset" }, { "BNEZC", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C, "BNEZC rt,offset" },
{ "BGEZL", &EmulateInstructionMIPS64::Emulate_BGEZL, "BGEZL rt,offset" }, { "BGEZL", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BGEZL rt,offset" },
{ "BGTZ", &EmulateInstructionMIPS64::Emulate_BGTZ, "BGTZ rt,offset" }, { "BGTZ", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BGTZ rt,offset" },
{ "BGTZL", &EmulateInstructionMIPS64::Emulate_BGTZL, "BGTZL rt,offset" }, { "BGTZL", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BGTZL rt,offset" },
{ "BLEZ", &EmulateInstructionMIPS64::Emulate_BLEZ, "BLEZ rt,offset" }, { "BLEZ", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BLEZ rt,offset" },
{ "BLEZL", &EmulateInstructionMIPS64::Emulate_BLEZL, "BLEZL rt,offset" }, { "BLEZL", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BLEZL rt,offset" },
{ "BLTZ", &EmulateInstructionMIPS64::Emulate_BLTZ, "BLTZ rt,offset" }, { "BLTZ", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BLTZ rt,offset" },
{ "BLTZAL", &EmulateInstructionMIPS64::Emulate_BLTZAL, "BLTZAL rt,offset" }, { "BLTZAL", &EmulateInstructionMIPS64::Emulate_Bcond_Link, "BLTZAL rt,offset" },
{ "BLTZALL", &EmulateInstructionMIPS64::Emulate_BLTZALL, "BLTZALL rt,offset" }, { "BLTZALL", &EmulateInstructionMIPS64::Emulate_Bcond_Link, "BLTZALL rt,offset" },
{ "BLTZL", &EmulateInstructionMIPS64::Emulate_BLTZL, "BLTZL rt,offset" }, { "BLTZL", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BLTZL rt,offset" },
{ "BOVC", &EmulateInstructionMIPS64::Emulate_BOVC, "BOVC rs,rt,offset" }, { "BOVC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C, "BOVC rs,rt,offset" },
{ "BNVC", &EmulateInstructionMIPS64::Emulate_BNVC, "BNVC rs,rt,offset" }, { "BNVC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C, "BNVC rs,rt,offset" },
{ "J", &EmulateInstructionMIPS64::Emulate_J, "J target" }, { "J", &EmulateInstructionMIPS64::Emulate_J, "J target" },
{ "JAL", &EmulateInstructionMIPS64::Emulate_JAL, "JAL target" }, { "JAL", &EmulateInstructionMIPS64::Emulate_JAL, "JAL target" },
{ "JALX", &EmulateInstructionMIPS64::Emulate_JAL, "JALX target" }, { "JALX", &EmulateInstructionMIPS64::Emulate_JAL, "JALX target" },
{ "JALR", &EmulateInstructionMIPS64::Emulate_JALR, "JALR target" }, { "JALR", &EmulateInstructionMIPS64::Emulate_JALR, "JALR target" },
{ "JALR_HB", &EmulateInstructionMIPS64::Emulate_JALR, "JALR.HB target" }, { "JALR_HB", &EmulateInstructionMIPS64::Emulate_JALR, "JALR.HB target" },
{ "JIALC", &EmulateInstructionMIPS64::Emulate_JIALC, "JIALC rt,offset" }, { "JIALC", &EmulateInstructionMIPS64::Emulate_JIALC, "JIALC rt,offset" },
{ "JIC", &EmulateInstructionMIPS64::Emulate_JIC, "JIC rt,offset" }, { "JIC", &EmulateInstructionMIPS64::Emulate_JIC, "JIC rt,offset" },
{ "JR", &EmulateInstructionMIPS64::Emulate_JR, "JR target" }, { "JR", &EmulateInstructionMIPS64::Emulate_JR, "JR target" },
{ "JR_HB", &EmulateInstructionMIPS64::Emulate_JR, "JR.HB target" }, { "JR_HB", &EmulateInstructionMIPS64::Emulate_JR, "JR.HB target" },
{ "BC1F", &EmulateInstructionMIPS64::Emulate_BC1F, "BC1F cc, offset" }, { "BC1F", &EmulateInstructionMIPS64::Emulate_FP_branch, "BC1F cc, offset" },
{ "BC1T", &EmulateInstructionMIPS64::Emulate_BC1T, "BC1T cc, offset" }, { "BC1T", &EmulateInstructionMIPS64::Emulate_FP_branch, "BC1T cc, offset" },
{ "BC1FL", &EmulateInstructionMIPS64::Emulate_BC1FL, "BC1FL cc, offset" }, { "BC1FL", &EmulateInstructionMIPS64::Emulate_FP_branch, "BC1FL cc, offset" },
{ "BC1TL", &EmulateInstructionMIPS64::Emulate_BC1TL, "BC1TL cc, offset" }, { "BC1TL", &EmulateInstructionMIPS64::Emulate_FP_branch, "BC1TL cc, offset" },
{ "BC1EQZ", &EmulateInstructionMIPS64::Emulate_BC1EQZ, "BC1EQZ ft, offset" }, { "BC1EQZ", &EmulateInstructionMIPS64::Emulate_BC1EQZ, "BC1EQZ ft, offset" },
{ "BC1NEZ", &EmulateInstructionMIPS64::Emulate_BC1NEZ, "BC1NEZ ft, offset" }, { "BC1NEZ", &EmulateInstructionMIPS64::Emulate_BC1NEZ, "BC1NEZ ft, offset" },
{ "BC1ANY2F", &EmulateInstructionMIPS64::Emulate_BC1ANY2F, "BC1ANY2F cc, offset" }, { "BC1ANY2F", &EmulateInstructionMIPS64::Emulate_3D_branch, "BC1ANY2F cc, offset" },
{ "BC1ANY2T", &EmulateInstructionMIPS64::Emulate_BC1ANY2T, "BC1ANY2T cc, offset" }, { "BC1ANY2T", &EmulateInstructionMIPS64::Emulate_3D_branch, "BC1ANY2T cc, offset" },
{ "BC1ANY4F", &EmulateInstructionMIPS64::Emulate_BC1ANY4F, "BC1ANY4F cc, offset" }, { "BC1ANY4F", &EmulateInstructionMIPS64::Emulate_3D_branch, "BC1ANY4F cc, offset" },
{ "BC1ANY4T", &EmulateInstructionMIPS64::Emulate_BC1ANY4T, "BC1ANY4T cc, offset" }, { "BC1ANY4T", &EmulateInstructionMIPS64::Emulate_3D_branch, "BC1ANY4T cc, offset" },
{ "BNZ_B", &EmulateInstructionMIPS64::Emulate_BNZB, "BNZ.b wt,s16" }, { "BNZ_B", &EmulateInstructionMIPS64::Emulate_BNZB, "BNZ.b wt,s16" },
{ "BNZ_H", &EmulateInstructionMIPS64::Emulate_BNZH, "BNZ.h wt,s16" }, { "BNZ_H", &EmulateInstructionMIPS64::Emulate_BNZH, "BNZ.h wt,s16" },
{ "BNZ_W", &EmulateInstructionMIPS64::Emulate_BNZW, "BNZ.w wt,s16" }, { "BNZ_W", &EmulateInstructionMIPS64::Emulate_BNZW, "BNZ.w wt,s16" },
{ "BNZ_D", &EmulateInstructionMIPS64::Emulate_BNZD, "BNZ.d wt,s16" }, { "BNZ_D", &EmulateInstructionMIPS64::Emulate_BNZD, "BNZ.d wt,s16" },
{ "BZ_B", &EmulateInstructionMIPS64::Emulate_BZB, "BZ.b wt,s16" }, { "BZ_B", &EmulateInstructionMIPS64::Emulate_BZB, "BZ.b wt,s16" },
{ "BZ_H", &EmulateInstructionMIPS64::Emulate_BZH, "BZ.h wt,s16" }, { "BZ_H", &EmulateInstructionMIPS64::Emulate_BZH, "BZ.h wt,s16" },
{ "BZ_W", &EmulateInstructionMIPS64::Emulate_BZW, "BZ.w wt,s16" }, { "BZ_W", &EmulateInstructionMIPS64::Emulate_BZW, "BZ.w wt,s16" },
{ "BZ_D", &EmulateInstructionMIPS64::Emulate_BZD, "BZ.d wt,s16" }, { "BZ_D", &EmulateInstructionMIPS64::Emulate_BZD, "BZ.d wt,s16" },
▲ Show 20 Lines • Show All 284 Lines • ▼ Show 20 Lines if (base == dwarf_sp_mips64 && nonvolatile_reg_p (src))
return false; return false;
return true; return true;
} }
return false; return false;
} }
bool
EmulateInstructionMIPS64::Emulate_BEQ (llvm::MCInst& insn)
{
bool success = false;
uint32_t rs, rt;
int64_t offset, pc, target, rs_val, rt_val;
/* /*
* BEQ rs, rt, offset Emulate below MIPS branch instructions.
* condition <- (GPR[rs] = GPR[rt]) BEQ, BNE : Branch on condition
* if condition then BEQL, BNEL : Branch likely
* PC = PC + sign_ext (offset << 2)
* else
* PC = PC + 4
*/ */
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg());
offset = insn.getOperand(2).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success)
return false;
rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success);
if (!success)
return false;
if (rs_val == rt_val)
target = pc + offset;
else
target = pc + 8;
Context context;
context.type = eContextRelativeBranchImmediate;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
return true;
}
bool bool
EmulateInstructionMIPS64::Emulate_BNE (llvm::MCInst& insn) EmulateInstructionMIPS64::Emulate_BXX_3ops (llvm::MCInst& insn)
{ {
bool success = false; bool success = false;
uint32_t rs, rt; uint32_t rs, rt;
int64_t offset, pc, target, rs_val, rt_val; int64_t offset, pc, rs_val, rt_val, target = 0;
const char *op_name = m_insn_info->getName (insn.getOpcode ());
/*
* BNE rs, rt, offset
* condition <- (GPR[rs] != GPR[rt])
* if condition then
* PC = PC + sign_ext (offset << 2)
*/
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg());
offset = insn.getOperand(2).getImm(); offset = insn.getOperand(2).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success) if (!success)
return false; return false;
rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success) if (!success)
return false; return false;
rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success); rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success);
if (!success) if (!success)
return false; return false;
if (rs_val != rt_val) if (!strcasecmp (op_name, "BEQ") ||
target = pc + offset; !strcasecmp (op_name, "BEQL"))
else
target = pc + 8;
Context context;
context.type = eContextRelativeBranchImmediate;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
return true;
}
bool
EmulateInstructionMIPS64::Emulate_BEQL (llvm::MCInst& insn)
{ {
bool success = false;
uint32_t rs, rt;
int64_t offset, pc, target, rs_val, rt_val;
/*
* BEQL rs, rt, offset
* condition <- (GPR[rs] = GPR[rt])
* if condition then
* PC = PC + sign_ext (offset << 2)
*/
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg());
offset = insn.getOperand(2).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success)
return false;
rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success);
if (!success)
return false;
if (rs_val == rt_val) if (rs_val == rt_val)
target = pc + offset; target = pc + offset;
else else
target = pc + 8; /* skip delay slot */ target = pc + 8;
Context context;
context.type = eContextRelativeBranchImmediate;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
return true;
} }
else if (!strcasecmp (op_name, "BNE") ||
bool !strcasecmp (op_name, "BNEL"))
EmulateInstructionMIPS64::Emulate_BNEL (llvm::MCInst& insn)
{ {
bool success = false;
uint32_t rs, rt;
int64_t offset, pc, target, rs_val, rt_val;
/*
* BNEL rs, rt, offset
* condition <- (GPR[rs] != GPR[rt])
* if condition then
* PC = PC + sign_ext (offset << 2)
*/
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg());
offset = insn.getOperand(2).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success)
return false;
rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success);
if (!success)
return false;
if (rs_val != rt_val) if (rs_val != rt_val)
target = pc + offset; target = pc + offset;
else else
target = pc + 8; /* skip delay slot */ target = pc + 8;
Context context;
context.type = eContextRelativeBranchImmediate;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
return true;
}
bool
EmulateInstructionMIPS64::Emulate_BGEZL (llvm::MCInst& insn)
{
bool success = false;
uint32_t rs;
int64_t offset, pc, target;
int64_t rs_val;
/*
* BGEZL rs, offset
* condition <- (GPR[rs] >= 0)
* if condition then
* PC = PC + sign_ext (offset << 2)
*/
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success)
return false;
if (rs_val >= 0)
target = pc + offset;
else
target = pc + 8; /* skip delay slot */
Context context;
context.type = eContextRelativeBranchImmediate;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
return true;
}
bool
EmulateInstructionMIPS64::Emulate_BLTZL (llvm::MCInst& insn)
{
bool success = false;
uint32_t rs;
int64_t offset, pc, target;
int64_t rs_val;
/*
* BLTZL rs, offset
* condition <- (GPR[rs] < 0)
* if condition then
* PC = PC + sign_ext (offset << 2)
*/
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success)
return false;
if (rs_val < 0)
target = pc + offset;
else
target = pc + 8; /* skip delay slot */
Context context;
context.type = eContextRelativeBranchImmediate;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
return true;
}
bool
EmulateInstructionMIPS64::Emulate_BGTZL (llvm::MCInst& insn)
{
bool success = false;
uint32_t rs;
int64_t offset, pc, target;
int64_t rs_val;
/*
* BGTZL rs, offset
* condition <- (GPR[rs] > 0)
* if condition then
* PC = PC + sign_ext (offset << 2)
*/
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success)
return false;
if (rs_val > 0)
target = pc + offset;
else
target = pc + 8; /* skip delay slot */
Context context;
context.type = eContextRelativeBranchImmediate;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
return true;
} }
bool
EmulateInstructionMIPS64::Emulate_BLEZL (llvm::MCInst& insn)
{
bool success = false;
uint32_t rs;
int64_t offset, pc, target;
int64_t rs_val;
/*
* BLEZL rs, offset
* condition <- (GPR[rs] <= 0)
* if condition then
* PC = PC + sign_ext (offset << 2)
*/
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success)
return false;
if (rs_val <= 0)
target = pc + offset;
else
target = pc + 8; /* skip delay slot */
Context context; Context context;
context.type = eContextRelativeBranchImmediate; context.type = eContextRelativeBranchImmediate;
context.SetImmediate (offset);
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false; return false;
return true; return true;
} }
bool
EmulateInstructionMIPS64::Emulate_BGTZ (llvm::MCInst& insn)
{
bool success = false;
uint32_t rs;
int64_t offset, pc, target;
int64_t rs_val;
/* /*
* BGTZ rs, offset Emulate below MIPS Non-Compact conditional branch and link instructions.
* condition <- (GPR[rs] > 0) BLTZAL, BGEZAL :
* if condition then BLTZALL, BGEZALL : Branch likely
* PC = PC + sign_ext (offset << 2)
*/ */
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success)
return false;
if (rs_val > 0)
target = pc + offset;
else
target = pc + 8;
Context context;
context.type = eContextRelativeBranchImmediate;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
return true;
}
bool bool
EmulateInstructionMIPS64::Emulate_BLEZ (llvm::MCInst& insn) EmulateInstructionMIPS64::Emulate_Bcond_Link (llvm::MCInst& insn)
{ {
bool success = false; bool success = false;
uint32_t rs; uint32_t rs;
int64_t offset, pc, target; int64_t offset, pc, target = 0;
int64_t rs_val; int64_t rs_val;
const char *op_name = m_insn_info->getName (insn.getOpcode ());
/*
* BLEZ rs, offset
* condition <- (GPR[rs] <= 0)
* if condition then
* PC = PC + sign_ext (offset << 2)
*/
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm(); offset = insn.getOperand(1).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success) if (!success)
return false; return false;
rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success) if (!success)
return false; return false;
if (rs_val <= 0) if (!strcasecmp (op_name, "BLTZAL") ||
target = pc + offset; !strcasecmp (op_name, "BLTZALL"))
else
target = pc + 8;
Context context;
context.type = eContextRelativeBranchImmediate;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
return true;
}
bool
EmulateInstructionMIPS64::Emulate_BLTZ (llvm::MCInst& insn)
{ {
bool success = false;
uint32_t rs;
int64_t offset, pc, target;
int64_t rs_val;
/*
* BLTZ rs, offset
* condition <- (GPR[rs] < 0)
* if condition then
* PC = PC + sign_ext (offset << 2)
*/
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success)
return false;
if (rs_val < 0) if (rs_val < 0)
target = pc + offset; target = pc + offset;
else else
target = pc + 8; target = pc + 8;
Context context;
context.type = eContextRelativeBranchImmediate;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
return true;
} }
else if (!strcasecmp (op_name, "BGEZAL") ||
bool !strcasecmp (op_name, "BGEZALL"))
EmulateInstructionMIPS64::Emulate_BGEZALL (llvm::MCInst& insn)
{ {
bool success = false;
uint32_t rs;
int64_t offset, pc, target;
int64_t rs_val;
/*
* BGEZALL rt, offset
* condition <- (GPR[rs] >= 0)
* if condition then
* PC = PC + sign_ext (offset << 2)
*/
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success)
return false;
if (rs_val >= 0) if (rs_val >= 0)
target = pc + offset; target = pc + offset;
else else
target = pc + 8; /* skip delay slot */ target = pc + 8;
}
Context context; Context context;
context.type = eContextRelativeBranchImmediate;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false; return false;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 8)) if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 8))
return false; return false;
return true; return true;
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false; return false;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 4)) if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 4))
return false; return false;
return true; return true;
} }
bool
EmulateInstructionMIPS64::Emulate_BGEZAL (llvm::MCInst& insn)
{
bool success = false;
uint32_t rs;
int64_t offset, pc, target;
int64_t rs_val;
/*
* BGEZAL rs,offset
* offset = sign_ext (offset << 2)
* condition <- (GPR[rs] >= 0)
* if condition then
* RA = PC + 8
* PC = PC + offset
*/
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success)
return false;
Context context;
if ((int64_t) rs_val >= 0)
target = pc + offset;
else
target = pc + 8;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 8))
return false;
return true;
}
bool
EmulateInstructionMIPS64::Emulate_BLTZAL (llvm::MCInst& insn)
{
bool success = false;
uint32_t rs;
int64_t offset, pc, target;
int64_t rs_val;
/* /*
* BLTZAL rs,offset Emulate below MIPS conditional branch and link instructions.
* offset = sign_ext (offset << 2) BLEZALC, BGEZALC, BLTZALC, BGTZALC, BEQZALC, BNEZALC : Compact branches
* condition <- (GPR[rs] < 0)
* if condition then
* RA = PC + 8
* PC = PC + offset
*/ */
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success)
return false;
Context context;
if ((int64_t) rs_val < 0)
target = pc + offset;
else
target = pc + 8;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 8))
return false;
return true;
}
bool bool
EmulateInstructionMIPS64::Emulate_BLTZALL (llvm::MCInst& insn) EmulateInstructionMIPS64::Emulate_Bcond_Link_C (llvm::MCInst& insn)
{ {
bool success = false; bool success = false;
uint32_t rs; uint32_t rs;
int64_t offset, pc, target; int64_t offset, pc, rs_val, target = 0;
int64_t rs_val; const char *op_name = m_insn_info->getName (insn.getOpcode ());
/*
* BLTZALL rs,offset
* offset = sign_ext (offset << 2)
* condition <- (GPR[rs] < 0)
* if condition then
* RA = PC + 8
* PC = PC + offset
*/
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm(); offset = insn.getOperand(1).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success) if (!success)
return false; return false;
rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success) if (!success)
return false; return false;
Context context; if (!strcasecmp (op_name, "BLEZALC"))
if (rs_val < 0)
target = pc + offset;
else
target = pc + 8; /* skip delay slot */
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 8))
return false;
return true;
}
bool
EmulateInstructionMIPS64::Emulate_BLEZALC (llvm::MCInst& insn)
{ {
bool success = false;
uint32_t rs;
int64_t offset, pc, target;
int64_t rs_val;
/*
* BLEZALC rs,offset
* offset = sign_ext (offset << 2)
* condition <- (GPR[rs] <= 0)
* if condition then
* RA = PC + 4
* PC = PC + offset
*/
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success)
return false;
Context context;
if (rs_val <= 0) if (rs_val <= 0)
target = pc + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 4))
return false;
return true;
} }
else if (!strcasecmp (op_name, "BGEZALC"))
bool
EmulateInstructionMIPS64::Emulate_BGEZALC (llvm::MCInst& insn)
{ {
bool success = false;
uint32_t rs;
int64_t offset, pc, target;
int64_t rs_val;
/*
* BGEZALC rs,offset
* offset = sign_ext (offset << 2)
* condition <- (GPR[rs] >= 0)
* if condition then
* RA = PC + 4
* PC = PC + offset
*/
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success)
return false;
Context context;
if (rs_val >= 0) if (rs_val >= 0)
target = pc + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 4))
return false;
return true;
} }
else if (!strcasecmp (op_name, "BLTZALC"))
bool
EmulateInstructionMIPS64::Emulate_BLTZALC (llvm::MCInst& insn)
{ {
bool success = false;
uint32_t rs;
int64_t offset, pc, target;
int64_t rs_val;
/*
* BLTZALC rs,offset
* offset = sign_ext (offset << 2)
* condition <- (GPR[rs] < 0)
* if condition then
* RA = PC + 4
* PC = PC + offset
*/
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success)
return false;
Context context;
if (rs_val < 0) if (rs_val < 0)
target = pc + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 4))
return false;
return true;
} }
else if (!strcasecmp (op_name, "BGTZALC"))
bool
EmulateInstructionMIPS64::Emulate_BGTZALC (llvm::MCInst& insn)
{ {
bool success = false;
uint32_t rs;
int64_t offset, pc, target;
int64_t rs_val;
/*
* BGTZALC rs,offset
* offset = sign_ext (offset << 2)
* condition <- (GPR[rs] > 0)
* if condition then
* RA = PC + 4
* PC = PC + offset
*/
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success)
return false;
Context context;
if (rs_val > 0) if (rs_val > 0)
target = pc + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 4))
return false;
return true;
} }
else if (!strcasecmp (op_name, "BEQZALC"))
bool
EmulateInstructionMIPS64::Emulate_BEQZALC (llvm::MCInst& insn)
{ {
bool success = false;
uint32_t rs;
int64_t offset, pc, target, rs_val;
/*
* BEQZALC rs,offset
* offset = sign_ext (offset << 2)
* condition <- (GPR[rs] == 0)
* if condition then
* RA = PC + 4
* PC = PC + offset
*/
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
pc = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success)
return false;
Context context;
if (rs_val == 0) if (rs_val == 0)
target = pc + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 4))
return false;
return true;
} }
else if (!strcasecmp (op_name, "BNEZALC"))
bool
EmulateInstructionMIPS64::Emulate_BNEZALC (llvm::MCInst& insn)
{ {
bool success = false;
uint32_t rs;
int64_t offset, pc, target, rs_val;
/*
* BNEZALC rs,offset
* offset = sign_ext (offset << 2)
* condition <- (GPR[rs] != 0)
* if condition then
* RA = PC + 4
* PC = PC + offset
*/
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success)
return false;
Context context;
if (rs_val != 0) if (rs_val != 0)
target = pc + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
}
Context context;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false; return false;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 4)) if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 4))
return false; return false;
return true; return true;
} }
/*
Emulate below MIPS branch instructions.
BLTZL, BGEZL, BGTZL, BLEZL : Branch likely
BLTZ, BGEZ, BGTZ, BLEZ : Non-compact branches
*/
bool bool
EmulateInstructionMIPS64::Emulate_BGEZ (llvm::MCInst& insn) EmulateInstructionMIPS64::Emulate_BXX_2ops (llvm::MCInst& insn)
{ {
bool success = false; bool success = false;
uint32_t rs; uint32_t rs;
int64_t offset, pc, target, rs_val; int64_t offset, pc, rs_val, target = 0;
const char *op_name = m_insn_info->getName (insn.getOpcode ());
/*
* BGEZ rs,offset
* offset = sign_ext (offset << 2)
* condition <- (GPR[rs] >= 0)
* if condition then
* PC = PC + offset
*/
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm(); offset = insn.getOperand(1).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success) if (!success)
return false; return false;
rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success) if (!success)
return false; return false;
Context context; if (!strcasecmp (op_name, "BLTZL") ||
!strcasecmp (op_name, "BLTZ"))
{
if (rs_val < 0)
target = pc + offset;
else
target = pc + 8;
}
else if (!strcasecmp (op_name, "BGEZL") ||
!strcasecmp (op_name, "BGEZ"))
{
if (rs_val >= 0) if (rs_val >= 0)
target = pc + offset; target = pc + offset;
else else
target = pc + 8; target = pc + 8;
}
else if (!strcasecmp (op_name, "BGTZL") ||
!strcasecmp (op_name, "BGTZ"))
{
if (rs_val > 0)
target = pc + offset;
else
target = pc + 8;
}
else if (!strcasecmp (op_name, "BLEZL") ||
!strcasecmp (op_name, "BLEZ"))
{
if (rs_val <= 0)
target = pc + offset;
else
target = pc + 8;
}
Context context;
context.type = eContextRelativeBranchImmediate;
context.SetImmediate (offset);
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false; return false;
return true; return true;
} }
bool bool
Show All 18 LinesEmulateInstructionMIPS64::Emulate_BC (llvm::MCInst& insn)
Context context; Context context;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false; return false;
return true; return true;
} }
static int
IsAdd64bitOverflow (int64_t a, int64_t b)
{
int64_t r = (uint64_t) a + (uint64_t) b;
return (a < 0 && b < 0 && r >= 0) || (a >= 0 && b >= 0 && r < 0);
}
/*
Emulate below MIPS branch instructions.
BEQC, BNEC, BLTC, BGEC, BLTUC, BGEUC, BOVC, BNVC: Compact branch instructions with no delay slot
*/
bool bool
EmulateInstructionMIPS64::Emulate_BEQC (llvm::MCInst& insn) EmulateInstructionMIPS64::Emulate_BXX_3ops_C (llvm::MCInst& insn)
{ {
bool success = false; bool success = false;
uint32_t rs, rt; uint32_t rs, rt;
int64_t offset, pc, target, rs_val, rt_val; int64_t offset, pc, rs_val, rt_val, target = 0;
const char *op_name = m_insn_info->getName (insn.getOpcode ());
uint32_t current_inst_size = m_insn_info->get(insn.getOpcode()).getSize();
/*
* BEQC rs, rt, offset
* condition <- (GPR[rs] = GPR[rt])
* if condition then
* PC = PC + sign_ext (offset << 2)
*/
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg());
offset = insn.getOperand(2).getImm(); offset = insn.getOperand(2).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success) if (!success)
return false; return false;
rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success) if (!success)
return false; return false;
rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success); rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success);
if (!success) if (!success)
return false; return false;
if (!strcasecmp (op_name, "BEQC"))
{
if (rs_val == rt_val) if (rs_val == rt_val)
target = pc + 4 + offset; target = pc + 4 + offset;
else else
target = pc + 4; target = pc + 4;
Context context;
context.type = eContextRelativeBranchImmediate;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
return true;
} }
else if (!strcasecmp (op_name, "BNEC"))
bool
EmulateInstructionMIPS64::Emulate_BNEC (llvm::MCInst& insn)
{ {
bool success = false;
uint32_t rs, rt;
int64_t offset, pc, target, rs_val, rt_val;
/*
* BNEC rs, rt, offset
* condition <- (GPR[rs] != GPR[rt])
* if condition then
* PC = PC + sign_ext (offset << 2)
*/
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg());
offset = insn.getOperand(2).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success)
return false;
rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success);
if (!success)
return false;
if (rs_val != rt_val) if (rs_val != rt_val)
target = pc + 4 + offset; target = pc + 4 + offset;
else else
target = pc + 4; target = pc + 4;
Context context;
context.type = eContextRelativeBranchImmediate;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
return true;
} }
else if (!strcasecmp (op_name, "BLTC"))
bool
EmulateInstructionMIPS64::Emulate_BLTC (llvm::MCInst& insn)
{ {
bool success = false;
uint32_t rs, rt;
int64_t offset, pc, target;
int64_t rs_val, rt_val;
/*
* BLTC rs, rt, offset
* condition <- (GPR[rs] < GPR[rt])
* if condition then
* PC = PC + sign_ext (offset << 2)
*/
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg());
offset = insn.getOperand(2).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success)
return false;
rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success);
if (!success)
return false;
if (rs_val < rt_val) if (rs_val < rt_val)
target = pc + 4 + offset; target = pc + 4 + offset;
else else
target = pc + 4; target = pc + 4;
Context context;
context.type = eContextRelativeBranchImmediate;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
return true;
} }
else if (!strcasecmp (op_name, "BGEC"))
bool
EmulateInstructionMIPS64::Emulate_BGEC (llvm::MCInst& insn)
{ {
bool success = false; if (rs_val >= rt_val)
uint32_t rs, rt;
int64_t offset, pc, target;
int64_t rs_val, rt_val;
/*
* BGEC rs, rt, offset
* condition <- (GPR[rs] > GPR[rt])
* if condition then
* PC = PC + sign_ext (offset << 2)
*/
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg());
offset = insn.getOperand(2).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success)
return false;
rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success);
if (!success)
return false;
if (rs_val > rt_val)
target = pc + 4 + offset; target = pc + 4 + offset;
else else
target = pc + 4; target = pc + 4;
Context context;
context.type = eContextRelativeBranchImmediate;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
return true;
} }
else if (!strcasecmp (op_name, "BLTUC"))
bool
EmulateInstructionMIPS64::Emulate_BLTUC (llvm::MCInst& insn)
{ {
bool success = false;
uint32_t rs, rt;
int64_t offset, pc, target;
uint64_t rs_val, rt_val;
/*
* BLTUC rs, rt, offset
* condition <- (GPR[rs] < GPR[rt])
* if condition then
* PC = PC + sign_ext (offset << 2)
*/
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg());
offset = insn.getOperand(2).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success)
return false;
rt_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success);
if (!success)
return false;
if (rs_val < rt_val) if (rs_val < rt_val)
target = pc + 4 + offset; target = pc + 4 + offset;
else else
target = pc + 4; target = pc + 4;
Context context;
context.type = eContextRelativeBranchImmediate;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
return true;
} }
else if (!strcasecmp (op_name, "BGEUC"))
bool
EmulateInstructionMIPS64::Emulate_BGEUC (llvm::MCInst& insn)
{ {
bool success = false; if ((uint32_t)rs_val >= (uint32_t)rt_val)
uint32_t rs, rt;
int64_t offset, pc, target;
uint64_t rs_val, rt_val;
/*
* BGEUC rs, rt, offset
* condition <- (GPR[rs] > GPR[rt])
* if condition then
* PC = PC + sign_ext (offset << 2)
*/
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg());
offset = insn.getOperand(2).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success)
return false;
rt_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success);
if (!success)
return false;
if (rs_val > rt_val)
target = pc + 4 + offset; target = pc + 4 + offset;
else else
target = pc + 4; target = pc + 4;
Context context;
context.type = eContextRelativeBranchImmediate;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
return true;
} }
else if (!strcasecmp (op_name, "BOVC"))
bool
EmulateInstructionMIPS64::Emulate_BLTZC (llvm::MCInst& insn)
{ {
bool success = false; if (IsAdd64bitOverflow (rs_val, rt_val))
uint32_t rs;
int64_t offset, pc, target;
int64_t rs_val;
/*
* BLTZC rs, offset
* condition <- (GPR[rs] < 0)
* if condition then
* PC = PC + sign_ext (offset << 2)
*/
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success)
return false;
if (rs_val < 0)
target = pc + 4 + offset; target = pc + 4 + offset;
else else
target = pc + 4; target = pc + 4;
Context context;
context.type = eContextRelativeBranchImmediate;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
return true;
} }
else if (!strcasecmp (op_name, "BNVC"))
bool
EmulateInstructionMIPS64::Emulate_BLEZC (llvm::MCInst& insn)
{ {
bool success = false; if (!IsAdd64bitOverflow (rs_val, rt_val))
uint32_t rs;
int64_t offset, pc, target;
int64_t rs_val;
/*
* BLEZC rs, offset
* condition <- (GPR[rs] <= 0)
* if condition then
* PC = PC + sign_ext (offset << 2)
*/
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success)
return false;
if (rs_val <= 0)
target = pc + 4 + offset; target = pc + 4 + offset;
else else
target = pc + 4; target = pc + 4;
}
Context context; Context context;
context.type = eContextRelativeBranchImmediate; context.type = eContextRelativeBranchImmediate;
context.SetImmediate (current_inst_size + offset);
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false; return false;
return true; return true;
} }
/*
Emulate below MIPS branch instructions.
BLTZC, BLEZC, BGEZC, BGTZC, BEQZC, BNEZC : Compact Branches
*/
bool bool
EmulateInstructionMIPS64::Emulate_BGEZC (llvm::MCInst& insn) EmulateInstructionMIPS64::Emulate_BXX_2ops_C (llvm::MCInst& insn)
{ {
bool success = false; bool success = false;
uint32_t rs; uint32_t rs;
int64_t offset, pc, target; int64_t offset, pc, target = 0;
int64_t rs_val; int64_t rs_val;
const char *op_name = m_insn_info->getName (insn.getOpcode ());
uint32_t current_inst_size = m_insn_info->get(insn.getOpcode()).getSize();
/*
* BGEZC rs, offset
* condition <- (GPR[rs] >= 0)
* if condition then
* PC = PC + sign_ext (offset << 2)
*/
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm(); offset = insn.getOperand(1).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success) if (!success)
return false; return false;
rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success) if (!success)
return false; return false;
if (rs_val >= 0) if (!strcasecmp (op_name, "BLTZC"))
{
if (rs_val < 0)
target = pc + 4 + offset; target = pc + 4 + offset;
else else
target = pc + 4; target = pc + 4;
Context context;
context.type = eContextRelativeBranchImmediate;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
return true;
} }
else if (!strcasecmp (op_name, "BLEZC"))
bool
EmulateInstructionMIPS64::Emulate_BGTZC (llvm::MCInst& insn)
{ {
bool success = false; if (rs_val <= 0)
uint32_t rs;
int64_t offset, pc, target;
int64_t rs_val;
/*
* BGTZC rs, offset
* condition <- (GPR[rs] > 0)
* if condition then
* PC = PC + sign_ext (offset << 2)
*/
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success)
return false;
if (rs_val > 0)
target = pc + 4 + offset; target = pc + 4 + offset;
else else
target = pc + 4; target = pc + 4;
Context context;
context.type = eContextRelativeBranchImmediate;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
return true;
} }
else if (!strcasecmp (op_name, "BGEZC"))
bool
EmulateInstructionMIPS64::Emulate_BEQZC (llvm::MCInst& insn)
{ {
bool success = false; if (rs_val >= 0)
uint32_t rs;
int64_t offset, pc, target;
uint64_t rs_val;
/*
* BEQZC rs, offset
* condition <- (GPR[rs] = 0)
* if condition then
* PC = PC + sign_ext (offset << 2)
*/
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success)
return false;
if (rs_val == 0)
target = pc + 4 + offset; target = pc + 4 + offset;
else else
target = pc + 4; target = pc + 4;
Context context;
context.type = eContextRelativeBranchImmediate;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
return true;
} }
else if (!strcasecmp (op_name, "BGTZC"))
bool
EmulateInstructionMIPS64::Emulate_BNEZC (llvm::MCInst& insn)
{ {
bool success = false; if (rs_val > 0)
uint32_t rs;
int64_t offset, pc, target;
uint64_t rs_val;
/*
* BNEZC rs, offset
* condition <- (GPR[rs] != 0)
* if condition then
* PC = PC + sign_ext (offset << 2)
*/
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success)
return false;
if (rs_val != 0)
target = pc + 4 + offset; target = pc + 4 + offset;
else else
target = pc + 4; target = pc + 4;
Context context;
context.type = eContextRelativeBranchImmediate;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
return true;
}
static int
IsAdd64bitOverflow (int64_t a, int64_t b)
{
int64_t r = (uint64_t) a + (uint64_t) b;
return (a < 0 && b < 0 && r >= 0) || (a >= 0 && b >= 0 && r < 0);
} }
else if (!strcasecmp (op_name, "BEQZC"))
bool
EmulateInstructionMIPS64::Emulate_BOVC (llvm::MCInst& insn)
{ {
bool success = false; if (rs_val == 0)
uint32_t rs, rt; target = pc + 4 + offset;
int64_t offset, pc, target;
int64_t rs_val, rt_val;
/*
* BOVC rs, rt, offset
* condition <- overflow(GPR[rs] + GPR[rt])
* if condition then
* PC = PC + sign_ext (offset << 2)
*/
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg());
offset = insn.getOperand(2).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success)
return false;
rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success);
if (!success)
return false;
if (IsAdd64bitOverflow (rs_val, rt_val))
target = pc + offset;
else else
target = pc + 4; target = pc + 4;
Context context;
context.type = eContextRelativeBranchImmediate;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
return true;
} }
else if (!strcasecmp (op_name, "BNEZC"))
bool
EmulateInstructionMIPS64::Emulate_BNVC (llvm::MCInst& insn)
{ {
bool success = false; if (rs_val != 0)
uint32_t rs, rt; target = pc + 4 + offset;
int64_t offset, pc, target;
int64_t rs_val, rt_val;
/*
* BNVC rs, rt, offset
* condition <- overflow(GPR[rs] + GPR[rt])
* if condition then
* PC = PC + sign_ext (offset << 2)
*/
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg());
offset = insn.getOperand(2).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success)
return false;
rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success);
if (!success)
return false;
if (! IsAdd64bitOverflow (rs_val, rt_val))
target = pc + offset;
else else
target = pc + 4; target = pc + 4;
}
Context context; Context context;
context.type = eContextRelativeBranchImmediate; context.type = eContextRelativeBranchImmediate;
context.SetImmediate (current_inst_size + offset);
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false; return false;
return true; return true;
} }
bool bool
▲ Show 20 Lines • Show All 175 Lines • ▼ Show 20 LinesEmulateInstructionMIPS64::Emulate_JR (llvm::MCInst& insn)
Context context; Context context;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, rs_val)) if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, rs_val))
return false; return false;
return true; return true;
} }
/*
Emulate Branch on FP True/False
BC1F, BC1FL : Branch on FP False (L stands for branch likely)
BC1T, BC1TL : Branch on FP True (L stands for branch likely)
*/
bool bool
EmulateInstructionMIPS64::Emulate_BC1F (llvm::MCInst& insn) EmulateInstructionMIPS64::Emulate_FP_branch (llvm::MCInst& insn)
{ {
bool success = false; bool success = false;
uint32_t cc, fcsr; uint32_t cc, fcsr;
int64_t target, pc, offset; int64_t pc, offset, target = 0;
const char *op_name = m_insn_info->getName (insn.getOpcode ());
/* /*
* BC1F cc, offset * BC1F cc, offset
* condition <- (FPConditionCode(cc) == 0) * condition <- (FPConditionCode(cc) == 0)
* if condition then * if condition then
* offset = sign_ext (offset) * offset = sign_ext (offset)
* PC = PC + offset * PC = PC + offset
*/ */
cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm(); offset = insn.getOperand(1).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success) if (!success)
return false; return false;
fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips64, 0, &success); fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips64, 0, &success);
if (!success) if (!success)
return false; return false;
/* fcsr[23], fcsr[25-31] are vaild condition bits */ /* fcsr[23], fcsr[25-31] are vaild condition bits */
fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01); fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);
if (!strcasecmp (op_name, "BC1F") ||
!strcasecmp (op_name, "BC1FL"))
{
if ((fcsr & (1 << cc)) == 0) if ((fcsr & (1 << cc)) == 0)
target = pc + offset; target = pc + offset;
else else
target = pc + 8; target = pc + 8;
Context context;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
return true;
} }
else if (!strcasecmp (op_name, "BC1T") ||
bool !strcasecmp (op_name, "BC1TL"))
EmulateInstructionMIPS64::Emulate_BC1T (llvm::MCInst& insn)
{ {
bool success = false;
uint32_t cc, fcsr;
int64_t target, pc, offset;
/*
* BC1T cc, offset
* condition <- (FPConditionCode(cc) != 0)
* if condition then
* offset = sign_ext (offset)
* PC = PC + offset
*/
cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips64, 0, &success);
if (!success)
return false;
/* fcsr[23], fcsr[25-31] are vaild condition bits */
fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);
if ((fcsr & (1 << cc)) != 0) if ((fcsr & (1 << cc)) != 0)
target = pc + offset; target = pc + offset;
else else
target = pc + 8; target = pc + 8;
Context context;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
return true;
} }
bool
EmulateInstructionMIPS64::Emulate_BC1FL (llvm::MCInst& insn)
{
bool success = false;
uint32_t cc, fcsr;
int64_t target, pc, offset;
/*
* BC1F cc, offset
* condition <- (FPConditionCode(cc) == 0)
* if condition then
* offset = sign_ext (offset)
* PC = PC + offset
*/
cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips64, 0, &success);
if (!success)
return false;
/* fcsr[23], fcsr[25-31] are vaild condition bits */
fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);
if ((fcsr & (1 << cc)) == 0)
target = pc + offset;
else
target = pc + 8; /* skip delay slot */
Context context;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
return true;
}
bool
EmulateInstructionMIPS64::Emulate_BC1TL (llvm::MCInst& insn)
{
bool success = false;
uint32_t cc, fcsr;
int64_t target, pc, offset;
/*
* BC1T cc, offset
* condition <- (FPConditionCode(cc) != 0)
* if condition then
* offset = sign_ext (offset)
* PC = PC + offset
*/
cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips64, 0, &success);
if (!success)
return false;
/* fcsr[23], fcsr[25-31] are vaild condition bits */
fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);
if ((fcsr & (1 << cc)) != 0)
target = pc + offset;
else
target = pc + 8; /* skip delay slot */
Context context; Context context;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false; return false;
return true; return true;
} }
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 LinesEmulateInstructionMIPS64::Emulate_BC1NEZ (llvm::MCInst& insn)
Context context; Context context;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false; return false;
return true; return true;
} }
/*
Emulate MIPS-3D Branch instructions
BC1ANY2F, BC1ANY2T : Branch on Any of Two Floating Point Condition Codes False/True
BC1ANY4F, BC1ANY4T : Branch on Any of Four Floating Point Condition Codes False/True
*/
bool bool
EmulateInstructionMIPS64::Emulate_BC1ANY2F (llvm::MCInst& insn) EmulateInstructionMIPS64::Emulate_3D_branch (llvm::MCInst& insn)
{ {
bool success = false; bool success = false;
uint32_t cc, fcsr; uint32_t cc, fcsr;
int64_t target, pc, offset; int64_t pc, offset, target = 0;
const char *op_name = m_insn_info->getName (insn.getOpcode ());
/*
* BC1ANY2F cc, offset
* condition <- (FPConditionCode(cc) == 0
* || FPConditionCode(cc+1) == 0)
* if condition then
* offset = sign_ext (offset)
* PC = PC + offset
*/
cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm(); offset = insn.getOperand(1).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success) if (!success)
return false; return false;
fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips64, 0, &success); fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips64, 0, &success);
if (!success) if (!success)
return false; return false;
/* fcsr[23], fcsr[25-31] are vaild condition bits */ /* fcsr[23], fcsr[25-31] are vaild condition bits */
fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01); fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);
if (!strcasecmp (op_name, "BC1ANY2F"))
{
/* if any one bit is 0 */ /* if any one bit is 0 */
if (((fcsr >> cc) & 3) != 3) if (((fcsr >> cc) & 3) != 3)
target = pc + offset; target = pc + offset;
else else
target = pc + 8; target = pc + 8;
Context context;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
return true;
} }
else if (!strcasecmp (op_name, "BC1ANY2T"))
bool
EmulateInstructionMIPS64::Emulate_BC1ANY2T (llvm::MCInst& insn)
{ {
bool success = false;
uint32_t cc, fcsr;
int64_t target, pc, offset;
/*
* BC1ANY2T cc, offset
* condition <- (FPConditionCode(cc) == 1
* || FPConditionCode(cc+1) == 1)
* if condition then
* offset = sign_ext (offset)
* PC = PC + offset
*/
cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips64, 0, &success);
if (!success)
return false;
/* fcsr[23], fcsr[25-31] are vaild condition bits */
fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);
/* if any one bit is 1 */ /* if any one bit is 1 */
if (((fcsr >> cc) & 3) != 0) if (((fcsr >> cc) & 3) != 0)
target = pc + offset; target = pc + offset;
else else
target = pc + 8; target = pc + 8;
Context context;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
return true;
} }
else if (!strcasecmp (op_name, "BC1ANY4F"))
bool
EmulateInstructionMIPS64::Emulate_BC1ANY4F (llvm::MCInst& insn)
{ {
bool success = false;
uint32_t cc, fcsr;
int64_t target, pc, offset;
/*
* BC1ANY4F cc, offset
* condition <- (FPConditionCode(cc) == 0
* || FPConditionCode(cc+1) == 0)
* || FPConditionCode(cc+2) == 0)
* || FPConditionCode(cc+3) == 0)
* if condition then
* offset = sign_ext (offset)
* PC = PC + offset
*/
cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips64, 0, &success);
if (!success)
return false;
/* fcsr[23], fcsr[25-31] are vaild condition bits */
fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);
/* if any one bit is 0 */ /* if any one bit is 0 */
if (((fcsr >> cc) & 0xf) != 0xf) if (((fcsr >> cc) & 0xf) != 0xf)
target = pc + offset; target = pc + offset;
else else
target = pc + 8; target = pc + 8;
Context context;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false;
return true;
} }
else if (!strcasecmp (op_name, "BC1ANY4T"))
bool
EmulateInstructionMIPS64::Emulate_BC1ANY4T (llvm::MCInst& insn)
{ {
bool success = false;
uint32_t cc, fcsr;
int64_t target, pc, offset;
/*
* BC1ANY4T cc, offset
* condition <- (FPConditionCode(cc) == 1
* || FPConditionCode(cc+1) == 1)
* || FPConditionCode(cc+2) == 1)
* || FPConditionCode(cc+3) == 1)
* if condition then
* offset = sign_ext (offset)
* PC = PC + offset
*/
cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success)
return false;
fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips64, 0, &success);
if (!success)
return false;
/* fcsr[23], fcsr[25-31] are vaild condition bits */
fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);
/* if any one bit is 1 */ /* if any one bit is 1 */
if (((fcsr >> cc) & 0xf) != 0) if (((fcsr >> cc) & 0xf) != 0)
target = pc + offset; target = pc + offset;
else else
target = pc + 8; target = pc + 8;
}
Context context; Context context;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false; return false;
return true; return true;
} }
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