diff --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td --- a/llvm/lib/Target/RISCV/RISCVGISel.td +++ b/llvm/lib/Target/RISCV/RISCVGISel.td @@ -15,6 +15,25 @@ include "RISCV.td" +// Return an immediate value plus 1. +def ImmPlus1 : SDNodeXFormgetTargetConstant(N->getSExtValue() + 1, SDLoc(N), + N->getValueType(0)); +}]>; + +// A 12-bit signed immediate plus one where the imm range will be [-2047, 2048]. +def simm12_plus1 : ImmLeaf(Imm) && Imm != -2048) || Imm == 2048;}]>; + +// A 12-bit signed immediate sub one and exclude zero +def simm12_minus1_nonzero : PatLeaf<(imm), [{ + if (!N->hasOneUse()) + return false; + // The immediate operand must be in range [-2049, 0) or (0, 2046]. + int64_t Imm = N->getSExtValue(); + return (Imm >= -2049 && Imm < 0) || (Imm > 0 && Imm <= 2046); +}]>; + // FIXME: This is labelled as handling 's32', however the ComplexPattern it // refers to handles both i32 and i64 based on the HwMode. Currently this LLT // parameter appears to be ignored so this pattern works for both, however we @@ -43,3 +62,32 @@ def : Pat<(i32 (udiv GPR:$rs1, GPR:$rs2)), (DIVUW GPR:$rs1, GPR:$rs2)>; def : Pat<(i32 (urem GPR:$rs1, GPR:$rs2)), (REMUW GPR:$rs1, GPR:$rs2)>; } + +// Define pattern expansions for setcc operations that aren't directly +// handled by a RISC-V instruction. +def : Pat<(XLenVT (seteq (XLenVT GPR:$rs1), 0)), (SLTIU GPR:$rs1, 1)>; +def : Pat<(XLenVT (seteq (XLenVT GPR:$rs1), GPR:$rs2)), + (SLTIU (XOR GPR:$rs1, GPR:$rs2), 1)>; +def : Pat<(XLenVT (seteq (XLenVT GPR:$rs1), simm12_plus1:$imm12)), + (SLTIU (ADDI GPR:$rs1, (NegImm simm12_plus1:$imm12)), 1)>; +def : Pat<(XLenVT (setne (XLenVT GPR:$rs1), 0)), (SLTU (XLenVT X0), GPR:$rs1)>; +def : Pat<(XLenVT (setne (XLenVT GPR:$rs1), GPR:$rs2)), + (SLTU (XLenVT X0), (XOR GPR:$rs1, GPR:$rs2))>; +def : Pat<(XLenVT (setne (XLenVT GPR:$rs1), simm12_plus1:$imm12)), + (SLTU (XLenVT X0), (ADDI GPR:$rs1, (NegImm simm12_plus1:$imm12)))>; +def : Pat<(XLenVT (setugt (XLenVT GPR:$rs1), GPR:$rs2)), + (SLTU GPR:$rs2, GPR:$rs1)>; +def : Pat<(XLenVT (setuge (XLenVT GPR:$rs1), GPR:$rs2)), + (XORI (SLTU GPR:$rs1, GPR:$rs2), 1)>; +def : Pat<(XLenVT (setule (XLenVT GPR:$rs1), GPR:$rs2)), + (XORI (SLTU GPR:$rs2, GPR:$rs1), 1)>; +def : Pat<(XLenVT (setgt (XLenVT GPR:$rs1), GPR:$rs2)), + (SLT GPR:$rs2, GPR:$rs1)>; +def : Pat<(XLenVT (setge (XLenVT GPR:$rs1), GPR:$rs2)), + (XORI (SLT GPR:$rs1, GPR:$rs2), 1)>; +def : Pat<(XLenVT (setle (XLenVT GPR:$rs1), GPR:$rs2)), + (XORI (SLT GPR:$rs2, GPR:$rs1), 1)>; +def : Pat<(XLenVT (setgt (XLenVT GPR:$rs1), simm12_minus1_nonzero:$imm)), + (XORI (SLTI GPR:$rs1, (ImmPlus1 simm12_minus1_nonzero:$imm)), 1)>; +def : Pat<(XLenVT (setugt (XLenVT GPR:$rs1), simm12_minus1_nonzero:$imm)), + (XORI (SLTIU GPR:$rs1, (ImmPlus1 simm12_minus1_nonzero:$imm)), 1)>; diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/cmp32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/cmp32.mir new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/cmp32.mir @@ -0,0 +1,563 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \ +# RUN: | FileCheck -check-prefix=RV32I %s +--- +name: cmp_ult_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_ult_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[SLTU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(ult), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_slt_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_slt_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[SLT]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(slt), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugt_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_ugt_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY1]], [[COPY]] + ; RV32I-NEXT: $x10 = COPY [[SLTU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(ugt), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgt_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_sgt_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY1]], [[COPY]] + ; RV32I-NEXT: $x10 = COPY [[SLT]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(sgt), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_eq_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_eq_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[XOR]], 1 + ; RV32I-NEXT: $x10 = COPY [[SLTIU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(eq), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ne_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_ne_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[XOR]] + ; RV32I-NEXT: $x10 = COPY [[SLTU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(ne), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ule_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_ule_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY1]], [[COPY]] + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTU]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(ule), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sle_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_sle_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY1]], [[COPY]] + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLT]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(sle), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_uge_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_uge_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTU]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(uge), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sge_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_sge_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLT]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(sge), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ulti_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_ulti_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[COPY]], 10 + ; RV32I-NEXT: $x10 = COPY [[SLTIU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 10 + %2:gprb(s32) = G_ICMP intpred(ult), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_slti_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_slti_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[SLTI:%[0-9]+]]:gpr = SLTI [[COPY]], 10 + ; RV32I-NEXT: $x10 = COPY [[SLTI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 10 + %2:gprb(s32) = G_ICMP intpred(slt), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugti_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_ugti_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[ADDI]], [[COPY]] + ; RV32I-NEXT: $x10 = COPY [[SLTU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 10 + %2:gprb(s32) = G_ICMP intpred(ugt), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgti_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_sgti_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; RV32I-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[ADDI]], [[COPY]] + ; RV32I-NEXT: $x10 = COPY [[SLT]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 10 + %2:gprb(s32) = G_ICMP intpred(sgt), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_eqi_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_eqi_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; RV32I-NEXT: [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[ADDI]] + ; RV32I-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[XOR]], 1 + ; RV32I-NEXT: $x10 = COPY [[SLTIU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 10 + %2:gprb(s32) = G_ICMP intpred(eq), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_nei_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_nei_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; RV32I-NEXT: [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[ADDI]] + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[XOR]] + ; RV32I-NEXT: $x10 = COPY [[SLTU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 10 + %2:gprb(s32) = G_ICMP intpred(ne), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ulei_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_ulei_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[ADDI]], [[COPY]] + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTU]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 10 + %2:gprb(s32) = G_ICMP intpred(ule), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_slei_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_slei_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; RV32I-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[ADDI]], [[COPY]] + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLT]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 10 + %2:gprb(s32) = G_ICMP intpred(sle), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugei_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_ugei_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[ADDI]] + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTU]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 10 + %2:gprb(s32) = G_ICMP intpred(uge), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgei_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_sgei_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; RV32I-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY]], [[ADDI]] + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLT]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 10 + %2:gprb(s32) = G_ICMP intpred(sge), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_eq0_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_eq0_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[COPY]], 1 + ; RV32I-NEXT: $x10 = COPY [[SLTIU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 0 + %2:gprb(s32) = G_ICMP intpred(eq), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ne0_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_ne0_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[COPY]] + ; RV32I-NEXT: $x10 = COPY [[SLTU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 0 + %2:gprb(s32) = G_ICMP intpred(ne), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugt_neg1_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_ugt_neg1_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1 + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[ADDI]], [[COPY]] + ; RV32I-NEXT: $x10 = COPY [[SLTU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 -1 + %2:gprb(s32) = G_ICMP intpred(ugt), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/cmp64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/cmp64.mir new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/cmp64.mir @@ -0,0 +1,565 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=riscv64 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \ +# RUN: | FileCheck -check-prefix=RV32I %s +--- +name: cmp_ult_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_ult_i64 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[SLTU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(ult), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_slt_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_slt_i64 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[SLT]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(slt), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugt_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_ugt_i64 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY1]], [[COPY]] + ; RV32I-NEXT: $x10 = COPY [[SLTU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(ugt), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgt_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_sgt_i64 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY1]], [[COPY]] + ; RV32I-NEXT: $x10 = COPY [[SLT]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(sgt), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_eq_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_eq_i64 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[XOR]], 1 + ; RV32I-NEXT: $x10 = COPY [[SLTIU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(eq), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ne_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_ne_i64 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[XOR]] + ; RV32I-NEXT: $x10 = COPY [[SLTU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(ne), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ule_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_ule_i64 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY1]], [[COPY]] + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTU]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(ule), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sle_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_sle_i64 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY1]], [[COPY]] + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLT]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(sle), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_uge_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_uge_i64 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTU]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(uge), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sge_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_sge_i64 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLT]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(sge), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ulti_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_ulti_i64 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[COPY]], 10 + ; RV32I-NEXT: $x10 = COPY [[SLTIU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 10 + %2:gprb(s64) = G_ICMP intpred(ult), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_slti_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_slti_i64 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[SLTI:%[0-9]+]]:gpr = SLTI [[COPY]], 10 + ; RV32I-NEXT: $x10 = COPY [[SLTI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 10 + %2:gprb(s64) = G_ICMP intpred(slt), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugti_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_ugti_i64 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[ADDI]], [[COPY]] + ; RV32I-NEXT: $x10 = COPY [[SLTU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 10 + %2:gprb(s64) = G_ICMP intpred(ugt), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgti_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_sgti_i64 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; RV32I-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[ADDI]], [[COPY]] + ; RV32I-NEXT: $x10 = COPY [[SLT]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 10 + %2:gprb(s64) = G_ICMP intpred(sgt), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_eqi_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_eqi_i64 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; RV32I-NEXT: [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[ADDI]] + ; RV32I-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[XOR]], 1 + ; RV32I-NEXT: $x10 = COPY [[SLTIU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 10 + %2:gprb(s64) = G_ICMP intpred(eq), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_nei_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_nei_i64 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; RV32I-NEXT: [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[ADDI]] + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[XOR]] + ; RV32I-NEXT: $x10 = COPY [[SLTU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 10 + %2:gprb(s64) = G_ICMP intpred(ne), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ulei_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_ulei_i64 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[ADDI]], [[COPY]] + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTU]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 10 + %2:gprb(s64) = G_ICMP intpred(ule), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_slei_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_slei_i64 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; RV32I-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[ADDI]], [[COPY]] + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLT]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 10 + %2:gprb(s64) = G_ICMP intpred(sle), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugei_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_ugei_i64 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[ADDI]] + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTU]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 10 + %2:gprb(s64) = G_ICMP intpred(uge), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgei_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_sgei_i64 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; RV32I-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY]], [[ADDI]] + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLT]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 10 + %2:gprb(s64) = G_ICMP intpred(sge), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_eq0_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_eq0_i64 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[COPY]], 1 + ; RV32I-NEXT: $x10 = COPY [[SLTIU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 0 + %2:gprb(s64) = G_ICMP intpred(eq), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ne0_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_ne0_i64 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; RV32I-NEXT: [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[ADDI]] + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[XOR]] + ; RV32I-NEXT: $x10 = COPY [[SLTU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 10 + %2:gprb(s64) = G_ICMP intpred(ne), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugt_neg1_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_ugt_neg1_i64 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1 + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[ADDI]], [[COPY]] + ; RV32I-NEXT: $x10 = COPY [[SLTU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 -1 + %2:gprb(s64) = G_ICMP intpred(ugt), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +...