diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -220,6 +220,8 @@ void getPostRAMutations(std::vector> &Mutations) const override; + + bool useAA() const override; }; } // End llvm namespace diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp --- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp @@ -48,6 +48,9 @@ cl::desc("The maximum cost used for building integers."), cl::init(0), cl::Hidden); +static cl::opt UseAA("riscv-use-aa", cl::init(true), + cl::desc("Enable the use of AA during codegen.")); + void RISCVSubtarget::anchor() {} RISCVSubtarget & @@ -175,3 +178,7 @@ std::vector> &Mutations) const { Mutations.push_back(createRISCVMacroFusionDAGMutation()); } + + /// Enable use of alias analysis during code generation (during MI + /// scheduling, DAGCombine, etc.). +bool RISCVSubtarget::useAA() const { return UseAA; } diff --git a/llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll b/llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll --- a/llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll +++ b/llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll @@ -15,15 +15,15 @@ ; CHECK-NEXT: slli a2, a2, 1 ; CHECK-NEXT: sub sp, sp, a2 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb -; CHECK-NEXT: addi a2, a0, 8 -; CHECK-NEXT: vl1re64.v v8, (a2) +; CHECK-NEXT: vl1re64.v v8, (a0) +; CHECK-NEXT: addi a0, a0, 8 ; CHECK-NEXT: vl1re64.v v9, (a0) -; CHECK-NEXT: addi a0, sp, 24 +; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: vs1r.v v8, (a0) -; CHECK-NEXT: addi a2, sp, 16 +; CHECK-NEXT: addi a2, sp, 24 ; CHECK-NEXT: vs1r.v v9, (a2) -; CHECK-NEXT: vl1re64.v v8, (a0) -; CHECK-NEXT: vl1re64.v v9, (a2) +; CHECK-NEXT: vl1re64.v v8, (a2) +; CHECK-NEXT: vl1re64.v v9, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: vfadd.vv v8, v9, v8 ; CHECK-NEXT: csrrs a0, vlenb, zero diff --git a/llvm/test/CodeGen/RISCV/vararg.ll b/llvm/test/CodeGen/RISCV/vararg.ll --- a/llvm/test/CodeGen/RISCV/vararg.ll +++ b/llvm/test/CodeGen/RISCV/vararg.ll @@ -495,6 +495,8 @@ ; ILP32-ILP32F-FPELIM-NEXT: sw a1, 20(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a6, 40(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a2, 24(sp) +; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 20 +; ILP32-ILP32F-FPELIM-NEXT: sw a0, 12(sp) ; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 27 ; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -8 ; ILP32-ILP32F-FPELIM-NEXT: addi a1, sp, 35 @@ -517,6 +519,8 @@ ; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0) +; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 4 +; ILP32-ILP32F-WITHFP-NEXT: sw a0, -12(s0) ; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 11 ; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -8 ; ILP32-ILP32F-WITHFP-NEXT: addi a1, s0, 19 @@ -538,6 +542,8 @@ ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 20(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 24(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 20 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 12(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 27 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -8 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, sp, 35 @@ -804,6 +810,8 @@ ; ILP32-ILP32F-FPELIM-NEXT: sw a5, 20(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a4, 16(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a3, 12(sp) +; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 12 +; ILP32-ILP32F-FPELIM-NEXT: sw a0, 4(sp) ; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 19 ; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -8 ; ILP32-ILP32F-FPELIM-NEXT: addi a3, sp, 27 @@ -828,6 +836,8 @@ ; ILP32-ILP32F-WITHFP-NEXT: sw a5, 12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a4, 8(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a3, 4(s0) +; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 4 +; ILP32-ILP32F-WITHFP-NEXT: sw a0, -12(s0) ; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 11 ; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -8 ; ILP32-ILP32F-WITHFP-NEXT: addi a3, s0, 19 @@ -851,6 +861,8 @@ ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 20(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 16(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 12(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 12 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 4(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 19 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -8 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a3, sp, 27 diff --git a/llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll b/llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll --- a/llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll +++ b/llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll @@ -85,23 +85,23 @@ ; RV32ZDINX-LABEL: foo4: ; RV32ZDINX: # %bb.0: # %entry ; RV32ZDINX-NEXT: addi sp, sp, -16 +; RV32ZDINX-NEXT: addi a1, a0, 2047 +; RV32ZDINX-NEXT: lw a2, -3(a1) +; RV32ZDINX-NEXT: lw a3, 1(a1) ; RV32ZDINX-NEXT: sw a0, 8(sp) -; RV32ZDINX-NEXT: addi a0, a0, 2047 -; RV32ZDINX-NEXT: lw a1, 1(a0) -; RV32ZDINX-NEXT: lw a0, -3(a0) -; RV32ZDINX-NEXT: lui a2, %hi(d) -; RV32ZDINX-NEXT: sw a0, %lo(d)(a2) -; RV32ZDINX-NEXT: sw a1, %lo(d+4)(a2) +; RV32ZDINX-NEXT: lui a0, %hi(d) +; RV32ZDINX-NEXT: sw a2, %lo(d)(a0) +; RV32ZDINX-NEXT: sw a3, %lo(d+4)(a0) ; RV32ZDINX-NEXT: addi sp, sp, 16 ; RV32ZDINX-NEXT: ret ; ; RV64ZDINX-LABEL: foo4: ; RV64ZDINX: # %bb.0: # %entry ; RV64ZDINX-NEXT: addi sp, sp, -16 +; RV64ZDINX-NEXT: ld a1, 2044(a0) ; RV64ZDINX-NEXT: sd a0, 8(sp) -; RV64ZDINX-NEXT: ld a0, 2044(a0) -; RV64ZDINX-NEXT: lui a1, %hi(d) -; RV64ZDINX-NEXT: sd a0, %lo(d)(a1) +; RV64ZDINX-NEXT: lui a0, %hi(d) +; RV64ZDINX-NEXT: sd a1, %lo(d)(a0) ; RV64ZDINX-NEXT: addi sp, sp, 16 ; RV64ZDINX-NEXT: ret entry: