Index: llvm/trunk/include/llvm/Support/ELFRelocs/Mips.def
===================================================================
--- llvm/trunk/include/llvm/Support/ELFRelocs/Mips.def
+++ llvm/trunk/include/llvm/Support/ELFRelocs/Mips.def
@@ -108,7 +108,7 @@
 ELF_RELOC(R_MICROMIPS_TLS_TPREL_LO16,   170)
 ELF_RELOC(R_MICROMIPS_GPREL7_S2,        172)
 ELF_RELOC(R_MICROMIPS_PC23_S2,          173)
-ELF_RELOC(R_MICROMIPS_PC21_S2,          174)
+ELF_RELOC(R_MICROMIPS_PC21_S1,          174)
 ELF_RELOC(R_MICROMIPS_PC26_S1,          175)
 ELF_RELOC(R_MICROMIPS_PC18_S3,          176)
 ELF_RELOC(R_MICROMIPS_PC19_S2,          177)
Index: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
===================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
@@ -189,7 +189,15 @@
       return 0;
     }
     break;
-
+  case Mips::fixup_MICROMIPS_PC21_S1:
+    // Forcing a signed division because Value can be negative.
+    Value = (int64_t)Value / 2;
+    // We now check if Value can be encoded as a 21-bit signed immediate.
+    if (!isInt<21>(Value) && Ctx) {
+      Ctx->reportError(Fixup.getLoc(), "out of range PC21 fixup");
+      return 0;
+    }
+    break;
   }
 
   return Value;
@@ -343,6 +351,7 @@
     { "fixup_MICROMIPS_PC26_S1", 0,     26,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_PC19_S2", 0,     19,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_PC18_S3", 0,     18,   MCFixupKindInfo::FKF_IsPCRel },
+    { "fixup_MICROMIPS_PC21_S1", 0,     21,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_CALL16",  0,     16,   0 },
     { "fixup_MICROMIPS_GOT_DISP",        0,     16,   0 },
     { "fixup_MICROMIPS_GOT_PAGE",        0,     16,   0 },
@@ -411,6 +420,7 @@
     { "fixup_MICROMIPS_PC26_S1", 6,     26,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_PC19_S2",13,     19,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_PC18_S3",14,     18,   MCFixupKindInfo::FKF_IsPCRel },
+    { "fixup_MICROMIPS_PC21_S1",11,     21,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_CALL16", 16,     16,   0 },
     { "fixup_MICROMIPS_GOT_DISP",        16,     16,   0 },
     { "fixup_MICROMIPS_GOT_PAGE",        16,     16,   0 },
Index: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
===================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
@@ -247,6 +247,8 @@
       return ELF::R_MICROMIPS_PC19_S2;
     case Mips::fixup_MICROMIPS_PC18_S3:
       return ELF::R_MICROMIPS_PC18_S3;
+    case Mips::fixup_MICROMIPS_PC21_S1:
+      return ELF::R_MICROMIPS_PC21_S1;
     case Mips::fixup_MIPS_PC19_S2:
       return ELF::R_MIPS_PC19_S2;
     case Mips::fixup_MIPS_PC18_S3:
@@ -608,7 +610,7 @@
   case ELF::R_MICROMIPS_TLS_TPREL_LO16:
   case ELF::R_MICROMIPS_GPREL7_S2:
   case ELF::R_MICROMIPS_PC23_S2:
-  case ELF::R_MICROMIPS_PC21_S2:
+  case ELF::R_MICROMIPS_PC21_S1:
   case ELF::R_MICROMIPS_PC26_S1:
   case ELF::R_MICROMIPS_PC18_S3:
   case ELF::R_MICROMIPS_PC19_S2:
Index: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h
===================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h
@@ -176,6 +176,9 @@
     // resulting in - R_MICROMIPS_PC18_S3
     fixup_MICROMIPS_PC18_S3,
 
+    // resulting in - R_MICROMIPS_PC21_S1
+    fixup_MICROMIPS_PC21_S1,
+
     // resulting in - R_MICROMIPS_CALL16
     fixup_MICROMIPS_CALL16,
 
Index: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
===================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
@@ -384,7 +384,10 @@
   assert(MO.isExpr() &&
     "getBranchTarget21OpValueMM expects only expressions or immediates");
 
-  // TODO: Push fixup.
+  const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
+      MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
+  Fixups.push_back(MCFixup::create(0, FixupExpression,
+                                   MCFixupKind(Mips::fixup_MICROMIPS_PC21_S1)));
   return 0;
 }
 
Index: llvm/trunk/test/MC/Mips/micromips32r6/relocations.s
===================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/relocations.s
+++ llvm/trunk/test/MC/Mips/micromips32r6/relocations.s
@@ -17,6 +17,12 @@
 # CHECK-FIXUP: lwpc    $2, bar  # encoding: [0x78,0b01001AAA,A,A]
 # CHECK-FIXUP:                  #   fixup A - offset: 0,
 # CHECK-FIXUP:                      value: bar, kind: fixup_MICROMIPS_PC19_S2
+# CHECK-FIXUP: beqzc $3, bar    # encoding: [0x80,0b011AAAAA,A,A]
+# CHECK-FIXUP:                  #   fixup A - offset: 0,
+# CHECK-FIXUP:                      value: bar-4, kind: fixup_MICROMIPS_PC21_S1
+# CHECK-FIXUP: bnezc $3, bar    # encoding: [0xa0,0b011AAAAA,A,A]
+# CHECK-FIXUP:                  #   fixup A - offset: 0,
+# CHECK-FIXUP:                      value: bar-4, kind: fixup_MICROMIPS_PC21_S1
 #------------------------------------------------------------------------------
 # Check that the appropriate relocations were created.
 #------------------------------------------------------------------------------
@@ -25,9 +31,13 @@
 # CHECK-ELF:     0x4 R_MICROMIPS_PC26_S1 bar 0x0
 # CHECK-ELF:     0x8 R_MICROMIPS_PC19_S2 bar 0x0
 # CHECK-ELF:     0xC R_MICROMIPS_PC19_S2 bar 0x0
+# CHECK-ELF:     0x10 R_MICROMIPS_PC21_S1 bar 0x0
+# CHECK-ELF:     0x14 R_MICROMIPS_PC21_S1 bar 0x0
 # CHECK-ELF: ]
 
   balc  bar
   bc    bar
   addiupc $2,bar
   lwpc    $2,bar
+  beqzc  $3, bar
+  bnezc  $3, bar
Index: llvm/trunk/test/MC/Mips/micromips64r6/relocations.s
===================================================================
--- llvm/trunk/test/MC/Mips/micromips64r6/relocations.s
+++ llvm/trunk/test/MC/Mips/micromips64r6/relocations.s
@@ -20,6 +20,12 @@
 # CHECK-FIXUP: ldpc  $2, bar    # encoding: [0x78,0b010110AA,A,A]
 # CHECK-FIXUP:                  #   fixup A - offset: 0,
 # CHECK-FIXUP:                      value: bar, kind: fixup_MICROMIPS_PC18_S3
+# CHECK-FIXUP: beqzc $3, bar        # encoding: [0x80,0b011AAAAA,A,A]
+# CHECK-FIXUP:                      #   fixup A - offset: 0,
+# CHECK-FIXUP:                          value: bar-4, kind: fixup_MICROMIPS_PC21_S1
+# CHECK-FIXUP: bnezc $3, bar        # encoding: [0xa0,0b011AAAAA,A,A]
+# CHECK-FIXUP:                      #   fixup A - offset: 0,
+# CHECK-FIXUP:                          value: bar-4, kind: fixup_MICROMIPS_PC21_S1
 #------------------------------------------------------------------------------
 # Check that the appropriate relocations were created.
 #------------------------------------------------------------------------------
@@ -29,6 +35,8 @@
 # CHECK-ELF:     0x8 R_MICROMIPS_PC19_S2 bar 0x0
 # CHECK-ELF:     0xC R_MICROMIPS_PC19_S2 bar 0x0
 # CHECK-ELF:     0x10 R_MICROMIPS_PC18_S3 bar 0x0
+# CHECK-ELF:     0x14 R_MICROMIPS_PC21_S1 bar 0x0
+# CHECK-ELF:     0x18 R_MICROMIPS_PC21_S1 bar 0x0
 # CHECK-ELF: ]
 
   balc  bar
@@ -36,3 +44,5 @@
   addiupc $2,bar
   lwpc    $2,bar
   ldpc  $2, bar
+  beqzc  $3, bar
+  bnezc  $3, bar