Index: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -1006,14 +1006,18 @@ class LLE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lle", GPR32Opnd>; class LWE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lwe", GPR32Opnd>; class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>, - MMR6Arch<"addu16">; + MMR6Arch<"addu16"> { + int AddedComplexity = 1; +} class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>, MMR6Arch<"and16">; class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, MMR6Arch<"andi16">; class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16">; class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>, - MMR6Arch<"or16">; + MMR6Arch<"or16"> { + int AddedComplexity = 1; +} class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>, MMR6Arch<"sll16">; class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>, Index: llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td +++ llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td @@ -278,7 +278,6 @@ class MMArch { string Arch = "micromips"; - list Pattern = []; } class ADD_FM_MM op, bits<10> funct> : MMArch { @@ -380,13 +379,15 @@ class LW_FM_MM op> : MMArch { bits<5> rt; bits<21> addr; + bits<5> base = addr{20-16}; + bits<16> offset = addr{15-0}; bits<32> Inst; let Inst{31-26} = op; let Inst{25-21} = rt; - let Inst{20-16} = addr{20-16}; - let Inst{15-0} = addr{15-0}; + let Inst{20-16} = base; + let Inst{15-0} = offset; } class POOL32C_LHUE_FM_MM op, bits<4> fmt, bits<3> funct> : MMArch { Index: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td +++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td @@ -761,8 +761,10 @@ let DecoderMethod = "DecodeMemMMImm16" in { def LB_MM : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>; def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>; - def LH_MM : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>; - def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>; + def LH_MM : LoadMemory<"lh", GPR32Opnd, mem_simm16, sextloadi16, II_LH, + addrDefault>, MMRel, LW_FM_MM<0xf>; + def LHu_MM : LoadMemory<"lhu", GPR32Opnd, mem_simm16, zextloadi16, II_LHU>, + MMRel, LW_FM_MM<0xd>; def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>; def SB_MM : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>; def SH_MM : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>; @@ -772,8 +774,10 @@ let DecoderMethod = "DecodeMemMMImm9" in { def LBE_MM : Load<"lbe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>; def LBuE_MM : Load<"lbue", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>; - def LHE_MM : Load<"lhe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x5>; - def LHuE_MM : Load<"lhue", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x1>; + def LHE_MM : LoadMemory<"lhe", GPR32Opnd, mem_simm9>, + POOL32C_LHUE_FM_MM<0x18, 0x6, 0x5>; + def LHuE_MM : LoadMemory<"lhue", GPR32Opnd, mem_simm9>, + POOL32C_LHUE_FM_MM<0x18, 0x6, 0x1>; def LWE_MM : LoadMemory<"lwe", GPR32Opnd, mem_simm9>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>; def SBE_MM : StoreMemory<"sbe", GPR32Opnd, mem_simm9>, @@ -1038,6 +1042,15 @@ def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs), (SUBu_MM GPR32:$lhs, GPR32:$rhs)>; +let AddedComplexity = 40 in { + def : MipsPat<(i32 (sextloadi16 addrRegImm:$a)), + (LH_MM addrRegImm:$a)>; +} +def : MipsPat<(atomic_load_16 addr:$a), + (LH_MM addr:$a)>; +def : MipsPat<(i32 (extloadi16 addr:$src)), + (LHu_MM addr:$src)>; + //===----------------------------------------------------------------------===// // MicroMips instruction aliases //===----------------------------------------------------------------------===// Index: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td @@ -1715,12 +1715,13 @@ def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>; def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel, LW_FM<0x24>; -def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel, - LW_FM<0x21>; -def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>; let AdditionalPredicates = [NotInMicroMips] in { -def LW : StdMMR6Rel, Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel, - LW_FM<0x23>; + def LH : LoadMemory<"lh", GPR32Opnd, mem_simm16, sextloadi16, II_LH, + addrDefault>, MMRel, LW_FM<0x21>; + def LHu : LoadMemory<"lhu", GPR32Opnd, mem_simm16, zextloadi16, II_LHU>, + MMRel, LW_FM<0x25>; + def LW : StdMMR6Rel, Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel, + LW_FM<0x23>; } def SB : StdMMR6Rel, Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>; @@ -2505,7 +2506,9 @@ // extended loads def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; -def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; +let AdditionalPredicates = [NotInMicroMips] in { + def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; +} // peepholes def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; @@ -2602,15 +2605,17 @@ // Load halfword/word patterns. let AddedComplexity = 40 in { def : LoadRegImmPat; - def : LoadRegImmPat; let AdditionalPredicates = [NotInMicroMips] in { - def : LoadRegImmPat; + def : LoadRegImmPat; + def : LoadRegImmPat; } } // Atomic load patterns. def : MipsPat<(atomic_load_8 addr:$a), (LB addr:$a)>; -def : MipsPat<(atomic_load_16 addr:$a), (LH addr:$a)>; +let AdditionalPredicates = [NotInMicroMips] in { + def : MipsPat<(atomic_load_16 addr:$a), (LH addr:$a)>; +} def : MipsPat<(atomic_load_32 addr:$a), (LW addr:$a)>; // Atomic store patterns. Index: llvm/trunk/test/CodeGen/Mips/llvm-ir/lh_lhu.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/llvm-ir/lh_lhu.ll +++ llvm/trunk/test/CodeGen/Mips/llvm-ir/lh_lhu.ll @@ -0,0 +1,32 @@ +; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips -relocation-model=pic | FileCheck %s +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s +; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips -relocation-model=pic | FileCheck %s + +@us = global i16 0, align 2 + +define i32 @lhfunc() { +entry: +; CHECK-LABEL: lhfunc +; CHECK: lh $[[REG1:[0-9]+]], 0(${{[0-9]+}}) + %0 = load i16, i16* @us, align 2 + %conv = sext i16 %0 to i32 + ret i32 %conv +} + +define i16 @lhfunc_atomic() { +entry: +; CHECK-LABEL: lhfunc_atomic +; CHECK: lh $[[REG1:[0-9]+]], 0(${{[0-9]+}}) + %0 = load atomic i16, i16* @us acquire, align 2 + ret i16 %0 +} + +define i32 @lhufunc() { +entry: +; CHECK-LABEL: lhufunc +; CHECK: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) + %0 = load i16, i16* @us, align 2 + %conv = zext i16 %0 to i32 + ret i32 %conv +} Index: llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt =================================================================== --- llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt +++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt @@ -72,6 +72,10 @@ 0x00 0x01 0xf3 0x7c # CHECK: eretnc 0x80 0x05 0x01 0x00 # CHECK: jialc $5, 256 0xa0 0x05 0x01 0x00 # CHECK: jic $5, 256 +0x3c 0x44 0x00 0x08 # CHECK: lh $2, 8($4) +0x60 0x82 0x6a 0x08 # CHECK: lhe $4, 8($2) +0x34 0x82 0x00 0x08 # CHECK: lhu $4, 8($2) +0x60 0x82 0x62 0x08 # CHECK: lhue $4, 8($2) 0x60 0x44 0x30 0x08 # CHECK: ll $2, 8($4) 0x20 0x44 0x50 0x08 # CHECK: lwm32 $16, $17, 8($4) 0x21 0x3b 0x59 0x84 # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, -1660($27) Index: llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt =================================================================== --- llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt +++ llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt @@ -248,6 +248,10 @@ 0x59 0x40 0x51 0x90 # CHECK: dneg $10, $10 0x59 0x60 0x09 0xd0 # CHECK: dnegu $1, $11 0x58 0xa0 0x29 0xd0 # CHECK: dnegu $5, $5 +0x3c 0x44 0x00 0x08 # CHECK: lh $2, 8($4) +0x60 0x82 0x6a 0x08 # CHECK: lhe $4, 8($2) +0x34 0x82 0x00 0x08 # CHECK: lhu $4, 8($2) +0x60 0x82 0x62 0x08 # CHECK: lhue $4, 8($2) 0x00 0xa4 0x18 0x18 # CHECK: mul $3, $4, $5 0x00 0xa4 0x18 0x58 # CHECK: muh $3, $4, $5 0x00 0xa4 0x18 0x98 # CHECK: mulu $3, $4, $5 Index: llvm/trunk/test/MC/Mips/micromips/invalid.s =================================================================== --- llvm/trunk/test/MC/Mips/micromips/invalid.s +++ llvm/trunk/test/MC/Mips/micromips/invalid.s @@ -83,6 +83,22 @@ she $4, 8($33) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset she $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset she $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset + lh $33, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lhe $34, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lhu $35, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lhue $36, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lh $2, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lhe $4, 8($33) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lhu $4, 8($35) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lhue $4, 8($37) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lh $2, -65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lh $2, 65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lhe $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lhe $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lhu $4, -65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lhu $4, 65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lhue $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lhue $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset lwp $31, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction # FIXME: This ought to point at the $34 but memory is treated as one operand. lwp $16, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset Index: llvm/trunk/test/MC/Mips/micromips32r6/invalid.s =================================================================== --- llvm/trunk/test/MC/Mips/micromips32r6/invalid.s +++ llvm/trunk/test/MC/Mips/micromips32r6/invalid.s @@ -172,6 +172,22 @@ she $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset she $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset swe $5, -513($4) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset + lh $33, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lhe $34, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lhu $35, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lhue $36, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lh $2, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lhe $4, 8($33) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lhu $4, 8($35) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lhue $4, 8($37) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lh $2, -65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lh $2, 65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lhe $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lhe $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lhu $4, -65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lhu $4, 65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lhue $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lhue $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset lwm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected lwm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected lwm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand Index: llvm/trunk/test/MC/Mips/micromips32r6/valid.s =================================================================== --- llvm/trunk/test/MC/Mips/micromips32r6/valid.s +++ llvm/trunk/test/MC/Mips/micromips32r6/valid.s @@ -63,6 +63,10 @@ jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xa0,0x05,0x01,0x00] jrc16 $9 # CHECK: jrc16 $9 # encoding: [0x45,0x23] jrcaddiusp 20 # CHECK: jrcaddiusp 20 # encoding: [0x44,0xb3] + lh $2, 8($4) # CHECK: lh $2, 8($4) # encoding: [0x3c,0x44,0x00,0x08] + lhe $4, 8($2) # CHECK: lhe $4, 8($2) # encoding: [0x60,0x82,0x6a,0x08] + lhu $4, 8($2) # CHECK: lhu $4, 8($2) # encoding: [0x34,0x82,0x00,0x08] + lhue $4, 8($2) # CHECK: lhue $4, 8($2) # encoding: [0x60,0x82,0x62,0x08] lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x43,0x24,0x0f] lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0x78,0x48,0x00,0x43] lwm $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22] Index: llvm/trunk/test/MC/Mips/micromips64r6/invalid.s =================================================================== --- llvm/trunk/test/MC/Mips/micromips64r6/invalid.s +++ llvm/trunk/test/MC/Mips/micromips64r6/invalid.s @@ -204,6 +204,22 @@ swe $5, 8($34) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset swe $5, 512($4) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset swe $5, -513($4) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset + lh $33, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lhe $34, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lhu $35, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lhue $36, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lh $2, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lhe $4, 8($33) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lhu $4, 8($35) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lhue $4, 8($37) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lh $2, -65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lh $2, 65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lhe $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lhe $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lhu $4, -65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lhu $4, 65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lhue $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lhue $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset lwm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected lwm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected lwm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand Index: llvm/trunk/test/MC/Mips/micromips64r6/valid.s =================================================================== --- llvm/trunk/test/MC/Mips/micromips64r6/valid.s +++ llvm/trunk/test/MC/Mips/micromips64r6/valid.s @@ -182,6 +182,10 @@ dinsu $4, $2, 32, 5 # CHECK: dinsu $4, $2, 32, 5 # encoding: [0x58,0x82,0x20,0x34] dinsm $4, $2, 3, 5 # CHECK: dinsm $4, $2, 3, 5 # encoding: [0x58,0x82,0x38,0xc4] dins $4, $2, 3, 5 # CHECK: dins $4, $2, 3, 5 # encoding: [0x58,0x82,0x38,0xcc] + lh $2, 8($4) # CHECK: lh $2, 8($4) # encoding: [0x3c,0x44,0x00,0x08] + lhe $4, 8($2) # CHECK: lhe $4, 8($2) # encoding: [0x60,0x82,0x6a,0x08] + lhu $4, 8($2) # CHECK: lhu $4, 8($2) # encoding: [0x34,0x82,0x00,0x08] + lhue $4, 8($2) # CHECK: lhue $4, 8($2) # encoding: [0x60,0x82,0x62,0x08] mtc0 $5, $9 # CHECK: mtc0 $5, $9, 0 # encoding: [0x00,0xa9,0x02,0xfc] mtc0 $1, $2, 7 # CHECK: mtc0 $1, $2, 7 # encoding: [0x00,0x22,0x3a,0xfc] mtc1 $3, $f4 # CHECK: mtc1 $3, $f4 # encoding: [0x54,0x64,0x28,0x3b] Index: llvm/trunk/test/MC/Mips/mips32r6/invalid.s =================================================================== --- llvm/trunk/test/MC/Mips/mips32r6/invalid.s +++ llvm/trunk/test/MC/Mips/mips32r6/invalid.s @@ -20,6 +20,22 @@ break 7, -1 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate break 7, 1024 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate break 1024, 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + lh $33, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lhe $34, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lhu $35, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lhue $36, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lh $2, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lhe $4, 8($33) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lhu $4, 8($35) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lhue $4, 8($37) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lh $2, -65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lh $2, 65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lhe $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lhe $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lhu $4, -65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lhu $4, 65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lhue $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lhue $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset // FIXME: Following tests are temporarely disabled, until "PredicateControl not in hierarchy" problem is resolved bltl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bltul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled Index: llvm/trunk/test/MC/Mips/mips64r6/invalid.s =================================================================== --- llvm/trunk/test/MC/Mips/mips64r6/invalid.s +++ llvm/trunk/test/MC/Mips/mips64r6/invalid.s @@ -20,6 +20,22 @@ break 7, -1 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate break 7, 1024 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate break 1024, 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + lh $33, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lhe $34, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lhu $35, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lhue $36, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lh $2, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lhe $4, 8($33) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lhu $4, 8($35) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lhue $4, 8($37) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lh $2, -65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lh $2, 65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lhe $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lhe $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lhu $4, -65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lhu $4, 65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lhue $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lhue $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset // FIXME: Following tests are temporarely disabled, until "PredicateControl not in hierarchy" problem is resolved bltl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bltul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled