Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.h
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.h
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.h
@@ -103,6 +103,8 @@
 
   void EmitFunctionEntryLabel() override;
 
+  void EmitGlobalVariable(const GlobalVariable *GV) override;
+
   bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                        unsigned AsmVariant, const char *ExtraCode,
                        raw_ostream &O) override;
Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -123,6 +123,13 @@
   AsmPrinter::EmitFunctionEntryLabel();
 }
 
+void AMDGPUAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
+
+  if (TM.getTargetTriple().getOS() != Triple::AMDHSA ||
+      !AMDGPU::isGroupSegment(GV))
+    return AsmPrinter::EmitGlobalVariable(GV);
+}
+
 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
 
   // The starting address of all shader programs must be 256 bytes aligned.
Index: llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -15,6 +15,7 @@
 namespace llvm {
 
 class FeatureBitset;
+class GlobalValue;
 class MCContext;
 class MCSection;
 
@@ -31,6 +32,8 @@
                                const FeatureBitset &Features);
 MCSection *getHSATextSection(MCContext &Ctx);
 
+bool isGroupSegment(const GlobalValue *GV);
+
 } // end namespace AMDGPU
 } // end namespace llvm
 
Index: llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -7,6 +7,8 @@
 //
 //===----------------------------------------------------------------------===//
 #include "AMDGPUBaseInfo.h"
+#include "AMDGPU.h"
+#include "llvm/IR/GlobalValue.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCSectionELF.h"
 #include "llvm/MC/SubtargetFeature.h"
@@ -66,5 +68,9 @@
                            ELF::SHF_AMDGPU_HSA_CODE);
 }
 
+bool isGroupSegment(const GlobalValue *GV) {
+  return GV->getType()->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
+}
+
 } // End namespace AMDGPU
 } // End namespace llvm
Index: llvm/trunk/test/CodeGen/AMDGPU/hsa-group-segment.ll
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/hsa-group-segment.ll
+++ llvm/trunk/test/CodeGen/AMDGPU/hsa-group-segment.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | FileCheck --check-prefix=HSA %s
+
+@internal_group = internal addrspace(3) global i32 undef
+@external_group = addrspace(3) global i32 undef
+
+define void @test() {
+entry:
+  store i32 0, i32 addrspace(3)* @internal_group
+  store i32 0, i32 addrspace(3)* @external_group
+  ret void
+}
+
+; HSA-NOT: internal_group:
+; HSA-NOT: external_group: