Index: llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td =================================================================== --- llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td +++ llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td @@ -352,9 +352,11 @@ let ParserMatchClass = Imm1_64Operand; } +def fixedpoint_f16_i32 : fixedpoint_i32; def fixedpoint_f32_i32 : fixedpoint_i32; def fixedpoint_f64_i32 : fixedpoint_i32; +def fixedpoint_f16_i64 : fixedpoint_i64; def fixedpoint_f32_i64 : fixedpoint_i64; def fixedpoint_f64_i64 : fixedpoint_i64; @@ -713,6 +715,17 @@ } // Floating-point immediate. +def fpimm16 : Operand, + PatLeaf<(f16 fpimm), [{ + return AArch64_AM::getFP16Imm(N->getValueAPF()) != -1; + }], SDNodeXFormgetValueAPF(); + uint32_t enc = AArch64_AM::getFP16Imm(InVal); + return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32); + }]>> { + let ParserMatchClass = FPImmOperand; + let PrintMethod = "printFPImmOperand"; +} def fpimm32 : Operand, PatLeaf<(f32 fpimm), [{ return AArch64_AM::getFP32Imm(N->getValueAPF()) != -1; @@ -3536,6 +3549,20 @@ multiclass FPToIntegerUnscaled rmode, bits<3> opcode, string asm, SDPatternOperator OpN> { + // Unscaled half-precision to 32-bit + def UWHr : BaseFPToIntegerUnscaled<0b11, rmode, opcode, FPR16, GPR32, asm, + [(set GPR32:$Rd, (OpN FPR16:$Rn))]> { + let Inst{31} = 0; // 32-bit GPR flag + let Predicates = [HasFullFP16]; + } + + // Unscaled half-precision to 64-bit + def UXHr : BaseFPToIntegerUnscaled<0b11, rmode, opcode, FPR16, GPR64, asm, + [(set GPR64:$Rd, (OpN FPR16:$Rn))]> { + let Inst{31} = 1; // 64-bit GPR flag + let Predicates = [HasFullFP16]; + } + // Unscaled single-precision to 32-bit def UWSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, GPR32, asm, [(set GPR32:$Rd, (OpN FPR32:$Rn))]> { @@ -3563,6 +3590,25 @@ multiclass FPToIntegerScaled rmode, bits<3> opcode, string asm, SDPatternOperator OpN> { + // Scaled half-precision to 32-bit + def SWHri : BaseFPToInteger<0b11, rmode, opcode, FPR16, GPR32, + fixedpoint_f16_i32, asm, + [(set GPR32:$Rd, (OpN (fmul FPR16:$Rn, + fixedpoint_f16_i32:$scale)))]> { + let Inst{31} = 0; // 32-bit GPR flag + let scale{5} = 1; + let Predicates = [HasFullFP16]; + } + + // Scaled half-precision to 64-bit + def SXHri : BaseFPToInteger<0b11, rmode, opcode, FPR16, GPR64, + fixedpoint_f16_i64, asm, + [(set GPR64:$Rd, (OpN (fmul FPR16:$Rn, + fixedpoint_f16_i64:$scale)))]> { + let Inst{31} = 1; // 64-bit GPR flag + let Predicates = [HasFullFP16]; + } + // Scaled single-precision to 32-bit def SWSri : BaseFPToInteger<0b00, rmode, opcode, FPR32, GPR32, fixedpoint_f32_i32, asm, @@ -3612,7 +3658,7 @@ bits<5> Rd; bits<5> Rn; bits<6> scale; - let Inst{30-23} = 0b00111100; + let Inst{30-24} = 0b0011110; let Inst{21-17} = 0b00001; let Inst{16} = isUnsigned; let Inst{15-10} = scale; @@ -3629,7 +3675,7 @@ bits<5> Rd; bits<5> Rn; bits<6> scale; - let Inst{30-23} = 0b00111100; + let Inst{30-24} = 0b0011110; let Inst{21-17} = 0b10001; let Inst{16} = isUnsigned; let Inst{15-10} = 0b000000; @@ -3639,33 +3685,55 @@ multiclass IntegerToFP { // Unscaled + def UWHri: BaseIntegerToFPUnscaled { + let Inst{31} = 0; // 32-bit GPR flag + let Inst{23-22} = 0b11; // 16-bit FPR flag + let Predicates = [HasFullFP16]; + } + def UWSri: BaseIntegerToFPUnscaled { let Inst{31} = 0; // 32-bit GPR flag - let Inst{22} = 0; // 32-bit FPR flag + let Inst{23-22} = 0b00; // 32-bit FPR flag } def UWDri: BaseIntegerToFPUnscaled { let Inst{31} = 0; // 32-bit GPR flag - let Inst{22} = 1; // 64-bit FPR flag + let Inst{23-22} = 0b01; // 64-bit FPR flag + } + + def UXHri: BaseIntegerToFPUnscaled { + let Inst{31} = 1; // 64-bit GPR flag + let Inst{23-22} = 0b11; // 16-bit FPR flag + let Predicates = [HasFullFP16]; } def UXSri: BaseIntegerToFPUnscaled { let Inst{31} = 1; // 64-bit GPR flag - let Inst{22} = 0; // 32-bit FPR flag + let Inst{23-22} = 0b00; // 32-bit FPR flag } def UXDri: BaseIntegerToFPUnscaled { let Inst{31} = 1; // 64-bit GPR flag - let Inst{22} = 1; // 64-bit FPR flag + let Inst{23-22} = 0b01; // 64-bit FPR flag } // Scaled + def SWHri: BaseIntegerToFP { + let Inst{31} = 0; // 32-bit GPR flag + let Inst{23-22} = 0b11; // 16-bit FPR flag + let scale{5} = 1; + let Predicates = [HasFullFP16]; + } + def SWSri: BaseIntegerToFP { let Inst{31} = 0; // 32-bit GPR flag - let Inst{22} = 0; // 32-bit FPR flag + let Inst{23-22} = 0b00; // 32-bit FPR flag let scale{5} = 1; } @@ -3674,16 +3742,25 @@ (fdiv (node GPR32:$Rn), fixedpoint_f64_i32:$scale))]> { let Inst{31} = 0; // 32-bit GPR flag - let Inst{22} = 1; // 64-bit FPR flag + let Inst{23-22} = 0b01; // 64-bit FPR flag let scale{5} = 1; } + def SXHri: BaseIntegerToFP { + let Inst{31} = 1; // 64-bit GPR flag + let Inst{23-22} = 0b11; // 16-bit FPR flag + let Predicates = [HasFullFP16]; + } + def SXSri: BaseIntegerToFP { let Inst{31} = 1; // 64-bit GPR flag - let Inst{22} = 0; // 32-bit FPR flag + let Inst{23-22} = 0b00; // 32-bit FPR flag } def SXDri: BaseIntegerToFP { let Inst{31} = 1; // 64-bit GPR flag - let Inst{22} = 1; // 64-bit FPR flag + let Inst{23-22} = 0b01; // 64-bit FPR flag } } @@ -3713,7 +3790,7 @@ Sched<[WriteFCopy]> { bits<5> Rd; bits<5> Rn; - let Inst{30-23} = 0b00111100; + let Inst{30-24} = 0b0011110; let Inst{21} = 1; let Inst{20-19} = rmode; let Inst{18-16} = opcode; @@ -3763,26 +3840,49 @@ } - multiclass UnscaledConversion { + def WHr : BaseUnscaledConversion<0b00, 0b111, GPR32, FPR16, asm> { + let Inst{31} = 0; // 32-bit GPR flag + let Inst{23-22} = 0b11; // 16-bit FPR flag + let Predicates = [HasFullFP16]; + } + + def XHr : BaseUnscaledConversion<0b00, 0b111, GPR64, FPR16, asm> { + let Inst{31} = 1; // 64-bit GPR flag + let Inst{23-22} = 0b11; // 16-bit FPR flag + let Predicates = [HasFullFP16]; + } + def WSr : BaseUnscaledConversion<0b00, 0b111, GPR32, FPR32, asm> { let Inst{31} = 0; // 32-bit GPR flag - let Inst{22} = 0; // 32-bit FPR flag + let Inst{23-22} = 0b00; // 32-bit FPR flag } def XDr : BaseUnscaledConversion<0b00, 0b111, GPR64, FPR64, asm> { let Inst{31} = 1; // 64-bit GPR flag - let Inst{22} = 1; // 64-bit FPR flag + let Inst{23-22} = 0b01; // 64-bit FPR flag + } + + def HWr : BaseUnscaledConversion<0b00, 0b110, FPR16, GPR32, asm> { + let Inst{31} = 0; // 32-bit GPR flag + let Inst{23-22} = 0b11; // 16-bit FPR flag + let Predicates = [HasFullFP16]; + } + + def HXr : BaseUnscaledConversion<0b00, 0b110, FPR16, GPR64, asm> { + let Inst{31} = 1; // 64-bit GPR flag + let Inst{23-22} = 0b11; // 16-bit FPR flag + let Predicates = [HasFullFP16]; } def SWr : BaseUnscaledConversion<0b00, 0b110, FPR32, GPR32, asm> { let Inst{31} = 0; // 32-bit GPR flag - let Inst{22} = 0; // 32-bit FPR flag + let Inst{23-22} = 0b00; // 32-bit FPR flag } def DXr : BaseUnscaledConversion<0b00, 0b110, FPR64, GPR64, asm> { let Inst{31} = 1; // 64-bit GPR flag - let Inst{22} = 1; // 64-bit FPR flag + let Inst{23-22} = 0b01; // 64-bit FPR flag } def XDHighr : BaseUnscaledConversionToHigh<0b01, 0b111, GPR64, V128, @@ -3855,7 +3955,7 @@ Sched<[WriteF]> { bits<5> Rd; bits<5> Rn; - let Inst{31-23} = 0b000111100; + let Inst{31-24} = 0b00011110; let Inst{21-19} = 0b100; let Inst{18-15} = opcode; let Inst{14-10} = 0b10000; @@ -3865,12 +3965,17 @@ multiclass SingleOperandFPData opcode, string asm, SDPatternOperator node = null_frag> { + def Hr : BaseSingleOperandFPData { + let Inst{23-22} = 0b11; // 16-bit size flag + let Predicates = [HasFullFP16]; + } + def Sr : BaseSingleOperandFPData { - let Inst{22} = 0; // 32-bit size flag + let Inst{23-22} = 0b00; // 32-bit size flag } def Dr : BaseSingleOperandFPData { - let Inst{22} = 1; // 64-bit size flag + let Inst{23-22} = 0b01; // 64-bit size flag } } @@ -3887,7 +3992,7 @@ bits<5> Rd; bits<5> Rn; bits<5> Rm; - let Inst{31-23} = 0b000111100; + let Inst{31-24} = 0b00011110; let Inst{21} = 1; let Inst{20-16} = Rm; let Inst{15-12} = opcode; @@ -3898,28 +4003,41 @@ multiclass TwoOperandFPData opcode, string asm, SDPatternOperator node = null_frag> { + def Hrr : BaseTwoOperandFPData { + let Inst{23-22} = 0b11; // 16-bit size flag + let Predicates = [HasFullFP16]; + } + def Srr : BaseTwoOperandFPData { - let Inst{22} = 0; // 32-bit size flag + let Inst{23-22} = 0b00; // 32-bit size flag } def Drr : BaseTwoOperandFPData { - let Inst{22} = 1; // 64-bit size flag + let Inst{23-22} = 0b01; // 64-bit size flag } } multiclass TwoOperandFPDataNeg opcode, string asm, SDNode node> { + def Hrr : BaseTwoOperandFPData { + let Inst{23-22} = 0b11; // 16-bit size flag + let Predicates = [HasFullFP16]; + } + def Srr : BaseTwoOperandFPData { - let Inst{22} = 0; // 32-bit size flag + let Inst{23-22} = 0b00; // 32-bit size flag } def Drr : BaseTwoOperandFPData { - let Inst{22} = 1; // 64-bit size flag + let Inst{23-22} = 0b01; // 64-bit size flag } } @@ -3937,7 +4055,7 @@ bits<5> Rn; bits<5> Rm; bits<5> Ra; - let Inst{31-23} = 0b000111110; + let Inst{31-24} = 0b00011111; let Inst{21} = isNegated; let Inst{20-16} = Rm; let Inst{15} = isSub; @@ -3948,16 +4066,23 @@ multiclass ThreeOperandFPData { + def Hrrr : BaseThreeOperandFPData { + let Inst{23-22} = 0b11; // 16-bit size flag + let Predicates = [HasFullFP16]; + } + def Srrr : BaseThreeOperandFPData { - let Inst{22} = 0; // 32-bit size flag + let Inst{23-22} = 0b00; // 32-bit size flag } def Drrr : BaseThreeOperandFPData { - let Inst{22} = 1; // 64-bit size flag + let Inst{23-22} = 0b01; // 64-bit size flag } } @@ -3972,7 +4097,7 @@ : I<(outs), (ins regtype:$Rn), asm, "\t$Rn, #0.0", "", pat>, Sched<[WriteFCmp]> { bits<5> Rn; - let Inst{31-23} = 0b000111100; + let Inst{31-24} = 0b00011110; let Inst{21} = 1; let Inst{15-10} = 0b001000; @@ -3991,7 +4116,7 @@ Sched<[WriteFCmp]> { bits<5> Rm; bits<5> Rn; - let Inst{31-23} = 0b000111100; + let Inst{31-24} = 0b00011110; let Inst{21} = 1; let Inst{20-16} = Rm; let Inst{15-10} = 0b001000; @@ -4003,24 +4128,36 @@ multiclass FPComparison { let Defs = [NZCV] in { + def Hrr : BaseTwoOperandFPComparison { + let Inst{23-22} = 0b11; + let Predicates = [HasFullFP16]; + } + + def Hri : BaseOneOperandFPComparison { + let Inst{23-22} = 0b11; + let Predicates = [HasFullFP16]; + } + def Srr : BaseTwoOperandFPComparison { - let Inst{22} = 0; + let Inst{23-22} = 0b00; } def Sri : BaseOneOperandFPComparison { - let Inst{22} = 0; + let Inst{23-22} = 0b00; } def Drr : BaseTwoOperandFPComparison { - let Inst{22} = 1; + let Inst{23-22} = 0b01; } def Dri : BaseOneOperandFPComparison { - let Inst{22} = 1; + let Inst{23-22} = 0b01; } } // Defs = [NZCV] } @@ -4043,7 +4180,7 @@ bits<4> nzcv; bits<4> cond; - let Inst{31-23} = 0b000111100; + let Inst{31-24} = 0b00011110; let Inst{21} = 1; let Inst{20-16} = Rm; let Inst{15-12} = cond; @@ -4055,15 +4192,21 @@ multiclass FPCondComparison { + def Hrr : BaseFPCondComparison { + let Inst{23-22} = 0b11; + let Predicates = [HasFullFP16]; + } + def Srr : BaseFPCondComparison { - let Inst{22} = 0; + let Inst{23-22} = 0b00; } + def Drr : BaseFPCondComparison { - let Inst{22} = 1; + let Inst{23-22} = 0b01; } } @@ -4083,7 +4226,7 @@ bits<5> Rm; bits<4> cond; - let Inst{31-23} = 0b000111100; + let Inst{31-24} = 0b00011110; let Inst{21} = 1; let Inst{20-16} = Rm; let Inst{15-12} = cond; @@ -4094,12 +4237,17 @@ multiclass FPCondSelect { let Uses = [NZCV] in { + def Hrrr : BaseFPCondSelect { + let Inst{23-22} = 0b11; + let Predicates = [HasFullFP16]; + } + def Srrr : BaseFPCondSelect { - let Inst{22} = 0; + let Inst{23-22} = 0b00; } def Drrr : BaseFPCondSelect { - let Inst{22} = 1; + let Inst{23-22} = 0b01; } } // Uses = [NZCV] } @@ -4114,7 +4262,7 @@ Sched<[WriteFImm]> { bits<5> Rd; bits<8> imm; - let Inst{31-23} = 0b000111100; + let Inst{31-24} = 0b00011110; let Inst{21} = 1; let Inst{20-13} = imm; let Inst{12-5} = 0b10000000; @@ -4122,12 +4270,17 @@ } multiclass FPMoveImmediate { + def Hi : BaseFPMoveImmediate { + let Inst{23-22} = 0b11; + let Predicates = [HasFullFP16]; + } + def Si : BaseFPMoveImmediate { - let Inst{22} = 0; + let Inst{23-22} = 0b00; } def Di : BaseFPMoveImmediate { - let Inst{22} = 1; + let Inst{23-22} = 0b01; } } } // end of 'let Predicates = [HasFPARMv8]' Index: llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp =================================================================== --- llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -3963,7 +3963,7 @@ AArch64Operand &ImmOp = static_cast(*Operands[2]); if (RegOp.isReg() && ImmOp.isFPImm() && ImmOp.getFPImm() == (unsigned)-1) { unsigned zreg = - AArch64MCRegisterClasses[AArch64::FPR32RegClassID].contains( + !AArch64MCRegisterClasses[AArch64::FPR64RegClassID].contains( RegOp.getReg()) ? AArch64::WZR : AArch64::XZR; Index: llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h =================================================================== --- llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h +++ llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h @@ -364,6 +364,32 @@ return FPUnion.F; } +/// getFP16Imm - Return an 8-bit floating-point version of the 16-bit +/// floating-point value. If the value cannot be represented as an 8-bit +/// floating-point value, then return -1. +static inline int getFP16Imm(const APInt &Imm) { + uint32_t Sign = Imm.lshr(15).getZExtValue() & 1; + int32_t Exp = (Imm.lshr(10).getSExtValue() & 0x1f) - 15; // -14 to 15 + int32_t Mantissa = Imm.getZExtValue() & 0x3ff; // 10 bits + + // We can handle 4 bits of mantissa. + // mantissa = (16+UInt(e:f:g:h))/16. + if (Mantissa & 0x3f) + return -1; + Mantissa >>= 6; + + // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3 + if (Exp < -3 || Exp > 4) + return -1; + Exp = ((Exp+3) & 0x7) ^ 4; + + return ((int)Sign << 7) | (Exp << 4) | Mantissa; +} + +static inline int getFP16Imm(const APFloat &FPImm) { + return getFP16Imm(FPImm.bitcastToAPInt()); +} + /// getFP32Imm - Return an 8-bit floating-point version of the 32-bit /// floating-point value. If the value cannot be represented as an 8-bit /// floating-point value, then return -1. Index: llvm/trunk/test/MC/AArch64/arm64-fp-encoding.s =================================================================== --- llvm/trunk/test/MC/AArch64/arm64-fp-encoding.s +++ llvm/trunk/test/MC/AArch64/arm64-fp-encoding.s @@ -1,99 +1,165 @@ -; RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon -show-encoding -output-asm-variant=1 < %s | FileCheck %s +; RUN: not llvm-mc -triple arm64-apple-darwin -mattr=neon -show-encoding -output-asm-variant=1 < %s 2>%t | FileCheck %s +; RUN: FileCheck %s < %t --check-prefix=NO-FP16 +; RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon,v8.2a,fullfp16 -show-encoding -output-asm-variant=1 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FP16 foo: ;----------------------------------------------------------------------------- ; Floating-point arithmetic ;----------------------------------------------------------------------------- + fabs h1, h2 fabs s1, s2 fabs d1, d2 +; FP16: fabs h1, h2 ; encoding: [0x41,0xc0,0xe0,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fabs h1, h2 ; CHECK: fabs s1, s2 ; encoding: [0x41,0xc0,0x20,0x1e] ; CHECK: fabs d1, d2 ; encoding: [0x41,0xc0,0x60,0x1e] + fadd h1, h2, h3 fadd s1, s2, s3 fadd d1, d2, d3 +; FP16: fadd h1, h2, h3 ; encoding: [0x41,0x28,0xe3,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fadd h1, h2, h3 ; CHECK: fadd s1, s2, s3 ; encoding: [0x41,0x28,0x23,0x1e] ; CHECK: fadd d1, d2, d3 ; encoding: [0x41,0x28,0x63,0x1e] + fdiv h1, h2, h3 fdiv s1, s2, s3 fdiv d1, d2, d3 +; FP16: fdiv h1, h2, h3 ; encoding: [0x41,0x18,0xe3,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fdiv h1, h2, h3 ; CHECK: fdiv s1, s2, s3 ; encoding: [0x41,0x18,0x23,0x1e] ; CHECK: fdiv d1, d2, d3 ; encoding: [0x41,0x18,0x63,0x1e] + fmadd h1, h2, h3, h4 fmadd s1, s2, s3, s4 fmadd d1, d2, d3, d4 +; FP16: fmadd h1, h2, h3, h4 ; encoding: [0x41,0x10,0xc3,0x1f] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fmadd h1, h2, h3, h4 ; CHECK: fmadd s1, s2, s3, s4 ; encoding: [0x41,0x10,0x03,0x1f] ; CHECK: fmadd d1, d2, d3, d4 ; encoding: [0x41,0x10,0x43,0x1f] + fmax h1, h2, h3 fmax s1, s2, s3 fmax d1, d2, d3 + fmaxnm h1, h2, h3 fmaxnm s1, s2, s3 fmaxnm d1, d2, d3 +; FP16: fmax h1, h2, h3 ; encoding: [0x41,0x48,0xe3,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fmax h1, h2, h3 ; CHECK: fmax s1, s2, s3 ; encoding: [0x41,0x48,0x23,0x1e] ; CHECK: fmax d1, d2, d3 ; encoding: [0x41,0x48,0x63,0x1e] +; FP16: fmaxnm h1, h2, h3 ; encoding: [0x41,0x68,0xe3,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fmaxnm h1, h2, h3 ; CHECK: fmaxnm s1, s2, s3 ; encoding: [0x41,0x68,0x23,0x1e] ; CHECK: fmaxnm d1, d2, d3 ; encoding: [0x41,0x68,0x63,0x1e] + fmin h1, h2, h3 fmin s1, s2, s3 fmin d1, d2, d3 + fminnm h1, h2, h3 fminnm s1, s2, s3 fminnm d1, d2, d3 +; FP16: fmin h1, h2, h3 ; encoding: [0x41,0x58,0xe3,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fmin h1, h2, h3 ; CHECK: fmin s1, s2, s3 ; encoding: [0x41,0x58,0x23,0x1e] ; CHECK: fmin d1, d2, d3 ; encoding: [0x41,0x58,0x63,0x1e] +; FP16: fminnm h1, h2, h3 ; encoding: [0x41,0x78,0xe3,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fminnm h1, h2, h3 ; CHECK: fminnm s1, s2, s3 ; encoding: [0x41,0x78,0x23,0x1e] ; CHECK: fminnm d1, d2, d3 ; encoding: [0x41,0x78,0x63,0x1e] + fmsub h1, h2, h3, h4 fmsub s1, s2, s3, s4 fmsub d1, d2, d3, d4 +; FP16: fmsub h1, h2, h3, h4 ; encoding: [0x41,0x90,0xc3,0x1f] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fmsub h1, h2, h3, h4 ; CHECK: fmsub s1, s2, s3, s4 ; encoding: [0x41,0x90,0x03,0x1f] ; CHECK: fmsub d1, d2, d3, d4 ; encoding: [0x41,0x90,0x43,0x1f] + fmul h1, h2, h3 fmul s1, s2, s3 fmul d1, d2, d3 +; FP16: fmul h1, h2, h3 ; encoding: [0x41,0x08,0xe3,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fmul h1, h2, h3 ; CHECK: fmul s1, s2, s3 ; encoding: [0x41,0x08,0x23,0x1e] ; CHECK: fmul d1, d2, d3 ; encoding: [0x41,0x08,0x63,0x1e] + fneg h1, h2 fneg s1, s2 fneg d1, d2 +; FP16: fneg h1, h2 ; encoding: [0x41,0x40,0xe1,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fneg h1, h2 ; CHECK: fneg s1, s2 ; encoding: [0x41,0x40,0x21,0x1e] ; CHECK: fneg d1, d2 ; encoding: [0x41,0x40,0x61,0x1e] + fnmadd h1, h2, h3, h4 fnmadd s1, s2, s3, s4 fnmadd d1, d2, d3, d4 +; FP16: fnmadd h1, h2, h3, h4 ; encoding: [0x41,0x10,0xe3,0x1f] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fnmadd h1, h2, h3, h4 ; CHECK: fnmadd s1, s2, s3, s4 ; encoding: [0x41,0x10,0x23,0x1f] ; CHECK: fnmadd d1, d2, d3, d4 ; encoding: [0x41,0x10,0x63,0x1f] + fnmsub h1, h2, h3, h4 fnmsub s1, s2, s3, s4 fnmsub d1, d2, d3, d4 +; FP16: fnmsub h1, h2, h3, h4 ; encoding: [0x41,0x90,0xe3,0x1f] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fnmsub h1, h2, h3, h4 ; CHECK: fnmsub s1, s2, s3, s4 ; encoding: [0x41,0x90,0x23,0x1f] ; CHECK: fnmsub d1, d2, d3, d4 ; encoding: [0x41,0x90,0x63,0x1f] + fnmul h1, h2, h3 fnmul s1, s2, s3 fnmul d1, d2, d3 +; FP16: fnmul h1, h2, h3 ; encoding: [0x41,0x88,0xe3,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fnmul h1, h2, h3 ; CHECK: fnmul s1, s2, s3 ; encoding: [0x41,0x88,0x23,0x1e] ; CHECK: fnmul d1, d2, d3 ; encoding: [0x41,0x88,0x63,0x1e] + fsqrt h1, h2 fsqrt s1, s2 fsqrt d1, d2 +; FP16: fsqrt h1, h2 ; encoding: [0x41,0xc0,0xe1,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fsqrt h1, h2 ; CHECK: fsqrt s1, s2 ; encoding: [0x41,0xc0,0x21,0x1e] ; CHECK: fsqrt d1, d2 ; encoding: [0x41,0xc0,0x61,0x1e] + fsub h1, h2, h3 fsub s1, s2, s3 fsub d1, d2, d3 +; FP16: fsub h1, h2, h3 ; encoding: [0x41,0x38,0xe3,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fsub h1, h2, h3 ; CHECK: fsub s1, s2, s3 ; encoding: [0x41,0x38,0x23,0x1e] ; CHECK: fsub d1, d2, d3 ; encoding: [0x41,0x38,0x63,0x1e] @@ -101,31 +167,55 @@ ; Floating-point comparison ;----------------------------------------------------------------------------- + fccmp h1, h2, #0, eq fccmp s1, s2, #0, eq fccmp d1, d2, #0, eq + fccmpe h1, h2, #0, eq fccmpe s1, s2, #0, eq fccmpe d1, d2, #0, eq +; FP16: fccmp h1, h2, #0, eq ; encoding: [0x20,0x04,0xe2,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fccmp h1, h2, #0, eq ; CHECK: fccmp s1, s2, #0, eq ; encoding: [0x20,0x04,0x22,0x1e] ; CHECK: fccmp d1, d2, #0, eq ; encoding: [0x20,0x04,0x62,0x1e] +; FP16: fccmpe h1, h2, #0, eq ; encoding: [0x30,0x04,0xe2,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fccmpe h1, h2, #0, eq ; CHECK: fccmpe s1, s2, #0, eq ; encoding: [0x30,0x04,0x22,0x1e] ; CHECK: fccmpe d1, d2, #0, eq ; encoding: [0x30,0x04,0x62,0x1e] + fcmp h1, h2 fcmp s1, s2 fcmp d1, d2 + fcmp h1, #0.0 fcmp s1, #0.0 fcmp d1, #0.0 + fcmpe h1, h2 fcmpe s1, s2 fcmpe d1, d2 + fcmpe h1, #0.0 fcmpe s1, #0.0 fcmpe d1, #0.0 +; FP16: fcmp h1, h2 ; encoding: [0x20,0x20,0xe2,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fcmp h1, h2 ; CHECK: fcmp s1, s2 ; encoding: [0x20,0x20,0x22,0x1e] ; CHECK: fcmp d1, d2 ; encoding: [0x20,0x20,0x62,0x1e] +; FP16: fcmp h1, #0.0 ; encoding: [0x28,0x20,0xe0,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fcmp h1, #0.0 ; CHECK: fcmp s1, #0.0 ; encoding: [0x28,0x20,0x20,0x1e] ; CHECK: fcmp d1, #0.0 ; encoding: [0x28,0x20,0x60,0x1e] +; FP16: fcmpe h1, h2 ; encoding: [0x30,0x20,0xe2,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fcmpe h1, h2 ; CHECK: fcmpe s1, s2 ; encoding: [0x30,0x20,0x22,0x1e] ; CHECK: fcmpe d1, d2 ; encoding: [0x30,0x20,0x62,0x1e] +; FP16: fcmpe h1, #0.0 ; encoding: [0x38,0x20,0xe0,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fcmpe h1, #0.0 ; CHECK: fcmpe s1, #0.0 ; encoding: [0x38,0x20,0x20,0x1e] ; CHECK: fcmpe d1, #0.0 ; encoding: [0x38,0x20,0x60,0x1e] @@ -133,9 +223,13 @@ ; Floating-point conditional select ;----------------------------------------------------------------------------- + fcsel h1, h2, h3, eq fcsel s1, s2, s3, eq fcsel d1, d2, d3, eq +; FP16: fcsel h1, h2, h3, eq ; encoding: [0x41,0x0c,0xe3,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fcsel h1, h2, h3, eq ; CHECK: fcsel s1, s2, s3, eq ; encoding: [0x41,0x0c,0x23,0x1e] ; CHECK: fcsel d1, d2, d3, eq ; encoding: [0x41,0x0c,0x63,0x1e] @@ -161,168 +255,314 @@ fcvtas x1, d2 fcvtas w1, s2 fcvtas x1, s2 + fcvtas w1, h2 + fcvtas x1, h2 -; CHECK: fcvtas w1, d2 ; encoding: [0x41,0x00,0x64,0x1e] -; CHECK: fcvtas x1, d2 ; encoding: [0x41,0x00,0x64,0x9e] -; CHECK: fcvtas w1, s2 ; encoding: [0x41,0x00,0x24,0x1e] -; CHECK: fcvtas x1, s2 ; encoding: [0x41,0x00,0x24,0x9e] +; CHECK: fcvtas w1, d2 ; encoding: [0x41,0x00,0x64,0x1e] +; CHECK: fcvtas x1, d2 ; encoding: [0x41,0x00,0x64,0x9e] +; CHECK: fcvtas w1, s2 ; encoding: [0x41,0x00,0x24,0x1e] +; CHECK: fcvtas x1, s2 ; encoding: [0x41,0x00,0x24,0x9e] +; FP16: fcvtas w1, h2 ; encoding: [0x41,0x00,0xe4,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fcvtas w1, h2 +; FP16: fcvtas x1, h2 ; encoding: [0x41,0x00,0xe4,0x9e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fcvtas x1, h2 + fcvtau w1, h2 fcvtau w1, s2 fcvtau w1, d2 + fcvtau x1, h2 fcvtau x1, s2 fcvtau x1, d2 -; CHECK: fcvtau w1, s2 ; encoding: [0x41,0x00,0x25,0x1e] -; CHECK: fcvtau w1, d2 ; encoding: [0x41,0x00,0x65,0x1e] -; CHECK: fcvtau x1, s2 ; encoding: [0x41,0x00,0x25,0x9e] -; CHECK: fcvtau x1, d2 ; encoding: [0x41,0x00,0x65,0x9e] +; FP16: fcvtau w1, h2 ; encoding: [0x41,0x00,0xe5,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fcvtau w1, h2 +; CHECK: fcvtau w1, s2 ; encoding: [0x41,0x00,0x25,0x1e] +; CHECK: fcvtau w1, d2 ; encoding: [0x41,0x00,0x65,0x1e] +; FP16: fcvtau x1, h2 ; encoding: [0x41,0x00,0xe5,0x9e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fcvtau x1, h2 +; CHECK: fcvtau x1, s2 ; encoding: [0x41,0x00,0x25,0x9e] +; CHECK: fcvtau x1, d2 ; encoding: [0x41,0x00,0x65,0x9e] + fcvtms w1, h2 fcvtms w1, s2 fcvtms w1, d2 + fcvtms x1, h2 fcvtms x1, s2 fcvtms x1, d2 -; CHECK: fcvtms w1, s2 ; encoding: [0x41,0x00,0x30,0x1e] -; CHECK: fcvtms w1, d2 ; encoding: [0x41,0x00,0x70,0x1e] -; CHECK: fcvtms x1, s2 ; encoding: [0x41,0x00,0x30,0x9e] -; CHECK: fcvtms x1, d2 ; encoding: [0x41,0x00,0x70,0x9e] +; FP16: fcvtms w1, h2 ; encoding: [0x41,0x00,0xf0,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fcvtms w1, h2 +; CHECK: fcvtms w1, s2 ; encoding: [0x41,0x00,0x30,0x1e] +; CHECK: fcvtms w1, d2 ; encoding: [0x41,0x00,0x70,0x1e] +; FP16: fcvtms x1, h2 ; encoding: [0x41,0x00,0xf0,0x9e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fcvtms x1, h2 +; CHECK: fcvtms x1, s2 ; encoding: [0x41,0x00,0x30,0x9e] +; CHECK: fcvtms x1, d2 ; encoding: [0x41,0x00,0x70,0x9e] + fcvtmu w1, h2 fcvtmu w1, s2 fcvtmu w1, d2 + fcvtmu x1, h2 fcvtmu x1, s2 fcvtmu x1, d2 -; CHECK: fcvtmu w1, s2 ; encoding: [0x41,0x00,0x31,0x1e] -; CHECK: fcvtmu w1, d2 ; encoding: [0x41,0x00,0x71,0x1e] -; CHECK: fcvtmu x1, s2 ; encoding: [0x41,0x00,0x31,0x9e] -; CHECK: fcvtmu x1, d2 ; encoding: [0x41,0x00,0x71,0x9e] +; FP16: fcvtmu w1, h2 ; encoding: [0x41,0x00,0xf1,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fcvtmu w1, h2 +; CHECK: fcvtmu w1, s2 ; encoding: [0x41,0x00,0x31,0x1e] +; CHECK: fcvtmu w1, d2 ; encoding: [0x41,0x00,0x71,0x1e] +; FP16: fcvtmu x1, h2 ; encoding: [0x41,0x00,0xf1,0x9e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fcvtmu x1, h2 +; CHECK: fcvtmu x1, s2 ; encoding: [0x41,0x00,0x31,0x9e] +; CHECK: fcvtmu x1, d2 ; encoding: [0x41,0x00,0x71,0x9e] + fcvtns w1, h2 fcvtns w1, s2 fcvtns w1, d2 + fcvtns x1, h2 fcvtns x1, s2 fcvtns x1, d2 -; CHECK: fcvtns w1, s2 ; encoding: [0x41,0x00,0x20,0x1e] -; CHECK: fcvtns w1, d2 ; encoding: [0x41,0x00,0x60,0x1e] -; CHECK: fcvtns x1, s2 ; encoding: [0x41,0x00,0x20,0x9e] -; CHECK: fcvtns x1, d2 ; encoding: [0x41,0x00,0x60,0x9e] +; FP16: fcvtns w1, h2 ; encoding: [0x41,0x00,0xe0,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fcvtns w1, h2 +; CHECK: fcvtns w1, s2 ; encoding: [0x41,0x00,0x20,0x1e] +; CHECK: fcvtns w1, d2 ; encoding: [0x41,0x00,0x60,0x1e] +; FP16: fcvtns x1, h2 ; encoding: [0x41,0x00,0xe0,0x9e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fcvtns x1, h2 +; CHECK: fcvtns x1, s2 ; encoding: [0x41,0x00,0x20,0x9e] +; CHECK: fcvtns x1, d2 ; encoding: [0x41,0x00,0x60,0x9e] + fcvtnu w1, h2 fcvtnu w1, s2 fcvtnu w1, d2 + fcvtnu x1, h2 fcvtnu x1, s2 fcvtnu x1, d2 -; CHECK: fcvtnu w1, s2 ; encoding: [0x41,0x00,0x21,0x1e] -; CHECK: fcvtnu w1, d2 ; encoding: [0x41,0x00,0x61,0x1e] -; CHECK: fcvtnu x1, s2 ; encoding: [0x41,0x00,0x21,0x9e] -; CHECK: fcvtnu x1, d2 ; encoding: [0x41,0x00,0x61,0x9e] +; FP16: fcvtnu w1, h2 ; encoding: [0x41,0x00,0xe1,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fcvtnu w1, h2 +; CHECK: fcvtnu w1, s2 ; encoding: [0x41,0x00,0x21,0x1e] +; CHECK: fcvtnu w1, d2 ; encoding: [0x41,0x00,0x61,0x1e] +; FP16: fcvtnu x1, h2 ; encoding: [0x41,0x00,0xe1,0x9e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fcvtnu x1, h2 +; CHECK: fcvtnu x1, s2 ; encoding: [0x41,0x00,0x21,0x9e] +; CHECK: fcvtnu x1, d2 ; encoding: [0x41,0x00,0x61,0x9e] + fcvtps w1, h2 fcvtps w1, s2 fcvtps w1, d2 + fcvtps x1, h2 fcvtps x1, s2 fcvtps x1, d2 -; CHECK: fcvtps w1, s2 ; encoding: [0x41,0x00,0x28,0x1e] -; CHECK: fcvtps w1, d2 ; encoding: [0x41,0x00,0x68,0x1e] -; CHECK: fcvtps x1, s2 ; encoding: [0x41,0x00,0x28,0x9e] -; CHECK: fcvtps x1, d2 ; encoding: [0x41,0x00,0x68,0x9e] +; FP16: fcvtps w1, h2 ; encoding: [0x41,0x00,0xe8,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fcvtps w1, h2 +; CHECK: fcvtps w1, s2 ; encoding: [0x41,0x00,0x28,0x1e] +; CHECK: fcvtps w1, d2 ; encoding: [0x41,0x00,0x68,0x1e] +; FP16: fcvtps x1, h2 ; encoding: [0x41,0x00,0xe8,0x9e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fcvtps x1, h2 +; CHECK: fcvtps x1, s2 ; encoding: [0x41,0x00,0x28,0x9e] +; CHECK: fcvtps x1, d2 ; encoding: [0x41,0x00,0x68,0x9e] + fcvtpu w1, h2 fcvtpu w1, s2 fcvtpu w1, d2 + fcvtpu x1, h2 fcvtpu x1, s2 fcvtpu x1, d2 -; CHECK: fcvtpu w1, s2 ; encoding: [0x41,0x00,0x29,0x1e] -; CHECK: fcvtpu w1, d2 ; encoding: [0x41,0x00,0x69,0x1e] -; CHECK: fcvtpu x1, s2 ; encoding: [0x41,0x00,0x29,0x9e] -; CHECK: fcvtpu x1, d2 ; encoding: [0x41,0x00,0x69,0x9e] +; FP16: fcvtpu w1, h2 ; encoding: [0x41,0x00,0xe9,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fcvtpu w1, h2 +; CHECK: fcvtpu w1, s2 ; encoding: [0x41,0x00,0x29,0x1e] +; CHECK: fcvtpu w1, d2 ; encoding: [0x41,0x00,0x69,0x1e] +; FP16: fcvtpu x1, h2 ; encoding: [0x41,0x00,0xe9,0x9e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fcvtpu x1, h2 +; CHECK: fcvtpu x1, s2 ; encoding: [0x41,0x00,0x29,0x9e] +; CHECK: fcvtpu x1, d2 ; encoding: [0x41,0x00,0x69,0x9e] + fcvtzs w1, h2 + fcvtzs w1, h2, #1 fcvtzs w1, s2 fcvtzs w1, s2, #1 fcvtzs w1, d2 fcvtzs w1, d2, #1 + fcvtzs x1, h2 + fcvtzs x1, h2, #1 fcvtzs x1, s2 fcvtzs x1, s2, #1 fcvtzs x1, d2 fcvtzs x1, d2, #1 -; CHECK: fcvtzs w1, s2 ; encoding: [0x41,0x00,0x38,0x1e] -; CHECK: fcvtzs w1, s2, #1 ; encoding: [0x41,0xfc,0x18,0x1e] -; CHECK: fcvtzs w1, d2 ; encoding: [0x41,0x00,0x78,0x1e] -; CHECK: fcvtzs w1, d2, #1 ; encoding: [0x41,0xfc,0x58,0x1e] -; CHECK: fcvtzs x1, s2 ; encoding: [0x41,0x00,0x38,0x9e] -; CHECK: fcvtzs x1, s2, #1 ; encoding: [0x41,0xfc,0x18,0x9e] -; CHECK: fcvtzs x1, d2 ; encoding: [0x41,0x00,0x78,0x9e] -; CHECK: fcvtzs x1, d2, #1 ; encoding: [0x41,0xfc,0x58,0x9e] +; FP16: fcvtzs w1, h2 ; encoding: [0x41,0x00,0xf8,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fcvtzs w1, h2 +; FP16: fcvtzs w1, h2, #1 ; encoding: [0x41,0xfc,0xd8,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fcvtzs w1, h2, #1 +; CHECK: fcvtzs w1, s2 ; encoding: [0x41,0x00,0x38,0x1e] +; CHECK: fcvtzs w1, s2, #1 ; encoding: [0x41,0xfc,0x18,0x1e] +; CHECK: fcvtzs w1, d2 ; encoding: [0x41,0x00,0x78,0x1e] +; CHECK: fcvtzs w1, d2, #1 ; encoding: [0x41,0xfc,0x58,0x1e] +; FP16: fcvtzs x1, h2 ; encoding: [0x41,0x00,0xf8,0x9e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fcvtzs x1, h2 +; FP16: fcvtzs x1, h2, #1 ; encoding: [0x41,0xfc,0xd8,0x9e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fcvtzs x1, h2, #1 +; CHECK: fcvtzs x1, s2 ; encoding: [0x41,0x00,0x38,0x9e] +; CHECK: fcvtzs x1, s2, #1 ; encoding: [0x41,0xfc,0x18,0x9e] +; CHECK: fcvtzs x1, d2 ; encoding: [0x41,0x00,0x78,0x9e] +; CHECK: fcvtzs x1, d2, #1 ; encoding: [0x41,0xfc,0x58,0x9e] + fcvtzu w1, h2 + fcvtzu w1, h2, #1 fcvtzu w1, s2 fcvtzu w1, s2, #1 fcvtzu w1, d2 fcvtzu w1, d2, #1 + fcvtzu x1, h2 + fcvtzu x1, h2, #1 fcvtzu x1, s2 fcvtzu x1, s2, #1 fcvtzu x1, d2 fcvtzu x1, d2, #1 -; CHECK: fcvtzu w1, s2 ; encoding: [0x41,0x00,0x39,0x1e] -; CHECK: fcvtzu w1, s2, #1 ; encoding: [0x41,0xfc,0x19,0x1e] -; CHECK: fcvtzu w1, d2 ; encoding: [0x41,0x00,0x79,0x1e] -; CHECK: fcvtzu w1, d2, #1 ; encoding: [0x41,0xfc,0x59,0x1e] -; CHECK: fcvtzu x1, s2 ; encoding: [0x41,0x00,0x39,0x9e] -; CHECK: fcvtzu x1, s2, #1 ; encoding: [0x41,0xfc,0x19,0x9e] -; CHECK: fcvtzu x1, d2 ; encoding: [0x41,0x00,0x79,0x9e] -; CHECK: fcvtzu x1, d2, #1 ; encoding: [0x41,0xfc,0x59,0x9e] +; FP16: fcvtzu w1, h2 ; encoding: [0x41,0x00,0xf9,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fcvtzu w1, h2 +; FP16: fcvtzu w1, h2, #1 ; encoding: [0x41,0xfc,0xd9,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fcvtzu w1, h2, #1 +; CHECK: fcvtzu w1, s2 ; encoding: [0x41,0x00,0x39,0x1e] +; CHECK: fcvtzu w1, s2, #1 ; encoding: [0x41,0xfc,0x19,0x1e] +; CHECK: fcvtzu w1, d2 ; encoding: [0x41,0x00,0x79,0x1e] +; CHECK: fcvtzu w1, d2, #1 ; encoding: [0x41,0xfc,0x59,0x1e] +; FP16: fcvtzu x1, h2 ; encoding: [0x41,0x00,0xf9,0x9e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fcvtzu x1, h2 +; FP16: fcvtzu x1, h2, #1 ; encoding: [0x41,0xfc,0xd9,0x9e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fcvtzu x1, h2, #1 +; CHECK: fcvtzu x1, s2 ; encoding: [0x41,0x00,0x39,0x9e] +; CHECK: fcvtzu x1, s2, #1 ; encoding: [0x41,0xfc,0x19,0x9e] +; CHECK: fcvtzu x1, d2 ; encoding: [0x41,0x00,0x79,0x9e] +; CHECK: fcvtzu x1, d2, #1 ; encoding: [0x41,0xfc,0x59,0x9e] + scvtf h1, w2 + scvtf h1, w2, #1 scvtf s1, w2 scvtf s1, w2, #1 scvtf d1, w2 scvtf d1, w2, #1 + scvtf h1, x2 + scvtf h1, x2, #1 scvtf s1, x2 scvtf s1, x2, #1 scvtf d1, x2 scvtf d1, x2, #1 -; CHECK: scvtf s1, w2 ; encoding: [0x41,0x00,0x22,0x1e] -; CHECK: scvtf s1, w2, #1 ; encoding: [0x41,0xfc,0x02,0x1e] -; CHECK: scvtf d1, w2 ; encoding: [0x41,0x00,0x62,0x1e] -; CHECK: scvtf d1, w2, #1 ; encoding: [0x41,0xfc,0x42,0x1e] -; CHECK: scvtf s1, x2 ; encoding: [0x41,0x00,0x22,0x9e] -; CHECK: scvtf s1, x2, #1 ; encoding: [0x41,0xfc,0x02,0x9e] -; CHECK: scvtf d1, x2 ; encoding: [0x41,0x00,0x62,0x9e] -; CHECK: scvtf d1, x2, #1 ; encoding: [0x41,0xfc,0x42,0x9e] +; FP16: scvtf h1, w2 ; encoding: [0x41,0x00,0xe2,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: scvtf h1, w2 +; FP16: scvtf h1, w2, #1 ; encoding: [0x41,0xfc,0xc2,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: scvtf h1, w2, #1 +; CHECK: scvtf s1, w2 ; encoding: [0x41,0x00,0x22,0x1e] +; CHECK: scvtf s1, w2, #1 ; encoding: [0x41,0xfc,0x02,0x1e] +; CHECK: scvtf d1, w2 ; encoding: [0x41,0x00,0x62,0x1e] +; CHECK: scvtf d1, w2, #1 ; encoding: [0x41,0xfc,0x42,0x1e] +; FP16: scvtf h1, x2 ; encoding: [0x41,0x00,0xe2,0x9e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: scvtf h1, x2 +; FP16: scvtf h1, x2, #1 ; encoding: [0x41,0xfc,0xc2,0x9e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: scvtf h1, x2, #1 +; CHECK: scvtf s1, x2 ; encoding: [0x41,0x00,0x22,0x9e] +; CHECK: scvtf s1, x2, #1 ; encoding: [0x41,0xfc,0x02,0x9e] +; CHECK: scvtf d1, x2 ; encoding: [0x41,0x00,0x62,0x9e] +; CHECK: scvtf d1, x2, #1 ; encoding: [0x41,0xfc,0x42,0x9e] + ucvtf h1, w2 + ucvtf h1, w2, #1 ucvtf s1, w2 ucvtf s1, w2, #1 ucvtf d1, w2 ucvtf d1, w2, #1 + ucvtf h1, x2 + ucvtf h1, x2, #1 ucvtf s1, x2 ucvtf s1, x2, #1 ucvtf d1, x2 ucvtf d1, x2, #1 -; CHECK: ucvtf s1, w2 ; encoding: [0x41,0x00,0x23,0x1e] -; CHECK: ucvtf s1, w2, #1 ; encoding: [0x41,0xfc,0x03,0x1e] -; CHECK: ucvtf d1, w2 ; encoding: [0x41,0x00,0x63,0x1e] -; CHECK: ucvtf d1, w2, #1 ; encoding: [0x41,0xfc,0x43,0x1e] -; CHECK: ucvtf s1, x2 ; encoding: [0x41,0x00,0x23,0x9e] -; CHECK: ucvtf s1, x2, #1 ; encoding: [0x41,0xfc,0x03,0x9e] -; CHECK: ucvtf d1, x2 ; encoding: [0x41,0x00,0x63,0x9e] -; CHECK: ucvtf d1, x2, #1 ; encoding: [0x41,0xfc,0x43,0x9e] +; FP16: ucvtf h1, w2 ; encoding: [0x41,0x00,0xe3,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: ucvtf h1, w2 +; FP16: ucvtf h1, w2, #1 ; encoding: [0x41,0xfc,0xc3,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: ucvtf h1, w2, #1 +; CHECK: ucvtf s1, w2 ; encoding: [0x41,0x00,0x23,0x1e] +; CHECK: ucvtf s1, w2, #1 ; encoding: [0x41,0xfc,0x03,0x1e] +; CHECK: ucvtf d1, w2 ; encoding: [0x41,0x00,0x63,0x1e] +; CHECK: ucvtf d1, w2, #1 ; encoding: [0x41,0xfc,0x43,0x1e] +; FP16: ucvtf h1, x2 ; encoding: [0x41,0x00,0xe3,0x9e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: ucvtf h1, x2 +; FP16: ucvtf h1, x2, #1 ; encoding: [0x41,0xfc,0xc3,0x9e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: ucvtf h1, x2, #1 +; CHECK: ucvtf s1, x2 ; encoding: [0x41,0x00,0x23,0x9e] +; CHECK: ucvtf s1, x2, #1 ; encoding: [0x41,0xfc,0x03,0x9e] +; CHECK: ucvtf d1, x2 ; encoding: [0x41,0x00,0x63,0x9e] +; CHECK: ucvtf d1, x2, #1 ; encoding: [0x41,0xfc,0x43,0x9e] ;----------------------------------------------------------------------------- ; Floating-point move ;----------------------------------------------------------------------------- + fmov h1, w2 + fmov w1, h2 + fmov h1, x2 + fmov x1, h2 fmov s1, w2 fmov w1, s2 fmov d1, x2 fmov x1, d2 +; FP16: fmov h1, w2 ; encoding: [0x41,0x00,0xe7,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fmov h1, w2 +; FP16: fmov w1, h2 ; encoding: [0x41,0x00,0xe6,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fmov w1, h2 +; FP16: fmov h1, x2 ; encoding: [0x41,0x00,0xe7,0x9e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fmov h1, x2 +; FP16: fmov x1, h2 ; encoding: [0x41,0x00,0xe6,0x9e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fmov x1, h2 ; CHECK: fmov s1, w2 ; encoding: [0x41,0x00,0x27,0x1e] ; CHECK: fmov w1, s2 ; encoding: [0x41,0x00,0x26,0x1e] ; CHECK: fmov d1, x2 ; encoding: [0x41,0x00,0x67,0x9e] ; CHECK: fmov x1, d2 ; encoding: [0x41,0x00,0x66,0x9e] + fmov h1, #0.125 + fmov h1, #0x40 fmov s1, #0.125 fmov s1, #0x40 fmov d1, #0.125 @@ -330,9 +570,16 @@ fmov d1, #-4.843750e-01 fmov d1, #4.843750e-01 fmov d3, #3 + fmov h2, #0.0 fmov s2, #0.0 fmov d2, #0.0 +; FP16: fmov h1, #0.12500000 ; encoding: [0x01,0x10,0xe8,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fmov h1, #0.125 +; FP16: fmov h1, #0.12500000 ; encoding: [0x01,0x10,0xe8,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fmov h1, #0x40 ; CHECK: fmov s1, #0.12500000 ; encoding: [0x01,0x10,0x28,0x1e] ; CHECK: fmov s1, #0.12500000 ; encoding: [0x01,0x10,0x28,0x1e] ; CHECK: fmov d1, #0.12500000 ; encoding: [0x01,0x10,0x68,0x1e] @@ -340,12 +587,19 @@ ; CHECK: fmov d1, #-0.48437500 ; encoding: [0x01,0xf0,0x7b,0x1e] ; CHECK: fmov d1, #0.48437500 ; encoding: [0x01,0xf0,0x6b,0x1e] ; CHECK: fmov d3, #3.00000000 ; encoding: [0x03,0x10,0x61,0x1e] +; FP16: fmov h2, wzr ; encoding: [0xe2,0x03,0xe7,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fmov h2, #0.0 ; CHECK: fmov s2, wzr ; encoding: [0xe2,0x03,0x27,0x1e] ; CHECK: fmov d2, xzr ; encoding: [0xe2,0x03,0x67,0x9e] + fmov h1, h2 fmov s1, s2 fmov d1, d2 +; FP16: fmov h1, h2 ; encoding: [0x41,0x40,0xe0,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: fmov h1, h2 ; CHECK: fmov s1, s2 ; encoding: [0x41,0x40,0x20,0x1e] ; CHECK: fmov d1, d2 ; encoding: [0x41,0x40,0x60,0x1e] @@ -355,63 +609,91 @@ fmov v1.d[1], x1 fmov.d v8[1], x6 -; CHECK: fmov.d x2, v5[1] ; encoding: [0xa2,0x00,0xae,0x9e] -; CHECK: fmov.d x9, v7[1] ; encoding: [0xe9,0x00,0xae,0x9e] -; CHECK: fmov.d v1[1], x1 ; encoding: [0x21,0x00,0xaf,0x9e] -; CHECK: fmov.d v8[1], x6 ; encoding: [0xc8,0x00,0xaf,0x9e] +; CHECK: fmov.d x2, v5[1] ; encoding: [0xa2,0x00,0xae,0x9e] +; CHECK: fmov.d x9, v7[1] ; encoding: [0xe9,0x00,0xae,0x9e] +; CHECK: fmov.d v1[1], x1 ; encoding: [0x21,0x00,0xaf,0x9e] +; CHECK: fmov.d v8[1], x6 ; encoding: [0xc8,0x00,0xaf,0x9e] ;----------------------------------------------------------------------------- ; Floating-point round to integral ;----------------------------------------------------------------------------- + frinta h1, h2 frinta s1, s2 frinta d1, d2 +; FP16: frinta h1, h2 ; encoding: [0x41,0x40,0xe6,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: frinta h1, h2 ; CHECK: frinta s1, s2 ; encoding: [0x41,0x40,0x26,0x1e] ; CHECK: frinta d1, d2 ; encoding: [0x41,0x40,0x66,0x1e] + frinti h1, h2 frinti s1, s2 frinti d1, d2 +; FP16: frinti h1, h2 ; encoding: [0x41,0xc0,0xe7,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: frinti h1, h2 ; CHECK: frinti s1, s2 ; encoding: [0x41,0xc0,0x27,0x1e] ; CHECK: frinti d1, d2 ; encoding: [0x41,0xc0,0x67,0x1e] + frintm h1, h2 frintm s1, s2 frintm d1, d2 +; FP16: frintm h1, h2 ; encoding: [0x41,0x40,0xe5,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: frintm h1, h2 ; CHECK: frintm s1, s2 ; encoding: [0x41,0x40,0x25,0x1e] ; CHECK: frintm d1, d2 ; encoding: [0x41,0x40,0x65,0x1e] + frintn h1, h2 frintn s1, s2 frintn d1, d2 +; FP16: frintn h1, h2 ; encoding: [0x41,0x40,0xe4,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: frintn h1, h2 ; CHECK: frintn s1, s2 ; encoding: [0x41,0x40,0x24,0x1e] ; CHECK: frintn d1, d2 ; encoding: [0x41,0x40,0x64,0x1e] + frintp h1, h2 frintp s1, s2 frintp d1, d2 +; FP16: frintp h1, h2 ; encoding: [0x41,0xc0,0xe4,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: frintp h1, h2 ; CHECK: frintp s1, s2 ; encoding: [0x41,0xc0,0x24,0x1e] ; CHECK: frintp d1, d2 ; encoding: [0x41,0xc0,0x64,0x1e] + frintx h1, h2 frintx s1, s2 frintx d1, d2 +; FP16: frintx h1, h2 ; encoding: [0x41,0x40,0xe7,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: frintx h1, h2 ; CHECK: frintx s1, s2 ; encoding: [0x41,0x40,0x27,0x1e] ; CHECK: frintx d1, d2 ; encoding: [0x41,0x40,0x67,0x1e] + frintz h1, h2 frintz s1, s2 frintz d1, d2 +; FP16: frintz h1, h2 ; encoding: [0x41,0xc0,0xe5,0x1e] +; NO-FP16: error: instruction requires: +; NO-FP16-NEXT: frintz h1, h2 ; CHECK: frintz s1, s2 ; encoding: [0x41,0xc0,0x25,0x1e] ; CHECK: frintz d1, d2 ; encoding: [0x41,0xc0,0x65,0x1e] cmhs d0, d0, d0 cmtst d0, d0, d0 -; CHECK: cmhs d0, d0, d0 ; encoding: [0x00,0x3c,0xe0,0x7e] -; CHECK: cmtst d0, d0, d0 ; encoding: [0x00,0x8c,0xe0,0x5e] +; CHECK: cmhs d0, d0, d0 ; encoding: [0x00,0x3c,0xe0,0x7e] +; CHECK: cmtst d0, d0, d0 ; encoding: [0x00,0x8c,0xe0,0x5e] Index: llvm/trunk/test/MC/AArch64/basic-a64-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/basic-a64-diagnostics.s +++ llvm/trunk/test/MC/AArch64/basic-a64-diagnostics.s @@ -1603,7 +1603,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: fcsel q3, q20, q9, pl // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: invalid operand for instruction +// CHECK-ERROR-NEXT: error: instruction requires: fullfp16 // CHECK-ERROR-NEXT: fcsel h9, h10, h11, mi // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction @@ -1652,7 +1652,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: fmadd b3, b4, b5, b6 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: invalid operand for instruction +// CHECK-ERROR-NEXT: error: instruction requires: fullfp16 // CHECK-ERROR-NEXT: fmsub h1, h2, h3, h4 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction Index: llvm/trunk/test/MC/Disassembler/AArch64/arm64-scalar-fp.txt =================================================================== --- llvm/trunk/test/MC/Disassembler/AArch64/arm64-scalar-fp.txt +++ llvm/trunk/test/MC/Disassembler/AArch64/arm64-scalar-fp.txt @@ -1,98 +1,131 @@ # RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon --disassemble -output-asm-variant=1 < %s | FileCheck %s +# RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon,v8.2a,fullfp16 --disassemble -output-asm-variant=1 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FP16 #----------------------------------------------------------------------------- # Floating-point arithmetic #----------------------------------------------------------------------------- +0x41 0xc0 0xe0 0x1e 0x41 0xc0 0x20 0x1e 0x41 0xc0 0x60 0x1e +# FP16: fabs h1, h2 # CHECK: fabs s1, s2 # CHECK: fabs d1, d2 +0x41 0x28 0xe3 0x1e 0x41 0x28 0x23 0x1e 0x41 0x28 0x63 0x1e +# FP16: fadd h1, h2, h3 # CHECK: fadd s1, s2, s3 # CHECK: fadd d1, d2, d3 +0x41 0x18 0xe3 0x1e 0x41 0x18 0x23 0x1e 0x41 0x18 0x63 0x1e +# FP16: fdiv h1, h2, h3 # CHECK: fdiv s1, s2, s3 # CHECK: fdiv d1, d2, d3 +0x41 0x10 0xc3 0x1f 0x41 0x10 0x03 0x1f 0x41 0x10 0x43 0x1f +# FP16: fmadd h1, h2, h3, h4 # CHECK: fmadd s1, s2, s3, s4 # CHECK: fmadd d1, d2, d3, d4 +0x41 0x48 0xe3 0x1e 0x41 0x48 0x23 0x1e 0x41 0x48 0x63 0x1e +0x41 0x68 0xe3 0x1e 0x41 0x68 0x23 0x1e 0x41 0x68 0x63 0x1e +# FP16: fmax h1, h2, h3 # CHECK: fmax s1, s2, s3 # CHECK: fmax d1, d2, d3 +# FP16: fmaxnm h1, h2, h3 # CHECK: fmaxnm s1, s2, s3 # CHECK: fmaxnm d1, d2, d3 +0x41 0x58 0xe3 0x1e 0x41 0x58 0x23 0x1e 0x41 0x58 0x63 0x1e +0x41 0x78 0xe3 0x1e 0x41 0x78 0x23 0x1e 0x41 0x78 0x63 0x1e +# FP16: fmin h1, h2, h3 # CHECK: fmin s1, s2, s3 # CHECK: fmin d1, d2, d3 +# FP16: fminnm h1, h2, h3 # CHECK: fminnm s1, s2, s3 # CHECK: fminnm d1, d2, d3 +0x41 0x90 0xc3 0x1f 0x41 0x90 0x03 0x1f 0x41 0x90 0x43 0x1f +# FP16: fmsub h1, h2, h3, h4 # CHECK: fmsub s1, s2, s3, s4 # CHECK: fmsub d1, d2, d3, d4 +0x41 0x08 0xe3 0x1e 0x41 0x08 0x23 0x1e 0x41 0x08 0x63 0x1e +# FP16: fmul h1, h2, h3 # CHECK: fmul s1, s2, s3 # CHECK: fmul d1, d2, d3 +0x41 0x40 0xe1 0x1e 0x41 0x40 0x21 0x1e 0x41 0x40 0x61 0x1e +# FP16: fneg h1, h2 # CHECK: fneg s1, s2 # CHECK: fneg d1, d2 +0x41 0x10 0xe3 0x1f 0x41 0x10 0x23 0x1f 0x41 0x10 0x63 0x1f +# FP16: fnmadd h1, h2, h3, h4 # CHECK: fnmadd s1, s2, s3, s4 # CHECK: fnmadd d1, d2, d3, d4 +0x41 0x90 0xe3 0x1f 0x41 0x90 0x23 0x1f 0x41 0x90 0x63 0x1f +# FP16: fnmsub h1, h2, h3, h4 # CHECK: fnmsub s1, s2, s3, s4 # CHECK: fnmsub d1, d2, d3, d4 +0x41 0x88 0xe3 0x1e 0x41 0x88 0x23 0x1e 0x41 0x88 0x63 0x1e +# FP16: fnmul h1, h2, h3 # CHECK: fnmul s1, s2, s3 # CHECK: fnmul d1, d2, d3 +0x41 0xc0 0xe1 0x1e 0x41 0xc0 0x21 0x1e 0x41 0xc0 0x61 0x1e +# FP16: fsqrt h1, h2 # CHECK: fsqrt s1, s2 # CHECK: fsqrt d1, d2 +0x41 0x38 0xe3 0x1e 0x41 0x38 0x23 0x1e 0x41 0x38 0x63 0x1e +# FP16: fsub h1, h2, h3 # CHECK: fsub s1, s2, s3 # CHECK: fsub d1, d2, d3 @@ -100,31 +133,43 @@ # Floating-point comparison #----------------------------------------------------------------------------- +0x20 0x04 0xe2 0x1e 0x20 0x04 0x22 0x1e 0x20 0x04 0x62 0x1e +0x30 0x04 0xe2 0x1e 0x30 0x04 0x22 0x1e 0x30 0x04 0x62 0x1e +# FP16: fccmp h1, h2, #0, eq # CHECK: fccmp s1, s2, #0, eq # CHECK: fccmp d1, d2, #0, eq +# FP16: fccmpe h1, h2, #0, eq # CHECK: fccmpe s1, s2, #0, eq # CHECK: fccmpe d1, d2, #0, eq +0x20 0x20 0xe2 0x1e 0x20 0x20 0x22 0x1e 0x20 0x20 0x62 0x1e +0x28 0x20 0xe0 0x1e 0x28 0x20 0x20 0x1e 0x28 0x20 0x60 0x1e +0x30 0x20 0xe2 0x1e 0x30 0x20 0x22 0x1e 0x30 0x20 0x62 0x1e +0x38 0x20 0xe0 0x1e 0x38 0x20 0x20 0x1e 0x38 0x20 0x60 0x1e +# FP16: fcmp h1, h2 # CHECK: fcmp s1, s2 # CHECK: fcmp d1, d2 +# FP16: fcmp h1, #0.0 # CHECK: fcmp s1, #0.0 # CHECK: fcmp d1, #0.0 +# FP16: fcmpe h1, h2 # CHECK: fcmpe s1, s2 # CHECK: fcmpe d1, d2 +# FP16: fcmpe h1, #0.0 # CHECK: fcmpe s1, #0.0 # CHECK: fcmpe d1, #0.0 @@ -132,9 +177,11 @@ # Floating-point conditional select #----------------------------------------------------------------------------- +0x41 0x0c 0xe3 0x1e 0x41 0x0c 0x23 0x1e 0x41 0x0c 0x63 0x1e +# FP16: fcsel h1, h2, h3, eq # CHECK: fcsel s1, s2, s3, eq # CHECK: fcsel d1, d2, d3, eq @@ -169,29 +216,37 @@ # Floating-point move #----------------------------------------------------------------------------- +0x41 0x00 0xe7 0x1e +0x41 0x00 0xe6 0x1e 0x41 0x00 0x27 0x1e 0x41 0x00 0x26 0x1e 0x41 0x00 0x67 0x9e 0x41 0x00 0x66 0x9e +# FP16: fmov h1, w2 +# FP16: fmov w1, h2 # CHECK: fmov s1, w2 # CHECK: fmov w1, s2 # CHECK: fmov d1, x2 # CHECK: fmov x1, d2 +0x01 0x10 0xe8 0x1e 0x01 0x10 0x28 0x1e 0x01 0x10 0x68 0x1e 0x01 0xf0 0x7b 0x1e 0x01 0xf0 0x6b 0x1e +# FP16: fmov h1, #0.12500000 # CHECK: fmov s1, #0.12500000 # CHECK: fmov d1, #0.12500000 # CHECK: fmov d1, #-0.48437500 # CHECK: fmov d1, #0.48437500 +0x41 0x40 0xe0 0x1e 0x41 0x40 0x20 0x1e 0x41 0x40 0x60 0x1e +# FP16: fmov h1, h2 # CHECK: fmov s1, s2 # CHECK: fmov d1, d2 @@ -199,45 +254,59 @@ # Floating-point round to integral #----------------------------------------------------------------------------- +0x41 0x40 0xe6 0x1e 0x41 0x40 0x26 0x1e 0x41 0x40 0x66 0x1e +# FP16: frinta h1, h2 # CHECK: frinta s1, s2 # CHECK: frinta d1, d2 +0x41 0xc0 0xe7 0x1e 0x41 0xc0 0x27 0x1e 0x41 0xc0 0x67 0x1e +# FP16: frinti h1, h2 # CHECK: frinti s1, s2 # CHECK: frinti d1, d2 +0x41 0x40 0xe5 0x1e 0x41 0x40 0x25 0x1e 0x41 0x40 0x65 0x1e +# FP16: frintm h1, h2 # CHECK: frintm s1, s2 # CHECK: frintm d1, d2 +0x41 0x40 0xe4 0x1e 0x41 0x40 0x24 0x1e 0x41 0x40 0x64 0x1e +# FP16: frintn h1, h2 # CHECK: frintn s1, s2 # CHECK: frintn d1, d2 +0x41 0xc0 0xe4 0x1e 0x41 0xc0 0x24 0x1e 0x41 0xc0 0x64 0x1e +# FP16: frintp h1, h2 # CHECK: frintp s1, s2 # CHECK: frintp d1, d2 +0x41 0x40 0xe7 0x1e 0x41 0x40 0x27 0x1e 0x41 0x40 0x67 0x1e +# FP16: frintx h1, h2 # CHECK: frintx s1, s2 # CHECK: frintx d1, d2 +0x41 0xc0 0xe5 0x1e 0x41 0xc0 0x25 0x1e 0x41 0xc0 0x65 0x1e +# FP16: frintz h1, h2 # CHECK: frintz s1, s2 # CHECK: frintz d1, d2 Index: llvm/trunk/test/MC/Disassembler/AArch64/basic-a64-instructions.txt =================================================================== --- llvm/trunk/test/MC/Disassembler/AArch64/basic-a64-instructions.txt +++ llvm/trunk/test/MC/Disassembler/AArch64/basic-a64-instructions.txt @@ -1,5 +1,6 @@ # RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s | FileCheck %s # RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8 -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8,+fullfp16 -disassemble < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FP16 #------------------------------------------------------------------------------ # Add/sub (immediate) @@ -1516,6 +1517,20 @@ # Floating-point <-> fixed-point conversion #------------------------------------------------------------------------------ +# FP16: fcvtzs w3, h5, #1 +# FP16: fcvtzs wzr, h20, #13 +# FP16: fcvtzs w19, h0, #32 +0xa3 0xfc 0xd8 0x1e +0x9f 0xce 0xd8 0x1e +0x13 0x80 0xd8 0x1e + +# FP16: fcvtzs x3, h5, #1 +# FP16: fcvtzs x12, h30, #45 +# FP16: fcvtzs x19, h0, #64 +0xa3 0xfc 0xd8 0x9e +0xcc 0x4f 0xd8 0x9e +0x13 0x00 0xd8 0x9e + # CHECK: fcvtzs w3, s5, #1 # CHECK: fcvtzs wzr, s20, #13 # CHECK: fcvtzs w19, s0, #32 @@ -1544,6 +1559,20 @@ 0xcc 0x4f 0x58 0x9e 0x13 0x00 0x58 0x9e +# FP16: fcvtzu w3, h5, #1 +# FP16: fcvtzu wzr, h20, #13 +# FP16: fcvtzu w19, h0, #32 +0xa3 0xfc 0xd9 0x1e +0x9f 0xce 0xd9 0x1e +0x13 0x80 0xd9 0x1e + +# FP16: fcvtzu x3, h5, #1 +# FP16: fcvtzu x12, h30, #45 +# FP16: fcvtzu x19, h0, #64 +0xa3 0xfc 0xd9 0x9e +0xcc 0x4f 0xd9 0x9e +0x13 0x00 0xd9 0x9e + # CHECK: fcvtzu w3, s5, #1 # CHECK: fcvtzu wzr, s20, #13 # CHECK: fcvtzu w19, s0, #32 @@ -1572,6 +1601,20 @@ 0xcc 0x4f 0x59 0x9e 0x13 0x00 0x59 0x9e +# FP16: scvtf h23, w19, #1 +# FP16: scvtf h31, wzr, #20 +# FP16: scvtf h14, w0, #32 +0x77 0xfe 0xc2 0x1e +0xff 0xb3 0xc2 0x1e +0x0e 0x80 0xc2 0x1e + +# FP16: scvtf h23, x19, #1 +# FP16: scvtf h31, xzr, #20 +# FP16: scvtf h14, x0, #64 +0x77 0xfe 0xc2 0x9e +0xff 0xb3 0xc2 0x9e +0x0e 0x00 0xc2 0x9e + # CHECK: scvtf s23, w19, #1 # CHECK: scvtf s31, wzr, #20 # CHECK: scvtf s14, w0, #32 @@ -1600,6 +1643,20 @@ 0xff 0xb3 0x42 0x9e 0x0e 0x00 0x42 0x9e +# FP16: ucvtf h23, w19, #1 +# FP16: ucvtf h31, wzr, #20 +# FP16: ucvtf h14, w0, #32 +0x77 0xfe 0xc3 0x1e +0xff 0xb3 0xc3 0x1e +0x0e 0x80 0xc3 0x1e + +# FP16: ucvtf h23, x19, #1 +# FP16: ucvtf h31, xzr, #20 +# FP16: ucvtf h14, x0, #64 +0x77 0xfe 0xc3 0x9e +0xff 0xb3 0xc3 0x9e +0x0e 0x00 0xc3 0x9e + # CHECK: ucvtf s23, w19, #1 # CHECK: ucvtf s31, wzr, #20 # CHECK: ucvtf s14, w0, #32 @@ -1631,6 +1688,61 @@ #------------------------------------------------------------------------------ # Floating-point <-> integer conversion #------------------------------------------------------------------------------ + +# FP16: fcvtns w3, h31 +# FP16: fcvtns xzr, h12 +# FP16: fcvtnu wzr, h12 +# FP16: fcvtnu x0, h0 +0xe3 0x3 0xe0 0x1e +0x9f 0x1 0xe0 0x9e +0x9f 0x1 0xe1 0x1e +0x0 0x0 0xe1 0x9e + +# FP16: fcvtps wzr, h9 +# FP16: fcvtps x12, h20 +# FP16: fcvtpu w30, h23 +# FP16: fcvtpu x29, h3 +0x3f 0x1 0xe8 0x1e +0x8c 0x2 0xe8 0x9e +0xfe 0x2 0xe9 0x1e +0x7d 0x0 0xe9 0x9e + +# FP16: fcvtms w2, h3 +# FP16: fcvtms x4, h5 +# FP16: fcvtmu w6, h7 +# FP16: fcvtmu x8, h9 +0x62 0x0 0xf0 0x1e +0xa4 0x0 0xf0 0x9e +0xe6 0x0 0xf1 0x1e +0x28 0x1 0xf1 0x9e + +# FP16: fcvtzs w10, h11 +# FP16: fcvtzs x12, h13 +# FP16: fcvtzu w14, h15 +# FP16: fcvtzu x15, h16 +0x6a 0x1 0xf8 0x1e +0xac 0x1 0xf8 0x9e +0xee 0x1 0xf9 0x1e +0xf 0x2 0xf9 0x9e + +# FP16: scvtf h17, w18 +# FP16: scvtf h19, x20 +# FP16: ucvtf h21, w22 +# FP16: scvtf h23, x24 +0x51 0x2 0xe2 0x1e +0x93 0x2 0xe2 0x9e +0xd5 0x2 0xe3 0x1e +0x17 0x3 0xe2 0x9e + +# FP16: fcvtas w25, h26 +# FP16: fcvtas x27, h28 +# FP16: fcvtau w29, h30 +# FP16: fcvtau xzr, h0 +0x59 0x3 0xe4 0x1e +0x9b 0x3 0xe4 0x9e +0xdd 0x3 0xe5 0x1e +0x1f 0x0 0xe5 0x9e + # CHECK: fcvtns w3, s31 # CHECK: fcvtns xzr, s12 # CHECK: fcvtnu wzr, s12 Index: llvm/trunk/test/MC/Disassembler/AArch64/fullfp16-neg.txt =================================================================== --- llvm/trunk/test/MC/Disassembler/AArch64/fullfp16-neg.txt +++ llvm/trunk/test/MC/Disassembler/AArch64/fullfp16-neg.txt @@ -0,0 +1,145 @@ +# RUN: not llvm-mc -disassemble -triple=aarch64 -mattr=+neon,-fullfp16 < %s 2>&1 | FileCheck %s +# RUN: not llvm-mc -disassemble -triple=aarch64 -mattr=-neon,-fullfp16 < %s 2>&1 | FileCheck %s + +[0x41,0xc0,0xe0,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0x28,0xe3,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0x18,0xe3,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0x10,0xc3,0x1f] +# CHECK: warning: invalid instruction encoding +[0x41,0x48,0xe3,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0x68,0xe3,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0x58,0xe3,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0x78,0xe3,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0x90,0xc3,0x1f] +# CHECK: warning: invalid instruction encoding +[0x41,0x08,0xe3,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0x40,0xe1,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0x10,0xe3,0x1f] +# CHECK: warning: invalid instruction encoding +[0x41,0x90,0xe3,0x1f] +# CHECK: warning: invalid instruction encoding +[0x41,0x88,0xe3,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0xc0,0xe1,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0x38,0xe3,0x1e] +# CHECK: warning: invalid instruction encoding +[0x20,0x04,0xe2,0x1e] +# CHECK: warning: invalid instruction encoding +[0x30,0x04,0xe2,0x1e] +# CHECK: warning: invalid instruction encoding +[0x20,0x20,0xe2,0x1e] +# CHECK: warning: invalid instruction encoding +[0x28,0x20,0xe0,0x1e] +# CHECK: warning: invalid instruction encoding +[0x30,0x20,0xe2,0x1e] +# CHECK: warning: invalid instruction encoding +[0x38,0x20,0xe0,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0x0c,0xe3,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0x00,0xe4,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0x00,0xe4,0x9e] +# CHECK: warning: invalid instruction encoding +[0x41,0x00,0xe5,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0x00,0xe5,0x9e] +# CHECK: warning: invalid instruction encoding +[0x41,0x00,0xf0,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0x00,0xf0,0x9e] +# CHECK: warning: invalid instruction encoding +[0x41,0x00,0xf1,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0x00,0xf1,0x9e] +# CHECK: warning: invalid instruction encoding +[0x41,0x00,0xe0,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0x00,0xe0,0x9e] +# CHECK: warning: invalid instruction encoding +[0x41,0x00,0xe1,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0x00,0xe1,0x9e] +# CHECK: warning: invalid instruction encoding +[0x41,0x00,0xe8,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0x00,0xe8,0x9e] +# CHECK: warning: invalid instruction encoding +[0x41,0x00,0xe9,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0x00,0xe9,0x9e] +# CHECK: warning: invalid instruction encoding +[0x41,0x00,0xf8,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0xfc,0xd8,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0x00,0xf8,0x9e] +# CHECK: warning: invalid instruction encoding +[0x41,0xfc,0xd8,0x9e] +# CHECK: warning: invalid instruction encoding +[0x41,0x00,0xf9,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0xfc,0xd9,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0x00,0xf9,0x9e] +# CHECK: warning: invalid instruction encoding +[0x41,0xfc,0xd9,0x9e] +# CHECK: warning: invalid instruction encoding +[0x41,0x00,0xe2,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0xfc,0xc2,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0x00,0xe2,0x9e] +# CHECK: warning: invalid instruction encoding +[0x41,0xfc,0xc2,0x9e] +# CHECK: warning: invalid instruction encoding +[0x41,0x00,0xe3,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0xfc,0xc3,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0x00,0xe3,0x9e] +# CHECK: warning: invalid instruction encoding +[0x41,0xfc,0xc3,0x9e] +# CHECK: warning: invalid instruction encoding +[0x41,0x00,0xe7,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0x00,0xe6,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0x00,0xe7,0x9e] +# CHECK: warning: invalid instruction encoding +[0x41,0x00,0xe6,0x9e] +# CHECK: warning: invalid instruction encoding +[0x01,0x10,0xe8,0x1e] +# CHECK: warning: invalid instruction encoding +[0x01,0x10,0xe8,0x1e] +# CHECK: warning: invalid instruction encoding +[0xe2,0x03,0xe7,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0x40,0xe0,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0x40,0xe6,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0xc0,0xe7,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0x40,0xe5,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0x40,0xe4,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0xc0,0xe4,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0x40,0xe7,0x1e] +# CHECK: warning: invalid instruction encoding +[0x41,0xc0,0xe5,0x1e] +# CHECK: warning: invalid instruction encoding + +# CHECK-NOT: warning: invalid instruction encoding