Index: include/llvm/Target/Target.td
===================================================================
--- include/llvm/Target/Target.td
+++ include/llvm/Target/Target.td
@@ -99,7 +99,8 @@
   list<SubRegIndex> SubRegIndices = [];
 
   // RegAltNameIndices - The alternate name indices which are valid for this
-  // register.
+  // register. Their order corresponds to the order of entries in the altNames
+  // list.
   list<RegAltNameIndex> RegAltNameIndices = [];
 
   // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
@@ -149,7 +150,7 @@
 // registers by register allocators.
 //
 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
-                    dag regList, RegAltNameIndex idx = NoRegAltName>
+                    dag regList>
   : DAGOperand {
   string Namespace = namespace;
 
@@ -182,11 +183,6 @@
   //
   dag MemberList = regList;
 
-  // AltNameIndex - The alternate register name to use when printing operands
-  // of this register class. Every register in the register class must have
-  // a valid alternate name for the given index.
-  RegAltNameIndex altNameIndex = idx;
-
   // isAllocatable - Specify that the register class can be used for virtual
   // registers and register allocation.  Some register classes are only used to
   // model instruction operand constraints, and should have isAllocatable = 0.
@@ -936,6 +932,11 @@
   // written register name matcher
   bit ShouldEmitMatchRegisterName = 1;
 
+  // MatchRegisterNameShouldMatchAltNames - set to true if the
+  // MatchRegisterName function should also match register AltNames. It is
+  // hoped this will become the default in the future and the option removed.
+  bit MatchRegisterNameShouldMatchAltNames = 0;
+
   /// Does the instruction mnemonic allow '.'
   bit MnemonicContainsDot = 0;
 }
Index: lib/Target/Hexagon/Hexagon.td
===================================================================
--- lib/Target/Hexagon/Hexagon.td
+++ lib/Target/Hexagon/Hexagon.td
@@ -251,6 +251,10 @@
 // Declare the target which we are implementing
 //===----------------------------------------------------------------------===//
 
+def HexagonAsmParser : AsmParser {
+  let MatchRegisterNameShouldMatchAltNames = 1;
+}
+
 def HexagonAsmParserVariant : AsmParserVariant {
   int Variant = 0;
   string TokenizingCharacters = "#()=:.<>!+*";
@@ -259,5 +263,6 @@
 def Hexagon : Target {
   // Pull in Instruction Info:
   let InstructionSet = HexagonInstrInfo;
+  let AssemblyParsers = [HexagonAsmParser];
   let AssemblyParserVariants = [HexagonAsmParserVariant];
 }
Index: lib/Target/Hexagon/HexagonRegisterInfo.td
===================================================================
--- lib/Target/Hexagon/HexagonRegisterInfo.td
+++ lib/Target/Hexagon/HexagonRegisterInfo.td
@@ -16,6 +16,7 @@
   class HexagonReg<bits<5> num, string n, list<string> alt = [], 
                    list<Register> alias = []> : Register<n> {
     field bits<5> Num;
+    let AltNames = alt;
     let Aliases = alias;
     let HWEncoding{4-0} = num;
   }
@@ -83,14 +84,18 @@
   def subreg_hireg  : SubRegIndex<32, 32>;
   def subreg_overflow : SubRegIndex<1, 0>;
 
+  def regaltname : RegAltNameIndex;
+
   // Integer registers.
   foreach i = 0-28 in {
     def R#i  : Ri<i, "r"#i>,  DwarfRegNum<[i]>;
   }
 
+  let RegAltNameIndices = [regaltname] in {
   def R29 : Ri<29, "r29", ["sp"]>, DwarfRegNum<[29]>;
   def R30 : Ri<30, "r30", ["fp"]>, DwarfRegNum<[30]>;
   def R31 : Ri<31, "r31", ["lr"]>, DwarfRegNum<[31]>;
+  }
 
   // Aliases of the R* registers used to hold 64-bit int values (doubles).
   let SubRegIndices = [subreg_loreg, subreg_hireg], CoveredBySubRegs = 1 in {
Index: lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h
===================================================================
--- lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h
+++ lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h
@@ -33,7 +33,8 @@
   void printInstruction(MCInst const *MI, raw_ostream &O);
 
   StringRef getRegName(unsigned RegNo) const;
-  static char const *getRegisterName(unsigned RegNo);
+  static const char *getRegisterName(unsigned RegNo,
+                                     unsigned AltIdx = Hexagon::NoRegAltName);
   void printRegName(raw_ostream &O, unsigned RegNo) const override;
 
   void printOperand(MCInst const *MI, unsigned OpNo, raw_ostream &O) const;
Index: test/MC/Hexagon/reg_altnames.s
===================================================================
--- /dev/null
+++ test/MC/Hexagon/reg_altnames.s
@@ -0,0 +1,10 @@
+# RUN: llvm-mc -triple hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s
+
+# CHECK: 11 df 75 f1
+r17 = xor(r21, lr)
+
+# CHECK: 1d df 35 f3
+sp = sub(lr, r21)
+
+# CHECK: 15 c0 3e 71
+fp.l = #21
Index: utils/TableGen/AsmMatcherEmitter.cpp
===================================================================
--- utils/TableGen/AsmMatcherEmitter.cpp
+++ utils/TableGen/AsmMatcherEmitter.cpp
@@ -2204,6 +2204,25 @@
 
     Matches.emplace_back(Reg.TheDef->getValueAsString("AsmName"),
                          "return " + utostr(Reg.EnumValue) + ";");
+
+    if (AsmParser->getValueAsBit("MatchRegisterNameShouldMatchAltNames")) {
+      const auto &AltNames = Reg.TheDef->getValueAsListOfStrings("AltNames");
+      const auto &RegAltNameIndices =
+          Reg.TheDef->getValueAsListOfDefs("RegAltNameIndices");
+
+      unsigned AltNameIndex = 0;
+      for (const Record *RegAltNameIndex : RegAltNameIndices) {
+        if (AltNames.size() <= AltNameIndex)
+          PrintFatalError(Reg.TheDef->getLoc(),
+                          "Register definition missing alt name for '" +
+                              RegAltNameIndex->getName() + "'.");
+        const StringRef &AltName = AltNames[AltNameIndex];
+        if (AltName.empty())
+          continue;
+        Matches.emplace_back(AltName, "return " + utostr(Reg.EnumValue) + ";");
+        AltNameIndex++;
+      }
+    }
   }
 
   OS << "static unsigned MatchRegisterName(StringRef Name) {\n";