diff --git a/llvm/test/CodeGen/AArch64/cmp-const-max.ll b/llvm/test/CodeGen/AArch64/cmp-const-max.ll --- a/llvm/test/CodeGen/AArch64/cmp-const-max.ll +++ b/llvm/test/CodeGen/AArch64/cmp-const-max.ll @@ -1,11 +1,19 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 ; RUN: llc -verify-machineinstrs -aarch64-enable-atomic-cfg-tidy=0 < %s -mtriple=aarch64-none-eabihf -fast-isel=false | FileCheck %s define i32 @ule_64_max(i64 %p) { -entry: ; CHECK-LABEL: ule_64_max: -; CHECK: cmn x0, #1 -; CHECK: b.hi [[RET_ZERO:.LBB[0-9]+_[0-9]+]] +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: cmn x0, #1 +; CHECK-NEXT: b.hi .LBB0_2 +; CHECK-NEXT: // %bb.1: // %ret_one +; CHECK-NEXT: mov w0, #1 // =0x1 +; CHECK-NEXT: ret +; CHECK-NEXT: .LBB0_2: // %ret_zero +; CHECK-NEXT: mov w0, wzr +; CHECK-NEXT: ret +entry: %cmp = icmp ule i64 %p, 18446744073709551615 ; 0xffffffffffffffff br i1 %cmp, label %ret_one, label %ret_zero @@ -13,16 +21,21 @@ ret i32 1 ret_zero: -; CHECK: [[RET_ZERO]]: -; CHECK-NEXT: mov w0, wzr ret i32 0 } define i32 @ugt_64_max(i64 %p) { -entry: ; CHECK-LABEL: ugt_64_max: -; CHECK: cmn x0, #1 -; CHECK: b.ls [[RET_ZERO:.LBB[0-9]+_[0-9]+]] +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: cmn x0, #1 +; CHECK-NEXT: b.ls .LBB1_2 +; CHECK-NEXT: // %bb.1: // %ret_one +; CHECK-NEXT: mov w0, #1 // =0x1 +; CHECK-NEXT: ret +; CHECK-NEXT: .LBB1_2: // %ret_zero +; CHECK-NEXT: mov w0, wzr +; CHECK-NEXT: ret +entry: %cmp = icmp ugt i64 %p, 18446744073709551615 ; 0xffffffffffffffff br i1 %cmp, label %ret_one, label %ret_zero @@ -30,7 +43,5 @@ ret i32 1 ret_zero: -; CHECK: [[RET_ZERO]]: -; CHECK-NEXT: mov w0, wzr ret i32 0 } diff --git a/llvm/test/CodeGen/ARM/sub-cmp-peephole.ll b/llvm/test/CodeGen/ARM/sub-cmp-peephole.ll --- a/llvm/test/CodeGen/ARM/sub-cmp-peephole.ll +++ b/llvm/test/CodeGen/ARM/sub-cmp-peephole.ll @@ -1,13 +1,22 @@ -; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s --check-prefix=V7 -; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi | FileCheck %s -check-prefix=V8 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: llc < %s -mtriple=arm-none | FileCheck %s +; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi | FileCheck %s --check-prefixes=V78,V7 +; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi | FileCheck %s -check-prefixes=V78,V8 define i32 @f(i32 %a, i32 %b) nounwind ssp { -entry: ; CHECK-LABEL: f: -; CHECK: subs -; CHECK-NOT: cmp +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: subs r0, r0, r1 +; CHECK-NEXT: movle r0, #0 +; CHECK-NEXT: mov pc, lr +; +; V78-LABEL: f: +; V78: @ %bb.0: @ %entry +; V78-NEXT: subs r0, r0, r1 +; V78-NEXT: movle r0, #0 +; V78-NEXT: bx lr +entry: %cmp = icmp sgt i32 %a, %b %sub = sub nsw i32 %a, %b %sub. = select i1 %cmp, i32 %sub, i32 0 @@ -15,10 +24,18 @@ } define i32 @g(i32 %a, i32 %b) nounwind ssp { -entry: ; CHECK-LABEL: g: -; CHECK: subs -; CHECK-NOT: cmp +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: subs r0, r1, r0 +; CHECK-NEXT: movle r0, #0 +; CHECK-NEXT: mov pc, lr +; +; V78-LABEL: g: +; V78: @ %bb.0: @ %entry +; V78-NEXT: subs r0, r1, r0 +; V78-NEXT: movle r0, #0 +; V78-NEXT: bx lr +entry: %cmp = icmp slt i32 %a, %b %sub = sub nsw i32 %b, %a %sub. = select i1 %cmp, i32 %sub, i32 0 @@ -26,10 +43,18 @@ } define i32 @h(i32 %a, i32 %b) nounwind ssp { -entry: ; CHECK-LABEL: h: -; CHECK: subs -; CHECK-NOT: cmp +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: subs r0, r0, #3 +; CHECK-NEXT: movle r0, r1 +; CHECK-NEXT: mov pc, lr +; +; V78-LABEL: h: +; V78: @ %bb.0: @ %entry +; V78-NEXT: subs r0, r0, #3 +; V78-NEXT: movle r0, r1 +; V78-NEXT: bx lr +entry: %cmp = icmp sgt i32 %a, 3 %sub = sub nsw i32 %a, 3 %sub. = select i1 %cmp, i32 %sub, i32 %b @@ -38,10 +63,18 @@ ; rdar://11725965 define i32 @i(i32 %a, i32 %b) nounwind readnone ssp { -entry: ; CHECK-LABEL: i: -; CHECK: subs -; CHECK-NOT: cmp +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: subs r0, r1, r0 +; CHECK-NEXT: movls r0, #0 +; CHECK-NEXT: mov pc, lr +; +; V78-LABEL: i: +; V78: @ %bb.0: @ %entry +; V78-NEXT: subs r0, r1, r0 +; V78-NEXT: movls r0, #0 +; V78-NEXT: bx lr +entry: %cmp = icmp ult i32 %a, %b %sub = sub i32 %b, %a %sub. = select i1 %cmp, i32 %sub, i32 0 @@ -50,10 +83,23 @@ ; If CPSR is live-out, we can't remove cmp if there exists ; a swapped sub. define i32 @j(i32 %a, i32 %b) nounwind { -entry: ; CHECK-LABEL: j: -; CHECK: sub -; CHECK: cmp +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: mov r2, r0 +; CHECK-NEXT: subs r0, r0, r1 +; CHECK-NEXT: movne pc, lr +; CHECK-NEXT: .LBB4_1: @ %if.then +; CHECK-NEXT: cmp r1, r2 +; CHECK-NEXT: movle r0, r2 +; CHECK-NEXT: mov pc, lr +; +; V78-LABEL: j: +; V78: @ %bb.0: @ %entry +; V78-NEXT: subs r1, r0, r1 +; V78-NEXT: movlt r0, r1 +; V78-NEXT: movne r0, r1 +; V78-NEXT: bx lr +entry: %cmp = icmp eq i32 %b, %a %sub = sub nsw i32 %a, %b br i1 %cmp, label %if.then, label %if.else @@ -70,10 +116,28 @@ ; If the sub/rsb instruction is predicated, we can't use the flags. ; ; Test case from MultiSource/Benchmarks/Ptrdist/bc/number.s -; CHECK: bc_raise -; CHECK: rsbeq -; CHECK: cmp define i32 @bc_raise(i1 %cond) nounwind ssp { +; CHECK-LABEL: bc_raise: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: mov r1, #1 +; CHECK-NEXT: tst r0, #1 +; CHECK-NEXT: bic r1, r1, r0 +; CHECK-NEXT: rsbeq r1, r1, #0 +; CHECK-NEXT: cmp r1, #0 +; CHECK-NEXT: movne r0, #23 +; CHECK-NEXT: moveq r0, #17 +; CHECK-NEXT: mov pc, lr +; +; V78-LABEL: bc_raise: +; V78: @ %bb.0: @ %entry +; V78-NEXT: mov r1, #1 +; V78-NEXT: tst r0, #1 +; V78-NEXT: bic r1, r1, r0 +; V78-NEXT: mov r0, #23 +; V78-NEXT: rsbeq r1, r1, #0 +; V78-NEXT: cmp r1, #0 +; V78-NEXT: movweq r0, #17 +; V78-NEXT: bx lr entry: %val.2.i = select i1 %cond, i32 0, i32 1 %sub.i = sub nsw i32 0, %val.2.i @@ -91,10 +155,22 @@ ; When considering the producer of cmp's src as the subsuming instruction, ; only consider that when the comparison is to 0. define i32 @cmp_src_nonzero(i32 %a, i32 %b, i32 %x, i32 %y) { -entry: ; CHECK-LABEL: cmp_src_nonzero: -; CHECK: sub -; CHECK: cmp +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: sub r0, r0, r1 +; CHECK-NEXT: cmp r0, #17 +; CHECK-NEXT: movne r2, r3 +; CHECK-NEXT: mov r0, r2 +; CHECK-NEXT: mov pc, lr +; +; V78-LABEL: cmp_src_nonzero: +; V78: @ %bb.0: @ %entry +; V78-NEXT: sub r0, r0, r1 +; V78-NEXT: cmp r0, #17 +; V78-NEXT: movne r2, r3 +; V78-NEXT: mov r0, r2 +; V78-NEXT: bx lr +entry: %sub = sub i32 %a, %b %cmp = icmp eq i32 %sub, 17 %ret = select i1 %cmp, i32 %x, i32 %y @@ -102,12 +178,31 @@ } define float @float_sel(i32 %a, i32 %b, float %x, float %y) { -entry: ; CHECK-LABEL: float_sel: -; CHECK-NOT: cmp +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: subs r0, r0, r1 +; CHECK-NEXT: movne r2, r3 +; CHECK-NEXT: mov r0, r2 +; CHECK-NEXT: mov pc, lr +; +; V7-LABEL: float_sel: +; V7: @ %bb.0: @ %entry +; V7-NEXT: vmov s2, r2 +; V7-NEXT: subs r0, r0, r1 +; V7-NEXT: vmov s0, r3 +; V7-NEXT: vmoveq.f32 s0, s2 +; V7-NEXT: vmov r0, s0 +; V7-NEXT: bx lr +; ; V8-LABEL: float_sel: -; V8-NOT: cmp -; V8: vseleq.f32 +; V8: @ %bb.0: @ %entry +; V8-NEXT: vmov s0, r3 +; V8-NEXT: subs r0, r0, r1 +; V8-NEXT: vmov s2, r2 +; V8-NEXT: vseleq.f32 s0, s2, s0 +; V8-NEXT: vmov r0, s0 +; V8-NEXT: bx lr +entry: %sub = sub i32 %a, %b %cmp = icmp eq i32 %sub, 0 %ret = select i1 %cmp, float %x, float %y @@ -115,12 +210,33 @@ } define double @double_sel(i32 %a, i32 %b, double %x, double %y) { -entry: ; CHECK-LABEL: double_sel: -; CHECK-NOT: cmp +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: subs r0, r0, r1 +; CHECK-NEXT: ldr r1, [sp, #4] +; CHECK-NEXT: ldr r0, [sp] +; CHECK-NEXT: moveq r1, r3 +; CHECK-NEXT: moveq r0, r2 +; CHECK-NEXT: mov pc, lr +; +; V7-LABEL: double_sel: +; V7: @ %bb.0: @ %entry +; V7-NEXT: vmov d17, r2, r3 +; V7-NEXT: vldr d16, [sp] +; V7-NEXT: subs r0, r0, r1 +; V7-NEXT: vmoveq.f64 d16, d17 +; V7-NEXT: vmov r0, r1, d16 +; V7-NEXT: bx lr +; ; V8-LABEL: double_sel: -; V8-NOT: cmp -; V8: vseleq.f64 +; V8: @ %bb.0: @ %entry +; V8-NEXT: vldr d16, [sp] +; V8-NEXT: vmov d17, r2, r3 +; V8-NEXT: subs r0, r0, r1 +; V8-NEXT: vseleq.f64 d16, d17, d16 +; V8-NEXT: vmov r0, r1, d16 +; V8-NEXT: bx lr +entry: %sub = sub i32 %a, %b %cmp = icmp eq i32 %sub, 0 %ret = select i1 %cmp, double %x, double %y @@ -129,12 +245,51 @@ @t = common global i32 0 define double @double_sub(i32 %a, i32 %b, double %x, double %y) { -entry: ; CHECK-LABEL: double_sub: -; CHECK: subs -; CHECK-NOT: cmp +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: subs r0, r0, r1 +; CHECK-NEXT: ldr r1, .LCPI9_0 +; CHECK-NEXT: str r0, [r1] +; CHECK-NEXT: ldr r0, [sp] +; CHECK-NEXT: ldr r1, [sp, #4] +; CHECK-NEXT: movgt r0, r2 +; CHECK-NEXT: movgt r1, r3 +; CHECK-NEXT: mov pc, lr +; CHECK-NEXT: .p2align 2 +; CHECK-NEXT: @ %bb.1: +; CHECK-NEXT: .LCPI9_0: +; CHECK-NEXT: .long t +; +; V7-LABEL: double_sub: +; V7: @ %bb.0: @ %entry +; V7-NEXT: vmov d17, r2, r3 +; V7-NEXT: cmp r0, r1 +; V7-NEXT: vldr d16, [sp] +; V7-NEXT: sub r0, r0, r1 +; V7-NEXT: vmovgt.f64 d16, d17 +; V7-NEXT: movw r1, :lower16:t +; V7-NEXT: movt r1, :upper16:t +; V7-NEXT: str r0, [r1] +; V7-NEXT: vmov r2, r3, d16 +; V7-NEXT: mov r0, r2 +; V7-NEXT: mov r1, r3 +; V7-NEXT: bx lr +; ; V8-LABEL: double_sub: -; V8: vsel +; V8: @ %bb.0: @ %entry +; V8-NEXT: vldr d16, [sp] +; V8-NEXT: cmp r0, r1 +; V8-NEXT: vmov d17, r2, r3 +; V8-NEXT: sub r0, r0, r1 +; V8-NEXT: vselgt.f64 d16, d17, d16 +; V8-NEXT: movw r1, :lower16:t +; V8-NEXT: vmov r2, r3, d16 +; V8-NEXT: movt r1, :upper16:t +; V8-NEXT: str r0, [r1] +; V8-NEXT: mov r0, r2 +; V8-NEXT: mov r1, r3 +; V8-NEXT: bx lr +entry: %cmp = icmp sgt i32 %a, %b %sub = sub i32 %a, %b store i32 %sub, ptr @t @@ -143,14 +298,51 @@ } define double @double_sub_swap(i32 %a, i32 %b, double %x, double %y) { -entry: +; CHECK-LABEL: double_sub_swap: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: subs r0, r1, r0 +; CHECK-NEXT: ldr r1, .LCPI10_0 +; CHECK-NEXT: str r0, [r1] +; CHECK-NEXT: ldr r0, [sp] +; CHECK-NEXT: ldr r1, [sp, #4] +; CHECK-NEXT: movlt r0, r2 +; CHECK-NEXT: movlt r1, r3 +; CHECK-NEXT: mov pc, lr +; CHECK-NEXT: .p2align 2 +; CHECK-NEXT: @ %bb.1: +; CHECK-NEXT: .LCPI10_0: +; CHECK-NEXT: .long t +; ; V7-LABEL: double_sub_swap: -; V7-NOT: cmp -; V7: subs +; V7: @ %bb.0: @ %entry +; V7-NEXT: vmov d17, r2, r3 +; V7-NEXT: cmp r1, r0 +; V7-NEXT: vldr d16, [sp] +; V7-NEXT: sub r0, r1, r0 +; V7-NEXT: vmovlt.f64 d16, d17 +; V7-NEXT: movw r1, :lower16:t +; V7-NEXT: movt r1, :upper16:t +; V7-NEXT: str r0, [r1] +; V7-NEXT: vmov r2, r3, d16 +; V7-NEXT: mov r0, r2 +; V7-NEXT: mov r1, r3 +; V7-NEXT: bx lr +; ; V8-LABEL: double_sub_swap: -; V8-NOT: subs -; V8: cmp -; V8: vsel +; V8: @ %bb.0: @ %entry +; V8-NEXT: vldr d16, [sp] +; V8-NEXT: cmp r1, r0 +; V8-NEXT: vmov d17, r2, r3 +; V8-NEXT: sub r0, r1, r0 +; V8-NEXT: vselge.f64 d16, d16, d17 +; V8-NEXT: movw r1, :lower16:t +; V8-NEXT: vmov r2, r3, d16 +; V8-NEXT: movt r1, :upper16:t +; V8-NEXT: str r0, [r1] +; V8-NEXT: mov r0, r2 +; V8-NEXT: mov r1, r3 +; V8-NEXT: bx lr +entry: %cmp = icmp sgt i32 %a, %b %sub = sub i32 %b, %a %ret = select i1 %cmp, double %x, double %y @@ -164,11 +356,40 @@ ; If the comparison uses the V bit (signed overflow/underflow), we can't ; omit the comparison. define i32 @cmp_slt0(i32 %a, i32 %b, i32 %x, i32 %y) { +; CHECK-LABEL: cmp_slt0: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: push {r11, lr} +; CHECK-NEXT: ldr r0, .LCPI11_0 +; CHECK-NEXT: ldr r0, [r0] +; CHECK-NEXT: sub r0, r0, #17 +; CHECK-NEXT: cmn r0, #1 +; CHECK-NEXT: ble .LBB11_2 +; CHECK-NEXT: @ %bb.1: @ %if.else +; CHECK-NEXT: mov r0, #0 +; CHECK-NEXT: bl exit +; CHECK-NEXT: .LBB11_2: @ %if.then +; CHECK-NEXT: bl abort +; CHECK-NEXT: .p2align 2 +; CHECK-NEXT: @ %bb.3: +; CHECK-NEXT: .LCPI11_0: +; CHECK-NEXT: .long t +; +; V78-LABEL: cmp_slt0: +; V78: @ %bb.0: @ %entry +; V78-NEXT: .save {r11, lr} +; V78-NEXT: push {r11, lr} +; V78-NEXT: movw r0, :lower16:t +; V78-NEXT: movt r0, :upper16:t +; V78-NEXT: ldr r0, [r0] +; V78-NEXT: sub r0, r0, #17 +; V78-NEXT: cmn r0, #1 +; V78-NEXT: ble .LBB11_2 +; V78-NEXT: @ %bb.1: @ %if.else +; V78-NEXT: mov r0, #0 +; V78-NEXT: bl exit +; V78-NEXT: .LBB11_2: @ %if.then +; V78-NEXT: bl abort entry: -; CHECK-LABEL: cmp_slt0 -; CHECK: sub -; CHECK: cmn -; CHECK: ble %load = load i32, ptr @t, align 4 %sub = sub i32 %load, 17 %cmp = icmp slt i32 %sub, 0 @@ -186,11 +407,40 @@ ; Same for the C bit. (Note the ult X, 0 is trivially ; false, so the DAG combiner may or may not optimize it). define i32 @cmp_ult0(i32 %a, i32 %b, i32 %x, i32 %y) { +; CHECK-LABEL: cmp_ult0: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: push {r11, lr} +; CHECK-NEXT: ldr r0, .LCPI12_0 +; CHECK-NEXT: ldr r0, [r0] +; CHECK-NEXT: sub r0, r0, #17 +; CHECK-NEXT: cmp r0, #0 +; CHECK-NEXT: bhs .LBB12_2 +; CHECK-NEXT: @ %bb.1: @ %if.then +; CHECK-NEXT: bl abort +; CHECK-NEXT: .LBB12_2: @ %if.else +; CHECK-NEXT: mov r0, #0 +; CHECK-NEXT: bl exit +; CHECK-NEXT: .p2align 2 +; CHECK-NEXT: @ %bb.3: +; CHECK-NEXT: .LCPI12_0: +; CHECK-NEXT: .long t +; +; V78-LABEL: cmp_ult0: +; V78: @ %bb.0: @ %entry +; V78-NEXT: .save {r11, lr} +; V78-NEXT: push {r11, lr} +; V78-NEXT: movw r0, :lower16:t +; V78-NEXT: movt r0, :upper16:t +; V78-NEXT: ldr r0, [r0] +; V78-NEXT: sub r0, r0, #17 +; V78-NEXT: cmp r0, #0 +; V78-NEXT: bhs .LBB12_2 +; V78-NEXT: @ %bb.1: @ %if.then +; V78-NEXT: bl abort +; V78-NEXT: .LBB12_2: @ %if.else +; V78-NEXT: mov r0, #0 +; V78-NEXT: bl exit entry: -; CHECK-LABEL: cmp_ult0 -; CHECK: sub -; CHECK: cmp -; CHECK: bhs %load = load i32, ptr @t, align 4 %sub = sub i32 %load, 17 %cmp = icmp ult i32 %sub, 0 diff --git a/llvm/test/CodeGen/SystemZ/int-cmp-46.ll b/llvm/test/CodeGen/SystemZ/int-cmp-46.ll --- a/llvm/test/CodeGen/SystemZ/int-cmp-46.ll +++ b/llvm/test/CodeGen/SystemZ/int-cmp-46.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 ; Test the use of TEST UNDER MASK for 32-bit operations. ; ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s @@ -7,9 +8,13 @@ ; Check the lowest useful TMLL value. define void @f1(i32 %a) { ; CHECK-LABEL: f1: -; CHECK: tmll %r2, 1 -; CHECK: ber %r14 -; CHECK: br %r14 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: tmll %r2, 1 +; CHECK-NEXT: ber %r14 +; CHECK-NEXT: .LBB0_1: # %store +; CHECK-NEXT: lgrl %r1, g@GOT +; CHECK-NEXT: mvhi 0(%r1), 1 +; CHECK-NEXT: br %r14 entry: %and = and i32 %a, 1 %cmp = icmp eq i32 %and, 0 @@ -26,9 +31,13 @@ ; Check the high end of the TMLL range. define void @f2(i32 %a) { ; CHECK-LABEL: f2: -; CHECK: tmll %r2, 65535 -; CHECK: bner %r14 -; CHECK: br %r14 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: tmll %r2, 65535 +; CHECK-NEXT: bner %r14 +; CHECK-NEXT: .LBB1_1: # %store +; CHECK-NEXT: lgrl %r1, g@GOT +; CHECK-NEXT: mvhi 0(%r1), 1 +; CHECK-NEXT: br %r14 entry: %and = and i32 %a, 65535 %cmp = icmp ne i32 %and, 0 @@ -45,9 +54,13 @@ ; Check the lowest useful TMLH value, which is the next value up. define void @f3(i32 %a) { ; CHECK-LABEL: f3: -; CHECK: tmlh %r2, 1 -; CHECK: bner %r14 -; CHECK: br %r14 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: tmlh %r2, 1 +; CHECK-NEXT: bner %r14 +; CHECK-NEXT: .LBB2_1: # %store +; CHECK-NEXT: lgrl %r1, g@GOT +; CHECK-NEXT: mvhi 0(%r1), 1 +; CHECK-NEXT: br %r14 entry: %and = and i32 %a, 65536 %cmp = icmp ne i32 %and, 0 @@ -64,8 +77,13 @@ ; Check the next value up again, which cannot use TM. define void @f4(i32 %a) { ; CHECK-LABEL: f4: -; CHECK-NOT: {{tm[lh].}} -; CHECK: br %r14 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: nilh %r2, 65534 +; CHECK-NEXT: cibe %r2, 0, 0(%r14) +; CHECK-NEXT: .LBB3_1: # %store +; CHECK-NEXT: lgrl %r1, g@GOT +; CHECK-NEXT: mvhi 0(%r1), 1 +; CHECK-NEXT: br %r14 entry: %and = and i32 %a, 4294901759 %cmp = icmp eq i32 %and, 0 @@ -82,9 +100,13 @@ ; Check the high end of the TMLH range. define void @f5(i32 %a) { ; CHECK-LABEL: f5: -; CHECK: tmlh %r2, 65535 -; CHECK: ber %r14 -; CHECK: br %r14 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: tmlh %r2, 65535 +; CHECK-NEXT: ber %r14 +; CHECK-NEXT: .LBB4_1: # %store +; CHECK-NEXT: lgrl %r1, g@GOT +; CHECK-NEXT: mvhi 0(%r1), 1 +; CHECK-NEXT: br %r14 entry: %and = and i32 %a, 4294901760 %cmp = icmp eq i32 %and, 0 @@ -102,9 +124,13 @@ ; an equality comparison with zero. define void @f6(i32 %a) { ; CHECK-LABEL: f6: -; CHECK: tmll %r2, 240 -; CHECK: ber %r14 -; CHECK: br %r14 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: tmll %r2, 240 +; CHECK-NEXT: ber %r14 +; CHECK-NEXT: .LBB5_1: # %store +; CHECK-NEXT: lgrl %r1, g@GOT +; CHECK-NEXT: mvhi 0(%r1), 1 +; CHECK-NEXT: br %r14 entry: %and = and i32 %a, 240 %cmp = icmp slt i32 %and, 16 @@ -121,9 +147,13 @@ ; ...same again with LE. define void @f7(i32 %a) { ; CHECK-LABEL: f7: -; CHECK: tmll %r2, 240 -; CHECK: ber %r14 -; CHECK: br %r14 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: tmll %r2, 240 +; CHECK-NEXT: ber %r14 +; CHECK-NEXT: .LBB6_1: # %store +; CHECK-NEXT: lgrl %r1, g@GOT +; CHECK-NEXT: mvhi 0(%r1), 1 +; CHECK-NEXT: br %r14 entry: %and = and i32 %a, 240 %cmp = icmp sle i32 %and, 15 @@ -141,9 +171,13 @@ ; an inequality comparison with zero. define void @f8(i32 %a) { ; CHECK-LABEL: f8: -; CHECK: tmll %r2, 240 -; CHECK: bner %r14 -; CHECK: br %r14 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: tmll %r2, 240 +; CHECK-NEXT: bner %r14 +; CHECK-NEXT: .LBB7_1: # %store +; CHECK-NEXT: lgrl %r1, g@GOT +; CHECK-NEXT: mvhi 0(%r1), 1 +; CHECK-NEXT: br %r14 entry: %and = and i32 %a, 240 %cmp = icmp uge i32 %and, 16 @@ -160,9 +194,13 @@ ; ...same again with GT. define void @f9(i32 %a) { ; CHECK-LABEL: f9: -; CHECK: tmll %r2, 240 -; CHECK: bner %r14 -; CHECK: br %r14 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: tmll %r2, 240 +; CHECK-NEXT: bner %r14 +; CHECK-NEXT: .LBB8_1: # %store +; CHECK-NEXT: lgrl %r1, g@GOT +; CHECK-NEXT: mvhi 0(%r1), 1 +; CHECK-NEXT: br %r14 entry: %and = and i32 %a, 240 %cmp = icmp ugt i32 %and, 15 @@ -180,9 +218,13 @@ ; test whether the top bit is clear. define void @f10(i32 %a) { ; CHECK-LABEL: f10: -; CHECK: tmll %r2, 35 -; CHECK: bler %r14 -; CHECK: br %r14 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: tmll %r2, 35 +; CHECK-NEXT: bler %r14 +; CHECK-NEXT: .LBB9_1: # %store +; CHECK-NEXT: lgrl %r1, g@GOT +; CHECK-NEXT: mvhi 0(%r1), 1 +; CHECK-NEXT: br %r14 entry: %and = and i32 %a, 35 %cmp = icmp ult i32 %and, 8 @@ -199,9 +241,13 @@ ; ...same again with LE. define void @f11(i32 %a) { ; CHECK-LABEL: f11: -; CHECK: tmll %r2, 35 -; CHECK: bler %r14 -; CHECK: br %r14 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: tmll %r2, 35 +; CHECK-NEXT: bler %r14 +; CHECK-NEXT: .LBB10_1: # %store +; CHECK-NEXT: lgrl %r1, g@GOT +; CHECK-NEXT: mvhi 0(%r1), 1 +; CHECK-NEXT: br %r14 entry: %and = and i32 %a, 35 %cmp = icmp ule i32 %and, 31 @@ -219,9 +265,13 @@ ; whether the top bit is set. define void @f12(i32 %a) { ; CHECK-LABEL: f12: -; CHECK: tmll %r2, 140 -; CHECK: bnler %r14 -; CHECK: br %r14 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: tmll %r2, 140 +; CHECK-NEXT: bnler %r14 +; CHECK-NEXT: .LBB11_1: # %store +; CHECK-NEXT: lgrl %r1, g@GOT +; CHECK-NEXT: mvhi 0(%r1), 1 +; CHECK-NEXT: br %r14 entry: %and = and i32 %a, 140 %cmp = icmp uge i32 %and, 128 @@ -238,9 +288,13 @@ ; ...same again for GT. define void @f13(i32 %a) { ; CHECK-LABEL: f13: -; CHECK: tmll %r2, 140 -; CHECK: bnler %r14 -; CHECK: br %r14 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: tmll %r2, 140 +; CHECK-NEXT: bnler %r14 +; CHECK-NEXT: .LBB12_1: # %store +; CHECK-NEXT: lgrl %r1, g@GOT +; CHECK-NEXT: mvhi 0(%r1), 1 +; CHECK-NEXT: br %r14 entry: %and = and i32 %a, 140 %cmp = icmp ugt i32 %and, 126 @@ -257,9 +311,13 @@ ; Check that we can use TMLL for equality comparisons with the mask. define void @f14(i32 %a) { ; CHECK-LABEL: f14: -; CHECK: tmll %r2, 101 -; CHECK: bor %r14 -; CHECK: br %r14 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: tmll %r2, 101 +; CHECK-NEXT: bor %r14 +; CHECK-NEXT: .LBB13_1: # %store +; CHECK-NEXT: lgrl %r1, g@GOT +; CHECK-NEXT: mvhi 0(%r1), 1 +; CHECK-NEXT: br %r14 entry: %and = and i32 %a, 101 %cmp = icmp eq i32 %and, 101 @@ -276,9 +334,13 @@ ; Check that we can use TMLL for inequality comparisons with the mask. define void @f15(i32 %a) { ; CHECK-LABEL: f15: -; CHECK: tmll %r2, 65519 -; CHECK: bnor %r14 -; CHECK: br %r14 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: tmll %r2, 65519 +; CHECK-NEXT: bnor %r14 +; CHECK-NEXT: .LBB14_1: # %store +; CHECK-NEXT: lgrl %r1, g@GOT +; CHECK-NEXT: mvhi 0(%r1), 1 +; CHECK-NEXT: br %r14 entry: %and = and i32 %a, 65519 %cmp = icmp ne i32 %and, 65519 @@ -296,9 +358,13 @@ ; to inequality comparisons with the mask. define void @f16(i32 %a) { ; CHECK-LABEL: f16: -; CHECK: tmll %r2, 130 -; CHECK: bnor %r14 -; CHECK: br %r14 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: tmll %r2, 130 +; CHECK-NEXT: bnor %r14 +; CHECK-NEXT: .LBB15_1: # %store +; CHECK-NEXT: lgrl %r1, g@GOT +; CHECK-NEXT: mvhi 0(%r1), 1 +; CHECK-NEXT: br %r14 entry: %and = and i32 %a, 130 %cmp = icmp ult i32 %and, 129 @@ -315,9 +381,13 @@ ; ...same again with LE. define void @f17(i32 %a) { ; CHECK-LABEL: f17: -; CHECK: tmll %r2, 130 -; CHECK: bnor %r14 -; CHECK: br %r14 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: tmll %r2, 130 +; CHECK-NEXT: bnor %r14 +; CHECK-NEXT: .LBB16_1: # %store +; CHECK-NEXT: lgrl %r1, g@GOT +; CHECK-NEXT: mvhi 0(%r1), 1 +; CHECK-NEXT: br %r14 entry: %and = and i32 %a, 130 %cmp = icmp ule i32 %and, 128 @@ -335,9 +405,13 @@ ; to equality comparisons with the mask. define void @f18(i32 %a) { ; CHECK-LABEL: f18: -; CHECK: tmll %r2, 194 -; CHECK: bor %r14 -; CHECK: br %r14 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: tmll %r2, 194 +; CHECK-NEXT: bor %r14 +; CHECK-NEXT: .LBB17_1: # %store +; CHECK-NEXT: lgrl %r1, g@GOT +; CHECK-NEXT: mvhi 0(%r1), 1 +; CHECK-NEXT: br %r14 entry: %and = and i32 %a, 194 %cmp = icmp uge i32 %and, 193 @@ -354,9 +428,13 @@ ; ...same again for GT. define void @f19(i32 %a) { ; CHECK-LABEL: f19: -; CHECK: tmll %r2, 194 -; CHECK: bor %r14 -; CHECK: br %r14 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: tmll %r2, 194 +; CHECK-NEXT: bor %r14 +; CHECK-NEXT: .LBB18_1: # %store +; CHECK-NEXT: lgrl %r1, g@GOT +; CHECK-NEXT: mvhi 0(%r1), 1 +; CHECK-NEXT: br %r14 entry: %and = and i32 %a, 194 %cmp = icmp ugt i32 %and, 192 @@ -374,9 +452,13 @@ ; when the mask has two bits. define void @f20(i32 %a) { ; CHECK-LABEL: f20: -; CHECK: tmll %r2, 20 -; CHECK: blr %r14 -; CHECK: br %r14 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: tmll %r2, 20 +; CHECK-NEXT: blr %r14 +; CHECK-NEXT: .LBB19_1: # %store +; CHECK-NEXT: lgrl %r1, g@GOT +; CHECK-NEXT: mvhi 0(%r1), 1 +; CHECK-NEXT: br %r14 entry: %and = and i32 %a, 20 %cmp = icmp eq i32 %and, 4 @@ -394,9 +476,13 @@ ; when the mask has two bits. define void @f21(i32 %a) { ; CHECK-LABEL: f21: -; CHECK: tmll %r2, 20 -; CHECK: bnlr %r14 -; CHECK: br %r14 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: tmll %r2, 20 +; CHECK-NEXT: bnlr %r14 +; CHECK-NEXT: .LBB20_1: # %store +; CHECK-NEXT: lgrl %r1, g@GOT +; CHECK-NEXT: mvhi 0(%r1), 1 +; CHECK-NEXT: br %r14 entry: %and = and i32 %a, 20 %cmp = icmp ne i32 %and, 4 @@ -414,9 +500,13 @@ ; when the mask has two bits. define void @f22(i32 %a) { ; CHECK-LABEL: f22: -; CHECK: tmll %r2, 20 -; CHECK: bhr %r14 -; CHECK: br %r14 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: tmll %r2, 20 +; CHECK-NEXT: bhr %r14 +; CHECK-NEXT: .LBB21_1: # %store +; CHECK-NEXT: lgrl %r1, g@GOT +; CHECK-NEXT: mvhi 0(%r1), 1 +; CHECK-NEXT: br %r14 entry: %and = and i32 %a, 20 %cmp = icmp eq i32 %and, 16 @@ -434,9 +524,13 @@ ; when the mask has two bits. define void @f23(i32 %a) { ; CHECK-LABEL: f23: -; CHECK: tmll %r2, 20 -; CHECK: bnhr %r14 -; CHECK: br %r14 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: tmll %r2, 20 +; CHECK-NEXT: bnhr %r14 +; CHECK-NEXT: .LBB22_1: # %store +; CHECK-NEXT: lgrl %r1, g@GOT +; CHECK-NEXT: mvhi 0(%r1), 1 +; CHECK-NEXT: br %r14 entry: %and = and i32 %a, 20 %cmp = icmp ne i32 %and, 16 @@ -453,9 +547,13 @@ ; Check that we can fold an SHL into a TMxx mask. define void @f24(i32 %a) { ; CHECK-LABEL: f24: -; CHECK: tmll %r2, 255 -; CHECK: bner %r14 -; CHECK: br %r14 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: tmll %r2, 255 +; CHECK-NEXT: bner %r14 +; CHECK-NEXT: .LBB23_1: # %store +; CHECK-NEXT: lgrl %r1, g@GOT +; CHECK-NEXT: mvhi 0(%r1), 1 +; CHECK-NEXT: br %r14 entry: %shl = shl i32 %a, 12 %and = and i32 %shl, 1044480 @@ -473,9 +571,13 @@ ; Check that we can fold an SHR into a TMxx mask. define void @f25(i32 %a) { ; CHECK-LABEL: f25: -; CHECK: tmlh %r2, 512 -; CHECK: bner %r14 -; CHECK: br %r14 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: tmlh %r2, 512 +; CHECK-NEXT: bner %r14 +; CHECK-NEXT: .LBB24_1: # %store +; CHECK-NEXT: lgrl %r1, g@GOT +; CHECK-NEXT: mvhi 0(%r1), 1 +; CHECK-NEXT: br %r14 entry: %shr = lshr i32 %a, 25 %and = and i32 %shr, 1 diff --git a/llvm/test/CodeGen/X86/2012-08-17-legalizer-crash.ll b/llvm/test/CodeGen/X86/2012-08-17-legalizer-crash.ll --- a/llvm/test/CodeGen/X86/2012-08-17-legalizer-crash.ll +++ b/llvm/test/CodeGen/X86/2012-08-17-legalizer-crash.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 ; RUN: llc < %s | FileCheck %s ; Check that an overly large immediate created by SROA doesn't crash the ; legalizer. @@ -11,6 +12,52 @@ @a = common global ptr null, align 8 define void @fn1() nounwind uwtable ssp { +; CHECK-LABEL: fn1: +; CHECK: ## %bb.0: ## %entry +; CHECK-NEXT: pushq %rbx +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset %rbx, -16 +; CHECK-NEXT: movq _a@GOTPCREL(%rip), %rax +; CHECK-NEXT: movq (%rax), %rax +; CHECK-NEXT: movq 64(%rax), %rcx +; CHECK-NEXT: xorl %edx, %edx +; CHECK-NEXT: movabsq $4294967296, %rsi ## imm = 0x100000000 +; CHECK-NEXT: cmpq %rsi, %rcx +; CHECK-NEXT: movl $0, %esi +; CHECK-NEXT: sbbq %rsi, %rsi +; CHECK-NEXT: movl $0, %esi +; CHECK-NEXT: sbbq %rsi, %rsi +; CHECK-NEXT: movl $0, %esi +; CHECK-NEXT: sbbq %rsi, %rsi +; CHECK-NEXT: movl $0, %esi +; CHECK-NEXT: sbbq %rsi, %rsi +; CHECK-NEXT: movl $0, %esi +; CHECK-NEXT: sbbq %rsi, %rsi +; CHECK-NEXT: movl $0, %esi +; CHECK-NEXT: sbbq %rsi, %rsi +; CHECK-NEXT: sbbq %rdx, %rdx +; CHECK-NEXT: jb LBB0_2 +; CHECK-NEXT: ## %bb.1: ## %if.then +; CHECK-NEXT: movq 56(%rax), %rdx +; CHECK-NEXT: movq 48(%rax), %rsi +; CHECK-NEXT: movq 40(%rax), %rdi +; CHECK-NEXT: movq 32(%rax), %r8 +; CHECK-NEXT: movq 24(%rax), %r9 +; CHECK-NEXT: movq 16(%rax), %r10 +; CHECK-NEXT: movq (%rax), %r11 +; CHECK-NEXT: movq 8(%rax), %rbx +; CHECK-NEXT: movq %r11, (%rax) +; CHECK-NEXT: movq %rbx, 8(%rax) +; CHECK-NEXT: movq %r10, 16(%rax) +; CHECK-NEXT: movq %r9, 24(%rax) +; CHECK-NEXT: movq %r8, 32(%rax) +; CHECK-NEXT: movq %rdi, 40(%rax) +; CHECK-NEXT: movq %rsi, 48(%rax) +; CHECK-NEXT: movq %rdx, 56(%rax) +; CHECK-NEXT: movq %rcx, 64(%rax) +; CHECK-NEXT: LBB0_2: ## %if.end +; CHECK-NEXT: popq %rbx +; CHECK-NEXT: retq entry: %0 = load ptr, ptr @a, align 8 %srcval2 = load i576, ptr %0, align 8 @@ -24,6 +71,4 @@ if.end: ; preds = %if.then, %entry ret void -; CHECK-LABEL: fn1: -; CHECK: jb }