diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -4240,6 +4240,105 @@
       !DAG.doesNodeExist(ISD::SUB, DAG.getVTList(OpVT), {N0, N1}))
     return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
 
+  // Try to constant fold SetCC.
+  if (OpVT.isInteger()) {
+    KnownBits KnownRHS = DAG.computeKnownBits(N1);
+    if (!KnownRHS.isUnknown()) {
+      KnownBits KnownLHS = DAG.computeKnownBits(N0);
+      std::optional<bool> Res;
+      // Check if we can constant fold this with knownbits.
+      switch (Cond) {
+      case ISD::SETEQ:
+        Res = KnownBits::eq(KnownLHS, KnownRHS);
+        break;
+      case ISD::SETNE:
+        Res = KnownBits::ne(KnownLHS, KnownRHS);
+        break;
+      case ISD::SETLT:
+        Res = KnownBits::slt(KnownLHS, KnownRHS);
+        break;
+      case ISD::SETULT:
+        Res = KnownBits::ult(KnownLHS, KnownRHS);
+        break;
+      case ISD::SETGT:
+        Res = KnownBits::sgt(KnownLHS, KnownRHS);
+        break;
+      case ISD::SETUGT:
+        Res = KnownBits::ugt(KnownLHS, KnownRHS);
+        break;
+      case ISD::SETLE:
+        Res = KnownBits::sle(KnownLHS, KnownRHS);
+        break;
+      case ISD::SETULE:
+        Res = KnownBits::ule(KnownLHS, KnownRHS);
+        break;
+      case ISD::SETGE:
+        Res = KnownBits::sge(KnownLHS, KnownRHS);
+        break;
+      case ISD::SETUGE:
+        Res = KnownBits::uge(KnownLHS, KnownRHS);
+        break;
+      default:
+        break;
+      }
+
+      if (Res)
+        return DAG.getBoolConstant(*Res, dl, VT, OpVT);
+
+      // We aren't able to constant fold with known bits but can either 1) make
+      // conditions stronger (i.e ule -> ult) or 2) simplify with
+      // isKnownNeverZero if RHS is zero.
+      switch (Cond) {
+      case ISD::SETLE:
+      case ISD::SETULE:
+      case ISD::SETGE:
+      case ISD::SETUGE:
+        Res = KnownBits::eq(KnownLHS, KnownRHS);
+        [[fallthrough]];
+      case ISD::SETEQ:
+      case ISD::SETNE:
+        // isKnownNeverZero is able to prove cases computeKnownBits can't.
+        if (!Res && KnownRHS.isZero() && DAG.isKnownNeverZero(N0))
+          Res = false;
+        break;
+      default:
+        break;
+      }
+
+      if (Res) {
+        assert(*Res == false &&
+               "There is a bug in KnownBits::{sge,uge,sle,ule}");
+        ISD::CondCode NewCond = Cond;
+        // NB: We could remove this switch and just do `Cond ^ ISD::SETEQ` for
+        // the new opcode.
+        switch (Cond) {
+          // Remove the or eq portion of the condition.
+        case ISD::SETULE:
+          NewCond = ISD::SETULT;
+          break;
+        case ISD::SETLE:
+          NewCond = ISD::SETLT;
+          break;
+        case ISD::SETUGE:
+          NewCond = ISD::SETUGT;
+          break;
+        case ISD::SETGE:
+          NewCond = ISD::SETGT;
+          break;
+          // Evaluate to true/false.
+        case ISD::SETNE:
+          return DAG.getBoolConstant(true, dl, VT, OpVT);
+        case ISD::SETEQ:
+          return DAG.getBoolConstant(false, dl, VT, OpVT);
+        default:
+          break;
+        }
+        if (Cond != NewCond)
+          return DAG.getSetCC(dl, VT, N0, N1, NewCond);
+      }
+    }
+  }
+
   if (SDValue V = foldSetCCWithRotate(VT, N0, N1, Cond, dl, DAG))
     return V;
 
diff --git a/llvm/test/CodeGen/AArch64/aarch64-split-and-bitmask-immediate.ll b/llvm/test/CodeGen/AArch64/aarch64-split-and-bitmask-immediate.ll
--- a/llvm/test/CodeGen/AArch64/aarch64-split-and-bitmask-immediate.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-split-and-bitmask-immediate.ll
@@ -20,10 +20,7 @@
 define i8 @test2(i32 %a) {
 ; CHECK-LABEL: test2:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov w8, #135
-; CHECK-NEXT:    and w8, w0, w8
-; CHECK-NEXT:    cmp w8, #1024
-; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    ret
 entry:
   %and = and i32 %a, 135
@@ -37,7 +34,7 @@
 define i8 @test3(i32 %a) {
 ; CHECK-LABEL: test3:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov w8, #1024
+; CHECK-NEXT:    mov w8, #1024 // =0x400
 ; CHECK-NEXT:    movk w8, #33, lsl #16
 ; CHECK-NEXT:    and w8, w0, w8
 ; CHECK-NEXT:    cmp w8, #1024
@@ -68,10 +65,7 @@
 define i8 @test5(i64 %a) {
 ; CHECK-LABEL: test5:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    and x8, x0, #0x3ffffc000
-; CHECK-NEXT:    and x8, x8, #0xfffffffe00007fff
-; CHECK-NEXT:    cmp x8, #1024
-; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    ret
 entry:
   %and = and i64 %a, 8589950976
@@ -84,10 +78,7 @@
 define i8 @test6(i64 %a) {
 ; CHECK-LABEL: test6:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov w8, #135
-; CHECK-NEXT:    and x8, x0, x8
-; CHECK-NEXT:    cmp x8, #1024
-; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    ret
 entry:
   %and = and i64 %a, 135
@@ -101,7 +92,7 @@
 define i8 @test7(i64 %a) {
 ; CHECK-LABEL: test7:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov w8, #1024
+; CHECK-NEXT:    mov w8, #1024 // =0x400
 ; CHECK-NEXT:    movk w8, #33, lsl #16
 ; CHECK-NEXT:    and x8, x0, x8
 ; CHECK-NEXT:    cmp x8, #1024
@@ -175,7 +166,7 @@
 ; CHECK-NEXT:    cmp w2, #1
 ; CHECK-NEXT:    b.lt .LBB8_3
 ; CHECK-NEXT:  // %bb.1: // %for.body.preheader
-; CHECK-NEXT:    mov w9, #1024
+; CHECK-NEXT:    mov w9, #1024 // =0x400
 ; CHECK-NEXT:    mov w8, w2
 ; CHECK-NEXT:    movk w9, #32, lsl #16
 ; CHECK-NEXT:  .LBB8_2: // %for.body
@@ -226,7 +217,7 @@
 ; CHECK-LABEL: test10:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ldr w8, [x1]
-; CHECK-NEXT:    mov w9, #1024
+; CHECK-NEXT:    mov w9, #1024 // =0x400
 ; CHECK-NEXT:    movk w9, #32, lsl #16
 ; CHECK-NEXT:    and w8, w8, w9
 ; CHECK-NEXT:    str w8, [x0]
@@ -253,10 +244,7 @@
 define i8 @test11(i64 %a) {
 ; CHECK-LABEL: test11:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov w8, #-1610612736
-; CHECK-NEXT:    and x8, x0, x8
-; CHECK-NEXT:    cmp x8, #1024
-; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    ret
 entry:
   %and = and i64 %a, 2684354560
diff --git a/llvm/test/CodeGen/AArch64/andcompare.ll b/llvm/test/CodeGen/AArch64/andcompare.ll
--- a/llvm/test/CodeGen/AArch64/andcompare.ll
+++ b/llvm/test/CodeGen/AArch64/andcompare.ll
@@ -2451,7 +2451,7 @@
 ;
 ; GISEL-LABEL: cmp_to_ands3:
 ; GISEL:       // %bb.0:
-; GISEL-NEXT:    mov w8, #23
+; GISEL-NEXT:    mov w8, #23 // =0x17
 ; GISEL-NEXT:    and w8, w0, w8
 ; GISEL-NEXT:    cmp w8, #7
 ; GISEL-NEXT:    csel w0, w1, wzr, hi
@@ -2466,8 +2466,8 @@
 ; SDISEL-LABEL: cmp_to_ands4:
 ; SDISEL:       // %bb.0:
 ; SDISEL-NEXT:    and w8, w0, #0x30
-; SDISEL-NEXT:    tst w0, #0x20
-; SDISEL-NEXT:    csel w0, w8, w1, eq
+; SDISEL-NEXT:    cmp w8, #31
+; SDISEL-NEXT:    csel w0, w8, w1, lo
 ; SDISEL-NEXT:    ret
 ;
 ; GISEL-LABEL: cmp_to_ands4:
diff --git a/llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll b/llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
--- a/llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
+++ b/llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
@@ -289,7 +289,7 @@
 define i1 @scalar_i32_x_is_const_eq(i32 %y) nounwind {
 ; CHECK-LABEL: scalar_i32_x_is_const_eq:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #43605
+; CHECK-NEXT:    mov w8, #43605 // =0xaa55
 ; CHECK-NEXT:    movk w8, #43605, lsl #16
 ; CHECK-NEXT:    lsl w8, w8, w0
 ; CHECK-NEXT:    tst w8, #0x1
@@ -303,8 +303,8 @@
 define i1 @scalar_i32_x_is_const2_eq(i32 %y) nounwind {
 ; CHECK-LABEL: scalar_i32_x_is_const2_eq:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #1
-; CHECK-NEXT:    mov w9, #43605
+; CHECK-NEXT:    mov w8, #1 // =0x1
+; CHECK-NEXT:    mov w9, #43605 // =0xaa55
 ; CHECK-NEXT:    lsl w8, w8, w0
 ; CHECK-NEXT:    movk w9, #43605, lsl #16
 ; CHECK-NEXT:    tst w8, w9
@@ -319,7 +319,7 @@
 define i1 @scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
 ; CHECK-LABEL: scalar_i8_bitsinmiddle_slt:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #24
+; CHECK-NEXT:    mov w8, #24 // =0x18
 ; CHECK-NEXT:    // kill: def $w1 killed $w1 def $x1
 ; CHECK-NEXT:    lsl w8, w8, w1
 ; CHECK-NEXT:    and w8, w8, w0
@@ -334,13 +334,7 @@
 define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {
 ; CHECK-LABEL: scalar_i8_signbit_eq_with_nonzero:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-128
-; CHECK-NEXT:    // kill: def $w1 killed $w1 def $x1
-; CHECK-NEXT:    lsl w8, w8, w1
-; CHECK-NEXT:    and w8, w8, w0
-; CHECK-NEXT:    and w8, w8, #0x80
-; CHECK-NEXT:    cmp w8, #1
-; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    ret
   %t0 = shl i8 128, %y
   %t1 = and i8 %t0, %x
diff --git a/llvm/test/CodeGen/AArch64/pr59902.ll b/llvm/test/CodeGen/AArch64/pr59902.ll
--- a/llvm/test/CodeGen/AArch64/pr59902.ll
+++ b/llvm/test/CodeGen/AArch64/pr59902.ll
@@ -6,13 +6,7 @@
 define i1 @test() {
 ; CHECK-LABEL: test:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #9007199254740990
-; CHECK-NEXT:    movk x8, #65503, lsl #16
-; CHECK-NEXT:    movk x8, #65407, lsl #32
-; CHECK-NEXT:    cmp x8, x8
-; CHECK-NEXT:    csel x9, x8, x8, gt
-; CHECK-NEXT:    cmp x9, x8
-; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    mov w0, #1 // =0x1
 ; CHECK-NEXT:    ret
   %1 = select i1 false, i64 0, i64 9006649496829950
   %2 = call i64 @llvm.smax.i64(i64 %1, i64 9006649496829950)
diff --git a/llvm/test/CodeGen/AArch64/urem-seteq-vec-tautological.ll b/llvm/test/CodeGen/AArch64/urem-seteq-vec-tautological.ll
--- a/llvm/test/CodeGen/AArch64/urem-seteq-vec-tautological.ll
+++ b/llvm/test/CodeGen/AArch64/urem-seteq-vec-tautological.ll
@@ -20,7 +20,7 @@
 define <4 x i1> @t1_all_odd_eq(<4 x i32> %X) nounwind {
 ; CHECK-LABEL: t1_all_odd_eq:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #43691
+; CHECK-NEXT:    mov w8, #43691 // =0xaaab
 ; CHECK-NEXT:    movk w8, #43690, lsl #16
 ; CHECK-NEXT:    dup v1.4s, w8
 ; CHECK-NEXT:    adrp x8, .LCPI1_0
@@ -39,7 +39,7 @@
 define <4 x i1> @t1_all_odd_ne(<4 x i32> %X) nounwind {
 ; CHECK-LABEL: t1_all_odd_ne:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #43691
+; CHECK-NEXT:    mov w8, #43691 // =0xaaab
 ; CHECK-NEXT:    movk w8, #43690, lsl #16
 ; CHECK-NEXT:    dup v1.4s, w8
 ; CHECK-NEXT:    adrp x8, .LCPI2_0
@@ -58,7 +58,7 @@
 define <8 x i1> @t2_narrow(<8 x i16> %X) nounwind {
 ; CHECK-LABEL: t2_narrow:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #43691
+; CHECK-NEXT:    mov w8, #43691 // =0xaaab
 ; CHECK-NEXT:    dup v1.8h, w8
 ; CHECK-NEXT:    adrp x8, .LCPI3_0
 ; CHECK-NEXT:    mul v0.8h, v0.8h, v1.8h
@@ -76,7 +76,7 @@
 define <2 x i1> @t3_wide(<2 x i64> %X) nounwind {
 ; CHECK-LABEL: t3_wide:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #-6148914691236517206
+; CHECK-NEXT:    mov x8, #-6148914691236517206 // =0xaaaaaaaaaaaaaaaa
 ; CHECK-NEXT:    fmov x9, d0
 ; CHECK-NEXT:    movk x8, #43691
 ; CHECK-NEXT:    mov x10, v0.d[1]
diff --git a/llvm/test/CodeGen/ARM/bfi.ll b/llvm/test/CodeGen/ARM/bfi.ll
--- a/llvm/test/CodeGen/ARM/bfi.ll
+++ b/llvm/test/CodeGen/ARM/bfi.ll
@@ -204,10 +204,9 @@
 define i32 @f13(i32 %x, i32 %y) {
 ; CHECK-LABEL: f13:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    and r2, r0, #4
-; CHECK-NEXT:    bic r0, r1, #255
-; CHECK-NEXT:    cmp r2, #42
-; CHECK-NEXT:    orrne r0, r0, #16
+; CHECK-NEXT:    mov r0, r1
+; CHECK-NEXT:    mov r1, #16
+; CHECK-NEXT:    bfi r0, r1, #0, #8
 ; CHECK-NEXT:    bx lr
   %y2 = and i32 %y, 4294967040 ; 0xFFFFFF00
   %and = and i32 %x, 4
diff --git a/llvm/test/CodeGen/ARM/cmp-peephole.ll b/llvm/test/CodeGen/ARM/cmp-peephole.ll
--- a/llvm/test/CodeGen/ARM/cmp-peephole.ll
+++ b/llvm/test/CodeGen/ARM/cmp-peephole.ll
@@ -137,23 +137,17 @@
 define i1 @cmp_ne_zero_or_ri(i32 %a) {
 ; ARM-LABEL: cmp_ne_zero_or_ri:
 ; ARM:       @ %bb.0:
-; ARM-NEXT:    orrs r0, r0, #42
-; ARM-NEXT:    movwne r0, #1
+; ARM-NEXT:    mov r0, #1
 ; ARM-NEXT:    bx lr
 ;
 ; THUMB-LABEL: cmp_ne_zero_or_ri:
 ; THUMB:       @ %bb.0:
-; THUMB-NEXT:    movs r1, #42
-; THUMB-NEXT:    orrs r0, r1
-; THUMB-NEXT:    subs r1, r0, #1
-; THUMB-NEXT:    sbcs r0, r1
+; THUMB-NEXT:    movs r0, #1
 ; THUMB-NEXT:    bx lr
 ;
 ; THUMB2-LABEL: cmp_ne_zero_or_ri:
 ; THUMB2:       @ %bb.0:
-; THUMB2-NEXT:    orrs r0, r0, #42
-; THUMB2-NEXT:    it ne
-; THUMB2-NEXT:    movne r0, #1
+; THUMB2-NEXT:    movs r0, #1
 ; THUMB2-NEXT:    bx lr
   %or = or i32 %a, 42
   %res = icmp ne i32 %or, 0
@@ -726,10 +720,7 @@
 ;
 ; THUMB-LABEL: cmp_eq_zero_or_ri:
 ; THUMB:       @ %bb.0:
-; THUMB-NEXT:    movs r1, #42
-; THUMB-NEXT:    orrs r0, r1
-; THUMB-NEXT:    rsbs r1, r0, #0
-; THUMB-NEXT:    adcs r0, r1
+; THUMB-NEXT:    movs r0, #0
 ; THUMB-NEXT:    bx lr
 ;
 ; THUMB2-LABEL: cmp_eq_zero_or_ri:
diff --git a/llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll b/llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
--- a/llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
+++ b/llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
@@ -966,48 +966,15 @@
 ;------------------------------------------------------------------------------;
 
 define i1 @negative_scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
-; ARM6-LABEL: negative_scalar_i8_bitsinmiddle_slt:
-; ARM6:       @ %bb.0:
-; ARM6-NEXT:    uxtb r1, r1
-; ARM6-NEXT:    mov r2, #24
-; ARM6-NEXT:    ands r0, r0, r2, lsr r1
-; ARM6-NEXT:    mov r0, #0
-; ARM6-NEXT:    movmi r0, #1
-; ARM6-NEXT:    bx lr
-;
-; ARM78-LABEL: negative_scalar_i8_bitsinmiddle_slt:
-; ARM78:       @ %bb.0:
-; ARM78-NEXT:    uxtb r1, r1
-; ARM78-NEXT:    mov r2, #24
-; ARM78-NEXT:    ands r0, r0, r2, lsr r1
-; ARM78-NEXT:    mov r0, #0
-; ARM78-NEXT:    movwmi r0, #1
-; ARM78-NEXT:    bx lr
-;
-; THUMB6-LABEL: negative_scalar_i8_bitsinmiddle_slt:
-; THUMB6:       @ %bb.0:
-; THUMB6-NEXT:    uxtb r1, r1
-; THUMB6-NEXT:    movs r2, #24
-; THUMB6-NEXT:    lsrs r2, r1
-; THUMB6-NEXT:    ands r2, r0
-; THUMB6-NEXT:    bmi .LBB20_2
-; THUMB6-NEXT:  @ %bb.1:
-; THUMB6-NEXT:    movs r0, #0
-; THUMB6-NEXT:    bx lr
-; THUMB6-NEXT:  .LBB20_2:
-; THUMB6-NEXT:    movs r0, #1
-; THUMB6-NEXT:    bx lr
+; ARM-LABEL: negative_scalar_i8_bitsinmiddle_slt:
+; ARM:       @ %bb.0:
+; ARM-NEXT:    mov r0, #0
+; ARM-NEXT:    bx lr
 ;
-; THUMB78-LABEL: negative_scalar_i8_bitsinmiddle_slt:
-; THUMB78:       @ %bb.0:
-; THUMB78-NEXT:    uxtb r1, r1
-; THUMB78-NEXT:    movs r2, #24
-; THUMB78-NEXT:    lsr.w r1, r2, r1
-; THUMB78-NEXT:    ands r0, r1
-; THUMB78-NEXT:    mov.w r0, #0
-; THUMB78-NEXT:    it mi
-; THUMB78-NEXT:    movmi r0, #1
-; THUMB78-NEXT:    bx lr
+; THUMB-LABEL: negative_scalar_i8_bitsinmiddle_slt:
+; THUMB:       @ %bb.0:
+; THUMB-NEXT:    movs r0, #0
+; THUMB-NEXT:    bx lr
   %t0 = lshr i8 24, %y
   %t1 = and i8 %t0, %x
   %res = icmp slt i8 %t1, 0
diff --git a/llvm/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll b/llvm/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
--- a/llvm/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
+++ b/llvm/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
@@ -1067,23 +1067,10 @@
 ; ARM-NEXT:    mov r0, #0
 ; ARM-NEXT:    bx lr
 ;
-; THUMB6-LABEL: scalar_i8_signbit_eq_with_nonzero:
-; THUMB6:       @ %bb.0:
-; THUMB6-NEXT:    uxtb r1, r1
-; THUMB6-NEXT:    movs r2, #127
-; THUMB6-NEXT:    mvns r2, r2
-; THUMB6-NEXT:    lsls r2, r1
-; THUMB6-NEXT:    ands r2, r0
-; THUMB6-NEXT:    uxtb r0, r2
-; THUMB6-NEXT:    subs r1, r0, #1
-; THUMB6-NEXT:    rsbs r0, r1, #0
-; THUMB6-NEXT:    adcs r0, r1
-; THUMB6-NEXT:    bx lr
-;
-; THUMB78-LABEL: scalar_i8_signbit_eq_with_nonzero:
-; THUMB78:       @ %bb.0:
-; THUMB78-NEXT:    movs r0, #0
-; THUMB78-NEXT:    bx lr
+; THUMB-LABEL: scalar_i8_signbit_eq_with_nonzero:
+; THUMB:       @ %bb.0:
+; THUMB-NEXT:    movs r0, #0
+; THUMB-NEXT:    bx lr
   %t0 = shl i8 128, %y
   %t1 = and i8 %t0, %x
   %res = icmp eq i8 %t1, 1 ; should be comparing with 0
diff --git a/llvm/test/CodeGen/Hexagon/vect/zext-v4i1.ll b/llvm/test/CodeGen/Hexagon/vect/zext-v4i1.ll
--- a/llvm/test/CodeGen/Hexagon/vect/zext-v4i1.ll
+++ b/llvm/test/CodeGen/Hexagon/vect/zext-v4i1.ll
@@ -10,35 +10,10 @@
 ; CHECK-LABEL: fred:
 ; CHECK:       // %bb.0: // %b0
 ; CHECK-NEXT:    {
-; CHECK-NEXT:     if (p0) jump:nt .LBB0_2
-; CHECK-NEXT:    }
-; CHECK-NEXT:  // %bb.1: // %b2
-; CHECK-NEXT:    {
-; CHECK-NEXT:     r3:2 = combine(#0,#0)
-; CHECK-NEXT:     r1:0 = memd(r0+#0)
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
-; CHECK-NEXT:     p0 = vcmph.eq(r1:0,r3:2)
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
-; CHECK-NEXT:     r1:0 = mask(p0)
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
-; CHECK-NEXT:     r0 = and(r0,#1)
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
-; CHECK-NEXT:     p0 = cmp.eq(r0,#11)
-; CHECK-NEXT:     r0 = #1
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
+; CHECK-NEXT:     if (!p0) r0 = #1
 ; CHECK-NEXT:     if (p0) r0 = #0
 ; CHECK-NEXT:     jumpr r31
 ; CHECK-NEXT:    }
-; CHECK-NEXT:  .LBB0_2: // %b14
-; CHECK-NEXT:    {
-; CHECK-NEXT:     r0 = #0
-; CHECK-NEXT:     jumpr r31
-; CHECK-NEXT:    }
 b0:
   switch i32 undef, label %b14 [
     i32 5, label %b2
diff --git a/llvm/test/CodeGen/RISCV/sextw-removal.ll b/llvm/test/CodeGen/RISCV/sextw-removal.ll
--- a/llvm/test/CodeGen/RISCV/sextw-removal.ll
+++ b/llvm/test/CodeGen/RISCV/sextw-removal.ll
@@ -409,14 +409,17 @@
 ; CHECK:       # %bb.0: # %bb
 ; CHECK-NEXT:    addi sp, sp, -16
 ; CHECK-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    sraw a0, a0, a1
+; CHECK-NEXT:    li s0, 1
 ; CHECK-NEXT:  .LBB7_1: # %bb2
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    call foo@plt
 ; CHECK-NEXT:    ori a0, a0, -256
-; CHECK-NEXT:    bnez a0, .LBB7_1
+; CHECK-NEXT:    bnez s0, .LBB7_1
 ; CHECK-NEXT:  # %bb.2: # %bb7
 ; CHECK-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
 ;
@@ -424,15 +427,18 @@
 ; NOREMOVAL:       # %bb.0: # %bb
 ; NOREMOVAL-NEXT:    addi sp, sp, -16
 ; NOREMOVAL-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; NOREMOVAL-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
 ; NOREMOVAL-NEXT:    sraw a0, a0, a1
+; NOREMOVAL-NEXT:    li s0, 1
 ; NOREMOVAL-NEXT:  .LBB7_1: # %bb2
 ; NOREMOVAL-NEXT:    # =>This Inner Loop Header: Depth=1
 ; NOREMOVAL-NEXT:    sext.w a0, a0
 ; NOREMOVAL-NEXT:    call foo@plt
 ; NOREMOVAL-NEXT:    ori a0, a0, -256
-; NOREMOVAL-NEXT:    bnez a0, .LBB7_1
+; NOREMOVAL-NEXT:    bnez s0, .LBB7_1
 ; NOREMOVAL-NEXT:  # %bb.2: # %bb7
 ; NOREMOVAL-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; NOREMOVAL-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
 ; NOREMOVAL-NEXT:    addi sp, sp, 16
 ; NOREMOVAL-NEXT:    ret
 bb:
diff --git a/llvm/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll b/llvm/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll
--- a/llvm/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll
+++ b/llvm/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll
@@ -4,25 +4,18 @@
 define signext i16 @f(ptr %bp, ptr %ss)   {
 ; CHECK-LABEL: f:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    pushl %esi
-; CHECK-NEXT:    .cfi_def_cfa_offset 8
-; CHECK-NEXT:    .cfi_offset %esi, -8
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT:    movb $1, %cl
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  .LBB0_1: # %cond_next127
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    movl (%eax), %edx
-; CHECK-NEXT:    movl (%ecx), %esi
 ; CHECK-NEXT:    andl $15, %edx
-; CHECK-NEXT:    andl $15, %esi
-; CHECK-NEXT:    addl %esi, (%ecx)
-; CHECK-NEXT:    cmpl $63, %edx
-; CHECK-NEXT:    jb .LBB0_1
+; CHECK-NEXT:    addl %edx, (%eax)
+; CHECK-NEXT:    testb %cl, %cl
+; CHECK-NEXT:    jne .LBB0_1
 ; CHECK-NEXT:  # %bb.2: # %UnifiedReturnBlock
 ; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    popl %esi
-; CHECK-NEXT:    .cfi_def_cfa_offset 4
 ; CHECK-NEXT:    retl
 entry:
 	br label %cond_next127
diff --git a/llvm/test/CodeGen/X86/avx512-mask-op.ll b/llvm/test/CodeGen/X86/avx512-mask-op.ll
--- a/llvm/test/CodeGen/X86/avx512-mask-op.ll
+++ b/llvm/test/CodeGen/X86/avx512-mask-op.ll
@@ -609,49 +609,16 @@
 }
 
 define void @test7(<8 x i1> %mask)  {
-; KNL-LABEL: test7:
-; KNL:       ## %bb.0: ## %allocas
-; KNL-NEXT:    vpmovsxwq %xmm0, %zmm0
-; KNL-NEXT:    vpsllq $63, %zmm0, %zmm0
-; KNL-NEXT:    vptestmq %zmm0, %zmm0, %k0
-; KNL-NEXT:    kmovw %k0, %eax
-; KNL-NEXT:    orb $85, %al
-; KNL-NEXT:    vzeroupper
-; KNL-NEXT:    retq
-;
-; SKX-LABEL: test7:
-; SKX:       ## %bb.0: ## %allocas
-; SKX-NEXT:    vpsllw $15, %xmm0, %xmm0
-; SKX-NEXT:    vpmovw2m %xmm0, %k0
-; SKX-NEXT:    kmovd %k0, %eax
-; SKX-NEXT:    orb $85, %al
-; SKX-NEXT:    retq
-;
-; AVX512BW-LABEL: test7:
-; AVX512BW:       ## %bb.0: ## %allocas
-; AVX512BW-NEXT:    vpsllw $15, %xmm0, %xmm0
-; AVX512BW-NEXT:    vpmovw2m %zmm0, %k0
-; AVX512BW-NEXT:    kmovd %k0, %eax
-; AVX512BW-NEXT:    orb $85, %al
-; AVX512BW-NEXT:    vzeroupper
-; AVX512BW-NEXT:    retq
-;
-; AVX512DQ-LABEL: test7:
-; AVX512DQ:       ## %bb.0: ## %allocas
-; AVX512DQ-NEXT:    vpmovsxwq %xmm0, %zmm0
-; AVX512DQ-NEXT:    vpsllq $63, %zmm0, %zmm0
-; AVX512DQ-NEXT:    vpmovq2m %zmm0, %k0
-; AVX512DQ-NEXT:    kmovw %k0, %eax
-; AVX512DQ-NEXT:    orb $85, %al
-; AVX512DQ-NEXT:    vzeroupper
-; AVX512DQ-NEXT:    retq
+; CHECK-LABEL: test7:
+; CHECK:       ## %bb.0: ## %allocas
+; CHECK-NEXT:    movb $1, %al
+; CHECK-NEXT:    testb %al, %al
+; CHECK-NEXT:    retq
 ;
 ; X86-LABEL: test7:
 ; X86:       ## %bb.0: ## %allocas
-; X86-NEXT:    vpsllw $15, %xmm0, %xmm0
-; X86-NEXT:    vpmovw2m %xmm0, %k0
-; X86-NEXT:    kmovd %k0, %eax
-; X86-NEXT:    orb $85, %al
+; X86-NEXT:    movb $1, %al
+; X86-NEXT:    testb %al, %al
 ; X86-NEXT:    retl
 allocas:
   %a= or <8 x i1> %mask, <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false>
diff --git a/llvm/test/CodeGen/X86/cmp.ll b/llvm/test/CodeGen/X86/cmp.ll
--- a/llvm/test/CodeGen/X86/cmp.ll
+++ b/llvm/test/CodeGen/X86/cmp.ll
@@ -280,9 +280,7 @@
 define i32 @test14(i32 %mask, i32 %base, i32 %intra) {
 ; CHECK-LABEL: test14:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movl %esi, %eax # encoding: [0x89,0xf0]
-; CHECK-NEXT:    shrl $7, %edi # encoding: [0xc1,0xef,0x07]
-; CHECK-NEXT:    cmovnsl %edx, %eax # encoding: [0x0f,0x49,0xc2]
+; CHECK-NEXT:    movl %edx, %eax # encoding: [0x89,0xd0]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
   %s = lshr i32 %mask, 7
   %tobool = icmp sgt i32 %s, -1
diff --git a/llvm/test/CodeGen/X86/fold-rmw-ops.ll b/llvm/test/CodeGen/X86/fold-rmw-ops.ll
--- a/llvm/test/CodeGen/X86/fold-rmw-ops.ll
+++ b/llvm/test/CodeGen/X86/fold-rmw-ops.ll
@@ -1352,9 +1352,11 @@
 define void @or64_imm32_br() nounwind {
 ; CHECK-LABEL: or64_imm32_br:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    orq $16777215, g64(%rip) # encoding: [0x48,0x81,0x0d,A,A,A,A,0xff,0xff,0xff,0x00]
-; CHECK-NEXT:    # fixup A - offset: 3, value: g64-8, kind: reloc_riprel_4byte
+; CHECK-NEXT:    orl $16777215, g64(%rip) # encoding: [0x81,0x0d,A,A,A,A,0xff,0xff,0xff,0x00]
+; CHECK-NEXT:    # fixup A - offset: 2, value: g64-8, kind: reloc_riprel_4byte
 ; CHECK-NEXT:    # imm = 0xFFFFFF
+; CHECK-NEXT:    movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT:    testb %al, %al # encoding: [0x84,0xc0]
 ; CHECK-NEXT:    jne b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
@@ -1385,6 +1387,8 @@
 ; CHECK-NEXT:    orq $-2147483648, g64(%rip) # encoding: [0x48,0x81,0x0d,A,A,A,A,0x00,0x00,0x00,0x80]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-8, kind: reloc_riprel_4byte
 ; CHECK-NEXT:    # imm = 0x80000000
+; CHECK-NEXT:    movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT:    testb %al, %al # encoding: [0x84,0xc0]
 ; CHECK-NEXT:    jne b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
@@ -1412,8 +1416,10 @@
 define void @or64_imm8_br() nounwind {
 ; CHECK-LABEL: or64_imm8_br:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    orq $15, g64(%rip) # encoding: [0x48,0x83,0x0d,A,A,A,A,0x0f]
-; CHECK-NEXT:    # fixup A - offset: 3, value: g64-5, kind: reloc_riprel_4byte
+; CHECK-NEXT:    orb $15, g64(%rip) # encoding: [0x80,0x0d,A,A,A,A,0x0f]
+; CHECK-NEXT:    # fixup A - offset: 2, value: g64-5, kind: reloc_riprel_4byte
+; CHECK-NEXT:    movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT:    testb %al, %al # encoding: [0x84,0xc0]
 ; CHECK-NEXT:    jne b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
@@ -1442,6 +1448,8 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    orq $-4, g64(%rip) # encoding: [0x48,0x83,0x0d,A,A,A,A,0xfc]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-5, kind: reloc_riprel_4byte
+; CHECK-NEXT:    movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT:    testb %al, %al # encoding: [0x84,0xc0]
 ; CHECK-NEXT:    jne b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
@@ -1468,9 +1476,10 @@
 define void @or32_imm_br() nounwind {
 ; CHECK-LABEL: or32_imm_br:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    orl $-2147483648, g32(%rip) # encoding: [0x81,0x0d,A,A,A,A,0x00,0x00,0x00,0x80]
-; CHECK-NEXT:    # fixup A - offset: 2, value: g32-8, kind: reloc_riprel_4byte
-; CHECK-NEXT:    # imm = 0x80000000
+; CHECK-NEXT:    orb $-128, g32+3(%rip) # encoding: [0x80,0x0d,A,A,A,A,0x80]
+; CHECK-NEXT:    # fixup A - offset: 2, value: (g32+3)-5, kind: reloc_riprel_4byte
+; CHECK-NEXT:    movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT:    testb %al, %al # encoding: [0x84,0xc0]
 ; CHECK-NEXT:    jne b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
@@ -1498,8 +1507,10 @@
 define void @or32_imm8_br() nounwind {
 ; CHECK-LABEL: or32_imm8_br:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    orl $15, g32(%rip) # encoding: [0x83,0x0d,A,A,A,A,0x0f]
+; CHECK-NEXT:    orb $15, g32(%rip) # encoding: [0x80,0x0d,A,A,A,A,0x0f]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g32-5, kind: reloc_riprel_4byte
+; CHECK-NEXT:    movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT:    testb %al, %al # encoding: [0x84,0xc0]
 ; CHECK-NEXT:    jne b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
@@ -1528,6 +1539,8 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    orl $-4, g32(%rip) # encoding: [0x83,0x0d,A,A,A,A,0xfc]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g32-5, kind: reloc_riprel_4byte
+; CHECK-NEXT:    movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT:    testb %al, %al # encoding: [0x84,0xc0]
 ; CHECK-NEXT:    jne b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
@@ -1554,9 +1567,10 @@
 define void @or16_imm_br() nounwind {
 ; CHECK-LABEL: or16_imm_br:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    orw $-32768, g16(%rip) # encoding: [0x66,0x81,0x0d,A,A,A,A,0x00,0x80]
-; CHECK-NEXT:    # fixup A - offset: 3, value: g16-6, kind: reloc_riprel_4byte
-; CHECK-NEXT:    # imm = 0x8000
+; CHECK-NEXT:    orb $-128, g16+1(%rip) # encoding: [0x80,0x0d,A,A,A,A,0x80]
+; CHECK-NEXT:    # fixup A - offset: 2, value: (g16+1)-5, kind: reloc_riprel_4byte
+; CHECK-NEXT:    movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT:    testb %al, %al # encoding: [0x84,0xc0]
 ; CHECK-NEXT:    jne b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
@@ -1583,8 +1597,10 @@
 define void @or16_imm8_br() nounwind {
 ; CHECK-LABEL: or16_imm8_br:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    orw $15, g16(%rip) # encoding: [0x66,0x83,0x0d,A,A,A,A,0x0f]
-; CHECK-NEXT:    # fixup A - offset: 3, value: g16-5, kind: reloc_riprel_4byte
+; CHECK-NEXT:    orb $15, g16(%rip) # encoding: [0x80,0x0d,A,A,A,A,0x0f]
+; CHECK-NEXT:    # fixup A - offset: 2, value: g16-5, kind: reloc_riprel_4byte
+; CHECK-NEXT:    movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT:    testb %al, %al # encoding: [0x84,0xc0]
 ; CHECK-NEXT:    jne b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
@@ -1613,6 +1629,8 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    orw $-4, g16(%rip) # encoding: [0x66,0x83,0x0d,A,A,A,A,0xfc]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g16-5, kind: reloc_riprel_4byte
+; CHECK-NEXT:    movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT:    testb %al, %al # encoding: [0x84,0xc0]
 ; CHECK-NEXT:    jne b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
@@ -1641,6 +1659,8 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    orb $-4, g8(%rip) # encoding: [0x80,0x0d,A,A,A,A,0xfc]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g8-5, kind: reloc_riprel_4byte
+; CHECK-NEXT:    movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT:    testb %al, %al # encoding: [0x84,0xc0]
 ; CHECK-NEXT:    jne b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
diff --git a/llvm/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll b/llvm/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
--- a/llvm/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
+++ b/llvm/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
@@ -792,23 +792,12 @@
 define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {
 ; X86-LABEL: scalar_i8_signbit_eq_with_nonzero:
 ; X86:       # %bb.0:
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT:    movb $-128, %al
-; X86-NEXT:    shlb %cl, %al
-; X86-NEXT:    andb {{[0-9]+}}(%esp), %al
-; X86-NEXT:    cmpb $1, %al
-; X86-NEXT:    sete %al
+; X86-NEXT:    xorl %eax, %eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: scalar_i8_signbit_eq_with_nonzero:
 ; X64:       # %bb.0:
-; X64-NEXT:    movl %esi, %ecx
-; X64-NEXT:    movb $-128, %al
-; X64-NEXT:    # kill: def $cl killed $cl killed $ecx
-; X64-NEXT:    shlb %cl, %al
-; X64-NEXT:    andb %dil, %al
-; X64-NEXT:    cmpb $1, %al
-; X64-NEXT:    sete %al
+; X64-NEXT:    xorl %eax, %eax
 ; X64-NEXT:    retq
   %t0 = shl i8 128, %y
   %t1 = and i8 %t0, %x
diff --git a/llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll b/llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll
--- a/llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll
+++ b/llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll
@@ -64,7 +64,7 @@
 ; CHECK-NEXT:    # kill: def $cl killed $cl killed $ecx
 ; CHECK-NEXT:    shll %cl, %edi
 ; CHECK-NEXT:    imull $-1431655765, %edi, %eax # imm = 0xAAAAAAAB
-; CHECK-NEXT:    cmpl $1431655766, %eax # imm = 0x55555556
+; CHECK-NEXT:    cmpl $1431655765, %eax # imm = 0x55555555
 ; CHECK-NEXT:    setb %al
 ; CHECK-NEXT:    retq
   %t0 = and i32 %x, 2 ; clearly a power-of-two or zero
diff --git a/llvm/test/CodeGen/X86/or-with-overflow.ll b/llvm/test/CodeGen/X86/or-with-overflow.ll
--- a/llvm/test/CodeGen/X86/or-with-overflow.ll
+++ b/llvm/test/CodeGen/X86/or-with-overflow.ll
@@ -10,20 +10,13 @@
 ; X86-LABEL: or_i8_ri:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    movl %eax, %ecx
-; X86-NEXT:    orb $-17, %cl
-; X86-NEXT:    je .LBB0_2
-; X86-NEXT:  # %bb.1:
-; X86-NEXT:    movl %ecx, %eax
-; X86-NEXT:  .LBB0_2:
+; X86-NEXT:    orb $-17, %al
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: or_i8_ri:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    orb $-17, %al
-; X64-NEXT:    movzbl %al, %eax
-; X64-NEXT:    cmovel %edi, %eax
 ; X64-NEXT:    # kill: def $al killed $al killed $eax
 ; X64-NEXT:    retq
   %3 = or i8 %0, -17
@@ -60,14 +53,8 @@
 define i16 @or_i16_ri(i16 zeroext %0, i16 zeroext %1) {
 ; X86-LABEL: or_i16_ri:
 ; X86:       # %bb.0:
-; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    movl %eax, %ecx
-; X86-NEXT:    orl $65519, %ecx # imm = 0xFFEF
-; X86-NEXT:    testw %cx, %cx
-; X86-NEXT:    je .LBB2_2
-; X86-NEXT:  # %bb.1:
-; X86-NEXT:    movl %ecx, %eax
-; X86-NEXT:  .LBB2_2:
+; X86-NEXT:    movl $65519, %eax # imm = 0xFFEF
+; X86-NEXT:    orl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    # kill: def $ax killed $ax killed $eax
 ; X86-NEXT:    retl
 ;
@@ -75,7 +62,6 @@
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    orl $65519, %eax # imm = 0xFFEF
-; X64-NEXT:    cmovel %edi, %eax
 ; X64-NEXT:    # kill: def $ax killed $ax killed $eax
 ; X64-NEXT:    retq
   %3 = or i16 %0, -17
@@ -114,19 +100,11 @@
 ; X86-LABEL: or_i32_ri:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    movl %eax, %ecx
-; X86-NEXT:    orl $-17, %ecx
-; X86-NEXT:    jle .LBB4_2
-; X86-NEXT:  # %bb.1:
-; X86-NEXT:    movl %ecx, %eax
-; X86-NEXT:  .LBB4_2:
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: or_i32_ri:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    orl $-17, %eax
-; X64-NEXT:    cmovlel %edi, %eax
 ; X64-NEXT:    retq
   %3 = or i32 %0, -17
   %4 = icmp slt i32 %3, 1
@@ -161,19 +139,13 @@
 define i64 @or_i64_ri(i64 %0, i64 %1) nounwind {
 ; X86-LABEL: or_i64_ri:
 ; X86:       # %bb.0:
-; X86-NEXT:    pushl %esi
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; X86-NEXT:    movl %eax, %ecx
-; X86-NEXT:    orl $17, %ecx
-; X86-NEXT:    cmpl $1, %ecx
-; X86-NEXT:    movl %edx, %esi
-; X86-NEXT:    sbbl $0, %esi
-; X86-NEXT:    jl .LBB6_2
+; X86-NEXT:    testl %edx, %edx
+; X86-NEXT:    js .LBB6_2
 ; X86-NEXT:  # %bb.1:
-; X86-NEXT:    movl %ecx, %eax
+; X86-NEXT:    orl $17, %eax
 ; X86-NEXT:  .LBB6_2:
-; X86-NEXT:    popl %esi
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: or_i64_ri:
diff --git a/llvm/test/CodeGen/X86/pr16031.ll b/llvm/test/CodeGen/X86/pr16031.ll
--- a/llvm/test/CodeGen/X86/pr16031.ll
+++ b/llvm/test/CodeGen/X86/pr16031.ll
@@ -4,16 +4,7 @@
 define i64 @main(i1 %tobool1) nounwind {
 ; CHECK-LABEL: main:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT:    andl $1, %eax
-; CHECK-NEXT:    decl %eax
-; CHECK-NEXT:    orl $-12, %eax
-; CHECK-NEXT:    xorl %ecx, %ecx
-; CHECK-NEXT:    movl %eax, %edx
-; CHECK-NEXT:    addl $-1, %edx
-; CHECK-NEXT:    movl $0, %edx
-; CHECK-NEXT:    adcl $-2, %edx
-; CHECK-NEXT:    cmovsl %ecx, %eax
+; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    retl
 entry:
diff --git a/llvm/test/CodeGen/X86/select.ll b/llvm/test/CodeGen/X86/select.ll
--- a/llvm/test/CodeGen/X86/select.ll
+++ b/llvm/test/CodeGen/X86/select.ll
@@ -60,7 +60,7 @@
 ; GENERIC-NEXT:    testb $1, %al
 ; GENERIC-NEXT:    movl $-3840, %eax ## imm = 0xF100
 ; GENERIC-NEXT:    cmovnel %ecx, %eax
-; GENERIC-NEXT:    cmpl $32768, %eax ## imm = 0x8000
+; GENERIC-NEXT:    cmpl $32767, %eax ## imm = 0x7FFF
 ; GENERIC-NEXT:    jge LBB1_1
 ; GENERIC-NEXT:  ## %bb.2: ## %bb91
 ; GENERIC-NEXT:    xorl %eax, %eax
@@ -77,7 +77,7 @@
 ; ATOM-NEXT:    movl $-3840, %edx ## imm = 0xF100
 ; ATOM-NEXT:    testb $1, %al
 ; ATOM-NEXT:    cmovnel %ecx, %edx
-; ATOM-NEXT:    cmpl $32768, %edx ## imm = 0x8000
+; ATOM-NEXT:    cmpl $32767, %edx ## imm = 0x7FFF
 ; ATOM-NEXT:    jge LBB1_1
 ; ATOM-NEXT:  ## %bb.2: ## %bb91
 ; ATOM-NEXT:    xorl %eax, %eax
@@ -94,7 +94,7 @@
 ; ATHLON-NEXT:    testb $1, %al
 ; ATHLON-NEXT:    movl $-3840, %eax ## imm = 0xF100
 ; ATHLON-NEXT:    cmovnel %ecx, %eax
-; ATHLON-NEXT:    cmpl $32768, %eax ## imm = 0x8000
+; ATHLON-NEXT:    cmpl $32767, %eax ## imm = 0x7FFF
 ; ATHLON-NEXT:    jge LBB1_1
 ; ATHLON-NEXT:  ## %bb.2: ## %bb91
 ; ATHLON-NEXT:    xorl %eax, %eax
@@ -112,7 +112,7 @@
 ; MCU-NEXT:  # %bb.1: # %entry
 ; MCU-NEXT:    movl $-3840, %ecx # imm = 0xF100
 ; MCU-NEXT:  .LBB1_2: # %entry
-; MCU-NEXT:    cmpl $32768, %ecx # imm = 0x8000
+; MCU-NEXT:    cmpl $32767, %ecx # imm = 0x7FFF
 ; MCU-NEXT:    jge .LBB1_3
 ; MCU-NEXT:  # %bb.4: # %bb91
 ; MCU-NEXT:    xorl %eax, %eax
diff --git a/llvm/test/CodeGen/X86/shrink-compare-pgso.ll b/llvm/test/CodeGen/X86/shrink-compare-pgso.ll
--- a/llvm/test/CodeGen/X86/shrink-compare-pgso.ll
+++ b/llvm/test/CodeGen/X86/shrink-compare-pgso.ll
@@ -124,8 +124,8 @@
 define dso_local void @test2_1(i32 %X) nounwind !prof !14 {
 ; CHECK-LABEL: test2_1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movzbl %dil, %eax
-; CHECK-NEXT:    cmpl $256, %eax # imm = 0x100
+; CHECK-NEXT:    movb $1, %al
+; CHECK-NEXT:    testb %al, %al
 ; CHECK-NEXT:    je bar # TAILCALL
 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    retq
diff --git a/llvm/test/CodeGen/X86/shrink-compare.ll b/llvm/test/CodeGen/X86/shrink-compare.ll
--- a/llvm/test/CodeGen/X86/shrink-compare.ll
+++ b/llvm/test/CodeGen/X86/shrink-compare.ll
@@ -124,8 +124,8 @@
 define dso_local void @test2_1(i32 %X) nounwind minsize {
 ; CHECK-LABEL: test2_1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movzbl %dil, %eax
-; CHECK-NEXT:    cmpl $256, %eax # imm = 0x100
+; CHECK-NEXT:    movb $1, %al
+; CHECK-NEXT:    testb %al, %al
 ; CHECK-NEXT:    je bar # TAILCALL
 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    retq