Index: lib/Target/PowerPC/PPC.td =================================================================== --- lib/Target/PowerPC/PPC.td +++ lib/Target/PowerPC/PPC.td @@ -137,6 +137,8 @@ "Enable Hardware Transactional Memory instructions">; def FeatureMFTB : SubtargetFeature<"", "FeatureMFTB", "true", "Implement mftb using the mfspr instruction">; +def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true", + "Target supports add/load integer fusion.">; def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true", "Treat vector data stream cache control instructions as deprecated">; @@ -168,7 +170,8 @@ FeatureMFTB, DeprecatedDST]; list Power8SpecificFeatures = [DirectivePwr8, FeatureP8Altivec, FeatureP8Vector, FeatureP8Crypto, - FeatureHTM, FeatureDirectMove, FeatureICBT, FeaturePartwordAtomic]; + FeatureHTM, FeatureDirectMove, FeatureICBT, FeaturePartwordAtomic, + FeatureFusion]; list Power8FeatureList = !listconcat(Power7FeatureList, Power8SpecificFeatures); } Index: lib/Target/PowerPC/PPCSubtarget.h =================================================================== --- lib/Target/PowerPC/PPCSubtarget.h +++ lib/Target/PowerPC/PPCSubtarget.h @@ -119,6 +119,7 @@ bool HasPartwordAtomics; bool HasDirectMove; bool HasHTM; + bool HasFusion; /// When targeting QPX running a stock PPC64 Linux kernel where the stack /// alignment has not been changed, we need to keep the 16-byte alignment @@ -254,6 +255,7 @@ return 16; } bool hasHTM() const { return HasHTM; } + bool hasFusion() const { return HasFusion; } const Triple &getTargetTriple() const { return TargetTriple; } Index: lib/Target/PowerPC/PPCSubtarget.cpp =================================================================== --- lib/Target/PowerPC/PPCSubtarget.cpp +++ lib/Target/PowerPC/PPCSubtarget.cpp @@ -100,6 +100,7 @@ HasDirectMove = false; IsQPXStackUnaligned = false; HasHTM = false; + HasFusion = false; } void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {