This is an archive of the discontinued LLVM Phabricator instance.

AMDGPU: Cache information about register pressure sets
ClosedPublic

Authored by tstellarAMD on Nov 18 2015, 7:42 PM.

Details

Summary

We can statically decide whether or not a register pressure set is for
SGPRs or VGPRs, so we don't need to re-compute this information in
SIRegisterInfo::getRegPressureSetLimit().

Diff Detail

Repository
rL LLVM

Event Timeline

tstellarAMD retitled this revision from to AMDGPU: Cache information about register pressure sets.
tstellarAMD updated this object.
tstellarAMD added a reviewer: arsenm.
tstellarAMD added a subscriber: llvm-commits.
arsenm added inline comments.Dec 14 2015, 9:45 AM
lib/Target/AMDGPU/SIRegisterInfo.cpp
118–121 ↗(On Diff #40597)

Are both SGPRPressureSets and VGPRPressureSets necessary? Can you just have one and assume if it isn't it's the other?

lib/Target/AMDGPU/SIRegisterInfo.cpp
118–121 ↗(On Diff #40597)

It's because of the VS_32 register class has both SGPRs. and VGPRs.

arsenm accepted this revision.Mar 22 2016, 1:24 PM
arsenm edited edge metadata.

LGTM

lib/Target/AMDGPU/SIRegisterInfo.cpp
118–121 ↗(On Diff #40597)

I should try to reapply my patch to try to get VS_32 to not influence pressure

This revision is now accepted and ready to land.Mar 22 2016, 1:24 PM
This revision was automatically updated to reflect the committed changes.