Index: lib/Target/Mips/AsmParser/MipsAsmParser.cpp =================================================================== --- lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -13,6 +13,7 @@ #include "MCTargetDesc/MipsMCTargetDesc.h" #include "MipsTargetStreamer.h" #include "MCTargetDesc/MipsBaseInfo.h" +#include "llvm/ADT/APFloat.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringSwitch.h" @@ -219,6 +220,10 @@ bool expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI); + bool expandLoadImmReal(MCInst &Inst, bool IsSingle, bool IsGPR, bool Is64FPU, + SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI); + bool expandLoadAddress(unsigned DstReg, unsigned BaseReg, const MCOperand &Offset, bool Is32BitAddress, SMLoc IDLoc, MCStreamer &Out, @@ -989,6 +994,16 @@ Inst.addOperand(MCOperand::createReg(getAFGR64Reg())); } + void addStrictlyAFGR64AsmRegOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + Inst.addOperand(MCOperand::createReg(getAFGR64Reg())); + } + + void addStrictlyFGR64AsmRegOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + Inst.addOperand(MCOperand::createReg(getFGR64Reg())); + } + void addFGR64AsmRegOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createReg(getFGR64Reg())); @@ -1005,6 +1020,15 @@ "registers"); } + void addStrictlyFGR32AsmRegOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + Inst.addOperand(MCOperand::createReg(getFGR32Reg())); + // FIXME: We ought to do this for -integrated-as without -via-file-asm too. + if (!AsmParser.useOddSPReg() && RegIdx.Index & 1) + AsmParser.Error(StartLoc, "-mno-odd-spreg prohibits the use of odd FPU " + "registers"); + } + void addFGRH32AsmRegOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createReg(getFGRH32Reg())); @@ -1543,6 +1567,11 @@ return isRegIdx() && RegIdx.Kind & RegKind_FGR && RegIdx.Index <= 31; } + bool isStrictlyFGRAsmReg() const { + // AFGR64 is $0-$15 but we handle this in getAFGR64() + return isRegIdx() && RegIdx.Kind == RegKind_FGR && RegIdx.Index <= 31; + } + bool isHWRegsAsmReg() const { return isRegIdx() && RegIdx.Kind & RegKind_HWRegs && RegIdx.Index <= 31; } @@ -2282,6 +2311,27 @@ case Mips::PseudoTRUNC_W_D: return expandTrunc(Inst, true, true, IDLoc, Out, STI) ? MER_Fail : MER_Success; + + case Mips::LoadImmSingleGPR: + return expandLoadImmReal(Inst, true, true, false, IDLoc, Out, STI) + ? MER_Fail + : MER_Success; + case Mips::LoadImmSingleFGR: + return expandLoadImmReal(Inst, true, false, false, IDLoc, Out, STI) + ? MER_Fail + : MER_Success; + case Mips::LoadImmDoubleGPR: + return expandLoadImmReal(Inst, false, true, false, IDLoc, Out, STI) + ? MER_Fail + : MER_Success; + case Mips::LoadImmDoubleFGR: + return expandLoadImmReal(Inst, false, false, true, IDLoc, Out, STI) + ? MER_Fail + : MER_Success; + case Mips::LoadImmDoubleFGR_32: + return expandLoadImmReal(Inst, false, false, false, IDLoc, Out, STI) + ? MER_Fail + : MER_Success; case Mips::Ulh: return expandUlh(Inst, true, IDLoc, Out, STI) ? MER_Fail : MER_Success; case Mips::Ulhu: @@ -2843,6 +2893,282 @@ return false; } +static unsigned nextReg(unsigned Reg) { + if (MipsMCRegisterClasses[Mips::FGR32RegClassID].contains(Reg)) + return Reg == (unsigned)Mips::F31 ? (unsigned)Mips::F0 : Reg + 1; + switch (Reg) { + default: llvm_unreachable("Unknown register in assembly macro expansion!"); + case Mips::ZERO: return Mips::AT; + case Mips::AT: return Mips::V0; + case Mips::V0: return Mips::V1; + case Mips::V1: return Mips::A0; + case Mips::A0: return Mips::A1; + case Mips::A1: return Mips::A2; + case Mips::A2: return Mips::A3; + case Mips::A3: return Mips::T0; + case Mips::T0: return Mips::T1; + case Mips::T1: return Mips::T2; + case Mips::T2: return Mips::T3; + case Mips::T3: return Mips::T4; + case Mips::T4: return Mips::T5; + case Mips::T5: return Mips::T6; + case Mips::T6: return Mips::T7; + case Mips::T7: return Mips::S0; + case Mips::S0: return Mips::S1; + case Mips::S1: return Mips::S2; + case Mips::S2: return Mips::S3; + case Mips::S3: return Mips::S4; + case Mips::S4: return Mips::S5; + case Mips::S5: return Mips::S6; + case Mips::S6: return Mips::S7; + case Mips::S7: return Mips::T8; + case Mips::T8: return Mips::T9; + case Mips::T9: return Mips::K0; + case Mips::K0: return Mips::K1; + case Mips::K1: return Mips::GP; + case Mips::GP: return Mips::SP; + case Mips::SP: return Mips::FP; + case Mips::FP: return Mips::RA; + case Mips::RA: return Mips::ZERO; + case Mips::D0: return Mips::F1; + case Mips::D1: return Mips::F3; + case Mips::D2: return Mips::F5; + case Mips::D3: return Mips::F7; + case Mips::D4: return Mips::F9; + case Mips::D5: return Mips::F11; + case Mips::D6: return Mips::F13; + case Mips::D7: return Mips::F15; + case Mips::D8: return Mips::F17; + case Mips::D9: return Mips::F19; + case Mips::D10: return Mips::F21; + case Mips::D11: return Mips::F23; + case Mips::D12: return Mips::F25; + case Mips::D13: return Mips::F27; + case Mips::D14: return Mips::F29; + case Mips::D15: return Mips::F31; + } +} + +bool MipsAsmParser::expandLoadImmReal(MCInst &Inst, bool IsSingle, bool IsGPR, + bool Is64FPU, SMLoc IDLoc, + MCStreamer &Out, + const MCSubtargetInfo *STI) { + MipsTargetStreamer &TOut = getTargetStreamer(); + assert(Inst.getNumOperands() == 2 && "Invalid operand count"); + assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() && + "Invalid instruction operand."); + + unsigned FirstReg = Inst.getOperand(0).getReg(); + uint64_t ImmOp64 = Inst.getOperand(1).getImm(); + + + + uint32_t HiImmOp64 = (ImmOp64 & 0xffffffff00000000) >> 32; + // If ImmOp64 is AsmToken::Integer type (all bits set to zero in the + // exponent field), convert it to double (e.g. 1 to 1.0) + if ((HiImmOp64 & 0x7ff00000) == 0) { + APFloat RealVal(APFloat::IEEEdouble(), ImmOp64); + ImmOp64 = RealVal.bitcastToAPInt().getZExtValue(); + } + + uint32_t LoImmOp64 = ImmOp64 & 0xffffffff; + HiImmOp64 = (ImmOp64 & 0xffffffff00000000) >> 32; + + if (IsSingle) { + // Conversion of a double in an uint64_t to a float in a uint32_t, + // retaining the bit pattern of a float. + uint32_t ImmOp32; + void *void_pt = static_cast(&ImmOp64); + double *double_pt = static_cast(void_pt); + float tmp_float = static_cast(*double_pt); + void_pt = &tmp_float; + uint32_t *uint32_pt = static_cast(void_pt); + ImmOp32 = *uint32_pt; + + if (IsGPR) { + if (loadImmediate(ImmOp32, FirstReg, Mips::NoRegister, true, true, IDLoc, + Out, STI)) + return true; + return false; + } else { + if (LoImmOp64 == 0) { + unsigned ATReg = getATReg(IDLoc); + if (!ATReg) + return true; + + if (loadImmediate(ImmOp32, ATReg, Mips::NoRegister, true, true, IDLoc, + Out, STI)) + return true; + TOut.emitRR(Mips::MTC1, FirstReg, ATReg, IDLoc, STI); + return false; + } + + MCSection *CS = getStreamer().getCurrentSectionOnly(); + // FIXME: Enhance this expansion to use the .lit4 & .lit8 sections + // where appropriate. + MCSection *ReadOnlySection = getContext().getELFSection( + ".rodata", ELF::SHT_PROGBITS, ELF::SHF_ALLOC); + getStreamer().SwitchSection(ReadOnlySection); + getStreamer().EmitIntValue(ImmOp32, 4); + getStreamer().SwitchSection(CS); + + MCSymbol *Sym = getContext().getOrCreateSymbol( + (dyn_cast(ReadOnlySection))->getSectionName()); + + const MCExpr *LitSym = + MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); + + const MipsMCExpr *LitExpr = + MipsMCExpr::create(MipsMCExpr::MEK_LITERAL, LitSym, getContext()); + + int32_t size_data_fragment = 0; + MCSection::FragmentListType &FragList = + ReadOnlySection->getFragmentList(); + if (!FragList.empty()) { + MCDataFragment *DF = + &cast(ReadOnlySection->getFragmentList().back()); + size_data_fragment = DF->getContents().size(); + } + + const MCExpr *FixupAddr = MCBinaryExpr::createAdd( + LitExpr, MCConstantExpr::create(size_data_fragment - 4, getContext()), + getContext()); + + TOut.emitRRX(Mips::LWC1, FirstReg, Mips::GP, + MCOperand::createExpr(FixupAddr), IDLoc, STI); + + return false; + } + return false; + } + + // if(!IsSingle) + if (IsGPR) { + unsigned ATReg = getATReg(IDLoc); + if (!ATReg) + return true; + + if (LoImmOp64 == 0) { + if (loadImmediate(HiImmOp64, FirstReg, Mips::NoRegister, true, true, + IDLoc, Out, STI)) + return true; + + if (loadImmediate(0, nextReg(FirstReg), Mips::NoRegister, true, true, + IDLoc, Out, STI)) + return true; + return false; + } + + MCSection *CS = getStreamer().getCurrentSectionOnly(); + MCSection *ReadOnlySection = getContext().getELFSection( + ".rodata", ELF::SHT_PROGBITS, ELF::SHF_ALLOC); + getStreamer().SwitchSection(ReadOnlySection); + getStreamer().EmitIntValue(HiImmOp64, 4); + getStreamer().EmitIntValue(LoImmOp64, 4); + getStreamer().SwitchSection(CS); + + int32_t size_data_fragment = 0; + MCSection::FragmentListType &FragList = ReadOnlySection->getFragmentList(); + if (!FragList.empty()) { + MCDataFragment *DF = + &cast(ReadOnlySection->getFragmentList().back()); + size_data_fragment = DF->getContents().size(); + } + + MCSymbol *Sym = getContext().getOrCreateSymbol( + (dyn_cast(ReadOnlySection))->getSectionName()); + + const MCExpr *HiSym = + MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); + + const MipsMCExpr *HiExpr = + MipsMCExpr::create(MipsMCExpr::MEK_HI, HiSym, getContext()); + + const MCExpr *LoSym = + MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); + + const MipsMCExpr *LoExpr = + MipsMCExpr::create(MipsMCExpr::MEK_LO, LoSym, getContext()); + + TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HiExpr), IDLoc, STI); + + const MCExpr *FixupAddr = MCBinaryExpr::createAdd( + LoExpr, MCConstantExpr::create(size_data_fragment - 8, getContext()), + getContext()); + + TOut.emitRRX(Mips::LW, FirstReg, ATReg, MCOperand::createExpr(FixupAddr), + IDLoc, STI); + + FixupAddr = MCBinaryExpr::createAdd( + LoExpr, MCConstantExpr::create(size_data_fragment - 4, getContext()), + getContext()); + + TOut.emitRRX(Mips::LW, nextReg(FirstReg), ATReg, + MCOperand::createExpr(FixupAddr), IDLoc, STI); + + return false; + } else { // if(!IsGPR && !IsSingle) + if ((LoImmOp64 == 0) && + !((HiImmOp64 & 0xffff0000) && (HiImmOp64 & 0x0000ffff))) { + unsigned ATReg = getATReg(IDLoc); + if (!ATReg) + return true; + // FIXME: In the case where the constant is zero, we can load the + // register directly from the zero register. + if (loadImmediate(HiImmOp64, ATReg, Mips::NoRegister, true, true, IDLoc, + Out, STI)) + return true; + if (hasMips64()) + TOut.emitRR(Mips::DMTC1, FirstReg, ATReg, IDLoc, STI); + else if (hasMips32r2()) { + TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI); + TOut.emitRRR(Mips::MTHC1_D32, FirstReg, FirstReg, ATReg, IDLoc, STI); + } else { + TOut.emitRR(Mips::MTC1, nextReg(FirstReg), ATReg, IDLoc, STI); + TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI); + } + return false; + } + + MCSection *CS = getStreamer().getCurrentSectionOnly(); + // FIXME: Enhance this expansion to use the .lit4 & .lit8 sections + // where appropriate. + MCSection *ReadOnlySection = getContext().getELFSection( + ".rodata", ELF::SHT_PROGBITS, ELF::SHF_ALLOC); + getStreamer().SwitchSection(ReadOnlySection); + getStreamer().EmitIntValue(HiImmOp64, 4); + getStreamer().EmitIntValue(LoImmOp64, 4); + getStreamer().SwitchSection(CS); + + int32_t size_data_fragment = 0; + MCSection::FragmentListType &FragList = ReadOnlySection->getFragmentList(); + if (!FragList.empty()) { + MCDataFragment *DF = + &cast(ReadOnlySection->getFragmentList().back()); + size_data_fragment = DF->getContents().size(); + } + + MCSymbol *Sym = getContext().getOrCreateSymbol( + (dyn_cast(ReadOnlySection))->getSectionName()); + + const MCExpr *LitSym = + MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); + + const MipsMCExpr *LitExpr = + MipsMCExpr::create(MipsMCExpr::MEK_LITERAL, LitSym, getContext()); + + const MCExpr *FixupAddr = MCBinaryExpr::createAdd( + LitExpr, MCConstantExpr::create(size_data_fragment - 8, getContext()), + getContext()); + + // FIXME: This expansion is incorrect for mips1 where it should expand to + // two word loads. + TOut.emitRRX(Is64FPU ? Mips::LDC164 : Mips::LDC1, FirstReg, Mips::GP, + MCOperand::createExpr(FixupAddr), IDLoc, STI); + } + return false; +} + bool MipsAsmParser::expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { @@ -4060,45 +4386,6 @@ return false; } -static unsigned nextReg(unsigned Reg) { - switch (Reg) { - case Mips::ZERO: return Mips::AT; - case Mips::AT: return Mips::V0; - case Mips::V0: return Mips::V1; - case Mips::V1: return Mips::A0; - case Mips::A0: return Mips::A1; - case Mips::A1: return Mips::A2; - case Mips::A2: return Mips::A3; - case Mips::A3: return Mips::T0; - case Mips::T0: return Mips::T1; - case Mips::T1: return Mips::T2; - case Mips::T2: return Mips::T3; - case Mips::T3: return Mips::T4; - case Mips::T4: return Mips::T5; - case Mips::T5: return Mips::T6; - case Mips::T6: return Mips::T7; - case Mips::T7: return Mips::S0; - case Mips::S0: return Mips::S1; - case Mips::S1: return Mips::S2; - case Mips::S2: return Mips::S3; - case Mips::S3: return Mips::S4; - case Mips::S4: return Mips::S5; - case Mips::S5: return Mips::S6; - case Mips::S6: return Mips::S7; - case Mips::S7: return Mips::T8; - case Mips::T8: return Mips::T9; - case Mips::T9: return Mips::K0; - case Mips::K0: return Mips::K1; - case Mips::K1: return Mips::GP; - case Mips::GP: return Mips::SP; - case Mips::SP: return Mips::FP; - case Mips::FP: return Mips::RA; - case Mips::RA: return Mips::ZERO; - default: return 0; - } - -} - // Expand 'ld $ offset($reg2)' to 'lw $, offset($reg2); // lw $>, offset+4($reg2)' // or expand 'sd $ offset($reg2)' to 'sw $, offset($reg2); Index: lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp +++ lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp @@ -290,6 +290,8 @@ return Type; } return ELF::R_MIPS_GPREL32; + case Mips::fixup_Mips_LITERAL: + return ELF::R_MIPS_LITERAL; case Mips::fixup_Mips_GPREL16: return ELF::R_MIPS_GPREL16; case Mips::fixup_Mips_26: Index: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp +++ lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp @@ -706,6 +706,9 @@ FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16 : Mips::fixup_Mips_LO16; break; + case MipsMCExpr::MEK_LITERAL: + FixupKind = Mips::fixup_Mips_LITERAL; + break; case MipsMCExpr::MEK_HIGHEST: FixupKind = Mips::fixup_Mips_HIGHEST; break; Index: lib/Target/Mips/MCTargetDesc/MipsMCExpr.h =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsMCExpr.h +++ lib/Target/Mips/MCTargetDesc/MipsMCExpr.h @@ -36,6 +36,7 @@ MEK_HI, MEK_HIGHER, MEK_HIGHEST, + MEK_LITERAL, MEK_LO, MEK_NEG, MEK_PCREL_HI16, Index: lib/Target/Mips/MCTargetDesc/MipsMCExpr.cpp =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsMCExpr.cpp +++ lib/Target/Mips/MCTargetDesc/MipsMCExpr.cpp @@ -91,6 +91,9 @@ case MEK_HIGHEST: OS << "%highest"; break; + case MEK_LITERAL: + OS << "%lit4"; + break; case MEK_LO: OS << "%lo"; break; @@ -172,6 +175,7 @@ case MEK_PCREL_LO16: case MEK_TLSGD: case MEK_TLSLDM: + case MEK_LITERAL: case MEK_TPREL_HI: case MEK_TPREL_LO: return false; @@ -259,6 +263,7 @@ case MEK_HI: case MEK_HIGHER: case MEK_HIGHEST: + case MEK_LITERAL: case MEK_LO: case MEK_NEG: case MEK_PCREL_HI16: Index: lib/Target/Mips/MipsInstrFPU.td =================================================================== --- lib/Target/Mips/MipsInstrFPU.td +++ lib/Target/Mips/MipsInstrFPU.td @@ -681,6 +681,29 @@ "trunc.w.d\t$fd, $fs, $rs">, FGR_64, HARDFLOAT; +def LoadImmSingleGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), + (ins imm64:$fpimm), + "li.s\t$rd, $fpimm">; + +def LoadImmSingleFGR : MipsAsmPseudoInst<(outs StrictlyFGR32Opnd:$rd), + (ins imm64:$fpimm), + "li.s\t$rd, $fpimm">, + HARDFLOAT; + +def LoadImmDoubleGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), + (ins imm64:$fpimm), + "li.d\t$rd, $fpimm">; + +def LoadImmDoubleFGR_32 : MipsAsmPseudoInst<(outs StrictlyAFGR64Opnd:$rd), + (ins imm64:$fpimm), + "li.d\t$rd, $fpimm">, + FGR_32, HARDFLOAT; + +def LoadImmDoubleFGR : MipsAsmPseudoInst<(outs StrictlyFGR64Opnd:$rd), + (ins imm64:$fpimm), + "li.d\t$rd, $fpimm">, + FGR_64, HARDFLOAT; + //===----------------------------------------------------------------------===// // InstAliases. //===----------------------------------------------------------------------===// Index: lib/Target/Mips/MipsRegisterInfo.td =================================================================== --- lib/Target/Mips/MipsRegisterInfo.td +++ lib/Target/Mips/MipsRegisterInfo.td @@ -523,16 +523,31 @@ let PredicateMethod = "isFGRAsmReg"; } +def StrictlyAFGR64AsmOperand : MipsAsmRegOperand { + let Name = "StrictlyAFGR64AsmReg"; + let PredicateMethod = "isStrictlyFGRAsmReg"; +} + def FGR64AsmOperand : MipsAsmRegOperand { let Name = "FGR64AsmReg"; let PredicateMethod = "isFGRAsmReg"; } +def StrictlyFGR64AsmOperand : MipsAsmRegOperand { + let Name = "StrictlyFGR64AsmReg"; + let PredicateMethod = "isStrictlyFGRAsmReg"; +} + def FGR32AsmOperand : MipsAsmRegOperand { let Name = "FGR32AsmReg"; let PredicateMethod = "isFGRAsmReg"; } +def StrictlyFGR32AsmOperand : MipsAsmRegOperand { + let Name = "StrictlyFGR32AsmReg"; + let PredicateMethod = "isStrictlyFGRAsmReg"; +} + def FGRH32AsmOperand : MipsAsmRegOperand { let Name = "FGRH32AsmReg"; let PredicateMethod = "isFGRAsmReg"; @@ -602,14 +617,26 @@ let ParserMatchClass = AFGR64AsmOperand; } +def StrictlyAFGR64Opnd : RegisterOperand { + let ParserMatchClass = StrictlyAFGR64AsmOperand; +} + def FGR64Opnd : RegisterOperand { let ParserMatchClass = FGR64AsmOperand; } +def StrictlyFGR64Opnd : RegisterOperand { + let ParserMatchClass = StrictlyFGR64AsmOperand; +} + def FGR32Opnd : RegisterOperand { let ParserMatchClass = FGR32AsmOperand; } +def StrictlyFGR32Opnd : RegisterOperand { + let ParserMatchClass = StrictlyFGR32AsmOperand; +} + def FGRCCOpnd : RegisterOperand { // The assembler doesn't use register classes so we can re-use // FGR32AsmOperand. Index: test/MC/Mips/macro-li.d.s =================================================================== --- test/MC/Mips/macro-li.d.s +++ test/MC/Mips/macro-li.d.s @@ -0,0 +1,283 @@ +# RUN: llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips32 -show-encoding | FileCheck %s --check-prefix=CHECK-MIPS32 +# RUN: llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips32r2 -show-encoding | FileCheck %s --check-prefix=CHECK-MIPS32r2 +# RUN: llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips64 -show-encoding | FileCheck %s --check-prefix=CHECK-MIPS64 + +li.d $4, 0 +# CHECK-MIPS32: addiu $4, $zero, 0 # encoding: [0x00,0x00,0x04,0x24] +# CHECK-MIPS32: addiu $5, $zero, 0 # encoding: [0x00,0x00,0x05,0x24] +# CHECK-MIPS32r2: addiu $4, $zero, 0 # encoding: [0x00,0x00,0x04,0x24] +# CHECK-MIPS32r2: addiu $5, $zero, 0 # encoding: [0x00,0x00,0x05,0x24] +# CHECK-MIPS64: addiu $4, $zero, 0 # encoding: [0x00,0x00,0x04,0x24] +# CHECK-MIPS64: addiu $5, $zero, 0 # encoding: [0x00,0x00,0x05,0x24] + +li.d $4, 0.0 +# CHECK-MIPS32: addiu $4, $zero, 0 # encoding: [0x00,0x00,0x04,0x24] +# CHECK-MIPS32: addiu $5, $zero, 0 # encoding: [0x00,0x00,0x05,0x24] +# CHECK-MIPS32r2: addiu $4, $zero, 0 # encoding: [0x00,0x00,0x04,0x24] +# CHECK-MIPS32r2: addiu $5, $zero, 0 # encoding: [0x00,0x00,0x05,0x24] +# CHECK-MIPS64: addiu $4, $zero, 0 # encoding: [0x00,0x00,0x04,0x24] +# CHECK-MIPS64: addiu $5, $zero, 0 # encoding: [0x00,0x00,0x05,0x24] + +li.d $4, 1.12345 +# CHECK-MIPS32: lui $1, %hi(.rodata) # encoding: [A,A,0x01,0x3c] +# CHECK-MIPS32: # fixup A - offset: 0, value: %hi(.rodata), kind: fixup_Mips_HI16 +# CHECK-MIPS32: lw $4, (%lo(.rodata))-8($1) # encoding: [0xf8'A',0xff'A',0x24,0x8c] +# CHECK-MIPS32: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 +# CHECK-MIPS32: lw $5, (%lo(.rodata))-4($1) # encoding: [0xfc'A',0xff'A',0x25,0x8c] +# CHECK-MIPS32: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 +# CHECK-MIPS32r2: lui $1, %hi(.rodata) # encoding: [A,A,0x01,0x3c] +# CHECK-MIPS32r2: # fixup A - offset: 0, value: %hi(.rodata), kind: fixup_Mips_HI16 +# CHECK-MIPS32r2: lw $4, (%lo(.rodata))-8($1) # encoding: [0xf8'A',0xff'A',0x24,0x8c] +# CHECK-MIPS32r2: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 +# CHECK-MIPS32r2: lw $5, (%lo(.rodata))-4($1) # encoding: [0xfc'A',0xff'A',0x25,0x8c] +# CHECK-MIPS32r2: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 +# CHECK-MIPS64: lui $1, %hi(.rodata) # encoding: [A,A,0x01,0x3c] +# CHECK-MIPS64: # fixup A - offset: 0, value: %hi(.rodata), kind: fixup_Mips_HI16 +# CHECK-MIPS64: lw $4, (%lo(.rodata))-8($1) # encoding: [0xf8'A',0xff'A',0x24,0x8c] +# CHECK-MIPS64: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 +# CHECK-MIPS64: lw $5, (%lo(.rodata))-4($1) # encoding: [0xfc'A',0xff'A',0x25,0x8c] +# CHECK-MIPS64: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 + +li.d $4, 1 +# CHECK-MIPS32: lui $4, 16368 # encoding: [0xf0,0x3f,0x04,0x3c] +# CHECK-MIPS32: addiu $5, $zero, 0 # encoding: [0x00,0x00,0x05,0x24] +# CHECK-MIPS32r2: lui $4, 16368 # encoding: [0xf0,0x3f,0x04,0x3c] +# CHECK-MIPS32r2: addiu $5, $zero, 0 # encoding: [0x00,0x00,0x05,0x24] +# CHECK-MIPS64: lui $4, 16368 # encoding: [0xf0,0x3f,0x04,0x3c] +# CHECK-MIPS64: addiu $5, $zero, 0 # encoding: [0x00,0x00,0x05,0x24] + +li.d $4, 1.0 +# CHECK-MIPS32: lui $4, 16368 # encoding: [0xf0,0x3f,0x04,0x3c] +# CHECK-MIPS32: addiu $5, $zero, 0 # encoding: [0x00,0x00,0x05,0x24] +# CHECK-MIPS32r2: lui $4, 16368 # encoding: [0xf0,0x3f,0x04,0x3c] +# CHECK-MIPS32r2: addiu $5, $zero, 0 # encoding: [0x00,0x00,0x05,0x24] +# CHECK-MIPS64: lui $4, 16368 # encoding: [0xf0,0x3f,0x04,0x3c] +# CHECK-MIPS64: addiu $5, $zero, 0 # encoding: [0x00,0x00,0x05,0x24] + +li.d $4, 12345678910 +# CHECK-MIPS32: lui $1, %hi(.rodata) # encoding: [A,A,0x01,0x3c] +# CHECK-MIPS32: # fixup A - offset: 0, value: %hi(.rodata), kind: fixup_Mips_HI16 +# CHECK-MIPS32: lw $4, (%lo(.rodata))-8($1) # encoding: [0xf8'A',0xff'A',0x24,0x8c] +# CHECK-MIPS32: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 +# CHECK-MIPS32: lw $5, (%lo(.rodata))-4($1) # encoding: [0xfc'A',0xff'A',0x25,0x8c] +# CHECK-MIPS32: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 +# CHECK-MIPS32r2: lui $1, %hi(.rodata) # encoding: [A,A,0x01,0x3c] +# CHECK-MIPS32r2: # fixup A - offset: 0, value: %hi(.rodata), kind: fixup_Mips_HI16 +# CHECK-MIPS32r2: lw $4, (%lo(.rodata))-8($1) # encoding: [0xf8'A',0xff'A',0x24,0x8c] +# CHECK-MIPS32r2: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 +# CHECK-MIPS32r2: lw $5, (%lo(.rodata))-4($1) # encoding: [0xfc'A',0xff'A',0x25,0x8c] +# CHECK-MIPS32r2: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 +# CHECK-MIPS64: lui $1, %hi(.rodata) # encoding: [A,A,0x01,0x3c] +# CHECK-MIPS64: # fixup A - offset: 0, value: %hi(.rodata), kind: fixup_Mips_HI16 +# CHECK-MIPS64: lw $4, (%lo(.rodata))-8($1) # encoding: [0xf8'A',0xff'A',0x24,0x8c] +# CHECK-MIPS64: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 +# CHECK-MIPS64: lw $5, (%lo(.rodata))-4($1) # encoding: [0xfc'A',0xff'A',0x25,0x8c] +# CHECK-MIPS64: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 + +li.d $4, 12345678910.0 +# CHECK-MIPS32: lui $1, %hi(.rodata) # encoding: [A,A,0x01,0x3c] +# CHECK-MIPS32: # fixup A - offset: 0, value: %hi(.rodata), kind: fixup_Mips_HI16 +# CHECK-MIPS32: lw $4, (%lo(.rodata))-8($1) # encoding: [0xf8'A',0xff'A',0x24,0x8c] +# CHECK-MIPS32: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 +# CHECK-MIPS32: lw $5, (%lo(.rodata))-4($1) # encoding: [0xfc'A',0xff'A',0x25,0x8c] +# CHECK-MIPS32: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 +# CHECK-MIPS32r2: lui $1, %hi(.rodata) # encoding: [A,A,0x01,0x3c] +# CHECK-MIPS32r2: # fixup A - offset: 0, value: %hi(.rodata), kind: fixup_Mips_HI16 +# CHECK-MIPS32r2: lw $4, (%lo(.rodata))-8($1) # encoding: [0xf8'A',0xff'A',0x24,0x8c] +# CHECK-MIPS32r2: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 +# CHECK-MIPS32r2: lw $5, (%lo(.rodata))-4($1) # encoding: [0xfc'A',0xff'A',0x25,0x8c] +# CHECK-MIPS32r2: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 +# CHECK-MIPS64: lui $1, %hi(.rodata) # encoding: [A,A,0x01,0x3c] +# CHECK-MIPS64: # fixup A - offset: 0, value: %hi(.rodata), kind: fixup_Mips_HI16 +# CHECK-MIPS64: lw $4, (%lo(.rodata))-8($1) # encoding: [0xf8'A',0xff'A',0x24,0x8c] +# CHECK-MIPS64: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 +# CHECK-MIPS64: lw $5, (%lo(.rodata))-4($1) # encoding: [0xfc'A',0xff'A',0x25,0x8c] +# CHECK-MIPS64: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 + +li.d $4, 0.4 +# CHECK-MIPS32: lui $1, %hi(.rodata) # encoding: [A,A,0x01,0x3c] +# CHECK-MIPS32: # fixup A - offset: 0, value: %hi(.rodata), kind: fixup_Mips_HI16 +# CHECK-MIPS32: lw $4, (%lo(.rodata))-8($1) # encoding: [0xf8'A',0xff'A',0x24,0x8c] +# CHECK-MIPS32: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 +# CHECK-MIPS32: lw $5, (%lo(.rodata))-4($1) # encoding: [0xfc'A',0xff'A',0x25,0x8c] +# CHECK-MIPS32: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 +# CHECK-MIPS32r2: lui $1, %hi(.rodata) # encoding: [A,A,0x01,0x3c] +# CHECK-MIPS32r2: # fixup A - offset: 0, value: %hi(.rodata), kind: fixup_Mips_HI16 +# CHECK-MIPS32r2: lw $4, (%lo(.rodata))-8($1) # encoding: [0xf8'A',0xff'A',0x24,0x8c] +# CHECK-MIPS32r2: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 +# CHECK-MIPS32r2: lw $5, (%lo(.rodata))-4($1) # encoding: [0xfc'A',0xff'A',0x25,0x8c] +# CHECK-MIPS32r2: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 +# CHECK-MIPS64: lui $1, %hi(.rodata) # encoding: [A,A,0x01,0x3c] +# CHECK-MIPS64: # fixup A - offset: 0, value: %hi(.rodata), kind: fixup_Mips_HI16 +# CHECK-MIPS64: lw $4, (%lo(.rodata))-8($1) # encoding: [0xf8'A',0xff'A',0x24,0x8c] +# CHECK-MIPS64: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 +# CHECK-MIPS64: lw $5, (%lo(.rodata))-4($1) # encoding: [0xfc'A',0xff'A',0x25,0x8c] +# CHECK-MIPS64: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 + +li.d $4, 1.5 +# CHECK-MIPS32: lui $4, 16376 # encoding: [0xf8,0x3f,0x04,0x3c] +# CHECK-MIPS32: addiu $5, $zero, 0 # encoding: [0x00,0x00,0x05,0x24] +# CHECK-MIPS32r2: lui $4, 16376 # encoding: [0xf8,0x3f,0x04,0x3c] +# CHECK-MIPS32r2: addiu $5, $zero, 0 # encoding: [0x00,0x00,0x05,0x24] +# CHECK-MIPS64: lui $4, 16376 # encoding: [0xf8,0x3f,0x04,0x3c] +# CHECK-MIPS64: addiu $5, $zero, 0 # encoding: [0x00,0x00,0x05,0x24] + +li.d $4, 12345678910.12345678910 +# CHECK-MIPS32: lui $1, %hi(.rodata) # encoding: [A,A,0x01,0x3c] +# CHECK-MIPS32: # fixup A - offset: 0, value: %hi(.rodata), kind: fixup_Mips_HI16 +# CHECK-MIPS32: lw $4, (%lo(.rodata))-8($1) # encoding: [0xf8'A',0xff'A',0x24,0x8c] +# CHECK-MIPS32: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 +# CHECK-MIPS32: lw $5, (%lo(.rodata))-4($1) # encoding: [0xfc'A',0xff'A',0x25,0x8c] +# CHECK-MIPS32: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 +# CHECK-MIPS32r2: lui $1, %hi(.rodata) # encoding: [A,A,0x01,0x3c] +# CHECK-MIPS32r2: # fixup A - offset: 0, value: %hi(.rodata), kind: fixup_Mips_HI16 +# CHECK-MIPS32r2: lw $4, (%lo(.rodata))-8($1) # encoding: [0xf8'A',0xff'A',0x24,0x8c] +# CHECK-MIPS32r2: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 +# CHECK-MIPS32r2: lw $5, (%lo(.rodata))-4($1) # encoding: [0xfc'A',0xff'A',0x25,0x8c] +# CHECK-MIPS32r2: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 +# CHECK-MIPS64: lui $1, %hi(.rodata) # encoding: [A,A,0x01,0x3c] +# CHECK-MIPS64: # fixup A - offset: 0, value: %hi(.rodata), kind: fixup_Mips_HI16 +# CHECK-MIPS64: lw $4, (%lo(.rodata))-8($1) # encoding: [0xf8'A',0xff'A',0x24,0x8c] +# CHECK-MIPS64: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 +# CHECK-MIPS64: lw $5, (%lo(.rodata))-4($1) # encoding: [0xfc'A',0xff'A',0x25,0x8c] +# CHECK-MIPS64: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 + +li.d $4, 12345678910123456789.12345678910 +# CHECK-MIPS32: lui $1, %hi(.rodata) # encoding: [A,A,0x01,0x3c] +# CHECK-MIPS32: # fixup A - offset: 0, value: %hi(.rodata), kind: fixup_Mips_HI16 +# CHECK-MIPS32: lw $4, (%lo(.rodata))-8($1) # encoding: [0xf8'A',0xff'A',0x24,0x8c] +# CHECK-MIPS32: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 +# CHECK-MIPS32: lw $5, (%lo(.rodata))-4($1) # encoding: [0xfc'A',0xff'A',0x25,0x8c] +# CHECK-MIPS32: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 +# CHECK-MIPS32r2: lui $1, %hi(.rodata) # encoding: [A,A,0x01,0x3c] +# CHECK-MIPS32r2: # fixup A - offset: 0, value: %hi(.rodata), kind: fixup_Mips_HI16 +# CHECK-MIPS32r2: lw $4, (%lo(.rodata))-8($1) # encoding: [0xf8'A',0xff'A',0x24,0x8c] +# CHECK-MIPS32r2: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 +# CHECK-MIPS32r2: lw $5, (%lo(.rodata))-4($1) # encoding: [0xfc'A',0xff'A',0x25,0x8c] +# CHECK-MIPS32r2: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 +# CHECK-MIPS64: lui $1, %hi(.rodata) # encoding: [A,A,0x01,0x3c] +# CHECK-MIPS64: # fixup A - offset: 0, value: %hi(.rodata), kind: fixup_Mips_HI16 +# CHECK-MIPS64: lw $4, (%lo(.rodata))-8($1) # encoding: [0xf8'A',0xff'A',0x24,0x8c] +# CHECK-MIPS64: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 +# CHECK-MIPS64: lw $5, (%lo(.rodata))-4($1) # encoding: [0xfc'A',0xff'A',0x25,0x8c] +# CHECK-MIPS64: # fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16 + +li.d $f4, 0 +# CHECK-MIPS32: addiu $1, $zero, 0 # encoding: [0x00,0x00,0x01,0x24] +# CHECK-MIPS32: mtc1 $1, $f5 # encoding: [0x00,0x28,0x81,0x44] +# CHECK-MIPS32: mtc1 $zero, $f4 # encoding: [0x00,0x20,0x80,0x44] +# CHECK-MIPS32r2: addiu $1, $zero, 0 # encoding: [0x00,0x00,0x01,0x24] +# CHECK-MIPS32r2: mtc1 $zero, $f4 # encoding: [0x00,0x20,0x80,0x44] +# CHECK-MIPS32r2: mthc1 $1, $f4 # encoding: [0x00,0x20,0xe1,0x44] +# CHECK-MIPS64: addiu $1, $zero, 0 # encoding: [0x00,0x00,0x01,0x24] +# CHECK-MIPS64: dmtc1 $1, $f4 # encoding: [0x00,0x20,0xa1,0x44] + +li.d $f4, 0.0 +# CHECK-MIPS32: addiu $1, $zero, 0 # encoding: [0x00,0x00,0x01,0x24] +# CHECK-MIPS32: mtc1 $1, $f5 # encoding: [0x00,0x28,0x81,0x44] +# CHECK-MIPS32: mtc1 $zero, $f4 # encoding: [0x00,0x20,0x80,0x44] +# CHECK-MIPS32r2: addiu $1, $zero, 0 # encoding: [0x00,0x00,0x01,0x24] +# CHECK-MIPS32r2: mtc1 $zero, $f4 # encoding: [0x00,0x20,0x80,0x44] +# CHECK-MIPS32r2: mthc1 $1, $f4 # encoding: [0x00,0x20,0xe1,0x44] +# CHECK-MIPS64: addiu $1, $zero, 0 # encoding: [0x00,0x00,0x01,0x24] +# CHECK-MIPS64: dmtc1 $1, $f4 # encoding: [0x00,0x20,0xa1,0x44] + +li.d $f4, 1.12345 +# CHECK-MIPS32: ldc1 $f4, (%lit4(.rodata))-8($gp) # encoding: [0xf8'A',0xff'A',0x84,0xd7] +# CHECK-MIPS32: # fixup A - offset: 0, value: %lit4(.rodata), kind: fixup_Mips_LITERAL +# CHECK-MIPS32r2: ldc1 $f4, (%lit4(.rodata))-8($gp) # encoding: [0xf8'A',0xff'A',0x84,0xd7] +# CHECK-MIPS32r2: # fixup A - offset: 0, value: %lit4(.rodata), kind: fixup_Mips_LITERAL +# CHECK-MIPS64: ldc1 $f4, (%lit4(.rodata))-8($gp) # encoding: [0xf8'A',0xff'A',0x84,0xd7] +# CHECK-MIPS64: # fixup A - offset: 0, value: %lit4(.rodata), kind: fixup_Mips_LITERAL + + +li.d $f4, 1 +# CHECK-MIPS32: lui $1, 16368 # encoding: [0xf0,0x3f,0x01,0x3c] +# CHECK-MIPS32: mtc1 $1, $f5 # encoding: [0x00,0x28,0x81,0x44] +# CHECK-MIPS32: mtc1 $zero, $f4 # encoding: [0x00,0x20,0x80,0x44] +# CHECK-MIPS32r2: lui $1, 16368 # encoding: [0xf0,0x3f,0x01,0x3c] +# CHECK-MIPS32r2: mtc1 $zero, $f4 # encoding: [0x00,0x20,0x80,0x44] +# CHECK-MIPS32r2: mthc1 $1, $f4 # encoding: [0x00,0x20,0xe1,0x44] +# CHECK-MIPS64: lui $1, 16368 # encoding: [0xf0,0x3f,0x01,0x3c] +# CHECK-MIPS64: dmtc1 $1, $f4 # encoding: [0x00,0x20,0xa1,0x44] + + +li.d $f4, 1.0 +# CHECK-MIPS32: lui $1, 16368 # encoding: [0xf0,0x3f,0x01,0x3c] +# CHECK-MIPS32: mtc1 $1, $f5 # encoding: [0x00,0x28,0x81,0x44] +# CHECK-MIPS32: mtc1 $zero, $f4 # encoding: [0x00,0x20,0x80,0x44] +# CHECK-MIPS32r2: lui $1, 16368 # encoding: [0xf0,0x3f,0x01,0x3c] +# CHECK-MIPS32r2: mtc1 $zero, $f4 # encoding: [0x00,0x20,0x80,0x44] +# CHECK-MIPS32r2: mthc1 $1, $f4 # encoding: [0x00,0x20,0xe1,0x44] +# CHECK-MIPS64: lui $1, 16368 # encoding: [0xf0,0x3f,0x01,0x3c] +# CHECK-MIPS64: dmtc1 $1, $f4 # encoding: [0x00,0x20,0xa1,0x44] + + +li.d $f4, 12345678910 +# CHECK-MIPS32: ldc1 $f4, (%lit4(.rodata))-8($gp) # encoding: [0xf8'A',0xff'A',0x84,0xd7] +# CHECK-MIPS32: # fixup A - offset: 0, value: %lit4(.rodata), kind: fixup_Mips_LITERAL +# CHECK-MIPS32r2: ldc1 $f4, (%lit4(.rodata))-8($gp) # encoding: [0xf8'A',0xff'A',0x84,0xd7] +# CHECK-MIPS32r2: # fixup A - offset: 0, value: %lit4(.rodata), kind: fixup_Mips_LITERAL +# CHECK-MIPS64: ldc1 $f4, (%lit4(.rodata))-8($gp) # encoding: [0xf8'A',0xff'A',0x84,0xd7] +# CHECK-MIPS64: # fixup A - offset: 0, value: %lit4(.rodata), kind: fixup_Mips_LITERAL + +li.d $f4, 12345678910.0 +# CHECK-MIPS32: ldc1 $f4, (%lit4(.rodata))-8($gp) # encoding: [0xf8'A',0xff'A',0x84,0xd7] +# CHECK-MIPS32: # fixup A - offset: 0, value: %lit4(.rodata), kind: fixup_Mips_LITERAL +# CHECK-MIPS32r2: ldc1 $f4, (%lit4(.rodata))-8($gp) # encoding: [0xf8'A',0xff'A',0x84,0xd7] +# CHECK-MIPS32r2: # fixup A - offset: 0, value: %lit4(.rodata), kind: fixup_Mips_LITERAL +# CHECK-MIPS64: ldc1 $f4, (%lit4(.rodata))-8($gp) # encoding: [0xf8'A',0xff'A',0x84,0xd7] +# CHECK-MIPS64: # fixup A - offset: 0, value: %lit4(.rodata), kind: fixup_Mips_LITERAL + + +li.d $f4, 0.4 +# CHECK-MIPS32: ldc1 $f4, (%lit4(.rodata))-8($gp) # encoding: [0xf8'A',0xff'A',0x84,0xd7] +# CHECK-MIPS32: # fixup A - offset: 0, value: %lit4(.rodata), kind: fixup_Mips_LITERAL +# CHECK-MIPS32r2: ldc1 $f4, (%lit4(.rodata))-8($gp) # encoding: [0xf8'A',0xff'A',0x84,0xd7] +# CHECK-MIPS32r2: # fixup A - offset: 0, value: %lit4(.rodata), kind: fixup_Mips_LITERAL +# CHECK-MIPS64: ldc1 $f4, (%lit4(.rodata))-8($gp) # encoding: [0xf8'A',0xff'A',0x84,0xd7] +# CHECK-MIPS64: # fixup A - offset: 0, value: %lit4(.rodata), kind: fixup_Mips_LITERAL + +li.d $f4, 1.5 +# CHECK-MIPS32: lui $1, 16376 # encoding: [0xf8,0x3f,0x01,0x3c] +# CHECK-MIPS32: mtc1 $1, $f5 # encoding: [0x00,0x28,0x81,0x44] +# CHECK-MIPS32: mtc1 $zero, $f4 # encoding: [0x00,0x20,0x80,0x44] +# CHECK-MIPS32r2: lui $1, 16376 # encoding: [0xf8,0x3f,0x01,0x3c] +# CHECK-MIPS32r2: mtc1 $zero, $f4 # encoding: [0x00,0x20,0x80,0x44] +# CHECK-MIPS32r2: mthc1 $1, $f4 # encoding: [0x00,0x20,0xe1,0x44] +# CHECK-MIPS64: lui $1, 16376 # encoding: [0xf8,0x3f,0x01,0x3c] +# CHECK-MIPS64: dmtc1 $1, $f4 # encoding: [0x00,0x20,0xa1,0x44] + +li.d $f4, 2.5 +# CHECK-MIPS32: lui $1, 16388 # encoding: [0x04,0x40,0x01,0x3c] +# CHECK-MIPS32: mtc1 $1, $f5 # encoding: [0x00,0x28,0x81,0x44] +# CHECK-MIPS32: mtc1 $zero, $f4 # encoding: [0x00,0x20,0x80,0x44] +# CHECK-MIPS32r2: lui $1, 16388 # encoding: [0x04,0x40,0x01,0x3c] +# CHECK-MIPS32r2: mtc1 $zero, $f4 # encoding: [0x00,0x20,0x80,0x44] +# CHECK-MIPS32r2: mthc1 $1, $f4 # encoding: [0x00,0x20,0xe1,0x44] +# CHECK-MIPS64: lui $1, 16388 # encoding: [0x04,0x40,0x01,0x3c] +# CHECK-MIPS64: dmtc1 $1, $f4 # encoding: [0x00,0x20,0xa1,0x44] + +li.d $f4, 2.515625 +# CHECK-MIPS32: ldc1 $f4, (%lit4(.rodata))-8($gp) # encoding: [0xf8'A',0xff'A',0x84,0xd7] +# CHECK-MIPS32: # fixup A - offset: 0, value: %lit4(.rodata), kind: fixup_Mips_LITERAL +# CHECK-MIPS32r2: ldc1 $f4, (%lit4(.rodata))-8($gp) # encoding: [0xf8'A',0xff'A',0x84,0xd7] +# CHECK-MIPS32r2: # fixup A - offset: 0, value: %lit4(.rodata), kind: fixup_Mips_LITERAL +# CHECK-MIPS64: ldc1 $f4, (%lit4(.rodata))-8($gp) # encoding: [0xf8'A',0xff'A',0x84,0xd7] +# CHECK-MIPS64: # fixup A - offset: 0, value: %lit4(.rodata), kind: fixup_Mips_LITERAL + +li.d $f4, 12345678910.12345678910 +# CHECK-MIPS32: ldc1 $f4, (%lit4(.rodata))-8($gp) # encoding: [0xf8'A',0xff'A',0x84,0xd7] +# CHECK-MIPS32: # fixup A - offset: 0, value: %lit4(.rodata), kind: fixup_Mips_LITERAL +# CHECK-MIPS32r2: ldc1 $f4, (%lit4(.rodata))-8($gp) # encoding: [0xf8'A',0xff'A',0x84,0xd7] +# CHECK-MIPS32r2: # fixup A - offset: 0, value: %lit4(.rodata), kind: fixup_Mips_LITERAL +# CHECK-MIPS64: ldc1 $f4, (%lit4(.rodata))-8($gp) # encoding: [0xf8'A',0xff'A',0x84,0xd7] +# CHECK-MIPS64: # fixup A - offset: 0, value: %lit4(.rodata), kind: fixup_Mips_LITERAL + +li.d $f4, 12345678910123456789.12345678910 +# CHECK-MIPS32: ldc1 $f4, (%lit4(.rodata))-8($gp) # encoding: [0xf8'A',0xff'A',0x84,0xd7] +# CHECK-MIPS32: # fixup A - offset: 0, value: %lit4(.rodata), kind: fixup_Mips_LITERAL +# CHECK-MIPS32r2: ldc1 $f4, (%lit4(.rodata))-8($gp) # encoding: [0xf8'A',0xff'A',0x84,0xd7] +# CHECK-MIPS32r2: # fixup A - offset: 0, value: %lit4(.rodata), kind: fixup_Mips_LITERAL +# CHECK-MIPS64: ldc1 $f4, (%lit4(.rodata))-8($gp) # encoding: [0xf8'A',0xff'A',0x84,0xd7] +# CHECK-MIPS64: # fixup A - offset: 0, value: %lit4(.rodata), kind: fixup_Mips_LITERAL Index: test/MC/Mips/macro-li.s =================================================================== --- test/MC/Mips/macro-li.s +++ test/MC/Mips/macro-li.s @@ -1,75 +0,0 @@ -# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 | \ -# RUN: FileCheck %s -# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 | \ -# RUN: FileCheck %s -# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r2 | \ -# RUN: FileCheck %s -# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 | \ -# RUN: FileCheck %s - -li $5, 0x00000001 # CHECK: addiu $5, $zero, 1 # encoding: [0x24,0x05,0x00,0x01] -li $5, 0x00000002 # CHECK: addiu $5, $zero, 2 # encoding: [0x24,0x05,0x00,0x02] -li $5, 0x00004000 # CHECK: addiu $5, $zero, 16384 # encoding: [0x24,0x05,0x40,0x00] -li $5, 0x00008000 # CHECK: ori $5, $zero, 32768 # encoding: [0x34,0x05,0x80,0x00] -li $5, 0xffffffff # CHECK: addiu $5, $zero, -1 # encoding: [0x24,0x05,0xff,0xff] -li $5, 0xfffffffe # CHECK: addiu $5, $zero, -2 # encoding: [0x24,0x05,0xff,0xfe] -li $5, 0xffffc000 # CHECK: addiu $5, $zero, -16384 # encoding: [0x24,0x05,0xc0,0x00] -li $5, 0xffff8000 # CHECK: addiu $5, $zero, -32768 # encoding: [0x24,0x05,0x80,0x00] - -li $5, 0x00010000 # CHECK: lui $5, 1 # encoding: [0x3c,0x05,0x00,0x01] -li $5, 0x00020000 # CHECK: lui $5, 2 # encoding: [0x3c,0x05,0x00,0x02] -li $5, 0x40000000 # CHECK: lui $5, 16384 # encoding: [0x3c,0x05,0x40,0x00] -li $5, 0x80000000 # CHECK: lui $5, 32768 # encoding: [0x3c,0x05,0x80,0x00] -li $5, 0xffff0000 # CHECK: lui $5, 65535 # encoding: [0x3c,0x05,0xff,0xff] -li $5, 0xfffe0000 # CHECK: lui $5, 65534 # encoding: [0x3c,0x05,0xff,0xfe] -li $5, 0xc0000000 # CHECK: lui $5, 49152 # encoding: [0x3c,0x05,0xc0,0x00] -li $5, 0x80000000 # CHECK: lui $5, 32768 # encoding: [0x3c,0x05,0x80,0x00] - -li $5, 0x00010001 # CHECK: lui $5, 1 # encoding: [0x3c,0x05,0x00,0x01] - # CHECK: ori $5, $5, 1 # encoding: [0x34,0xa5,0x00,0x01] -li $5, 0x00020001 # CHECK: lui $5, 2 # encoding: [0x3c,0x05,0x00,0x02] - # CHECK: ori $5, $5, 1 # encoding: [0x34,0xa5,0x00,0x01] -li $5, 0x40000001 # CHECK: lui $5, 16384 # encoding: [0x3c,0x05,0x40,0x00] - # CHECK: ori $5, $5, 1 # encoding: [0x34,0xa5,0x00,0x01] -li $5, 0x80000001 # CHECK: lui $5, 32768 # encoding: [0x3c,0x05,0x80,0x00] - # CHECK: ori $5, $5, 1 # encoding: [0x34,0xa5,0x00,0x01] -li $5, 0x00010002 # CHECK: lui $5, 1 # encoding: [0x3c,0x05,0x00,0x01] - # CHECK: ori $5, $5, 2 # encoding: [0x34,0xa5,0x00,0x02] -li $5, 0x00020002 # CHECK: lui $5, 2 # encoding: [0x3c,0x05,0x00,0x02] - # CHECK: ori $5, $5, 2 # encoding: [0x34,0xa5,0x00,0x02] -li $5, 0x40000002 # CHECK: lui $5, 16384 # encoding: [0x3c,0x05,0x40,0x00] - # CHECK: ori $5, $5, 2 # encoding: [0x34,0xa5,0x00,0x02] -li $5, 0x80000002 # CHECK: lui $5, 32768 # encoding: [0x3c,0x05,0x80,0x00] - # CHECK: ori $5, $5, 2 # encoding: [0x34,0xa5,0x00,0x02] -li $5, 0x00014000 # CHECK: lui $5, 1 # encoding: [0x3c,0x05,0x00,0x01] - # CHECK: ori $5, $5, 16384 # encoding: [0x34,0xa5,0x40,0x00] -li $5, 0x00024000 # CHECK: lui $5, 2 # encoding: [0x3c,0x05,0x00,0x02] - # CHECK: ori $5, $5, 16384 # encoding: [0x34,0xa5,0x40,0x00] -li $5, 0x40004000 # CHECK: lui $5, 16384 # encoding: [0x3c,0x05,0x40,0x00] - # CHECK: ori $5, $5, 16384 # encoding: [0x34,0xa5,0x40,0x00] -li $5, 0x80004000 # CHECK: lui $5, 32768 # encoding: [0x3c,0x05,0x80,0x00] - # CHECK: ori $5, $5, 16384 # encoding: [0x34,0xa5,0x40,0x00] -li $5, 0x00018000 # CHECK: lui $5, 1 # encoding: [0x3c,0x05,0x00,0x01] - # CHECK: ori $5, $5, 32768 # encoding: [0x34,0xa5,0x80,0x00] -li $5, 0x00028000 # CHECK: lui $5, 2 # encoding: [0x3c,0x05,0x00,0x02] - # CHECK: ori $5, $5, 32768 # encoding: [0x34,0xa5,0x80,0x00] -li $5, 0x40008000 # CHECK: lui $5, 16384 # encoding: [0x3c,0x05,0x40,0x00] - # CHECK: ori $5, $5, 32768 # encoding: [0x34,0xa5,0x80,0x00] -li $5, 0x80008000 # CHECK: lui $5, 32768 # encoding: [0x3c,0x05,0x80,0x00] - # CHECK: ori $5, $5, 32768 # encoding: [0x34,0xa5,0x80,0x00] -li $5, 0xffff4000 # CHECK: lui $5, 65535 # encoding: [0x3c,0x05,0xff,0xff] - # CHECK: ori $5, $5, 16384 # encoding: [0x34,0xa5,0x40,0x00] -li $5, 0xfffe8000 # CHECK: lui $5, 65534 # encoding: [0x3c,0x05,0xff,0xfe] - # CHECK: ori $5, $5, 32768 # encoding: [0x34,0xa5,0x80,0x00] -li $5, 0xc0008000 # CHECK: lui $5, 49152 # encoding: [0x3c,0x05,0xc0,0x00] - # CHECK: ori $5, $5, 32768 # encoding: [0x34,0xa5,0x80,0x00] -li $5, 0x80008000 # CHECK: lui $5, 32768 # encoding: [0x3c,0x05,0x80,0x00] - # CHECK: ori $5, $5, 32768 # encoding: [0x34,0xa5,0x80,0x00] -li $4, ~0xffffffff # CHECK: addiu $4, $zero, 0 # encoding: [0x24,0x04,0x00,0x00] -li $4, ~0x80000001 # CHECK: lui $4, 32767 # encoding: [0x3c,0x04,0x7f,0xff] - # CHECK: ori $4, $4, 65534 # encoding: [0x34,0x84,0xff,0xfe] -li $4, ~0x80000000 # CHECK: lui $4, 32767 # encoding: [0x3c,0x04,0x7f,0xff] - # CHECK: ori $4, $4, 65535 # encoding: [0x34,0x84,0xff,0xff] -li $4, ~0x7fffffff # CHECK: lui $4, 32768 # encoding: [0x3c,0x04,0x80,0x00] -li $4, ~0x00000001 # CHECK: addiu $4, $zero, -2 # encoding: [0x24,0x04,0xff,0xfe] -li $4, ~0x00000000 # CHECK: addiu $4, $zero, -1 # encoding: [0x24,0x04,0xff,0xff] Index: test/MC/Mips/macro-li.s.s =================================================================== --- test/MC/Mips/macro-li.s.s +++ test/MC/Mips/macro-li.s.s @@ -0,0 +1,102 @@ +# RUN: llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips32 -show-encoding | FileCheck %s +# RUN: llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips64 -show-encoding | FileCheck %s + +li.s $4, 0 +# CHECK: addiu $4, $zero, 0 # encoding: [0x00,0x00,0x04,0x24] + +li.s $4, 0.0 +# CHECK: addiu $4, $zero, 0 # encoding: [0x00,0x00,0x04,0x24] + +li.s $4, 1.12345 +# CHECK: lui $4, 16271 # encoding: [0x8f,0x3f,0x04,0x3c] +# CHECK: ori $4, $4, 52534 # encoding: [0x36,0xcd,0x84,0x34] + +li.s $4, 1 +# CHECK: lui $4, 16256 # encoding: [0x80,0x3f,0x04,0x3c] + +li.s $4, 1.0 +# CHECK: lui $4, 16256 # encoding: [0x80,0x3f,0x04,0x3c] + +li.s $4, 12345678910 +# CHECK: lui $4, 20535 # encoding: [0x37,0x50,0x04,0x3c] +# CHECK: ori $4, $4, 63239 # encoding: [0x07,0xf7,0x84,0x34] + +li.s $4, 12345678910.0 +# CHECK: lui $4, 20535 # encoding: [0x37,0x50,0x04,0x3c] +# CHECK: ori $4, $4, 63239 # encoding: [0x07,0xf7,0x84,0x34] + +li.s $4, 0.4 +# CHECK: lui $4, 16076 # encoding: [0xcc,0x3e,0x04,0x3c] +# CHECK: ori $4, $4, 52429 # encoding: [0xcd,0xcc,0x84,0x34] + +li.s $4, 1.5 +# CHECK: lui $4, 16320 # encoding: [0xc0,0x3f,0x04,0x3c] + +li.s $4, 12345678910.12345678910 +# CHECK: lui $4, 20535 # encoding: [0x37,0x50,0x04,0x3c] +# CHECK: ori $4, $4, 63239 # encoding: [0x07,0xf7,0x84,0x34] + +li.s $4, 12345678910123456789.12345678910 +# CHECK: lui $4, 24363 # encoding: [0x2b,0x5f,0x04,0x3c] +# CHECK: ori $4, $4, 21674 # encoding: [0xaa,0x54,0x84,0x34] + +li.s $f4, 0 +# CHECK: addiu $1, $zero, 0 # encoding: [0x00,0x00,0x01,0x24] +# CHECK: mtc1 $1, $f4 # encoding: [0x00,0x20,0x81,0x44] + +li.s $f4, 0.0 +# CHECK: addiu $1, $zero, 0 # encoding: [0x00,0x00,0x01,0x24] +# CHECK: mtc1 $1, $f4 # encoding: [0x00,0x20,0x81,0x44] + +li.s $f4, 1.12345 +# CHECK: .section .rodata,"a",@progbits +# CHECK: .4byte 1066388790 +# CHECK: .text +# CHECK: lwc1 $f4, (%lit4(.rodata))-4($gp) # encoding: [0xfc'A',0xff'A',0x84,0xc7] +# CHECK: # fixup A - offset: 0, value: %lit4(.rodata), kind: fixup_Mips_LITERAL +li.s $f4, 1 +# CHECK: lui $1, 16256 # encoding: [0x80,0x3f,0x01,0x3c] +# CHECK: mtc1 $1, $f4 # encoding: [0x00,0x20,0x81,0x44] + +li.s $f4, 1.0 +# CHECK: lui $1, 16256 # encoding: [0x80,0x3f,0x01,0x3c] +# CHECK: mtc1 $1, $f4 # encoding: [0x00,0x20,0x81,0x44] + +li.s $f4, 12345678910 +# CHECK: .section .rodata,"a",@progbits +# CHECK: .4byte 1345844999 +# CHECK: .text +# CHECK: lwc1 $f4, (%lit4(.rodata))-4($gp) # encoding: [0xfc'A',0xff'A',0x84,0xc7] +# CHECK: # fixup A - offset: 0, value: %lit4(.rodata), kind: fixup_Mips_LITERAL + +li.s $f4, 12345678910.0 +# CHECK: .section .rodata,"a",@progbits +# CHECK: .4byte 1345844999 +# CHECK: .text +# CHECK: lwc1 $f4, (%lit4(.rodata))-4($gp) # encoding: [0xfc'A',0xff'A',0x84,0xc7] +# CHECK: # fixup A - offset: 0, value: %lit4(.rodata), kind: fixup_Mips_LITERAL + +li.s $f4, 0.4 +# CHECK: .section .rodata,"a",@progbits +# CHECK: .4byte 1053609165 +# CHECK: .text +# CHECK: lwc1 $f4, (%lit4(.rodata))-4($gp) # encoding: [0xfc'A',0xff'A',0x84,0xc7] +# CHECK: # fixup A - offset: 0, value: %lit4(.rodata), kind: fixup_Mips_LITERAL + +li.s $f4, 1.5 +# CHECK: lui $1, 16320 # encoding: [0xc0,0x3f,0x01,0x3c] +# CHECK: mtc1 $1, $f4 # encoding: [0x00,0x20,0x81,0x44] + +li.s $f4, 12345678910.12345678910 +# CHECK: .section .rodata,"a",@progbits +# CHECK: .4byte 1345844999 +# CHECK: .text +# CHECK: lwc1 $f4, (%lit4(.rodata))-4($gp) # encoding: [0xfc'A',0xff'A',0x84,0xc7] +# CHECK: # fixup A - offset: 0, value: %lit4(.rodata), kind: fixup_Mips_LITERAL + +li.s $f4, 12345678910123456789.12345678910 +# CHECK: .section .rodata,"a",@progbits +# CHECK: .4byte 1596675242 +# CHECK: .text +# CHECK: lwc1 $f4, (%lit4(.rodata))-4($gp) # encoding: [0xfc'A',0xff'A',0x84,0xc7] +# CHECK: # fixup A - offset: 0, value: %lit4(.rodata), kind: fixup_Mips_LITERAL