Index: lib/Target/ARM/ARMFrameLowering.h =================================================================== --- lib/Target/ARM/ARMFrameLowering.h +++ lib/Target/ARM/ARMFrameLowering.h @@ -57,6 +57,11 @@ void adjustForSegmentedStacks(MachineFunction &MF, MachineBasicBlock &MBB) const override; + /// Returns true if the target will correctly handle shrink wrapping. + bool enableShrinkWrapping(const MachineFunction &MF) const override { + return true; + } + private: void emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector &CSI, unsigned StmOpc, Index: test/CodeGen/ARM/call-tc.ll =================================================================== --- test/CodeGen/ARM/call-tc.ll +++ test/CodeGen/ARM/call-tc.ll @@ -83,9 +83,11 @@ define void @t7() nounwind { entry: ; CHECKT2D-LABEL: t7: -; CHECKT2D: blxeq _foo -; CHECKT2D-NEXT: pop.w -; CHECKT2D-NEXT: b.w _foo +; CHECKT2D: it ne +; CHECKT2D-NEXT: bne.w _foo +; CHECKT2D-NEXT: push +; CHECKT2D-NEXT: mov r7, sp +; CHECKT2D-NEXT: blx _foo br i1 undef, label %bb, label %bb1.lr.ph bb1.lr.ph: Index: test/CodeGen/ARM/fold-stack-adjust.ll =================================================================== --- test/CodeGen/ARM/fold-stack-adjust.ll +++ test/CodeGen/ARM/fold-stack-adjust.ll @@ -1,4 +1,6 @@ -; RUN: llc -mtriple=thumbv7-apple-none-macho < %s | FileCheck %s +; Disable shrink-wrapping on the first test otherwise we wouldn't +; exerce the path for PR18136. +; RUN: llc -mtriple=thumbv7-apple-none-macho < %s -enable-shrink-wrap=false | FileCheck %s ; RUN: llc -mtriple=thumbv6m-apple-none-macho -disable-fp-elim < %s | FileCheck %s --check-prefix=CHECK-T1 ; RUN: llc -mtriple=thumbv7-apple-darwin-ios -disable-fp-elim < %s | FileCheck %s --check-prefix=CHECK-IOS ; RUN: llc -mtriple=thumbv7--linux-gnueabi -disable-fp-elim < %s | FileCheck %s --check-prefix=CHECK-LINUX Index: test/CodeGen/ARM/ifcvt5.ll =================================================================== --- test/CodeGen/ARM/ifcvt5.ll +++ test/CodeGen/ARM/ifcvt5.ll @@ -13,10 +13,10 @@ define i32 @t1(i32 %a, i32 %b) { ; A8-LABEL: t1: -; A8: poplt {r7, pc} +; A8: bxlt lr ; SWIFT-LABEL: t1: -; SWIFT: pop {r7, pc} +; SWIFT: bxlt lr ; SWIFT: pop {r7, pc} entry: %tmp1 = icmp sgt i32 %a, 10 ; [#uses=1] Index: test/CodeGen/ARM/ifcvt6.ll =================================================================== --- test/CodeGen/ARM/ifcvt6.ll +++ test/CodeGen/ARM/ifcvt6.ll @@ -3,7 +3,7 @@ define void @foo(i32 %X, i32 %Y) { entry: ; CHECK: cmpne -; CHECK: pophi +; CHECK: bxhi lr %tmp1 = icmp ult i32 %X, 4 ; [#uses=1] %tmp4 = icmp eq i32 %Y, 0 ; [#uses=1] %tmp7 = or i1 %tmp4, %tmp1 ; [#uses=1] Index: test/CodeGen/ARM/ifcvt8.ll =================================================================== --- test/CodeGen/ARM/ifcvt8.ll +++ test/CodeGen/ARM/ifcvt8.ll @@ -5,7 +5,9 @@ declare void @abort() define fastcc void @t(%struct.SString* %word, i8 signext %c) { -; CHECK: popne +; CHECK-NOT: pop +; CHECK: bxne +; CHECK-NOT: pop entry: %tmp1 = icmp eq %struct.SString* %word, null ; [#uses=1] br i1 %tmp1, label %cond_true, label %cond_false Index: test/CodeGen/ARM/machine-cse-cmp.ll =================================================================== --- test/CodeGen/ARM/machine-cse-cmp.ll +++ test/CodeGen/ARM/machine-cse-cmp.ll @@ -27,7 +27,7 @@ entry: ; CHECK-LABEL: f2: ; CHECK: cmp -; CHECK: poplt +; CHECK: bxlt ; CHECK-NOT: cmp ; CHECK: movle %0 = load i32, i32* @foo, align 4 Index: test/CodeGen/ARM/thumb-alignment.ll =================================================================== --- test/CodeGen/ARM/thumb-alignment.ll +++ test/CodeGen/ARM/thumb-alignment.ll @@ -23,7 +23,7 @@ ; CHECK: .globl baz ; CHECK-NEXT: .align 2 -; CHECK: adr.w +; CHECK: tbb define i32 @baz() { %1 = load i32, i32* @c, align 4 switch i32 %1, label %7 [ Index: test/CodeGen/Thumb2/ifcvt-compare.ll =================================================================== --- test/CodeGen/Thumb2/ifcvt-compare.ll +++ test/CodeGen/Thumb2/ifcvt-compare.ll @@ -19,7 +19,8 @@ define void @f1(i32 %x) optsize { ; CHECK-LABEL: f1: ; CHECK: cmp r0, #1 - ; CHECK: it eq + ; CHECK: it ne + ; CHECK-NEXT: bxne lr %p = icmp eq i32 %x, 1 br i1 %p, label %t, label %f @@ -34,7 +35,8 @@ define void @f2(i32 %x) { ; CHECK-LABEL: f2: ; CHECK: cmp r0, #0 - ; CHECK: it eq + ; CHECK: it ne + ; CHECK-NEXT: bxne lr %p = icmp eq i32 %x, 0 br i1 %p, label %t, label %f Index: test/CodeGen/Thumb2/thumb2-ifcvt1.ll =================================================================== --- test/CodeGen/Thumb2/thumb2-ifcvt1.ll +++ test/CodeGen/Thumb2/thumb2-ifcvt1.ll @@ -72,9 +72,10 @@ define void @t3(i32 %a, i32 %b) nounwind { entry: ; CHECK-LABEL: t3: -; CHECK: itt ge -; CHECK: movge r0, r1 -; CHECK: blge {{_?}}foo +; CHECK: it lt +; CHECK-NEXT: bxlt lr +; CHECK: mov r0, r1 +; CHECK: bl {{_?}}foo %tmp1 = icmp sgt i32 %a, 10 ; [#uses=1] br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock Index: test/CodeGen/Thumb2/thumb2-ifcvt2.ll =================================================================== --- test/CodeGen/Thumb2/thumb2-ifcvt2.ll +++ test/CodeGen/Thumb2/thumb2-ifcvt2.ll @@ -8,7 +8,7 @@ ; CHECK: it ne ; CHECK: cmpne ; CHECK: it hi -; CHECK: pophi {r7, pc} +; CHECK: bxhi lr %tmp1 = icmp ult i32 %X, 4 ; [#uses=1] %tmp4 = icmp eq i32 %Y, 0 ; [#uses=1] %tmp7 = or i1 %tmp4, %tmp1 ; [#uses=1] @@ -69,7 +69,7 @@ entry: ; CHECK-LABEL: t1: ; CHECK: it ne -; CHECK: popne {r7, pc} +; CHECK: bxne lr %tmp1 = icmp eq %struct.SString* %word, null ; [#uses=1] br i1 %tmp1, label %cond_true, label %cond_false Index: test/CodeGen/Thumb2/v8_IT_5.ll =================================================================== --- test/CodeGen/Thumb2/v8_IT_5.ll +++ test/CodeGen/Thumb2/v8_IT_5.ll @@ -9,7 +9,7 @@ ; CHECK-NEXT: b ; CHECK: [[JUMPTARGET]]:{{.*}}%if.else173 ; CHECK-NEXT: mov.w -; CHECK-NEXT: pop +; CHECK-NEXT: bx lr ; CHECK-NEXT: %if.else145 ; CHECK-NEXT: mov.w