Index: lib/Target/X86/X86.td =================================================================== --- lib/Target/X86/X86.td +++ lib/Target/X86/X86.td @@ -31,6 +31,9 @@ // X86 Subtarget features //===----------------------------------------------------------------------===// +def FeatureX87 : SubtargetFeature<"x87","HasX87", "true", + "Enable X87 float instructions">; + def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true", "Enable conditional move instructions">; @@ -234,37 +237,38 @@ class Proc Features> : ProcessorModel; -def : Proc<"generic", [FeatureSlowUAMem16]>; -def : Proc<"i386", [FeatureSlowUAMem16]>; -def : Proc<"i486", [FeatureSlowUAMem16]>; -def : Proc<"i586", [FeatureSlowUAMem16]>; -def : Proc<"pentium", [FeatureSlowUAMem16]>; -def : Proc<"pentium-mmx", [FeatureSlowUAMem16, FeatureMMX]>; -def : Proc<"i686", [FeatureSlowUAMem16]>; -def : Proc<"pentiumpro", [FeatureSlowUAMem16, FeatureCMOV]>; -def : Proc<"pentium2", [FeatureSlowUAMem16, FeatureMMX, FeatureCMOV, - FeatureFXSR]>; -def : Proc<"pentium3", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1, - FeatureFXSR]>; -def : Proc<"pentium3m", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1, - FeatureFXSR, FeatureSlowBTMem]>; -def : Proc<"pentium-m", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2, - FeatureFXSR, FeatureSlowBTMem]>; -def : Proc<"pentium4", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2, - FeatureFXSR]>; -def : Proc<"pentium4m", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2, - FeatureFXSR, FeatureSlowBTMem]>; +def : Proc<"generic", [FeatureX87, FeatureSlowUAMem16]>; +def : Proc<"i386", [FeatureX87, FeatureSlowUAMem16]>; +def : Proc<"i486", [FeatureX87, FeatureSlowUAMem16]>; +def : Proc<"i586", [FeatureX87, FeatureSlowUAMem16]>; +def : Proc<"pentium", [FeatureX87, FeatureSlowUAMem16]>; +def : Proc<"pentium-mmx", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>; +def : Proc<"i686", [FeatureX87, FeatureSlowUAMem16]>; +def : Proc<"pentiumpro", [FeatureX87, FeatureSlowUAMem16, FeatureCMOV]>; +def : Proc<"pentium2", [FeatureX87, FeatureSlowUAMem16, FeatureMMX, + FeatureCMOV, FeatureFXSR]>; +def : Proc<"pentium3", [FeatureX87, FeatureSlowUAMem16, FeatureMMX, + FeatureSSE1, FeatureFXSR]>; +def : Proc<"pentium3m", [FeatureX87, FeatureSlowUAMem16, FeatureMMX, + FeatureSSE1, FeatureFXSR, FeatureSlowBTMem]>; +def : Proc<"pentium-m", [FeatureX87, FeatureSlowUAMem16, FeatureMMX, + FeatureSSE2, FeatureFXSR, FeatureSlowBTMem]>; +def : Proc<"pentium4", [FeatureX87, FeatureSlowUAMem16, FeatureMMX, + FeatureSSE2, FeatureFXSR]>; +def : Proc<"pentium4m", [FeatureX87, FeatureSlowUAMem16, FeatureMMX, + FeatureSSE2, FeatureFXSR, FeatureSlowBTMem]>; // Intel Core Duo. def : ProcessorModel<"yonah", SandyBridgeModel, - [FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, FeatureFXSR, - FeatureSlowBTMem]>; + [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, + FeatureFXSR, FeatureSlowBTMem]>; // NetBurst. def : Proc<"prescott", - [FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, FeatureFXSR, - FeatureSlowBTMem]>; + [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, + FeatureFXSR, FeatureSlowBTMem]>; def : Proc<"nocona", [ + FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, @@ -275,6 +279,7 @@ // Intel Core 2 Solo/Duo. def : ProcessorModel<"core2", SandyBridgeModel, [ + FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSSE3, @@ -284,6 +289,7 @@ FeatureLAHFSAHF ]>; def : ProcessorModel<"penryn", SandyBridgeModel, [ + FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE41, @@ -296,6 +302,7 @@ // Atom CPUs. class BonnellProc : ProcessorModel : ProcessorModel : ProcessorModel : ProcessorModel : ProcessorModel; // Legacy alias. class IvyBridgeProc : ProcessorModel; // Legacy alias. class HaswellProc : ProcessorModel; // Legacy alias. class BroadwellProc : ProcessorModel : ProcessorModel : ProcessorModel; // Legacy alias. class CannonlakeProc : ProcessorModel; -def : Proc<"k6-2", [FeatureSlowUAMem16, Feature3DNow]>; -def : Proc<"k6-3", [FeatureSlowUAMem16, Feature3DNow]>; -def : Proc<"athlon", [FeatureSlowUAMem16, Feature3DNowA, +def : Proc<"k6", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>; +def : Proc<"k6-2", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>; +def : Proc<"k6-3", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>; +def : Proc<"athlon", [FeatureX87, FeatureSlowUAMem16, Feature3DNowA, FeatureSlowBTMem, FeatureSlowSHLD]>; -def : Proc<"athlon-tbird", [FeatureSlowUAMem16, Feature3DNowA, +def : Proc<"athlon-tbird", [FeatureX87, FeatureSlowUAMem16, Feature3DNowA, FeatureSlowBTMem, FeatureSlowSHLD]>; -def : Proc<"athlon-4", [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA, - FeatureFXSR, FeatureSlowBTMem, FeatureSlowSHLD]>; -def : Proc<"athlon-xp", [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA, - FeatureFXSR, FeatureSlowBTMem, FeatureSlowSHLD]>; -def : Proc<"athlon-mp", [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA, - FeatureFXSR, FeatureSlowBTMem, FeatureSlowSHLD]>; -def : Proc<"k8", [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA, - FeatureFXSR, Feature64Bit, FeatureSlowBTMem, - FeatureSlowSHLD]>; -def : Proc<"opteron", [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA, - FeatureFXSR, Feature64Bit, FeatureSlowBTMem, - FeatureSlowSHLD]>; -def : Proc<"athlon64", [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA, - FeatureFXSR, Feature64Bit, FeatureSlowBTMem, +def : Proc<"athlon-4", [FeatureX87, FeatureSlowUAMem16, FeatureSSE1, + Feature3DNowA, FeatureFXSR, FeatureSlowBTMem, FeatureSlowSHLD]>; -def : Proc<"athlon-fx", [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA, - FeatureFXSR, Feature64Bit, FeatureSlowBTMem, +def : Proc<"athlon-xp", [FeatureX87, FeatureSlowUAMem16, FeatureSSE1, + Feature3DNowA, FeatureFXSR, FeatureSlowBTMem, FeatureSlowSHLD]>; -def : Proc<"k8-sse3", [FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA, - FeatureFXSR, FeatureCMPXCHG16B, FeatureSlowBTMem, +def : Proc<"athlon-mp", [FeatureX87, FeatureSlowUAMem16, FeatureSSE1, + Feature3DNowA, FeatureFXSR, FeatureSlowBTMem, FeatureSlowSHLD]>; -def : Proc<"opteron-sse3", [FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA, - FeatureFXSR, FeatureCMPXCHG16B, FeatureSlowBTMem, - FeatureSlowSHLD]>; -def : Proc<"athlon64-sse3", [FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA, - FeatureFXSR, FeatureCMPXCHG16B, FeatureSlowBTMem, - FeatureSlowSHLD]>; -def : Proc<"amdfam10", [FeatureSSE4A, Feature3DNowA, FeatureFXSR, - FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT, - FeatureSlowBTMem, FeatureSlowSHLD, FeatureLAHFSAHF]>; -def : Proc<"barcelona", [FeatureSSE4A, Feature3DNowA, FeatureFXSR, - FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT, - FeatureSlowBTMem, FeatureSlowSHLD, FeatureLAHFSAHF]>; +def : Proc<"k8", [FeatureX87, FeatureSlowUAMem16, FeatureSSE2, + Feature3DNowA, FeatureFXSR, Feature64Bit, + FeatureSlowBTMem, FeatureSlowSHLD]>; +def : Proc<"opteron", [FeatureX87, FeatureSlowUAMem16, FeatureSSE2, + Feature3DNowA, FeatureFXSR, Feature64Bit, + FeatureSlowBTMem, FeatureSlowSHLD]>; +def : Proc<"athlon64", [FeatureX87, FeatureSlowUAMem16, FeatureSSE2, + Feature3DNowA, FeatureFXSR, Feature64Bit, + FeatureSlowBTMem, FeatureSlowSHLD]>; +def : Proc<"athlon-fx", [FeatureX87, FeatureSlowUAMem16, FeatureSSE2, + Feature3DNowA, FeatureFXSR, Feature64Bit, + FeatureSlowBTMem, FeatureSlowSHLD]>; +def : Proc<"k8-sse3", [FeatureX87, FeatureSlowUAMem16, FeatureSSE3, + Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B, + FeatureSlowBTMem, FeatureSlowSHLD]>; +def : Proc<"opteron-sse3", [FeatureX87, FeatureSlowUAMem16, FeatureSSE3, + Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B, + FeatureSlowBTMem, FeatureSlowSHLD]>; +def : Proc<"athlon64-sse3", [FeatureX87, FeatureSlowUAMem16, FeatureSSE3, + Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B, + FeatureSlowBTMem, FeatureSlowSHLD]>; +def : Proc<"amdfam10", [FeatureX87, FeatureSSE4A, Feature3DNowA, + FeatureFXSR, FeatureCMPXCHG16B, FeatureLZCNT, + FeaturePOPCNT, FeatureSlowBTMem, FeatureSlowSHLD, + FeatureLAHFSAHF]>; +def : Proc<"barcelona", [FeatureX87, FeatureSSE4A, Feature3DNowA, + FeatureFXSR, FeatureCMPXCHG16B, FeatureLZCNT, + FeaturePOPCNT, FeatureSlowBTMem, FeatureSlowSHLD, + FeatureLAHFSAHF]>; // Bobcat def : Proc<"btver1", [ + FeatureX87, FeatureMMX, FeatureSSSE3, FeatureSSE4A, @@ -623,6 +646,7 @@ // Jaguar def : ProcessorModel<"btver2", BtVer2Model, [ + FeatureX87, FeatureMMX, FeatureAVX, FeatureFXSR, @@ -644,6 +668,7 @@ // Bulldozer def : Proc<"bdver1", [ + FeatureX87, FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B, @@ -662,6 +687,7 @@ ]>; // Piledriver def : Proc<"bdver2", [ + FeatureX87, FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B, @@ -685,6 +711,7 @@ // Steamroller def : Proc<"bdver3", [ + FeatureX87, FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B, @@ -710,6 +737,7 @@ // Excavator def : Proc<"bdver4", [ + FeatureX87, FeatureMMX, FeatureAVX2, FeatureFXSR, @@ -732,12 +760,13 @@ FeatureLAHFSAHF ]>; -def : Proc<"geode", [FeatureSlowUAMem16, Feature3DNowA]>; +def : Proc<"geode", [FeatureX87, FeatureSlowUAMem16, Feature3DNowA]>; -def : Proc<"winchip-c6", [FeatureSlowUAMem16, FeatureMMX]>; -def : Proc<"winchip2", [FeatureSlowUAMem16, Feature3DNow]>; -def : Proc<"c3", [FeatureSlowUAMem16, Feature3DNow]>; -def : Proc<"c3-2", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1, FeatureFXSR]>; +def : Proc<"winchip-c6", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>; +def : Proc<"winchip2", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>; +def : Proc<"c3", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>; +def : Proc<"c3-2", [FeatureX87, FeatureSlowUAMem16, FeatureMMX, + FeatureSSE1, FeatureFXSR]>; // We also provide a generic 64-bit specific x86 processor model which tries to // be good for modern chips without enabling instruction set encodings past the @@ -750,8 +779,8 @@ // knobs which need to be tuned differently for AMD chips, we might consider // forming a common base for them. def : ProcessorModel<"x86-64", SandyBridgeModel, - [FeatureMMX, FeatureSSE2, FeatureFXSR, Feature64Bit, - FeatureSlowBTMem ]>; + [FeatureX87, FeatureMMX, FeatureSSE2, FeatureFXSR, + Feature64Bit, FeatureSlowBTMem ]>; //===----------------------------------------------------------------------===// // Register File Description Index: lib/Target/X86/X86ISelLowering.cpp =================================================================== --- lib/Target/X86/X86ISelLowering.cpp +++ lib/Target/X86/X86ISelLowering.cpp @@ -523,7 +523,7 @@ setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom); setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom); - if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) { + if (!Subtarget->useSoftFloat() && Subtarget->hasX87() && X86ScalarSSEf64) { // f32 and f64 use SSE. // Set up the FP register classes. addRegisterClass(MVT::f32, &X86::FR32RegClass); @@ -557,7 +557,8 @@ // cases we handle. addLegalFPImmediate(APFloat(+0.0)); // xorpd addLegalFPImmediate(APFloat(+0.0f)); // xorps - } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) { + } else if (!Subtarget->useSoftFloat() && Subtarget->hasX87() && + X86ScalarSSEf32) { // Use SSE for f32, x87 for f64. // Set up the FP register classes. addRegisterClass(MVT::f32, &X86::FR32RegClass); @@ -592,7 +593,7 @@ setOperationAction(ISD::FCOS , MVT::f64, Expand); setOperationAction(ISD::FSINCOS, MVT::f64, Expand); } - } else if (!Subtarget->useSoftFloat()) { + } else if (!Subtarget->useSoftFloat() && Subtarget->hasX87()) { // f32 and f64 in x87. // Set up the FP register classes. addRegisterClass(MVT::f64, &X86::RFP64RegClass); @@ -626,7 +627,7 @@ setOperationAction(ISD::FMA, MVT::f32, Expand); // Long double always uses X87, except f128 in MMX. - if (!Subtarget->useSoftFloat()) { + if (!Subtarget->useSoftFloat() && Subtarget->hasX87()) { if (Subtarget->is64Bit() && Subtarget->hasMMX()) { addRegisterClass(MVT::f128, &X86::FR128RegClass); ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat); Index: lib/Target/X86/X86Subtarget.h =================================================================== --- lib/Target/X86/X86Subtarget.h +++ lib/Target/X86/X86Subtarget.h @@ -70,6 +70,9 @@ /// MMX, 3DNow, 3DNow Athlon, or none supported. X863DNowEnum X863DNowLevel; + /// True if the processor supports X87 instructions. + bool HasX87; + /// True if this processor has conditional move instructions /// (generally pentium pro+). bool HasCMov; @@ -339,6 +342,7 @@ PICStyles::Style getPICStyle() const { return PICStyle; } void setPICStyle(PICStyles::Style Style) { PICStyle = Style; } + bool hasX87() const { return HasX87; } bool hasCMov() const { return HasCMov; } bool hasSSE1() const { return X86SSELevel >= SSE1; } bool hasSSE2() const { return X86SSELevel >= SSE2; } Index: lib/Target/X86/X86Subtarget.cpp =================================================================== --- lib/Target/X86/X86Subtarget.cpp +++ lib/Target/X86/X86Subtarget.cpp @@ -239,6 +239,7 @@ void X86Subtarget::initializeEnvironment() { X86SSELevel = NoSSE; X863DNowLevel = NoThreeDNow; + HasX87 = false; HasCMov = false; HasX86_64 = false; HasPOPCNT = false; Index: test/CodeGen/X86/x87.ll =================================================================== --- /dev/null +++ test/CodeGen/X86/x87.ll @@ -0,0 +1,79 @@ +; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=X87 +; RUN: llc < %s -march=x86-64 -mattr=-sse | FileCheck %s -check-prefix=X87 +; RUN: llc < %s -march=x86 -mattr=-x87 | FileCheck %s -check-prefix=NOX87 +; RUN: llc < %s -march=x86-64 -mattr=-x87 | FileCheck %s -check-prefix=NOX87 +; RUN: llc < %s -march=x86 -mattr=-x87,+sse | FileCheck %s -check-prefix=NOX87 +; RUN: llc < %s -march=x86-64 -mattr=-x87,+sse | FileCheck %s -check-prefix=NOX87 +; RUN: llc < %s -march=x86 -mattr=-x87,+sse2 | FileCheck %s -check-prefix=NOX87 +; RUN: llc < %s -march=x86-64 -mattr=-x87,+sse2 | FileCheck %s -check-prefix=NOX87 + +; X87: {{ }}f{{.*}} +; NOX87-NOT: {{ }}f{{.*}} + +define void @test() nounwind readnone { +entry: + %pi = alloca i32 + %pl = alloca i64 + %pf1 = alloca float + %pf2 = alloca float + %pd1 = alloca double + %pd2 = alloca double + %pld1 = alloca fp128 + %pld2 = alloca fp128 + + %i = load i32, i32* %pi + %l = load i64, i64* %pl + %f1 = load float, float* %pf1 + %f2 = load float, float* %pf2 + %d1 = load double, double* %pd1 + %d2 = load double, double* %pd2 + %ld1 = load fp128, fp128* %pld1 + %ld2 = load fp128, fp128* %pld2 + + %tmp = fadd float %f1, %f2 + store float %tmp, float* %pf1 + + %tmp1 = fadd double %d1, %d2 + store double %tmp1, double* %pd1 + + %tmp2 = fadd fp128 %ld1, %ld2 + store fp128 %tmp2, fp128* %pld1 + + %tmp3 = uitofp i32 %i to float + store float %tmp3, float* %pf1 + + %tmp4 = uitofp i32 %i to double + store double %tmp4, double* %pd1 + + %tmp5 = uitofp i32 %i to fp128 + store fp128 %tmp5, fp128* %pld1 + + %tmp6 = uitofp i64 %l to float + store float %tmp6, float* %pf2 + + %tmp7 = uitofp i64 %l to double + store double %tmp7, double* %pd2 + + %tmp8 = uitofp i64 %l to fp128 + store fp128 %tmp8, fp128* %pld2 + + %tmp9 = sitofp i32 %i to float + store float %tmp9, float* %pf1 + + %tmp10 = sitofp i32 %i to double + store double %tmp10, double* %pd1 + + %tmp11 = sitofp i32 %i to fp128 + store fp128 %tmp11, fp128* %pld1 + + %tmp12 = sitofp i64 %l to float + store float %tmp12, float* %pf2 + + %tmp13 = sitofp i64 %l to double + store double %tmp13, double* %pd2 + + %tmp14 = sitofp i64 %l to fp128 + store fp128 %tmp14, fp128* %pld2 + + ret void +}