Index: lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp =================================================================== --- lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -1080,8 +1080,8 @@ static_cast(Subtarget->getRegisterInfo()); const SIMachineFunctionInfo *Info = MF.getInfo(); - unsigned ScratchOffsetReg - = TRI->getPreloadedValue(MF, SIRegisterInfo::SCRATCH_WAVE_OFFSET); + unsigned ScratchOffsetReg = TRI->getPreloadedValue( + MF, SIRegisterInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET); Rsrc = CurDAG->getRegister(Info->getScratchRSrcReg(), MVT::v4i32); SOffset = CurDAG->getRegister(ScratchOffsetReg, MVT::i32); Index: lib/Target/AMDGPU/SIISelLowering.cpp =================================================================== --- lib/Target/AMDGPU/SIISelLowering.cpp +++ lib/Target/AMDGPU/SIISelLowering.cpp @@ -476,7 +476,7 @@ static_cast(Subtarget->getRegisterInfo()); if (!BasePtrReg) - BasePtrReg = TRI->getPreloadedValue(MF, SIRegisterInfo::INPUT_PTR); + BasePtrReg = TRI->getPreloadedValue(MF, SIRegisterInfo::KERNARG_SEGMENT_PTR); Type *Ty = VT.getTypeForEVT(*DAG.getContext()); @@ -590,7 +590,7 @@ Info->NumUserSGPRs += 4; unsigned InputPtrReg = - TRI->getPreloadedValue(MF, SIRegisterInfo::INPUT_PTR); + TRI->getPreloadedValue(MF, SIRegisterInfo::KERNARG_SEGMENT_PTR); unsigned InputPtrRegLo = TRI->getPhysRegSubReg(InputPtrReg, &AMDGPU::SReg_32RegClass, 0); unsigned InputPtrRegHi = @@ -600,14 +600,8 @@ CCInfo.AllocateReg(InputPtrRegHi); MF.addLiveIn(InputPtrReg, &AMDGPU::SReg_64RegClass); if (Subtarget->isAmdHsaOS()) { - unsigned DispatchPtrReg = - TRI->getPreloadedValue(MF, SIRegisterInfo::DISPATCH_PTR); - unsigned DispatchPtrRegLo = - TRI->getPhysRegSubReg(DispatchPtrReg, &AMDGPU::SReg_32RegClass, 0); - unsigned DispatchPtrRegHi = - TRI->getPhysRegSubReg(DispatchPtrReg, &AMDGPU::SReg_32RegClass, 1); - CCInfo.AllocateReg(DispatchPtrRegLo); - CCInfo.AllocateReg(DispatchPtrRegHi); + unsigned DispatchPtrReg + = TRI->getPreloadedValue(MF, SIRegisterInfo::DISPATCH_PTR); MF.addLiveIn(DispatchPtrReg, &AMDGPU::SReg_64RegClass); } } @@ -639,8 +633,8 @@ VA.getLocMemOffset(); // The first 36 bytes of the input buffer contains information about // thread group and global sizes. - unsigned InputPtrReg = TRI->getPreloadedValue(MF, - SIRegisterInfo::INPUT_PTR); + unsigned InputPtrReg = TRI->getPreloadedValue( + MF, SIRegisterInfo::KERNARG_SEGMENT_PTR); SDValue Arg = LowerParameter(DAG, VT, MemVT, DL, Chain, Offset, InputPtrReg, Ins[i].Flags.isSExt()); Chains.push_back(Arg.getValue(1)); @@ -1054,7 +1048,7 @@ } } else { - BasePtr = TRI->getPreloadedValue(MF, SIRegisterInfo::INPUT_PTR); + BasePtr = TRI->getPreloadedValue(MF, SIRegisterInfo::KERNARG_SEGMENT_PTR); Offset = SI::KernelInputOffsets::LOCAL_SIZE_X + (Dim * 4); Param = LowerParameter(DAG, MVT::i32, MVT::i32, DL, DAG.getEntryNode(), @@ -1076,7 +1070,8 @@ EVT VT = Op.getValueType(); SDLoc DL(Op); unsigned IntrinsicID = cast(Op.getOperand(0))->getZExtValue(); - unsigned InputPtrReg = TRI->getPreloadedValue(MF, SIRegisterInfo::INPUT_PTR); + unsigned InputPtrReg = TRI->getPreloadedValue( + MF, SIRegisterInfo::KERNARG_SEGMENT_PTR); // TODO: Should this propagate fast-math-flags? @@ -1119,22 +1114,22 @@ case Intrinsic::r600_read_tgid_x: return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass, - TRI->getPreloadedValue(MF, SIRegisterInfo::TGID_X), VT); + TRI->getPreloadedValue(MF, SIRegisterInfo::WORKGROUP_ID_X), VT); case Intrinsic::r600_read_tgid_y: return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass, - TRI->getPreloadedValue(MF, SIRegisterInfo::TGID_Y), VT); + TRI->getPreloadedValue(MF, SIRegisterInfo::WORKGROUP_ID_Y), VT); case Intrinsic::r600_read_tgid_z: return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass, - TRI->getPreloadedValue(MF, SIRegisterInfo::TGID_Z), VT); + TRI->getPreloadedValue(MF, SIRegisterInfo::WORKGROUP_ID_Z), VT); case Intrinsic::r600_read_tidig_x: return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass, - TRI->getPreloadedValue(MF, SIRegisterInfo::TIDIG_X), VT); + TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_X), VT); case Intrinsic::r600_read_tidig_y: return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass, - TRI->getPreloadedValue(MF, SIRegisterInfo::TIDIG_Y), VT); + TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_Y), VT); case Intrinsic::r600_read_tidig_z: return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass, - TRI->getPreloadedValue(MF, SIRegisterInfo::TIDIG_Z), VT); + TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_Z), VT); case AMDGPUIntrinsic::SI_load_const: { SDValue Ops[] = { Op.getOperand(1), Index: lib/Target/AMDGPU/SIInstrInfo.cpp =================================================================== --- lib/Target/AMDGPU/SIInstrInfo.cpp +++ lib/Target/AMDGPU/SIInstrInfo.cpp @@ -551,8 +551,8 @@ assert(RI.hasVGPRs(RC) && "Only VGPR spilling expected"); - unsigned ScratchOffsetPreloadReg - = RI.getPreloadedValue(*MF, SIRegisterInfo::SCRATCH_WAVE_OFFSET); + unsigned ScratchOffsetPreloadReg = RI.getPreloadedValue( + *MF, SIRegisterInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET); unsigned Opcode = getVGPRSpillSaveOpcode(RC->getSize()); MFI->setHasSpilledVGPRs(); @@ -638,8 +638,8 @@ assert(RI.hasVGPRs(RC) && "Only VGPR spilling expected"); - unsigned ScratchOffsetPreloadReg - = RI.getPreloadedValue(*MF, SIRegisterInfo::SCRATCH_WAVE_OFFSET); + unsigned ScratchOffsetPreloadReg = RI.getPreloadedValue( + *MF, SIRegisterInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET); unsigned Opcode = getVGPRSpillRestoreOpcode(RC->getSize()); BuildMI(MBB, MI, DL, get(Opcode), DestReg) @@ -678,11 +678,14 @@ if (MFI->getShaderType() == ShaderType::COMPUTE && WorkGroupSize > WavefrontSize) { - unsigned TIDIGXReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_X); - unsigned TIDIGYReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Y); - unsigned TIDIGZReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Z); + unsigned TIDIGXReg + = TRI->getPreloadedValue(*MF, SIRegisterInfo::WORKGROUP_ID_X); + unsigned TIDIGYReg + = TRI->getPreloadedValue(*MF, SIRegisterInfo::WORKGROUP_ID_Y); + unsigned TIDIGZReg + = TRI->getPreloadedValue(*MF, SIRegisterInfo::WORKGROUP_ID_Z); unsigned InputPtrReg = - TRI->getPreloadedValue(*MF, SIRegisterInfo::INPUT_PTR); + TRI->getPreloadedValue(*MF, SIRegisterInfo::KERNARG_SEGMENT_PTR); for (unsigned Reg : {TIDIGXReg, TIDIGYReg, TIDIGZReg}) { if (!Entry.isLiveIn(Reg)) Entry.addLiveIn(Reg); Index: lib/Target/AMDGPU/SIRegisterInfo.h =================================================================== --- lib/Target/AMDGPU/SIRegisterInfo.h +++ lib/Target/AMDGPU/SIRegisterInfo.h @@ -93,23 +93,25 @@ /// \returns True if operands defined with this operand type can accept /// an inline constant. i.e. An integer value in the range (-16, 64) or - /// -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f. + /// -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f. bool opCanUseInlineConstant(unsigned OpType) const; enum PreloadedValue { // SGPRS: - SCRATCH_PTR = 0, + PRIVATE_SEGMENT_BUFFER = 0, DISPATCH_PTR = 1, - INPUT_PTR = 3, - TGID_X = 10, - TGID_Y = 11, - TGID_Z = 12, - SCRATCH_WAVE_OFFSET = 14, + QUEUE_PTR = 2, + KERNARG_SEGMENT_PTR = 3, + WORKGROUP_ID_X = 10, + WORKGROUP_ID_Y = 11, + WORKGROUP_ID_Z = 12, + PRIVATE_SEGMENT_WAVE_BYTE_OFFSET = 14, + // VGPRS: FIRST_VGPR_VALUE = 15, - TIDIG_X = FIRST_VGPR_VALUE, - TIDIG_Y = 16, - TIDIG_Z = 17, + WORKITEM_ID_X = FIRST_VGPR_VALUE, + WORKITEM_ID_Y = 16, + WORKITEM_ID_Z = 17 }; /// \brief Returns the physical register that \p Value is stored in. Index: lib/Target/AMDGPU/SIRegisterInfo.cpp =================================================================== --- lib/Target/AMDGPU/SIRegisterInfo.cpp +++ lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -65,7 +65,7 @@ unsigned ScratchRSrcReg = MFI->getScratchRSrcReg(); if (ScratchRSrcReg != AMDGPU::NoRegister) { unsigned ScratchOffsetPreloadReg - = getPreloadedValue(MF, SIRegisterInfo::SCRATCH_WAVE_OFFSET); + = getPreloadedValue(MF, SIRegisterInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET); // We will need to use this user SGPR argument for spilling, and thus never // want it to be spilled. reserveRegisterTuples(Reserved, ScratchOffsetPreloadReg); @@ -525,27 +525,29 @@ const AMDGPUSubtarget &STI = MF.getSubtarget(); const SIMachineFunctionInfo *MFI = MF.getInfo(); switch (Value) { - case SIRegisterInfo::TGID_X: + case SIRegisterInfo::WORKGROUP_ID_X: return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 0); - case SIRegisterInfo::TGID_Y: + case SIRegisterInfo::WORKGROUP_ID_Y: return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 1); - case SIRegisterInfo::TGID_Z: + case SIRegisterInfo::WORKGROUP_ID_Z: return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 2); - case SIRegisterInfo::SCRATCH_WAVE_OFFSET: + case SIRegisterInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET: if (MFI->getShaderType() != ShaderType::COMPUTE) return MFI->ScratchOffsetReg; return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 4); - case SIRegisterInfo::SCRATCH_PTR: - return AMDGPU::SGPR2_SGPR3; - case SIRegisterInfo::INPUT_PTR: + case SIRegisterInfo::PRIVATE_SEGMENT_BUFFER: + llvm_unreachable("currently unused"); + case SIRegisterInfo::KERNARG_SEGMENT_PTR: return STI.isAmdHsaOS() ? AMDGPU::SGPR2_SGPR3 : AMDGPU::SGPR0_SGPR1; case SIRegisterInfo::DISPATCH_PTR: return AMDGPU::SGPR0_SGPR1; - case SIRegisterInfo::TIDIG_X: + case SIRegisterInfo::QUEUE_PTR: + llvm_unreachable("not implemented"); + case SIRegisterInfo::WORKITEM_ID_X: return AMDGPU::VGPR0; - case SIRegisterInfo::TIDIG_Y: + case SIRegisterInfo::WORKITEM_ID_Y: return AMDGPU::VGPR1; - case SIRegisterInfo::TIDIG_Z: + case SIRegisterInfo::WORKITEM_ID_Z: return AMDGPU::VGPR2; } llvm_unreachable("unexpected preloaded value type");