Index: lib/Target/Mips/MipsISelLowering.cpp
===================================================================
--- lib/Target/Mips/MipsISelLowering.cpp
+++ lib/Target/Mips/MipsISelLowering.cpp
@@ -1404,8 +1404,11 @@
 
   MachineFunction *MF = BB->getParent();
   MachineRegisterInfo &RegInfo = MF->getRegInfo();
-  const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
+  bool isABI64 = Subtarget.isABI_N64();
+  const TargetRegisterClass *RC = 
+    getRegClassFor(isABI64 ? MVT::i64 : MVT::i32);
   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
+  bool is64 =  Subtarget.isGP64bit();
   DebugLoc DL = MI->getDebugLoc();
 
   unsigned Dest    = MI->getOperand(0).getReg();
@@ -1470,28 +1473,28 @@
   //    sll     shiftednewval,maskednewval,shiftamt
   int64_t MaskImm = (Size == 1) ? 255 : 65535;
   BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
-    .addReg(Mips::ZERO).addImm(-4);
-  BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
+    .addReg(is64 ? Mips::ZERO_64 : Mips::ZERO).addImm(-4);
+  BuildMI(BB, DL, TII->get(is64 ? Mips::AND64 : Mips::AND), AlignedAddr)
     .addReg(Ptr).addReg(MaskLSB2);
-  BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
+  BuildMI(BB, DL, TII->get(is64 ?  Mips::ANDi64 : Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
   if (Subtarget.isLittle()) {
     BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
   } else {
     unsigned Off = RegInfo.createVirtualRegister(RC);
-    BuildMI(BB, DL, TII->get(Mips::XORi), Off)
+    BuildMI(BB, DL, TII->get(is64 ? Mips::XORi64 : Mips::XORi), Off)
       .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
-    BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
+    BuildMI(BB, DL, TII->get( Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
   }
-  BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
+  BuildMI(BB, DL, TII->get(is64? Mips::ORi64 : Mips::ORi), MaskUpper)
     .addReg(Mips::ZERO).addImm(MaskImm);
   BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
     .addReg(MaskUpper).addReg(ShiftAmt);
-  BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
-  BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
+  BuildMI(BB, DL, TII->get(is64? Mips::NOR64 : Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
+  BuildMI(BB, DL, TII->get(is64? Mips::ANDi64 : Mips::ANDi), MaskedCmpVal)
     .addReg(CmpVal).addImm(MaskImm);
   BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
     .addReg(MaskedCmpVal).addReg(ShiftAmt);
-  BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
+  BuildMI(BB, DL, TII->get(is64 ? Mips::ANDi64 : Mips::ANDi), MaskedNewVal)
     .addReg(NewVal).addImm(MaskImm);
   BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
     .addReg(MaskedNewVal).addReg(ShiftAmt);
@@ -1503,9 +1506,9 @@
   BB = loop1MBB;
   unsigned LL = isMicroMips ? Mips::LL_MM : Mips::LL;
   BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
-  BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
+  BuildMI(BB, DL, TII->get(is64? Mips::AND64 : Mips::AND), MaskedOldVal0)
     .addReg(OldVal).addReg(Mask);
-  BuildMI(BB, DL, TII->get(Mips::BNE))
+  BuildMI(BB, DL, TII->get(is64 ? Mips::BNE64 : Mips::BNE))
     .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
 
   //  loop2MBB:
@@ -1514,15 +1517,15 @@
   //    sc      success,storeval,0(alignedaddr)
   //    beq     success,$0,loop1MBB
   BB = loop2MBB;
-  BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
+  BuildMI(BB, DL, TII->get(is64? Mips::AND64 : Mips::AND), MaskedOldVal1)
     .addReg(OldVal).addReg(Mask2);
-  BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
+  BuildMI(BB, DL, TII->get(is64? Mips::OR64 : Mips::OR), StoreVal)
     .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
   unsigned SC = isMicroMips ? Mips::SC_MM : Mips::SC;
   BuildMI(BB, DL, TII->get(SC), Success)
       .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
-  BuildMI(BB, DL, TII->get(Mips::BEQ))
-      .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
+  BuildMI(BB, DL, TII->get(is64? Mips::BEQ64 : Mips::BEQ))
+      .addReg(Success).addReg(is64? Mips::ZERO_64 : Mips::ZERO).addMBB(loop1MBB);
 
   //  sinkMBB:
   //    srl     srlres,maskedoldval0,shiftamt
Index: test/CodeGen/Mips/atomicCmpSwapPW.ll
===================================================================
--- test/CodeGen/Mips/atomicCmpSwapPW.ll
+++ test/CodeGen/Mips/atomicCmpSwapPW.ll
@@ -0,0 +1,18 @@
+; RUN: llc  -O0 -march=mips64el -mcpu=mips64r2 < %s -filetype=asm -o - \
+; RUN:   | FileCheck %s -implicit-check-not=lw
+
+@_ZZ14InitializeOncevE5array = global [1 x i32*] zeroinitializer, align 8
+@_ZGVZ14InitializeOncevE5array = global i64 0, align 8
+
+define void @_Z14InitializeOncev()
+#0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+entry:
+  %exn.slot = alloca i8*
+  %ehselector.slot = alloca i32
+  %0 = load atomic i8,
+     i8* bitcast (i64* @_ZGVZ14InitializeOncevE5array to i8*) acquire, align 8
+  ret void
+}
+
+
+declare i32 @__gxx_personality_v0(...)