Index: lib/Target/ARM/ARMTargetMachine.cpp
===================================================================
--- lib/Target/ARM/ARMTargetMachine.cpp
+++ lib/Target/ARM/ARMTargetMachine.cpp
@@ -364,7 +364,7 @@
 bool ARMPassConfig::addInstSelector() {
   addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
 
-  if (TM->getTargetTriple().isOSBinFormatELF() && TM->Options.EnableFastISel)
+  if (TM->getTargetTriple().isOSBinFormatELF())
     addPass(createARMGlobalBaseRegPass());
   return false;
 }
Index: test/CodeGen/ARM/optnone-pic.ll
===================================================================
--- /dev/null
+++ test/CodeGen/ARM/optnone-pic.ll
@@ -0,0 +1,16 @@
+; Ensure ARMGlobalBaseReg pass runs even when FastISel is globally disabled.
+
+; In PIC mode of ARM code generation, FastISel emits instructions that require
+; ARMGlobalBaseReg pass.
+; Though the pass is usually not required when FastISel is disabled, a function
+; with optnone attribute uses FastISel and does require the pass. Without the
+; pass, llc crash in the code generation.
+
+; RUN:  llc < %s -mtriple=armv7-unknown-linux-gnueabi -fast-isel=false \
+; RUN:           -relocation-model=pic
+
+@a = global i32 0
+define i32 @optnone_test() noinline optnone {
+  %1 = load i32, i32* @a
+  ret i32 %1
+}