Index: lib/Target/X86/X86InstrCMovSetCC.td
===================================================================
--- lib/Target/X86/X86InstrCMovSetCC.td
+++ lib/Target/X86/X86InstrCMovSetCC.td
@@ -40,19 +40,19 @@
   let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
       SchedRW = [WriteALULd, ReadAfterLd] in {
     def NAME#16rm
-      : I<opc, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
+      : I<opc, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, anyi16mem:$src2),
           !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
           [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
                                     CondNode, EFLAGS))], IIC_CMOV16_RM>,
                                     TB, OpSize16;
     def NAME#32rm
-      : I<opc, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
+      : I<opc, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, anyi32mem:$src2),
           !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),
           [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
                                     CondNode, EFLAGS))], IIC_CMOV32_RM>,
                                     TB, OpSize32;
     def NAME#64rm
-      :RI<opc, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
+      :RI<opc, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, anyi64mem:$src2),
           !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),
           [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
                                     CondNode, EFLAGS))], IIC_CMOV32_RM>, TB;
@@ -86,7 +86,7 @@
                      !strconcat(Mnemonic, "\t$dst"),
                      [(set GR8:$dst, (X86setcc OpNode, EFLAGS))],
                      IIC_SET_R>, TB, Sched<[WriteALU]>;
-    def m    : I<opc, MRMXm,  (outs), (ins i8mem:$dst),
+    def m    : I<opc, MRMXm,  (outs), (ins anyi8mem:$dst),
                      !strconcat(Mnemonic, "\t$dst"),
                      [(store (X86setcc OpNode, EFLAGS), addr:$dst)],
                      IIC_SET_M>, TB, Sched<[WriteALU, WriteStore]>;
Index: lib/Target/X86/X86InstrInfo.td
===================================================================
--- lib/Target/X86/X86InstrInfo.td
+++ lib/Target/X86/X86InstrInfo.td
@@ -309,6 +309,10 @@
 }
 
 def anymem : X86MemOperand<"printanymem">;
+def anyi8mem  : X86MemOperand<"printi8mem">;
+def anyi16mem : X86MemOperand<"printi16mem">;
+def anyi32mem : X86MemOperand<"printi32mem">;
+def anyi64mem : X86MemOperand<"printi64mem">;
 
 def opaque32mem : X86MemOperand<"printopaquemem">;
 def opaque48mem : X86MemOperand<"printopaquemem">;
Index: test/MC/X86/msCompatibility.s
===================================================================
--- test/MC/X86/msCompatibility.s
+++ test/MC/X86/msCompatibility.s
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 %s | FileCheck %s 
+
+//CHECK:cmova ax, word ptr [test_mem] 
+cmova ax,XMMWORD PTR test_mem
+//CHECK:cmova ax, word ptr [test_mem] 
+cmova ax,QWORD PTR test_mem
+//CHECK:cmova ax, word ptr [test_mem] 
+cmova ax,TBYTE PTR test_mem
+//CHECK:cmova ax, word ptr [test_mem] 
+cmova ax,DWORD PTR test_mem
+//CHECK:cmova ax, word ptr [test_mem] 
+cmova ax,BYTE PTR test_mem
+//CHECK:cmova eax, dword ptr [test_mem] 
+cmova eax,XMMWORD PTR test_mem
+//CHECK:cmova eax, dword ptr [test_mem] 
+cmova eax,QWORD PTR test_mem
+//CHECK:cmova eax, dword ptr [test_mem] 
+cmova eax,TBYTE PTR test_mem
+//CHECK:cmova eax, dword ptr [test_mem] 
+cmova eax,WORD PTR test_mem
+//CHECK:cmova eax, dword ptr [test_mem] 
+cmova eax,BYTE PTR test_mem
+//CHECK:cmova rax, qword ptr [test_mem] 
+cmova rax,XMMWORD PTR test_mem
+//CHECK:cmova rax, qword ptr [test_mem] 
+cmova rax,TBYTE PTR test_mem
+//CHECK:cmova rax, qword ptr [test_mem] 
+cmova rax,DWORD PTR test_mem
+//CHECK:cmova rax, qword ptr [test_mem] 
+cmova rax,WORD PTR test_mem
+//CHECK:cmova rax, qword ptr [test_mem] 
+cmova rax,BYTE PTR test_mem
Index: utils/TableGen/X86RecognizableInstr.cpp
===================================================================
--- utils/TableGen/X86RecognizableInstr.cpp
+++ utils/TableGen/X86RecognizableInstr.cpp
@@ -980,6 +980,10 @@
   TYPE("VR64",                TYPE_MM64)
   TYPE("i64imm",              TYPE_IMMv)
   TYPE("anymem",              TYPE_M)
+  TYPE("anyi8mem",            TYPE_M)
+  TYPE("anyi16mem",           TYPE_M)
+  TYPE("anyi32mem",           TYPE_M)
+  TYPE("anyi64mem",           TYPE_M)
   TYPE("opaque32mem",         TYPE_M1616)
   TYPE("opaque48mem",         TYPE_M1632)
   TYPE("opaque80mem",         TYPE_M1664)
@@ -1211,6 +1215,10 @@
   ENCODING("lea64_32mem",     ENCODING_RM)
   ENCODING("lea64mem",        ENCODING_RM)
   ENCODING("anymem",          ENCODING_RM)
+  ENCODING("anyi8mem",        ENCODING_RM)
+  ENCODING("anyi16mem",       ENCODING_RM)
+  ENCODING("anyi32mem",       ENCODING_RM)
+  ENCODING("anyi64mem",       ENCODING_RM)
   ENCODING("opaque32mem",     ENCODING_RM)
   ENCODING("opaque48mem",     ENCODING_RM)
   ENCODING("opaque80mem",     ENCODING_RM)