Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -14892,6 +14892,8 @@
                SplitStack || MF.shouldProbeStack();
   SDLoc dl(Op);
 
+  const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
+
   if (!Lower) {
     const TargetLowering &TLI = DAG.getTargetLoweringInfo();
     SDNode* Node = Op.getNode();
@@ -14914,7 +14916,6 @@
     SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
     Chain = SP.getValue(1);
     unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
-    const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
     unsigned StackAlign = TFI.getStackAlignment();
     Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
     if (Align > StackAlign)
@@ -14934,7 +14935,6 @@
   SDValue Chain = Op.getOperand(0);
   SDValue Size  = Op.getOperand(1);
   unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
-  EVT VT = Op.getNode()->getValueType(0);
 
   bool Is64Bit = Subtarget->is64Bit();
   MVT SPTy = getPointerTy(DAG.getDataLayout());
@@ -14962,7 +14962,14 @@
     SDValue Ops1[2] = { Value, Chain };
     return DAG.getMergeValues(Ops1, dl);
   } else {
+    unsigned StackAlign = TFI.getStackAlignment();
     SDValue Flag;
+    if (Align > StackAlign) {
+      Size = DAG.getNode(ISD::ADD, dl, SPTy, Size, DAG.getIntPtrConstant(Align - 1, dl));
+      Size = DAG.getNode(ISD::AND, dl, SPTy, Size,
+                         DAG.getIntPtrConstant(~(uint64_t)(Align - 1), dl));
+    }
+
     const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
 
     Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
@@ -14984,12 +14991,6 @@
     SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
     Chain = SP.getValue(1);
 
-    if (Align) {
-      SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
-                       DAG.getConstant(-(uint64_t)Align, dl, VT));
-      Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
-    }
-
     SDValue Ops1[2] = { SP, Chain };
     return DAG.getMergeValues(Ops1, dl);
   }
Index: test/CodeGen/X86/win64_alloca_dynalloca.ll
===================================================================
--- test/CodeGen/X86/win64_alloca_dynalloca.ll
+++ test/CodeGen/X86/win64_alloca_dynalloca.ll
@@ -95,21 +95,17 @@
 
   %buf1 = alloca i8, i64 %n, align 128
 
-; M64: leaq  15(%{{.*}}), %rax
-; M64: andq  $-16, %rax
+; M64: addq  $127, %rax
+; M64: andq  $-128, %rax
 ; M64: callq ___chkstk_ms
 ; M64: subq  %rax, %rsp
 ; M64: movq  %rsp, [[R2:%r.*]]
-; M64: andq  $-128, [[R2]]
-; M64: movq  [[R2]], %rsp
 
-; W64: leaq  15(%{{.*}}), %rax
-; W64: andq  $-16, %rax
+; W64: addq  $127, %rax
+; W64: andq  $-128, %rax
 ; W64: callq __chkstk
 ; W64: subq  %rax, %rsp
 ; W64: movq  %rsp, [[R2:%r.*]]
-; W64: andq  $-128, [[R2]]
-; W64: movq  [[R2]], %rsp
 
 ; EFI: leaq  15(%{{.*}}), [[R1:%r.*]]
 ; EFI: andq  $-16, [[R1]]