[AMDGPU][GFX10][MC] Updated symbolic names of internal HW registers

[dp]

Summary

GFX10 no longer support HW_ID. It has been replaced with HW_ID1 and HW_ID2.
See bug 52904.

llvm/docs/AMDGPU/gfx10_hwreg.rst

 Defined register *names* include:
 
     =================== ==========================================
     Name                Description
     =================== ==========================================
     HW_REG_MODE         Shader writeable mode bits.
     HW_REG_STATUS       Shader read-only status.
     HW_REG_TRAPSTS      Trap status.
-    HW_REG_HW_ID        Id of wave, simd, compute unit, etc.
+    HW_REG_HW_ID1       Id of wave, simd, compute unit, etc.
+    HW_REG_HW_ID2       Id of queue, pipeline, etc.
     HW_REG_GPR_ALLOC    Per-wave SGPR and VGPR allocation.
     HW_REG_LDS_ALLOC    Per-wave LDS allocation.
     HW_REG_IB_STS       Counters of outstanding instructions.
     HW_REG_SH_MEM_BASES Memory aperture.
     HW_REG_TBA_LO       tba_lo register.
     HW_REG_TBA_HI       tba_hi register.
     HW_REG_TMA_LO       tma_lo register.
     HW_REG_TMA_HI       tma_hi register.

llvm/lib/Target/AMDGPU/SIDefines.h

enum Id { // HwRegCode, (6) [5:0]
   ID_TBA_LO = 16,
   ID_SYMBOLIC_FIRST_GFX10_ = ID_TBA_LO,
   ID_TBA_HI = 17,
   ID_TMA_LO = 18,
   ID_TMA_HI = 19,
   ID_FLAT_SCR_LO = 20,
   ID_FLAT_SCR_HI = 21,
   ID_XNACK_MASK = 22,
+  ID_HW_ID1 = 23,
+  ID_HW_ID2 = 24,
   ID_POPS_PACKER = 25,
   ID_SHADER_CYCLES = 29,
   ID_SYMBOLIC_FIRST_GFX1030_ = ID_SHADER_CYCLES,
   ID_SYMBOLIC_LAST_ = 30,
   ID_SHIFT_ = 0,
   ID_WIDTH_ = 6,
   ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
 };

llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp

const char* const IdSymbolic[] = {
   "HW_REG_SH_MEM_BASES",
   "HW_REG_TBA_LO",
   "HW_REG_TBA_HI",
   "HW_REG_TMA_LO",
   "HW_REG_TMA_HI",
   "HW_REG_FLAT_SCR_LO",
   "HW_REG_FLAT_SCR_HI",
   "HW_REG_XNACK_MASK",
-  nullptr, // HW_ID1, no predictable values
-  nullptr, // HW_ID2, no predictable values
+  "HW_REG_HW_ID1",
+  "HW_REG_HW_ID2",
   "HW_REG_POPS_PACKER",
   nullptr,
   nullptr,
   nullptr,
   "HW_REG_SHADER_CYCLES"
 };
 
 } // namespace Hwreg

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

else if (isGFX9(STI))
     return ID_SYMBOLIC_FIRST_GFX10_;
   else if (isGFX10(STI) && !isGFX10_BEncoding(STI))
     return ID_SYMBOLIC_FIRST_GFX1030_;
   else
     return ID_SYMBOLIC_LAST_;
 }
 
 bool isValidHwreg(int64_t Id, const MCSubtargetInfo &STI) {
-  return
-    ID_SYMBOLIC_FIRST_ <= Id && Id < getLastSymbolicHwreg(STI) &&
-    IdSymbolic[Id] && (Id != ID_XNACK_MASK || !AMDGPU::isGFX10_BEncoding(STI));
+  switch (Id) {
+  case ID_HW_ID:
+    return isSI(STI) || isCI(STI) || isVI(STI) || isGFX9(STI);
+  case ID_HW_ID1:
+  case ID_HW_ID2:
+    return isGFX10Plus(STI);
+  case ID_XNACK_MASK:
+    return isGFX10(STI) && !AMDGPU::isGFX10_BEncoding(STI);
+  default:
+    return ID_SYMBOLIC_FIRST_ <= Id && Id < getLastSymbolicHwreg(STI) &&
+           IdSymbolic[Id];
+  }
 }
 
 bool isValidHwreg(int64_t Id) {
   return 0 <= Id && isUInt<ID_WIDTH_>(Id);
 }
 
 bool isValidHwregOffset(int64_t Offset) {
   return 0 <= Offset && isUInt<OFFSET_WIDTH_>(Offset);

llvm/test/MC/AMDGPU/sopk.s

 // RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck --check-prefixes=GCN,SICI %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck --check-prefixes=GCN,SICI %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck --check-prefixes=GCN,VI9,VI %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefixes=GCN,VI9,GFX9 %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck --check-prefixes=GCN,GFX10 %s
 
 // RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck -check-prefix=NOSICIVI --implicit-check-not=error: %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=NOSICIVI --implicit-check-not=error: %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=fiji %s 2>&1 | FileCheck -check-prefix=NOSICIVI --implicit-check-not=error: %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck --check-prefix=NOGFX9 --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck --check-prefix=NOGFX10 --implicit-check-not=error: %s
 
 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
 
 s_movk_i32 s2, 0x6
 // GCN: s_movk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb0]
 

 s_mulk_i32 s2, 0xFFFF
 // SICI: s_mulk_i32 s2, 0xffff ; encoding: [0xff,0xff,0x02,0xb8]
 // VI9:  s_mulk_i32 s2, 0xffff ; encoding: [0xff,0xff,0x82,0xb7]
 // GFX10: s_mulk_i32 s2, 0xffff ; encoding: [0xff,0xff,0x02,0xb8]
 
 s_cbranch_i_fork s[2:3], 0x6
 // SICI: s_cbranch_i_fork s[2:3], 6 ; encoding: [0x06,0x00,0x82,0xb8]
 // VI9:  s_cbranch_i_fork s[2:3], 6 ; encoding: [0x06,0x00,0x02,0xb8]
+// NOGFX10: error: instruction not supported on this GPU
 
 //===----------------------------------------------------------------------===//
 // getreg/setreg and hwreg macro
 //===----------------------------------------------------------------------===//
 
 // raw number mapped to known HW register
 s_getreg_b32 s2, 0x6
 // SICI: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x02,0xb9]

 s_getreg_b32 s2, hwreg(22)
 // SICI:  s_getreg_b32 s2, hwreg(22) ; encoding: [0x16,0xf8,0x02,0xb9]
 // VI9:   s_getreg_b32 s2, hwreg(22) ; encoding: [0x16,0xf8,0x82,0xb8]
 // GFX10: s_getreg_b32 s2, hwreg(HW_REG_XNACK_MASK) ; encoding: [0x16,0xf8,0x02,0xb9]
 
 s_getreg_b32 s2, hwreg(23)
 // SICI:  s_getreg_b32 s2, hwreg(23) ; encoding: [0x17,0xf8,0x02,0xb9]
 // VI9:   s_getreg_b32 s2, hwreg(23) ; encoding: [0x17,0xf8,0x82,0xb8]
-// GFX10: s_getreg_b32 s2, hwreg(23) ; encoding: [0x17,0xf8,0x02,0xb9]
+// GFX10: s_getreg_b32 s2, hwreg(HW_REG_HW_ID1) ; encoding: [0x17,0xf8,0x02,0xb9]
 
 s_getreg_b32 s2, hwreg(24)
 // SICI:  s_getreg_b32 s2, hwreg(24) ; encoding: [0x18,0xf8,0x02,0xb9]
 // VI9:   s_getreg_b32 s2, hwreg(24) ; encoding: [0x18,0xf8,0x82,0xb8]
-// GFX10: s_getreg_b32 s2, hwreg(24) ; encoding: [0x18,0xf8,0x02,0xb9]
+// GFX10: s_getreg_b32 s2, hwreg(HW_REG_HW_ID2) ; encoding: [0x18,0xf8,0x02,0xb9]
 
 s_getreg_b32 s2, hwreg(25)
 // SICI:  s_getreg_b32 s2, hwreg(25) ; encoding: [0x19,0xf8,0x02,0xb9]
 // VI9:   s_getreg_b32 s2, hwreg(25) ; encoding: [0x19,0xf8,0x82,0xb8]
 // GFX10: s_getreg_b32 s2, hwreg(HW_REG_POPS_PACKER) ; encoding: [0x19,0xf8,0x02,0xb9]
 
 // raw number mapped to known HW register
 s_setreg_b32 0x6, s2

 // SICI: s_setreg_b32 hwreg(HW_REG_TRAPSTS), s2       ; encoding: [0x03,0xf8,0x82,0xb9]
 // VI9:  s_setreg_b32 hwreg(HW_REG_TRAPSTS), s2       ; encoding: [0x03,0xf8,0x02,0xb9]
 // GFX10: s_setreg_b32 hwreg(HW_REG_TRAPSTS), s2 ; encoding: [0x03,0xf8,0x82,0xb9]
 
 // HW register identifier, default offset/width implied
 s_setreg_b32 hwreg(HW_REG_HW_ID), s2
 // SICI: s_setreg_b32 hwreg(HW_REG_HW_ID), s2       ; encoding: [0x04,0xf8,0x82,0xb9]
 // VI9:  s_setreg_b32 hwreg(HW_REG_HW_ID), s2       ; encoding: [0x04,0xf8,0x02,0xb9]
-// GFX10: s_setreg_b32 hwreg(HW_REG_HW_ID), s2 ; encoding: [0x04,0xf8,0x82,0xb9]
+// NOGFX10: error: specified hardware register is not supported on this GPU
+
+s_setreg_b32 hwreg(HW_REG_HW_ID1), s2
+// NOSICIVI: error: specified hardware register is not supported on this GPU
+// NOGFX9: error: specified hardware register is not supported on this GPU
+// GFX10: s_setreg_b32 hwreg(HW_REG_HW_ID1), s2      ; encoding: [0x17,0xf8,0x82,0xb9]
+
+s_setreg_b32 hwreg(HW_REG_HW_ID2), s2
+// NOSICIVI: error: specified hardware register is not supported on this GPU
+// NOGFX9: error: specified hardware register is not supported on this GPU
+// GFX10: s_setreg_b32 hwreg(HW_REG_HW_ID2), s2      ; encoding: [0x18,0xf8,0x82,0xb9]
 
 // HW register identifier, non-default offset/width
 s_setreg_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), s2
 // SICI: s_setreg_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), s2       ; encoding: [0x45,0xf0,0x82,0xb9]
 // VI9:  s_setreg_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), s2       ; encoding: [0x45,0xf0,0x02,0xb9]
 // GFX10: s_setreg_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), s2 ; encoding: [0x45,0xf0,0x82,0xb9]
 
 // HW register code of unknown HW register, valid symbolic name range but no name available

 s_setreg_b32 hwreg(22), s2
 // SICI:  s_setreg_b32 hwreg(22), s2      ; encoding: [0x16,0xf8,0x82,0xb9]
 // VI9:   s_setreg_b32 hwreg(22), s2      ; encoding: [0x16,0xf8,0x02,0xb9]
 // GFX10: s_setreg_b32 hwreg(HW_REG_XNACK_MASK), s2 ; encoding: [0x16,0xf8,0x82,0xb9]
 
 s_setreg_b32 hwreg(23), s2
 // SICI:  s_setreg_b32 hwreg(23), s2      ; encoding: [0x17,0xf8,0x82,0xb9]
 // VI9:   s_setreg_b32 hwreg(23), s2      ; encoding: [0x17,0xf8,0x02,0xb9]
-// GFX10: s_setreg_b32 hwreg(23), s2      ; encoding: [0x17,0xf8,0x82,0xb9]
+// GFX10: s_setreg_b32 hwreg(HW_REG_HW_ID1), s2      ; encoding: [0x17,0xf8,0x82,0xb9]
 
 s_setreg_b32 hwreg(24), s2
 // SICI:  s_setreg_b32 hwreg(24), s2      ; encoding: [0x18,0xf8,0x82,0xb9]
 // VI9:   s_setreg_b32 hwreg(24), s2      ; encoding: [0x18,0xf8,0x02,0xb9]
-// GFX10: s_setreg_b32 hwreg(24), s2      ; encoding: [0x18,0xf8,0x82,0xb9]
+// GFX10: s_setreg_b32 hwreg(HW_REG_HW_ID2), s2      ; encoding: [0x18,0xf8,0x82,0xb9]
 
 s_setreg_b32 hwreg(25), s2
 // SICI:  s_setreg_b32 hwreg(25), s2      ; encoding: [0x19,0xf8,0x82,0xb9]
 // VI9:   s_setreg_b32 hwreg(25), s2      ; encoding: [0x19,0xf8,0x02,0xb9]
 // GFX10: s_setreg_b32 hwreg(HW_REG_POPS_PACKER), s2 ; encoding: [0x19,0xf8,0x82,0xb9]
 
 // HW register code, non-default offset/width
 s_setreg_b32 hwreg(5, 1, 31), s2