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Differential D117219

[LSV] Vectorize loads of vectors by turning it into a larger vector
ClosedPublic

Authored by bkramer on Jan 13 2022, 6:00 AM.

Details

Reviewers
arsenm
tra
Commits
rG0776f6e04d8c: [LSV] Vectorize loads of vectors by turning it into a larger vector
Summary

Use shufflevector to do the subvector extracts. This allows a lot more
load merging on AMDGPU and also on NVPTX when <2 x half> is involved.

Diff Detail

Event Timeline

bkramer created this revision.Jan 13 2022, 6:00 AM
Herald added subscribers: asavonic, kerbowa, hiraditya and 4 others. · View Herald TranscriptJan 13 2022, 6:00 AM
bkramer requested review of this revision.Jan 13 2022, 6:00 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 13 2022, 6:00 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
Harbormaster completed remote builds in B143143: Diff 399647.Jan 13 2022, 6:35 AM
arsenm added a comment.Jan 13 2022, 6:51 AM

Thanks, I completely forgot this didn't handle this

llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
1302

Too many spaces before In?

llvm/test/Transforms/LoadStoreVectorizer/NVPTX/4x2xhalf.ll
6

Should use named values in tests

34

Should add a larger variety of tests with more vector widths, particularly some 3 element vectors

bkramer updated this revision to Diff 399671.Jan 13 2022, 7:24 AM

Address review comments

bkramer marked 2 inline comments as done.Jan 13 2022, 7:24 AM
bkramer added inline comments.
llvm/test/Transforms/LoadStoreVectorizer/NVPTX/4x2xhalf.ll
34

Anything in particular you're looking for? Currently the pass also has the limitation of only creating vector sizes that are a power of 2, which means there is no interesting case for 3-element vectors.

Harbormaster completed remote builds in B143162: Diff 399671.Jan 13 2022, 7:57 AM
arsenm added inline comments.Jan 19 2022, 6:55 AM
llvm/test/Transforms/LoadStoreVectorizer/NVPTX/4x2xhalf.ll
34

Not handling those is of interest itself?

Vectors of pointers are always an interesting source of edge cases

bkramer updated this revision to Diff 401227.Jan 19 2022, 7:08 AM

Add negative tests for non-pow2 vectors and vectors of pointers

bkramer added inline comments.Jan 19 2022, 7:09 AM
llvm/test/Transforms/LoadStoreVectorizer/NVPTX/4x2xhalf.ll
34

I don't think that's a particularly valuable test, but added some.

bkramer updated this revision to Diff 401229.Jan 19 2022, 7:12 AM

Adjust offset in test

Harbormaster completed remote builds in B144289: Diff 401229.Jan 19 2022, 8:12 AM
arsenm accepted this revision.Jan 25 2022, 6:26 AM
arsenm added inline comments.
llvm/test/Transforms/LoadStoreVectorizer/NVPTX/4x2xhalf.ll
95–96

I would have expected this to vectorize

This revision is now accepted and ready to land.Jan 25 2022, 6:26 AM
Closed by commit rG0776f6e04d8c: [LSV] Vectorize loads of vectors by turning it into a larger vector (authored by bkramer). · Explain WhyJan 26 2022, 2:38 AM
This revision was automatically updated to reflect the committed changes.
bkramer added a commit: rG0776f6e04d8c: [LSV] Vectorize loads of vectors by turning it into a larger vector.
bkramer added inline comments.Jan 26 2022, 2:40 AM
llvm/test/Transforms/LoadStoreVectorizer/NVPTX/4x2xhalf.ll
95–96

The pass explicitly disallows pointers of vectors. Shouldn't be hard to turn it on though, I guess it didn't really matter so far.

Revision Contents

PathSize
llvm/
lib/
Transforms/
Vectorize/
73 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
1664 lines
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27 lines
63 lines
34 lines
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142 lines
74 lines
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276 lines
Transforms/
LoadStoreVectorizer/
NVPTX/
96 lines

Diff 403186

llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp

Show First 20 Lines • Show All 848 Lines • ▼ Show 20 Lines if (LoadInst *LI = dyn_cast<LoadInst>(&I)) {
unsigned VF = VecRegSize / TySize; unsigned VF = VecRegSize / TySize;
VectorType *VecTy = dyn_cast<VectorType>(Ty); VectorType *VecTy = dyn_cast<VectorType>(Ty);
// No point in looking at these if they're too big to vectorize. // No point in looking at these if they're too big to vectorize.
if (TySize > VecRegSize / 2 || if (TySize > VecRegSize / 2 ||
(VecTy && TTI.getLoadVectorFactor(VF, TySize, TySize / 8, VecTy) == 0)) (VecTy && TTI.getLoadVectorFactor(VF, TySize, TySize / 8, VecTy) == 0))
continue; continue;
// Make sure all the users of a vector are constant-index extracts.
if (isa<VectorType>(Ty) && !llvm::all_of(LI->users(), [](const User *U) {
const ExtractElementInst *EEI = dyn_cast<ExtractElementInst>(U);
return EEI && isa<ConstantInt>(EEI->getOperand(1));
}))
continue;
// Save the load locations. // Save the load locations.
const ChainID ID = getChainID(Ptr); const ChainID ID = getChainID(Ptr);
LoadRefs[ID].push_back(LI); LoadRefs[ID].push_back(LI);
} else if (StoreInst *SI = dyn_cast<StoreInst>(&I)) { } else if (StoreInst *SI = dyn_cast<StoreInst>(&I)) {
if (!SI->isSimple()) if (!SI->isSimple())
continue; continue;
// Skip if it's not legal. // Skip if it's not legal.
Show All 24 Lines if (LoadInst *LI = dyn_cast<LoadInst>(&I)) {
unsigned VF = VecRegSize / TySize; unsigned VF = VecRegSize / TySize;
VectorType *VecTy = dyn_cast<VectorType>(Ty); VectorType *VecTy = dyn_cast<VectorType>(Ty);
// No point in looking at these if they're too big to vectorize. // No point in looking at these if they're too big to vectorize.
if (TySize > VecRegSize / 2 || if (TySize > VecRegSize / 2 ||
(VecTy && TTI.getStoreVectorFactor(VF, TySize, TySize / 8, VecTy) == 0)) (VecTy && TTI.getStoreVectorFactor(VF, TySize, TySize / 8, VecTy) == 0))
continue; continue;
if (isa<VectorType>(Ty) && !llvm::all_of(SI->users(), [](const User *U) {
const ExtractElementInst *EEI = dyn_cast<ExtractElementInst>(U);
return EEI && isa<ConstantInt>(EEI->getOperand(1));
}))
continue;
// Save store location. // Save store location.
const ChainID ID = getChainID(Ptr); const ChainID ID = getChainID(Ptr);
StoreRefs[ID].push_back(SI); StoreRefs[ID].push_back(SI);
} }
} }
return {LoadRefs, StoreRefs}; return {LoadRefs, StoreRefs};
} }
▲ Show 20 Lines • Show All 367 Lines • ▼ Show 20 Linesbool Vectorizer::vectorizeLoadChain(
Builder.SetInsertPoint(&*First); Builder.SetInsertPoint(&*First);
Value *Bitcast = Value *Bitcast =
Builder.CreateBitCast(L0->getPointerOperand(), VecTy->getPointerTo(AS)); Builder.CreateBitCast(L0->getPointerOperand(), VecTy->getPointerTo(AS));
LoadInst *LI = LoadInst *LI =
Builder.CreateAlignedLoad(VecTy, Bitcast, MaybeAlign(Alignment)); Builder.CreateAlignedLoad(VecTy, Bitcast, MaybeAlign(Alignment));
propagateMetadata(LI, Chain); propagateMetadata(LI, Chain);
for (unsigned I = 0, E = Chain.size(); I != E; ++I) {
Value *CV = Chain[I];
Value *V;
if (VecLoadTy) { if (VecLoadTy) {
SmallVector<Instruction *, 16> InstrsToErase; // Extract a subvector using shufflevector.
unsigned VecWidth = VecLoadTy->getNumElements(); unsigned VecWidth = VecLoadTy->getNumElements();
for (unsigned I = 0, E = Chain.size(); I != E; ++I) { auto Mask =
for (auto Use : Chain[I]->users()) { llvm::to_vector<8>(llvm::seq<int>(I * VecWidth, (I + 1) * VecWidth));
// All users of vector loads are ExtractElement instructions with V = Builder.CreateShuffleVector(LI, Mask, CV->getName());
// constant indices, otherwise we would have bailed before now. } else {
Instruction *UI = cast<Instruction>(Use); V = Builder.CreateExtractElement(LI, Builder.getInt32(I), CV->getName());
unsigned Idx = cast<ConstantInt>(UI->getOperand(1))->getZExtValue();
unsigned NewIdx = Idx + I * VecWidth;
Value *V = Builder.CreateExtractElement(LI, Builder.getInt32(NewIdx),
UI->getName());
if (V->getType() != UI->getType())
V = Builder.CreateBitCast(V, UI->getType());
// Replace the old instruction.
UI->replaceAllUsesWith(V);
InstrsToErase.push_back(UI);
}
} }
// Bitcast might not be an Instruction, if the value being loaded is a
// constant. In that case, no need to reorder anything.
if (Instruction *BitcastInst = dyn_cast<Instruction>(Bitcast))
reorder(BitcastInst);
for (auto I : InstrsToErase)
I->eraseFromParent();
} else {
for (unsigned I = 0, E = Chain.size(); I != E; ++I) {
Value *CV = Chain[I];
Value *V =
Builder.CreateExtractElement(LI, Builder.getInt32(I), CV->getName());
if (V->getType() != CV->getType()) { if (V->getType() != CV->getType()) {
V = Builder.CreateBitOrPointerCast(V, CV->getType()); V = Builder.CreateBitOrPointerCast(V, CV->getType());
} }
// Replace the old instruction. // Replace the old instruction.
CV->replaceAllUsesWith(V); CV->replaceAllUsesWith(V);
} }
// Bitcast might not be an Instruction, if the value being loaded is a
// constant. In that case, no need to reorder anything.
arsenmUnsubmitted
Done
ReplyInline Actions

Too many spaces before In?

arsenm: Too many spaces before In?
if (Instruction *BitcastInst = dyn_cast<Instruction>(Bitcast)) if (Instruction *BitcastInst = dyn_cast<Instruction>(Bitcast))
reorder(BitcastInst); reorder(BitcastInst);
}
eraseInstructions(Chain); eraseInstructions(Chain);
++NumVectorInstructions; ++NumVectorInstructions;
NumScalarsVectorized += Chain.size(); NumScalarsVectorized += Chain.size();
return true; return true;
} }
Show All 13 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll

Show First 20 Lines • Show All 661 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_endpgm
%rem = srem i64 %x, %y %rem = srem i64 %x, %y
store i64 %rem, i64 addrspace(1)* %out1 store i64 %rem, i64 addrspace(1)* %out1
ret void ret void
} }
define amdgpu_kernel void @sdivrem_v2i32(<2 x i32> addrspace(1)* %out0, <2 x i32> addrspace(1)* %out1, <2 x i32> %x, <2 x i32> %y) { define amdgpu_kernel void @sdivrem_v2i32(<2 x i32> addrspace(1)* %out0, <2 x i32> addrspace(1)* %out1, <2 x i32> %x, <2 x i32> %y) {
; GFX8-LABEL: sdivrem_v2i32: ; GFX8-LABEL: sdivrem_v2i32:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x18 ; GFX8-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x10
; GFX8-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x10
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0 ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_ashr_i32 s8, s0, 31 ; GFX8-NEXT: s_ashr_i32 s2, s10, 31
; GFX8-NEXT: s_add_i32 s0, s0, s8 ; GFX8-NEXT: s_add_i32 s0, s10, s2
; GFX8-NEXT: s_xor_b32 s9, s0, s8 ; GFX8-NEXT: s_xor_b32 s3, s0, s2
; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s9 ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s3
; GFX8-NEXT: s_ashr_i32 s11, s1, 31 ; GFX8-NEXT: s_sub_i32 s1, 0, s3
; GFX8-NEXT: s_add_i32 s0, s1, s11 ; GFX8-NEXT: s_ashr_i32 s12, s11, 31
; GFX8-NEXT: s_sub_i32 s1, 0, s9 ; GFX8-NEXT: s_add_i32 s0, s11, s12
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_xor_b32 s12, s0, s11 ; GFX8-NEXT: s_xor_b32 s11, s0, s12
; GFX8-NEXT: v_cvt_f32_u32_e32 v2, s12 ; GFX8-NEXT: v_cvt_f32_u32_e32 v2, s11
; GFX8-NEXT: s_ashr_i32 s10, s2, 31 ; GFX8-NEXT: s_ashr_i32 s10, s8, 31
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: s_add_i32 s0, s2, s10 ; GFX8-NEXT: s_add_i32 s0, s8, s10
; GFX8-NEXT: s_xor_b32 s0, s0, s10 ; GFX8-NEXT: s_xor_b32 s0, s0, s10
; GFX8-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX8-NEXT: v_mul_lo_u32 v1, s1, v0 ; GFX8-NEXT: v_mul_lo_u32 v1, s1, v0
; GFX8-NEXT: s_ashr_i32 s2, s3, 31 ; GFX8-NEXT: s_sub_i32 s8, 0, s11
; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0 ; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0
; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2 ; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX8-NEXT: v_mul_lo_u32 v2, v0, s9 ; GFX8-NEXT: v_mul_lo_u32 v2, v0, s3
; GFX8-NEXT: v_add_u32_e32 v3, vcc, 1, v0 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, 1, v0
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s0, v2 ; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s0, v2
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s9, v2 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s3, v2
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX8-NEXT: v_subrev_u32_e64 v3, s[0:1], s9, v2 ; GFX8-NEXT: v_subrev_u32_e64 v3, s[0:1], s3, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX8-NEXT: v_add_u32_e32 v3, vcc, 1, v0 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, 1, v0
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s9, v2 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s3, v2
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX8-NEXT: v_subrev_u32_e64 v3, s[0:1], s9, v2 ; GFX8-NEXT: v_subrev_u32_e64 v3, s[0:1], s3, v2
; GFX8-NEXT: s_sub_i32 s0, 0, s12
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX8-NEXT: v_mul_lo_u32 v3, s0, v1 ; GFX8-NEXT: v_mul_lo_u32 v3, s8, v1
; GFX8-NEXT: s_add_i32 s1, s3, s2 ; GFX8-NEXT: s_xor_b32 s0, s10, s2
; GFX8-NEXT: s_xor_b32 s1, s1, s2 ; GFX8-NEXT: s_ashr_i32 s2, s9, 31
; GFX8-NEXT: s_xor_b32 s0, s10, s8 ; GFX8-NEXT: s_add_i32 s1, s9, s2
; GFX8-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX8-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX8-NEXT: s_xor_b32 s1, s1, s2
; GFX8-NEXT: v_xor_b32_e32 v0, s0, v0 ; GFX8-NEXT: v_xor_b32_e32 v0, s0, v0
; GFX8-NEXT: v_xor_b32_e32 v2, s10, v2 ; GFX8-NEXT: v_xor_b32_e32 v2, s10, v2
; GFX8-NEXT: v_subrev_u32_e32 v0, vcc, s0, v0
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v3 ; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v3
; GFX8-NEXT: v_mul_hi_u32 v1, s1, v1 ; GFX8-NEXT: v_mul_hi_u32 v1, s1, v1
; GFX8-NEXT: v_subrev_u32_e32 v0, vcc, s0, v0
; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s10, v2 ; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s10, v2
; GFX8-NEXT: v_mul_lo_u32 v3, v1, s12 ; GFX8-NEXT: v_mul_lo_u32 v3, v1, s11
; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v1 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v1
; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s1, v3 ; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s1, v3
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s12, v3 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s11, v3
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s12, v3 ; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s11, v3
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v1 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v1
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s12, v3 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s11, v3
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s12, v3 ; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s11, v3
; GFX8-NEXT: s_xor_b32 s0, s2, s11 ; GFX8-NEXT: s_xor_b32 s0, s2, s12
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX8-NEXT: v_xor_b32_e32 v1, s0, v1 ; GFX8-NEXT: v_xor_b32_e32 v1, s0, v1
; GFX8-NEXT: v_mov_b32_e32 v4, s4 ; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_subrev_u32_e32 v1, vcc, s0, v1 ; GFX8-NEXT: v_subrev_u32_e32 v1, vcc, s0, v1
; GFX8-NEXT: v_mov_b32_e32 v5, s5 ; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: v_xor_b32_e32 v3, s2, v3 ; GFX8-NEXT: v_xor_b32_e32 v3, s2, v3
; GFX8-NEXT: flat_store_dwordx2 v[4:5], v[0:1] ; GFX8-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
; GFX8-NEXT: v_mov_b32_e32 v0, s6 ; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, s2, v3 ; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, s2, v3
; GFX8-NEXT: v_mov_b32_e32 v1, s7 ; GFX8-NEXT: v_mov_b32_e32 v1, s7
; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3] ; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-LABEL: sdivrem_v2i32: ; GFX9-LABEL: sdivrem_v2i32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x18 ; GFX9-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x10
; GFX9-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x10
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_ashr_i32 s10, s6, 31 ; GFX9-NEXT: s_ashr_i32 s6, s10, 31
; GFX9-NEXT: s_add_i32 s0, s6, s10 ; GFX9-NEXT: s_add_i32 s0, s10, s6
; GFX9-NEXT: s_xor_b32 s6, s0, s10 ; GFX9-NEXT: s_xor_b32 s7, s0, s6
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s6 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s7
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX9-NEXT: s_ashr_i32 s5, s7, 31 ; GFX9-NEXT: s_ashr_i32 s4, s11, 31
; GFX9-NEXT: s_add_i32 s7, s7, s5 ; GFX9-NEXT: s_add_i32 s5, s11, s4
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: s_xor_b32 s7, s7, s5 ; GFX9-NEXT: s_xor_b32 s5, s5, s4
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s7 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s5
; GFX9-NEXT: s_sub_i32 s11, 0, s6 ; GFX9-NEXT: s_sub_i32 s11, 0, s7
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX9-NEXT: s_ashr_i32 s4, s8, 31 ; GFX9-NEXT: s_ashr_i32 s10, s8, 31
; GFX9-NEXT: s_add_i32 s8, s8, s4 ; GFX9-NEXT: s_add_i32 s8, s8, s10
; GFX9-NEXT: v_mul_lo_u32 v2, s11, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, s11, v0
; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: s_xor_b32 s8, s8, s4 ; GFX9-NEXT: s_xor_b32 s8, s8, s10
; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX9-NEXT: s_sub_i32 s12, 0, s7 ; GFX9-NEXT: s_sub_i32 s11, 0, s5
; GFX9-NEXT: v_mul_lo_u32 v3, s11, v1
; GFX9-NEXT: s_ashr_i32 s11, s9, 31 ; GFX9-NEXT: s_ashr_i32 s11, s9, 31
; GFX9-NEXT: s_add_i32 s9, s9, s11
; GFX9-NEXT: v_add_u32_e32 v0, v0, v2 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v0, s8, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s8, v0
; GFX9-NEXT: v_mul_lo_u32 v2, s12, v1 ; GFX9-NEXT: v_mul_hi_u32 v2, v1, v3
; GFX9-NEXT: s_add_i32 s9, s9, s11
; GFX9-NEXT: s_xor_b32 s9, s9, s11 ; GFX9-NEXT: s_xor_b32 s9, s9, s11
; GFX9-NEXT: v_mul_lo_u32 v3, v0, s6 ; GFX9-NEXT: v_mul_lo_u32 v3, v0, s7
; GFX9-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX9-NEXT: v_add_u32_e32 v4, 1, v0
; GFX9-NEXT: v_sub_u32_e32 v3, s8, v3
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v3
; GFX9-NEXT: v_add_u32_e32 v1, v1, v2 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v2
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; GFX9-NEXT: v_add_u32_e32 v2, 1, v0
; GFX9-NEXT: v_subrev_u32_e32 v4, s6, v3
; GFX9-NEXT: v_mul_hi_u32 v1, s9, v1 ; GFX9-NEXT: v_mul_hi_u32 v1, s9, v1
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; GFX9-NEXT: v_sub_u32_e32 v3, s8, v3
; GFX9-NEXT: v_add_u32_e32 v4, 1, v0 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v3
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v3 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; GFX9-NEXT: v_subrev_u32_e32 v2, s7, v3
; GFX9-NEXT: v_subrev_u32_e32 v4, s6, v3 ; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc ; GFX9-NEXT: v_add_u32_e32 v3, 1, v0
; GFX9-NEXT: v_mul_lo_u32 v3, v1, s7 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v2
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: v_subrev_u32_e32 v3, s7, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX9-NEXT: v_mul_lo_u32 v3, v1, s5
; GFX9-NEXT: v_add_u32_e32 v4, 1, v1 ; GFX9-NEXT: v_add_u32_e32 v4, 1, v1
; GFX9-NEXT: v_xor_b32_e32 v2, s4, v2 ; GFX9-NEXT: s_xor_b32 s6, s10, s6
; GFX9-NEXT: s_xor_b32 s6, s4, s10 ; GFX9-NEXT: s_xor_b32 s4, s11, s4
; GFX9-NEXT: v_sub_u32_e32 v3, s9, v3 ; GFX9-NEXT: v_sub_u32_e32 v3, s9, v3
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s5, v3
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX9-NEXT: v_subrev_u32_e32 v4, s7, v3 ; GFX9-NEXT: v_subrev_u32_e32 v4, s5, v3
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX9-NEXT: v_add_u32_e32 v4, 1, v1 ; GFX9-NEXT: v_add_u32_e32 v4, 1, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s5, v3
; GFX9-NEXT: v_subrev_u32_e32 v2, s4, v2
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX9-NEXT: v_subrev_u32_e32 v4, s7, v3 ; GFX9-NEXT: v_subrev_u32_e32 v4, s5, v3
; GFX9-NEXT: s_xor_b32 s4, s11, s5
; GFX9-NEXT: v_xor_b32_e32 v0, s6, v0 ; GFX9-NEXT: v_xor_b32_e32 v0, s6, v0
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX9-NEXT: v_xor_b32_e32 v1, s4, v1 ; GFX9-NEXT: v_xor_b32_e32 v1, s4, v1
; GFX9-NEXT: v_subrev_u32_e32 v0, s6, v0 ; GFX9-NEXT: v_subrev_u32_e32 v0, s6, v0
; GFX9-NEXT: v_xor_b32_e32 v2, s10, v2
; GFX9-NEXT: v_subrev_u32_e32 v1, s4, v1 ; GFX9-NEXT: v_subrev_u32_e32 v1, s4, v1
; GFX9-NEXT: v_xor_b32_e32 v3, s11, v3 ; GFX9-NEXT: v_xor_b32_e32 v3, s11, v3
; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: v_subrev_u32_e32 v2, s10, v2
; GFX9-NEXT: v_subrev_u32_e32 v3, s11, v3 ; GFX9-NEXT: v_subrev_u32_e32 v3, s11, v3
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1] ; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX9-NEXT: global_store_dwordx2 v4, v[2:3], s[2:3] ; GFX9-NEXT: global_store_dwordx2 v4, v[2:3], s[2:3]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: sdivrem_v2i32: ; GFX10-LABEL: sdivrem_v2i32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x18 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x10
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_ashr_i32 s2, s0, 31 ; GFX10-NEXT: s_ashr_i32 s8, s2, 31
; GFX10-NEXT: s_ashr_i32 s3, s1, 31 ; GFX10-NEXT: s_ashr_i32 s9, s3, 31
; GFX10-NEXT: s_add_i32 s0, s0, s2 ; GFX10-NEXT: s_add_i32 s2, s2, s8
; GFX10-NEXT: s_add_i32 s1, s1, s3 ; GFX10-NEXT: s_add_i32 s3, s3, s9
; GFX10-NEXT: s_xor_b32 s8, s0, s2 ; GFX10-NEXT: s_xor_b32 s2, s2, s8
; GFX10-NEXT: s_xor_b32 s9, s1, s3 ; GFX10-NEXT: s_xor_b32 s3, s3, s9
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s8 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s9 ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s3
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x10 ; GFX10-NEXT: s_sub_i32 s6, 0, s2
; GFX10-NEXT: s_sub_i32 s6, 0, s8 ; GFX10-NEXT: s_sub_i32 s7, 0, s3
; GFX10-NEXT: s_sub_i32 s7, 0, s9 ; GFX10-NEXT: s_ashr_i32 s10, s0, 31
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX10-NEXT: s_ashr_i32 s11, s1, 31
; GFX10-NEXT: s_add_i32 s0, s0, s10
; GFX10-NEXT: s_add_i32 s1, s1, s11
; GFX10-NEXT: s_xor_b32 s0, s0, s10
; GFX10-NEXT: s_xor_b32 s1, s1, s11
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 ; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_ashr_i32 s10, s0, 31
; GFX10-NEXT: s_ashr_i32 s11, s1, 31
; GFX10-NEXT: s_add_i32 s0, s0, s10
; GFX10-NEXT: v_mul_lo_u32 v2, s6, v0 ; GFX10-NEXT: v_mul_lo_u32 v2, s6, v0
; GFX10-NEXT: v_mul_lo_u32 v3, s7, v1 ; GFX10-NEXT: v_mul_lo_u32 v3, s7, v1
; GFX10-NEXT: s_add_i32 s1, s1, s11
; GFX10-NEXT: s_xor_b32 s0, s0, s10
; GFX10-NEXT: s_xor_b32 s1, s1, s11
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX10-NEXT: v_mul_hi_u32 v2, v0, v2 ; GFX10-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX10-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX10-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2 ; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2
; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v3 ; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v3
; GFX10-NEXT: v_mul_hi_u32 v0, s0, v0 ; GFX10-NEXT: v_mul_hi_u32 v0, s0, v0
; GFX10-NEXT: v_mul_hi_u32 v1, s1, v1 ; GFX10-NEXT: v_mul_hi_u32 v1, s1, v1
; GFX10-NEXT: v_mul_lo_u32 v2, v0, s8 ; GFX10-NEXT: v_mul_lo_u32 v2, v0, s2
; GFX10-NEXT: v_mul_lo_u32 v3, v1, s9 ; GFX10-NEXT: v_mul_lo_u32 v3, v1, s3
; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v0
; GFX10-NEXT: v_add_nc_u32_e32 v5, 1, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v5, 1, v1
; GFX10-NEXT: v_sub_nc_u32_e32 v2, s0, v2 ; GFX10-NEXT: v_sub_nc_u32_e32 v2, s0, v2
; GFX10-NEXT: v_sub_nc_u32_e32 v3, s1, v3 ; GFX10-NEXT: v_sub_nc_u32_e32 v3, s1, v3
; GFX10-NEXT: s_xor_b32 s1, s10, s2 ; GFX10-NEXT: s_xor_b32 s1, s10, s8
; GFX10-NEXT: v_subrev_nc_u32_e32 v6, s8, v2 ; GFX10-NEXT: v_subrev_nc_u32_e32 v6, s2, v2
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s9, v3 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s3, v3
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s8, v2 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s2, v2
; GFX10-NEXT: v_subrev_nc_u32_e32 v7, s9, v3 ; GFX10-NEXT: v_subrev_nc_u32_e32 v7, s3, v3
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v6, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v6, s0
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
; GFX10-NEXT: v_add_nc_u32_e32 v5, 1, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v5, 1, v1
; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s8, v2 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s2, v2
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s9, v3 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s3, v3
; GFX10-NEXT: v_subrev_nc_u32_e32 v6, s8, v2 ; GFX10-NEXT: v_subrev_nc_u32_e32 v6, s2, v2
; GFX10-NEXT: v_subrev_nc_u32_e32 v7, s9, v3 ; GFX10-NEXT: v_subrev_nc_u32_e32 v7, s3, v3
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v6, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v6, s0
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
; GFX10-NEXT: s_xor_b32 s0, s11, s3 ; GFX10-NEXT: s_xor_b32 s0, s11, s9
; GFX10-NEXT: v_xor_b32_e32 v0, s1, v0 ; GFX10-NEXT: v_xor_b32_e32 v0, s1, v0
; GFX10-NEXT: v_xor_b32_e32 v1, s0, v1 ; GFX10-NEXT: v_xor_b32_e32 v1, s0, v1
; GFX10-NEXT: v_xor_b32_e32 v2, s10, v2 ; GFX10-NEXT: v_xor_b32_e32 v2, s10, v2
; GFX10-NEXT: v_xor_b32_e32 v3, s11, v3 ; GFX10-NEXT: v_xor_b32_e32 v3, s11, v3
; GFX10-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_subrev_nc_u32_e32 v0, s1, v0 ; GFX10-NEXT: v_subrev_nc_u32_e32 v0, s1, v0
; GFX10-NEXT: v_subrev_nc_u32_e32 v1, s0, v1 ; GFX10-NEXT: v_subrev_nc_u32_e32 v1, s0, v1
; GFX10-NEXT: v_subrev_nc_u32_e32 v2, s10, v2 ; GFX10-NEXT: v_subrev_nc_u32_e32 v2, s10, v2
; GFX10-NEXT: v_subrev_nc_u32_e32 v3, s11, v3 ; GFX10-NEXT: v_subrev_nc_u32_e32 v3, s11, v3
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_store_dwordx2 v4, v[0:1], s[4:5] ; GFX10-NEXT: global_store_dwordx2 v4, v[0:1], s[4:5]
; GFX10-NEXT: global_store_dwordx2 v4, v[2:3], s[6:7] ; GFX10-NEXT: global_store_dwordx2 v4, v[2:3], s[6:7]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%div = sdiv <2 x i32> %x, %y %div = sdiv <2 x i32> %x, %y
store <2 x i32> %div, <2 x i32> addrspace(1)* %out0 store <2 x i32> %div, <2 x i32> addrspace(1)* %out0
%rem = srem <2 x i32> %x, %y %rem = srem <2 x i32> %x, %y
store <2 x i32> %rem, <2 x i32> addrspace(1)* %out1 store <2 x i32> %rem, <2 x i32> addrspace(1)* %out1
ret void ret void
} }
define amdgpu_kernel void @sdivrem_v4i32(<4 x i32> addrspace(1)* %out0, <4 x i32> addrspace(1)* %out1, <4 x i32> %x, <4 x i32> %y) { define amdgpu_kernel void @sdivrem_v4i32(<4 x i32> addrspace(1)* %out0, <4 x i32> addrspace(1)* %out1, <4 x i32> %x, <4 x i32> %y) {
; GFX8-LABEL: sdivrem_v4i32: ; GFX8-LABEL: sdivrem_v4i32:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x20 ; GFX8-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x10
; GFX8-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x10 ; GFX8-NEXT: v_mov_b32_e32 v2, 0x4f7ffffe
; GFX8-NEXT: v_mov_b32_e32 v3, 0x4f7ffffe
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0 ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_ashr_i32 s12, s0, 31 ; GFX8-NEXT: s_ashr_i32 s2, s12, 31
; GFX8-NEXT: s_add_i32 s0, s0, s12 ; GFX8-NEXT: s_add_i32 s0, s12, s2
; GFX8-NEXT: s_xor_b32 s13, s0, s12 ; GFX8-NEXT: s_xor_b32 s3, s0, s2
; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s13 ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s3
; GFX8-NEXT: s_ashr_i32 s15, s1, 31 ; GFX8-NEXT: s_sub_i32 s1, 0, s3
; GFX8-NEXT: s_add_i32 s0, s1, s15 ; GFX8-NEXT: s_ashr_i32 s16, s13, 31
; GFX8-NEXT: s_sub_i32 s1, 0, s13 ; GFX8-NEXT: s_add_i32 s0, s13, s16
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_xor_b32 s16, s0, s15 ; GFX8-NEXT: s_xor_b32 s13, s0, s16
; GFX8-NEXT: v_cvt_f32_u32_e32 v2, s16 ; GFX8-NEXT: v_cvt_f32_u32_e32 v3, s13
; GFX8-NEXT: s_ashr_i32 s14, s8, 31 ; GFX8-NEXT: s_ashr_i32 s12, s8, 31
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: s_add_i32 s0, s8, s14 ; GFX8-NEXT: s_add_i32 s0, s8, s12
; GFX8-NEXT: s_xor_b32 s0, s0, s14 ; GFX8-NEXT: s_xor_b32 s0, s0, s12
; GFX8-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX8-NEXT: v_mul_lo_u32 v1, s1, v0 ; GFX8-NEXT: v_mul_lo_u32 v1, s1, v0
; GFX8-NEXT: s_ashr_i32 s8, s9, 31
; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0 ; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0
; GFX8-NEXT: v_mul_f32_e32 v1, v2, v3 ; GFX8-NEXT: v_mul_f32_e32 v1, v3, v2
; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX8-NEXT: v_mul_lo_u32 v2, v0, s13 ; GFX8-NEXT: v_mul_lo_u32 v3, v0, s3
; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v0 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v0
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s0, v2 ; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s0, v3
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s13, v2 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s3, v3
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s13, v2 ; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s3, v3
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v0 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v0
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s13, v2 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s3, v3
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s13, v2 ; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s3, v3
; GFX8-NEXT: s_sub_i32 s0, 0, s16 ; GFX8-NEXT: s_sub_i32 s0, 0, s13
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX8-NEXT: v_mul_lo_u32 v4, s0, v1 ; GFX8-NEXT: v_mul_lo_u32 v4, s0, v1
; GFX8-NEXT: s_add_i32 s1, s9, s8 ; GFX8-NEXT: s_xor_b32 s0, s12, s2
; GFX8-NEXT: s_xor_b32 s1, s1, s8 ; GFX8-NEXT: s_ashr_i32 s2, s9, 31
; GFX8-NEXT: s_xor_b32 s0, s14, s12 ; GFX8-NEXT: s_add_i32 s1, s9, s2
; GFX8-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX8-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX8-NEXT: s_xor_b32 s1, s1, s2
; GFX8-NEXT: v_xor_b32_e32 v0, s0, v0 ; GFX8-NEXT: v_xor_b32_e32 v0, s0, v0
; GFX8-NEXT: v_xor_b32_e32 v2, s14, v2 ; GFX8-NEXT: v_xor_b32_e32 v3, s12, v3
; GFX8-NEXT: s_ashr_i32 s9, s2, 31
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v4 ; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v4
; GFX8-NEXT: v_mul_hi_u32 v1, s1, v1 ; GFX8-NEXT: v_mul_hi_u32 v1, s1, v1
; GFX8-NEXT: s_ashr_i32 s3, s14, 31
; GFX8-NEXT: v_subrev_u32_e32 v0, vcc, s0, v0 ; GFX8-NEXT: v_subrev_u32_e32 v0, vcc, s0, v0
; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s14, v2 ; GFX8-NEXT: v_mul_lo_u32 v5, v1, s13
; GFX8-NEXT: v_mul_lo_u32 v5, v1, s16 ; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s12, v3
; GFX8-NEXT: s_add_i32 s0, s2, s9 ; GFX8-NEXT: s_add_i32 s0, s14, s3
; GFX8-NEXT: s_xor_b32 s2, s0, s9 ; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s1, v5
; GFX8-NEXT: s_ashr_i32 s12, s10, 31
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s1, v5
; GFX8-NEXT: v_add_u32_e32 v5, vcc, 1, v1 ; GFX8-NEXT: v_add_u32_e32 v5, vcc, 1, v1
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s16, v2 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s13, v3
; GFX8-NEXT: s_xor_b32 s8, s0, s3
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX8-NEXT: v_cvt_f32_u32_e32 v5, s2 ; GFX8-NEXT: v_cvt_f32_u32_e32 v5, s8
; GFX8-NEXT: v_subrev_u32_e64 v6, s[0:1], s16, v2 ; GFX8-NEXT: v_subrev_u32_e64 v6, s[0:1], s13, v3
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
; GFX8-NEXT: v_rcp_iflag_f32_e32 v5, v5 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v5, v5
; GFX8-NEXT: v_add_u32_e32 v6, vcc, 1, v1 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, 1, v1
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s16, v2 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s13, v3
; GFX8-NEXT: v_mul_f32_e32 v5, v5, v3 ; GFX8-NEXT: v_mul_f32_e32 v5, v5, v2
; GFX8-NEXT: v_cvt_u32_f32_e32 v5, v5 ; GFX8-NEXT: v_cvt_u32_f32_e32 v5, v5
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
; GFX8-NEXT: v_subrev_u32_e64 v6, s[0:1], s16, v2 ; GFX8-NEXT: v_subrev_u32_e64 v6, s[0:1], s13, v3
; GFX8-NEXT: s_sub_i32 s0, 0, s2 ; GFX8-NEXT: s_sub_i32 s0, 0, s8
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
; GFX8-NEXT: v_mul_lo_u32 v6, s0, v5 ; GFX8-NEXT: v_mul_lo_u32 v6, s0, v5
; GFX8-NEXT: s_add_i32 s1, s10, s12 ; GFX8-NEXT: s_ashr_i32 s9, s10, 31
; GFX8-NEXT: s_xor_b32 s1, s1, s12 ; GFX8-NEXT: s_add_i32 s1, s10, s9
; GFX8-NEXT: s_xor_b32 s0, s8, s15 ; GFX8-NEXT: s_xor_b32 s1, s1, s9
; GFX8-NEXT: v_mul_hi_u32 v6, v5, v6 ; GFX8-NEXT: v_mul_hi_u32 v6, v5, v6
; GFX8-NEXT: v_xor_b32_e32 v2, s8, v2 ; GFX8-NEXT: s_xor_b32 s0, s2, s16
; GFX8-NEXT: v_xor_b32_e32 v3, s2, v3
; GFX8-NEXT: v_xor_b32_e32 v1, s0, v1 ; GFX8-NEXT: v_xor_b32_e32 v1, s0, v1
; GFX8-NEXT: v_subrev_u32_e32 v1, vcc, s0, v1
; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v6 ; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v6
; GFX8-NEXT: v_mul_hi_u32 v6, s1, v5 ; GFX8-NEXT: v_mul_hi_u32 v6, s1, v5
; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s8, v2 ; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s2, v3
; GFX8-NEXT: s_ashr_i32 s8, s3, 31 ; GFX8-NEXT: s_ashr_i32 s2, s15, 31
; GFX8-NEXT: v_mul_lo_u32 v7, v6, s2 ; GFX8-NEXT: v_mul_lo_u32 v7, v6, s8
; GFX8-NEXT: s_add_i32 s0, s3, s8 ; GFX8-NEXT: v_subrev_u32_e32 v1, vcc, s0, v1
; GFX8-NEXT: s_xor_b32 s3, s0, s8 ; GFX8-NEXT: s_add_i32 s0, s15, s2
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s1, v7 ; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s1, v7
; GFX8-NEXT: v_add_u32_e32 v7, vcc, 1, v6 ; GFX8-NEXT: v_add_u32_e32 v7, vcc, 1, v6
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s2, v2 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s8, v3
; GFX8-NEXT: s_xor_b32 s10, s0, s2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
; GFX8-NEXT: v_cvt_f32_u32_e32 v7, s3 ; GFX8-NEXT: v_cvt_f32_u32_e32 v7, s10
; GFX8-NEXT: v_subrev_u32_e64 v8, s[0:1], s2, v2 ; GFX8-NEXT: v_subrev_u32_e64 v8, s[0:1], s8, v3
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
; GFX8-NEXT: v_rcp_iflag_f32_e32 v7, v7 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v7, v7
; GFX8-NEXT: v_add_u32_e32 v8, vcc, 1, v6 ; GFX8-NEXT: v_add_u32_e32 v8, vcc, 1, v6
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s2, v2 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s8, v3
; GFX8-NEXT: v_mul_f32_e32 v3, v7, v3 ; GFX8-NEXT: v_mul_f32_e32 v2, v7, v2
; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX8-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX8-NEXT: v_subrev_u32_e64 v7, s[0:1], s2, v2 ; GFX8-NEXT: v_subrev_u32_e64 v7, s[0:1], s8, v3
; GFX8-NEXT: s_sub_i32 s0, 0, s3 ; GFX8-NEXT: s_sub_i32 s0, 0, s10
; GFX8-NEXT: v_cndmask_b32_e32 v7, v2, v7, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
; GFX8-NEXT: v_mul_lo_u32 v2, s0, v3 ; GFX8-NEXT: v_mul_lo_u32 v7, s0, v2
; GFX8-NEXT: s_ashr_i32 s2, s11, 31 ; GFX8-NEXT: s_xor_b32 s0, s9, s3
; GFX8-NEXT: s_add_i32 s1, s11, s2 ; GFX8-NEXT: s_ashr_i32 s3, s11, 31
; GFX8-NEXT: s_add_i32 s1, s11, s3
; GFX8-NEXT: v_mul_hi_u32 v7, v2, v7
; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
; GFX8-NEXT: v_mul_hi_u32 v2, v3, v2 ; GFX8-NEXT: s_xor_b32 s1, s1, s3
; GFX8-NEXT: s_xor_b32 s1, s1, s2
; GFX8-NEXT: s_xor_b32 s0, s12, s9
; GFX8-NEXT: v_xor_b32_e32 v6, s0, v6 ; GFX8-NEXT: v_xor_b32_e32 v6, s0, v6
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v2 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v7
; GFX8-NEXT: v_mul_hi_u32 v3, s1, v2 ; GFX8-NEXT: v_mul_hi_u32 v7, s1, v2
; GFX8-NEXT: v_xor_b32_e32 v3, s9, v3
; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s0, v6 ; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s0, v6
; GFX8-NEXT: v_xor_b32_e32 v6, s12, v7 ; GFX8-NEXT: v_mul_lo_u32 v8, v7, s10
; GFX8-NEXT: v_mul_lo_u32 v7, v3, s3 ; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, s9, v3
; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, s12, v6 ; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s1, v8
; GFX8-NEXT: v_add_u32_e32 v8, vcc, 1, v3 ; GFX8-NEXT: v_add_u32_e32 v8, vcc, 1, v7
; GFX8-NEXT: v_sub_u32_e32 v7, vcc, s1, v7 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s10, v3
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s3, v7
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
; GFX8-NEXT: v_subrev_u32_e64 v8, s[0:1], s3, v7
; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
; GFX8-NEXT: v_add_u32_e32 v8, vcc, 1, v3 ; GFX8-NEXT: v_subrev_u32_e64 v8, s[0:1], s10, v3
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s3, v7
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
; GFX8-NEXT: v_subrev_u32_e64 v8, s[0:1], s3, v7 ; GFX8-NEXT: v_add_u32_e32 v8, vcc, 1, v7
; GFX8-NEXT: s_xor_b32 s0, s2, s8 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s10, v3
; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
; GFX8-NEXT: v_xor_b32_e32 v3, s0, v3 ; GFX8-NEXT: v_subrev_u32_e64 v8, s[0:1], s10, v3
; GFX8-NEXT: v_cndmask_b32_e32 v8, v3, v8, vcc
; GFX8-NEXT: s_xor_b32 s0, s3, s2
; GFX8-NEXT: v_xor_b32_e32 v3, s0, v7
; GFX8-NEXT: v_xor_b32_e32 v7, s3, v8
; GFX8-NEXT: v_mov_b32_e32 v9, s5 ; GFX8-NEXT: v_mov_b32_e32 v9, s5
; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, s0, v3 ; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, s0, v3
; GFX8-NEXT: v_mov_b32_e32 v8, s4 ; GFX8-NEXT: v_mov_b32_e32 v8, s4
; GFX8-NEXT: v_xor_b32_e32 v7, s2, v7
; GFX8-NEXT: flat_store_dwordx4 v[8:9], v[0:3] ; GFX8-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
; GFX8-NEXT: v_subrev_u32_e32 v7, vcc, s2, v7 ; GFX8-NEXT: v_subrev_u32_e32 v7, vcc, s3, v7
; GFX8-NEXT: v_mov_b32_e32 v0, s6 ; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: v_mov_b32_e32 v1, s7 ; GFX8-NEXT: v_mov_b32_e32 v1, s7
; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[4:7] ; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-LABEL: sdivrem_v4i32: ; GFX9-LABEL: sdivrem_v4i32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[12:15], s[4:5], 0x20 ; GFX9-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x10
; GFX9-NEXT: v_mov_b32_e32 v2, 0x4f7ffffe ; GFX9-NEXT: v_mov_b32_e32 v2, 0x4f7ffffe
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_ashr_i32 s6, s12, 31 ; GFX9-NEXT: s_ashr_i32 s6, s12, 31
; GFX9-NEXT: s_add_i32 s0, s12, s6 ; GFX9-NEXT: s_add_i32 s0, s12, s6
; GFX9-NEXT: s_xor_b32 s7, s0, s6 ; GFX9-NEXT: s_xor_b32 s7, s0, s6
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s7 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s7
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX9-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x10 ; GFX9-NEXT: s_ashr_i32 s5, s13, 31
; GFX9-NEXT: s_ashr_i32 s4, s13, 31 ; GFX9-NEXT: s_add_i32 s12, s13, s5
; GFX9-NEXT: s_add_i32 s5, s13, s4
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: s_sub_i32 s12, 0, s7 ; GFX9-NEXT: s_xor_b32 s12, s12, s5
; GFX9-NEXT: s_xor_b32 s5, s5, s4 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s12
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s5 ; GFX9-NEXT: s_sub_i32 s13, 0, s7
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: s_sub_i32 s13, 0, s5
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX9-NEXT: v_mul_lo_u32 v3, s12, v0 ; GFX9-NEXT: s_ashr_i32 s4, s8, 31
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_add_i32 s8, s8, s4
; GFX9-NEXT: s_ashr_i32 s12, s8, 31 ; GFX9-NEXT: v_mul_lo_u32 v3, s13, v0
; GFX9-NEXT: s_add_i32 s8, s8, s12
; GFX9-NEXT: s_xor_b32 s8, s8, s12
; GFX9-NEXT: v_mul_hi_u32 v3, v0, v3
; GFX9-NEXT: v_mul_f32_e32 v1, v1, v2 ; GFX9-NEXT: v_mul_f32_e32 v1, v1, v2
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: s_xor_b32 s6, s12, s6 ; GFX9-NEXT: s_xor_b32 s8, s8, s4
; GFX9-NEXT: v_add_u32_e32 v0, v0, v3 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, v3
; GFX9-NEXT: v_mul_hi_u32 v0, s8, v0 ; GFX9-NEXT: s_sub_i32 s16, 0, s12
; GFX9-NEXT: v_mul_lo_u32 v3, s13, v1
; GFX9-NEXT: s_ashr_i32 s13, s9, 31 ; GFX9-NEXT: s_ashr_i32 s13, s9, 31
; GFX9-NEXT: s_add_i32 s9, s9, s13 ; GFX9-NEXT: s_add_i32 s9, s9, s13
; GFX9-NEXT: v_add_u32_e32 v0, v0, v3
; GFX9-NEXT: v_mul_hi_u32 v0, s8, v0
; GFX9-NEXT: v_mul_lo_u32 v3, s16, v1
; GFX9-NEXT: s_xor_b32 s9, s9, s13
; GFX9-NEXT: s_xor_b32 s6, s4, s6
; GFX9-NEXT: v_mul_lo_u32 v4, v0, s7 ; GFX9-NEXT: v_mul_lo_u32 v4, v0, s7
; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX9-NEXT: v_add_u32_e32 v5, 1, v0 ; GFX9-NEXT: v_add_u32_e32 v5, 1, v0
; GFX9-NEXT: s_xor_b32 s4, s13, s4 ; GFX9-NEXT: s_xor_b32 s5, s13, s5
; GFX9-NEXT: v_sub_u32_e32 v4, s8, v4 ; GFX9-NEXT: v_sub_u32_e32 v4, s8, v4
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v4 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v4
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
; GFX9-NEXT: v_subrev_u32_e32 v5, s7, v4 ; GFX9-NEXT: v_subrev_u32_e32 v5, s7, v4
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
; GFX9-NEXT: v_mul_hi_u32 v1, s9, v1
; GFX9-NEXT: v_add_u32_e32 v5, 1, v0 ; GFX9-NEXT: v_add_u32_e32 v5, 1, v0
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v4 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v4
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
; GFX9-NEXT: v_subrev_u32_e32 v5, s7, v4 ; GFX9-NEXT: v_subrev_u32_e32 v5, s7, v4
; GFX9-NEXT: s_xor_b32 s7, s9, s13
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_mul_hi_u32 v1, s7, v1
; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
; GFX9-NEXT: v_mul_lo_u32 v5, v1, s12
; GFX9-NEXT: v_xor_b32_e32 v3, s4, v3
; GFX9-NEXT: v_xor_b32_e32 v0, s6, v0 ; GFX9-NEXT: v_xor_b32_e32 v0, s6, v0
; GFX9-NEXT: v_subrev_u32_e32 v4, s4, v3
; GFX9-NEXT: s_ashr_i32 s4, s14, 31
; GFX9-NEXT: v_subrev_u32_e32 v0, s6, v0 ; GFX9-NEXT: v_subrev_u32_e32 v0, s6, v0
; GFX9-NEXT: v_mul_lo_u32 v5, v1, s5 ; GFX9-NEXT: s_add_i32 s6, s14, s4
; GFX9-NEXT: v_xor_b32_e32 v3, s12, v3 ; GFX9-NEXT: s_xor_b32 s6, s6, s4
; GFX9-NEXT: s_ashr_i32 s6, s14, 31 ; GFX9-NEXT: v_sub_u32_e32 v3, s9, v5
; GFX9-NEXT: v_subrev_u32_e32 v4, s12, v3 ; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s6
; GFX9-NEXT: v_sub_u32_e32 v3, s7, v5
; GFX9-NEXT: s_add_i32 s7, s14, s6
; GFX9-NEXT: s_xor_b32 s7, s7, s6
; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s7
; GFX9-NEXT: v_add_u32_e32 v6, 1, v1 ; GFX9-NEXT: v_add_u32_e32 v6, 1, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s5, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s12, v3
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v5 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v5
; GFX9-NEXT: v_subrev_u32_e32 v6, s5, v3 ; GFX9-NEXT: v_subrev_u32_e32 v6, s12, v3
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
; GFX9-NEXT: v_add_u32_e32 v6, 1, v1 ; GFX9-NEXT: v_add_u32_e32 v6, 1, v1
; GFX9-NEXT: v_mul_f32_e32 v5, v5, v2 ; GFX9-NEXT: v_mul_f32_e32 v5, v5, v2
; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5 ; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s5, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s12, v3
; GFX9-NEXT: s_sub_i32 s8, 0, s7 ; GFX9-NEXT: s_sub_i32 s7, 0, s6
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
; GFX9-NEXT: v_mul_lo_u32 v6, s8, v5 ; GFX9-NEXT: v_mul_lo_u32 v6, s7, v5
; GFX9-NEXT: v_xor_b32_e32 v1, s4, v1 ; GFX9-NEXT: v_xor_b32_e32 v1, s5, v1
; GFX9-NEXT: v_subrev_u32_e32 v1, s4, v1 ; GFX9-NEXT: v_subrev_u32_e32 v1, s5, v1
; GFX9-NEXT: s_ashr_i32 s4, s15, 31 ; GFX9-NEXT: s_ashr_i32 s5, s15, 31
; GFX9-NEXT: s_add_i32 s9, s15, s4 ; GFX9-NEXT: s_add_i32 s9, s15, s5
; GFX9-NEXT: v_mul_hi_u32 v6, v5, v6 ; GFX9-NEXT: v_mul_hi_u32 v6, v5, v6
; GFX9-NEXT: s_xor_b32 s9, s9, s4 ; GFX9-NEXT: s_xor_b32 s9, s9, s5
; GFX9-NEXT: v_cvt_f32_u32_e32 v8, s9 ; GFX9-NEXT: v_cvt_f32_u32_e32 v8, s9
; GFX9-NEXT: v_subrev_u32_e32 v7, s5, v3 ; GFX9-NEXT: s_ashr_i32 s7, s10, 31
; GFX9-NEXT: s_ashr_i32 s5, s10, 31 ; GFX9-NEXT: s_add_i32 s8, s10, s7
; GFX9-NEXT: s_add_i32 s8, s10, s5 ; GFX9-NEXT: s_xor_b32 s8, s8, s7
; GFX9-NEXT: s_xor_b32 s8, s8, s5
; GFX9-NEXT: v_add_u32_e32 v5, v5, v6 ; GFX9-NEXT: v_add_u32_e32 v5, v5, v6
; GFX9-NEXT: v_mul_hi_u32 v6, s8, v5 ; GFX9-NEXT: v_mul_hi_u32 v6, s8, v5
; GFX9-NEXT: v_rcp_iflag_f32_e32 v8, v8 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v8, v8
; GFX9-NEXT: v_subrev_u32_e32 v7, s12, v3
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
; GFX9-NEXT: v_xor_b32_e32 v3, s13, v3 ; GFX9-NEXT: v_mul_lo_u32 v7, v6, s6
; GFX9-NEXT: v_mul_lo_u32 v7, v6, s7
; GFX9-NEXT: v_mul_f32_e32 v2, v8, v2 ; GFX9-NEXT: v_mul_f32_e32 v2, v8, v2
; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX9-NEXT: v_xor_b32_e32 v3, s13, v3
; GFX9-NEXT: v_subrev_u32_e32 v5, s13, v3 ; GFX9-NEXT: v_subrev_u32_e32 v5, s13, v3
; GFX9-NEXT: v_sub_u32_e32 v3, s8, v7 ; GFX9-NEXT: v_sub_u32_e32 v3, s8, v7
; GFX9-NEXT: s_sub_i32 s8, 0, s9 ; GFX9-NEXT: s_sub_i32 s8, 0, s9
; GFX9-NEXT: v_mul_lo_u32 v8, s8, v2 ; GFX9-NEXT: v_mul_lo_u32 v8, s8, v2
; GFX9-NEXT: v_add_u32_e32 v7, 1, v6 ; GFX9-NEXT: v_add_u32_e32 v7, 1, v6
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v3
; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
; GFX9-NEXT: v_subrev_u32_e32 v7, s7, v3 ; GFX9-NEXT: v_subrev_u32_e32 v7, s6, v3
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
; GFX9-NEXT: v_mul_hi_u32 v8, v2, v8 ; GFX9-NEXT: v_mul_hi_u32 v8, v2, v8
; GFX9-NEXT: v_add_u32_e32 v7, 1, v6 ; GFX9-NEXT: v_add_u32_e32 v7, 1, v6
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v3
; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
; GFX9-NEXT: v_subrev_u32_e32 v7, s7, v3 ; GFX9-NEXT: v_subrev_u32_e32 v7, s6, v3
; GFX9-NEXT: s_ashr_i32 s7, s11, 31 ; GFX9-NEXT: s_ashr_i32 s6, s11, 31
; GFX9-NEXT: s_add_i32 s8, s11, s7 ; GFX9-NEXT: s_add_i32 s8, s11, s6
; GFX9-NEXT: s_xor_b32 s8, s8, s7 ; GFX9-NEXT: s_xor_b32 s8, s8, s6
; GFX9-NEXT: v_add_u32_e32 v2, v2, v8 ; GFX9-NEXT: v_add_u32_e32 v2, v2, v8
; GFX9-NEXT: v_mul_hi_u32 v8, s8, v2 ; GFX9-NEXT: v_mul_hi_u32 v8, s8, v2
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
; GFX9-NEXT: s_xor_b32 s6, s5, s6
; GFX9-NEXT: v_xor_b32_e32 v3, s5, v3
; GFX9-NEXT: v_mul_lo_u32 v7, v8, s9
; GFX9-NEXT: v_xor_b32_e32 v2, s6, v6
; GFX9-NEXT: v_subrev_u32_e32 v6, s5, v3
; GFX9-NEXT: s_xor_b32 s4, s7, s4 ; GFX9-NEXT: s_xor_b32 s4, s7, s4
; GFX9-NEXT: v_xor_b32_e32 v3, s7, v3
; GFX9-NEXT: v_mul_lo_u32 v7, v8, s9
; GFX9-NEXT: v_xor_b32_e32 v2, s4, v6
; GFX9-NEXT: v_subrev_u32_e32 v6, s7, v3
; GFX9-NEXT: v_subrev_u32_e32 v2, s4, v2
; GFX9-NEXT: v_sub_u32_e32 v3, s8, v7 ; GFX9-NEXT: v_sub_u32_e32 v3, s8, v7
; GFX9-NEXT: v_add_u32_e32 v7, 1, v8 ; GFX9-NEXT: v_add_u32_e32 v7, 1, v8
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v3
; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc
; GFX9-NEXT: v_subrev_u32_e32 v8, s9, v3 ; GFX9-NEXT: v_subrev_u32_e32 v8, s9, v3
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
; GFX9-NEXT: v_add_u32_e32 v8, 1, v7 ; GFX9-NEXT: v_add_u32_e32 v8, 1, v7
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v3
; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
; GFX9-NEXT: v_subrev_u32_e32 v8, s9, v3 ; GFX9-NEXT: v_subrev_u32_e32 v8, s9, v3
; GFX9-NEXT: s_xor_b32 s4, s6, s5
; GFX9-NEXT: v_cndmask_b32_e32 v8, v3, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v8, v3, v8, vcc
; GFX9-NEXT: v_xor_b32_e32 v3, s4, v7 ; GFX9-NEXT: v_xor_b32_e32 v3, s4, v7
; GFX9-NEXT: v_subrev_u32_e32 v2, s6, v2
; GFX9-NEXT: v_subrev_u32_e32 v3, s4, v3 ; GFX9-NEXT: v_subrev_u32_e32 v3, s4, v3
; GFX9-NEXT: v_xor_b32_e32 v7, s7, v8 ; GFX9-NEXT: v_xor_b32_e32 v7, s6, v8
; GFX9-NEXT: v_mov_b32_e32 v8, 0 ; GFX9-NEXT: v_mov_b32_e32 v8, 0
; GFX9-NEXT: v_subrev_u32_e32 v7, s7, v7 ; GFX9-NEXT: v_subrev_u32_e32 v7, s6, v7
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1] ; GFX9-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1]
; GFX9-NEXT: global_store_dwordx4 v8, v[4:7], s[2:3] ; GFX9-NEXT: global_store_dwordx4 v8, v[4:7], s[2:3]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: sdivrem_v4i32: ; GFX10-LABEL: sdivrem_v4i32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x10
; GFX10-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x20
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x10
; GFX10-NEXT: v_mov_b32_e32 v4, 0x4f7ffffe ; GFX10-NEXT: v_mov_b32_e32 v4, 0x4f7ffffe
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_ashr_i32 s12, s8, 31 ; GFX10-NEXT: s_ashr_i32 s0, s12, 31
; GFX10-NEXT: s_ashr_i32 s14, s10, 31 ; GFX10-NEXT: s_ashr_i32 s2, s14, 31
; GFX10-NEXT: s_add_i32 s6, s8, s12 ; GFX10-NEXT: s_add_i32 s6, s12, s0
; GFX10-NEXT: s_add_i32 s8, s10, s14 ; GFX10-NEXT: s_add_i32 s12, s14, s2
; GFX10-NEXT: s_xor_b32 s10, s6, s12 ; GFX10-NEXT: s_xor_b32 s14, s6, s0
; GFX10-NEXT: s_ashr_i32 s13, s9, 31 ; GFX10-NEXT: s_ashr_i32 s1, s13, 31
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s10 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s14
; GFX10-NEXT: s_ashr_i32 s15, s11, 31 ; GFX10-NEXT: s_ashr_i32 s3, s15, 31
; GFX10-NEXT: s_add_i32 s7, s9, s13 ; GFX10-NEXT: s_add_i32 s7, s13, s1
; GFX10-NEXT: s_add_i32 s9, s11, s15 ; GFX10-NEXT: s_add_i32 s13, s15, s3
; GFX10-NEXT: s_xor_b32 s11, s7, s13 ; GFX10-NEXT: s_xor_b32 s15, s7, s1
; GFX10-NEXT: s_xor_b32 s8, s8, s14 ; GFX10-NEXT: s_xor_b32 s12, s12, s2
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s15
; GFX10-NEXT: v_cvt_f32_u32_e32 v2, s12
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s11 ; GFX10-NEXT: s_xor_b32 s13, s13, s3
; GFX10-NEXT: v_cvt_f32_u32_e32 v2, s8 ; GFX10-NEXT: s_sub_i32 s6, 0, s14
; GFX10-NEXT: s_xor_b32 s9, s9, s15 ; GFX10-NEXT: v_cvt_f32_u32_e32 v3, s13
; GFX10-NEXT: s_sub_i32 s6, 0, s10
; GFX10-NEXT: v_cvt_f32_u32_e32 v3, s9
; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX10-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX10-NEXT: s_sub_i32 s7, 0, s11 ; GFX10-NEXT: s_sub_i32 s7, 0, s15
; GFX10-NEXT: s_sub_i32 s19, 0, s8 ; GFX10-NEXT: s_sub_i32 s19, 0, s12
; GFX10-NEXT: v_rcp_iflag_f32_e32 v3, v3 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX10-NEXT: s_ashr_i32 s16, s8, 31
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: s_ashr_i32 s16, s0, 31 ; GFX10-NEXT: s_ashr_i32 s18, s10, 31
; GFX10-NEXT: s_ashr_i32 s17, s1, 31 ; GFX10-NEXT: s_ashr_i32 s17, s9, 31
; GFX10-NEXT: s_add_i32 s0, s0, s16 ; GFX10-NEXT: s_xor_b32 s20, s16, s0
; GFX10-NEXT: s_ashr_i32 s18, s2, 31
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: v_mul_f32_e32 v1, v1, v4 ; GFX10-NEXT: v_mul_f32_e32 v1, v1, v4
; GFX10-NEXT: v_mul_f32_e32 v2, v2, v4 ; GFX10-NEXT: v_mul_f32_e32 v2, v2, v4
; GFX10-NEXT: s_xor_b32 s0, s0, s16 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: s_xor_b32 s21, s17, s1
; GFX10-NEXT: v_mul_f32_e32 v3, v3, v4 ; GFX10-NEXT: v_mul_f32_e32 v3, v3, v4
; GFX10-NEXT: v_mul_lo_u32 v4, s6, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX10-NEXT: s_sub_i32 s6, 0, s9 ; GFX10-NEXT: v_mul_lo_u32 v4, s6, v0
; GFX10-NEXT: s_sub_i32 s6, 0, s13
; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX10-NEXT: s_add_i32 s1, s1, s17
; GFX10-NEXT: v_mul_lo_u32 v5, s7, v1 ; GFX10-NEXT: v_mul_lo_u32 v5, s7, v1
; GFX10-NEXT: v_mul_lo_u32 v6, s19, v2 ; GFX10-NEXT: v_mul_lo_u32 v6, s19, v2
; GFX10-NEXT: v_mul_hi_u32 v4, v0, v4 ; GFX10-NEXT: s_ashr_i32 s19, s11, 31
; GFX10-NEXT: s_add_i32 s7, s9, s17
; GFX10-NEXT: v_mul_lo_u32 v7, s6, v3 ; GFX10-NEXT: v_mul_lo_u32 v7, s6, v3
; GFX10-NEXT: s_add_i32 s2, s2, s18 ; GFX10-NEXT: v_mul_hi_u32 v4, v0, v4
; GFX10-NEXT: s_ashr_i32 s19, s3, 31 ; GFX10-NEXT: s_add_i32 s6, s8, s16
; GFX10-NEXT: s_xor_b32 s1, s1, s17 ; GFX10-NEXT: s_add_i32 s8, s10, s18
; GFX10-NEXT: s_xor_b32 s2, s2, s18
; GFX10-NEXT: v_mul_hi_u32 v5, v1, v5 ; GFX10-NEXT: v_mul_hi_u32 v5, v1, v5
; GFX10-NEXT: v_mul_hi_u32 v6, v2, v6 ; GFX10-NEXT: v_mul_hi_u32 v6, v2, v6
; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v4 ; GFX10-NEXT: s_xor_b32 s10, s6, s16
; GFX10-NEXT: s_add_i32 s9, s11, s19
; GFX10-NEXT: v_mul_hi_u32 v7, v3, v7 ; GFX10-NEXT: v_mul_hi_u32 v7, v3, v7
; GFX10-NEXT: s_add_i32 s3, s3, s19 ; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v4
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0 ; GFX10-NEXT: s_xor_b32 s11, s7, s17
; GFX10-NEXT: s_xor_b32 s3, s3, s19 ; GFX10-NEXT: s_xor_b32 s8, s8, s18
; GFX10-NEXT: v_mul_hi_u32 v0, s0, v0
; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v5 ; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v5
; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v6 ; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v6
; GFX10-NEXT: s_xor_b32 s12, s16, s12 ; GFX10-NEXT: v_mul_hi_u32 v0, s10, v0
; GFX10-NEXT: s_xor_b32 s9, s9, s19
; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v7 ; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v7
; GFX10-NEXT: s_xor_b32 s13, s17, s13 ; GFX10-NEXT: v_mul_hi_u32 v1, s11, v1
; GFX10-NEXT: v_mul_hi_u32 v1, s1, v1 ; GFX10-NEXT: v_mul_hi_u32 v2, s8, v2
; GFX10-NEXT: v_mul_hi_u32 v2, s2, v2 ; GFX10-NEXT: s_xor_b32 s22, s18, s2
; GFX10-NEXT: v_mul_lo_u32 v4, v0, s10 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX10-NEXT: v_mul_hi_u32 v3, s3, v3 ; GFX10-NEXT: v_mul_hi_u32 v3, s9, v3
; GFX10-NEXT: v_mul_lo_u32 v4, v0, s14
; GFX10-NEXT: v_add_nc_u32_e32 v8, 1, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v8, 1, v0
; GFX10-NEXT: s_xor_b32 s14, s18, s14 ; GFX10-NEXT: v_mul_lo_u32 v5, v1, s15
; GFX10-NEXT: v_mul_lo_u32 v5, v1, s11 ; GFX10-NEXT: v_mul_lo_u32 v6, v2, s12
; GFX10-NEXT: v_mul_lo_u32 v6, v2, s8
; GFX10-NEXT: v_sub_nc_u32_e32 v4, s0, v4
; GFX10-NEXT: v_mul_lo_u32 v7, v3, s9
; GFX10-NEXT: v_add_nc_u32_e32 v9, 1, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v9, 1, v1
; GFX10-NEXT: v_add_nc_u32_e32 v10, 1, v2 ; GFX10-NEXT: v_add_nc_u32_e32 v10, 1, v2
; GFX10-NEXT: v_mul_lo_u32 v7, v3, s13
; GFX10-NEXT: v_sub_nc_u32_e32 v4, s10, v4
; GFX10-NEXT: v_add_nc_u32_e32 v11, 1, v3 ; GFX10-NEXT: v_add_nc_u32_e32 v11, 1, v3
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s10, v4 ; GFX10-NEXT: v_sub_nc_u32_e32 v5, s11, v5
; GFX10-NEXT: v_sub_nc_u32_e32 v5, s1, v5 ; GFX10-NEXT: v_sub_nc_u32_e32 v6, s8, v6
; GFX10-NEXT: v_sub_nc_u32_e32 v6, s2, v6 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s14, v4
; GFX10-NEXT: v_sub_nc_u32_e32 v7, s3, v7 ; GFX10-NEXT: v_sub_nc_u32_e32 v7, s9, v7
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s15, v5
; GFX10-NEXT: v_cmp_le_u32_e64 s1, s12, v6
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
; GFX10-NEXT: v_subrev_nc_u32_e32 v8, s10, v4 ; GFX10-NEXT: v_subrev_nc_u32_e32 v8, s14, v4
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s11, v5 ; GFX10-NEXT: v_cmp_le_u32_e64 s2, s13, v7
; GFX10-NEXT: v_cmp_le_u32_e64 s1, s8, v6
; GFX10-NEXT: v_cmp_le_u32_e64 s2, s9, v7
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v9, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v9, s0
; GFX10-NEXT: v_subrev_nc_u32_e32 v9, s11, v5 ; GFX10-NEXT: v_subrev_nc_u32_e32 v9, s15, v5
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v10, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v10, s1
; GFX10-NEXT: v_subrev_nc_u32_e32 v10, s8, v6 ; GFX10-NEXT: v_subrev_nc_u32_e32 v10, s12, v6
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v11, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v11, s2
; GFX10-NEXT: v_subrev_nc_u32_e32 v11, s9, v7 ; GFX10-NEXT: v_subrev_nc_u32_e32 v11, s13, v7
; GFX10-NEXT: v_add_nc_u32_e32 v8, 1, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v8, 1, v0
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s10, v4
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v9, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v9, s0
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v10, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v10, s1
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s14, v4
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v11, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v11, s2
; GFX10-NEXT: v_add_nc_u32_e32 v9, 1, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v9, 1, v1
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
; GFX10-NEXT: v_subrev_nc_u32_e32 v8, s10, v4
; GFX10-NEXT: v_add_nc_u32_e32 v10, 1, v2 ; GFX10-NEXT: v_add_nc_u32_e32 v10, 1, v2
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s11, v5 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s15, v5
; GFX10-NEXT: v_cmp_le_u32_e64 s1, s8, v6 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
; GFX10-NEXT: v_subrev_nc_u32_e32 v8, s14, v4
; GFX10-NEXT: v_cmp_le_u32_e64 s1, s12, v6
; GFX10-NEXT: v_add_nc_u32_e32 v11, 1, v3 ; GFX10-NEXT: v_add_nc_u32_e32 v11, 1, v3
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo ; GFX10-NEXT: v_cmp_le_u32_e64 s2, s13, v7
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s9, v7
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v9, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v9, s0
; GFX10-NEXT: v_subrev_nc_u32_e32 v9, s11, v5 ; GFX10-NEXT: v_subrev_nc_u32_e32 v9, s15, v5
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v10, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v10, s1
; GFX10-NEXT: v_subrev_nc_u32_e32 v10, s8, v6 ; GFX10-NEXT: v_subrev_nc_u32_e32 v10, s12, v6
; GFX10-NEXT: v_subrev_nc_u32_e32 v12, s9, v7 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo ; GFX10-NEXT: v_subrev_nc_u32_e32 v8, s13, v7
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v11, s2
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v9, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v9, s0
; GFX10-NEXT: s_xor_b32 s0, s19, s15
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v10, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v10, s1
; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v12, vcc_lo ; GFX10-NEXT: s_xor_b32 s0, s19, s3
; GFX10-NEXT: v_xor_b32_e32 v0, s12, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v8, s2
; GFX10-NEXT: v_xor_b32_e32 v1, s13, v1 ; GFX10-NEXT: v_xor_b32_e32 v0, s20, v0
; GFX10-NEXT: v_xor_b32_e32 v2, s14, v2 ; GFX10-NEXT: v_xor_b32_e32 v1, s21, v1
; GFX10-NEXT: v_xor_b32_e32 v2, s22, v2
; GFX10-NEXT: v_xor_b32_e32 v3, s0, v3 ; GFX10-NEXT: v_xor_b32_e32 v3, s0, v3
; GFX10-NEXT: v_xor_b32_e32 v4, s16, v4 ; GFX10-NEXT: v_xor_b32_e32 v4, s16, v4
; GFX10-NEXT: v_xor_b32_e32 v5, s17, v5 ; GFX10-NEXT: v_xor_b32_e32 v5, s17, v5
; GFX10-NEXT: v_xor_b32_e32 v6, s18, v6 ; GFX10-NEXT: v_xor_b32_e32 v6, s18, v6
; GFX10-NEXT: v_xor_b32_e32 v7, s19, v7 ; GFX10-NEXT: v_xor_b32_e32 v7, s19, v7
; GFX10-NEXT: v_subrev_nc_u32_e32 v0, s12, v0 ; GFX10-NEXT: v_subrev_nc_u32_e32 v0, s20, v0
; GFX10-NEXT: v_subrev_nc_u32_e32 v1, s13, v1 ; GFX10-NEXT: v_subrev_nc_u32_e32 v1, s21, v1
; GFX10-NEXT: v_subrev_nc_u32_e32 v2, s14, v2 ; GFX10-NEXT: v_subrev_nc_u32_e32 v2, s22, v2
; GFX10-NEXT: v_subrev_nc_u32_e32 v3, s0, v3 ; GFX10-NEXT: v_subrev_nc_u32_e32 v3, s0, v3
; GFX10-NEXT: v_mov_b32_e32 v8, 0 ; GFX10-NEXT: v_mov_b32_e32 v8, 0
; GFX10-NEXT: v_subrev_nc_u32_e32 v4, s16, v4 ; GFX10-NEXT: v_subrev_nc_u32_e32 v4, s16, v4
; GFX10-NEXT: v_subrev_nc_u32_e32 v5, s17, v5 ; GFX10-NEXT: v_subrev_nc_u32_e32 v5, s17, v5
; GFX10-NEXT: v_subrev_nc_u32_e32 v6, s18, v6 ; GFX10-NEXT: v_subrev_nc_u32_e32 v6, s18, v6
; GFX10-NEXT: v_subrev_nc_u32_e32 v7, s19, v7 ; GFX10-NEXT: v_subrev_nc_u32_e32 v7, s19, v7
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_store_dwordx4 v8, v[0:3], s[4:5] ; GFX10-NEXT: global_store_dwordx4 v8, v[0:3], s[4:5]
; GFX10-NEXT: global_store_dwordx4 v8, v[4:7], s[6:7] ; GFX10-NEXT: global_store_dwordx4 v8, v[4:7], s[6:7]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%div = sdiv <4 x i32> %x, %y %div = sdiv <4 x i32> %x, %y
store <4 x i32> %div, <4 x i32> addrspace(1)* %out0 store <4 x i32> %div, <4 x i32> addrspace(1)* %out0
%rem = srem <4 x i32> %x, %y %rem = srem <4 x i32> %x, %y
store <4 x i32> %rem, <4 x i32> addrspace(1)* %out1 store <4 x i32> %rem, <4 x i32> addrspace(1)* %out1
ret void ret void
} }
define amdgpu_kernel void @sdivrem_v2i64(<2 x i64> addrspace(1)* %out0, <2 x i64> addrspace(1)* %out1, <2 x i64> %x, <2 x i64> %y) { define amdgpu_kernel void @sdivrem_v2i64(<2 x i64> addrspace(1)* %out0, <2 x i64> addrspace(1)* %out1, <2 x i64> %x, <2 x i64> %y) {
; GFX8-LABEL: sdivrem_v2i64: ; GFX8-LABEL: sdivrem_v2i64:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x10 ; GFX8-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x10
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x20
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_ashr_i32 s6, s9, 31 ; GFX8-NEXT: s_ashr_i32 s2, s9, 31
; GFX8-NEXT: s_ashr_i32 s12, s1, 31 ; GFX8-NEXT: s_ashr_i32 s6, s13, 31
; GFX8-NEXT: s_add_u32 s14, s8, s6 ; GFX8-NEXT: s_add_u32 s0, s8, s2
; GFX8-NEXT: s_cselect_b32 s7, 1, 0 ; GFX8-NEXT: s_cselect_b32 s1, 1, 0
; GFX8-NEXT: s_and_b32 s7, s7, 1 ; GFX8-NEXT: s_and_b32 s1, s1, 1
; GFX8-NEXT: s_cmp_lg_u32 s7, 0 ; GFX8-NEXT: s_cmp_lg_u32 s1, 0
; GFX8-NEXT: s_addc_u32 s15, s9, s6 ; GFX8-NEXT: s_addc_u32 s1, s9, s2
; GFX8-NEXT: s_add_u32 s0, s0, s12 ; GFX8-NEXT: s_add_u32 s8, s12, s6
; GFX8-NEXT: s_cselect_b32 s7, 1, 0 ; GFX8-NEXT: s_cselect_b32 s3, 1, 0
; GFX8-NEXT: s_and_b32 s7, s7, 1 ; GFX8-NEXT: s_and_b32 s3, s3, 1
; GFX8-NEXT: s_cmp_lg_u32 s7, 0 ; GFX8-NEXT: s_cmp_lg_u32 s3, 0
; GFX8-NEXT: s_mov_b32 s13, s12 ; GFX8-NEXT: s_mov_b32 s7, s6
; GFX8-NEXT: s_addc_u32 s1, s1, s12 ; GFX8-NEXT: s_addc_u32 s9, s13, s6
; GFX8-NEXT: s_xor_b64 s[8:9], s[0:1], s[12:13] ; GFX8-NEXT: s_xor_b64 s[8:9], s[8:9], s[6:7]
; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s9 ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s9
; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s8 ; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s8
; GFX8-NEXT: s_mov_b32 s7, s6 ; GFX8-NEXT: s_mov_b32 s3, s2
; GFX8-NEXT: s_xor_b64 s[14:15], s[14:15], s[6:7] ; GFX8-NEXT: s_xor_b64 s[12:13], s[0:1], s[2:3]
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GFX8-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_sub_u32 s0, 0, s8 ; GFX8-NEXT: s_sub_u32 s0, 0, s8
; GFX8-NEXT: s_cselect_b32 s1, 1, 0 ; GFX8-NEXT: s_cselect_b32 s1, 1, 0
; GFX8-NEXT: s_and_b32 s1, s1, 1 ; GFX8-NEXT: s_and_b32 s1, s1, 1
; GFX8-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX8-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX8-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
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; GFX8-NEXT: v_add_u32_e32 v5, vcc, v7, v5 ; GFX8-NEXT: v_add_u32_e32 v5, vcc, v7, v5
; GFX8-NEXT: v_mul_hi_u32 v2, v1, v2 ; GFX8-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v4, v3 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v4, v3
; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v5, v4 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, v5, v4
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v4 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v4
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v3 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v3
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; GFX8-NEXT: v_mul_lo_u32 v2, s15, v0 ; GFX8-NEXT: v_mul_lo_u32 v2, s13, v0
; GFX8-NEXT: v_mul_lo_u32 v3, s14, v1 ; GFX8-NEXT: v_mul_lo_u32 v3, s12, v1
; GFX8-NEXT: v_mul_hi_u32 v5, s14, v0 ; GFX8-NEXT: v_mul_hi_u32 v5, s12, v0
; GFX8-NEXT: v_mul_hi_u32 v0, s15, v0 ; GFX8-NEXT: v_mul_hi_u32 v0, s13, v0
; GFX8-NEXT: v_mov_b32_e32 v4, s15 ; GFX8-NEXT: v_mov_b32_e32 v4, s13
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3
; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX8-NEXT: v_mul_lo_u32 v5, s15, v1 ; GFX8-NEXT: v_mul_lo_u32 v5, s13, v1
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v2 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v2
; GFX8-NEXT: v_mul_hi_u32 v3, s14, v1 ; GFX8-NEXT: v_mul_hi_u32 v3, s12, v1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v5, v0 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v5, v0
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v3 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v3
; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v5, v3 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v5, v3
; GFX8-NEXT: v_mul_hi_u32 v1, s15, v1 ; GFX8-NEXT: v_mul_hi_u32 v1, s13, v1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v2 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v2
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v2 ; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v2
; GFX8-NEXT: v_mul_lo_u32 v2, s9, v0 ; GFX8-NEXT: v_mul_lo_u32 v2, s9, v0
; GFX8-NEXT: v_mul_lo_u32 v3, s8, v1 ; GFX8-NEXT: v_mul_lo_u32 v3, s8, v1
; GFX8-NEXT: v_mul_hi_u32 v7, s8, v0 ; GFX8-NEXT: v_mul_hi_u32 v7, s8, v0
; GFX8-NEXT: v_mul_lo_u32 v5, s8, v0 ; GFX8-NEXT: v_mul_lo_u32 v5, s8, v0
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v7 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v7
; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s14, v5 ; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s12, v5
; GFX8-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v2, vcc ; GFX8-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v2, vcc
; GFX8-NEXT: v_sub_u32_e64 v2, s[0:1], s15, v2 ; GFX8-NEXT: v_sub_u32_e64 v2, s[0:1], s13, v2
; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v4 ; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v4
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v3 ; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v3
; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1]
; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v4 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v4
; GFX8-NEXT: v_subb_u32_e32 v2, vcc, v2, v6, vcc ; GFX8-NEXT: v_subb_u32_e32 v2, vcc, v2, v6, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v5, v5, v7, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v5, v5, v7, s[0:1]
; GFX8-NEXT: v_subrev_u32_e32 v7, vcc, s8, v3 ; GFX8-NEXT: v_subrev_u32_e32 v7, vcc, s8, v3
Show All 14 Lines
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GFX8-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v11 ; GFX8-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v11
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v5, v7, v6, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v5, v7, v6, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e64 v2, v8, v2, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v2, v8, v2, s[0:1]
; GFX8-NEXT: s_xor_b64 s[0:1], s[6:7], s[12:13] ; GFX8-NEXT: s_xor_b64 s[0:1], s[2:3], s[6:7]
; GFX8-NEXT: v_xor_b32_e32 v0, s0, v0 ; GFX8-NEXT: v_xor_b32_e32 v0, s0, v0
; GFX8-NEXT: s_ashr_i32 s8, s11, 31 ; GFX8-NEXT: s_ashr_i32 s6, s11, 31
; GFX8-NEXT: s_ashr_i32 s12, s3, 31 ; GFX8-NEXT: s_ashr_i32 s8, s15, 31
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v10, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v10, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX8-NEXT: v_subrev_u32_e32 v0, vcc, s0, v0 ; GFX8-NEXT: v_subrev_u32_e32 v0, vcc, s0, v0
; GFX8-NEXT: s_add_u32 s0, s10, s8 ; GFX8-NEXT: s_add_u32 s0, s10, s6
; GFX8-NEXT: v_xor_b32_e32 v1, s1, v1 ; GFX8-NEXT: v_xor_b32_e32 v1, s1, v1
; GFX8-NEXT: v_mov_b32_e32 v4, s1 ; GFX8-NEXT: v_mov_b32_e32 v4, s1
; GFX8-NEXT: s_cselect_b32 s1, 1, 0 ; GFX8-NEXT: s_cselect_b32 s1, 1, 0
; GFX8-NEXT: s_and_b32 s1, s1, 1 ; GFX8-NEXT: s_and_b32 s1, s1, 1
; GFX8-NEXT: s_cmp_lg_u32 s1, 0 ; GFX8-NEXT: s_cmp_lg_u32 s1, 0
; GFX8-NEXT: s_addc_u32 s1, s11, s8 ; GFX8-NEXT: s_addc_u32 s1, s11, s6
; GFX8-NEXT: s_add_u32 s2, s2, s12 ; GFX8-NEXT: s_add_u32 s10, s14, s8
; GFX8-NEXT: s_cselect_b32 s7, 1, 0 ; GFX8-NEXT: s_cselect_b32 s3, 1, 0
; GFX8-NEXT: s_and_b32 s7, s7, 1 ; GFX8-NEXT: s_and_b32 s3, s3, 1
; GFX8-NEXT: s_cmp_lg_u32 s7, 0 ; GFX8-NEXT: s_cmp_lg_u32 s3, 0
; GFX8-NEXT: s_mov_b32 s13, s12
; GFX8-NEXT: s_addc_u32 s3, s3, s12
; GFX8-NEXT: s_xor_b64 s[2:3], s[2:3], s[12:13]
; GFX8-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc
; GFX8-NEXT: v_cvt_f32_u32_e32 v4, s3
; GFX8-NEXT: v_cvt_f32_u32_e32 v5, s2
; GFX8-NEXT: s_mov_b32 s9, s8 ; GFX8-NEXT: s_mov_b32 s9, s8
; GFX8-NEXT: s_xor_b64 s[10:11], s[0:1], s[8:9] ; GFX8-NEXT: s_addc_u32 s11, s15, s8
; GFX8-NEXT: s_xor_b64 s[10:11], s[10:11], s[8:9]
; GFX8-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc
; GFX8-NEXT: v_cvt_f32_u32_e32 v4, s11
; GFX8-NEXT: v_cvt_f32_u32_e32 v5, s10
; GFX8-NEXT: s_mov_b32 s7, s6
; GFX8-NEXT: s_xor_b64 s[12:13], s[0:1], s[6:7]
; GFX8-NEXT: v_mul_f32_e32 v4, 0x4f800000, v4 ; GFX8-NEXT: v_mul_f32_e32 v4, 0x4f800000, v4
; GFX8-NEXT: v_add_f32_e32 v4, v4, v5 ; GFX8-NEXT: v_add_f32_e32 v4, v4, v5
; GFX8-NEXT: v_rcp_iflag_f32_e32 v4, v4 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v4, v4
; GFX8-NEXT: s_sub_u32 s0, 0, s2 ; GFX8-NEXT: s_sub_u32 s0, 0, s10
; GFX8-NEXT: s_cselect_b32 s1, 1, 0 ; GFX8-NEXT: s_cselect_b32 s1, 1, 0
; GFX8-NEXT: s_and_b32 s1, s1, 1 ; GFX8-NEXT: s_and_b32 s1, s1, 1
; GFX8-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; GFX8-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
; GFX8-NEXT: v_mul_f32_e32 v6, 0x2f800000, v4 ; GFX8-NEXT: v_mul_f32_e32 v6, 0x2f800000, v4
; GFX8-NEXT: v_trunc_f32_e32 v6, v6 ; GFX8-NEXT: v_trunc_f32_e32 v6, v6
; GFX8-NEXT: v_mul_f32_e32 v7, 0xcf800000, v6 ; GFX8-NEXT: v_mul_f32_e32 v7, 0xcf800000, v6
; GFX8-NEXT: v_add_f32_e32 v4, v7, v4 ; GFX8-NEXT: v_add_f32_e32 v4, v7, v4
; GFX8-NEXT: v_cvt_u32_f32_e32 v7, v4 ; GFX8-NEXT: v_cvt_u32_f32_e32 v7, v4
; GFX8-NEXT: v_cvt_u32_f32_e32 v6, v6 ; GFX8-NEXT: v_cvt_u32_f32_e32 v6, v6
; GFX8-NEXT: s_cmp_lg_u32 s1, 0 ; GFX8-NEXT: s_cmp_lg_u32 s1, 0
; GFX8-NEXT: s_subb_u32 s1, 0, s3 ; GFX8-NEXT: s_subb_u32 s1, 0, s11
; GFX8-NEXT: v_mul_lo_u32 v4, s1, v7 ; GFX8-NEXT: v_mul_lo_u32 v4, s1, v7
; GFX8-NEXT: v_mul_lo_u32 v8, s0, v6 ; GFX8-NEXT: v_mul_lo_u32 v8, s0, v6
; GFX8-NEXT: v_mul_hi_u32 v10, s0, v7 ; GFX8-NEXT: v_mul_hi_u32 v10, s0, v7
; GFX8-NEXT: v_mul_lo_u32 v9, s0, v7 ; GFX8-NEXT: v_mul_lo_u32 v9, s0, v7
; GFX8-NEXT: v_xor_b32_e32 v3, s6, v3 ; GFX8-NEXT: v_xor_b32_e32 v3, s2, v3
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v8 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v8
; GFX8-NEXT: v_add_u32_e32 v8, vcc, v4, v10 ; GFX8-NEXT: v_add_u32_e32 v8, vcc, v4, v10
; GFX8-NEXT: v_xor_b32_e32 v2, s6, v2 ; GFX8-NEXT: v_xor_b32_e32 v2, s2, v2
; GFX8-NEXT: v_mov_b32_e32 v5, s6 ; GFX8-NEXT: v_mov_b32_e32 v5, s2
; GFX8-NEXT: v_mul_lo_u32 v10, v6, v9 ; GFX8-NEXT: v_mul_lo_u32 v10, v6, v9
; GFX8-NEXT: v_mul_lo_u32 v11, v7, v8 ; GFX8-NEXT: v_mul_lo_u32 v11, v7, v8
; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s6, v3 ; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s2, v3
; GFX8-NEXT: v_subb_u32_e32 v5, vcc, v2, v5, vcc ; GFX8-NEXT: v_subb_u32_e32 v5, vcc, v2, v5, vcc
; GFX8-NEXT: v_mul_hi_u32 v2, v7, v9 ; GFX8-NEXT: v_mul_hi_u32 v2, v7, v9
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v10, v11 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v10, v11
; GFX8-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v2 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX8-NEXT: v_mul_lo_u32 v3, v6, v8 ; GFX8-NEXT: v_mul_lo_u32 v3, v6, v8
; GFX8-NEXT: v_mul_hi_u32 v9, v6, v9 ; GFX8-NEXT: v_mul_hi_u32 v9, v6, v9
Show All 10 Lines
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v9, v3 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v9, v3
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v8, v3 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v8, v3
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v7, v2 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v7, v2
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v6, v3, vcc ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v6, v3, vcc
; GFX8-NEXT: v_mul_lo_u32 v6, s1, v2 ; GFX8-NEXT: v_mul_lo_u32 v6, s1, v2
; GFX8-NEXT: v_mul_lo_u32 v7, s0, v3 ; GFX8-NEXT: v_mul_lo_u32 v7, s0, v3
; GFX8-NEXT: v_mul_hi_u32 v9, s0, v2 ; GFX8-NEXT: v_mul_hi_u32 v9, s0, v2
; GFX8-NEXT: v_mul_lo_u32 v8, s0, v2 ; GFX8-NEXT: v_mul_lo_u32 v8, s0, v2
; GFX8-NEXT: v_mov_b32_e32 v10, s3 ; GFX8-NEXT: v_mov_b32_e32 v10, s11
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v7 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v7
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v9 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v9
; GFX8-NEXT: v_mul_lo_u32 v7, v3, v8 ; GFX8-NEXT: v_mul_lo_u32 v7, v3, v8
; GFX8-NEXT: v_mul_lo_u32 v9, v2, v6 ; GFX8-NEXT: v_mul_lo_u32 v9, v2, v6
; GFX8-NEXT: v_mul_hi_u32 v11, v2, v8 ; GFX8-NEXT: v_mul_hi_u32 v11, v2, v8
; GFX8-NEXT: v_mul_hi_u32 v8, v3, v8 ; GFX8-NEXT: v_mul_hi_u32 v8, v3, v8
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v9 ; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v9
; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v11 ; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v11
; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX8-NEXT: v_mul_lo_u32 v11, v3, v6 ; GFX8-NEXT: v_mul_lo_u32 v11, v3, v6
; GFX8-NEXT: v_add_u32_e32 v7, vcc, v9, v7 ; GFX8-NEXT: v_add_u32_e32 v7, vcc, v9, v7
; GFX8-NEXT: v_mul_hi_u32 v9, v2, v6 ; GFX8-NEXT: v_mul_hi_u32 v9, v2, v6
; GFX8-NEXT: v_add_u32_e32 v8, vcc, v11, v8 ; GFX8-NEXT: v_add_u32_e32 v8, vcc, v11, v8
; GFX8-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v8, vcc, v8, v9 ; GFX8-NEXT: v_add_u32_e32 v8, vcc, v8, v9
; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v9, vcc, v11, v9 ; GFX8-NEXT: v_add_u32_e32 v9, vcc, v11, v9
; GFX8-NEXT: v_mul_hi_u32 v6, v3, v6 ; GFX8-NEXT: v_mul_hi_u32 v6, v3, v6
; GFX8-NEXT: v_add_u32_e32 v7, vcc, v8, v7 ; GFX8-NEXT: v_add_u32_e32 v7, vcc, v8, v7
; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v8, vcc, v9, v8 ; GFX8-NEXT: v_add_u32_e32 v8, vcc, v9, v8
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v8 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v8
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v7 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v7
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v3, v6, vcc ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v3, v6, vcc
; GFX8-NEXT: v_mul_lo_u32 v6, s11, v2 ; GFX8-NEXT: v_mul_lo_u32 v6, s13, v2
; GFX8-NEXT: v_mul_lo_u32 v7, s10, v3 ; GFX8-NEXT: v_mul_lo_u32 v7, s12, v3
; GFX8-NEXT: v_mul_hi_u32 v9, s10, v2 ; GFX8-NEXT: v_mul_hi_u32 v9, s12, v2
; GFX8-NEXT: v_mul_hi_u32 v2, s11, v2 ; GFX8-NEXT: v_mul_hi_u32 v2, s13, v2
; GFX8-NEXT: v_mov_b32_e32 v8, s11 ; GFX8-NEXT: v_mov_b32_e32 v8, s13
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v7 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v7
; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v9 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v9
; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX8-NEXT: v_mul_lo_u32 v9, s11, v3 ; GFX8-NEXT: v_mul_lo_u32 v9, s13, v3
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v7, v6 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v7, v6
; GFX8-NEXT: v_mul_hi_u32 v7, s10, v3 ; GFX8-NEXT: v_mul_hi_u32 v7, s12, v3
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v9, v2 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v9, v2
; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v7 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v7
; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v7, vcc, v9, v7 ; GFX8-NEXT: v_add_u32_e32 v7, vcc, v9, v7
; GFX8-NEXT: v_mul_hi_u32 v3, s11, v3 ; GFX8-NEXT: v_mul_hi_u32 v3, s13, v3
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v6 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v6
; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v7, v6 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v7, v6
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v6 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v6
; GFX8-NEXT: v_mul_lo_u32 v6, s3, v2 ; GFX8-NEXT: v_mul_lo_u32 v6, s11, v2
; GFX8-NEXT: v_mul_lo_u32 v7, s2, v3 ; GFX8-NEXT: v_mul_lo_u32 v7, s10, v3
; GFX8-NEXT: v_mul_hi_u32 v11, s2, v2 ; GFX8-NEXT: v_mul_hi_u32 v11, s10, v2
; GFX8-NEXT: v_mul_lo_u32 v9, s2, v2 ; GFX8-NEXT: v_mul_lo_u32 v9, s10, v2
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v7 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v7
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v11 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v11
; GFX8-NEXT: v_sub_u32_e32 v7, vcc, s10, v9 ; GFX8-NEXT: v_sub_u32_e32 v7, vcc, s12, v9
; GFX8-NEXT: v_subb_u32_e64 v8, s[0:1], v8, v6, vcc ; GFX8-NEXT: v_subb_u32_e64 v8, s[0:1], v8, v6, vcc
; GFX8-NEXT: v_sub_u32_e64 v6, s[0:1], s11, v6 ; GFX8-NEXT: v_sub_u32_e64 v6, s[0:1], s13, v6
; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v8 ; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v8
; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[0:1]
; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v7 ; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v7
; GFX8-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[0:1]
; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v8 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v8
; GFX8-NEXT: v_subb_u32_e32 v6, vcc, v6, v10, vcc ; GFX8-NEXT: v_subb_u32_e32 v6, vcc, v6, v10, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v9, v9, v11, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v9, v9, v11, s[0:1]
; GFX8-NEXT: v_subrev_u32_e32 v11, vcc, s2, v7 ; GFX8-NEXT: v_subrev_u32_e32 v11, vcc, s10, v7
; GFX8-NEXT: v_subbrev_u32_e64 v12, s[0:1], 0, v6, vcc ; GFX8-NEXT: v_subbrev_u32_e64 v12, s[0:1], 0, v6, vcc
; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v12 ; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v12
; GFX8-NEXT: v_cndmask_b32_e64 v13, 0, -1, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v13, 0, -1, s[0:1]
; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v11 ; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v11
; GFX8-NEXT: v_cndmask_b32_e64 v14, 0, -1, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v14, 0, -1, s[0:1]
; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v12 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v12
; GFX8-NEXT: v_cndmask_b32_e64 v13, v13, v14, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v13, v13, v14, s[0:1]
; GFX8-NEXT: v_add_u32_e64 v14, s[0:1], 1, v2 ; GFX8-NEXT: v_add_u32_e64 v14, s[0:1], 1, v2
; GFX8-NEXT: v_subb_u32_e32 v6, vcc, v6, v10, vcc ; GFX8-NEXT: v_subb_u32_e32 v6, vcc, v6, v10, vcc
; GFX8-NEXT: v_addc_u32_e64 v15, s[0:1], 0, v3, s[0:1] ; GFX8-NEXT: v_addc_u32_e64 v15, s[0:1], 0, v3, s[0:1]
; GFX8-NEXT: v_add_u32_e32 v10, vcc, 1, v14 ; GFX8-NEXT: v_add_u32_e32 v10, vcc, 1, v14
; GFX8-NEXT: v_addc_u32_e32 v16, vcc, 0, v15, vcc ; GFX8-NEXT: v_addc_u32_e32 v16, vcc, 0, v15, vcc
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13
; GFX8-NEXT: v_subrev_u32_e64 v13, s[0:1], s2, v11 ; GFX8-NEXT: v_subrev_u32_e64 v13, s[0:1], s10, v11
; GFX8-NEXT: v_subbrev_u32_e64 v6, s[0:1], 0, v6, s[0:1] ; GFX8-NEXT: v_subbrev_u32_e64 v6, s[0:1], 0, v6, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e32 v10, v14, v10, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v10, v14, v10, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v14, v15, v16, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v14, v15, v16, vcc
; GFX8-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v9 ; GFX8-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v9
; GFX8-NEXT: v_cndmask_b32_e32 v9, v11, v13, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v9, v11, v13, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v6, v12, v6, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v6, v12, v6, vcc
; GFX8-NEXT: s_load_dwordx4 s[12:15], s[4:5], 0x0
; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v10, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v10, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v14, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v14, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e64 v6, v8, v6, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v6, v8, v6, s[0:1]
; GFX8-NEXT: s_xor_b64 s[0:1], s[8:9], s[12:13] ; GFX8-NEXT: s_xor_b64 s[0:1], s[6:7], s[8:9]
; GFX8-NEXT: v_xor_b32_e32 v2, s0, v2 ; GFX8-NEXT: v_xor_b32_e32 v2, s0, v2
; GFX8-NEXT: v_xor_b32_e32 v3, s1, v3 ; GFX8-NEXT: v_xor_b32_e32 v3, s1, v3
; GFX8-NEXT: v_mov_b32_e32 v8, s1 ; GFX8-NEXT: v_mov_b32_e32 v8, s1
; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s0, v2 ; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s0, v2
; GFX8-NEXT: v_subb_u32_e32 v3, vcc, v3, v8, vcc ; GFX8-NEXT: v_subb_u32_e32 v3, vcc, v3, v8, vcc
; GFX8-NEXT: v_xor_b32_e32 v7, s8, v7 ; GFX8-NEXT: v_xor_b32_e32 v7, s6, v7
; GFX8-NEXT: v_xor_b32_e32 v8, s8, v6 ; GFX8-NEXT: v_xor_b32_e32 v8, s6, v6
; GFX8-NEXT: v_mov_b32_e32 v9, s8 ; GFX8-NEXT: v_mov_b32_e32 v9, s6
; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, s8, v7 ; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, s6, v7
; GFX8-NEXT: v_subb_u32_e32 v7, vcc, v8, v9, vcc ; GFX8-NEXT: v_subb_u32_e32 v7, vcc, v8, v9, vcc
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v9, s5 ; GFX8-NEXT: v_mov_b32_e32 v8, s12
; GFX8-NEXT: v_mov_b32_e32 v8, s4 ; GFX8-NEXT: v_mov_b32_e32 v9, s13
; GFX8-NEXT: flat_store_dwordx4 v[8:9], v[0:3] ; GFX8-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
; GFX8-NEXT: s_nop 0 ; GFX8-NEXT: s_nop 0
; GFX8-NEXT: v_mov_b32_e32 v0, s6 ; GFX8-NEXT: v_mov_b32_e32 v0, s14
; GFX8-NEXT: v_mov_b32_e32 v1, s7 ; GFX8-NEXT: v_mov_b32_e32 v1, s15
; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[4:7] ; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-LABEL: sdivrem_v2i64: ; GFX9-LABEL: sdivrem_v2i64:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x10 ; GFX9-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x10
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x20
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_ashr_i32 s6, s9, 31 ; GFX9-NEXT: s_ashr_i32 s2, s9, 31
; GFX9-NEXT: s_ashr_i32 s12, s1, 31 ; GFX9-NEXT: s_ashr_i32 s6, s13, 31
; GFX9-NEXT: s_add_u32 s14, s8, s6 ; GFX9-NEXT: s_add_u32 s0, s8, s2
; GFX9-NEXT: s_cselect_b32 s7, 1, 0 ; GFX9-NEXT: s_cselect_b32 s1, 1, 0
; GFX9-NEXT: s_and_b32 s7, s7, 1 ; GFX9-NEXT: s_and_b32 s1, s1, 1
; GFX9-NEXT: s_cmp_lg_u32 s7, 0 ; GFX9-NEXT: s_cmp_lg_u32 s1, 0
; GFX9-NEXT: s_addc_u32 s15, s9, s6 ; GFX9-NEXT: s_addc_u32 s1, s9, s2
; GFX9-NEXT: s_add_u32 s0, s0, s12 ; GFX9-NEXT: s_add_u32 s8, s12, s6
; GFX9-NEXT: s_cselect_b32 s7, 1, 0 ; GFX9-NEXT: s_cselect_b32 s3, 1, 0
; GFX9-NEXT: s_and_b32 s7, s7, 1 ; GFX9-NEXT: s_and_b32 s3, s3, 1
; GFX9-NEXT: s_cmp_lg_u32 s7, 0 ; GFX9-NEXT: s_cmp_lg_u32 s3, 0
; GFX9-NEXT: s_mov_b32 s13, s12 ; GFX9-NEXT: s_mov_b32 s7, s6
; GFX9-NEXT: s_addc_u32 s1, s1, s12 ; GFX9-NEXT: s_addc_u32 s9, s13, s6
; GFX9-NEXT: s_xor_b64 s[8:9], s[0:1], s[12:13] ; GFX9-NEXT: s_xor_b64 s[8:9], s[8:9], s[6:7]
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s9 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s9
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s8 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s8
; GFX9-NEXT: s_mov_b32 s7, s6 ; GFX9-NEXT: s_mov_b32 s3, s2
; GFX9-NEXT: s_xor_b64 s[14:15], s[14:15], s[6:7] ; GFX9-NEXT: s_xor_b64 s[12:13], s[0:1], s[2:3]
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GFX9-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: s_sub_u32 s0, 0, s8 ; GFX9-NEXT: s_sub_u32 s0, 0, s8
; GFX9-NEXT: s_cselect_b32 s1, 1, 0 ; GFX9-NEXT: s_cselect_b32 s1, 1, 0
; GFX9-NEXT: s_and_b32 s1, s1, 1 ; GFX9-NEXT: s_and_b32 s1, s1, 1
; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1
; GFX9-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1 ; GFX9-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1
; GFX9-NEXT: v_add_f32_e32 v0, v2, v0 ; GFX9-NEXT: v_add_f32_e32 v0, v2, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: s_cmp_lg_u32 s1, 0 ; GFX9-NEXT: s_cmp_lg_u32 s1, 0
; GFX9-NEXT: s_subb_u32 s1, 0, s9 ; GFX9-NEXT: s_subb_u32 s1, 0, s9
; GFX9-NEXT: v_mul_lo_u32 v2, s0, v1 ; GFX9-NEXT: v_mul_lo_u32 v2, s0, v1
; GFX9-NEXT: v_mul_lo_u32 v3, s1, v0 ; GFX9-NEXT: v_mul_lo_u32 v3, s1, v0
; GFX9-NEXT: v_mul_hi_u32 v4, s0, v0 ; GFX9-NEXT: v_mul_hi_u32 v4, s0, v0
; GFX9-NEXT: v_mul_lo_u32 v5, s0, v0 ; GFX9-NEXT: v_mul_lo_u32 v5, s0, v0
; GFX9-NEXT: v_mov_b32_e32 v7, s15 ; GFX9-NEXT: v_mov_b32_e32 v7, s13
; GFX9-NEXT: v_add3_u32 v2, v3, v2, v4 ; GFX9-NEXT: v_add3_u32 v2, v3, v2, v4
; GFX9-NEXT: v_mul_lo_u32 v3, v1, v5 ; GFX9-NEXT: v_mul_lo_u32 v3, v1, v5
; GFX9-NEXT: v_mul_lo_u32 v4, v0, v2 ; GFX9-NEXT: v_mul_lo_u32 v4, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v6, v0, v5 ; GFX9-NEXT: v_mul_hi_u32 v6, v0, v5
; GFX9-NEXT: v_mul_hi_u32 v5, v1, v5 ; GFX9-NEXT: v_mul_hi_u32 v5, v1, v5
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6
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; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX9-NEXT: v_add_u32_e32 v5, v6, v5 ; GFX9-NEXT: v_add_u32_e32 v5, v6, v5
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-NEXT: v_add3_u32 v2, v5, v4, v2 ; GFX9-NEXT: v_add3_u32 v2, v5, v4, v2
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v2, vcc
; GFX9-NEXT: v_mul_lo_u32 v2, s15, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, s13, v0
; GFX9-NEXT: v_mul_lo_u32 v3, s14, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, s12, v1
; GFX9-NEXT: v_mul_hi_u32 v4, s14, v0 ; GFX9-NEXT: v_mul_hi_u32 v4, s12, v0
; GFX9-NEXT: v_mul_hi_u32 v0, s15, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s13, v0
; GFX9-NEXT: v_mov_b32_e32 v5, s9 ; GFX9-NEXT: v_mov_b32_e32 v5, s9
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3
; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, s15, v1 ; GFX9-NEXT: v_mul_lo_u32 v4, s13, v1
; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
; GFX9-NEXT: v_mul_hi_u32 v3, s14, v1 ; GFX9-NEXT: v_mul_hi_u32 v3, s12, v1
; GFX9-NEXT: v_mul_hi_u32 v1, s15, v1 ; GFX9-NEXT: v_mul_hi_u32 v1, s13, v1
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v4, v0 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v4, v0
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: v_add_u32_e32 v3, v4, v3 ; GFX9-NEXT: v_add_u32_e32 v3, v4, v3
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_add3_u32 v1, v3, v2, v1 ; GFX9-NEXT: v_add3_u32 v1, v3, v2, v1
; GFX9-NEXT: v_mul_lo_u32 v2, s9, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, s9, v0
; GFX9-NEXT: v_mul_lo_u32 v3, s8, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, s8, v1
; GFX9-NEXT: v_mul_hi_u32 v4, s8, v0 ; GFX9-NEXT: v_mul_hi_u32 v4, s8, v0
; GFX9-NEXT: v_mul_lo_u32 v6, s8, v0 ; GFX9-NEXT: v_mul_lo_u32 v6, s8, v0
; GFX9-NEXT: v_add3_u32 v2, v2, v3, v4 ; GFX9-NEXT: v_add3_u32 v2, v2, v3, v4
; GFX9-NEXT: v_sub_co_u32_e32 v3, vcc, s14, v6 ; GFX9-NEXT: v_sub_co_u32_e32 v3, vcc, s12, v6
; GFX9-NEXT: v_subb_co_u32_e64 v4, s[0:1], v7, v2, vcc ; GFX9-NEXT: v_subb_co_u32_e64 v4, s[0:1], v7, v2, vcc
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v4 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v4
; GFX9-NEXT: v_sub_u32_e32 v2, s15, v2 ; GFX9-NEXT: v_sub_u32_e32 v2, s13, v2
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v3 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v3
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v4 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v4
; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v5, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v5, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[0:1]
; GFX9-NEXT: v_subrev_co_u32_e32 v7, vcc, s8, v3 ; GFX9-NEXT: v_subrev_co_u32_e32 v7, vcc, s8, v3
; GFX9-NEXT: v_subbrev_co_u32_e64 v8, s[0:1], 0, v2, vcc ; GFX9-NEXT: v_subbrev_co_u32_e64 v8, s[0:1], 0, v2, vcc
; GFX9-NEXT: v_add_co_u32_e64 v9, s[0:1], 1, v0 ; GFX9-NEXT: v_add_co_u32_e64 v9, s[0:1], 1, v0
; GFX9-NEXT: v_addc_co_u32_e64 v10, s[0:1], 0, v1, s[0:1] ; GFX9-NEXT: v_addc_co_u32_e64 v10, s[0:1], 0, v1, s[0:1]
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v8 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v8
; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v7 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v7
; GFX9-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v8 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v8
; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, v12, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, v12, s[0:1]
; GFX9-NEXT: v_add_co_u32_e64 v12, s[0:1], 1, v9 ; GFX9-NEXT: v_add_co_u32_e64 v12, s[0:1], 1, v9
; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v5, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v5, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v13, s[0:1], 0, v10, s[0:1] ; GFX9-NEXT: v_addc_co_u32_e64 v13, s[0:1], 0, v10, s[0:1]
; GFX9-NEXT: v_subrev_co_u32_e32 v5, vcc, s8, v7 ; GFX9-NEXT: v_subrev_co_u32_e32 v5, vcc, s8, v7
; GFX9-NEXT: v_subbrev_co_u32_e32 v2, vcc, 0, v2, vcc ; GFX9-NEXT: v_subbrev_co_u32_e32 v2, vcc, 0, v2, vcc
; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v11 ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v11
; GFX9-NEXT: v_cndmask_b32_e64 v5, v7, v5, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v5, v7, v5, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v2, v8, v2, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v2, v8, v2, s[0:1]
; GFX9-NEXT: s_xor_b64 s[0:1], s[6:7], s[12:13] ; GFX9-NEXT: s_xor_b64 s[0:1], s[2:3], s[6:7]
; GFX9-NEXT: s_ashr_i32 s8, s11, 31 ; GFX9-NEXT: s_ashr_i32 s6, s11, 31
; GFX9-NEXT: s_ashr_i32 s12, s3, 31 ; GFX9-NEXT: s_ashr_i32 s8, s15, 31
; GFX9-NEXT: s_add_u32 s10, s10, s8 ; GFX9-NEXT: s_add_u32 s12, s10, s6
; GFX9-NEXT: s_cselect_b32 s7, 1, 0 ; GFX9-NEXT: s_cselect_b32 s3, 1, 0
; GFX9-NEXT: s_and_b32 s7, s7, 1 ; GFX9-NEXT: s_and_b32 s3, s3, 1
; GFX9-NEXT: s_cmp_lg_u32 s7, 0 ; GFX9-NEXT: s_cmp_lg_u32 s3, 0
; GFX9-NEXT: s_addc_u32 s11, s11, s8 ; GFX9-NEXT: s_addc_u32 s13, s11, s6
; GFX9-NEXT: s_add_u32 s2, s2, s12 ; GFX9-NEXT: s_add_u32 s10, s14, s8
; GFX9-NEXT: s_cselect_b32 s7, 1, 0 ; GFX9-NEXT: s_cselect_b32 s3, 1, 0
; GFX9-NEXT: s_and_b32 s7, s7, 1 ; GFX9-NEXT: s_and_b32 s3, s3, 1
; GFX9-NEXT: s_cmp_lg_u32 s7, 0 ; GFX9-NEXT: s_cmp_lg_u32 s3, 0
; GFX9-NEXT: s_mov_b32 s13, s12 ; GFX9-NEXT: s_mov_b32 s9, s8
; GFX9-NEXT: s_addc_u32 s3, s3, s12 ; GFX9-NEXT: s_addc_u32 s11, s15, s8
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; GFX9-NEXT: s_xor_b64 s[2:3], s[2:3], s[12:13] ; GFX9-NEXT: s_xor_b64 s[10:11], s[10:11], s[8:9]
; GFX9-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; GFX9-NEXT: v_cvt_f32_u32_e32 v6, s3 ; GFX9-NEXT: v_cvt_f32_u32_e32 v6, s11
; GFX9-NEXT: v_cvt_f32_u32_e32 v7, s2 ; GFX9-NEXT: v_cvt_f32_u32_e32 v7, s10
; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX9-NEXT: v_mul_f32_e32 v4, 0x4f800000, v6 ; GFX9-NEXT: v_mul_f32_e32 v4, 0x4f800000, v6
; GFX9-NEXT: v_add_f32_e32 v4, v4, v7 ; GFX9-NEXT: v_add_f32_e32 v4, v4, v7
; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v4 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v4
; GFX9-NEXT: s_mov_b32 s9, s8 ; GFX9-NEXT: s_mov_b32 s7, s6
; GFX9-NEXT: s_xor_b64 s[10:11], s[10:11], s[8:9] ; GFX9-NEXT: s_xor_b64 s[12:13], s[12:13], s[6:7]
; GFX9-NEXT: s_sub_u32 s7, 0, s2 ; GFX9-NEXT: s_sub_u32 s3, 0, s10
; GFX9-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; GFX9-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
; GFX9-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4 ; GFX9-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4
; GFX9-NEXT: v_trunc_f32_e32 v5, v5 ; GFX9-NEXT: v_trunc_f32_e32 v5, v5
; GFX9-NEXT: v_mul_f32_e32 v6, 0xcf800000, v5 ; GFX9-NEXT: v_mul_f32_e32 v6, 0xcf800000, v5
; GFX9-NEXT: v_add_f32_e32 v4, v6, v4 ; GFX9-NEXT: v_add_f32_e32 v4, v6, v4
; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4 ; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4
; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5 ; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5
; GFX9-NEXT: s_cselect_b32 s14, 1, 0 ; GFX9-NEXT: s_cselect_b32 s14, 1, 0
; GFX9-NEXT: s_and_b32 s14, s14, 1 ; GFX9-NEXT: s_and_b32 s14, s14, 1
; GFX9-NEXT: s_cmp_lg_u32 s14, 0 ; GFX9-NEXT: s_cmp_lg_u32 s14, 0
; GFX9-NEXT: s_subb_u32 s14, 0, s3 ; GFX9-NEXT: s_subb_u32 s14, 0, s11
; GFX9-NEXT: v_mul_lo_u32 v6, s14, v4 ; GFX9-NEXT: v_mul_lo_u32 v6, s14, v4
; GFX9-NEXT: v_mul_lo_u32 v7, s7, v5 ; GFX9-NEXT: v_mul_lo_u32 v7, s3, v5
; GFX9-NEXT: v_mul_hi_u32 v8, s7, v4 ; GFX9-NEXT: v_mul_hi_u32 v8, s3, v4
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc
; GFX9-NEXT: v_mul_lo_u32 v9, s7, v4 ; GFX9-NEXT: v_mul_lo_u32 v9, s3, v4
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v10, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v10, vcc
; GFX9-NEXT: v_xor_b32_e32 v0, s0, v0 ; GFX9-NEXT: v_xor_b32_e32 v0, s0, v0
; GFX9-NEXT: v_add3_u32 v6, v6, v7, v8 ; GFX9-NEXT: v_add3_u32 v6, v6, v7, v8
; GFX9-NEXT: v_xor_b32_e32 v1, s1, v1 ; GFX9-NEXT: v_xor_b32_e32 v1, s1, v1
; GFX9-NEXT: v_mov_b32_e32 v10, s1 ; GFX9-NEXT: v_mov_b32_e32 v10, s1
; GFX9-NEXT: v_mul_lo_u32 v7, v5, v9 ; GFX9-NEXT: v_mul_lo_u32 v7, v5, v9
; GFX9-NEXT: v_mul_lo_u32 v8, v4, v6 ; GFX9-NEXT: v_mul_lo_u32 v8, v4, v6
; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s0, v0 ; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s0, v0
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; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7 ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7
; GFX9-NEXT: v_add_u32_e32 v9, v10, v9 ; GFX9-NEXT: v_add_u32_e32 v9, v10, v9
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX9-NEXT: v_add3_u32 v6, v9, v8, v6 ; GFX9-NEXT: v_add3_u32 v6, v9, v8, v6
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v7 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v7
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v6, vcc
; GFX9-NEXT: v_mul_lo_u32 v6, s14, v4 ; GFX9-NEXT: v_mul_lo_u32 v6, s14, v4
; GFX9-NEXT: v_mul_lo_u32 v7, s7, v5 ; GFX9-NEXT: v_mul_lo_u32 v7, s3, v5
; GFX9-NEXT: v_mul_hi_u32 v8, s7, v4 ; GFX9-NEXT: v_mul_hi_u32 v8, s3, v4
; GFX9-NEXT: v_mul_lo_u32 v9, s7, v4 ; GFX9-NEXT: v_mul_lo_u32 v9, s3, v4
; GFX9-NEXT: v_xor_b32_e32 v3, s6, v3 ; GFX9-NEXT: v_xor_b32_e32 v3, s2, v3
; GFX9-NEXT: v_xor_b32_e32 v2, s6, v2 ; GFX9-NEXT: v_xor_b32_e32 v2, s2, v2
; GFX9-NEXT: v_add3_u32 v6, v6, v7, v8 ; GFX9-NEXT: v_add3_u32 v6, v6, v7, v8
; GFX9-NEXT: v_mul_lo_u32 v7, v5, v9 ; GFX9-NEXT: v_mul_lo_u32 v7, v5, v9
; GFX9-NEXT: v_mul_lo_u32 v8, v4, v6 ; GFX9-NEXT: v_mul_lo_u32 v8, v4, v6
; GFX9-NEXT: v_mul_hi_u32 v11, v4, v9 ; GFX9-NEXT: v_mul_hi_u32 v11, v4, v9
; GFX9-NEXT: v_mul_hi_u32 v9, v5, v9 ; GFX9-NEXT: v_mul_hi_u32 v9, v5, v9
; GFX9-NEXT: v_mov_b32_e32 v10, s6 ; GFX9-NEXT: v_mov_b32_e32 v10, s2
; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v8 ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v8
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v11 ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v11
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX9-NEXT: v_mul_lo_u32 v11, v5, v6 ; GFX9-NEXT: v_mul_lo_u32 v11, v5, v6
; GFX9-NEXT: v_add_u32_e32 v7, v8, v7 ; GFX9-NEXT: v_add_u32_e32 v7, v8, v7
; GFX9-NEXT: v_mul_hi_u32 v8, v4, v6 ; GFX9-NEXT: v_mul_hi_u32 v8, v4, v6
; GFX9-NEXT: v_mul_hi_u32 v6, v5, v6 ; GFX9-NEXT: v_mul_hi_u32 v6, v5, v6
; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v11, v9 ; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v11, v9
; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8 ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8
; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7 ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7
; GFX9-NEXT: v_add_u32_e32 v9, v11, v9 ; GFX9-NEXT: v_add_u32_e32 v9, v11, v9
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX9-NEXT: v_add3_u32 v6, v9, v8, v6 ; GFX9-NEXT: v_add3_u32 v6, v9, v8, v6
; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v4, v7 ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v4, v7
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v5, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v5, v6, vcc
; GFX9-NEXT: v_mul_lo_u32 v8, s11, v7 ; GFX9-NEXT: v_mul_lo_u32 v8, s13, v7
; GFX9-NEXT: v_mul_lo_u32 v9, s10, v6 ; GFX9-NEXT: v_mul_lo_u32 v9, s12, v6
; GFX9-NEXT: v_subrev_co_u32_e32 v4, vcc, s6, v3 ; GFX9-NEXT: v_subrev_co_u32_e32 v4, vcc, s2, v3
; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v2, v10, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v2, v10, vcc
; GFX9-NEXT: v_mul_hi_u32 v2, s10, v7 ; GFX9-NEXT: v_mul_hi_u32 v2, s12, v7
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v8, v9 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v8, v9
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_mul_lo_u32 v3, s11, v6 ; GFX9-NEXT: v_mul_lo_u32 v3, s13, v6
; GFX9-NEXT: v_mul_hi_u32 v7, s11, v7 ; GFX9-NEXT: v_mul_hi_u32 v7, s13, v7
; GFX9-NEXT: v_add_u32_e32 v2, v8, v2 ; GFX9-NEXT: v_add_u32_e32 v2, v8, v2
; GFX9-NEXT: v_mul_hi_u32 v8, s10, v6 ; GFX9-NEXT: v_mul_hi_u32 v8, s12, v6
; GFX9-NEXT: v_mul_hi_u32 v6, s11, v6 ; GFX9-NEXT: v_mul_hi_u32 v6, s13, v6
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v8 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v8
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_add_u32_e32 v7, v7, v8 ; GFX9-NEXT: v_add_u32_e32 v7, v7, v8
; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX9-NEXT: v_add3_u32 v3, v7, v3, v6 ; GFX9-NEXT: v_add3_u32 v3, v7, v3, v6
; GFX9-NEXT: v_mul_lo_u32 v6, s3, v2 ; GFX9-NEXT: v_mul_lo_u32 v6, s11, v2
; GFX9-NEXT: v_mul_lo_u32 v7, s2, v3 ; GFX9-NEXT: v_mul_lo_u32 v7, s10, v3
; GFX9-NEXT: v_mul_hi_u32 v8, s2, v2 ; GFX9-NEXT: v_mul_hi_u32 v8, s10, v2
; GFX9-NEXT: v_mul_lo_u32 v10, s2, v2 ; GFX9-NEXT: v_mul_lo_u32 v10, s10, v2
; GFX9-NEXT: v_mov_b32_e32 v11, s11 ; GFX9-NEXT: v_mov_b32_e32 v11, s13
; GFX9-NEXT: v_mov_b32_e32 v9, s3 ; GFX9-NEXT: v_mov_b32_e32 v9, s11
; GFX9-NEXT: v_add3_u32 v6, v6, v7, v8 ; GFX9-NEXT: v_add3_u32 v6, v6, v7, v8
; GFX9-NEXT: v_sub_co_u32_e32 v7, vcc, s10, v10 ; GFX9-NEXT: v_sub_co_u32_e32 v7, vcc, s12, v10
; GFX9-NEXT: v_subb_co_u32_e64 v8, s[0:1], v11, v6, vcc ; GFX9-NEXT: v_subb_co_u32_e64 v8, s[0:1], v11, v6, vcc
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v8 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v8
; GFX9-NEXT: v_sub_u32_e32 v6, s11, v6 ; GFX9-NEXT: v_sub_u32_e32 v6, s13, v6
; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v7 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v7
; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v8 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v8
; GFX9-NEXT: v_subb_co_u32_e32 v6, vcc, v6, v9, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v6, vcc, v6, v9, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v10, v10, v11, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v10, v10, v11, s[0:1]
; GFX9-NEXT: v_subrev_co_u32_e32 v11, vcc, s2, v7 ; GFX9-NEXT: v_subrev_co_u32_e32 v11, vcc, s10, v7
; GFX9-NEXT: v_subbrev_co_u32_e64 v12, s[0:1], 0, v6, vcc ; GFX9-NEXT: v_subbrev_co_u32_e64 v12, s[0:1], 0, v6, vcc
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v12 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v12
; GFX9-NEXT: v_cndmask_b32_e64 v13, 0, -1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v13, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v11 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v11
; GFX9-NEXT: v_cndmask_b32_e64 v14, 0, -1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v14, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v12 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v12
; GFX9-NEXT: v_cndmask_b32_e64 v13, v13, v14, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v13, v13, v14, s[0:1]
; GFX9-NEXT: v_add_co_u32_e64 v14, s[0:1], 1, v2 ; GFX9-NEXT: v_add_co_u32_e64 v14, s[0:1], 1, v2
; GFX9-NEXT: v_subb_co_u32_e32 v6, vcc, v6, v9, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v6, vcc, v6, v9, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v15, s[0:1], 0, v3, s[0:1] ; GFX9-NEXT: v_addc_co_u32_e64 v15, s[0:1], 0, v3, s[0:1]
; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, 1, v14 ; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, 1, v14
; GFX9-NEXT: v_addc_co_u32_e32 v16, vcc, 0, v15, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v16, vcc, 0, v15, vcc
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13
; GFX9-NEXT: v_cndmask_b32_e32 v9, v14, v9, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v9, v14, v9, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v14, v15, v16, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v14, v15, v16, vcc
; GFX9-NEXT: v_subrev_co_u32_e64 v15, s[0:1], s2, v11 ; GFX9-NEXT: v_subrev_co_u32_e64 v15, s[0:1], s10, v11
; GFX9-NEXT: v_subbrev_co_u32_e64 v6, s[0:1], 0, v6, s[0:1] ; GFX9-NEXT: v_subbrev_co_u32_e64 v6, s[0:1], 0, v6, s[0:1]
; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v10 ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v10
; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v9, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v9, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e32 v9, v11, v15, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v9, v11, v15, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v6, v12, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v6, v12, v6, vcc
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0 ; GFX9-NEXT: s_load_dwordx4 s[12:15], s[4:5], 0x0
; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v14, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v14, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v6, v8, v6, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v6, v8, v6, s[0:1]
; GFX9-NEXT: s_xor_b64 s[0:1], s[8:9], s[12:13] ; GFX9-NEXT: s_xor_b64 s[0:1], s[6:7], s[8:9]
; GFX9-NEXT: v_xor_b32_e32 v2, s0, v2 ; GFX9-NEXT: v_xor_b32_e32 v2, s0, v2
; GFX9-NEXT: v_xor_b32_e32 v3, s1, v3 ; GFX9-NEXT: v_xor_b32_e32 v3, s1, v3
; GFX9-NEXT: v_mov_b32_e32 v8, s1 ; GFX9-NEXT: v_mov_b32_e32 v8, s1
; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s0, v2 ; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s0, v2
; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v8, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v8, vcc
; GFX9-NEXT: v_xor_b32_e32 v7, s8, v7 ; GFX9-NEXT: v_xor_b32_e32 v7, s6, v7
; GFX9-NEXT: v_mov_b32_e32 v13, 0 ; GFX9-NEXT: v_mov_b32_e32 v13, 0
; GFX9-NEXT: v_xor_b32_e32 v8, s8, v6 ; GFX9-NEXT: v_xor_b32_e32 v8, s6, v6
; GFX9-NEXT: v_mov_b32_e32 v9, s8 ; GFX9-NEXT: v_mov_b32_e32 v9, s6
; GFX9-NEXT: v_subrev_co_u32_e32 v6, vcc, s8, v7 ; GFX9-NEXT: v_subrev_co_u32_e32 v6, vcc, s6, v7
; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, v8, v9, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, v8, v9, vcc
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dwordx4 v13, v[0:3], s[4:5] ; GFX9-NEXT: global_store_dwordx4 v13, v[0:3], s[12:13]
; GFX9-NEXT: global_store_dwordx4 v13, v[4:7], s[6:7] ; GFX9-NEXT: global_store_dwordx4 v13, v[4:7], s[14:15]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: sdivrem_v2i64: ; GFX10-LABEL: sdivrem_v2i64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x10
; GFX10-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x10
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x20
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_ashr_i32 s12, s9, 31 ; GFX10-NEXT: s_ashr_i32 s2, s9, 31
; GFX10-NEXT: s_ashr_i32 s6, s1, 31 ; GFX10-NEXT: s_ashr_i32 s6, s13, 31
; GFX10-NEXT: s_add_u32 s14, s8, s12 ; GFX10-NEXT: s_add_u32 s0, s8, s2
; GFX10-NEXT: s_cselect_b32 s7, 1, 0 ; GFX10-NEXT: s_cselect_b32 s1, 1, 0
; GFX10-NEXT: s_mov_b32 s13, s12
; GFX10-NEXT: s_and_b32 s7, s7, 1
; GFX10-NEXT: s_cmp_lg_u32 s7, 0
; GFX10-NEXT: s_addc_u32 s15, s9, s12
; GFX10-NEXT: s_add_u32 s0, s0, s6
; GFX10-NEXT: s_cselect_b32 s7, 1, 0
; GFX10-NEXT: s_and_b32 s8, s7, 1
; GFX10-NEXT: s_mov_b32 s7, s6 ; GFX10-NEXT: s_mov_b32 s7, s6
; GFX10-NEXT: s_cmp_lg_u32 s8, 0 ; GFX10-NEXT: s_and_b32 s1, s1, 1
; GFX10-NEXT: s_addc_u32 s1, s1, s6 ; GFX10-NEXT: s_cmp_lg_u32 s1, 0
; GFX10-NEXT: s_xor_b64 s[8:9], s[0:1], s[6:7] ; GFX10-NEXT: s_addc_u32 s1, s9, s2
; GFX10-NEXT: s_xor_b64 s[0:1], s[14:15], s[12:13] ; GFX10-NEXT: s_add_u32 s8, s12, s6
; GFX10-NEXT: s_cselect_b32 s3, 1, 0
; GFX10-NEXT: s_and_b32 s3, s3, 1
; GFX10-NEXT: s_cmp_lg_u32 s3, 0
; GFX10-NEXT: s_mov_b32 s3, s2
; GFX10-NEXT: s_addc_u32 s9, s13, s6
; GFX10-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[6:7]
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s9 ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s9
; GFX10-NEXT: s_sub_u32 s20, 0, s8 ; GFX10-NEXT: s_sub_u32 s20, 0, s8
; GFX10-NEXT: s_cselect_b32 s14, 1, 0 ; GFX10-NEXT: s_cselect_b32 s12, 1, 0
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s8 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s8
; GFX10-NEXT: s_and_b32 s14, s14, 1 ; GFX10-NEXT: s_and_b32 s12, s12, 1
; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f800000, v1 ; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f800000, v1
; GFX10-NEXT: s_cmp_lg_u32 s14, 0 ; GFX10-NEXT: s_cmp_lg_u32 s12, 0
; GFX10-NEXT: s_subb_u32 s21, 0, s9 ; GFX10-NEXT: s_subb_u32 s21, 0, s9
; GFX10-NEXT: s_ashr_i32 s14, s11, 31 ; GFX10-NEXT: s_ashr_i32 s12, s11, 31
; GFX10-NEXT: s_xor_b64 s[18:19], s[12:13], s[6:7] ; GFX10-NEXT: s_xor_b64 s[18:19], s[2:3], s[6:7]
; GFX10-NEXT: s_ashr_i32 s16, s3, 31 ; GFX10-NEXT: s_ashr_i32 s16, s15, 31
; GFX10-NEXT: v_add_f32_e32 v0, v1, v0 ; GFX10-NEXT: v_add_f32_e32 v0, v1, v0
; GFX10-NEXT: s_add_u32 s6, s10, s14 ; GFX10-NEXT: s_add_u32 s6, s10, s12
; GFX10-NEXT: s_cselect_b32 s7, 1, 0 ; GFX10-NEXT: s_cselect_b32 s3, 1, 0
; GFX10-NEXT: s_mov_b32 s17, s16 ; GFX10-NEXT: s_mov_b32 s17, s16
; GFX10-NEXT: s_and_b32 s7, s7, 1 ; GFX10-NEXT: s_and_b32 s3, s3, 1
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: s_cmp_lg_u32 s7, 0 ; GFX10-NEXT: s_cmp_lg_u32 s3, 0
; GFX10-NEXT: s_mov_b32 s15, s14 ; GFX10-NEXT: s_mov_b32 s13, s12
; GFX10-NEXT: s_addc_u32 s7, s11, s14 ; GFX10-NEXT: s_addc_u32 s7, s11, s12
; GFX10-NEXT: s_add_u32 s2, s2, s16 ; GFX10-NEXT: s_add_u32 s10, s14, s16
; GFX10-NEXT: s_cselect_b32 s10, 1, 0 ; GFX10-NEXT: s_cselect_b32 s3, 1, 0
; GFX10-NEXT: s_and_b32 s10, s10, 1 ; GFX10-NEXT: s_and_b32 s3, s3, 1
; GFX10-NEXT: s_cmp_lg_u32 s10, 0 ; GFX10-NEXT: s_cmp_lg_u32 s3, 0
; GFX10-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX10-NEXT: s_addc_u32 s3, s3, s16 ; GFX10-NEXT: s_addc_u32 s11, s15, s16
; GFX10-NEXT: s_xor_b64 s[10:11], s[6:7], s[14:15] ; GFX10-NEXT: s_xor_b64 s[14:15], s[6:7], s[12:13]
; GFX10-NEXT: s_xor_b64 s[2:3], s[2:3], s[16:17] ; GFX10-NEXT: s_xor_b64 s[10:11], s[10:11], s[16:17]
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s3 ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s11
; GFX10-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0 ; GFX10-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0
; GFX10-NEXT: v_cvt_f32_u32_e32 v3, s2 ; GFX10-NEXT: v_cvt_f32_u32_e32 v3, s10
; GFX10-NEXT: s_sub_u32 s6, 0, s2 ; GFX10-NEXT: s_sub_u32 s3, 0, s10
; GFX10-NEXT: s_cselect_b32 s7, 1, 0 ; GFX10-NEXT: s_cselect_b32 s6, 1, 0
; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f800000, v1 ; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f800000, v1
; GFX10-NEXT: v_trunc_f32_e32 v2, v2 ; GFX10-NEXT: v_trunc_f32_e32 v2, v2
; GFX10-NEXT: s_and_b32 s7, s7, 1 ; GFX10-NEXT: s_and_b32 s6, s6, 1
; GFX10-NEXT: s_cmp_lg_u32 s7, 0 ; GFX10-NEXT: s_cmp_lg_u32 s6, 0
; GFX10-NEXT: v_add_f32_e32 v1, v1, v3 ; GFX10-NEXT: v_add_f32_e32 v1, v1, v3
; GFX10-NEXT: v_mul_f32_e32 v3, 0xcf800000, v2 ; GFX10-NEXT: v_mul_f32_e32 v3, 0xcf800000, v2
; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX10-NEXT: s_subb_u32 s7, 0, s3 ; GFX10-NEXT: s_subb_u32 s6, 0, s11
; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX10-NEXT: v_add_f32_e32 v0, v3, v0 ; GFX10-NEXT: v_add_f32_e32 v0, v3, v0
; GFX10-NEXT: v_mul_lo_u32 v3, s20, v2 ; GFX10-NEXT: v_mul_lo_u32 v3, s20, v2
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v1 ; GFX10-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v1
; GFX10-NEXT: v_mul_lo_u32 v4, s21, v0 ; GFX10-NEXT: v_mul_lo_u32 v4, s21, v0
; GFX10-NEXT: v_mul_hi_u32 v5, s20, v0 ; GFX10-NEXT: v_mul_hi_u32 v5, s20, v0
; GFX10-NEXT: v_mul_lo_u32 v6, s20, v0 ; GFX10-NEXT: v_mul_lo_u32 v6, s20, v0
; GFX10-NEXT: v_mul_f32_e32 v7, 0x2f800000, v1 ; GFX10-NEXT: v_mul_f32_e32 v7, 0x2f800000, v1
; GFX10-NEXT: v_add3_u32 v3, v4, v3, v5 ; GFX10-NEXT: v_add3_u32 v3, v4, v3, v5
; GFX10-NEXT: v_trunc_f32_e32 v4, v7 ; GFX10-NEXT: v_trunc_f32_e32 v4, v7
; GFX10-NEXT: v_mul_lo_u32 v5, v2, v6 ; GFX10-NEXT: v_mul_lo_u32 v5, v2, v6
; GFX10-NEXT: v_mul_hi_u32 v7, v0, v6 ; GFX10-NEXT: v_mul_hi_u32 v7, v0, v6
; GFX10-NEXT: v_mul_hi_u32 v6, v2, v6 ; GFX10-NEXT: v_mul_hi_u32 v6, v2, v6
; GFX10-NEXT: v_mul_lo_u32 v8, v0, v3 ; GFX10-NEXT: v_mul_lo_u32 v8, v0, v3
; GFX10-NEXT: v_mul_lo_u32 v10, v2, v3 ; GFX10-NEXT: v_mul_lo_u32 v10, v2, v3
; GFX10-NEXT: v_mul_f32_e32 v9, 0xcf800000, v4 ; GFX10-NEXT: v_mul_f32_e32 v9, 0xcf800000, v4
; GFX10-NEXT: v_mul_hi_u32 v11, v0, v3 ; GFX10-NEXT: v_mul_hi_u32 v11, v0, v3
; GFX10-NEXT: v_cvt_u32_f32_e32 v4, v4 ; GFX10-NEXT: v_cvt_u32_f32_e32 v4, v4
; GFX10-NEXT: v_mul_hi_u32 v3, v2, v3 ; GFX10-NEXT: v_mul_hi_u32 v3, v2, v3
; GFX10-NEXT: v_add_f32_e32 v1, v9, v1 ; GFX10-NEXT: v_add_f32_e32 v1, v9, v1
; GFX10-NEXT: v_add_co_u32 v5, s13, v5, v8 ; GFX10-NEXT: v_add_co_u32 v5, s7, v5, v8
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s13 ; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s7
; GFX10-NEXT: v_add_co_u32 v6, s13, v10, v6 ; GFX10-NEXT: v_add_co_u32 v6, s7, v10, v6
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s13 ; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s7
; GFX10-NEXT: v_add_co_u32 v5, s13, v5, v7 ; GFX10-NEXT: v_add_co_u32 v5, s7, v5, v7
; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s13 ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s7
; GFX10-NEXT: v_mul_lo_u32 v9, s6, v4 ; GFX10-NEXT: v_mul_lo_u32 v9, s3, v4
; GFX10-NEXT: v_add_co_u32 v6, s13, v6, v11 ; GFX10-NEXT: v_add_co_u32 v6, s7, v6, v11
; GFX10-NEXT: v_mul_lo_u32 v12, s7, v1 ; GFX10-NEXT: v_mul_lo_u32 v12, s6, v1
; GFX10-NEXT: v_mul_hi_u32 v13, s6, v1 ; GFX10-NEXT: v_mul_hi_u32 v13, s3, v1
; GFX10-NEXT: v_add_nc_u32_e32 v5, v8, v5 ; GFX10-NEXT: v_add_nc_u32_e32 v5, v8, v5
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s13 ; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s7
; GFX10-NEXT: v_mul_lo_u32 v11, s6, v1 ; GFX10-NEXT: v_mul_lo_u32 v11, s3, v1
; GFX10-NEXT: v_add_co_u32 v5, s13, v6, v5 ; GFX10-NEXT: v_add_co_u32 v5, s7, v6, v5
; GFX10-NEXT: v_add_nc_u32_e32 v7, v10, v7 ; GFX10-NEXT: v_add_nc_u32_e32 v7, v10, v7
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s13 ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s7
; GFX10-NEXT: v_add3_u32 v8, v12, v9, v13 ; GFX10-NEXT: v_add3_u32 v8, v12, v9, v13
; GFX10-NEXT: v_mul_lo_u32 v9, v4, v11 ; GFX10-NEXT: v_mul_lo_u32 v9, v4, v11
; GFX10-NEXT: v_mul_hi_u32 v10, v1, v11 ; GFX10-NEXT: v_mul_hi_u32 v10, v1, v11
; GFX10-NEXT: v_mul_hi_u32 v11, v4, v11 ; GFX10-NEXT: v_mul_hi_u32 v11, v4, v11
; GFX10-NEXT: v_add3_u32 v3, v7, v6, v3 ; GFX10-NEXT: v_add3_u32 v3, v7, v6, v3
; GFX10-NEXT: v_mul_lo_u32 v6, v1, v8 ; GFX10-NEXT: v_mul_lo_u32 v6, v1, v8
; GFX10-NEXT: v_mul_lo_u32 v7, v4, v8 ; GFX10-NEXT: v_mul_lo_u32 v7, v4, v8
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v5 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v5
; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v2, v3, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v2, v3, vcc_lo
; GFX10-NEXT: v_mul_hi_u32 v5, v1, v8 ; GFX10-NEXT: v_mul_hi_u32 v5, v1, v8
; GFX10-NEXT: v_mul_lo_u32 v12, s21, v0 ; GFX10-NEXT: v_mul_lo_u32 v12, s21, v0
; GFX10-NEXT: v_add_co_u32 v6, s13, v9, v6 ; GFX10-NEXT: v_add_co_u32 v6, s7, v9, v6
; GFX10-NEXT: v_mul_hi_u32 v13, s20, v0 ; GFX10-NEXT: v_mul_hi_u32 v13, s20, v0
; GFX10-NEXT: v_mul_lo_u32 v14, s20, v2 ; GFX10-NEXT: v_mul_lo_u32 v14, s20, v2
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s13 ; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s7
; GFX10-NEXT: v_add_co_u32 v7, s13, v7, v11 ; GFX10-NEXT: v_add_co_u32 v7, s7, v7, v11
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 1, s13 ; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 1, s7
; GFX10-NEXT: v_add_co_u32 v6, s13, v6, v10 ; GFX10-NEXT: v_add_co_u32 v6, s7, v6, v10
; GFX10-NEXT: v_mul_lo_u32 v3, s20, v0 ; GFX10-NEXT: v_mul_lo_u32 v3, s20, v0
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s13 ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s7
; GFX10-NEXT: v_add_co_u32 v5, s13, v7, v5 ; GFX10-NEXT: v_add_co_u32 v5, s7, v7, v5
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s13 ; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s7
; GFX10-NEXT: v_add3_u32 v12, v12, v14, v13 ; GFX10-NEXT: v_add3_u32 v12, v12, v14, v13
; GFX10-NEXT: v_add_nc_u32_e32 v6, v9, v6 ; GFX10-NEXT: v_add_nc_u32_e32 v6, v9, v6
; GFX10-NEXT: v_mul_hi_u32 v8, v4, v8 ; GFX10-NEXT: v_mul_hi_u32 v8, v4, v8
; GFX10-NEXT: v_mul_lo_u32 v10, v2, v3 ; GFX10-NEXT: v_mul_lo_u32 v10, v2, v3
; GFX10-NEXT: v_add_nc_u32_e32 v7, v11, v7 ; GFX10-NEXT: v_add_nc_u32_e32 v7, v11, v7
; GFX10-NEXT: v_mul_lo_u32 v11, v0, v12 ; GFX10-NEXT: v_mul_lo_u32 v11, v0, v12
; GFX10-NEXT: v_add_co_u32 v5, s13, v5, v6 ; GFX10-NEXT: v_add_co_u32 v5, s7, v5, v6
; GFX10-NEXT: v_mul_hi_u32 v9, v0, v3 ; GFX10-NEXT: v_mul_hi_u32 v9, v0, v3
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s13 ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s7
; GFX10-NEXT: v_mul_hi_u32 v3, v2, v3 ; GFX10-NEXT: v_mul_hi_u32 v3, v2, v3
; GFX10-NEXT: v_mul_lo_u32 v13, v2, v12 ; GFX10-NEXT: v_mul_lo_u32 v13, v2, v12
; GFX10-NEXT: v_add_co_u32 v1, vcc_lo, v1, v5 ; GFX10-NEXT: v_add_co_u32 v1, vcc_lo, v1, v5
; GFX10-NEXT: v_add_co_u32 v5, s13, v10, v11 ; GFX10-NEXT: v_add_co_u32 v5, s7, v10, v11
; GFX10-NEXT: v_mul_hi_u32 v14, v0, v12
; GFX10-NEXT: v_add3_u32 v6, v7, v6, v8 ; GFX10-NEXT: v_add3_u32 v6, v7, v6, v8
; GFX10-NEXT: v_mul_lo_u32 v10, s7, v1 ; GFX10-NEXT: v_mul_hi_u32 v14, v0, v12
; GFX10-NEXT: v_add_co_u32 v5, s7, v5, v9 ; GFX10-NEXT: v_mul_lo_u32 v10, s6, v1
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s13 ; GFX10-NEXT: v_add_co_u32 v5, s6, v5, v9
; GFX10-NEXT: v_add_co_u32 v3, s13, v13, v3 ; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s7
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s7 ; GFX10-NEXT: v_add_co_u32 v3, s7, v13, v3
; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, v4, v6, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, v4, v6, vcc_lo
; GFX10-NEXT: v_add_co_u32 v3, s7, v3, v14 ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s6
; GFX10-NEXT: v_mul_hi_u32 v11, s3, v1
; GFX10-NEXT: v_add_co_u32 v3, s6, v3, v14
; GFX10-NEXT: v_mul_lo_u32 v13, s3, v4
; GFX10-NEXT: v_add_nc_u32_e32 v5, v7, v5 ; GFX10-NEXT: v_add_nc_u32_e32 v5, v7, v5
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s13 ; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s7
; GFX10-NEXT: v_mul_hi_u32 v11, s6, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s6
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s7
; GFX10-NEXT: v_mul_lo_u32 v13, s6, v4
; GFX10-NEXT: v_mul_hi_u32 v7, v2, v12 ; GFX10-NEXT: v_mul_hi_u32 v7, v2, v12
; GFX10-NEXT: v_mul_lo_u32 v6, s6, v1 ; GFX10-NEXT: v_mul_lo_u32 v6, s3, v1
; GFX10-NEXT: v_add_co_u32 v3, s6, v3, v5 ; GFX10-NEXT: v_add_co_u32 v3, s3, v3, v5
; GFX10-NEXT: v_add_nc_u32_e32 v8, v8, v9 ; GFX10-NEXT: v_add_nc_u32_e32 v8, v8, v9
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s6 ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s3
; GFX10-NEXT: v_add3_u32 v9, v10, v13, v11 ; GFX10-NEXT: v_add3_u32 v9, v10, v13, v11
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v3 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v3
; GFX10-NEXT: v_add3_u32 v5, v8, v5, v7
; GFX10-NEXT: v_mul_lo_u32 v10, v4, v6 ; GFX10-NEXT: v_mul_lo_u32 v10, v4, v6
; GFX10-NEXT: v_add3_u32 v5, v8, v5, v7
; GFX10-NEXT: v_mul_lo_u32 v7, v1, v9 ; GFX10-NEXT: v_mul_lo_u32 v7, v1, v9
; GFX10-NEXT: v_mul_hi_u32 v11, v1, v6 ; GFX10-NEXT: v_mul_hi_u32 v11, v1, v6
; GFX10-NEXT: v_mul_hi_u32 v6, v4, v6 ; GFX10-NEXT: v_mul_hi_u32 v6, v4, v6
; GFX10-NEXT: v_mul_lo_u32 v8, v4, v9
; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v2, v5, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v2, v5, vcc_lo
; GFX10-NEXT: v_mul_lo_u32 v3, v4, v9 ; GFX10-NEXT: v_mul_hi_u32 v3, v1, v9
; GFX10-NEXT: v_mul_lo_u32 v5, s1, v0 ; GFX10-NEXT: v_mul_lo_u32 v5, s1, v0
; GFX10-NEXT: v_mul_hi_u32 v12, s0, v0 ; GFX10-NEXT: v_add_co_u32 v7, s3, v10, v7
; GFX10-NEXT: v_mul_lo_u32 v13, s0, v2 ; GFX10-NEXT: v_mul_lo_u32 v13, s0, v2
; GFX10-NEXT: v_add_co_u32 v7, s6, v10, v7 ; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s3
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s6 ; GFX10-NEXT: v_add_co_u32 v6, s3, v8, v6
; GFX10-NEXT: v_mul_hi_u32 v12, s0, v0
; GFX10-NEXT: v_mul_hi_u32 v0, s1, v0 ; GFX10-NEXT: v_mul_hi_u32 v0, s1, v0
; GFX10-NEXT: v_add_co_u32 v3, s6, v3, v6
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s6
; GFX10-NEXT: v_add_co_u32 v7, s6, v7, v11
; GFX10-NEXT: v_mul_lo_u32 v14, s1, v2 ; GFX10-NEXT: v_mul_lo_u32 v14, s1, v2
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s6 ; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s3
; GFX10-NEXT: v_add_co_u32 v5, s6, v5, v13 ; GFX10-NEXT: v_add_co_u32 v7, s3, v7, v11
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s3
; GFX10-NEXT: v_add_co_u32 v3, s3, v6, v3
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s3
; GFX10-NEXT: v_add_co_u32 v5, s3, v5, v13
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 1, s3
; GFX10-NEXT: v_add_co_u32 v0, s3, v14, v0
; GFX10-NEXT: v_mul_hi_u32 v15, s0, v2 ; GFX10-NEXT: v_mul_hi_u32 v15, s0, v2
; GFX10-NEXT: v_mul_hi_u32 v8, v1, v9 ; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, 1, s3
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 1, s6 ; GFX10-NEXT: v_add_co_u32 v5, s3, v5, v12
; GFX10-NEXT: v_add_co_u32 v5, s7, v5, v12 ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s3
; GFX10-NEXT: v_add_co_u32 v0, s6, v14, v0
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s7
; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, 1, s6
; GFX10-NEXT: v_mul_hi_u32 v2, s1, v2 ; GFX10-NEXT: v_mul_hi_u32 v2, s1, v2
; GFX10-NEXT: v_add_co_u32 v0, s6, v0, v15
; GFX10-NEXT: v_add_nc_u32_e32 v5, v11, v5
; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, 1, s6
; GFX10-NEXT: v_add_co_u32 v3, s6, v3, v8
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s6
; GFX10-NEXT: v_add_co_u32 v0, s6, v0, v5
; GFX10-NEXT: v_add_nc_u32_e32 v11, v12, v13
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s6
; GFX10-NEXT: v_add_nc_u32_e32 v7, v10, v7 ; GFX10-NEXT: v_add_nc_u32_e32 v7, v10, v7
; GFX10-NEXT: v_add_nc_u32_e32 v6, v8, v6
; GFX10-NEXT: v_add_co_u32 v0, s3, v0, v15
; GFX10-NEXT: v_add_nc_u32_e32 v5, v11, v5
; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, 1, s3
; GFX10-NEXT: v_mul_hi_u32 v9, v4, v9 ; GFX10-NEXT: v_mul_hi_u32 v9, v4, v9
; GFX10-NEXT: v_add_nc_u32_e32 v6, v6, v8
; GFX10-NEXT: v_mul_hi_u32 v8, s8, v0
; GFX10-NEXT: v_add3_u32 v2, v11, v5, v2
; GFX10-NEXT: v_add_co_u32 v3, s6, v3, v7
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s6
; GFX10-NEXT: v_mul_lo_u32 v7, s9, v0
; GFX10-NEXT: v_mul_lo_u32 v10, s8, v2
; GFX10-NEXT: v_add_co_u32 v1, vcc_lo, v1, v3
; GFX10-NEXT: v_add3_u32 v5, v6, v5, v9
; GFX10-NEXT: v_mul_lo_u32 v6, s8, v0
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX10-NEXT: v_mov_b32_e32 v9, 0 ; GFX10-NEXT: v_add_co_u32 v0, s3, v0, v5
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v4, v5, vcc_lo ; GFX10-NEXT: v_add_nc_u32_e32 v8, v13, v12
; GFX10-NEXT: v_add3_u32 v4, v7, v10, v8 ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s3
; GFX10-NEXT: v_mul_lo_u32 v5, s11, v1 ; GFX10-NEXT: v_add_co_u32 v3, s3, v3, v7
; GFX10-NEXT: v_sub_co_u32 v6, vcc_lo, s0, v6 ; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s3
; GFX10-NEXT: v_mul_lo_u32 v14, s10, v3 ; GFX10-NEXT: v_add3_u32 v2, v8, v5, v2
; GFX10-NEXT: v_sub_nc_u32_e32 v8, s1, v4 ; GFX10-NEXT: v_add_co_u32 v1, vcc_lo, v1, v3
; GFX10-NEXT: v_sub_co_ci_u32_e64 v4, s0, s1, v4, vcc_lo ; GFX10-NEXT: v_add3_u32 v5, v6, v7, v9
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s8, v6 ; GFX10-NEXT: v_mul_lo_u32 v6, s9, v0
; GFX10-NEXT: v_mul_hi_u32 v7, s11, v1 ; GFX10-NEXT: v_mul_hi_u32 v7, s8, v0
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo ; GFX10-NEXT: v_mul_lo_u32 v9, s8, v2
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s9, v4 ; GFX10-NEXT: v_mul_lo_u32 v3, s8, v0
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, -1, s0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, v4, v5, vcc_lo
; GFX10-NEXT: v_mul_lo_u32 v15, s11, v3 ; GFX10-NEXT: v_mul_lo_u32 v5, s15, v1
; GFX10-NEXT: v_mul_hi_u32 v1, s10, v1 ; GFX10-NEXT: v_mul_hi_u32 v10, s15, v1
; GFX10-NEXT: v_mul_hi_u32 v17, s10, v3 ; GFX10-NEXT: v_mul_hi_u32 v1, s14, v1
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc_lo ; GFX10-NEXT: v_mul_hi_u32 v17, s14, v4
; GFX10-NEXT: v_sub_co_u32 v12, vcc_lo, v6, s8 ; GFX10-NEXT: v_add3_u32 v6, v6, v9, v7
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v13, s0, 0, v8, vcc_lo ; GFX10-NEXT: v_sub_co_u32 v3, vcc_lo, s0, v3
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s9, v4 ; GFX10-NEXT: v_mul_lo_u32 v7, s14, v4
; GFX10-NEXT: v_mul_hi_u32 v3, s11, v3 ; GFX10-NEXT: v_mul_lo_u32 v9, s15, v4
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo ; GFX10-NEXT: v_sub_nc_u32_e32 v11, s1, v6
; GFX10-NEXT: v_cndmask_b32_e64 v10, v11, v10, s0 ; GFX10-NEXT: v_sub_co_ci_u32_e64 v6, s0, s1, v6, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s9, v13 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s8, v3
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, -1, s0 ; GFX10-NEXT: v_mul_hi_u32 v4, s15, v4
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s8, v12 ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s9, v6
; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, -1, s0
; GFX10-NEXT: v_mov_b32_e32 v8, 0
; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, -1, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v14, vcc_lo, v3, s8
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v15, s0, 0, v11, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s9, v6
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v12, v13, v12, s0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s8, v14
; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, -1, s0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s9, v15
; GFX10-NEXT: v_cndmask_b32_e64 v16, 0, -1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v16, 0, -1, s0
; GFX10-NEXT: v_add_co_u32 v5, s0, v5, v14 ; GFX10-NEXT: v_add_co_u32 v5, s0, v5, v7
; GFX10-NEXT: v_cndmask_b32_e64 v14, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v7, s0, v15, v7 ; GFX10-NEXT: v_add_co_u32 v9, s0, v9, v10
; GFX10-NEXT: v_add_co_u32 v1, s1, v5, v1 ; GFX10-NEXT: v_add_co_u32 v1, s1, v5, v1
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s1
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v7, s0, v7, v17 ; GFX10-NEXT: v_add_co_u32 v9, s0, v9, v17
; GFX10-NEXT: v_cndmask_b32_e64 v15, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v17, s0, v0, 1 ; GFX10-NEXT: v_add_co_u32 v17, s0, v0, 1
; GFX10-NEXT: v_add_co_ci_u32_e64 v18, s0, 0, v2, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v18, s0, 0, v2, s0
; GFX10-NEXT: v_add_nc_u32_e32 v1, v14, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v1, v7, v1
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s9, v13 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s9, v15
; GFX10-NEXT: v_add_nc_u32_e32 v5, v5, v15 ; GFX10-NEXT: v_add_nc_u32_e32 v5, v5, v10
; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v16, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v16, v13, s0
; GFX10-NEXT: v_add_co_u32 v7, s0, v7, v1 ; GFX10-NEXT: v_add_co_u32 v9, s0, v9, v1
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v14, s0, v17, 1 ; GFX10-NEXT: v_add_co_u32 v10, s0, v17, 1
; GFX10-NEXT: v_add_co_ci_u32_e64 v15, s0, 0, v18, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v13, s0, 0, v18, s0
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v11 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v7
; GFX10-NEXT: v_add3_u32 v3, v5, v1, v3 ; GFX10-NEXT: v_add3_u32 v4, v5, v1, v4
; GFX10-NEXT: v_sub_co_u32 v1, s0, v12, s8 ; GFX10-NEXT: v_sub_co_u32 v1, s0, v14, s8
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v5, s0, 0, v8, s0 ; GFX10-NEXT: v_subrev_co_ci_u32_e64 v5, s0, 0, v11, s0
; GFX10-NEXT: v_cndmask_b32_e32 v8, v17, v14, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v10, v17, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v14, v18, v15, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v11, v18, v13, vcc_lo
; GFX10-NEXT: v_mul_lo_u32 v15, s3, v7 ; GFX10-NEXT: v_mul_lo_u32 v13, s11, v9
; GFX10-NEXT: v_mul_lo_u32 v16, s2, v3 ; GFX10-NEXT: v_mul_lo_u32 v16, s10, v4
; GFX10-NEXT: v_mul_hi_u32 v17, s2, v7 ; GFX10-NEXT: v_mul_hi_u32 v17, s10, v9
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12
; GFX10-NEXT: v_mul_lo_u32 v10, s2, v7 ; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v7
; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v11 ; GFX10-NEXT: v_mul_lo_u32 v7, s10, v9
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v14, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v1, v14, v1, s0
; GFX10-NEXT: v_add3_u32 v8, v15, v16, v17 ; GFX10-NEXT: v_add3_u32 v10, v13, v16, v17
; GFX10-NEXT: v_cndmask_b32_e64 v1, v12, v1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v5, v15, v5, s0
; GFX10-NEXT: v_cndmask_b32_e64 v5, v13, v5, s0 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v11, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v10, s0, s10, v10 ; GFX10-NEXT: v_sub_co_u32 v7, s0, s14, v7
; GFX10-NEXT: v_sub_co_ci_u32_e64 v11, s1, s11, v8, s0 ; GFX10-NEXT: v_sub_co_ci_u32_e64 v11, s1, s15, v10, s0
; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc_lo
; GFX10-NEXT: v_sub_nc_u32_e32 v1, s11, v8 ; GFX10-NEXT: v_sub_nc_u32_e32 v1, s15, v10
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s3, v11 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s11, v11
; GFX10-NEXT: v_xor_b32_e32 v0, s18, v0 ; GFX10-NEXT: v_xor_b32_e32 v0, s18, v0
; GFX10-NEXT: v_xor_b32_e32 v2, s19, v2 ; GFX10-NEXT: v_xor_b32_e32 v2, s19, v2
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc_lo ; GFX10-NEXT: v_xor_b32_e32 v5, s2, v5
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v8, vcc_lo, s3, v1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v10 ; GFX10-NEXT: v_subrev_co_ci_u32_e64 v10, vcc_lo, s11, v1, s0
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s10, v7
; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v13, vcc_lo, v10, s2 ; GFX10-NEXT: v_sub_co_u32 v13, vcc_lo, v7, s10
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v14, s0, 0, v8, vcc_lo ; GFX10-NEXT: v_subrev_co_ci_u32_e64 v14, s0, 0, v10, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v0, s0, v0, s18 ; GFX10-NEXT: v_sub_co_u32 v0, s0, v0, s18
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v1, s0, s19, v2, s0 ; GFX10-NEXT: v_subrev_co_ci_u32_e64 v1, s0, s19, v2, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s3, v11 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s11, v11
; GFX10-NEXT: v_xor_b32_e32 v2, s12, v6 ; GFX10-NEXT: v_xor_b32_e32 v2, s2, v3
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v10, vcc_lo, s11, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v12, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v6, v12, s0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s3, v14 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s11, v14
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, -1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, -1, s0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s2, v13 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s10, v13
; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, -1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, -1, s0
; GFX10-NEXT: v_add_co_u32 v15, s0, v7, 1 ; GFX10-NEXT: v_add_co_u32 v15, s0, v9, 1
; GFX10-NEXT: v_add_co_ci_u32_e64 v16, s0, 0, v3, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v16, s0, 0, v4, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s3, v14 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s11, v14
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v12, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v12, s0
; GFX10-NEXT: v_add_co_u32 v12, s0, v15, 1 ; GFX10-NEXT: v_add_co_u32 v12, s0, v15, 1
; GFX10-NEXT: v_add_co_ci_u32_e64 v17, s0, 0, v16, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v17, s0, 0, v16, s0
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
; GFX10-NEXT: v_sub_co_u32 v6, s0, v13, s2 ; GFX10-NEXT: v_sub_co_u32 v6, s0, v13, s10
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v8, s0, 0, v8, s0 ; GFX10-NEXT: v_subrev_co_ci_u32_e64 v10, s0, 0, v10, s0
; GFX10-NEXT: v_cndmask_b32_e32 v12, v15, v12, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v12, v15, v12, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v5 ; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v3
; GFX10-NEXT: v_cndmask_b32_e32 v15, v16, v17, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v15, v16, v17, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v5, v13, v6, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v13, v6, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v6, v14, v8, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v6, v14, v10, vcc_lo
; GFX10-NEXT: v_xor_b32_e32 v8, s12, v4 ; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v12, s0
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v12, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v10, v4, v15, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v15, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v5, s0
; GFX10-NEXT: v_cndmask_b32_e64 v6, v11, v6, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v11, v6, s0
; GFX10-NEXT: s_xor_b64 s[0:1], s[14:15], s[16:17] ; GFX10-NEXT: s_xor_b64 s[0:1], s[12:13], s[16:17]
; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v2, s12 ; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v2, s2
; GFX10-NEXT: v_xor_b32_e32 v2, s0, v7 ; GFX10-NEXT: v_xor_b32_e32 v2, s0, v9
; GFX10-NEXT: v_xor_b32_e32 v3, s1, v3 ; GFX10-NEXT: v_xor_b32_e32 v7, s1, v10
; GFX10-NEXT: v_xor_b32_e32 v7, s14, v10 ; GFX10-NEXT: v_xor_b32_e32 v9, s12, v3
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v5, vcc_lo, s12, v8, vcc_lo ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v5, vcc_lo, s2, v5, vcc_lo
; GFX10-NEXT: v_xor_b32_e32 v8, s14, v6 ; GFX10-NEXT: v_xor_b32_e32 v10, s12, v6
; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, v2, s0 ; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, v2, s0
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v3, vcc_lo, s1, v7, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v6, vcc_lo, v7, s14 ; GFX10-NEXT: v_sub_co_u32 v6, vcc_lo, v9, s12
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v7, vcc_lo, s14, v8, vcc_lo ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v7, vcc_lo, s12, v10, vcc_lo
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_store_dwordx4 v9, v[0:3], s[4:5] ; GFX10-NEXT: global_store_dwordx4 v8, v[0:3], s[4:5]
; GFX10-NEXT: global_store_dwordx4 v9, v[4:7], s[6:7] ; GFX10-NEXT: global_store_dwordx4 v8, v[4:7], s[6:7]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%div = sdiv <2 x i64> %x, %y %div = sdiv <2 x i64> %x, %y
store <2 x i64> %div, <2 x i64> addrspace(1)* %out0 store <2 x i64> %div, <2 x i64> addrspace(1)* %out0
%rem = srem <2 x i64> %x, %y %rem = srem <2 x i64> %x, %y
store <2 x i64> %rem, <2 x i64> addrspace(1)* %out1 store <2 x i64> %rem, <2 x i64> addrspace(1)* %out1
ret void ret void
} }
▲ Show 20 Lines • Show All 551 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_endpgm
%rem = srem i16 %x, %y %rem = srem i16 %x, %y
store i16 %rem, i16 addrspace(1)* %out1 store i16 %rem, i16 addrspace(1)* %out1
ret void ret void
} }
define amdgpu_kernel void @sdivrem_v2i16(<2 x i16> addrspace(1)* %out0, <2 x i16> addrspace(1)* %out1, <2 x i16> %x, <2 x i16> %y) { define amdgpu_kernel void @sdivrem_v2i16(<2 x i16> addrspace(1)* %out0, <2 x i16> addrspace(1)* %out1, <2 x i16> %x, <2 x i16> %y) {
; GFX8-LABEL: sdivrem_v2i16: ; GFX8-LABEL: sdivrem_v2i16:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dword s0, s[4:5], 0x14 ; GFX8-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x10
; GFX8-NEXT: s_load_dword s8, s[4:5], 0x10 ; GFX8-NEXT: s_mov_b32 s10, 0x100010
; GFX8-NEXT: s_mov_b32 s9, 0x100010
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_sext_i32_i16 s1, s0 ; GFX8-NEXT: s_sext_i32_i16 s0, s3
; GFX8-NEXT: s_ashr_i32 s2, s1, 31 ; GFX8-NEXT: s_ashr_i32 s8, s0, 31
; GFX8-NEXT: s_add_i32 s1, s1, s2 ; GFX8-NEXT: s_add_i32 s0, s0, s8
; GFX8-NEXT: s_xor_b32 s3, s1, s2 ; GFX8-NEXT: s_xor_b32 s9, s0, s8
; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s3 ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s9
; GFX8-NEXT: s_sub_i32 s6, 0, s3 ; GFX8-NEXT: s_sub_i32 s6, 0, s9
; GFX8-NEXT: s_sext_i32_i16 s1, s8 ; GFX8-NEXT: s_sext_i32_i16 s0, s2
; GFX8-NEXT: s_bfe_i32 s0, s0, s9 ; GFX8-NEXT: s_bfe_i32 s1, s3, s10
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_ashr_i32 s10, s1, 31 ; GFX8-NEXT: s_ashr_i32 s3, s0, 31
; GFX8-NEXT: s_ashr_i32 s11, s0, 31 ; GFX8-NEXT: s_ashr_i32 s11, s1, 31
; GFX8-NEXT: s_add_i32 s1, s1, s10 ; GFX8-NEXT: s_add_i32 s0, s0, s3
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: s_add_i32 s0, s0, s11 ; GFX8-NEXT: s_add_i32 s1, s1, s11
; GFX8-NEXT: s_xor_b32 s1, s1, s10 ; GFX8-NEXT: s_xor_b32 s0, s0, s3
; GFX8-NEXT: s_xor_b32 s12, s0, s11 ; GFX8-NEXT: s_xor_b32 s12, s1, s11
; GFX8-NEXT: v_mul_lo_u32 v1, s6, v0 ; GFX8-NEXT: v_mul_lo_u32 v1, s6, v0
; GFX8-NEXT: v_cvt_f32_u32_e32 v2, s12 ; GFX8-NEXT: v_cvt_f32_u32_e32 v2, s12
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0 ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
; GFX8-NEXT: v_mul_hi_u32 v0, s1, v0 ; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0
; GFX8-NEXT: v_rcp_iflag_f32_e32 v1, v2 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v1, v2
; GFX8-NEXT: v_mul_lo_u32 v2, v0, s3 ; GFX8-NEXT: v_mul_lo_u32 v2, v0, s9
; GFX8-NEXT: v_add_u32_e32 v3, vcc, 1, v0 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, 1, v0
; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 ; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s1, v2 ; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s0, v2
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s3, v2 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s9, v2
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX8-NEXT: v_subrev_u32_e64 v3, s[0:1], s3, v2 ; GFX8-NEXT: v_subrev_u32_e64 v3, s[0:1], s9, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX8-NEXT: v_add_u32_e32 v3, vcc, 1, v0 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, 1, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s3, v2 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s9, v2
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX8-NEXT: v_subrev_u32_e64 v3, s[0:1], s3, v2 ; GFX8-NEXT: v_subrev_u32_e64 v3, s[0:1], s9, v2
; GFX8-NEXT: s_sub_i32 s1, 0, s12 ; GFX8-NEXT: s_sub_i32 s1, 0, s12
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX8-NEXT: v_mul_lo_u32 v3, s1, v1 ; GFX8-NEXT: v_mul_lo_u32 v3, s1, v1
; GFX8-NEXT: s_bfe_i32 s1, s8, s9 ; GFX8-NEXT: s_bfe_i32 s1, s2, s10
; GFX8-NEXT: s_xor_b32 s0, s10, s2
; GFX8-NEXT: s_ashr_i32 s2, s1, 31 ; GFX8-NEXT: s_ashr_i32 s2, s1, 31
; GFX8-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX8-NEXT: s_add_i32 s1, s1, s2 ; GFX8-NEXT: s_add_i32 s1, s1, s2
; GFX8-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX8-NEXT: s_xor_b32 s1, s1, s2 ; GFX8-NEXT: s_xor_b32 s1, s1, s2
; GFX8-NEXT: s_xor_b32 s0, s3, s8
; GFX8-NEXT: v_xor_b32_e32 v0, s0, v0 ; GFX8-NEXT: v_xor_b32_e32 v0, s0, v0
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v3 ; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v3
; GFX8-NEXT: v_mul_hi_u32 v1, s1, v1 ; GFX8-NEXT: v_mul_hi_u32 v1, s1, v1
; GFX8-NEXT: v_xor_b32_e32 v2, s10, v2 ; GFX8-NEXT: v_xor_b32_e32 v2, s3, v2
; GFX8-NEXT: v_subrev_u32_e32 v0, vcc, s0, v0 ; GFX8-NEXT: v_subrev_u32_e32 v0, vcc, s0, v0
; GFX8-NEXT: v_mul_lo_u32 v3, v1, s12 ; GFX8-NEXT: v_mul_lo_u32 v3, v1, s12
; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s10, v2 ; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s3, v2
; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v1 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v1
; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s1, v3 ; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s1, v3
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s12, v3 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s12, v3
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s12, v3 ; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s12, v3
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v1 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v1
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s12, v3 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s12, v3
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; GFX8-NEXT: flat_store_dword v[0:1], v4 ; GFX8-NEXT: flat_store_dword v[0:1], v4
; GFX8-NEXT: v_mov_b32_e32 v0, s6 ; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: v_mov_b32_e32 v1, s7 ; GFX8-NEXT: v_mov_b32_e32 v1, s7
; GFX8-NEXT: flat_store_dword v[0:1], v2 ; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-LABEL: sdivrem_v2i16: ; GFX9-LABEL: sdivrem_v2i16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dword s6, s[4:5], 0x14 ; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x10
; GFX9-NEXT: s_mov_b32 s10, 0x100010
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_sext_i32_i16 s0, s6 ; GFX9-NEXT: s_sext_i32_i16 s0, s7
; GFX9-NEXT: s_ashr_i32 s7, s0, 31 ; GFX9-NEXT: s_ashr_i32 s8, s0, 31
; GFX9-NEXT: s_add_i32 s0, s0, s7 ; GFX9-NEXT: s_add_i32 s0, s0, s8
; GFX9-NEXT: s_xor_b32 s8, s0, s7 ; GFX9-NEXT: s_xor_b32 s9, s0, s8
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s8 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s9
; GFX9-NEXT: s_load_dword s9, s[4:5], 0x10 ; GFX9-NEXT: s_bfe_i32 s1, s7, s10
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; GFX9-NEXT: s_ashr_i32 s7, s1, 31
; GFX9-NEXT: s_mov_b32 s4, 0x100010 ; GFX9-NEXT: s_add_i32 s1, s1, s7
; GFX9-NEXT: s_bfe_i32 s6, s6, s4
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: s_ashr_i32 s10, s6, 31 ; GFX9-NEXT: s_xor_b32 s11, s1, s7
; GFX9-NEXT: s_add_i32 s6, s6, s10 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s11
; GFX9-NEXT: s_sub_i32 s11, 0, s8 ; GFX9-NEXT: s_sub_i32 s1, 0, s9
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: s_xor_b32 s6, s6, s10 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s6 ; GFX9-NEXT: s_sext_i32_i16 s0, s6
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_ashr_i32 s12, s0, 31
; GFX9-NEXT: s_sext_i32_i16 s5, s9 ; GFX9-NEXT: v_mul_lo_u32 v2, s1, v0
; GFX9-NEXT: v_mul_lo_u32 v1, s11, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX9-NEXT: s_ashr_i32 s11, s5, 31
; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX9-NEXT: s_add_i32 s5, s5, s11
; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX9-NEXT: s_xor_b32 s5, s5, s11
; GFX9-NEXT: s_bfe_i32 s4, s9, s4
; GFX9-NEXT: s_sub_i32 s9, 0, s6
; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_mul_hi_u32 v0, s5, v0 ; GFX9-NEXT: s_add_i32 s0, s0, s12
; GFX9-NEXT: s_xor_b32 s7, s11, s7 ; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX9-NEXT: v_mul_lo_u32 v3, s9, v1 ; GFX9-NEXT: s_xor_b32 s13, s0, s12
; GFX9-NEXT: v_mul_lo_u32 v2, v0, s8 ; GFX9-NEXT: s_sub_i32 s0, 0, s11
; GFX9-NEXT: v_add_u32_e32 v4, 1, v0 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX9-NEXT: v_mul_hi_u32 v0, s13, v0
; GFX9-NEXT: v_sub_u32_e32 v2, s5, v2 ; GFX9-NEXT: v_mul_lo_u32 v2, s0, v1
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX9-NEXT: s_bfe_i32 s4, s6, s10
; GFX9-NEXT: v_mul_lo_u32 v3, v0, s9
; GFX9-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX9-NEXT: s_ashr_i32 s5, s4, 31 ; GFX9-NEXT: s_ashr_i32 s5, s4, 31
; GFX9-NEXT: s_add_i32 s4, s4, s5 ; GFX9-NEXT: s_add_i32 s4, s4, s5
; GFX9-NEXT: v_sub_u32_e32 v3, s13, v3
; GFX9-NEXT: v_add_u32_e32 v4, 1, v0
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v3
; GFX9-NEXT: s_xor_b32 s4, s4, s5 ; GFX9-NEXT: s_xor_b32 s4, s4, s5
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v2
; GFX9-NEXT: v_mul_hi_u32 v1, s4, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v2
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX9-NEXT: v_subrev_u32_e32 v4, s8, v2 ; GFX9-NEXT: v_subrev_u32_e32 v4, s9, v3
; GFX9-NEXT: v_mul_lo_u32 v3, v1, s6 ; GFX9-NEXT: v_mul_hi_u32 v1, s4, v1
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX9-NEXT: v_add_u32_e32 v4, 1, v0 ; GFX9-NEXT: v_add_u32_e32 v4, 1, v0
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v2 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v3
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX9-NEXT: v_subrev_u32_e32 v4, s8, v2 ; GFX9-NEXT: v_subrev_u32_e32 v4, s9, v3
; GFX9-NEXT: v_sub_u32_e32 v3, s4, v3 ; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX9-NEXT: v_mul_lo_u32 v3, v1, s11
; GFX9-NEXT: v_add_u32_e32 v4, 1, v1 ; GFX9-NEXT: v_add_u32_e32 v4, 1, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v3 ; GFX9-NEXT: s_xor_b32 s6, s12, s8
; GFX9-NEXT: v_xor_b32_e32 v0, s6, v0
; GFX9-NEXT: v_sub_u32_e32 v3, s4, v3
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v3
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX9-NEXT: v_subrev_u32_e32 v4, s6, v3 ; GFX9-NEXT: v_subrev_u32_e32 v4, s11, v3
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX9-NEXT: v_add_u32_e32 v4, 1, v1 ; GFX9-NEXT: v_add_u32_e32 v4, 1, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v3
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX9-NEXT: v_subrev_u32_e32 v4, s6, v3 ; GFX9-NEXT: v_subrev_u32_e32 v4, s11, v3
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX9-NEXT: s_xor_b32 s4, s5, s10 ; GFX9-NEXT: s_xor_b32 s4, s5, s7
; GFX9-NEXT: v_xor_b32_e32 v0, s7, v0 ; GFX9-NEXT: v_xor_b32_e32 v2, s12, v2
; GFX9-NEXT: v_xor_b32_e32 v2, s11, v2
; GFX9-NEXT: v_xor_b32_e32 v1, s4, v1 ; GFX9-NEXT: v_xor_b32_e32 v1, s4, v1
; GFX9-NEXT: v_xor_b32_e32 v3, s5, v3 ; GFX9-NEXT: v_xor_b32_e32 v3, s5, v3
; GFX9-NEXT: v_subrev_u32_e32 v0, s7, v0 ; GFX9-NEXT: v_subrev_u32_e32 v0, s6, v0
; GFX9-NEXT: v_subrev_u32_e32 v2, s11, v2 ; GFX9-NEXT: v_subrev_u32_e32 v2, s12, v2
; GFX9-NEXT: v_sub_u32_sdwa v1, v1, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-NEXT: v_sub_u32_sdwa v1, v1, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_sub_u32_sdwa v3, v3, s5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-NEXT: v_sub_u32_sdwa v3, v3, s5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_mov_b32_e32 v4, 0xffff ; GFX9-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX9-NEXT: v_and_or_b32 v0, v0, v4, v1 ; GFX9-NEXT: v_and_or_b32 v0, v0, v4, v1
; GFX9-NEXT: v_and_or_b32 v1, v2, v4, v3 ; GFX9-NEXT: v_and_or_b32 v1, v2, v4, v3
; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dword v2, v0, s[0:1] ; GFX9-NEXT: global_store_dword v2, v0, s[0:1]
; GFX9-NEXT: global_store_dword v2, v1, s[2:3] ; GFX9-NEXT: global_store_dword v2, v1, s[2:3]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: sdivrem_v2i16: ; GFX10-LABEL: sdivrem_v2i16:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dword s0, s[4:5], 0x14 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x10
; GFX10-NEXT: s_mov_b32 s1, 0x100010 ; GFX10-NEXT: s_mov_b32 s2, 0x100010
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_sext_i32_i16 s2, s0 ; GFX10-NEXT: s_sext_i32_i16 s3, s1
; GFX10-NEXT: s_bfe_i32 s0, s0, s1 ; GFX10-NEXT: s_bfe_i32 s1, s1, s2
; GFX10-NEXT: s_ashr_i32 s3, s2, 31 ; GFX10-NEXT: s_ashr_i32 s8, s3, 31
; GFX10-NEXT: s_ashr_i32 s8, s0, 31 ; GFX10-NEXT: s_ashr_i32 s9, s1, 31
; GFX10-NEXT: s_add_i32 s2, s2, s3 ; GFX10-NEXT: s_add_i32 s3, s3, s8
; GFX10-NEXT: s_add_i32 s0, s0, s8 ; GFX10-NEXT: s_add_i32 s1, s1, s9
; GFX10-NEXT: s_xor_b32 s2, s2, s3 ; GFX10-NEXT: s_xor_b32 s3, s3, s8
; GFX10-NEXT: s_xor_b32 s9, s0, s8 ; GFX10-NEXT: s_xor_b32 s1, s1, s9
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s2 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s3
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s9 ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s1
; GFX10-NEXT: s_load_dword s0, s[4:5], 0x10 ; GFX10-NEXT: s_sub_i32 s6, 0, s3
; GFX10-NEXT: s_sub_i32 s6, 0, s2 ; GFX10-NEXT: s_sub_i32 s7, 0, s1
; GFX10-NEXT: s_sub_i32 s7, 0, s9
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 ; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX10-NEXT: v_mul_lo_u32 v2, s6, v0 ; GFX10-NEXT: v_mul_lo_u32 v2, s6, v0
; GFX10-NEXT: v_mul_lo_u32 v3, s7, v1 ; GFX10-NEXT: v_mul_lo_u32 v3, s7, v1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_sext_i32_i16 s6, s0 ; GFX10-NEXT: s_sext_i32_i16 s6, s0
; GFX10-NEXT: s_bfe_i32 s0, s0, s1 ; GFX10-NEXT: s_bfe_i32 s0, s0, s2
; GFX10-NEXT: s_ashr_i32 s1, s6, 31 ; GFX10-NEXT: s_ashr_i32 s2, s6, 31
; GFX10-NEXT: s_ashr_i32 s10, s0, 31 ; GFX10-NEXT: s_ashr_i32 s10, s0, 31
; GFX10-NEXT: s_add_i32 s6, s6, s1 ; GFX10-NEXT: s_add_i32 s6, s6, s2
; GFX10-NEXT: s_add_i32 s0, s0, s10 ; GFX10-NEXT: s_add_i32 s0, s0, s10
; GFX10-NEXT: v_mul_hi_u32 v2, v0, v2 ; GFX10-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX10-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX10-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX10-NEXT: s_xor_b32 s6, s6, s1 ; GFX10-NEXT: s_xor_b32 s6, s6, s2
; GFX10-NEXT: s_xor_b32 s0, s0, s10 ; GFX10-NEXT: s_xor_b32 s0, s0, s10
; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2 ; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2
; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v3 ; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v3
; GFX10-NEXT: v_mul_hi_u32 v0, s6, v0 ; GFX10-NEXT: v_mul_hi_u32 v0, s6, v0
; GFX10-NEXT: v_mul_hi_u32 v1, s0, v1 ; GFX10-NEXT: v_mul_hi_u32 v1, s0, v1
; GFX10-NEXT: v_mul_lo_u32 v2, v0, s2 ; GFX10-NEXT: v_mul_lo_u32 v2, v0, s3
; GFX10-NEXT: v_mul_lo_u32 v3, v1, s9 ; GFX10-NEXT: v_mul_lo_u32 v3, v1, s1
; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v0
; GFX10-NEXT: v_add_nc_u32_e32 v5, 1, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v5, 1, v1
; GFX10-NEXT: v_sub_nc_u32_e32 v2, s6, v2 ; GFX10-NEXT: v_sub_nc_u32_e32 v2, s6, v2
; GFX10-NEXT: v_sub_nc_u32_e32 v3, s0, v3 ; GFX10-NEXT: v_sub_nc_u32_e32 v3, s0, v3
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX10-NEXT: v_subrev_nc_u32_e32 v6, s2, v2 ; GFX10-NEXT: v_subrev_nc_u32_e32 v6, s3, v2
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s9, v3 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s1, v3
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s2, v2 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s3, v2
; GFX10-NEXT: v_subrev_nc_u32_e32 v7, s9, v3 ; GFX10-NEXT: v_subrev_nc_u32_e32 v7, s1, v3
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v6, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v6, s0
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
; GFX10-NEXT: v_add_nc_u32_e32 v5, 1, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v5, 1, v1
; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s2, v2 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s3, v2
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s9, v3 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s1, v3
; GFX10-NEXT: v_subrev_nc_u32_e32 v6, s2, v2 ; GFX10-NEXT: v_subrev_nc_u32_e32 v6, s3, v2
; GFX10-NEXT: v_subrev_nc_u32_e32 v7, s9, v3 ; GFX10-NEXT: v_subrev_nc_u32_e32 v7, s1, v3
; GFX10-NEXT: s_xor_b32 s2, s1, s3 ; GFX10-NEXT: s_xor_b32 s1, s2, s8
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v6, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v6, s0
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
; GFX10-NEXT: s_xor_b32 s0, s10, s8 ; GFX10-NEXT: s_xor_b32 s0, s10, s9
; GFX10-NEXT: v_xor_b32_e32 v0, s2, v0 ; GFX10-NEXT: v_xor_b32_e32 v0, s1, v0
; GFX10-NEXT: v_xor_b32_e32 v1, s0, v1 ; GFX10-NEXT: v_xor_b32_e32 v1, s0, v1
; GFX10-NEXT: v_xor_b32_e32 v2, s1, v2 ; GFX10-NEXT: v_xor_b32_e32 v2, s2, v2
; GFX10-NEXT: v_xor_b32_e32 v3, s10, v3 ; GFX10-NEXT: v_xor_b32_e32 v3, s10, v3
; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff ; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX10-NEXT: v_subrev_nc_u32_e32 v0, s2, v0 ; GFX10-NEXT: v_subrev_nc_u32_e32 v0, s1, v0
; GFX10-NEXT: v_sub_nc_u32_sdwa v1, v1, s0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_sub_nc_u32_sdwa v1, v1, s0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_subrev_nc_u32_e32 v2, s1, v2 ; GFX10-NEXT: v_subrev_nc_u32_e32 v2, s2, v2
; GFX10-NEXT: v_sub_nc_u32_sdwa v3, v3, s10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-NEXT: v_sub_nc_u32_sdwa v3, v3, s10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_and_or_b32 v0, v0, v4, v1 ; GFX10-NEXT: v_and_or_b32 v0, v0, v4, v1
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: v_and_or_b32 v2, v2, v4, v3 ; GFX10-NEXT: v_and_or_b32 v2, v2, v4, v3
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_store_dword v1, v0, s[4:5] ; GFX10-NEXT: global_store_dword v1, v0, s[4:5]
; GFX10-NEXT: global_store_dword v1, v2, s[6:7] ; GFX10-NEXT: global_store_dword v1, v2, s[6:7]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
▲ Show 20 Lines • Show All 310 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll

Show First 20 Lines • Show All 549 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_endpgm
%rem = urem i64 %x, %y %rem = urem i64 %x, %y
store i64 %rem, i64 addrspace(1)* %out1 store i64 %rem, i64 addrspace(1)* %out1
ret void ret void
} }
define amdgpu_kernel void @udivrem_v2i32(<2 x i32> addrspace(1)* %out0, <2 x i32> addrspace(1)* %out1, <2 x i32> %x, <2 x i32> %y) { define amdgpu_kernel void @udivrem_v2i32(<2 x i32> addrspace(1)* %out0, <2 x i32> addrspace(1)* %out1, <2 x i32> %x, <2 x i32> %y) {
; GFX8-LABEL: udivrem_v2i32: ; GFX8-LABEL: udivrem_v2i32:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x18 ; GFX8-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x10
; GFX8-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x10
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0 ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s2 ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s10
; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s3 ; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s11
; GFX8-NEXT: s_sub_i32 s0, 0, s2 ; GFX8-NEXT: s_sub_i32 s0, 0, s10
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 ; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX8-NEXT: v_mul_lo_u32 v2, s0, v0 ; GFX8-NEXT: v_mul_lo_u32 v2, s0, v0
; GFX8-NEXT: s_sub_i32 s0, 0, s3 ; GFX8-NEXT: s_sub_i32 s0, 0, s11
; GFX8-NEXT: v_mul_lo_u32 v3, s0, v1 ; GFX8-NEXT: v_mul_lo_u32 v3, s0, v1
; GFX8-NEXT: v_mul_hi_u32 v2, v0, v2 ; GFX8-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX8-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX8-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_mul_hi_u32 v0, s8, v0 ; GFX8-NEXT: v_mul_hi_u32 v0, s8, v0
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v3 ; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v3
; GFX8-NEXT: v_mul_hi_u32 v1, s9, v1 ; GFX8-NEXT: v_mul_hi_u32 v1, s9, v1
; GFX8-NEXT: v_mul_lo_u32 v2, v0, s2 ; GFX8-NEXT: v_mul_lo_u32 v2, v0, s10
; GFX8-NEXT: v_add_u32_e32 v3, vcc, 1, v0 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, 1, v0
; GFX8-NEXT: v_mul_lo_u32 v4, v1, s3 ; GFX8-NEXT: v_mul_lo_u32 v4, v1, s11
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s8, v2 ; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s8, v2
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s2, v2 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s10, v2
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX8-NEXT: v_subrev_u32_e64 v3, s[0:1], s2, v2 ; GFX8-NEXT: v_subrev_u32_e64 v3, s[0:1], s10, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX8-NEXT: v_add_u32_e32 v3, vcc, 1, v0 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, 1, v0
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s2, v2 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s10, v2
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX8-NEXT: v_subrev_u32_e64 v3, s[0:1], s2, v2 ; GFX8-NEXT: v_subrev_u32_e64 v3, s[0:1], s10, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s9, v4 ; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s9, v4
; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v1 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v1
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s3, v3 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s11, v3
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s3, v3 ; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s11, v3
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v1 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v1
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s3, v3 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s11, v3
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s3, v3 ; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s11, v3
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX8-NEXT: v_mov_b32_e32 v4, s4 ; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_mov_b32_e32 v5, s5 ; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: flat_store_dwordx2 v[4:5], v[0:1] ; GFX8-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
; GFX8-NEXT: v_mov_b32_e32 v0, s6 ; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: v_mov_b32_e32 v1, s7 ; GFX8-NEXT: v_mov_b32_e32 v1, s7
; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3] ; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-LABEL: udivrem_v2i32: ; GFX9-LABEL: udivrem_v2i32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x18 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x10
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s2 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s3 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s3
; GFX9-NEXT: s_sub_i32 s0, 0, s2 ; GFX9-NEXT: s_sub_i32 s6, 0, s2
; GFX9-NEXT: s_sub_i32 s1, 0, s3 ; GFX9-NEXT: s_sub_i32 s7, 0, s3
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_mul_lo_u32 v2, s0, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, s6, v0
; GFX9-NEXT: v_mul_lo_u32 v3, s1, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, s7, v1
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x10
; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX9-NEXT: v_add_u32_e32 v0, v0, v2 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mul_hi_u32 v0, s0, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s0, v0
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_mul_hi_u32 v1, s1, v1 ; GFX9-NEXT: v_mul_hi_u32 v1, s1, v1
; GFX9-NEXT: v_mul_lo_u32 v2, v0, s2 ; GFX9-NEXT: v_mul_lo_u32 v2, v0, s2
; GFX9-NEXT: v_add_u32_e32 v4, 1, v0 ; GFX9-NEXT: v_add_u32_e32 v4, 1, v0
; GFX9-NEXT: v_mul_lo_u32 v3, v1, s3 ; GFX9-NEXT: v_mul_lo_u32 v3, v1, s3
; GFX9-NEXT: v_add_u32_e32 v5, 1, v1 ; GFX9-NEXT: v_add_u32_e32 v5, 1, v1
; GFX9-NEXT: v_sub_u32_e32 v2, s0, v2 ; GFX9-NEXT: v_sub_u32_e32 v2, s0, v2
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v2 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v2
; GFX9-NEXT: v_sub_u32_e32 v3, s1, v3 ; GFX9-NEXT: v_sub_u32_e32 v3, s1, v3
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX9-NEXT: v_subrev_u32_e32 v4, s2, v2 ; GFX9-NEXT: v_subrev_u32_e32 v4, s2, v2
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v3 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v3
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[0:1]
; GFX9-NEXT: v_subrev_u32_e32 v5, s3, v3 ; GFX9-NEXT: v_subrev_u32_e32 v5, s3, v3
; GFX9-NEXT: v_add_u32_e32 v4, 1, v0 ; GFX9-NEXT: v_add_u32_e32 v4, 1, v0
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v2 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v2
; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX9-NEXT: v_subrev_u32_e32 v4, s2, v2 ; GFX9-NEXT: v_subrev_u32_e32 v4, s2, v2
; GFX9-NEXT: v_add_u32_e32 v5, 1, v1
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX9-NEXT: v_add_u32_e32 v4, 1, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v3
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX9-NEXT: v_subrev_u32_e32 v4, s3, v3 ; GFX9-NEXT: v_subrev_u32_e32 v4, s3, v3
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[4:5] ; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[4:5]
; GFX9-NEXT: global_store_dwordx2 v4, v[2:3], s[6:7] ; GFX9-NEXT: global_store_dwordx2 v4, v[2:3], s[6:7]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: udivrem_v2i32: ; GFX10-LABEL: udivrem_v2i32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x18 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x10
; GFX10-NEXT: v_mov_b32_e32 v8, 0 ; GFX10-NEXT: v_mov_b32_e32 v8, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s2 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s3 ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s3
; GFX10-NEXT: s_sub_i32 s0, 0, s2 ; GFX10-NEXT: s_sub_i32 s6, 0, s2
; GFX10-NEXT: s_sub_i32 s1, 0, s3 ; GFX10-NEXT: s_sub_i32 s7, 0, s3
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 ; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX10-NEXT: v_mul_lo_u32 v2, s0, v0 ; GFX10-NEXT: v_mul_lo_u32 v2, s6, v0
; GFX10-NEXT: v_mul_lo_u32 v3, s1, v1 ; GFX10-NEXT: v_mul_lo_u32 v3, s7, v1
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x10 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX10-NEXT: v_mul_hi_u32 v2, v0, v2 ; GFX10-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX10-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX10-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2 ; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2
; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v3 ; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v3
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mul_hi_u32 v0, s0, v0 ; GFX10-NEXT: v_mul_hi_u32 v0, s0, v0
; GFX10-NEXT: v_mul_hi_u32 v1, s1, v1 ; GFX10-NEXT: v_mul_hi_u32 v1, s1, v1
; GFX10-NEXT: v_mul_lo_u32 v2, v0, s2 ; GFX10-NEXT: v_mul_lo_u32 v2, v0, s2
; GFX10-NEXT: v_mul_lo_u32 v3, v1, s3 ; GFX10-NEXT: v_mul_lo_u32 v3, v1, s3
; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v0
; GFX10-NEXT: v_add_nc_u32_e32 v5, 1, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v5, 1, v1
; GFX10-NEXT: v_sub_nc_u32_e32 v2, s0, v2 ; GFX10-NEXT: v_sub_nc_u32_e32 v2, s0, v2
; GFX10-NEXT: v_sub_nc_u32_e32 v3, s1, v3 ; GFX10-NEXT: v_sub_nc_u32_e32 v3, s1, v3
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; GFX10-NEXT: v_cmp_le_u32_e64 s0, s2, v2 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s2, v2
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s3, v3 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s3, v3
; GFX10-NEXT: v_subrev_nc_u32_e32 v6, s2, v2 ; GFX10-NEXT: v_subrev_nc_u32_e32 v6, s2, v2
; GFX10-NEXT: v_subrev_nc_u32_e32 v7, s3, v3 ; GFX10-NEXT: v_subrev_nc_u32_e32 v7, s3, v3
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v6, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v6, s0
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_store_dwordx2 v8, v[0:1], s[4:5] ; GFX10-NEXT: global_store_dwordx2 v8, v[0:1], s[4:5]
; GFX10-NEXT: global_store_dwordx2 v8, v[2:3], s[6:7] ; GFX10-NEXT: global_store_dwordx2 v8, v[2:3], s[6:7]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%div = udiv <2 x i32> %x, %y %div = udiv <2 x i32> %x, %y
store <2 x i32> %div, <2 x i32> addrspace(1)* %out0 store <2 x i32> %div, <2 x i32> addrspace(1)* %out0
%rem = urem <2 x i32> %x, %y %rem = urem <2 x i32> %x, %y
store <2 x i32> %rem, <2 x i32> addrspace(1)* %out1 store <2 x i32> %rem, <2 x i32> addrspace(1)* %out1
ret void ret void
} }
define amdgpu_kernel void @udivrem_v4i32(<4 x i32> addrspace(1)* %out0, <4 x i32> addrspace(1)* %out1, <4 x i32> %x, <4 x i32> %y) { define amdgpu_kernel void @udivrem_v4i32(<4 x i32> addrspace(1)* %out0, <4 x i32> addrspace(1)* %out1, <4 x i32> %x, <4 x i32> %y) {
; GFX8-LABEL: udivrem_v4i32: ; GFX8-LABEL: udivrem_v4i32:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x20 ; GFX8-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x10
; GFX8-NEXT: s_load_dwordx4 s[12:15], s[4:5], 0x10
; GFX8-NEXT: v_mov_b32_e32 v2, 0x4f7ffffe ; GFX8-NEXT: v_mov_b32_e32 v2, 0x4f7ffffe
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0 ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s8 ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s12
; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s9 ; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s13
; GFX8-NEXT: s_sub_i32 s0, 0, s8 ; GFX8-NEXT: s_sub_i32 s0, 0, s12
; GFX8-NEXT: v_cvt_f32_u32_e32 v6, s10 ; GFX8-NEXT: v_cvt_f32_u32_e32 v6, s14
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: v_mul_f32_e32 v1, v1, v2 ; GFX8-NEXT: v_mul_f32_e32 v1, v1, v2
; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX8-NEXT: v_mul_lo_u32 v3, s0, v0 ; GFX8-NEXT: v_mul_lo_u32 v3, s0, v0
; GFX8-NEXT: s_sub_i32 s0, 0, s9 ; GFX8-NEXT: s_sub_i32 s0, 0, s13
; GFX8-NEXT: v_mul_lo_u32 v4, s0, v1 ; GFX8-NEXT: v_mul_lo_u32 v4, s0, v1
; GFX8-NEXT: v_mul_hi_u32 v3, v0, v3 ; GFX8-NEXT: v_mul_hi_u32 v3, v0, v3
; GFX8-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX8-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v3 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v3
; GFX8-NEXT: v_mul_hi_u32 v0, s12, v0 ; GFX8-NEXT: v_mul_hi_u32 v0, s8, v0
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v4 ; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v4
; GFX8-NEXT: v_mul_hi_u32 v1, s13, v1 ; GFX8-NEXT: v_mul_hi_u32 v1, s9, v1
; GFX8-NEXT: v_mul_lo_u32 v3, v0, s8 ; GFX8-NEXT: v_mul_lo_u32 v3, v0, s12
; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v0 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v0
; GFX8-NEXT: v_mul_lo_u32 v5, v1, s9 ; GFX8-NEXT: v_mul_lo_u32 v5, v1, s13
; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s12, v3 ; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s8, v3
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s8, v3 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s12, v3
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s8, v3 ; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s12, v3
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v0 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v0
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s8, v3 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s12, v3
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s8, v3 ; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s12, v3
; GFX8-NEXT: v_cndmask_b32_e32 v4, v3, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v4, v3, v4, vcc
; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s13, v5 ; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s9, v5
; GFX8-NEXT: v_rcp_iflag_f32_e32 v5, v6 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v5, v6
; GFX8-NEXT: v_add_u32_e32 v6, vcc, 1, v1 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, 1, v1
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s9, v3 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s13, v3
; GFX8-NEXT: v_mul_f32_e32 v5, v5, v2 ; GFX8-NEXT: v_mul_f32_e32 v5, v5, v2
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
; GFX8-NEXT: v_cvt_u32_f32_e32 v5, v5 ; GFX8-NEXT: v_cvt_u32_f32_e32 v5, v5
; GFX8-NEXT: v_subrev_u32_e64 v6, s[0:1], s9, v3 ; GFX8-NEXT: v_subrev_u32_e64 v6, s[0:1], s13, v3
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
; GFX8-NEXT: v_add_u32_e32 v6, vcc, 1, v1 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, 1, v1
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s9, v3 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s13, v3
; GFX8-NEXT: s_sub_i32 s0, 0, s10 ; GFX8-NEXT: s_sub_i32 s0, 0, s14
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
; GFX8-NEXT: v_cvt_f32_u32_e32 v6, s11 ; GFX8-NEXT: v_cvt_f32_u32_e32 v6, s15
; GFX8-NEXT: v_mul_lo_u32 v7, s0, v5 ; GFX8-NEXT: v_mul_lo_u32 v7, s0, v5
; GFX8-NEXT: v_rcp_iflag_f32_e32 v6, v6 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v6, v6
; GFX8-NEXT: v_mul_hi_u32 v7, v5, v7 ; GFX8-NEXT: v_mul_hi_u32 v7, v5, v7
; GFX8-NEXT: v_mul_f32_e32 v2, v6, v2 ; GFX8-NEXT: v_mul_f32_e32 v2, v6, v2
; GFX8-NEXT: v_add_u32_e64 v5, s[0:1], v5, v7 ; GFX8-NEXT: v_add_u32_e64 v5, s[0:1], v5, v7
; GFX8-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GFX8-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX8-NEXT: v_mul_hi_u32 v7, s14, v5 ; GFX8-NEXT: v_mul_hi_u32 v7, s10, v5
; GFX8-NEXT: v_subrev_u32_e64 v5, s[0:1], s9, v3 ; GFX8-NEXT: v_subrev_u32_e64 v5, s[0:1], s13, v3
; GFX8-NEXT: s_sub_i32 s0, 0, s11 ; GFX8-NEXT: s_sub_i32 s0, 0, s15
; GFX8-NEXT: v_mul_lo_u32 v6, s0, v2 ; GFX8-NEXT: v_mul_lo_u32 v6, s0, v2
; GFX8-NEXT: v_cndmask_b32_e32 v5, v3, v5, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v5, v3, v5, vcc
; GFX8-NEXT: v_mul_lo_u32 v3, v7, s10 ; GFX8-NEXT: v_mul_lo_u32 v3, v7, s14
; GFX8-NEXT: v_add_u32_e32 v8, vcc, 1, v7 ; GFX8-NEXT: v_add_u32_e32 v8, vcc, 1, v7
; GFX8-NEXT: v_mul_hi_u32 v6, v2, v6 ; GFX8-NEXT: v_mul_hi_u32 v6, v2, v6
; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s14, v3 ; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s10, v3
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s10, v3 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s14, v3
; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
; GFX8-NEXT: v_subrev_u32_e64 v8, s[0:1], s10, v3 ; GFX8-NEXT: v_subrev_u32_e64 v8, s[0:1], s14, v3
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v6 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v6
; GFX8-NEXT: v_mul_hi_u32 v8, s15, v2 ; GFX8-NEXT: v_mul_hi_u32 v8, s11, v2
; GFX8-NEXT: v_add_u32_e32 v2, vcc, 1, v7 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, 1, v7
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s10, v3 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s14, v3
; GFX8-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc
; GFX8-NEXT: v_mul_lo_u32 v7, v8, s11 ; GFX8-NEXT: v_mul_lo_u32 v7, v8, s15
; GFX8-NEXT: v_subrev_u32_e64 v6, s[0:1], s10, v3 ; GFX8-NEXT: v_subrev_u32_e64 v6, s[0:1], s14, v3
; GFX8-NEXT: v_cndmask_b32_e32 v6, v3, v6, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v6, v3, v6, vcc
; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s15, v7 ; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s11, v7
; GFX8-NEXT: v_add_u32_e32 v7, vcc, 1, v8 ; GFX8-NEXT: v_add_u32_e32 v7, vcc, 1, v8
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s11, v3 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s15, v3
; GFX8-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc
; GFX8-NEXT: v_subrev_u32_e64 v8, s[0:1], s11, v3 ; GFX8-NEXT: v_subrev_u32_e64 v8, s[0:1], s15, v3
; GFX8-NEXT: v_cndmask_b32_e32 v8, v3, v8, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v8, v3, v8, vcc
; GFX8-NEXT: v_add_u32_e32 v3, vcc, 1, v7 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, 1, v7
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s11, v8 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s15, v8
; GFX8-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX8-NEXT: v_subrev_u32_e64 v7, s[0:1], s11, v8 ; GFX8-NEXT: v_subrev_u32_e64 v7, s[0:1], s15, v8
; GFX8-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc
; GFX8-NEXT: v_mov_b32_e32 v9, s5 ; GFX8-NEXT: v_mov_b32_e32 v9, s5
; GFX8-NEXT: v_mov_b32_e32 v8, s4 ; GFX8-NEXT: v_mov_b32_e32 v8, s4
; GFX8-NEXT: flat_store_dwordx4 v[8:9], v[0:3] ; GFX8-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
; GFX8-NEXT: s_nop 0 ; GFX8-NEXT: s_nop 0
; GFX8-NEXT: v_mov_b32_e32 v0, s6 ; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: v_mov_b32_e32 v1, s7 ; GFX8-NEXT: v_mov_b32_e32 v1, s7
; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[4:7] ; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-LABEL: udivrem_v4i32: ; GFX9-LABEL: udivrem_v4i32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x20 ; GFX9-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x10
; GFX9-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x10
; GFX9-NEXT: v_mov_b32_e32 v2, 0x4f7ffffe ; GFX9-NEXT: v_mov_b32_e32 v2, 0x4f7ffffe
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s0 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s12
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s1 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s13
; GFX9-NEXT: s_sub_i32 s6, 0, s0 ; GFX9-NEXT: s_sub_i32 s0, 0, s12
; GFX9-NEXT: s_sub_i32 s7, 0, s1 ; GFX9-NEXT: s_sub_i32 s1, 0, s13
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s2 ; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s14
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v1, v1, v2 ; GFX9-NEXT: v_mul_f32_e32 v1, v1, v2
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v5 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v5
; GFX9-NEXT: v_mul_lo_u32 v3, s6, v0 ; GFX9-NEXT: v_mul_lo_u32 v3, s0, v0
; GFX9-NEXT: v_mul_lo_u32 v4, s7, v1 ; GFX9-NEXT: v_mul_lo_u32 v4, s1, v1
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX9-NEXT: v_mul_hi_u32 v3, v0, v3 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, v3
; GFX9-NEXT: s_sub_i32 s4, 0, s14
; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX9-NEXT: v_add_u32_e32 v0, v0, v3 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v3
; GFX9-NEXT: v_mul_hi_u32 v0, s8, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s8, v0
; GFX9-NEXT: v_add_u32_e32 v1, v1, v4 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v4
; GFX9-NEXT: v_mul_hi_u32 v1, s9, v1 ; GFX9-NEXT: v_mul_hi_u32 v1, s9, v1
; GFX9-NEXT: v_mul_f32_e32 v3, v5, v2 ; GFX9-NEXT: v_mul_f32_e32 v3, v5, v2
; GFX9-NEXT: v_mul_lo_u32 v4, v0, s0 ; GFX9-NEXT: v_mul_lo_u32 v4, v0, s12
; GFX9-NEXT: v_add_u32_e32 v6, 1, v0 ; GFX9-NEXT: v_add_u32_e32 v6, 1, v0
; GFX9-NEXT: v_mul_lo_u32 v5, v1, s1 ; GFX9-NEXT: v_mul_lo_u32 v5, v1, s13
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX9-NEXT: v_add_u32_e32 v7, 1, v1
; GFX9-NEXT: v_sub_u32_e32 v4, s8, v4 ; GFX9-NEXT: v_sub_u32_e32 v4, s8, v4
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s0, v4 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s12, v4
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
; GFX9-NEXT: v_subrev_u32_e32 v6, s0, v4 ; GFX9-NEXT: v_subrev_u32_e32 v6, s12, v4
; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX9-NEXT: v_add_u32_e32 v6, 1, v0 ; GFX9-NEXT: v_add_u32_e32 v6, 1, v0
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s0, v4 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s12, v4
; GFX9-NEXT: v_sub_u32_e32 v5, s9, v5 ; GFX9-NEXT: v_sub_u32_e32 v5, s9, v5
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
; GFX9-NEXT: v_subrev_u32_e32 v6, s0, v4 ; GFX9-NEXT: v_subrev_u32_e32 v6, s12, v4
; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX9-NEXT: v_add_u32_e32 v6, 1, v1 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s13, v5
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s1, v5 ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc ; GFX9-NEXT: v_cvt_f32_u32_e32 v7, s15
; GFX9-NEXT: v_cvt_f32_u32_e32 v6, s3 ; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX9-NEXT: s_sub_i32 s0, 0, s2 ; GFX9-NEXT: v_subrev_u32_e32 v8, s13, v5
; GFX9-NEXT: v_mul_lo_u32 v7, s0, v3
; GFX9-NEXT: s_sub_i32 s0, 0, s3
; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v6
; GFX9-NEXT: v_subrev_u32_e32 v8, s1, v5
; GFX9-NEXT: v_mul_hi_u32 v7, v3, v7
; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
; GFX9-NEXT: v_mul_f32_e32 v2, v6, v2 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v7, v7
; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GFX9-NEXT: v_mul_lo_u32 v6, s4, v3
; GFX9-NEXT: v_add_u32_e32 v3, v3, v7 ; GFX9-NEXT: s_sub_i32 s4, 0, s15
; GFX9-NEXT: v_mul_hi_u32 v3, s10, v3
; GFX9-NEXT: v_add_u32_e32 v8, 1, v1 ; GFX9-NEXT: v_add_u32_e32 v8, 1, v1
; GFX9-NEXT: v_mul_lo_u32 v7, s0, v2 ; GFX9-NEXT: v_mul_f32_e32 v2, v7, v2
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s1, v5 ; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX9-NEXT: v_mul_lo_u32 v6, v3, s2 ; GFX9-NEXT: v_mul_hi_u32 v6, v3, v6
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s13, v5
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc
; GFX9-NEXT: v_mul_lo_u32 v7, s4, v2
; GFX9-NEXT: v_add_u32_e32 v3, v3, v6
; GFX9-NEXT: v_mul_hi_u32 v3, s10, v3
; GFX9-NEXT: v_subrev_u32_e32 v8, s13, v5
; GFX9-NEXT: v_mul_hi_u32 v7, v2, v7 ; GFX9-NEXT: v_mul_hi_u32 v7, v2, v7
; GFX9-NEXT: v_subrev_u32_e32 v8, s1, v5
; GFX9-NEXT: v_sub_u32_e32 v6, s10, v6
; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
; GFX9-NEXT: v_mul_lo_u32 v6, v3, s14
; GFX9-NEXT: v_add_u32_e32 v8, 1, v3
; GFX9-NEXT: v_add_u32_e32 v2, v2, v7 ; GFX9-NEXT: v_add_u32_e32 v2, v2, v7
; GFX9-NEXT: v_mul_hi_u32 v7, s11, v2 ; GFX9-NEXT: v_mul_hi_u32 v7, s11, v2
; GFX9-NEXT: v_add_u32_e32 v8, 1, v3 ; GFX9-NEXT: v_sub_u32_e32 v6, s10, v6
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v6 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s14, v6
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
; GFX9-NEXT: v_subrev_u32_e32 v2, s2, v6 ; GFX9-NEXT: v_subrev_u32_e32 v2, s14, v6
; GFX9-NEXT: v_mul_lo_u32 v8, v7, s3 ; GFX9-NEXT: v_mul_lo_u32 v8, v7, s15
; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v2, vcc
; GFX9-NEXT: v_add_u32_e32 v2, 1, v3 ; GFX9-NEXT: v_add_u32_e32 v2, 1, v3
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v6 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s14, v6
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX9-NEXT: v_subrev_u32_e32 v3, s2, v6 ; GFX9-NEXT: v_subrev_u32_e32 v3, s14, v6
; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v3, vcc
; GFX9-NEXT: v_sub_u32_e32 v3, s11, v8 ; GFX9-NEXT: v_sub_u32_e32 v3, s11, v8
; GFX9-NEXT: v_add_u32_e32 v8, 1, v7 ; GFX9-NEXT: v_add_u32_e32 v8, 1, v7
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s15, v3
; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
; GFX9-NEXT: v_subrev_u32_e32 v8, s3, v3 ; GFX9-NEXT: v_subrev_u32_e32 v8, s15, v3
; GFX9-NEXT: v_cndmask_b32_e32 v8, v3, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v8, v3, v8, vcc
; GFX9-NEXT: v_add_u32_e32 v3, 1, v7 ; GFX9-NEXT: v_add_u32_e32 v3, 1, v7
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v8 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s15, v8
; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX9-NEXT: v_subrev_u32_e32 v7, s3, v8 ; GFX9-NEXT: v_subrev_u32_e32 v7, s15, v8
; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc
; GFX9-NEXT: v_mov_b32_e32 v8, 0 ; GFX9-NEXT: v_mov_b32_e32 v8, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dwordx4 v8, v[0:3], s[4:5] ; GFX9-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1]
; GFX9-NEXT: global_store_dwordx4 v8, v[4:7], s[6:7] ; GFX9-NEXT: global_store_dwordx4 v8, v[4:7], s[2:3]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: udivrem_v4i32: ; GFX10-LABEL: udivrem_v4i32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x10
; GFX10-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x20
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x10
; GFX10-NEXT: v_mov_b32_e32 v4, 0x4f7ffffe ; GFX10-NEXT: v_mov_b32_e32 v4, 0x4f7ffffe
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX10-NEXT: v_mov_b32_e32 v8, 0 ; GFX10-NEXT: v_mov_b32_e32 v8, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s8 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s12
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s9 ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s13
; GFX10-NEXT: v_cvt_f32_u32_e32 v2, s10 ; GFX10-NEXT: v_cvt_f32_u32_e32 v2, s14
; GFX10-NEXT: v_cvt_f32_u32_e32 v3, s11 ; GFX10-NEXT: v_cvt_f32_u32_e32 v3, s15
; GFX10-NEXT: s_sub_i32 s6, 0, s8 ; GFX10-NEXT: s_sub_i32 s0, 0, s12
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX10-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX10-NEXT: v_rcp_iflag_f32_e32 v3, v3 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX10-NEXT: s_sub_i32 s7, 0, s9 ; GFX10-NEXT: s_sub_i32 s1, 0, s13
; GFX10-NEXT: s_sub_i32 s12, 0, s10 ; GFX10-NEXT: s_sub_i32 s2, 0, s14
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: v_mul_f32_e32 v1, v1, v4 ; GFX10-NEXT: v_mul_f32_e32 v1, v1, v4
; GFX10-NEXT: v_mul_f32_e32 v2, v2, v4 ; GFX10-NEXT: v_mul_f32_e32 v2, v2, v4
; GFX10-NEXT: v_mul_f32_e32 v3, v3, v4 ; GFX10-NEXT: v_mul_f32_e32 v3, v3, v4
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX10-NEXT: v_mul_lo_u32 v4, s6, v0 ; GFX10-NEXT: v_mul_lo_u32 v4, s0, v0
; GFX10-NEXT: v_mul_lo_u32 v5, s7, v1 ; GFX10-NEXT: v_mul_lo_u32 v5, s1, v1
; GFX10-NEXT: v_mul_lo_u32 v6, s12, v2 ; GFX10-NEXT: v_mul_lo_u32 v6, s2, v2
; GFX10-NEXT: s_sub_i32 s6, 0, s11 ; GFX10-NEXT: s_sub_i32 s0, 0, s15
; GFX10-NEXT: v_mul_lo_u32 v7, s6, v3 ; GFX10-NEXT: v_mul_lo_u32 v7, s0, v3
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX10-NEXT: v_mul_hi_u32 v4, v0, v4 ; GFX10-NEXT: v_mul_hi_u32 v4, v0, v4
; GFX10-NEXT: v_mul_hi_u32 v5, v1, v5 ; GFX10-NEXT: v_mul_hi_u32 v5, v1, v5
; GFX10-NEXT: v_mul_hi_u32 v6, v2, v6 ; GFX10-NEXT: v_mul_hi_u32 v6, v2, v6
; GFX10-NEXT: v_mul_hi_u32 v7, v3, v7 ; GFX10-NEXT: v_mul_hi_u32 v7, v3, v7
; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v4 ; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v4
; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v5 ; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v5
; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v6 ; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v6
; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v7 ; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v7
; GFX10-NEXT: v_mul_hi_u32 v0, s0, v0 ; GFX10-NEXT: v_mul_hi_u32 v0, s8, v0
; GFX10-NEXT: v_mul_hi_u32 v1, s1, v1 ; GFX10-NEXT: v_mul_hi_u32 v1, s9, v1
; GFX10-NEXT: v_mul_hi_u32 v2, s2, v2 ; GFX10-NEXT: v_mul_hi_u32 v2, s10, v2
; GFX10-NEXT: v_mul_hi_u32 v3, s3, v3 ; GFX10-NEXT: v_mul_hi_u32 v3, s11, v3
; GFX10-NEXT: v_mul_lo_u32 v4, v0, s8 ; GFX10-NEXT: v_mul_lo_u32 v4, v0, s12
; GFX10-NEXT: v_mul_lo_u32 v5, v1, s9 ; GFX10-NEXT: v_mul_lo_u32 v5, v1, s13
; GFX10-NEXT: v_mul_lo_u32 v6, v2, s10 ; GFX10-NEXT: v_mul_lo_u32 v6, v2, s14
; GFX10-NEXT: v_add_nc_u32_e32 v9, 1, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v9, 1, v0
; GFX10-NEXT: v_mul_lo_u32 v7, v3, s11 ; GFX10-NEXT: v_mul_lo_u32 v7, v3, s15
; GFX10-NEXT: v_add_nc_u32_e32 v10, 1, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v10, 1, v1
; GFX10-NEXT: v_add_nc_u32_e32 v11, 1, v2 ; GFX10-NEXT: v_add_nc_u32_e32 v11, 1, v2
; GFX10-NEXT: v_add_nc_u32_e32 v12, 1, v3 ; GFX10-NEXT: v_add_nc_u32_e32 v12, 1, v3
; GFX10-NEXT: v_sub_nc_u32_e32 v4, s0, v4 ; GFX10-NEXT: v_sub_nc_u32_e32 v4, s8, v4
; GFX10-NEXT: v_sub_nc_u32_e32 v5, s1, v5 ; GFX10-NEXT: v_sub_nc_u32_e32 v5, s9, v5
; GFX10-NEXT: v_sub_nc_u32_e32 v6, s2, v6 ; GFX10-NEXT: v_sub_nc_u32_e32 v6, s10, v6
; GFX10-NEXT: v_sub_nc_u32_e32 v7, s3, v7 ; GFX10-NEXT: v_sub_nc_u32_e32 v7, s11, v7
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s8, v4 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s12, v4
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s9, v5 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s13, v5
; GFX10-NEXT: v_cmp_le_u32_e64 s1, s10, v6 ; GFX10-NEXT: v_cmp_le_u32_e64 s1, s14, v6
; GFX10-NEXT: v_cmp_le_u32_e64 s2, s11, v7 ; GFX10-NEXT: v_cmp_le_u32_e64 s2, s15, v7
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc_lo
; GFX10-NEXT: v_subrev_nc_u32_e32 v9, s8, v4 ; GFX10-NEXT: v_subrev_nc_u32_e32 v9, s12, v4
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v10, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v10, s0
; GFX10-NEXT: v_subrev_nc_u32_e32 v10, s9, v5 ; GFX10-NEXT: v_subrev_nc_u32_e32 v10, s13, v5
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v11, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v11, s1
; GFX10-NEXT: v_subrev_nc_u32_e32 v11, s10, v6 ; GFX10-NEXT: v_subrev_nc_u32_e32 v11, s14, v6
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v12, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v12, s2
; GFX10-NEXT: v_subrev_nc_u32_e32 v12, s11, v7 ; GFX10-NEXT: v_subrev_nc_u32_e32 v12, s15, v7
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v10, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v10, s0
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v11, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v11, s1
; GFX10-NEXT: v_add_nc_u32_e32 v9, 1, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v9, 1, v0
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v12, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v12, s2
; GFX10-NEXT: v_add_nc_u32_e32 v10, 1, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v10, 1, v1
; GFX10-NEXT: v_add_nc_u32_e32 v11, 1, v2 ; GFX10-NEXT: v_add_nc_u32_e32 v11, 1, v2
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s8, v4 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s12, v4
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s9, v5 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s13, v5
; GFX10-NEXT: v_cmp_le_u32_e64 s1, s10, v6 ; GFX10-NEXT: v_cmp_le_u32_e64 s1, s14, v6
; GFX10-NEXT: v_add_nc_u32_e32 v12, 1, v3 ; GFX10-NEXT: v_add_nc_u32_e32 v12, 1, v3
; GFX10-NEXT: v_cmp_le_u32_e64 s2, s11, v7 ; GFX10-NEXT: v_cmp_le_u32_e64 s2, s15, v7
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc_lo
; GFX10-NEXT: v_subrev_nc_u32_e32 v9, s8, v4 ; GFX10-NEXT: v_subrev_nc_u32_e32 v9, s12, v4
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v10, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v10, s0
; GFX10-NEXT: v_subrev_nc_u32_e32 v10, s9, v5 ; GFX10-NEXT: v_subrev_nc_u32_e32 v10, s13, v5
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v11, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v11, s1
; GFX10-NEXT: v_subrev_nc_u32_e32 v11, s10, v6 ; GFX10-NEXT: v_subrev_nc_u32_e32 v11, s14, v6
; GFX10-NEXT: v_subrev_nc_u32_e32 v13, s11, v7 ; GFX10-NEXT: v_subrev_nc_u32_e32 v13, s15, v7
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v12, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v12, s2
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v10, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v10, s0
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v11, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v11, s1
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v13, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v13, s2
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_store_dwordx4 v8, v[0:3], s[4:5] ; GFX10-NEXT: global_store_dwordx4 v8, v[0:3], s[4:5]
; GFX10-NEXT: global_store_dwordx4 v8, v[4:7], s[6:7] ; GFX10-NEXT: global_store_dwordx4 v8, v[4:7], s[6:7]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%div = udiv <4 x i32> %x, %y %div = udiv <4 x i32> %x, %y
store <4 x i32> %div, <4 x i32> addrspace(1)* %out0 store <4 x i32> %div, <4 x i32> addrspace(1)* %out0
%rem = urem <4 x i32> %x, %y %rem = urem <4 x i32> %x, %y
store <4 x i32> %rem, <4 x i32> addrspace(1)* %out1 store <4 x i32> %rem, <4 x i32> addrspace(1)* %out1
ret void ret void
} }
define amdgpu_kernel void @udivrem_v2i64(<2 x i64> addrspace(1)* %out0, <2 x i64> addrspace(1)* %out1, <2 x i64> %x, <2 x i64> %y) { define amdgpu_kernel void @udivrem_v2i64(<2 x i64> addrspace(1)* %out0, <2 x i64> addrspace(1)* %out1, <2 x i64> %x, <2 x i64> %y) {
; GFX8-LABEL: udivrem_v2i64: ; GFX8-LABEL: udivrem_v2i64:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x20 ; GFX8-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x10
; GFX8-NEXT: s_load_dwordx4 s[12:15], s[4:5], 0x10
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0 ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s9 ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s13
; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s8 ; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s12
; GFX8-NEXT: s_sub_u32 s0, 0, s8 ; GFX8-NEXT: s_sub_u32 s0, 0, s12
; GFX8-NEXT: s_cselect_b32 s1, 1, 0 ; GFX8-NEXT: s_cselect_b32 s1, 1, 0
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GFX8-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_and_b32 s1, s1, 1 ; GFX8-NEXT: s_and_b32 s1, s1, 1
; GFX8-NEXT: s_cmp_lg_u32 s1, 0 ; GFX8-NEXT: s_cmp_lg_u32 s1, 0
; GFX8-NEXT: s_subb_u32 s1, 0, s9 ; GFX8-NEXT: s_subb_u32 s1, 0, s13
; GFX8-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX8-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX8-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX8-NEXT: v_trunc_f32_e32 v1, v1 ; GFX8-NEXT: v_trunc_f32_e32 v1, v1
; GFX8-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1 ; GFX8-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1
; GFX8-NEXT: v_add_f32_e32 v0, v2, v0 ; GFX8-NEXT: v_add_f32_e32 v0, v2, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: s_sub_u32 s2, 0, s10 ; GFX8-NEXT: s_sub_u32 s2, 0, s14
; GFX8-NEXT: v_mul_lo_u32 v2, s0, v1 ; GFX8-NEXT: v_mul_lo_u32 v2, s0, v1
; GFX8-NEXT: v_mul_lo_u32 v3, s1, v0 ; GFX8-NEXT: v_mul_lo_u32 v3, s1, v0
; GFX8-NEXT: v_mul_hi_u32 v5, s0, v0 ; GFX8-NEXT: v_mul_hi_u32 v5, s0, v0
; GFX8-NEXT: v_mul_lo_u32 v4, s0, v0 ; GFX8-NEXT: v_mul_lo_u32 v4, s0, v0
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v2 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v2
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5
; GFX8-NEXT: v_mul_lo_u32 v3, v1, v4 ; GFX8-NEXT: v_mul_lo_u32 v3, v1, v4
; GFX8-NEXT: v_mul_lo_u32 v5, v0, v2 ; GFX8-NEXT: v_mul_lo_u32 v5, v0, v2
; GFX8-NEXT: v_mul_hi_u32 v6, v0, v4 ; GFX8-NEXT: v_mul_hi_u32 v6, v0, v4
; GFX8-NEXT: v_mul_lo_u32 v7, v1, v2
; GFX8-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX8-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v5 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v5
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v6 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v6
; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX8-NEXT: v_mul_lo_u32 v6, v1, v2
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v5, v3 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v5, v3
; GFX8-NEXT: v_mul_hi_u32 v5, v0, v2 ; GFX8-NEXT: v_mul_hi_u32 v5, v0, v2
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v6, v4 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, v7, v4
; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v5 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v5
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v5, vcc, v6, v5 ; GFX8-NEXT: v_add_u32_e32 v5, vcc, v6, v5
; GFX8-NEXT: v_mul_hi_u32 v2, v1, v2 ; GFX8-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v4, v3 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v4, v3
; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v5, v4 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, v5, v4
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v4 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v4
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v3 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v3
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; GFX8-NEXT: v_mul_lo_u32 v2, s1, v0 ; GFX8-NEXT: v_mul_lo_u32 v2, s1, v0
; GFX8-NEXT: v_mul_lo_u32 v3, s0, v1 ; GFX8-NEXT: v_mul_lo_u32 v3, s0, v1
; GFX8-NEXT: v_mul_hi_u32 v5, s0, v0 ; GFX8-NEXT: v_mul_hi_u32 v5, s0, v0
; GFX8-NEXT: v_mul_lo_u32 v4, s0, v0 ; GFX8-NEXT: v_mul_lo_u32 v4, s0, v0
; GFX8-NEXT: v_mov_b32_e32 v6, s9 ; GFX8-NEXT: v_mov_b32_e32 v6, s13
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5
; GFX8-NEXT: v_mul_lo_u32 v3, v1, v4 ; GFX8-NEXT: v_mul_lo_u32 v3, v1, v4
; GFX8-NEXT: v_mul_lo_u32 v5, v0, v2 ; GFX8-NEXT: v_mul_lo_u32 v5, v0, v2
; GFX8-NEXT: v_mul_hi_u32 v7, v0, v4 ; GFX8-NEXT: v_mul_hi_u32 v7, v0, v4
; GFX8-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX8-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v5 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v5
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
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; GFX8-NEXT: v_add_u32_e32 v5, vcc, v7, v5 ; GFX8-NEXT: v_add_u32_e32 v5, vcc, v7, v5
; GFX8-NEXT: v_mul_hi_u32 v2, v1, v2 ; GFX8-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v4, v3 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v4, v3
; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v5, v4 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, v5, v4
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v4 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v4
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v3 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v3
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; GFX8-NEXT: v_mul_lo_u32 v2, s13, v0 ; GFX8-NEXT: v_mul_lo_u32 v2, s9, v0
; GFX8-NEXT: v_mul_lo_u32 v3, s12, v1 ; GFX8-NEXT: v_mul_lo_u32 v3, s8, v1
; GFX8-NEXT: v_mul_hi_u32 v5, s12, v0 ; GFX8-NEXT: v_mul_hi_u32 v5, s8, v0
; GFX8-NEXT: v_mul_hi_u32 v0, s13, v0 ; GFX8-NEXT: v_mul_hi_u32 v0, s9, v0
; GFX8-NEXT: v_mov_b32_e32 v4, s13 ; GFX8-NEXT: v_mov_b32_e32 v4, s9
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3
; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX8-NEXT: v_mul_lo_u32 v5, s13, v1 ; GFX8-NEXT: v_mul_lo_u32 v5, s9, v1
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v2 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v2
; GFX8-NEXT: v_mul_hi_u32 v3, s12, v1 ; GFX8-NEXT: v_mul_hi_u32 v3, s8, v1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v5, v0 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v5, v0
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v3 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v3
; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v5, v3 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v5, v3
; GFX8-NEXT: v_mul_hi_u32 v1, s13, v1 ; GFX8-NEXT: v_mul_hi_u32 v1, s9, v1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v2 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v2
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v2 ; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v2
; GFX8-NEXT: v_mul_lo_u32 v2, s9, v0 ; GFX8-NEXT: v_mul_lo_u32 v2, s13, v0
; GFX8-NEXT: v_mul_lo_u32 v3, s8, v1 ; GFX8-NEXT: v_mul_lo_u32 v3, s12, v1
; GFX8-NEXT: v_mul_hi_u32 v7, s8, v0 ; GFX8-NEXT: v_mul_hi_u32 v7, s12, v0
; GFX8-NEXT: v_mul_lo_u32 v5, s8, v0 ; GFX8-NEXT: v_mul_lo_u32 v5, s12, v0
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v7 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v7
; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s12, v5 ; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s8, v5
; GFX8-NEXT: v_subb_u32_e64 v5, s[0:1], v4, v2, vcc ; GFX8-NEXT: v_subb_u32_e64 v5, s[0:1], v4, v2, vcc
; GFX8-NEXT: v_sub_u32_e64 v2, s[0:1], s13, v2 ; GFX8-NEXT: v_sub_u32_e64 v2, s[0:1], s9, v2
; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v5 ; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v5
; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1]
; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v3 ; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s12, v3
; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1]
; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v5 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], s13, v5
; GFX8-NEXT: v_subb_u32_e32 v2, vcc, v2, v6, vcc ; GFX8-NEXT: v_subb_u32_e32 v2, vcc, v2, v6, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[0:1]
; GFX8-NEXT: v_subrev_u32_e32 v7, vcc, s8, v3 ; GFX8-NEXT: v_subrev_u32_e32 v7, vcc, s12, v3
; GFX8-NEXT: v_subbrev_u32_e64 v8, s[0:1], 0, v2, vcc ; GFX8-NEXT: v_subbrev_u32_e64 v8, s[0:1], 0, v2, vcc
; GFX8-NEXT: v_add_u32_e64 v9, s[0:1], 1, v0 ; GFX8-NEXT: v_add_u32_e64 v9, s[0:1], 1, v0
; GFX8-NEXT: v_addc_u32_e64 v10, s[0:1], 0, v1, s[0:1] ; GFX8-NEXT: v_addc_u32_e64 v10, s[0:1], 0, v1, s[0:1]
; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v8 ; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v8
; GFX8-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[0:1]
; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v7 ; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s12, v7
; GFX8-NEXT: v_subb_u32_e32 v2, vcc, v2, v6, vcc ; GFX8-NEXT: v_subb_u32_e32 v2, vcc, v2, v6, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[0:1]
; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v8 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], s13, v8
; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, s8, v7 ; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, s12, v7
; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v12, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v12, s[0:1]
; GFX8-NEXT: v_add_u32_e64 v12, s[0:1], 1, v9 ; GFX8-NEXT: v_add_u32_e64 v12, s[0:1], 1, v9
; GFX8-NEXT: v_subbrev_u32_e32 v2, vcc, 0, v2, vcc ; GFX8-NEXT: v_subbrev_u32_e32 v2, vcc, 0, v2, vcc
; GFX8-NEXT: v_addc_u32_e64 v13, s[0:1], 0, v10, s[0:1] ; GFX8-NEXT: v_addc_u32_e64 v13, s[0:1], 0, v10, s[0:1]
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; GFX8-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc
; GFX8-NEXT: v_cvt_f32_u32_e32 v13, s11 ; GFX8-NEXT: v_cvt_f32_u32_e32 v13, s15
; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc
; GFX8-NEXT: v_cvt_f32_u32_e32 v12, s10 ; GFX8-NEXT: v_cvt_f32_u32_e32 v12, s14
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; GFX8-NEXT: v_mul_f32_e32 v4, 0x4f800000, v13 ; GFX8-NEXT: v_mul_f32_e32 v4, 0x4f800000, v13
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc
; GFX8-NEXT: v_add_f32_e32 v4, v4, v12 ; GFX8-NEXT: v_add_f32_e32 v4, v4, v12
; GFX8-NEXT: v_rcp_iflag_f32_e32 v9, v4 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v9, v4
; GFX8-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v11 ; GFX8-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v11
; GFX8-NEXT: v_cndmask_b32_e64 v4, v7, v6, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v4, v7, v6, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e32 v4, v3, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v4, v3, v4, vcc
; GFX8-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v9 ; GFX8-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v9
; GFX8-NEXT: v_mul_f32_e32 v6, 0x2f800000, v3 ; GFX8-NEXT: v_mul_f32_e32 v6, 0x2f800000, v3
; GFX8-NEXT: v_trunc_f32_e32 v6, v6 ; GFX8-NEXT: v_trunc_f32_e32 v6, v6
; GFX8-NEXT: v_mul_f32_e32 v7, 0xcf800000, v6 ; GFX8-NEXT: v_mul_f32_e32 v7, 0xcf800000, v6
; GFX8-NEXT: v_add_f32_e32 v3, v7, v3 ; GFX8-NEXT: v_add_f32_e32 v3, v7, v3
; GFX8-NEXT: v_cndmask_b32_e64 v2, v8, v2, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v2, v8, v2, s[0:1]
; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX8-NEXT: v_cvt_u32_f32_e32 v6, v6 ; GFX8-NEXT: v_cvt_u32_f32_e32 v6, v6
; GFX8-NEXT: s_cselect_b32 s0, 1, 0 ; GFX8-NEXT: s_cselect_b32 s0, 1, 0
; GFX8-NEXT: s_and_b32 s0, s0, 1 ; GFX8-NEXT: s_and_b32 s0, s0, 1
; GFX8-NEXT: s_cmp_lg_u32 s0, 0 ; GFX8-NEXT: s_cmp_lg_u32 s0, 0
; GFX8-NEXT: s_subb_u32 s3, 0, s11 ; GFX8-NEXT: s_subb_u32 s3, 0, s15
; GFX8-NEXT: v_mul_lo_u32 v7, s3, v3 ; GFX8-NEXT: v_mul_lo_u32 v7, s3, v3
; GFX8-NEXT: v_mul_lo_u32 v8, s2, v6 ; GFX8-NEXT: v_mul_lo_u32 v8, s2, v6
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v10, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v10, vcc
; GFX8-NEXT: v_mul_hi_u32 v10, s2, v3 ; GFX8-NEXT: v_mul_hi_u32 v10, s2, v3
; GFX8-NEXT: v_mul_lo_u32 v9, s2, v3 ; GFX8-NEXT: v_mul_lo_u32 v9, s2, v3
; GFX8-NEXT: v_add_u32_e64 v7, s[0:1], v7, v8 ; GFX8-NEXT: v_add_u32_e64 v7, s[0:1], v7, v8
; GFX8-NEXT: v_add_u32_e64 v7, s[0:1], v7, v10 ; GFX8-NEXT: v_add_u32_e64 v7, s[0:1], v7, v10
; GFX8-NEXT: v_mul_lo_u32 v8, v6, v9 ; GFX8-NEXT: v_mul_lo_u32 v8, v6, v9
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; GFX8-NEXT: v_add_u32_e32 v8, vcc, v9, v8 ; GFX8-NEXT: v_add_u32_e32 v8, vcc, v9, v8
; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v8 ; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v8
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v2 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v2
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v6, v7, vcc ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v6, v7, vcc
; GFX8-NEXT: v_mul_lo_u32 v6, s3, v2 ; GFX8-NEXT: v_mul_lo_u32 v6, s3, v2
; GFX8-NEXT: v_mul_lo_u32 v7, s2, v3 ; GFX8-NEXT: v_mul_lo_u32 v7, s2, v3
; GFX8-NEXT: v_mul_hi_u32 v9, s2, v2 ; GFX8-NEXT: v_mul_hi_u32 v9, s2, v2
; GFX8-NEXT: v_mul_lo_u32 v8, s2, v2 ; GFX8-NEXT: v_mul_lo_u32 v8, s2, v2
; GFX8-NEXT: v_mov_b32_e32 v10, s11 ; GFX8-NEXT: v_mov_b32_e32 v10, s15
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v7 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v7
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v9 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v9
; GFX8-NEXT: v_mul_lo_u32 v7, v3, v8 ; GFX8-NEXT: v_mul_lo_u32 v7, v3, v8
; GFX8-NEXT: v_mul_lo_u32 v9, v2, v6 ; GFX8-NEXT: v_mul_lo_u32 v9, v2, v6
; GFX8-NEXT: v_mul_hi_u32 v11, v2, v8 ; GFX8-NEXT: v_mul_hi_u32 v11, v2, v8
; GFX8-NEXT: v_mul_hi_u32 v8, v3, v8 ; GFX8-NEXT: v_mul_hi_u32 v8, v3, v8
; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v9 ; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v9
; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
Show All 9 Lines
; GFX8-NEXT: v_add_u32_e32 v9, vcc, v11, v9 ; GFX8-NEXT: v_add_u32_e32 v9, vcc, v11, v9
; GFX8-NEXT: v_mul_hi_u32 v6, v3, v6 ; GFX8-NEXT: v_mul_hi_u32 v6, v3, v6
; GFX8-NEXT: v_add_u32_e32 v7, vcc, v8, v7 ; GFX8-NEXT: v_add_u32_e32 v7, vcc, v8, v7
; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v8, vcc, v9, v8 ; GFX8-NEXT: v_add_u32_e32 v8, vcc, v9, v8
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v8 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v8
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v7 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v7
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v3, v6, vcc ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v3, v6, vcc
; GFX8-NEXT: v_mul_lo_u32 v6, s15, v2 ; GFX8-NEXT: v_mul_lo_u32 v6, s11, v2
; GFX8-NEXT: v_mul_lo_u32 v7, s14, v3 ; GFX8-NEXT: v_mul_lo_u32 v7, s10, v3
; GFX8-NEXT: v_mul_hi_u32 v9, s14, v2 ; GFX8-NEXT: v_mul_hi_u32 v9, s10, v2
; GFX8-NEXT: v_mul_hi_u32 v2, s15, v2 ; GFX8-NEXT: v_mul_hi_u32 v2, s11, v2
; GFX8-NEXT: v_mov_b32_e32 v8, s15 ; GFX8-NEXT: v_mov_b32_e32 v8, s11
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v7 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v7
; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v9 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v9
; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX8-NEXT: v_mul_lo_u32 v9, s15, v3 ; GFX8-NEXT: v_mul_lo_u32 v9, s11, v3
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v7, v6 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v7, v6
; GFX8-NEXT: v_mul_hi_u32 v7, s14, v3 ; GFX8-NEXT: v_mul_hi_u32 v7, s10, v3
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v9, v2 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v9, v2
; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v7 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v7
; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v7, vcc, v9, v7 ; GFX8-NEXT: v_add_u32_e32 v7, vcc, v9, v7
; GFX8-NEXT: v_mul_hi_u32 v3, s15, v3 ; GFX8-NEXT: v_mul_hi_u32 v3, s11, v3
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v6 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v6
; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v7, v6 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v7, v6
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v6 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v6
; GFX8-NEXT: v_mul_lo_u32 v6, s11, v2 ; GFX8-NEXT: v_mul_lo_u32 v6, s15, v2
; GFX8-NEXT: v_mul_lo_u32 v7, s10, v3 ; GFX8-NEXT: v_mul_lo_u32 v7, s14, v3
; GFX8-NEXT: v_mul_hi_u32 v11, s10, v2 ; GFX8-NEXT: v_mul_hi_u32 v11, s14, v2
; GFX8-NEXT: v_mul_lo_u32 v9, s10, v2 ; GFX8-NEXT: v_mul_lo_u32 v9, s14, v2
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v7 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v7
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v11 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v11
; GFX8-NEXT: v_sub_u32_e32 v7, vcc, s14, v9 ; GFX8-NEXT: v_sub_u32_e32 v7, vcc, s10, v9
; GFX8-NEXT: v_subb_u32_e64 v8, s[0:1], v8, v6, vcc ; GFX8-NEXT: v_subb_u32_e64 v8, s[0:1], v8, v6, vcc
; GFX8-NEXT: v_sub_u32_e64 v6, s[0:1], s15, v6 ; GFX8-NEXT: v_sub_u32_e64 v6, s[0:1], s11, v6
; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v8 ; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s15, v8
; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[0:1]
; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v7 ; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s14, v7
; GFX8-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[0:1]
; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v8 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], s15, v8
; GFX8-NEXT: v_subb_u32_e32 v6, vcc, v6, v10, vcc ; GFX8-NEXT: v_subb_u32_e32 v6, vcc, v6, v10, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v9, v9, v11, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v9, v9, v11, s[0:1]
; GFX8-NEXT: v_subrev_u32_e32 v11, vcc, s10, v7 ; GFX8-NEXT: v_subrev_u32_e32 v11, vcc, s14, v7
; GFX8-NEXT: v_subbrev_u32_e64 v12, s[0:1], 0, v6, vcc ; GFX8-NEXT: v_subbrev_u32_e64 v12, s[0:1], 0, v6, vcc
; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v12 ; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s15, v12
; GFX8-NEXT: v_cndmask_b32_e64 v13, 0, -1, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v13, 0, -1, s[0:1]
; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v11 ; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s14, v11
; GFX8-NEXT: v_cndmask_b32_e64 v14, 0, -1, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v14, 0, -1, s[0:1]
; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v12 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], s15, v12
; GFX8-NEXT: v_cndmask_b32_e64 v13, v13, v14, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v13, v13, v14, s[0:1]
; GFX8-NEXT: v_add_u32_e64 v14, s[0:1], 1, v2 ; GFX8-NEXT: v_add_u32_e64 v14, s[0:1], 1, v2
; GFX8-NEXT: v_subb_u32_e32 v6, vcc, v6, v10, vcc ; GFX8-NEXT: v_subb_u32_e32 v6, vcc, v6, v10, vcc
; GFX8-NEXT: v_addc_u32_e64 v15, s[0:1], 0, v3, s[0:1] ; GFX8-NEXT: v_addc_u32_e64 v15, s[0:1], 0, v3, s[0:1]
; GFX8-NEXT: v_add_u32_e32 v10, vcc, 1, v14 ; GFX8-NEXT: v_add_u32_e32 v10, vcc, 1, v14
; GFX8-NEXT: v_addc_u32_e32 v16, vcc, 0, v15, vcc ; GFX8-NEXT: v_addc_u32_e32 v16, vcc, 0, v15, vcc
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13
; GFX8-NEXT: v_subrev_u32_e64 v13, s[0:1], s10, v11 ; GFX8-NEXT: v_subrev_u32_e64 v13, s[0:1], s14, v11
; GFX8-NEXT: v_subbrev_u32_e64 v6, s[0:1], 0, v6, s[0:1] ; GFX8-NEXT: v_subbrev_u32_e64 v6, s[0:1], 0, v6, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e32 v10, v14, v10, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v10, v14, v10, vcc
; GFX8-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v9 ; GFX8-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v9
; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v10, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v10, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e32 v9, v11, v13, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v9, v11, v13, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v10, v12, v6, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v10, v12, v6, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v14, v15, v16, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v14, v15, v16, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v6, v7, v9, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v6, v7, v9, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e64 v7, v8, v10, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v7, v8, v10, s[0:1]
; GFX8-NEXT: v_mov_b32_e32 v9, s5 ; GFX8-NEXT: v_mov_b32_e32 v9, s5
; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v14, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v14, s[0:1]
; GFX8-NEXT: v_mov_b32_e32 v8, s4 ; GFX8-NEXT: v_mov_b32_e32 v8, s4
; GFX8-NEXT: flat_store_dwordx4 v[8:9], v[0:3] ; GFX8-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
; GFX8-NEXT: s_nop 0 ; GFX8-NEXT: s_nop 0
; GFX8-NEXT: v_mov_b32_e32 v0, s6 ; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: v_mov_b32_e32 v1, s7 ; GFX8-NEXT: v_mov_b32_e32 v1, s7
; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[4:7] ; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-LABEL: udivrem_v2i64: ; GFX9-LABEL: udivrem_v2i64:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x20 ; GFX9-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x10
; GFX9-NEXT: s_load_dwordx4 s[12:15], s[4:5], 0x10
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s9 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s13
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s8 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s12
; GFX9-NEXT: s_sub_u32 s0, 0, s8 ; GFX9-NEXT: s_sub_u32 s0, 0, s12
; GFX9-NEXT: s_cselect_b32 s1, 1, 0 ; GFX9-NEXT: s_cselect_b32 s1, 1, 0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GFX9-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: s_and_b32 s1, s1, 1 ; GFX9-NEXT: s_and_b32 s1, s1, 1
; GFX9-NEXT: s_cmp_lg_u32 s1, 0 ; GFX9-NEXT: s_cmp_lg_u32 s1, 0
; GFX9-NEXT: s_subb_u32 s1, 0, s9 ; GFX9-NEXT: s_subb_u32 s1, 0, s13
; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1
; GFX9-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1 ; GFX9-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1
; GFX9-NEXT: v_add_f32_e32 v0, v2, v0 ; GFX9-NEXT: v_add_f32_e32 v0, v2, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_f32_u32_e32 v14, s11 ; GFX9-NEXT: v_cvt_f32_u32_e32 v14, s15
; GFX9-NEXT: s_sub_u32 s2, 0, s10 ; GFX9-NEXT: s_sub_u32 s2, 0, s14
; GFX9-NEXT: v_mul_lo_u32 v2, s0, v1 ; GFX9-NEXT: v_mul_lo_u32 v2, s0, v1
; GFX9-NEXT: v_mul_lo_u32 v3, s1, v0 ; GFX9-NEXT: v_mul_lo_u32 v3, s1, v0
; GFX9-NEXT: v_mul_hi_u32 v4, s0, v0 ; GFX9-NEXT: v_mul_hi_u32 v4, s0, v0
; GFX9-NEXT: v_mul_lo_u32 v5, s0, v0 ; GFX9-NEXT: v_mul_lo_u32 v5, s0, v0
; GFX9-NEXT: v_mul_f32_e32 v14, 0x4f800000, v14 ; GFX9-NEXT: v_mul_f32_e32 v14, 0x4f800000, v14
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX9-NEXT: v_add3_u32 v2, v3, v2, v4 ; GFX9-NEXT: v_add3_u32 v2, v3, v2, v4
; GFX9-NEXT: v_mul_lo_u32 v3, v1, v5 ; GFX9-NEXT: v_mul_lo_u32 v3, v1, v5
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; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-NEXT: v_add3_u32 v2, v5, v4, v2 ; GFX9-NEXT: v_add3_u32 v2, v5, v4, v2
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v2, vcc
; GFX9-NEXT: v_mul_lo_u32 v2, s1, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, s1, v0
; GFX9-NEXT: v_mul_lo_u32 v3, s0, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, s0, v1
; GFX9-NEXT: v_mul_hi_u32 v4, s0, v0 ; GFX9-NEXT: v_mul_hi_u32 v4, s0, v0
; GFX9-NEXT: v_mul_lo_u32 v5, s0, v0 ; GFX9-NEXT: v_mul_lo_u32 v5, s0, v0
; GFX9-NEXT: v_mov_b32_e32 v7, s13 ; GFX9-NEXT: v_mov_b32_e32 v7, s9
; GFX9-NEXT: v_add3_u32 v2, v2, v3, v4 ; GFX9-NEXT: v_add3_u32 v2, v2, v3, v4
; GFX9-NEXT: v_mul_lo_u32 v3, v1, v5 ; GFX9-NEXT: v_mul_lo_u32 v3, v1, v5
; GFX9-NEXT: v_mul_lo_u32 v4, v0, v2 ; GFX9-NEXT: v_mul_lo_u32 v4, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v6, v0, v5 ; GFX9-NEXT: v_mul_hi_u32 v6, v0, v5
; GFX9-NEXT: v_mul_hi_u32 v5, v1, v5 ; GFX9-NEXT: v_mul_hi_u32 v5, v1, v5
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6
; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX9-NEXT: v_mul_lo_u32 v6, v1, v2 ; GFX9-NEXT: v_mul_lo_u32 v6, v1, v2
; GFX9-NEXT: v_add_u32_e32 v3, v4, v3 ; GFX9-NEXT: v_add_u32_e32 v3, v4, v3
; GFX9-NEXT: v_mul_hi_u32 v4, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v4, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v2, v1, v2 ; GFX9-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v6, v5 ; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v6, v5
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX9-NEXT: v_add_u32_e32 v5, v6, v5 ; GFX9-NEXT: v_add_u32_e32 v5, v6, v5
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-NEXT: v_add3_u32 v2, v5, v4, v2 ; GFX9-NEXT: v_add3_u32 v2, v5, v4, v2
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v2, vcc
; GFX9-NEXT: v_mul_lo_u32 v2, s13, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, s9, v0
; GFX9-NEXT: v_mul_lo_u32 v3, s12, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, s8, v1
; GFX9-NEXT: v_mul_hi_u32 v4, s12, v0 ; GFX9-NEXT: v_mul_hi_u32 v4, s8, v0
; GFX9-NEXT: v_mul_hi_u32 v0, s13, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s9, v0
; GFX9-NEXT: v_mov_b32_e32 v5, s9 ; GFX9-NEXT: v_mov_b32_e32 v5, s13
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3
; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, s13, v1 ; GFX9-NEXT: v_mul_lo_u32 v4, s9, v1
; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
; GFX9-NEXT: v_mul_hi_u32 v3, s12, v1 ; GFX9-NEXT: v_mul_hi_u32 v3, s8, v1
; GFX9-NEXT: v_mul_hi_u32 v1, s13, v1 ; GFX9-NEXT: v_mul_hi_u32 v1, s9, v1
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v4, v0 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v4, v0
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: v_add_u32_e32 v3, v4, v3 ; GFX9-NEXT: v_add_u32_e32 v3, v4, v3
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_add3_u32 v1, v3, v2, v1 ; GFX9-NEXT: v_add3_u32 v1, v3, v2, v1
; GFX9-NEXT: v_mul_lo_u32 v2, s9, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, s13, v0
; GFX9-NEXT: v_mul_lo_u32 v3, s8, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, s12, v1
; GFX9-NEXT: v_mul_hi_u32 v4, s8, v0 ; GFX9-NEXT: v_mul_hi_u32 v4, s12, v0
; GFX9-NEXT: v_mul_lo_u32 v6, s8, v0 ; GFX9-NEXT: v_mul_lo_u32 v6, s12, v0
; GFX9-NEXT: v_add3_u32 v2, v2, v3, v4 ; GFX9-NEXT: v_add3_u32 v2, v2, v3, v4
; GFX9-NEXT: v_sub_co_u32_e32 v3, vcc, s12, v6 ; GFX9-NEXT: v_sub_co_u32_e32 v3, vcc, s8, v6
; GFX9-NEXT: v_subb_co_u32_e64 v6, s[0:1], v7, v2, vcc ; GFX9-NEXT: v_subb_co_u32_e64 v6, s[0:1], v7, v2, vcc
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v6 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v6
; GFX9-NEXT: v_sub_u32_e32 v2, s13, v2 ; GFX9-NEXT: v_sub_u32_e32 v2, s9, v2
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v3 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s12, v3
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v6 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s13, v6
; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v5, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v5, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[0:1]
; GFX9-NEXT: v_subrev_co_u32_e32 v7, vcc, s8, v3 ; GFX9-NEXT: v_subrev_co_u32_e32 v7, vcc, s12, v3
; GFX9-NEXT: v_subbrev_co_u32_e64 v8, s[0:1], 0, v2, vcc ; GFX9-NEXT: v_subbrev_co_u32_e64 v8, s[0:1], 0, v2, vcc
; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v5, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v5, vcc
; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s10 ; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s14
; GFX9-NEXT: v_add_co_u32_e64 v9, s[0:1], 1, v0 ; GFX9-NEXT: v_add_co_u32_e64 v9, s[0:1], 1, v0
; GFX9-NEXT: v_addc_co_u32_e64 v10, s[0:1], 0, v1, s[0:1] ; GFX9-NEXT: v_addc_co_u32_e64 v10, s[0:1], 0, v1, s[0:1]
; GFX9-NEXT: v_add_f32_e32 v5, v14, v5 ; GFX9-NEXT: v_add_f32_e32 v5, v14, v5
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v8 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v8
; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v5 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v5
; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v7 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s12, v7
; GFX9-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v8 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s13, v8
; GFX9-NEXT: v_subrev_co_u32_e32 v15, vcc, s8, v7 ; GFX9-NEXT: v_subrev_co_u32_e32 v15, vcc, s12, v7
; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, v12, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, v12, s[0:1]
; GFX9-NEXT: v_subbrev_co_u32_e32 v2, vcc, 0, v2, vcc ; GFX9-NEXT: v_subbrev_co_u32_e32 v2, vcc, 0, v2, vcc
; GFX9-NEXT: v_add_co_u32_e64 v12, s[0:1], 1, v9 ; GFX9-NEXT: v_add_co_u32_e64 v12, s[0:1], 1, v9
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; GFX9-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5 ; GFX9-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5
; GFX9-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc
; GFX9-NEXT: v_mul_f32_e32 v12, 0x2f800000, v5 ; GFX9-NEXT: v_mul_f32_e32 v12, 0x2f800000, v5
; GFX9-NEXT: v_addc_co_u32_e64 v13, s[0:1], 0, v10, s[0:1] ; GFX9-NEXT: v_addc_co_u32_e64 v13, s[0:1], 0, v10, s[0:1]
; GFX9-NEXT: v_trunc_f32_e32 v12, v12 ; GFX9-NEXT: v_trunc_f32_e32 v12, v12
; GFX9-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc
; GFX9-NEXT: v_mul_f32_e32 v13, 0xcf800000, v12 ; GFX9-NEXT: v_mul_f32_e32 v13, 0xcf800000, v12
; GFX9-NEXT: v_add_f32_e32 v5, v13, v5 ; GFX9-NEXT: v_add_f32_e32 v5, v13, v5
; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5 ; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5
; GFX9-NEXT: v_cvt_u32_f32_e32 v12, v12 ; GFX9-NEXT: v_cvt_u32_f32_e32 v12, v12
; GFX9-NEXT: s_cselect_b32 s0, 1, 0 ; GFX9-NEXT: s_cselect_b32 s0, 1, 0
; GFX9-NEXT: s_and_b32 s0, s0, 1 ; GFX9-NEXT: s_and_b32 s0, s0, 1
; GFX9-NEXT: s_cmp_lg_u32 s0, 0 ; GFX9-NEXT: s_cmp_lg_u32 s0, 0
; GFX9-NEXT: s_subb_u32 s3, 0, s11 ; GFX9-NEXT: s_subb_u32 s3, 0, s15
; GFX9-NEXT: v_mul_lo_u32 v13, s3, v5 ; GFX9-NEXT: v_mul_lo_u32 v13, s3, v5
; GFX9-NEXT: v_mul_lo_u32 v14, s2, v12 ; GFX9-NEXT: v_mul_lo_u32 v14, s2, v12
; GFX9-NEXT: v_mul_hi_u32 v16, s2, v5 ; GFX9-NEXT: v_mul_hi_u32 v16, s2, v5
; GFX9-NEXT: v_mul_lo_u32 v17, s2, v5 ; GFX9-NEXT: v_mul_lo_u32 v17, s2, v5
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc
; GFX9-NEXT: v_add3_u32 v4, v13, v14, v16 ; GFX9-NEXT: v_add3_u32 v4, v13, v14, v16
; GFX9-NEXT: v_mul_lo_u32 v9, v12, v17 ; GFX9-NEXT: v_mul_lo_u32 v9, v12, v17
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_add_co_u32_e64 v7, s[0:1], v7, v11 ; GFX9-NEXT: v_add_co_u32_e64 v7, s[0:1], v7, v11
; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[0:1]
; GFX9-NEXT: v_add_co_u32_e64 v3, s[0:1], v7, v3 ; GFX9-NEXT: v_add_co_u32_e64 v3, s[0:1], v7, v3
; GFX9-NEXT: v_add_u32_e32 v10, v10, v11 ; GFX9-NEXT: v_add_u32_e32 v10, v10, v11
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[0:1]
; GFX9-NEXT: v_add3_u32 v7, v10, v7, v8 ; GFX9-NEXT: v_add3_u32 v7, v10, v7, v8
; GFX9-NEXT: v_add_co_u32_e64 v3, s[0:1], v5, v3 ; GFX9-NEXT: v_add_co_u32_e64 v3, s[0:1], v5, v3
; GFX9-NEXT: v_addc_co_u32_e64 v7, s[0:1], v9, v7, s[0:1] ; GFX9-NEXT: v_addc_co_u32_e64 v7, s[0:1], v9, v7, s[0:1]
; GFX9-NEXT: v_mul_lo_u32 v8, s15, v3 ; GFX9-NEXT: v_mul_lo_u32 v8, s11, v3
; GFX9-NEXT: v_mul_lo_u32 v9, s14, v7 ; GFX9-NEXT: v_mul_lo_u32 v9, s10, v7
; GFX9-NEXT: v_cndmask_b32_e32 v5, v6, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v5, v6, v2, vcc
; GFX9-NEXT: v_mul_hi_u32 v2, s14, v3 ; GFX9-NEXT: v_mul_hi_u32 v2, s10, v3
; GFX9-NEXT: v_mul_hi_u32 v3, s15, v3 ; GFX9-NEXT: v_mul_hi_u32 v3, s11, v3
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v8, v9 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v8, v9
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v6, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v6, v2
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_mul_lo_u32 v6, s15, v7 ; GFX9-NEXT: v_mul_lo_u32 v6, s11, v7
; GFX9-NEXT: v_add_u32_e32 v2, v8, v2 ; GFX9-NEXT: v_add_u32_e32 v2, v8, v2
; GFX9-NEXT: v_mul_hi_u32 v8, s14, v7 ; GFX9-NEXT: v_mul_hi_u32 v8, s10, v7
; GFX9-NEXT: v_mul_hi_u32 v7, s15, v7 ; GFX9-NEXT: v_mul_hi_u32 v7, s11, v7
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v6, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v6, v3
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v8 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v8
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_add_u32_e32 v6, v6, v8 ; GFX9-NEXT: v_add_u32_e32 v6, v6, v8
; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX9-NEXT: v_add3_u32 v3, v6, v3, v7 ; GFX9-NEXT: v_add3_u32 v3, v6, v3, v7
; GFX9-NEXT: v_mul_lo_u32 v6, s11, v2 ; GFX9-NEXT: v_mul_lo_u32 v6, s15, v2
; GFX9-NEXT: v_mul_lo_u32 v7, s10, v3 ; GFX9-NEXT: v_mul_lo_u32 v7, s14, v3
; GFX9-NEXT: v_mul_hi_u32 v8, s10, v2 ; GFX9-NEXT: v_mul_hi_u32 v8, s14, v2
; GFX9-NEXT: v_mul_lo_u32 v10, s10, v2 ; GFX9-NEXT: v_mul_lo_u32 v10, s14, v2
; GFX9-NEXT: v_mov_b32_e32 v11, s15 ; GFX9-NEXT: v_mov_b32_e32 v11, s11
; GFX9-NEXT: v_mov_b32_e32 v9, s11 ; GFX9-NEXT: v_mov_b32_e32 v9, s15
; GFX9-NEXT: v_add3_u32 v6, v6, v7, v8 ; GFX9-NEXT: v_add3_u32 v6, v6, v7, v8
; GFX9-NEXT: v_sub_co_u32_e32 v7, vcc, s14, v10 ; GFX9-NEXT: v_sub_co_u32_e32 v7, vcc, s10, v10
; GFX9-NEXT: v_subb_co_u32_e64 v8, s[0:1], v11, v6, vcc ; GFX9-NEXT: v_subb_co_u32_e64 v8, s[0:1], v11, v6, vcc
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v8 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s15, v8
; GFX9-NEXT: v_sub_u32_e32 v6, s15, v6 ; GFX9-NEXT: v_sub_u32_e32 v6, s11, v6
; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v7 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s14, v7
; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v8 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s15, v8
; GFX9-NEXT: v_subb_co_u32_e32 v6, vcc, v6, v9, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v6, vcc, v6, v9, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v10, v10, v11, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v10, v10, v11, s[0:1]
; GFX9-NEXT: v_subrev_co_u32_e32 v11, vcc, s10, v7 ; GFX9-NEXT: v_subrev_co_u32_e32 v11, vcc, s14, v7
; GFX9-NEXT: v_subbrev_co_u32_e64 v12, s[0:1], 0, v6, vcc ; GFX9-NEXT: v_subbrev_co_u32_e64 v12, s[0:1], 0, v6, vcc
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v12 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s15, v12
; GFX9-NEXT: v_cndmask_b32_e64 v13, 0, -1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v13, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v11 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s14, v11
; GFX9-NEXT: v_cndmask_b32_e64 v14, 0, -1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v14, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v12 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s15, v12
; GFX9-NEXT: v_cndmask_b32_e64 v13, v13, v14, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v13, v13, v14, s[0:1]
; GFX9-NEXT: v_add_co_u32_e64 v14, s[0:1], 1, v2 ; GFX9-NEXT: v_add_co_u32_e64 v14, s[0:1], 1, v2
; GFX9-NEXT: v_subb_co_u32_e32 v6, vcc, v6, v9, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v6, vcc, v6, v9, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v15, s[0:1], 0, v3, s[0:1] ; GFX9-NEXT: v_addc_co_u32_e64 v15, s[0:1], 0, v3, s[0:1]
; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, 1, v14 ; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, 1, v14
; GFX9-NEXT: v_addc_co_u32_e32 v16, vcc, 0, v15, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v16, vcc, 0, v15, vcc
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13
; GFX9-NEXT: v_cndmask_b32_e32 v9, v14, v9, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v9, v14, v9, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v14, v15, v16, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v14, v15, v16, vcc
; GFX9-NEXT: v_subrev_co_u32_e64 v15, s[0:1], s10, v11 ; GFX9-NEXT: v_subrev_co_u32_e64 v15, s[0:1], s14, v11
; GFX9-NEXT: v_subbrev_co_u32_e64 v6, s[0:1], 0, v6, s[0:1] ; GFX9-NEXT: v_subbrev_co_u32_e64 v6, s[0:1], 0, v6, s[0:1]
; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v10 ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v10
; GFX9-NEXT: v_mov_b32_e32 v13, 0 ; GFX9-NEXT: v_mov_b32_e32 v13, 0
; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v9, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v9, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v14, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v14, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e32 v9, v11, v15, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v9, v11, v15, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v10, v12, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v10, v12, v6, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v6, v7, v9, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v6, v7, v9, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v7, v8, v10, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v7, v8, v10, s[0:1]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dwordx4 v13, v[0:3], s[4:5] ; GFX9-NEXT: global_store_dwordx4 v13, v[0:3], s[4:5]
; GFX9-NEXT: global_store_dwordx4 v13, v[4:7], s[6:7] ; GFX9-NEXT: global_store_dwordx4 v13, v[4:7], s[6:7]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: udivrem_v2i64: ; GFX10-LABEL: udivrem_v2i64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x20 ; GFX10-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x10
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s9 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s13
; GFX10-NEXT: v_cvt_f32_u32_e32 v2, s11 ; GFX10-NEXT: v_cvt_f32_u32_e32 v2, s15
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s8 ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s12
; GFX10-NEXT: v_cvt_f32_u32_e32 v3, s10 ; GFX10-NEXT: v_cvt_f32_u32_e32 v3, s14
; GFX10-NEXT: s_sub_u32 s6, 0, s8 ; GFX10-NEXT: s_sub_u32 s0, 0, s12
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GFX10-NEXT: v_mul_f32_e32 v2, 0x4f800000, v2 ; GFX10-NEXT: v_mul_f32_e32 v2, 0x4f800000, v2
; GFX10-NEXT: s_cselect_b32 s0, 1, 0 ; GFX10-NEXT: s_cselect_b32 s1, 1, 0
; GFX10-NEXT: s_and_b32 s0, s0, 1 ; GFX10-NEXT: s_and_b32 s1, s1, 1
; GFX10-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
; GFX10-NEXT: v_add_f32_e32 v1, v2, v3 ; GFX10-NEXT: v_add_f32_e32 v1, v2, v3
; GFX10-NEXT: s_cmp_lg_u32 s0, 0 ; GFX10-NEXT: s_cmp_lg_u32 s1, 0
; GFX10-NEXT: s_subb_u32 s7, 0, s9 ; GFX10-NEXT: s_subb_u32 s1, 0, s13
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX10-NEXT: s_sub_u32 s12, 0, s10 ; GFX10-NEXT: s_sub_u32 s2, 0, s14
; GFX10-NEXT: s_cselect_b32 s0, 1, 0 ; GFX10-NEXT: s_cselect_b32 s3, 1, 0
; GFX10-NEXT: s_and_b32 s0, s0, 1 ; GFX10-NEXT: s_and_b32 s3, s3, 1
; GFX10-NEXT: s_cmp_lg_u32 s0, 0 ; GFX10-NEXT: s_cmp_lg_u32 s3, 0
; GFX10-NEXT: s_subb_u32 s13, 0, s11 ; GFX10-NEXT: s_subb_u32 s3, 0, s15
; GFX10-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX10-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v1 ; GFX10-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v1
; GFX10-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0 ; GFX10-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0
; GFX10-NEXT: v_mul_f32_e32 v3, 0x2f800000, v1 ; GFX10-NEXT: v_mul_f32_e32 v3, 0x2f800000, v1
; GFX10-NEXT: v_trunc_f32_e32 v2, v2 ; GFX10-NEXT: v_trunc_f32_e32 v2, v2
; GFX10-NEXT: v_trunc_f32_e32 v3, v3 ; GFX10-NEXT: v_trunc_f32_e32 v3, v3
; GFX10-NEXT: v_mul_f32_e32 v4, 0xcf800000, v2 ; GFX10-NEXT: v_mul_f32_e32 v4, 0xcf800000, v2
; GFX10-NEXT: v_mul_f32_e32 v5, 0xcf800000, v3 ; GFX10-NEXT: v_mul_f32_e32 v5, 0xcf800000, v3
; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX10-NEXT: v_add_f32_e32 v0, v4, v0 ; GFX10-NEXT: v_add_f32_e32 v0, v4, v0
; GFX10-NEXT: v_add_f32_e32 v1, v5, v1 ; GFX10-NEXT: v_add_f32_e32 v1, v5, v1
; GFX10-NEXT: v_mul_lo_u32 v4, s6, v2 ; GFX10-NEXT: v_mul_lo_u32 v4, s0, v2
; GFX10-NEXT: v_mul_lo_u32 v8, s12, v3 ; GFX10-NEXT: v_mul_lo_u32 v8, s2, v3
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX10-NEXT: v_mul_lo_u32 v5, s7, v0 ; GFX10-NEXT: v_mul_lo_u32 v5, s1, v0
; GFX10-NEXT: v_mul_hi_u32 v6, s6, v0 ; GFX10-NEXT: v_mul_hi_u32 v6, s0, v0
; GFX10-NEXT: v_mul_lo_u32 v9, s13, v1 ; GFX10-NEXT: v_mul_lo_u32 v9, s3, v1
; GFX10-NEXT: v_mul_hi_u32 v10, s12, v1 ; GFX10-NEXT: v_mul_hi_u32 v10, s2, v1
; GFX10-NEXT: v_mul_lo_u32 v7, s6, v0 ; GFX10-NEXT: v_mul_lo_u32 v7, s0, v0
; GFX10-NEXT: v_mul_lo_u32 v11, s12, v1 ; GFX10-NEXT: v_mul_lo_u32 v11, s2, v1
; GFX10-NEXT: v_add3_u32 v4, v5, v4, v6 ; GFX10-NEXT: v_add3_u32 v4, v5, v4, v6
; GFX10-NEXT: v_add3_u32 v8, v9, v8, v10 ; GFX10-NEXT: v_add3_u32 v8, v9, v8, v10
; GFX10-NEXT: v_mul_lo_u32 v5, v2, v7 ; GFX10-NEXT: v_mul_lo_u32 v5, v2, v7
; GFX10-NEXT: v_mul_hi_u32 v6, v0, v7 ; GFX10-NEXT: v_mul_hi_u32 v6, v0, v7
; GFX10-NEXT: v_mul_lo_u32 v12, v0, v4 ; GFX10-NEXT: v_mul_lo_u32 v12, v0, v4
; GFX10-NEXT: v_mul_hi_u32 v7, v2, v7 ; GFX10-NEXT: v_mul_hi_u32 v7, v2, v7
; GFX10-NEXT: v_mul_lo_u32 v13, v2, v4 ; GFX10-NEXT: v_mul_lo_u32 v13, v2, v4
; GFX10-NEXT: v_mul_lo_u32 v9, v3, v11 ; GFX10-NEXT: v_mul_lo_u32 v9, v3, v11
; GFX10-NEXT: v_mul_lo_u32 v15, v1, v8 ; GFX10-NEXT: v_mul_lo_u32 v15, v1, v8
; GFX10-NEXT: v_mul_hi_u32 v10, v1, v11 ; GFX10-NEXT: v_mul_hi_u32 v10, v1, v11
; GFX10-NEXT: v_mul_hi_u32 v11, v3, v11 ; GFX10-NEXT: v_mul_hi_u32 v11, v3, v11
; GFX10-NEXT: v_mul_lo_u32 v16, v3, v8 ; GFX10-NEXT: v_mul_lo_u32 v16, v3, v8
; GFX10-NEXT: v_add_co_u32 v5, s0, v5, v12 ; GFX10-NEXT: v_add_co_u32 v5, s6, v5, v12
; GFX10-NEXT: v_mul_hi_u32 v14, v0, v4 ; GFX10-NEXT: v_mul_hi_u32 v14, v0, v4
; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, 1, s6
; GFX10-NEXT: v_add_co_u32 v7, s0, v13, v7 ; GFX10-NEXT: v_add_co_u32 v7, s6, v13, v7
; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, 1, s6
; GFX10-NEXT: v_add_co_u32 v9, s0, v9, v15 ; GFX10-NEXT: v_add_co_u32 v9, s6, v9, v15
; GFX10-NEXT: v_cndmask_b32_e64 v15, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v15, 0, 1, s6
; GFX10-NEXT: v_add_co_u32 v11, s0, v16, v11 ; GFX10-NEXT: v_add_co_u32 v11, s6, v16, v11
; GFX10-NEXT: v_cndmask_b32_e64 v16, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v16, 0, 1, s6
; GFX10-NEXT: v_add_co_u32 v5, s0, v5, v6 ; GFX10-NEXT: v_add_co_u32 v5, s6, v5, v6
; GFX10-NEXT: v_mul_hi_u32 v17, v1, v8 ; GFX10-NEXT: v_mul_hi_u32 v17, v1, v8
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s6
; GFX10-NEXT: v_add_co_u32 v6, s0, v7, v14 ; GFX10-NEXT: v_add_co_u32 v6, s6, v7, v14
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s6
; GFX10-NEXT: v_add_co_u32 v9, s0, v9, v10 ; GFX10-NEXT: v_add_co_u32 v9, s6, v9, v10
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s6
; GFX10-NEXT: v_add_nc_u32_e32 v5, v12, v5 ; GFX10-NEXT: v_add_nc_u32_e32 v5, v12, v5
; GFX10-NEXT: v_add_co_u32 v10, s0, v11, v17 ; GFX10-NEXT: v_add_co_u32 v10, s6, v11, v17
; GFX10-NEXT: v_mul_hi_u32 v4, v2, v4 ; GFX10-NEXT: v_mul_hi_u32 v4, v2, v4
; GFX10-NEXT: v_add_nc_u32_e32 v9, v15, v9 ; GFX10-NEXT: v_add_nc_u32_e32 v9, v15, v9
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 1, s6
; GFX10-NEXT: v_add_co_u32 v5, s0, v6, v5 ; GFX10-NEXT: v_add_co_u32 v5, s6, v6, v5
; GFX10-NEXT: v_add_nc_u32_e32 v7, v13, v7 ; GFX10-NEXT: v_add_nc_u32_e32 v7, v13, v7
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s6
; GFX10-NEXT: v_mul_hi_u32 v8, v3, v8 ; GFX10-NEXT: v_mul_hi_u32 v8, v3, v8
; GFX10-NEXT: v_add_co_u32 v9, s0, v10, v9 ; GFX10-NEXT: v_add_co_u32 v9, s6, v10, v9
; GFX10-NEXT: v_add_nc_u32_e32 v11, v16, v11 ; GFX10-NEXT: v_add_nc_u32_e32 v11, v16, v11
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s6
; GFX10-NEXT: v_add3_u32 v4, v7, v6, v4 ; GFX10-NEXT: v_add3_u32 v4, v7, v6, v4
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v5 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v5
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x10 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX10-NEXT: v_add3_u32 v5, v11, v10, v8 ; GFX10-NEXT: v_add3_u32 v5, v11, v10, v8
; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v2, v4, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v2, v4, vcc_lo
; GFX10-NEXT: v_add_co_u32 v1, vcc_lo, v1, v9 ; GFX10-NEXT: v_add_co_u32 v1, vcc_lo, v1, v9
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v3, v5, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v3, v5, vcc_lo
; GFX10-NEXT: v_mul_lo_u32 v6, s7, v0 ; GFX10-NEXT: v_mul_lo_u32 v6, s1, v0
; GFX10-NEXT: v_mul_hi_u32 v7, s6, v0 ; GFX10-NEXT: v_mul_hi_u32 v7, s0, v0
; GFX10-NEXT: v_mul_lo_u32 v5, s6, v2 ; GFX10-NEXT: v_mul_lo_u32 v5, s0, v2
; GFX10-NEXT: v_mul_lo_u32 v9, s13, v1 ; GFX10-NEXT: v_mul_lo_u32 v9, s3, v1
; GFX10-NEXT: v_mul_hi_u32 v10, s12, v1 ; GFX10-NEXT: v_mul_hi_u32 v10, s2, v1
; GFX10-NEXT: v_mul_lo_u32 v11, s12, v3 ; GFX10-NEXT: v_mul_lo_u32 v11, s2, v3
; GFX10-NEXT: v_mul_lo_u32 v4, s6, v0 ; GFX10-NEXT: v_mul_lo_u32 v4, s0, v0
; GFX10-NEXT: v_mul_lo_u32 v8, s12, v1 ; GFX10-NEXT: v_mul_lo_u32 v8, s2, v1
; GFX10-NEXT: v_add3_u32 v5, v6, v5, v7 ; GFX10-NEXT: v_add3_u32 v5, v6, v5, v7
; GFX10-NEXT: v_add3_u32 v9, v9, v11, v10 ; GFX10-NEXT: v_add3_u32 v9, v9, v11, v10
; GFX10-NEXT: v_mul_lo_u32 v12, v2, v4 ; GFX10-NEXT: v_mul_lo_u32 v12, v2, v4
; GFX10-NEXT: v_mul_lo_u32 v10, v0, v5 ; GFX10-NEXT: v_mul_lo_u32 v10, v0, v5
; GFX10-NEXT: v_mul_hi_u32 v13, v0, v4 ; GFX10-NEXT: v_mul_hi_u32 v13, v0, v4
; GFX10-NEXT: v_mul_hi_u32 v4, v2, v4 ; GFX10-NEXT: v_mul_hi_u32 v4, v2, v4
; GFX10-NEXT: v_mul_lo_u32 v11, v2, v5 ; GFX10-NEXT: v_mul_lo_u32 v11, v2, v5
; GFX10-NEXT: v_mul_lo_u32 v6, v3, v8 ; GFX10-NEXT: v_mul_lo_u32 v6, v3, v8
; GFX10-NEXT: v_mul_lo_u32 v15, v1, v9 ; GFX10-NEXT: v_mul_lo_u32 v15, v1, v9
; GFX10-NEXT: v_mul_hi_u32 v7, v1, v8 ; GFX10-NEXT: v_mul_hi_u32 v7, v1, v8
; GFX10-NEXT: v_mul_hi_u32 v8, v3, v8 ; GFX10-NEXT: v_mul_hi_u32 v8, v3, v8
; GFX10-NEXT: v_add_co_u32 v10, s6, v12, v10 ; GFX10-NEXT: v_add_co_u32 v10, s0, v12, v10
; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, 1, s6 ; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v4, s6, v11, v4 ; GFX10-NEXT: v_add_co_u32 v4, s0, v11, v4
; GFX10-NEXT: v_mul_lo_u32 v16, v3, v9 ; GFX10-NEXT: v_mul_lo_u32 v16, v3, v9
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 1, s6 ; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v6, s6, v6, v15 ; GFX10-NEXT: v_add_co_u32 v6, s0, v6, v15
; GFX10-NEXT: v_mul_hi_u32 v14, v0, v5 ; GFX10-NEXT: v_mul_hi_u32 v14, v0, v5
; GFX10-NEXT: v_cndmask_b32_e64 v15, 0, 1, s6 ; GFX10-NEXT: v_cndmask_b32_e64 v15, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v10, s6, v10, v13 ; GFX10-NEXT: v_add_co_u32 v10, s0, v10, v13
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s6 ; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v8, s6, v16, v8 ; GFX10-NEXT: v_add_co_u32 v8, s0, v16, v8
; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, 1, s6 ; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v4, s6, v4, v14 ; GFX10-NEXT: v_add_co_u32 v4, s0, v4, v14
; GFX10-NEXT: v_add_nc_u32_e32 v10, v12, v10 ; GFX10-NEXT: v_add_nc_u32_e32 v10, v12, v10
; GFX10-NEXT: v_cndmask_b32_e64 v14, 0, 1, s6 ; GFX10-NEXT: v_cndmask_b32_e64 v14, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v6, s6, v6, v7 ; GFX10-NEXT: v_add_co_u32 v6, s0, v6, v7
; GFX10-NEXT: v_mul_hi_u32 v5, v2, v5 ; GFX10-NEXT: v_mul_hi_u32 v5, v2, v5
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s6 ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v4, s6, v4, v10 ; GFX10-NEXT: v_add_co_u32 v4, s0, v4, v10
; GFX10-NEXT: v_add_nc_u32_e32 v7, v11, v14 ; GFX10-NEXT: v_add_nc_u32_e32 v7, v11, v14
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s6 ; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
; GFX10-NEXT: v_mul_hi_u32 v17, v1, v9 ; GFX10-NEXT: v_mul_hi_u32 v17, v1, v9
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4
; GFX10-NEXT: v_add_nc_u32_e32 v6, v15, v6 ; GFX10-NEXT: v_add_nc_u32_e32 v6, v15, v6
; GFX10-NEXT: v_add3_u32 v5, v7, v10, v5 ; GFX10-NEXT: v_add3_u32 v5, v7, v10, v5
; GFX10-NEXT: v_mul_hi_u32 v9, v3, v9 ; GFX10-NEXT: v_mul_hi_u32 v9, v3, v9
; GFX10-NEXT: v_mov_b32_e32 v10, 0 ; GFX10-NEXT: v_mul_hi_u32 v10, s9, v0
; GFX10-NEXT: v_add_co_u32 v8, s6, v8, v17 ; GFX10-NEXT: v_mov_b32_e32 v12, 0
; GFX10-NEXT: v_add_co_u32 v8, s0, v8, v17
; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v2, v5, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v2, v5, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 1, s6 ; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v4, s12, v8, v6 ; GFX10-NEXT: v_add_co_u32 v4, s0, v8, v6
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: v_mul_lo_u32 v6, s9, v0
; GFX10-NEXT: v_mul_lo_u32 v6, s1, v0 ; GFX10-NEXT: v_mul_lo_u32 v8, s8, v2
; GFX10-NEXT: v_mul_lo_u32 v8, s0, v2 ; GFX10-NEXT: v_mul_hi_u32 v0, s8, v0
; GFX10-NEXT: v_add_nc_u32_e32 v7, v13, v11 ; GFX10-NEXT: v_add_nc_u32_e32 v7, v13, v11
; GFX10-NEXT: v_mul_hi_u32 v11, s1, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0
; GFX10-NEXT: v_mul_hi_u32 v0, s0, v0 ; GFX10-NEXT: v_mul_lo_u32 v11, s9, v2
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s12
; GFX10-NEXT: v_mul_lo_u32 v12, s1, v2
; GFX10-NEXT: v_add_co_u32 v1, vcc_lo, v1, v4 ; GFX10-NEXT: v_add_co_u32 v1, vcc_lo, v1, v4
; GFX10-NEXT: v_add_co_u32 v6, s12, v6, v8 ; GFX10-NEXT: v_add_co_u32 v6, s0, v6, v8
; GFX10-NEXT: v_add3_u32 v5, v7, v5, v9 ; GFX10-NEXT: v_add3_u32 v5, v7, v5, v9
; GFX10-NEXT: v_mul_hi_u32 v7, s0, v2 ; GFX10-NEXT: v_mul_hi_u32 v7, s8, v2
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s12 ; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v0, s13, v6, v0 ; GFX10-NEXT: v_add_co_u32 v0, s1, v6, v0
; GFX10-NEXT: v_add_co_u32 v9, s12, v12, v11 ; GFX10-NEXT: v_add_co_u32 v9, s0, v11, v10
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s13 ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s1
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s12 ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0
; GFX10-NEXT: v_mul_hi_u32 v2, s1, v2 ; GFX10-NEXT: v_mul_hi_u32 v2, s9, v2
; GFX10-NEXT: v_add_co_u32 v7, s12, v9, v7 ; GFX10-NEXT: v_add_co_u32 v7, s0, v9, v7
; GFX10-NEXT: v_add_nc_u32_e32 v0, v8, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v0, v8, v0
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s12 ; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v3, v5, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v3, v5, vcc_lo
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0 ; GFX10-NEXT: v_add_co_u32 v0, s0, v7, v0
; GFX10-NEXT: v_add_co_u32 v0, s12, v7, v0
; GFX10-NEXT: v_add_nc_u32_e32 v4, v6, v9 ; GFX10-NEXT: v_add_nc_u32_e32 v4, v6, v9
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s12 ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0
; GFX10-NEXT: v_mul_lo_u32 v6, s3, v1 ; GFX10-NEXT: v_mul_lo_u32 v6, s11, v1
; GFX10-NEXT: v_mul_lo_u32 v8, s2, v3 ; GFX10-NEXT: v_mul_lo_u32 v8, s10, v3
; GFX10-NEXT: v_mul_lo_u32 v9, s9, v0 ; GFX10-NEXT: v_mul_lo_u32 v9, s13, v0
; GFX10-NEXT: v_mul_hi_u32 v11, s8, v0 ; GFX10-NEXT: v_mul_hi_u32 v10, s12, v0
; GFX10-NEXT: v_add3_u32 v2, v4, v5, v2 ; GFX10-NEXT: v_add3_u32 v2, v4, v5, v2
; GFX10-NEXT: v_mul_hi_u32 v7, s2, v1 ; GFX10-NEXT: v_mul_hi_u32 v7, s10, v1
; GFX10-NEXT: v_mul_lo_u32 v13, s8, v0 ; GFX10-NEXT: v_mul_hi_u32 v1, s11, v1
; GFX10-NEXT: v_mul_hi_u32 v1, s3, v1 ; GFX10-NEXT: v_mul_lo_u32 v4, s11, v3
; GFX10-NEXT: v_mul_lo_u32 v4, s3, v3 ; GFX10-NEXT: v_mul_lo_u32 v13, s12, v0
; GFX10-NEXT: v_mul_lo_u32 v12, s8, v2 ; GFX10-NEXT: v_mul_lo_u32 v11, s12, v2
; GFX10-NEXT: v_add_co_u32 v6, s12, v6, v8 ; GFX10-NEXT: v_add_co_u32 v6, s0, v6, v8
; GFX10-NEXT: v_mul_hi_u32 v5, s2, v3 ; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s12 ; GFX10-NEXT: v_mul_hi_u32 v5, s10, v3
; GFX10-NEXT: v_mul_hi_u32 v3, s3, v3 ; GFX10-NEXT: v_mul_hi_u32 v3, s11, v3
; GFX10-NEXT: v_add_co_u32 v1, s12, v4, v1 ; GFX10-NEXT: v_add_co_u32 v1, s0, v4, v1
; GFX10-NEXT: v_add3_u32 v9, v9, v12, v11 ; GFX10-NEXT: v_add3_u32 v9, v9, v11, v10
; GFX10-NEXT: v_sub_co_u32 v11, vcc_lo, s0, v13 ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
; GFX10-NEXT: v_sub_co_u32 v10, vcc_lo, s8, v13
; GFX10-NEXT: v_add_co_u32 v6, s0, v6, v7 ; GFX10-NEXT: v_add_co_u32 v6, s0, v6, v7
; GFX10-NEXT: v_sub_nc_u32_e32 v7, s1, v9 ; GFX10-NEXT: v_sub_nc_u32_e32 v7, s9, v9
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0
; GFX10-NEXT: v_sub_co_ci_u32_e64 v9, s0, s1, v9, vcc_lo ; GFX10-NEXT: v_sub_co_ci_u32_e64 v9, s0, s9, v9, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s8, v11 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s12, v10
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v7, vcc_lo, s13, v7, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s9, v9 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s13, v9
; GFX10-NEXT: v_add_nc_u32_e32 v6, v8, v6 ; GFX10-NEXT: v_add_nc_u32_e32 v6, v8, v6
; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, -1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, -1, s0
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s12
; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, -1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, -1, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v14, vcc_lo, v11, s8 ; GFX10-NEXT: v_sub_co_u32 v14, vcc_lo, v10, s12
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v15, s0, 0, v7, vcc_lo ; GFX10-NEXT: v_subrev_co_ci_u32_e64 v15, s0, 0, v7, vcc_lo
; GFX10-NEXT: v_add_co_u32 v1, s0, v1, v5 ; GFX10-NEXT: v_add_co_u32 v1, s0, v1, v5
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s9, v9 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s13, v9
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v7, vcc_lo, s13, v7, vcc_lo
; GFX10-NEXT: v_add_nc_u32_e32 v4, v4, v5 ; GFX10-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX10-NEXT: v_cndmask_b32_e64 v12, v13, v12, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v11, v13, v11, s0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s9, v15 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s13, v15
; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, -1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, -1, s0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s8, v14 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s12, v14
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, -1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, -1, s0
; GFX10-NEXT: v_add_co_u32 v6, s0, v1, v6 ; GFX10-NEXT: v_add_co_u32 v6, s0, v1, v6
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v5, s0, v0, 1 ; GFX10-NEXT: v_add_co_u32 v5, s0, v0, 1
; GFX10-NEXT: v_add_co_ci_u32_e64 v16, s0, 0, v2, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v16, s0, 0, v2, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s9, v15 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s13, v15
; GFX10-NEXT: v_add3_u32 v3, v4, v1, v3 ; GFX10-NEXT: v_add3_u32 v3, v4, v1, v3
; GFX10-NEXT: v_mul_hi_u32 v18, s10, v6 ; GFX10-NEXT: v_mul_hi_u32 v18, s14, v6
; GFX10-NEXT: v_cndmask_b32_e64 v8, v13, v8, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v8, v13, v8, s0
; GFX10-NEXT: v_mul_lo_u32 v13, s11, v6 ; GFX10-NEXT: v_mul_lo_u32 v13, s15, v6
; GFX10-NEXT: v_mul_lo_u32 v17, s10, v3 ; GFX10-NEXT: v_mul_lo_u32 v17, s14, v3
; GFX10-NEXT: v_add_co_u32 v1, s0, v5, 1 ; GFX10-NEXT: v_add_co_u32 v1, s0, v5, 1
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; GFX10-NEXT: v_add_co_ci_u32_e64 v4, s0, 0, v16, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v4, s0, 0, v16, s0
; GFX10-NEXT: v_sub_co_u32 v19, s0, v14, s8 ; GFX10-NEXT: v_sub_co_u32 v19, s0, v14, s12
; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX10-NEXT: v_mul_lo_u32 v5, s10, v6 ; GFX10-NEXT: v_mul_lo_u32 v5, s14, v6
; GFX10-NEXT: v_cndmask_b32_e32 v4, v16, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v4, v16, v4, vcc_lo
; GFX10-NEXT: v_add3_u32 v13, v13, v17, v18 ; GFX10-NEXT: v_add3_u32 v13, v13, v17, v18
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v11
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v7, s0, 0, v7, s0 ; GFX10-NEXT: v_subrev_co_ci_u32_e64 v7, s0, 0, v7, s0
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
; GFX10-NEXT: v_sub_nc_u32_e32 v2, s3, v13 ; GFX10-NEXT: v_sub_nc_u32_e32 v2, s11, v13
; GFX10-NEXT: v_sub_co_u32 v12, s0, s2, v5 ; GFX10-NEXT: v_sub_co_u32 v11, s0, s10, v5
; GFX10-NEXT: v_sub_co_ci_u32_e64 v16, s1, s3, v13, s0 ; GFX10-NEXT: v_sub_co_ci_u32_e64 v16, s1, s11, v13, s0
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v2, s0, s11, v2, s0 ; GFX10-NEXT: v_subrev_co_ci_u32_e64 v2, s0, s15, v2, s0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s10, v12 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s14, v11
; GFX10-NEXT: v_cmp_ne_u32_e64 s1, 0, v8 ; GFX10-NEXT: v_cmp_ne_u32_e64 s1, 0, v8
; GFX10-NEXT: v_cmp_le_u32_e64 s2, s11, v16 ; GFX10-NEXT: v_cmp_le_u32_e64 s2, s15, v16
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, -1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, -1, s0
; GFX10-NEXT: v_sub_co_u32 v13, s0, v12, s10 ; GFX10-NEXT: v_sub_co_u32 v13, s0, v11, s14
; GFX10-NEXT: v_cndmask_b32_e64 v4, v14, v19, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v4, v14, v19, s1
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, -1, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, -1, s2
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v14, s2, 0, v2, s0 ; GFX10-NEXT: v_subrev_co_ci_u32_e64 v14, s2, 0, v2, s0
; GFX10-NEXT: v_cndmask_b32_e64 v7, v15, v7, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v15, v7, s1
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, s11, v16 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, s15, v16
; GFX10-NEXT: v_cndmask_b32_e32 v4, v11, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v4, v10, v4, vcc_lo
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v2, s0, s11, v2, s0 ; GFX10-NEXT: v_subrev_co_ci_u32_e64 v2, s0, s15, v2, s0
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v8, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v8, s1
; GFX10-NEXT: v_cmp_le_u32_e64 s1, s11, v14 ; GFX10-NEXT: v_cmp_le_u32_e64 s1, s15, v14
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, -1, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, -1, s1
; GFX10-NEXT: v_cmp_le_u32_e64 s1, s10, v13 ; GFX10-NEXT: v_cmp_le_u32_e64 s1, s14, v13
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, -1, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, -1, s1
; GFX10-NEXT: v_add_co_u32 v15, s1, v6, 1 ; GFX10-NEXT: v_add_co_u32 v15, s1, v6, 1
; GFX10-NEXT: v_add_co_ci_u32_e64 v17, s1, 0, v3, s1 ; GFX10-NEXT: v_add_co_ci_u32_e64 v17, s1, 0, v3, s1
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, s11, v14 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, s15, v14
; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v11, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v10, s1
; GFX10-NEXT: v_add_co_u32 v11, s1, v15, 1 ; GFX10-NEXT: v_add_co_u32 v10, s1, v15, 1
; GFX10-NEXT: v_add_co_ci_u32_e64 v18, s1, 0, v17, s1 ; GFX10-NEXT: v_add_co_ci_u32_e64 v18, s1, 0, v17, s1
; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v8 ; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v8
; GFX10-NEXT: v_sub_co_u32 v8, s1, v13, s10 ; GFX10-NEXT: v_sub_co_u32 v8, s1, v13, s14
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v2, s1, 0, v2, s1 ; GFX10-NEXT: v_subrev_co_ci_u32_e64 v2, s1, 0, v2, s1
; GFX10-NEXT: v_cndmask_b32_e64 v11, v15, v11, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v10, v15, v10, s0
; GFX10-NEXT: v_cndmask_b32_e64 v15, v17, v18, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v15, v17, v18, s0
; GFX10-NEXT: v_cmp_ne_u32_e64 s1, 0, v5 ; GFX10-NEXT: v_cmp_ne_u32_e64 s1, 0, v5
; GFX10-NEXT: v_cndmask_b32_e64 v8, v13, v8, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v8, v13, v8, s0
; GFX10-NEXT: v_cndmask_b32_e64 v13, v14, v2, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v13, v14, v2, s0
; GFX10-NEXT: v_cndmask_b32_e32 v5, v9, v7, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v5, v9, v7, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v11, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v10, s1
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v15, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v15, s1
; GFX10-NEXT: v_cndmask_b32_e64 v6, v12, v8, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v11, v8, s1
; GFX10-NEXT: v_cndmask_b32_e64 v7, v16, v13, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v16, v13, s1
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_store_dwordx4 v10, v[0:3], s[4:5] ; GFX10-NEXT: global_store_dwordx4 v12, v[0:3], s[4:5]
; GFX10-NEXT: global_store_dwordx4 v10, v[4:7], s[6:7] ; GFX10-NEXT: global_store_dwordx4 v12, v[4:7], s[6:7]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%div = udiv <2 x i64> %x, %y %div = udiv <2 x i64> %x, %y
store <2 x i64> %div, <2 x i64> addrspace(1)* %out0 store <2 x i64> %div, <2 x i64> addrspace(1)* %out0
%rem = urem <2 x i64> %x, %y %rem = urem <2 x i64> %x, %y
store <2 x i64> %rem, <2 x i64> addrspace(1)* %out1 store <2 x i64> %rem, <2 x i64> addrspace(1)* %out1
ret void ret void
} }
▲ Show 20 Lines • Show All 418 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_endpgm
%rem = urem i16 %x, %y %rem = urem i16 %x, %y
store i16 %rem, i16 addrspace(1)* %out1 store i16 %rem, i16 addrspace(1)* %out1
ret void ret void
} }
define amdgpu_kernel void @udivrem_v2i16(<2 x i16> addrspace(1)* %out0, <2 x i16> addrspace(1)* %out1, <2 x i16> %x, <2 x i16> %y) { define amdgpu_kernel void @udivrem_v2i16(<2 x i16> addrspace(1)* %out0, <2 x i16> addrspace(1)* %out1, <2 x i16> %x, <2 x i16> %y) {
; GFX8-LABEL: udivrem_v2i16: ; GFX8-LABEL: udivrem_v2i16:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dword s0, s[4:5], 0x14 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x10
; GFX8-NEXT: s_mov_b32 s2, 0xffff ; GFX8-NEXT: s_mov_b32 s2, 0xffff
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_and_b32 s6, s0, s2 ; GFX8-NEXT: s_and_b32 s3, s1, s2
; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s6 ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s3
; GFX8-NEXT: s_lshr_b32 s3, s0, 16 ; GFX8-NEXT: s_lshr_b32 s8, s1, 16
; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s3 ; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s8
; GFX8-NEXT: s_sub_i32 s1, 0, s6 ; GFX8-NEXT: s_sub_i32 s1, 0, s3
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX8-NEXT: s_lshr_b32 s9, s0, 16
; GFX8-NEXT: s_load_dword s0, s[4:5], 0x10
; GFX8-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX8-NEXT: s_and_b32 s0, s0, s2
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 ; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_lshr_b32 s4, s0, 16
; GFX8-NEXT: v_mul_lo_u32 v2, s1, v0 ; GFX8-NEXT: v_mul_lo_u32 v2, s1, v0
; GFX8-NEXT: s_sub_i32 s1, 0, s3 ; GFX8-NEXT: s_sub_i32 s1, 0, s8
; GFX8-NEXT: s_and_b32 s0, s0, s2
; GFX8-NEXT: v_mul_lo_u32 v3, s1, v1 ; GFX8-NEXT: v_mul_lo_u32 v3, s1, v1
; GFX8-NEXT: v_mul_hi_u32 v2, v0, v2 ; GFX8-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX8-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX8-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0 ; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v3 ; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v3
; GFX8-NEXT: v_mul_hi_u32 v1, s4, v1 ; GFX8-NEXT: v_mul_hi_u32 v1, s9, v1
; GFX8-NEXT: v_mul_lo_u32 v2, v0, s6 ; GFX8-NEXT: v_mul_lo_u32 v2, v0, s3
; GFX8-NEXT: v_add_u32_e32 v3, vcc, 1, v0 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, 1, v0
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s0, v2 ; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s0, v2
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s6, v2 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s3, v2
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX8-NEXT: v_subrev_u32_e64 v3, s[0:1], s6, v2 ; GFX8-NEXT: v_subrev_u32_e64 v3, s[0:1], s3, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX8-NEXT: v_add_u32_e32 v3, vcc, 1, v0 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, 1, v0
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s6, v2 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s3, v2
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX8-NEXT: v_mul_lo_u32 v3, v1, s3 ; GFX8-NEXT: v_mul_lo_u32 v3, v1, s8
; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s6, v2 ; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s3, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s4, v3 ; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s9, v3
; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v1 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v1
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s3, v3 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s8, v3
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s3, v3 ; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s8, v3
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v1 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v1
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s3, v3 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s8, v3
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s3, v3 ; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s8, v3
; GFX8-NEXT: v_and_b32_e32 v1, s2, v1 ; GFX8-NEXT: v_and_b32_e32 v1, s2, v1
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX8-NEXT: v_or_b32_sdwa v4, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_or_b32_sdwa v4, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: v_and_b32_e32 v0, s2, v3 ; GFX8-NEXT: v_and_b32_e32 v0, s2, v3
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0 ; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX8-NEXT: v_or_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_or_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: v_mov_b32_e32 v0, s8 ; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s9 ; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: flat_store_dword v[0:1], v4 ; GFX8-NEXT: flat_store_dword v[0:1], v4
; GFX8-NEXT: v_mov_b32_e32 v0, s10 ; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: v_mov_b32_e32 v1, s11 ; GFX8-NEXT: v_mov_b32_e32 v1, s7
; GFX8-NEXT: flat_store_dword v[0:1], v2 ; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-LABEL: udivrem_v2i16: ; GFX9-LABEL: udivrem_v2i16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dword s0, s[4:5], 0x14 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x10
; GFX9-NEXT: s_mov_b32 s1, 0xffff ; GFX9-NEXT: s_mov_b32 s2, 0xffff
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_and_b32 s7, s0, s1 ; GFX9-NEXT: s_and_b32 s7, s1, s2
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s7 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s7
; GFX9-NEXT: s_lshr_b32 s6, s0, 16 ; GFX9-NEXT: s_lshr_b32 s6, s1, 16
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s6 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s6
; GFX9-NEXT: s_sub_i32 s2, 0, s7 ; GFX9-NEXT: s_sub_i32 s1, 0, s7
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: s_load_dword s0, s[4:5], 0x10
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX9-NEXT: s_sub_i32 s3, 0, s6 ; GFX9-NEXT: s_sub_i32 s3, 0, s6
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX9-NEXT: s_and_b32 s9, s0, s2
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_and_b32 s9, s0, s1
; GFX9-NEXT: v_mul_lo_u32 v2, s2, v0
; GFX9-NEXT: s_lshr_b32 s8, s0, 16 ; GFX9-NEXT: s_lshr_b32 s8, s0, 16
; GFX9-NEXT: v_mul_lo_u32 v2, s1, v0
; GFX9-NEXT: v_mul_lo_u32 v3, s3, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, s3, v1
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX9-NEXT: v_add_u32_e32 v0, v0, v2 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v0, s9, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s9, v0
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_mul_hi_u32 v1, s8, v1 ; GFX9-NEXT: v_mul_hi_u32 v1, s8, v1
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; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dword v2, v0, s[0:1] ; GFX9-NEXT: global_store_dword v2, v0, s[0:1]
; GFX9-NEXT: global_store_dword v2, v1, s[2:3] ; GFX9-NEXT: global_store_dword v2, v1, s[2:3]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: udivrem_v2i16: ; GFX10-LABEL: udivrem_v2i16:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dword s0, s[4:5], 0x14 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x10
; GFX10-NEXT: s_mov_b32 s2, 0xffff ; GFX10-NEXT: s_mov_b32 s3, 0xffff
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_lshr_b32 s1, s0, 16 ; GFX10-NEXT: s_lshr_b32 s2, s1, 16
; GFX10-NEXT: s_and_b32 s3, s0, s2 ; GFX10-NEXT: s_and_b32 s1, s1, s3
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s1 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s3 ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s1
; GFX10-NEXT: s_sub_i32 s6, 0, s1 ; GFX10-NEXT: s_sub_i32 s6, 0, s2
; GFX10-NEXT: s_load_dword s0, s[4:5], 0x10
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 ; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX10-NEXT: v_mul_lo_u32 v2, s6, v0 ; GFX10-NEXT: v_mul_lo_u32 v2, s6, v0
; GFX10-NEXT: s_sub_i32 s6, 0, s3 ; GFX10-NEXT: s_sub_i32 s6, 0, s1
; GFX10-NEXT: v_mul_lo_u32 v3, s6, v1 ; GFX10-NEXT: v_mul_lo_u32 v3, s6, v1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_lshr_b32 s6, s0, 16 ; GFX10-NEXT: s_lshr_b32 s6, s0, 16
; GFX10-NEXT: s_and_b32 s0, s0, s2 ; GFX10-NEXT: s_and_b32 s0, s0, s3
; GFX10-NEXT: v_mul_hi_u32 v2, v0, v2 ; GFX10-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX10-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX10-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2 ; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2
; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v3 ; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v3
; GFX10-NEXT: v_mul_hi_u32 v0, s6, v0 ; GFX10-NEXT: v_mul_hi_u32 v0, s6, v0
; GFX10-NEXT: v_mul_hi_u32 v1, s0, v1 ; GFX10-NEXT: v_mul_hi_u32 v1, s0, v1
; GFX10-NEXT: v_mul_lo_u32 v2, v0, s1 ; GFX10-NEXT: v_mul_lo_u32 v2, v0, s2
; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v0
; GFX10-NEXT: v_mul_lo_u32 v3, v1, s3 ; GFX10-NEXT: v_mul_lo_u32 v3, v1, s1
; GFX10-NEXT: v_add_nc_u32_e32 v6, 1, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v6, 1, v1
; GFX10-NEXT: v_sub_nc_u32_e32 v2, s6, v2 ; GFX10-NEXT: v_sub_nc_u32_e32 v2, s6, v2
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX10-NEXT: v_sub_nc_u32_e32 v3, s0, v3 ; GFX10-NEXT: v_sub_nc_u32_e32 v3, s0, v3
; GFX10-NEXT: v_subrev_nc_u32_e32 v5, s1, v2 ; GFX10-NEXT: v_subrev_nc_u32_e32 v5, s2, v2
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s1, v2 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v2
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s3, v3 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s1, v3
; GFX10-NEXT: v_subrev_nc_u32_e32 v7, s3, v3 ; GFX10-NEXT: v_subrev_nc_u32_e32 v7, s1, v3
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v6, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v6, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v7, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v7, s0
; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v0
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s1, v2 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v2
; GFX10-NEXT: v_subrev_nc_u32_e32 v5, s1, v2 ; GFX10-NEXT: v_subrev_nc_u32_e32 v5, s2, v2
; GFX10-NEXT: v_add_nc_u32_e32 v6, 1, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v6, 1, v1
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s3, v3 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s1, v3
; GFX10-NEXT: v_subrev_nc_u32_e32 v7, s3, v3 ; GFX10-NEXT: v_subrev_nc_u32_e32 v7, s1, v3
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff ; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v6, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v6, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v7, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v7, s0
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX10-NEXT: v_and_or_b32 v0, v1, v4, v0 ; GFX10-NEXT: v_and_or_b32 v0, v1, v4, v0
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llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll

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; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; GFX6-LABEL: udiv_v4i16: ; GFX6-LABEL: udiv_v4i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb ; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GFX6-NEXT: s_mov_b32 s8, 0xffff ; GFX6-NEXT: s_mov_b32 s8, 0xffff
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_and_b32 s9, s6, s8 ; GFX6-NEXT: s_and_b32 s2, s6, s8
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s9 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX6-NEXT: s_lshr_b32 s9, s4, 16 ; GFX6-NEXT: s_and_b32 s9, s4, s8
; GFX6-NEXT: s_and_b32 s4, s4, s8
; GFX6-NEXT: s_lshr_b32 s6, s6, 16 ; GFX6-NEXT: s_lshr_b32 s6, s6, 16
; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s4 ; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s9
; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0
; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s6 ; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s6
; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s9 ; GFX6-NEXT: s_lshr_b32 s4, s4, 16
; GFX6-NEXT: s_and_b32 s6, s7, s8 ; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s4
; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2 ; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2
; GFX6-NEXT: v_rcp_iflag_f32_e32 v5, v3 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v5, v3
; GFX6-NEXT: v_trunc_f32_e32 v2, v2 ; GFX6-NEXT: v_trunc_f32_e32 v2, v2
; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
; GFX6-NEXT: v_mul_f32_e32 v1, v4, v5 ; GFX6-NEXT: v_mul_f32_e32 v1, v4, v5
; GFX6-NEXT: v_trunc_f32_e32 v1, v1 ; GFX6-NEXT: v_trunc_f32_e32 v1, v1
; GFX6-NEXT: s_and_b32 s4, s7, s8
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
; GFX6-NEXT: v_mad_f32 v2, -v1, v3, v4 ; GFX6-NEXT: v_mad_f32 v2, -v1, v3, v4
; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s6 ; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s4
; GFX6-NEXT: s_lshr_b32 s4, s5, 16 ; GFX6-NEXT: s_and_b32 s4, s5, s8
; GFX6-NEXT: s_lshr_b32 s10, s7, 16
; GFX6-NEXT: s_and_b32 s5, s5, s8
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: v_cvt_f32_u32_e32 v5, s5 ; GFX6-NEXT: v_cvt_f32_u32_e32 v5, s4
; GFX6-NEXT: v_rcp_iflag_f32_e32 v6, v4 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v6, v4
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v3 ; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v3
; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s10
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v1, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v1, vcc
; GFX6-NEXT: v_mul_f32_e32 v1, v5, v6 ; GFX6-NEXT: v_mul_f32_e32 v1, v5, v6
; GFX6-NEXT: v_cvt_f32_u32_e32 v6, s4
; GFX6-NEXT: v_rcp_iflag_f32_e32 v7, v3
; GFX6-NEXT: v_trunc_f32_e32 v1, v1 ; GFX6-NEXT: v_trunc_f32_e32 v1, v1
; GFX6-NEXT: v_mad_f32 v5, -v1, v4, v5 ; GFX6-NEXT: s_lshr_b32 s4, s7, 16
; GFX6-NEXT: v_mad_f32 v3, -v1, v4, v5
; GFX6-NEXT: v_cvt_f32_u32_e32 v5, s4
; GFX6-NEXT: s_lshr_b32 s4, s5, 16
; GFX6-NEXT: v_cvt_f32_u32_e32 v6, s4
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v5|, v4 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v7, v5
; GFX6-NEXT: v_mul_f32_e32 v4, v6, v7 ; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v4
; GFX6-NEXT: v_trunc_f32_e32 v4, v4 ; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_cvt_u32_f32_e32 v5, v4
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX6-NEXT: v_mad_f32 v4, -v4, v3, v6 ; GFX6-NEXT: v_mul_f32_e32 v3, v6, v7
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, v3 ; GFX6-NEXT: v_trunc_f32_e32 v3, v3
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc ; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; GFX6-NEXT: v_mad_f32 v3, -v3, v5, v6
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v5
; GFX6-NEXT: v_and_b32_e32 v1, s8, v1 ; GFX6-NEXT: v_and_b32_e32 v1, s8, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_and_b32_e32 v0, s8, v0 ; GFX6-NEXT: v_and_b32_e32 v0, s8, v0
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: v_or_b32_e32 v1, v1, v3 ; GFX6-NEXT: v_or_b32_e32 v1, v1, v3
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: udiv_v4i16: ; GFX9-LABEL: udiv_v4i16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX9-NEXT: s_mov_b32 s0, 0xffff ; GFX9-NEXT: s_mov_b32 s0, 0xffff
; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_and_b32 s8, s6, s0 ; GFX9-NEXT: s_and_b32 s8, s6, s0
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s8 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s8
; GFX9-NEXT: s_lshr_b32 s6, s6, 16
; GFX9-NEXT: s_and_b32 s1, s4, s0
; GFX9-NEXT: v_cvt_f32_u32_e32 v3, s6
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s1
; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v0
; GFX9-NEXT: s_lshr_b32 s1, s4, 16 ; GFX9-NEXT: s_lshr_b32 s1, s4, 16
; GFX9-NEXT: s_and_b32 s4, s4, s0
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s4
; GFX9-NEXT: s_lshr_b32 s4, s6, 16
; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v0
; GFX9-NEXT: v_cvt_f32_u32_e32 v4, s4
; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s1 ; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s1
; GFX9-NEXT: s_and_b32 s1, s7, s0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v3
; GFX9-NEXT: v_mul_f32_e32 v3, v1, v3 ; GFX9-NEXT: v_mul_f32_e32 v4, v1, v4
; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v4 ; GFX9-NEXT: v_trunc_f32_e32 v4, v4
; GFX9-NEXT: v_trunc_f32_e32 v3, v3 ; GFX9-NEXT: v_mad_f32 v1, -v4, v0, v1
; GFX9-NEXT: v_mad_f32 v1, -v3, v0, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
; GFX9-NEXT: v_mul_f32_e32 v1, v5, v6 ; GFX9-NEXT: v_mul_f32_e32 v1, v5, v6
; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v3, vcc ; GFX9-NEXT: s_and_b32 s1, s7, s0
; GFX9-NEXT: v_mad_f32 v3, -v1, v4, v5 ; GFX9-NEXT: v_cvt_u32_f32_e32 v7, v4
; GFX9-NEXT: v_mad_f32 v4, -v1, v3, v5
; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s1 ; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s1
; GFX9-NEXT: s_lshr_b32 s6, s7, 16
; GFX9-NEXT: s_and_b32 s0, s5, s0 ; GFX9-NEXT: s_and_b32 s0, s5, s0
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v7, vcc
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_cvt_f32_u32_e32 v6, s0 ; GFX9-NEXT: v_cvt_f32_u32_e32 v6, s0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v7, v5 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v7, v5
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v4 ; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, v3
; GFX9-NEXT: v_cvt_f32_u32_e32 v4, s6
; GFX9-NEXT: s_lshr_b32 s8, s5, 16
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
; GFX9-NEXT: v_mul_f32_e32 v1, v6, v7 ; GFX9-NEXT: v_mul_f32_e32 v1, v6, v7
; GFX9-NEXT: v_cvt_f32_u32_e32 v7, s8
; GFX9-NEXT: v_rcp_iflag_f32_e32 v8, v4
; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1
; GFX9-NEXT: v_mad_f32 v6, -v1, v5, v6 ; GFX9-NEXT: s_lshr_b32 s0, s7, 16
; GFX9-NEXT: v_mad_f32 v4, -v1, v5, v6
; GFX9-NEXT: v_cvt_f32_u32_e32 v6, s0
; GFX9-NEXT: s_lshr_b32 s0, s5, 16
; GFX9-NEXT: v_cvt_f32_u32_e32 v7, s0
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v6|, v5 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v8, v6
; GFX9-NEXT: v_mul_f32_e32 v5, v7, v8 ; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, v5
; GFX9-NEXT: v_trunc_f32_e32 v5, v5
; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v5
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: v_mad_f32 v5, -v5, v4, v7 ; GFX9-NEXT: v_mul_f32_e32 v4, v7, v8
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v5|, v4 ; GFX9-NEXT: v_trunc_f32_e32 v4, v4
; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v4
; GFX9-NEXT: v_mad_f32 v4, -v4, v6, v7
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, v6
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
; GFX9-NEXT: v_mov_b32_e32 v5, 0xffff ; GFX9-NEXT: v_mov_b32_e32 v5, 0xffff
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v6, vcc
; GFX9-NEXT: v_and_b32_e32 v1, v5, v1 ; GFX9-NEXT: v_and_b32_e32 v1, v5, v1
; GFX9-NEXT: v_and_b32_e32 v0, v5, v0 ; GFX9-NEXT: v_and_b32_e32 v0, v5, v0
; GFX9-NEXT: v_lshl_or_b32 v1, v4, 16, v1 ; GFX9-NEXT: v_lshl_or_b32 v1, v4, 16, v1
; GFX9-NEXT: v_lshl_or_b32 v0, v3, 16, v0 ; GFX9-NEXT: v_lshl_or_b32 v0, v3, 16, v0
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%r = udiv <4 x i16> %x, %y %r = udiv <4 x i16> %x, %y
store <4 x i16> %r, <4 x i16> addrspace(1)* %out store <4 x i16> %r, <4 x i16> addrspace(1)* %out
▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; GFX6-LABEL: urem_v4i16: ; GFX6-LABEL: urem_v4i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb ; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GFX6-NEXT: s_mov_b32 s8, 0xffff ; GFX6-NEXT: s_mov_b32 s8, 0xffff
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_and_b32 s9, s6, s8 ; GFX6-NEXT: s_and_b32 s2, s6, s8
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s9 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX6-NEXT: s_and_b32 s10, s4, s8 ; GFX6-NEXT: v_mov_b32_e32 v4, s6
; GFX6-NEXT: s_lshr_b32 s11, s6, 16 ; GFX6-NEXT: v_alignbit_b32 v4, s7, v4, 16
; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s10 ; GFX6-NEXT: s_and_b32 s9, s4, s8
; GFX6-NEXT: v_and_b32_e32 v5, s8, v4
; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s9
; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0
; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s11 ; GFX6-NEXT: v_cvt_f32_u32_e32 v5, v5
; GFX6-NEXT: s_lshr_b32 s9, s4, 16 ; GFX6-NEXT: v_mov_b32_e32 v3, s4
; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s9 ; GFX6-NEXT: v_alignbit_b32 v3, s5, v3, 16
; GFX6-NEXT: v_and_b32_e32 v6, s8, v3
; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2 ; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2
; GFX6-NEXT: v_rcp_iflag_f32_e32 v5, v3 ; GFX6-NEXT: v_cvt_f32_u32_e32 v6, v6
; GFX6-NEXT: v_rcp_iflag_f32_e32 v7, v5
; GFX6-NEXT: v_trunc_f32_e32 v2, v2 ; GFX6-NEXT: v_trunc_f32_e32 v2, v2
; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
; GFX6-NEXT: v_mul_f32_e32 v1, v4, v5 ; GFX6-NEXT: v_mul_f32_e32 v1, v6, v7
; GFX6-NEXT: v_trunc_f32_e32 v1, v1 ; GFX6-NEXT: v_trunc_f32_e32 v1, v1
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v1
; GFX6-NEXT: v_mad_f32 v1, -v1, v3, v4 ; GFX6-NEXT: v_mad_f32 v1, -v1, v5, v6
; GFX6-NEXT: v_mul_lo_u32 v0, v0, s6 ; GFX6-NEXT: v_mul_lo_u32 v0, v0, s6
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v3 ; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v5
; GFX6-NEXT: s_and_b32 s6, s7, s8 ; GFX6-NEXT: s_and_b32 s6, s7, s8
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc
; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s6 ; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s6
; GFX6-NEXT: s_and_b32 s6, s5, s8 ; GFX6-NEXT: s_and_b32 s6, s5, s8
; GFX6-NEXT: v_mul_lo_u32 v1, v1, s11 ; GFX6-NEXT: v_mul_lo_u32 v1, v1, v4
; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s6 ; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s6
; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v2 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v5, v2
; GFX6-NEXT: s_lshr_b32 s12, s7, 16
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, s9, v1
; GFX6-NEXT: v_mul_f32_e32 v1, v3, v4
; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s12
; GFX6-NEXT: s_lshr_b32 s10, s5, 16
; GFX6-NEXT: v_cvt_f32_u32_e32 v6, s10
; GFX6-NEXT: v_trunc_f32_e32 v1, v1
; GFX6-NEXT: v_rcp_iflag_f32_e32 v7, v4
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0 ; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
; GFX6-NEXT: v_mad_f32 v3, -v1, v2, v3 ; GFX6-NEXT: s_lshr_b32 s4, s7, 16
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v1
; GFX6-NEXT: v_mul_f32_e32 v1, v4, v5
; GFX6-NEXT: v_cvt_f32_u32_e32 v5, s4
; GFX6-NEXT: s_lshr_b32 s6, s5, 16
; GFX6-NEXT: v_cvt_f32_u32_e32 v6, s6
; GFX6-NEXT: v_trunc_f32_e32 v1, v1
; GFX6-NEXT: v_rcp_iflag_f32_e32 v7, v5
; GFX6-NEXT: v_mad_f32 v4, -v1, v2, v4
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v2 ; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, v2
; GFX6-NEXT: v_mul_f32_e32 v2, v6, v7 ; GFX6-NEXT: v_mul_f32_e32 v2, v6, v7
; GFX6-NEXT: v_trunc_f32_e32 v2, v2 ; GFX6-NEXT: v_trunc_f32_e32 v2, v2
; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v2 ; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v2
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX6-NEXT: v_mad_f32 v2, -v2, v4, v6 ; GFX6-NEXT: v_mad_f32 v2, -v2, v5, v6
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4 ; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v5
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v1, v1, s7 ; GFX6-NEXT: v_mul_lo_u32 v1, v1, s7
; GFX6-NEXT: v_mul_lo_u32 v2, v2, s12 ; GFX6-NEXT: v_mul_lo_u32 v2, v2, s4
; GFX6-NEXT: v_and_b32_e32 v0, s8, v0 ; GFX6-NEXT: v_and_b32_e32 v0, s8, v0
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s5, v1 ; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s5, v1
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s10, v2 ; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s6, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_and_b32_e32 v1, s8, v1 ; GFX6-NEXT: v_and_b32_e32 v1, s8, v1
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2 ; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v5 ; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: urem_v4i16: ; GFX9-LABEL: urem_v4i16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX9-NEXT: s_mov_b32 s0, 0xffff ; GFX9-NEXT: s_mov_b32 s0, 0xffff
; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_and_b32 s8, s6, s0 ; GFX9-NEXT: s_and_b32 s8, s6, s0
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s8 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s8
; GFX9-NEXT: s_and_b32 s9, s4, s0 ; GFX9-NEXT: s_and_b32 s1, s4, s0
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s9 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s1
; GFX9-NEXT: s_lshr_b32 s9, s6, 16 ; GFX9-NEXT: s_lshr_b32 s6, s6, 16
; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v0
; GFX9-NEXT: v_cvt_f32_u32_e32 v4, s9 ; GFX9-NEXT: v_cvt_f32_u32_e32 v3, s6
; GFX9-NEXT: s_lshr_b32 s1, s4, 16 ; GFX9-NEXT: s_lshr_b32 s4, s4, 16
; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s1 ; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s4
; GFX9-NEXT: v_mul_f32_e32 v3, v1, v3 ; GFX9-NEXT: v_mul_f32_e32 v4, v1, v4
; GFX9-NEXT: v_trunc_f32_e32 v3, v3 ; GFX9-NEXT: v_trunc_f32_e32 v4, v4
; GFX9-NEXT: v_mad_f32 v1, -v3, v0, v1 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v3
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX9-NEXT: v_cvt_u32_f32_e32 v7, v4
; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v4 ; GFX9-NEXT: v_mad_f32 v1, -v4, v0, v1
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
; GFX9-NEXT: s_lshr_b32 s10, s7, 16
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
; GFX9-NEXT: v_mul_f32_e32 v1, v5, v6 ; GFX9-NEXT: v_mul_f32_e32 v1, v5, v6
; GFX9-NEXT: v_mul_lo_u32 v0, v0, s6 ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v7, vcc
; GFX9-NEXT: v_mul_lo_u32 v0, v0, s8
; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1
; GFX9-NEXT: s_and_b32 s6, s7, s0 ; GFX9-NEXT: s_and_b32 s8, s7, s0
; GFX9-NEXT: v_mad_f32 v3, -v1, v4, v5 ; GFX9-NEXT: v_mad_f32 v4, -v1, v3, v5
; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s6 ; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s8
; GFX9-NEXT: s_and_b32 s0, s5, s0 ; GFX9-NEXT: s_and_b32 s0, s5, s0
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_cvt_f32_u32_e32 v6, s0 ; GFX9-NEXT: v_cvt_f32_u32_e32 v6, s0
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v4
; GFX9-NEXT: v_rcp_iflag_f32_e32 v7, v5 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v7, v5
; GFX9-NEXT: v_cvt_f32_u32_e32 v4, s10 ; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, v3
; GFX9-NEXT: s_lshr_b32 s8, s5, 16 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_mul_f32_e32 v3, v6, v7 ; GFX9-NEXT: v_mul_f32_e32 v3, v6, v7
; GFX9-NEXT: v_cvt_f32_u32_e32 v7, s8 ; GFX9-NEXT: v_mul_lo_u32 v1, v1, s6
; GFX9-NEXT: v_rcp_iflag_f32_e32 v8, v4
; GFX9-NEXT: v_trunc_f32_e32 v3, v3 ; GFX9-NEXT: v_trunc_f32_e32 v3, v3
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: s_lshr_b32 s6, s7, 16
; GFX9-NEXT: v_mad_f32 v6, -v3, v5, v6 ; GFX9-NEXT: v_mad_f32 v4, -v3, v5, v6
; GFX9-NEXT: v_cvt_f32_u32_e32 v6, s6
; GFX9-NEXT: s_lshr_b32 s5, s5, 16
; GFX9-NEXT: v_cvt_f32_u32_e32 v7, s5
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v6|, v5 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v8, v6
; GFX9-NEXT: v_mul_f32_e32 v5, v7, v8 ; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, v5
; GFX9-NEXT: v_trunc_f32_e32 v5, v5 ; GFX9-NEXT: v_sub_u32_e32 v0, s1, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v5
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_mad_f32 v5, -v5, v4, v7 ; GFX9-NEXT: v_mul_f32_e32 v4, v7, v8
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v5|, v4 ; GFX9-NEXT: v_trunc_f32_e32 v4, v4
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v6, vcc ; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v4
; GFX9-NEXT: v_mul_lo_u32 v1, v1, s9 ; GFX9-NEXT: v_mad_f32 v4, -v4, v6, v7
; GFX9-NEXT: v_mul_lo_u32 v3, v3, s7 ; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, v6
; GFX9-NEXT: v_mul_lo_u32 v4, v4, s10 ; GFX9-NEXT: v_mul_lo_u32 v3, v3, s8
; GFX9-NEXT: v_sub_u32_e32 v0, s4, v0 ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
; GFX9-NEXT: v_sub_u32_e32 v5, s1, v1 ; GFX9-NEXT: v_mul_lo_u32 v4, v4, s6
; GFX9-NEXT: v_sub_u32_e32 v1, s5, v3 ; GFX9-NEXT: v_sub_u32_e32 v5, s4, v1
; GFX9-NEXT: v_sub_u32_e32 v3, s8, v4 ; GFX9-NEXT: v_sub_u32_e32 v1, s0, v3
; GFX9-NEXT: v_sub_u32_e32 v3, s5, v4
; GFX9-NEXT: v_mov_b32_e32 v4, 0xffff ; GFX9-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX9-NEXT: v_and_b32_e32 v1, v4, v1 ; GFX9-NEXT: v_and_b32_e32 v1, v4, v1
; GFX9-NEXT: v_and_b32_e32 v0, v4, v0 ; GFX9-NEXT: v_and_b32_e32 v0, v4, v0
; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1 ; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: v_lshl_or_b32 v0, v5, 16, v0 ; GFX9-NEXT: v_lshl_or_b32 v0, v5, 16, v0
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%r = urem <4 x i16> %x, %y %r = urem <4 x i16> %x, %y
▲ Show 20 Lines • Show All 391 Lines • ▼ Show 20 Lines
; GFX6-NEXT: s_or_b32 s8, s8, 1 ; GFX6-NEXT: s_or_b32 s8, s8, 1
; GFX6-NEXT: v_mov_b32_e32 v3, s8 ; GFX6-NEXT: v_mov_b32_e32 v3, s8
; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2 ; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2
; GFX6-NEXT: v_trunc_f32_e32 v2, v2 ; GFX6-NEXT: v_trunc_f32_e32 v2, v2
; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1
; GFX6-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GFX6-NEXT: v_cvt_i32_f32_e32 v2, v2
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| ; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; GFX6-NEXT: v_mov_b32_e32 v1, s4
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_mov_b32_e32 v2, s6
; GFX6-NEXT: v_alignbit_b32 v2, s7, v2, 16
; GFX6-NEXT: v_bfe_i32 v3, v2, 0, 16
; GFX6-NEXT: v_cvt_f32_i32_e32 v4, v3
; GFX6-NEXT: v_alignbit_b32 v1, s5, v1, 16
; GFX6-NEXT: v_bfe_i32 v5, v1, 0, 16
; GFX6-NEXT: v_cvt_f32_i32_e32 v6, v5
; GFX6-NEXT: v_rcp_iflag_f32_e32 v7, v4
; GFX6-NEXT: v_mul_lo_u32 v0, v0, s6 ; GFX6-NEXT: v_mul_lo_u32 v0, v0, s6
; GFX6-NEXT: s_ashr_i32 s6, s6, 16 ; GFX6-NEXT: v_xor_b32_e32 v3, v5, v3
; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s6 ; GFX6-NEXT: v_ashrrev_i32_e32 v3, 30, v3
; GFX6-NEXT: v_mul_f32_e32 v5, v6, v7
; GFX6-NEXT: v_trunc_f32_e32 v5, v5
; GFX6-NEXT: v_mad_f32 v6, -v5, v4, v6
; GFX6-NEXT: v_cvt_i32_f32_e32 v5, v5
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0 ; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
; GFX6-NEXT: s_ashr_i32 s4, s4, 16 ; GFX6-NEXT: v_or_b32_e32 v3, 1, v3
; GFX6-NEXT: v_cvt_f32_i32_e32 v2, s4 ; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v6|, |v4|
; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v1 ; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
; GFX6-NEXT: s_xor_b32 s8, s4, s6 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GFX6-NEXT: s_ashr_i32 s8, s8, 30 ; GFX6-NEXT: s_sext_i32_i16 s4, s7
; GFX6-NEXT: s_or_b32 s8, s8, 1 ; GFX6-NEXT: v_mul_lo_u32 v2, v3, v2
; GFX6-NEXT: v_mul_f32_e32 v3, v2, v3 ; GFX6-NEXT: v_cvt_f32_i32_e32 v3, s4
; GFX6-NEXT: v_trunc_f32_e32 v3, v3 ; GFX6-NEXT: s_sext_i32_i16 s6, s5
; GFX6-NEXT: v_mad_f32 v2, -v3, v1, v2 ; GFX6-NEXT: s_xor_b32 s4, s6, s4
; GFX6-NEXT: v_cvt_i32_f32_e32 v3, v3 ; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT: v_mov_b32_e32 v4, s8
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, |v1|
; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GFX6-NEXT: v_mul_lo_u32 v1, v1, s6
; GFX6-NEXT: s_sext_i32_i16 s6, s7
; GFX6-NEXT: v_cvt_f32_i32_e32 v2, s6 ; GFX6-NEXT: v_cvt_f32_i32_e32 v2, s6
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s4, v1 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v3
; GFX6-NEXT: s_sext_i32_i16 s4, s5
; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s4
; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v2
; GFX6-NEXT: s_xor_b32 s4, s4, s6
; GFX6-NEXT: s_ashr_i32 s4, s4, 30 ; GFX6-NEXT: s_ashr_i32 s4, s4, 30
; GFX6-NEXT: s_or_b32 s4, s4, 1 ; GFX6-NEXT: s_or_b32 s4, s4, 1
; GFX6-NEXT: v_mul_f32_e32 v4, v1, v4
; GFX6-NEXT: v_trunc_f32_e32 v4, v4
; GFX6-NEXT: v_mad_f32 v1, -v4, v2, v1
; GFX6-NEXT: v_mov_b32_e32 v5, s4 ; GFX6-NEXT: v_mov_b32_e32 v5, s4
; GFX6-NEXT: s_ashr_i32 s4, s7, 16 ; GFX6-NEXT: v_mul_f32_e32 v4, v2, v4
; GFX6-NEXT: v_trunc_f32_e32 v4, v4
; GFX6-NEXT: v_mad_f32 v2, -v4, v3, v2
; GFX6-NEXT: v_cvt_i32_f32_e32 v4, v4 ; GFX6-NEXT: v_cvt_i32_f32_e32 v4, v4
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v2| ; GFX6-NEXT: s_ashr_i32 s4, s7, 16
; GFX6-NEXT: v_cvt_f32_i32_e32 v2, s4 ; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, |v3|
; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc ; GFX6-NEXT: v_cvt_f32_i32_e32 v3, s4
; GFX6-NEXT: s_ashr_i32 s6, s5, 16 ; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v5, vcc
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v4 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_cvt_f32_i32_e32 v4, s6 ; GFX6-NEXT: v_mul_lo_u32 v2, v2, s7
; GFX6-NEXT: v_rcp_iflag_f32_e32 v5, v2 ; GFX6-NEXT: s_lshr_b32 s6, s7, 16
; GFX6-NEXT: v_mul_lo_u32 v1, v1, s7 ; GFX6-NEXT: s_ashr_i32 s7, s5, 16
; GFX6-NEXT: s_xor_b32 s7, s6, s4 ; GFX6-NEXT: v_cvt_f32_i32_e32 v4, s7
; GFX6-NEXT: s_ashr_i32 s7, s7, 30 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v5, v3
; GFX6-NEXT: s_xor_b32 s4, s7, s4
; GFX6-NEXT: s_ashr_i32 s4, s4, 30
; GFX6-NEXT: s_or_b32 s4, s4, 1
; GFX6-NEXT: v_mul_f32_e32 v5, v4, v5 ; GFX6-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX6-NEXT: v_trunc_f32_e32 v5, v5 ; GFX6-NEXT: v_trunc_f32_e32 v5, v5
; GFX6-NEXT: v_mad_f32 v4, -v5, v2, v4 ; GFX6-NEXT: v_mad_f32 v4, -v5, v3, v4
; GFX6-NEXT: v_cvt_i32_f32_e32 v5, v5 ; GFX6-NEXT: v_cvt_i32_f32_e32 v5, v5
; GFX6-NEXT: s_or_b32 s7, s7, 1 ; GFX6-NEXT: v_mov_b32_e32 v6, s4
; GFX6-NEXT: v_mov_b32_e32 v6, s7 ; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, |v3|
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, |v2| ; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v6, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5 ; GFX6-NEXT: v_mul_lo_u32 v3, v3, s6
; GFX6-NEXT: v_mul_lo_u32 v2, v2, s4 ; GFX6-NEXT: s_lshr_b32 s4, s5, 16
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s5, v1 ; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s5, v2
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s4, v3
; GFX6-NEXT: s_mov_b32 s4, 0xffff ; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s6, v2 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 ; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v3
; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: srem_v4i16: ; GFX9-LABEL: srem_v4i16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_sext_i32_i16 s0, s6 ; GFX9-NEXT: s_sext_i32_i16 s8, s6
; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s0 ; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s8
; GFX9-NEXT: s_sext_i32_i16 s1, s4 ; GFX9-NEXT: s_sext_i32_i16 s9, s4
; GFX9-NEXT: v_cvt_f32_i32_e32 v1, s1 ; GFX9-NEXT: v_cvt_f32_i32_e32 v1, s9
; GFX9-NEXT: s_xor_b32 s0, s1, s0 ; GFX9-NEXT: s_xor_b32 s0, s9, s8
; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v0
; GFX9-NEXT: s_ashr_i32 s0, s0, 30 ; GFX9-NEXT: s_ashr_i32 s0, s0, 30
; GFX9-NEXT: s_or_b32 s8, s0, 1 ; GFX9-NEXT: s_or_b32 s10, s0, 1
; GFX9-NEXT: v_mul_f32_e32 v3, v1, v3 ; GFX9-NEXT: v_mul_f32_e32 v3, v1, v3
; GFX9-NEXT: v_trunc_f32_e32 v3, v3 ; GFX9-NEXT: v_trunc_f32_e32 v3, v3
; GFX9-NEXT: v_mad_f32 v1, -v3, v0, v1 ; GFX9-NEXT: v_mad_f32 v1, -v3, v0, v1
; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, |v0| ; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, |v0|
; GFX9-NEXT: s_and_b64 s[0:1], s[0:1], exec ; GFX9-NEXT: s_and_b64 s[0:1], s[0:1], exec
; GFX9-NEXT: s_cselect_b32 s0, s8, 0 ; GFX9-NEXT: s_cselect_b32 s0, s10, 0
; GFX9-NEXT: s_ashr_i32 s9, s6, 16 ; GFX9-NEXT: s_ashr_i32 s6, s6, 16
; GFX9-NEXT: v_cvt_i32_f32_e32 v3, v3 ; GFX9-NEXT: v_cvt_i32_f32_e32 v3, v3
; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s9 ; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s6
; GFX9-NEXT: s_ashr_i32 s8, s4, 16 ; GFX9-NEXT: s_ashr_i32 s4, s4, 16
; GFX9-NEXT: v_add_u32_e32 v1, s0, v3 ; GFX9-NEXT: v_add_u32_e32 v1, s0, v3
; GFX9-NEXT: v_cvt_f32_i32_e32 v3, s8 ; GFX9-NEXT: v_cvt_f32_i32_e32 v3, s4
; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v0
; GFX9-NEXT: s_xor_b32 s0, s8, s9 ; GFX9-NEXT: s_xor_b32 s0, s4, s6
; GFX9-NEXT: s_ashr_i32 s0, s0, 30 ; GFX9-NEXT: s_ashr_i32 s0, s0, 30
; GFX9-NEXT: v_mul_lo_u32 v1, v1, s6 ; GFX9-NEXT: v_mul_lo_u32 v1, v1, s8
; GFX9-NEXT: v_mul_f32_e32 v4, v3, v4 ; GFX9-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX9-NEXT: v_trunc_f32_e32 v4, v4 ; GFX9-NEXT: v_trunc_f32_e32 v4, v4
; GFX9-NEXT: v_mad_f32 v3, -v4, v0, v3 ; GFX9-NEXT: v_mad_f32 v3, -v4, v0, v3
; GFX9-NEXT: v_cvt_i32_f32_e32 v4, v4 ; GFX9-NEXT: s_or_b32 s8, s0, 1
; GFX9-NEXT: s_or_b32 s6, s0, 1
; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v3|, |v0| ; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v3|, |v0|
; GFX9-NEXT: v_cvt_i32_f32_e32 v4, v4
; GFX9-NEXT: s_and_b64 s[0:1], s[0:1], exec ; GFX9-NEXT: s_and_b64 s[0:1], s[0:1], exec
; GFX9-NEXT: s_cselect_b32 s0, s6, 0 ; GFX9-NEXT: s_cselect_b32 s0, s8, 0
; GFX9-NEXT: s_sext_i32_i16 s8, s7
; GFX9-NEXT: v_cvt_f32_i32_e32 v3, s8
; GFX9-NEXT: v_add_u32_e32 v0, s0, v4 ; GFX9-NEXT: v_add_u32_e32 v0, s0, v4
; GFX9-NEXT: s_sext_i32_i16 s0, s7 ; GFX9-NEXT: v_mul_lo_u32 v0, v0, s6
; GFX9-NEXT: v_cvt_f32_i32_e32 v3, s0 ; GFX9-NEXT: s_sext_i32_i16 s6, s5
; GFX9-NEXT: s_sext_i32_i16 s1, s5 ; GFX9-NEXT: v_cvt_f32_i32_e32 v4, s6
; GFX9-NEXT: v_cvt_f32_i32_e32 v4, s1
; GFX9-NEXT: s_xor_b32 s0, s1, s0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v3 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v3
; GFX9-NEXT: s_xor_b32 s0, s6, s8
; GFX9-NEXT: s_ashr_i32 s0, s0, 30 ; GFX9-NEXT: s_ashr_i32 s0, s0, 30
; GFX9-NEXT: s_or_b32 s6, s0, 1 ; GFX9-NEXT: s_or_b32 s10, s0, 1
; GFX9-NEXT: v_mul_lo_u32 v0, v0, s9
; GFX9-NEXT: v_mul_f32_e32 v5, v4, v5 ; GFX9-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX9-NEXT: v_trunc_f32_e32 v5, v5 ; GFX9-NEXT: v_trunc_f32_e32 v5, v5
; GFX9-NEXT: v_mad_f32 v4, -v5, v3, v4 ; GFX9-NEXT: v_mad_f32 v4, -v5, v3, v4
; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v4|, |v3| ; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v4|, |v3|
; GFX9-NEXT: v_cvt_i32_f32_e32 v5, v5
; GFX9-NEXT: s_and_b64 s[0:1], s[0:1], exec ; GFX9-NEXT: s_and_b64 s[0:1], s[0:1], exec
; GFX9-NEXT: s_cselect_b32 s0, s6, 0 ; GFX9-NEXT: s_cselect_b32 s0, s10, 0
; GFX9-NEXT: s_ashr_i32 s6, s7, 16 ; GFX9-NEXT: s_ashr_i32 s7, s7, 16
; GFX9-NEXT: v_cvt_f32_i32_e32 v4, s6 ; GFX9-NEXT: v_cvt_i32_f32_e32 v5, v5
; GFX9-NEXT: v_cvt_f32_i32_e32 v4, s7
; GFX9-NEXT: s_ashr_i32 s5, s5, 16
; GFX9-NEXT: v_sub_u32_e32 v0, s4, v0
; GFX9-NEXT: v_add_u32_e32 v3, s0, v5 ; GFX9-NEXT: v_add_u32_e32 v3, s0, v5
; GFX9-NEXT: v_mul_lo_u32 v3, v3, s7 ; GFX9-NEXT: v_cvt_f32_i32_e32 v5, s5
; GFX9-NEXT: s_ashr_i32 s7, s5, 16
; GFX9-NEXT: v_cvt_f32_i32_e32 v5, s7
; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v4 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v4
; GFX9-NEXT: s_xor_b32 s0, s7, s6 ; GFX9-NEXT: s_xor_b32 s0, s5, s7
; GFX9-NEXT: s_ashr_i32 s0, s0, 30 ; GFX9-NEXT: s_ashr_i32 s0, s0, 30
; GFX9-NEXT: s_or_b32 s9, s0, 1 ; GFX9-NEXT: v_mul_lo_u32 v3, v3, s8
; GFX9-NEXT: v_mul_f32_e32 v6, v5, v6 ; GFX9-NEXT: v_mul_f32_e32 v6, v5, v6
; GFX9-NEXT: v_trunc_f32_e32 v6, v6 ; GFX9-NEXT: v_trunc_f32_e32 v6, v6
; GFX9-NEXT: v_mad_f32 v5, -v6, v4, v5 ; GFX9-NEXT: v_mad_f32 v5, -v6, v4, v5
; GFX9-NEXT: v_cvt_i32_f32_e32 v6, v6 ; GFX9-NEXT: v_cvt_i32_f32_e32 v6, v6
; GFX9-NEXT: s_or_b32 s8, s0, 1
; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v5|, |v4| ; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v5|, |v4|
; GFX9-NEXT: s_and_b64 s[0:1], s[0:1], exec ; GFX9-NEXT: s_and_b64 s[0:1], s[0:1], exec
; GFX9-NEXT: s_cselect_b32 s0, s9, 0 ; GFX9-NEXT: s_cselect_b32 s0, s8, 0
; GFX9-NEXT: v_add_u32_e32 v4, s0, v6 ; GFX9-NEXT: v_add_u32_e32 v4, s0, v6
; GFX9-NEXT: v_mul_lo_u32 v4, v4, s6 ; GFX9-NEXT: v_mul_lo_u32 v4, v4, s7
; GFX9-NEXT: v_sub_u32_e32 v5, s4, v1 ; GFX9-NEXT: v_sub_u32_e32 v5, s9, v1
; GFX9-NEXT: v_sub_u32_e32 v1, s5, v3 ; GFX9-NEXT: v_sub_u32_e32 v1, s6, v3
; GFX9-NEXT: v_sub_u32_e32 v0, s8, v0 ; GFX9-NEXT: v_sub_u32_e32 v3, s5, v4
; GFX9-NEXT: v_sub_u32_e32 v3, s7, v4
; GFX9-NEXT: v_mov_b32_e32 v4, 0xffff ; GFX9-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX9-NEXT: v_and_b32_e32 v1, v4, v1 ; GFX9-NEXT: v_and_b32_e32 v1, v4, v1
; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1 ; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: v_and_b32_e32 v3, v4, v5 ; GFX9-NEXT: v_and_b32_e32 v3, v4, v5
; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v3 ; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v3
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%r = srem <4 x i16> %x, %y %r = srem <4 x i16> %x, %y
▲ Show 20 Lines • Show All 385 Lines • ▼ Show 20 Lines
; CHECK-NEXT: [[TMP58:%.*]] = and i32 [[TMP57]], 65535 ; CHECK-NEXT: [[TMP58:%.*]] = and i32 [[TMP57]], 65535
; CHECK-NEXT: [[TMP59:%.*]] = trunc i32 [[TMP58]] to i16 ; CHECK-NEXT: [[TMP59:%.*]] = trunc i32 [[TMP58]] to i16
; CHECK-NEXT: [[TMP60:%.*]] = insertelement <3 x i16> [[TMP40]], i16 [[TMP59]], i64 2 ; CHECK-NEXT: [[TMP60:%.*]] = insertelement <3 x i16> [[TMP40]], i16 [[TMP59]], i64 2
; CHECK-NEXT: store <3 x i16> [[TMP60]], <3 x i16> addrspace(1)* [[OUT:%.*]], align 8 ; CHECK-NEXT: store <3 x i16> [[TMP60]], <3 x i16> addrspace(1)* [[OUT:%.*]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; GFX6-LABEL: udiv_v3i16: ; GFX6-LABEL: udiv_v3i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd ; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
; GFX6-NEXT: s_mov_b32 s8, 0xffff ; GFX6-NEXT: s_mov_b32 s8, 0xffff
; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_and_b32 s6, s2, s8 ; GFX6-NEXT: s_and_b32 s2, s6, s8
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s6 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX6-NEXT: s_and_b32 s6, s0, s8 ; GFX6-NEXT: s_and_b32 s9, s4, s8
; GFX6-NEXT: s_lshr_b32 s2, s2, 16 ; GFX6-NEXT: s_lshr_b32 s6, s6, 16
; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s6 ; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s9
; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0
; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s2 ; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s6
; GFX6-NEXT: s_lshr_b32 s0, s0, 16 ; GFX6-NEXT: s_lshr_b32 s4, s4, 16
; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s0 ; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s4
; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2 ; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2
; GFX6-NEXT: v_rcp_iflag_f32_e32 v5, v3 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v5, v3
; GFX6-NEXT: v_trunc_f32_e32 v2, v2 ; GFX6-NEXT: v_trunc_f32_e32 v2, v2
; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
; GFX6-NEXT: v_mul_f32_e32 v1, v4, v5 ; GFX6-NEXT: v_mul_f32_e32 v1, v4, v5
; GFX6-NEXT: v_trunc_f32_e32 v1, v1 ; GFX6-NEXT: v_trunc_f32_e32 v1, v1
; GFX6-NEXT: s_and_b32 s0, s3, s8 ; GFX6-NEXT: s_and_b32 s4, s7, s8
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
; GFX6-NEXT: v_mad_f32 v2, -v1, v3, v4 ; GFX6-NEXT: v_mad_f32 v2, -v1, v3, v4
; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s0 ; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s4
; GFX6-NEXT: s_and_b32 s0, s1, s8 ; GFX6-NEXT: s_and_b32 s4, s5, s8
; GFX6-NEXT: v_cvt_f32_u32_e32 v5, s0 ; GFX6-NEXT: v_cvt_f32_u32_e32 v5, s4
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: v_rcp_iflag_f32_e32 v6, v4 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v6, v4
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v3 ; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v3
; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX6-NEXT: v_mul_f32_e32 v2, v5, v6 ; GFX6-NEXT: v_mul_f32_e32 v2, v5, v6
; GFX6-NEXT: v_trunc_f32_e32 v2, v2 ; GFX6-NEXT: v_trunc_f32_e32 v2, v2
; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v2 ; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v2
; GFX6-NEXT: v_mad_f32 v2, -v2, v4, v5 ; GFX6-NEXT: v_mad_f32 v2, -v2, v4, v5
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4 ; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc
; GFX6-NEXT: v_and_b32_e32 v0, s8, v0 ; GFX6-NEXT: v_and_b32_e32 v0, s8, v0
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: buffer_store_short v2, off, s[4:7], 0 offset:4 ; GFX6-NEXT: buffer_store_short v2, off, s[0:3], 0 offset:4
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: udiv_v3i16: ; GFX9-LABEL: udiv_v3i16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x2c
; GFX9-NEXT: s_mov_b32 s0, 0xffff ; GFX9-NEXT: s_mov_b32 s0, 0xffff
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_and_b32 s1, s2, s0 ; GFX9-NEXT: s_and_b32 s8, s6, s0
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s1 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s8
; GFX9-NEXT: s_and_b32 s1, s6, s0 ; GFX9-NEXT: s_lshr_b32 s6, s6, 16
; GFX9-NEXT: s_lshr_b32 s2, s2, 16 ; GFX9-NEXT: s_and_b32 s1, s4, s0
; GFX9-NEXT: v_cvt_f32_u32_e32 v3, s6
; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s1 ; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s1
; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v1
; GFX9-NEXT: v_cvt_f32_u32_e32 v4, s2 ; GFX9-NEXT: s_lshr_b32 s1, s4, 16
; GFX9-NEXT: s_lshr_b32 s1, s6, 16
; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s1 ; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s1
; GFX9-NEXT: v_mul_f32_e32 v3, v2, v3 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v3
; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v4 ; GFX9-NEXT: v_mul_f32_e32 v4, v2, v4
; GFX9-NEXT: v_trunc_f32_e32 v3, v3 ; GFX9-NEXT: v_trunc_f32_e32 v4, v4
; GFX9-NEXT: v_mad_f32 v2, -v3, v0, v2 ; GFX9-NEXT: v_mad_f32 v2, -v4, v1, v2
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v1
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0
; GFX9-NEXT: v_mul_f32_e32 v2, v5, v6 ; GFX9-NEXT: v_mul_f32_e32 v2, v5, v6
; GFX9-NEXT: v_trunc_f32_e32 v2, v2 ; GFX9-NEXT: v_trunc_f32_e32 v2, v2
; GFX9-NEXT: s_and_b32 s1, s3, s0 ; GFX9-NEXT: s_and_b32 s1, s7, s0
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v3, vcc ; GFX9-NEXT: v_cvt_u32_f32_e32 v7, v4
; GFX9-NEXT: v_mad_f32 v3, -v2, v4, v5 ; GFX9-NEXT: v_mad_f32 v4, -v2, v3, v5
; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s1 ; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s1
; GFX9-NEXT: s_and_b32 s0, s7, s0 ; GFX9-NEXT: s_and_b32 s0, s5, s0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v7, vcc
; GFX9-NEXT: v_cvt_f32_u32_e32 v6, s0 ; GFX9-NEXT: v_cvt_f32_u32_e32 v6, s0
; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX9-NEXT: v_rcp_iflag_f32_e32 v7, v5 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v7, v5
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v4 ; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, v3
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc ; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX9-NEXT: v_mul_f32_e32 v3, v6, v7 ; GFX9-NEXT: v_mul_f32_e32 v3, v6, v7
; GFX9-NEXT: v_trunc_f32_e32 v3, v3 ; GFX9-NEXT: v_trunc_f32_e32 v3, v3
; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v3 ; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v3
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc
; GFX9-NEXT: v_mad_f32 v3, -v3, v5, v6 ; GFX9-NEXT: v_mad_f32 v3, -v3, v5, v6
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v5 ; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v5
; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
; GFX9-NEXT: global_store_short v1, v3, s[4:5] offset:4 ; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: global_store_dword v1, v0, s[4:5] ; GFX9-NEXT: global_store_short v0, v3, s[2:3] offset:4
; GFX9-NEXT: global_store_dword v0, v1, s[2:3]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%r = udiv <3 x i16> %x, %y %r = udiv <3 x i16> %x, %y
store <3 x i16> %r, <3 x i16> addrspace(1)* %out store <3 x i16> %r, <3 x i16> addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @urem_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x, <3 x i16> %y) { define amdgpu_kernel void @urem_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x, <3 x i16> %y) {
; CHECK-LABEL: @urem_v3i16( ; CHECK-LABEL: @urem_v3i16(
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; CHECK-NEXT: [[TMP64:%.*]] = and i32 [[TMP63]], 65535 ; CHECK-NEXT: [[TMP64:%.*]] = and i32 [[TMP63]], 65535
; CHECK-NEXT: [[TMP65:%.*]] = trunc i32 [[TMP64]] to i16 ; CHECK-NEXT: [[TMP65:%.*]] = trunc i32 [[TMP64]] to i16
; CHECK-NEXT: [[TMP66:%.*]] = insertelement <3 x i16> [[TMP44]], i16 [[TMP65]], i64 2 ; CHECK-NEXT: [[TMP66:%.*]] = insertelement <3 x i16> [[TMP44]], i16 [[TMP65]], i64 2
; CHECK-NEXT: store <3 x i16> [[TMP66]], <3 x i16> addrspace(1)* [[OUT:%.*]], align 8 ; CHECK-NEXT: store <3 x i16> [[TMP66]], <3 x i16> addrspace(1)* [[OUT:%.*]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; GFX6-LABEL: urem_v3i16: ; GFX6-LABEL: urem_v3i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd ; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
; GFX6-NEXT: s_mov_b32 s8, 0xffff ; GFX6-NEXT: s_mov_b32 s8, 0xffff
; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_and_b32 s6, s2, s8 ; GFX6-NEXT: s_and_b32 s9, s6, s8
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s6 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s9
; GFX6-NEXT: s_and_b32 s6, s0, s8 ; GFX6-NEXT: s_and_b32 s2, s4, s8
; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s6 ; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s2
; GFX6-NEXT: v_mov_b32_e32 v4, s2 ; GFX6-NEXT: v_mov_b32_e32 v2, s6
; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v0 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v0
; GFX6-NEXT: v_alignbit_b32 v4, s3, v4, 16 ; GFX6-NEXT: v_alignbit_b32 v2, s7, v2, 16
; GFX6-NEXT: v_and_b32_e32 v5, s8, v4 ; GFX6-NEXT: v_and_b32_e32 v5, s8, v2
; GFX6-NEXT: v_mov_b32_e32 v1, s0 ; GFX6-NEXT: v_cvt_f32_u32_e32 v5, v5
; GFX6-NEXT: v_mul_f32_e32 v3, v2, v3 ; GFX6-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX6-NEXT: v_trunc_f32_e32 v3, v3 ; GFX6-NEXT: v_trunc_f32_e32 v4, v4
; GFX6-NEXT: v_cvt_u32_f32_e32 v6, v3 ; GFX6-NEXT: v_cvt_u32_f32_e32 v6, v4
; GFX6-NEXT: v_mad_f32 v2, -v3, v0, v2 ; GFX6-NEXT: v_mad_f32 v3, -v4, v0, v3
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0 ; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v0
; GFX6-NEXT: v_cvt_f32_u32_e32 v2, v5 ; GFX6-NEXT: v_mov_b32_e32 v1, s4
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v6, vcc ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v6, vcc
; GFX6-NEXT: v_mul_lo_u32 v0, v0, s2 ; GFX6-NEXT: v_mul_lo_u32 v0, v0, s6
; GFX6-NEXT: v_alignbit_b32 v1, s1, v1, 16 ; GFX6-NEXT: v_alignbit_b32 v1, s5, v1, 16
; GFX6-NEXT: v_and_b32_e32 v3, s8, v1 ; GFX6-NEXT: v_and_b32_e32 v3, s8, v1
; GFX6-NEXT: v_cvt_f32_u32_e32 v3, v3 ; GFX6-NEXT: v_cvt_f32_u32_e32 v3, v3
; GFX6-NEXT: v_rcp_iflag_f32_e32 v5, v2 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v5
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0 ; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
; GFX6-NEXT: s_and_b32 s0, s3, s8 ; GFX6-NEXT: s_and_b32 s4, s7, s8
; GFX6-NEXT: v_cvt_f32_u32_e32 v6, s0 ; GFX6-NEXT: v_cvt_f32_u32_e32 v6, s4
; GFX6-NEXT: v_mul_f32_e32 v5, v3, v5 ; GFX6-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX6-NEXT: s_and_b32 s0, s1, s8 ; GFX6-NEXT: v_trunc_f32_e32 v4, v4
; GFX6-NEXT: v_trunc_f32_e32 v5, v5 ; GFX6-NEXT: v_mad_f32 v3, -v4, v5, v3
; GFX6-NEXT: v_cvt_f32_u32_e32 v7, s0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v4
; GFX6-NEXT: s_and_b32 s4, s5, s8
; GFX6-NEXT: v_cvt_f32_u32_e32 v7, s4
; GFX6-NEXT: v_rcp_iflag_f32_e32 v8, v6 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v8, v6
; GFX6-NEXT: v_mad_f32 v3, -v5, v2, v3 ; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v5
; GFX6-NEXT: v_cvt_u32_f32_e32 v5, v5 ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v2 ; GFX6-NEXT: v_mul_lo_u32 v2, v3, v2
; GFX6-NEXT: v_mul_f32_e32 v3, v7, v8 ; GFX6-NEXT: v_mul_f32_e32 v3, v7, v8
; GFX6-NEXT: v_trunc_f32_e32 v3, v3 ; GFX6-NEXT: v_trunc_f32_e32 v3, v3
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, v2, v4
; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v3 ; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v3
; GFX6-NEXT: v_mad_f32 v3, -v3, v6, v7 ; GFX6-NEXT: v_mad_f32 v3, -v3, v6, v7
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v6 ; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v6
; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v3, v3, s3 ; GFX6-NEXT: v_mul_lo_u32 v3, v3, s7
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2 ; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s1, v3 ; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s5, v3
; GFX6-NEXT: v_and_b32_e32 v0, s8, v0 ; GFX6-NEXT: v_and_b32_e32 v0, s8, v0
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: buffer_store_short v2, off, s[4:7], 0 offset:4 ; GFX6-NEXT: buffer_store_short v2, off, s[0:3], 0 offset:4
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: urem_v3i16: ; GFX9-LABEL: urem_v3i16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34 ; GFX9-NEXT: s_mov_b32 s2, 0xffff
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: s_mov_b32 s0, 0xffff
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_and_b32 s1, s2, s0 ; GFX9-NEXT: s_and_b32 s8, s6, s2
; GFX9-NEXT: s_and_b32 s8, s4, s0
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s8 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s8
; GFX9-NEXT: s_and_b32 s3, s4, s2
; GFX9-NEXT: s_lshr_b32 s6, s6, 16
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s6
; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s3
; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v0
; GFX9-NEXT: s_lshr_b32 s4, s4, 16 ; GFX9-NEXT: s_lshr_b32 s4, s4, 16
; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s4 ; GFX9-NEXT: v_cvt_f32_u32_e32 v3, s4
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s1 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v1
; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v0 ; GFX9-NEXT: v_mul_f32_e32 v4, v2, v4
; GFX9-NEXT: s_lshr_b32 s2, s2, 16 ; GFX9-NEXT: v_trunc_f32_e32 v4, v4
; GFX9-NEXT: v_cvt_f32_u32_e32 v4, s2 ; GFX9-NEXT: s_and_b32 s7, s7, s2
; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v2 ; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v4
; GFX9-NEXT: v_mul_f32_e32 v3, v1, v3 ; GFX9-NEXT: v_mad_f32 v2, -v4, v0, v2
; GFX9-NEXT: v_trunc_f32_e32 v3, v3 ; GFX9-NEXT: v_cvt_f32_u32_e32 v4, s7
; GFX9-NEXT: v_mad_f32 v1, -v3, v0, v1 ; GFX9-NEXT: v_mul_f32_e32 v5, v3, v5
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0
; GFX9-NEXT: v_mul_f32_e32 v1, v4, v5 ; GFX9-NEXT: v_trunc_f32_e32 v2, v5
; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: s_and_b32 s2, s5, s2
; GFX9-NEXT: s_and_b32 s5, s5, s0
; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v3
; GFX9-NEXT: v_mad_f32 v3, -v1, v2, v4
; GFX9-NEXT: v_cvt_f32_u32_e32 v4, s5
; GFX9-NEXT: s_and_b32 s0, s3, s0
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v6, vcc
; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s0 ; GFX9-NEXT: v_mad_f32 v3, -v2, v1, v3
; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s2
; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v4 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v4
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v1
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v2 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
; GFX9-NEXT: v_mul_lo_u32 v0, v0, s8
; GFX9-NEXT: v_mul_f32_e32 v2, v5, v6 ; GFX9-NEXT: v_mul_f32_e32 v2, v5, v6
; GFX9-NEXT: v_trunc_f32_e32 v2, v2 ; GFX9-NEXT: v_trunc_f32_e32 v2, v2
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v2 ; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: v_mad_f32 v2, -v2, v4, v5 ; GFX9-NEXT: v_mad_f32 v2, -v2, v4, v5
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4 ; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4
; GFX9-NEXT: v_mul_lo_u32 v0, v0, s8
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v3, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v3, vcc
; GFX9-NEXT: v_mul_lo_u32 v1, v1, s4 ; GFX9-NEXT: v_mul_lo_u32 v1, v1, s6
; GFX9-NEXT: v_mul_lo_u32 v2, v2, s5 ; GFX9-NEXT: v_mul_lo_u32 v2, v2, s7
; GFX9-NEXT: v_sub_u32_e32 v0, s1, v0 ; GFX9-NEXT: v_sub_u32_e32 v0, s3, v0
; GFX9-NEXT: v_mov_b32_e32 v3, 0 ; GFX9-NEXT: v_mov_b32_e32 v3, 0
; GFX9-NEXT: v_sub_u32_e32 v1, s2, v1 ; GFX9-NEXT: v_sub_u32_e32 v1, s4, v1
; GFX9-NEXT: v_sub_u32_e32 v2, s0, v2 ; GFX9-NEXT: v_sub_u32_e32 v2, s2, v2
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0 ; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: global_store_short v3, v2, s[6:7] offset:4 ; GFX9-NEXT: global_store_short v3, v2, s[0:1] offset:4
; GFX9-NEXT: global_store_dword v3, v0, s[6:7] ; GFX9-NEXT: global_store_dword v3, v0, s[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%r = urem <3 x i16> %x, %y %r = urem <3 x i16> %x, %y
store <3 x i16> %r, <3 x i16> addrspace(1)* %out store <3 x i16> %r, <3 x i16> addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @sdiv_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x, <3 x i16> %y) { define amdgpu_kernel void @sdiv_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x, <3 x i16> %y) {
; CHECK-LABEL: @sdiv_v3i16( ; CHECK-LABEL: @sdiv_v3i16(
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; CHECK-NEXT: [[TMP70:%.*]] = ashr i32 [[TMP69]], 16 ; CHECK-NEXT: [[TMP70:%.*]] = ashr i32 [[TMP69]], 16
; CHECK-NEXT: [[TMP71:%.*]] = trunc i32 [[TMP70]] to i16 ; CHECK-NEXT: [[TMP71:%.*]] = trunc i32 [[TMP70]] to i16
; CHECK-NEXT: [[TMP72:%.*]] = insertelement <3 x i16> [[TMP48]], i16 [[TMP71]], i64 2 ; CHECK-NEXT: [[TMP72:%.*]] = insertelement <3 x i16> [[TMP48]], i16 [[TMP71]], i64 2
; CHECK-NEXT: store <3 x i16> [[TMP72]], <3 x i16> addrspace(1)* [[OUT:%.*]], align 8 ; CHECK-NEXT: store <3 x i16> [[TMP72]], <3 x i16> addrspace(1)* [[OUT:%.*]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; GFX6-LABEL: sdiv_v3i16: ; GFX6-LABEL: sdiv_v3i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd ; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_sext_i32_i16 s8, s2 ; GFX6-NEXT: s_sext_i32_i16 s8, s6
; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s8 ; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s8
; GFX6-NEXT: s_sext_i32_i16 s9, s0 ; GFX6-NEXT: s_sext_i32_i16 s9, s4
; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s9 ; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s9
; GFX6-NEXT: s_xor_b32 s8, s9, s8 ; GFX6-NEXT: s_xor_b32 s8, s9, s8
; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0
; GFX6-NEXT: s_ashr_i32 s2, s2, 16 ; GFX6-NEXT: s_ashr_i32 s6, s6, 16
; GFX6-NEXT: s_ashr_i32 s8, s8, 30 ; GFX6-NEXT: s_ashr_i32 s8, s8, 30
; GFX6-NEXT: s_or_b32 s8, s8, 1 ; GFX6-NEXT: s_or_b32 s8, s8, 1
; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2 ; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2
; GFX6-NEXT: v_trunc_f32_e32 v2, v2 ; GFX6-NEXT: v_trunc_f32_e32 v2, v2
; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1
; GFX6-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GFX6-NEXT: v_cvt_i32_f32_e32 v2, v2
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| ; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s2 ; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s6
; GFX6-NEXT: v_mov_b32_e32 v3, s8 ; GFX6-NEXT: v_mov_b32_e32 v3, s8
; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; GFX6-NEXT: s_ashr_i32 s0, s0, 16 ; GFX6-NEXT: s_ashr_i32 s4, s4, 16
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_cvt_f32_i32_e32 v2, s0 ; GFX6-NEXT: v_cvt_f32_i32_e32 v2, s4
; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v1 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v1
; GFX6-NEXT: s_xor_b32 s0, s0, s2 ; GFX6-NEXT: s_xor_b32 s4, s4, s6
; GFX6-NEXT: s_ashr_i32 s0, s0, 30 ; GFX6-NEXT: s_ashr_i32 s4, s4, 30
; GFX6-NEXT: s_or_b32 s0, s0, 1 ; GFX6-NEXT: s_or_b32 s4, s4, 1
; GFX6-NEXT: v_mul_f32_e32 v3, v2, v3 ; GFX6-NEXT: v_mul_f32_e32 v3, v2, v3
; GFX6-NEXT: v_trunc_f32_e32 v3, v3 ; GFX6-NEXT: v_trunc_f32_e32 v3, v3
; GFX6-NEXT: v_mad_f32 v2, -v3, v1, v2 ; GFX6-NEXT: v_mad_f32 v2, -v3, v1, v2
; GFX6-NEXT: v_mov_b32_e32 v4, s0 ; GFX6-NEXT: v_mov_b32_e32 v4, s4
; GFX6-NEXT: s_sext_i32_i16 s0, s3 ; GFX6-NEXT: s_sext_i32_i16 s4, s7
; GFX6-NEXT: v_cvt_i32_f32_e32 v3, v3 ; GFX6-NEXT: v_cvt_i32_f32_e32 v3, v3
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, |v1| ; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, |v1|
; GFX6-NEXT: v_cvt_f32_i32_e32 v2, s0 ; GFX6-NEXT: v_cvt_f32_i32_e32 v2, s4
; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc
; GFX6-NEXT: s_sext_i32_i16 s1, s1 ; GFX6-NEXT: s_sext_i32_i16 s5, s5
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GFX6-NEXT: v_cvt_f32_i32_e32 v3, s1 ; GFX6-NEXT: v_cvt_f32_i32_e32 v3, s5
; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v2 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v2
; GFX6-NEXT: s_xor_b32 s0, s1, s0 ; GFX6-NEXT: s_xor_b32 s4, s5, s4
; GFX6-NEXT: s_ashr_i32 s0, s0, 30 ; GFX6-NEXT: s_ashr_i32 s4, s4, 30
; GFX6-NEXT: s_or_b32 s0, s0, 1 ; GFX6-NEXT: s_or_b32 s4, s4, 1
; GFX6-NEXT: v_mul_f32_e32 v4, v3, v4 ; GFX6-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX6-NEXT: v_trunc_f32_e32 v4, v4 ; GFX6-NEXT: v_trunc_f32_e32 v4, v4
; GFX6-NEXT: v_mad_f32 v3, -v4, v2, v3 ; GFX6-NEXT: v_mad_f32 v3, -v4, v2, v3
; GFX6-NEXT: v_cvt_i32_f32_e32 v4, v4 ; GFX6-NEXT: v_cvt_i32_f32_e32 v4, v4
; GFX6-NEXT: v_mov_b32_e32 v5, s0 ; GFX6-NEXT: v_mov_b32_e32 v5, s4
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v2| ; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v2|
; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v5, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v5, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: buffer_store_short v2, off, s[4:7], 0 offset:4 ; GFX6-NEXT: buffer_store_short v2, off, s[0:3], 0 offset:4
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: sdiv_v3i16: ; GFX9-LABEL: sdiv_v3i16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x24
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_sext_i32_i16 s0, s2 ; GFX9-NEXT: s_sext_i32_i16 s0, s6
; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s0 ; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s0
; GFX9-NEXT: s_sext_i32_i16 s1, s4 ; GFX9-NEXT: s_sext_i32_i16 s1, s4
; GFX9-NEXT: v_cvt_f32_i32_e32 v2, s1 ; GFX9-NEXT: v_cvt_f32_i32_e32 v2, s1
; GFX9-NEXT: s_xor_b32 s0, s1, s0 ; GFX9-NEXT: s_xor_b32 s0, s1, s0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v0
; GFX9-NEXT: s_ashr_i32 s0, s0, 30 ; GFX9-NEXT: s_ashr_i32 s0, s0, 30
; GFX9-NEXT: s_or_b32 s8, s0, 1 ; GFX9-NEXT: s_or_b32 s8, s0, 1
; GFX9-NEXT: v_mul_f32_e32 v3, v2, v3 ; GFX9-NEXT: v_mul_f32_e32 v3, v2, v3
; GFX9-NEXT: v_trunc_f32_e32 v3, v3 ; GFX9-NEXT: v_trunc_f32_e32 v3, v3
; GFX9-NEXT: v_mad_f32 v2, -v3, v0, v2 ; GFX9-NEXT: v_mad_f32 v2, -v3, v0, v2
; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v2|, |v0| ; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v2|, |v0|
; GFX9-NEXT: s_and_b64 s[0:1], s[0:1], exec ; GFX9-NEXT: s_and_b64 s[0:1], s[0:1], exec
; GFX9-NEXT: s_cselect_b32 s0, s8, 0 ; GFX9-NEXT: s_cselect_b32 s0, s8, 0
; GFX9-NEXT: s_ashr_i32 s1, s2, 16 ; GFX9-NEXT: s_ashr_i32 s1, s6, 16
; GFX9-NEXT: v_cvt_i32_f32_e32 v3, v3 ; GFX9-NEXT: v_cvt_i32_f32_e32 v3, v3
; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s1 ; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s1
; GFX9-NEXT: s_ashr_i32 s2, s4, 16 ; GFX9-NEXT: s_ashr_i32 s4, s4, 16
; GFX9-NEXT: v_add_u32_e32 v2, s0, v3 ; GFX9-NEXT: v_add_u32_e32 v2, s0, v3
; GFX9-NEXT: v_cvt_f32_i32_e32 v3, s2 ; GFX9-NEXT: v_cvt_f32_i32_e32 v3, s4
; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v0
; GFX9-NEXT: s_xor_b32 s0, s2, s1 ; GFX9-NEXT: s_xor_b32 s0, s4, s1
; GFX9-NEXT: s_ashr_i32 s0, s0, 30 ; GFX9-NEXT: s_ashr_i32 s0, s0, 30
; GFX9-NEXT: s_or_b32 s2, s0, 1 ; GFX9-NEXT: s_or_b32 s4, s0, 1
; GFX9-NEXT: v_mul_f32_e32 v4, v3, v4 ; GFX9-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX9-NEXT: v_trunc_f32_e32 v4, v4 ; GFX9-NEXT: v_trunc_f32_e32 v4, v4
; GFX9-NEXT: v_mad_f32 v3, -v4, v0, v3 ; GFX9-NEXT: v_mad_f32 v3, -v4, v0, v3
; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v3|, |v0| ; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v3|, |v0|
; GFX9-NEXT: s_and_b64 s[0:1], s[0:1], exec ; GFX9-NEXT: s_and_b64 s[0:1], s[0:1], exec
; GFX9-NEXT: v_cvt_i32_f32_e32 v4, v4 ; GFX9-NEXT: v_cvt_i32_f32_e32 v4, v4
; GFX9-NEXT: s_sext_i32_i16 s1, s3 ; GFX9-NEXT: s_sext_i32_i16 s1, s7
; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s1 ; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s1
; GFX9-NEXT: s_cselect_b32 s0, s2, 0 ; GFX9-NEXT: s_cselect_b32 s0, s4, 0
; GFX9-NEXT: v_add_u32_e32 v3, s0, v4 ; GFX9-NEXT: v_add_u32_e32 v3, s0, v4
; GFX9-NEXT: s_sext_i32_i16 s0, s5 ; GFX9-NEXT: s_sext_i32_i16 s0, s5
; GFX9-NEXT: v_cvt_f32_i32_e32 v4, s0 ; GFX9-NEXT: v_cvt_f32_i32_e32 v4, s0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v0
; GFX9-NEXT: s_xor_b32 s0, s0, s1 ; GFX9-NEXT: s_xor_b32 s0, s0, s1
; GFX9-NEXT: s_ashr_i32 s0, s0, 30 ; GFX9-NEXT: s_ashr_i32 s0, s0, 30
; GFX9-NEXT: s_or_b32 s2, s0, 1 ; GFX9-NEXT: s_or_b32 s4, s0, 1
; GFX9-NEXT: v_mul_f32_e32 v5, v4, v5 ; GFX9-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX9-NEXT: v_trunc_f32_e32 v5, v5 ; GFX9-NEXT: v_trunc_f32_e32 v5, v5
; GFX9-NEXT: v_mad_f32 v4, -v5, v0, v4 ; GFX9-NEXT: v_mad_f32 v4, -v5, v0, v4
; GFX9-NEXT: v_cvt_i32_f32_e32 v5, v5 ; GFX9-NEXT: v_cvt_i32_f32_e32 v5, v5
; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v4|, |v0| ; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v4|, |v0|
; GFX9-NEXT: s_and_b64 s[0:1], s[0:1], exec ; GFX9-NEXT: s_and_b64 s[0:1], s[0:1], exec
; GFX9-NEXT: s_cselect_b32 s0, s2, 0 ; GFX9-NEXT: s_cselect_b32 s0, s4, 0
; GFX9-NEXT: v_add_u32_e32 v0, s0, v5 ; GFX9-NEXT: v_add_u32_e32 v0, s0, v5
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2 ; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: global_store_short v1, v0, s[6:7] offset:4 ; GFX9-NEXT: global_store_short v1, v0, s[2:3] offset:4
; GFX9-NEXT: global_store_dword v1, v2, s[6:7] ; GFX9-NEXT: global_store_dword v1, v2, s[2:3]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%r = sdiv <3 x i16> %x, %y %r = sdiv <3 x i16> %x, %y
store <3 x i16> %r, <3 x i16> addrspace(1)* %out store <3 x i16> %r, <3 x i16> addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @srem_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x, <3 x i16> %y) { define amdgpu_kernel void @srem_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x, <3 x i16> %y) {
; CHECK-LABEL: @srem_v3i16( ; CHECK-LABEL: @srem_v3i16(
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines
; CHECK-NEXT: [[TMP76:%.*]] = ashr i32 [[TMP75]], 16 ; CHECK-NEXT: [[TMP76:%.*]] = ashr i32 [[TMP75]], 16
; CHECK-NEXT: [[TMP77:%.*]] = trunc i32 [[TMP76]] to i16 ; CHECK-NEXT: [[TMP77:%.*]] = trunc i32 [[TMP76]] to i16
; CHECK-NEXT: [[TMP78:%.*]] = insertelement <3 x i16> [[TMP52]], i16 [[TMP77]], i64 2 ; CHECK-NEXT: [[TMP78:%.*]] = insertelement <3 x i16> [[TMP52]], i16 [[TMP77]], i64 2
; CHECK-NEXT: store <3 x i16> [[TMP78]], <3 x i16> addrspace(1)* [[OUT:%.*]], align 8 ; CHECK-NEXT: store <3 x i16> [[TMP78]], <3 x i16> addrspace(1)* [[OUT:%.*]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; GFX6-LABEL: srem_v3i16: ; GFX6-LABEL: srem_v3i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd ; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
; GFX6-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0xb
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_sext_i32_i16 s2, s4
; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s2
; GFX6-NEXT: s_sext_i32_i16 s8, s6 ; GFX6-NEXT: s_sext_i32_i16 s8, s6
; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s8 ; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s8
; GFX6-NEXT: s_xor_b32 s2, s8, s2 ; GFX6-NEXT: s_sext_i32_i16 s9, s4
; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s9
; GFX6-NEXT: s_xor_b32 s8, s9, s8
; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0
; GFX6-NEXT: s_ashr_i32 s2, s2, 30 ; GFX6-NEXT: s_ashr_i32 s8, s8, 30
; GFX6-NEXT: s_or_b32 s2, s2, 1 ; GFX6-NEXT: s_or_b32 s8, s8, 1
; GFX6-NEXT: v_mov_b32_e32 v3, s2 ; GFX6-NEXT: v_mov_b32_e32 v3, s8
; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2 ; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2
; GFX6-NEXT: v_trunc_f32_e32 v2, v2 ; GFX6-NEXT: v_trunc_f32_e32 v2, v2
; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1
; GFX6-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GFX6-NEXT: v_cvt_i32_f32_e32 v2, v2
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| ; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; GFX6-NEXT: v_mov_b32_e32 v1, s6 ; GFX6-NEXT: v_mov_b32_e32 v1, s4
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_mov_b32_e32 v2, s4 ; GFX6-NEXT: v_mov_b32_e32 v2, s6
; GFX6-NEXT: v_alignbit_b32 v2, s5, v2, 16 ; GFX6-NEXT: v_alignbit_b32 v2, s7, v2, 16
; GFX6-NEXT: v_bfe_i32 v3, v2, 0, 16 ; GFX6-NEXT: v_bfe_i32 v3, v2, 0, 16
; GFX6-NEXT: v_cvt_f32_i32_e32 v4, v3 ; GFX6-NEXT: v_cvt_f32_i32_e32 v4, v3
; GFX6-NEXT: v_alignbit_b32 v1, s7, v1, 16 ; GFX6-NEXT: v_alignbit_b32 v1, s5, v1, 16
; GFX6-NEXT: v_bfe_i32 v5, v1, 0, 16 ; GFX6-NEXT: v_bfe_i32 v5, v1, 0, 16
; GFX6-NEXT: v_cvt_f32_i32_e32 v6, v5 ; GFX6-NEXT: v_cvt_f32_i32_e32 v6, v5
; GFX6-NEXT: v_rcp_iflag_f32_e32 v7, v4 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v7, v4
; GFX6-NEXT: v_mul_lo_u32 v0, v0, s4 ; GFX6-NEXT: v_mul_lo_u32 v0, v0, s6
; GFX6-NEXT: v_xor_b32_e32 v3, v5, v3 ; GFX6-NEXT: v_xor_b32_e32 v3, v5, v3
; GFX6-NEXT: s_sext_i32_i16 s4, s5 ; GFX6-NEXT: v_ashrrev_i32_e32 v3, 30, v3
; GFX6-NEXT: v_mul_f32_e32 v5, v6, v7 ; GFX6-NEXT: v_mul_f32_e32 v5, v6, v7
; GFX6-NEXT: v_trunc_f32_e32 v5, v5 ; GFX6-NEXT: v_trunc_f32_e32 v5, v5
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s6, v0 ; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
; GFX6-NEXT: v_mad_f32 v6, -v5, v4, v6 ; GFX6-NEXT: v_mad_f32 v6, -v5, v4, v6
; GFX6-NEXT: v_cvt_i32_f32_e32 v5, v5 ; GFX6-NEXT: v_cvt_i32_f32_e32 v5, v5
; GFX6-NEXT: v_ashrrev_i32_e32 v3, 30, v3 ; GFX6-NEXT: s_sext_i32_i16 s4, s7
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v6|, |v4| ; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v6|, |v4|
; GFX6-NEXT: v_cvt_f32_i32_e32 v4, s4 ; GFX6-NEXT: v_cvt_f32_i32_e32 v4, s4
; GFX6-NEXT: v_or_b32_e32 v3, 1, v3 ; GFX6-NEXT: v_or_b32_e32 v3, 1, v3
; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GFX6-NEXT: s_sext_i32_i16 s6, s7 ; GFX6-NEXT: s_sext_i32_i16 s6, s5
; GFX6-NEXT: v_mul_lo_u32 v2, v3, v2 ; GFX6-NEXT: v_mul_lo_u32 v2, v3, v2
; GFX6-NEXT: v_cvt_f32_i32_e32 v3, s6 ; GFX6-NEXT: v_cvt_f32_i32_e32 v3, s6
; GFX6-NEXT: v_rcp_iflag_f32_e32 v5, v4 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v5, v4
; GFX6-NEXT: s_xor_b32 s4, s6, s4 ; GFX6-NEXT: s_xor_b32 s4, s6, s4
; GFX6-NEXT: s_ashr_i32 s4, s4, 30 ; GFX6-NEXT: s_ashr_i32 s4, s4, 30
; GFX6-NEXT: s_or_b32 s4, s4, 1 ; GFX6-NEXT: s_or_b32 s4, s4, 1
; GFX6-NEXT: v_mul_f32_e32 v5, v3, v5 ; GFX6-NEXT: v_mul_f32_e32 v5, v3, v5
; GFX6-NEXT: v_trunc_f32_e32 v5, v5 ; GFX6-NEXT: v_trunc_f32_e32 v5, v5
; GFX6-NEXT: v_mad_f32 v3, -v5, v4, v3 ; GFX6-NEXT: v_mad_f32 v3, -v5, v4, v3
; GFX6-NEXT: v_cvt_i32_f32_e32 v5, v5 ; GFX6-NEXT: v_cvt_i32_f32_e32 v5, v5
; GFX6-NEXT: v_mov_b32_e32 v6, s4 ; GFX6-NEXT: v_mov_b32_e32 v6, s4
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v4| ; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v4|
; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v6, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v6, vcc
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GFX6-NEXT: v_mul_lo_u32 v3, v3, s5 ; GFX6-NEXT: v_mul_lo_u32 v3, v3, s7
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2 ; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s7, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s5, v3
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: buffer_store_short v2, off, s[0:3], 0 offset:4 ; GFX6-NEXT: buffer_store_short v2, off, s[0:3], 0 offset:4
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: srem_v3i16: ; GFX9-LABEL: srem_v3i16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_sext_i32_i16 s8, s2 ; GFX9-NEXT: s_sext_i32_i16 s8, s6
; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s8 ; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s8
; GFX9-NEXT: s_sext_i32_i16 s9, s4 ; GFX9-NEXT: s_sext_i32_i16 s9, s4
; GFX9-NEXT: v_cvt_f32_i32_e32 v1, s9 ; GFX9-NEXT: v_cvt_f32_i32_e32 v1, s9
; GFX9-NEXT: s_xor_b32 s6, s9, s8 ; GFX9-NEXT: s_xor_b32 s2, s9, s8
; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v0
; GFX9-NEXT: s_ashr_i32 s6, s6, 30 ; GFX9-NEXT: s_ashr_i32 s2, s2, 30
; GFX9-NEXT: s_or_b32 s10, s6, 1 ; GFX9-NEXT: s_or_b32 s10, s2, 1
; GFX9-NEXT: s_sext_i32_i16 s5, s5 ; GFX9-NEXT: s_sext_i32_i16 s7, s7
; GFX9-NEXT: v_mul_f32_e32 v2, v1, v2 ; GFX9-NEXT: v_mul_f32_e32 v2, v1, v2
; GFX9-NEXT: v_trunc_f32_e32 v2, v2 ; GFX9-NEXT: v_trunc_f32_e32 v2, v2
; GFX9-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GFX9-NEXT: v_mad_f32 v1, -v2, v0, v1
; GFX9-NEXT: v_cmp_ge_f32_e64 s[6:7], |v1|, |v0| ; GFX9-NEXT: v_cmp_ge_f32_e64 s[2:3], |v1|, |v0|
; GFX9-NEXT: s_and_b64 s[6:7], s[6:7], exec ; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
; GFX9-NEXT: s_cselect_b32 s6, s10, 0 ; GFX9-NEXT: s_cselect_b32 s2, s10, 0
; GFX9-NEXT: s_ashr_i32 s2, s2, 16 ; GFX9-NEXT: s_ashr_i32 s6, s6, 16
; GFX9-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GFX9-NEXT: v_cvt_i32_f32_e32 v2, v2
; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s2 ; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s6
; GFX9-NEXT: s_ashr_i32 s4, s4, 16 ; GFX9-NEXT: s_ashr_i32 s4, s4, 16
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX9-NEXT: s_sext_i32_i16 s5, s5
; GFX9-NEXT: v_add_u32_e32 v1, s6, v2 ; GFX9-NEXT: v_add_u32_e32 v1, s2, v2
; GFX9-NEXT: v_cvt_f32_i32_e32 v2, s4 ; GFX9-NEXT: v_cvt_f32_i32_e32 v2, s4
; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v0
; GFX9-NEXT: s_xor_b32 s6, s4, s2 ; GFX9-NEXT: s_xor_b32 s2, s4, s6
; GFX9-NEXT: s_ashr_i32 s6, s6, 30 ; GFX9-NEXT: s_ashr_i32 s2, s2, 30
; GFX9-NEXT: v_mul_lo_u32 v1, v1, s8 ; GFX9-NEXT: v_mul_lo_u32 v1, v1, s8
; GFX9-NEXT: v_mul_f32_e32 v3, v2, v3 ; GFX9-NEXT: v_mul_f32_e32 v3, v2, v3
; GFX9-NEXT: v_trunc_f32_e32 v3, v3 ; GFX9-NEXT: v_trunc_f32_e32 v3, v3
; GFX9-NEXT: v_mad_f32 v2, -v3, v0, v2 ; GFX9-NEXT: v_mad_f32 v2, -v3, v0, v2
; GFX9-NEXT: s_or_b32 s8, s2, 1
; GFX9-NEXT: v_cvt_i32_f32_e32 v3, v3 ; GFX9-NEXT: v_cvt_i32_f32_e32 v3, v3
; GFX9-NEXT: s_or_b32 s8, s6, 1 ; GFX9-NEXT: v_cmp_ge_f32_e64 s[2:3], |v2|, |v0|
; GFX9-NEXT: v_cmp_ge_f32_e64 s[6:7], |v2|, |v0| ; GFX9-NEXT: v_cvt_f32_i32_e32 v2, s7
; GFX9-NEXT: s_and_b64 s[6:7], s[6:7], exec ; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
; GFX9-NEXT: s_cselect_b32 s6, s8, 0 ; GFX9-NEXT: s_cselect_b32 s2, s8, 0
; GFX9-NEXT: v_add_u32_e32 v0, s6, v3 ; GFX9-NEXT: v_add_u32_e32 v0, s2, v3
; GFX9-NEXT: s_sext_i32_i16 s6, s3
; GFX9-NEXT: v_cvt_f32_i32_e32 v2, s6
; GFX9-NEXT: v_cvt_f32_i32_e32 v3, s5 ; GFX9-NEXT: v_cvt_f32_i32_e32 v3, s5
; GFX9-NEXT: v_mul_lo_u32 v0, v0, s2
; GFX9-NEXT: s_xor_b32 s2, s5, s6
; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v2 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v2
; GFX9-NEXT: s_xor_b32 s2, s5, s7
; GFX9-NEXT: s_ashr_i32 s2, s2, 30 ; GFX9-NEXT: s_ashr_i32 s2, s2, 30
; GFX9-NEXT: s_or_b32 s7, s2, 1 ; GFX9-NEXT: v_mul_lo_u32 v0, v0, s6
; GFX9-NEXT: v_sub_u32_e32 v1, s9, v1
; GFX9-NEXT: v_mul_f32_e32 v4, v3, v4 ; GFX9-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX9-NEXT: v_trunc_f32_e32 v4, v4 ; GFX9-NEXT: v_trunc_f32_e32 v4, v4
; GFX9-NEXT: v_mad_f32 v3, -v4, v2, v3 ; GFX9-NEXT: v_mad_f32 v3, -v4, v2, v3
; GFX9-NEXT: v_cvt_i32_f32_e32 v4, v4 ; GFX9-NEXT: v_cvt_i32_f32_e32 v4, v4
; GFX9-NEXT: s_or_b32 s6, s2, 1
; GFX9-NEXT: v_cmp_ge_f32_e64 s[2:3], |v3|, |v2| ; GFX9-NEXT: v_cmp_ge_f32_e64 s[2:3], |v3|, |v2|
; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec ; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
; GFX9-NEXT: s_cselect_b32 s2, s7, 0 ; GFX9-NEXT: s_cselect_b32 s2, s6, 0
; GFX9-NEXT: v_add_u32_e32 v2, s2, v4 ; GFX9-NEXT: v_add_u32_e32 v2, s2, v4
; GFX9-NEXT: v_mul_lo_u32 v2, v2, s6 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: v_mul_lo_u32 v2, v2, s7
; GFX9-NEXT: v_sub_u32_e32 v1, s9, v1
; GFX9-NEXT: v_mov_b32_e32 v3, 0 ; GFX9-NEXT: v_mov_b32_e32 v3, 0
; GFX9-NEXT: v_sub_u32_e32 v0, s4, v0 ; GFX9-NEXT: v_sub_u32_e32 v0, s4, v0
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX9-NEXT: v_sub_u32_e32 v2, s5, v2 ; GFX9-NEXT: v_sub_u32_e32 v2, s5, v2
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v1 ; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_short v3, v2, s[0:1] offset:4 ; GFX9-NEXT: global_store_short v3, v2, s[0:1] offset:4
; GFX9-NEXT: global_store_dword v3, v0, s[0:1] ; GFX9-NEXT: global_store_dword v3, v0, s[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%r = srem <3 x i16> %x, %y %r = srem <3 x i16> %x, %y
store <3 x i16> %r, <3 x i16> addrspace(1)* %out store <3 x i16> %r, <3 x i16> addrspace(1)* %out
ret void ret void
▲ Show 20 Lines • Show All 1,137 Lines • ▼ Show 20 Lines
; CHECK-NEXT: [[TMP62:%.*]] = add i32 [[TMP58]], 1 ; CHECK-NEXT: [[TMP62:%.*]] = add i32 [[TMP58]], 1
; CHECK-NEXT: [[TMP63:%.*]] = select i1 [[TMP61]], i32 [[TMP62]], i32 [[TMP58]] ; CHECK-NEXT: [[TMP63:%.*]] = select i1 [[TMP61]], i32 [[TMP62]], i32 [[TMP58]]
; CHECK-NEXT: [[TMP64:%.*]] = insertelement <2 x i32> [[TMP32]], i32 [[TMP63]], i64 1 ; CHECK-NEXT: [[TMP64:%.*]] = insertelement <2 x i32> [[TMP32]], i32 [[TMP63]], i64 1
; CHECK-NEXT: store <2 x i32> [[TMP64]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8 ; CHECK-NEXT: store <2 x i32> [[TMP64]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; GFX6-LABEL: udiv_v2i32_pow2_shl_denom: ; GFX6-LABEL: udiv_v2i32_pow2_shl_denom:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd ; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
; GFX6-NEXT: s_movk_i32 s4, 0x1000 ; GFX6-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9
; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: s_movk_i32 s2, 0x1000
; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: s_mov_b32 s0, 0x4f7ffffe
; GFX6-NEXT: s_mov_b32 s11, 0xf000
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_lshl_b32 s8, s4, s2 ; GFX6-NEXT: s_lshl_b32 s3, s2, s6
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s8 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s3
; GFX6-NEXT: s_lshl_b32 s9, s4, s3 ; GFX6-NEXT: s_lshl_b32 s2, s2, s7
; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s9 ; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s2
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; GFX6-NEXT: s_mov_b32 s10, -1
; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX6-NEXT: s_mov_b32 s0, 0x4f7ffffe
; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX6-NEXT: v_mul_f32_e32 v0, s0, v0 ; GFX6-NEXT: v_mul_f32_e32 v0, s0, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: v_mul_f32_e32 v1, s0, v1 ; GFX6-NEXT: v_mul_f32_e32 v1, s0, v1
; GFX6-NEXT: s_sub_i32 s0, 0, s8 ; GFX6-NEXT: s_sub_i32 s0, 0, s3
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: v_mul_lo_u32 v2, s0, v0 ; GFX6-NEXT: v_mul_lo_u32 v2, s0, v0
; GFX6-NEXT: s_sub_i32 s0, 0, s9 ; GFX6-NEXT: s_sub_i32 s0, 0, s2
; GFX6-NEXT: v_mul_lo_u32 v3, s0, v1 ; GFX6-NEXT: v_mul_lo_u32 v3, s0, v1
; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2 ; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v0
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s2, v0
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v3, v1 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v3, v1
; GFX6-NEXT: v_mul_hi_u32 v1, s3, v1 ; GFX6-NEXT: v_mul_hi_u32 v1, s5, v1
; GFX6-NEXT: v_mul_lo_u32 v2, v0, s8 ; GFX6-NEXT: v_mul_lo_u32 v2, v0, s3
; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v0 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v0
; GFX6-NEXT: v_mul_lo_u32 v4, v1, s9 ; GFX6-NEXT: v_mul_lo_u32 v4, v1, s2
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s2, v2 ; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s4, v2
; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v2 ; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v2
; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1]
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s8, v2 ; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s3, v2
; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v0 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v0
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v2 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v2
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s3, v4 ; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s5, v4
; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v1 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v1
; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v2 ; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v2
; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s9, v2 ; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s2, v2
; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v1 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v1
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s9, v2 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s2, v2
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: udiv_v2i32_pow2_shl_denom: ; GFX9-LABEL: udiv_v2i32_pow2_shl_denom:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
; GFX9-NEXT: s_movk_i32 s4, 0x1000 ; GFX9-NEXT: s_movk_i32 s2, 0x1000
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshl_b32 s5, s4, s3 ; GFX9-NEXT: s_lshl_b32 s6, s2, s6
; GFX9-NEXT: s_lshl_b32 s4, s4, s2 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s6
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s4 ; GFX9-NEXT: s_lshl_b32 s7, s2, s7
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s5 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s7
; GFX9-NEXT: s_mov_b32 s2, 0x4f7ffffe ; GFX9-NEXT: s_mov_b32 s2, 0x4f7ffffe
; GFX9-NEXT: s_sub_i32 s3, 0, s5
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: s_sub_i32 s3, 0, s7
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX9-NEXT: v_mul_f32_e32 v0, s2, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, s2, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v1, s2, v1 ; GFX9-NEXT: v_mul_f32_e32 v1, s2, v1
; GFX9-NEXT: s_sub_i32 s2, 0, s4
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: s_sub_i32 s2, 0, s6
; GFX9-NEXT: v_mul_lo_u32 v2, s2, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, s2, v0
; GFX9-NEXT: v_mul_lo_u32 v3, s3, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, s3, v1
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX9-NEXT: v_add_u32_e32 v0, v0, v2 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX9-NEXT: v_mul_hi_u32 v0, s2, v0
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_mul_hi_u32 v1, s3, v1 ; GFX9-NEXT: v_mul_hi_u32 v1, s5, v1
; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: v_mul_lo_u32 v3, v0, s4 ; GFX9-NEXT: v_mul_lo_u32 v3, v0, s6
; GFX9-NEXT: v_add_u32_e32 v5, 1, v0 ; GFX9-NEXT: v_add_u32_e32 v5, 1, v0
; GFX9-NEXT: v_mul_lo_u32 v4, v1, s5 ; GFX9-NEXT: v_mul_lo_u32 v4, v1, s7
; GFX9-NEXT: v_add_u32_e32 v6, 1, v1 ; GFX9-NEXT: v_add_u32_e32 v6, 1, v1
; GFX9-NEXT: v_sub_u32_e32 v3, s2, v3 ; GFX9-NEXT: v_sub_u32_e32 v3, s4, v3
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v3
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
; GFX9-NEXT: v_subrev_u32_e32 v5, s4, v3 ; GFX9-NEXT: v_subrev_u32_e32 v5, s6, v3
; GFX9-NEXT: v_sub_u32_e32 v4, s5, v4
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX9-NEXT: v_sub_u32_e32 v4, s3, v4 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s7, v4
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v3
; GFX9-NEXT: v_subrev_u32_e32 v3, s7, v4
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[0:1]
; GFX9-NEXT: v_add_u32_e32 v5, 1, v0 ; GFX9-NEXT: v_add_u32_e32 v5, 1, v0
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v3 ; GFX9-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s5, v4
; GFX9-NEXT: v_subrev_u32_e32 v3, s5, v4
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX9-NEXT: v_add_u32_e32 v4, 1, v1 ; GFX9-NEXT: v_add_u32_e32 v4, 1, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s5, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v3
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y %shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y
%r = udiv <2 x i32> %x, %shl.y %r = udiv <2 x i32> %x, %shl.y
store <2 x i32> %r, <2 x i32> addrspace(1)* %out store <2 x i32> %r, <2 x i32> addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @urem_i32_oddk_denom(i32 addrspace(1)* %out, i32 %x) { define amdgpu_kernel void @urem_i32_oddk_denom(i32 addrspace(1)* %out, i32 %x) {
▲ Show 20 Lines • Show All 221 Lines • ▼ Show 20 Lines
; CHECK-NEXT: [[TMP58:%.*]] = sub i32 [[TMP56]], [[TMP32]] ; CHECK-NEXT: [[TMP58:%.*]] = sub i32 [[TMP56]], [[TMP32]]
; CHECK-NEXT: [[TMP59:%.*]] = select i1 [[TMP57]], i32 [[TMP58]], i32 [[TMP56]] ; CHECK-NEXT: [[TMP59:%.*]] = select i1 [[TMP57]], i32 [[TMP58]], i32 [[TMP56]]
; CHECK-NEXT: [[TMP60:%.*]] = insertelement <2 x i32> [[TMP30]], i32 [[TMP59]], i64 1 ; CHECK-NEXT: [[TMP60:%.*]] = insertelement <2 x i32> [[TMP30]], i32 [[TMP59]], i64 1
; CHECK-NEXT: store <2 x i32> [[TMP60]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8 ; CHECK-NEXT: store <2 x i32> [[TMP60]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; GFX6-LABEL: urem_v2i32_pow2_shl_denom: ; GFX6-LABEL: urem_v2i32_pow2_shl_denom:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd ; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
; GFX6-NEXT: s_movk_i32 s4, 0x1000 ; GFX6-NEXT: s_movk_i32 s2, 0x1000
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_lshl_b32 s6, s4, s2 ; GFX6-NEXT: s_lshl_b32 s6, s2, s6
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s6 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s6
; GFX6-NEXT: s_lshl_b32 s7, s4, s3 ; GFX6-NEXT: s_lshl_b32 s7, s2, s7
; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s7 ; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s7
; GFX6-NEXT: s_mov_b32 s2, 0x4f7ffffe ; GFX6-NEXT: s_mov_b32 s2, 0x4f7ffffe
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb
; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GFX6-NEXT: v_mul_f32_e32 v0, s2, v0 ; GFX6-NEXT: v_mul_f32_e32 v0, s2, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: v_mul_f32_e32 v1, s2, v1 ; GFX6-NEXT: v_mul_f32_e32 v1, s2, v1
; GFX6-NEXT: s_sub_i32 s2, 0, s6 ; GFX6-NEXT: s_sub_i32 s2, 0, s6
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: v_mul_lo_u32 v2, s2, v0 ; GFX6-NEXT: v_mul_lo_u32 v2, s2, v0
; GFX6-NEXT: s_sub_i32 s2, 0, s7 ; GFX6-NEXT: s_sub_i32 s2, 0, s7
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: v_mul_lo_u32 v3, s2, v1 ; GFX6-NEXT: v_mul_lo_u32 v3, s2, v1
; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2 ; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX6-NEXT: s_mov_b32 s2, -1 ; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mul_hi_u32 v0, s4, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v3, v1 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v3, v1
; GFX6-NEXT: v_mul_hi_u32 v1, s5, v1 ; GFX6-NEXT: v_mul_hi_u32 v1, s5, v1
; GFX6-NEXT: v_mul_lo_u32 v0, v0, s6 ; GFX6-NEXT: v_mul_lo_u32 v0, v0, s6
; GFX6-NEXT: v_mul_lo_u32 v1, v1, s7 ; GFX6-NEXT: v_mul_lo_u32 v1, v1, s7
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0 ; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s6, v0 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s6, v0
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s6, v0 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s6, v0 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s6, v0
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s6, v0 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s5, v1 ; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s5, v1
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s7, v1 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s7, v1
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s7, v1 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s7, v1 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s7, v1
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s7, v1 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: urem_v2i32_pow2_shl_denom: ; GFX9-LABEL: urem_v2i32_pow2_shl_denom:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
; GFX9-NEXT: s_movk_i32 s4, 0x1000 ; GFX9-NEXT: s_movk_i32 s2, 0x1000
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshl_b32 s5, s4, s3 ; GFX9-NEXT: s_lshl_b32 s3, s2, s7
; GFX9-NEXT: s_lshl_b32 s4, s4, s2 ; GFX9-NEXT: s_lshl_b32 s2, s2, s6
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s4 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s5 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s3
; GFX9-NEXT: s_mov_b32 s2, 0x4f7ffffe ; GFX9-NEXT: s_mov_b32 s6, 0x4f7ffffe
; GFX9-NEXT: s_sub_i32 s3, 0, s5 ; GFX9-NEXT: s_sub_i32 s7, 0, s3
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX9-NEXT: v_mul_f32_e32 v0, s2, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, s6, v0
; GFX9-NEXT: v_mul_f32_e32 v1, s2, v1 ; GFX9-NEXT: v_mul_f32_e32 v1, s6, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: s_sub_i32 s2, 0, s4 ; GFX9-NEXT: s_sub_i32 s6, 0, s2
; GFX9-NEXT: v_mul_lo_u32 v2, s2, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, s6, v0
; GFX9-NEXT: v_mul_lo_u32 v3, s3, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, s7, v1
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: v_add_u32_e32 v0, v0, v2 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX9-NEXT: v_mul_hi_u32 v0, s2, v0 ; GFX9-NEXT: v_mul_hi_u32 v1, s5, v1
; GFX9-NEXT: v_mul_hi_u32 v1, s3, v1
; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: v_mul_lo_u32 v0, v0, s4 ; GFX9-NEXT: v_mul_lo_u32 v0, v0, s2
; GFX9-NEXT: v_mul_lo_u32 v1, v1, s5 ; GFX9-NEXT: v_mul_lo_u32 v1, v1, s3
; GFX9-NEXT: v_sub_u32_e32 v0, s2, v0 ; GFX9-NEXT: v_sub_u32_e32 v0, s4, v0
; GFX9-NEXT: v_sub_u32_e32 v1, s3, v1 ; GFX9-NEXT: v_sub_u32_e32 v1, s5, v1
; GFX9-NEXT: v_subrev_u32_e32 v3, s4, v0 ; GFX9-NEXT: v_subrev_u32_e32 v3, s2, v0
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v0 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v0
; GFX9-NEXT: v_subrev_u32_e32 v4, s5, v1 ; GFX9-NEXT: v_subrev_u32_e32 v4, s3, v1
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s5, v1 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX9-NEXT: v_subrev_u32_e32 v3, s4, v0 ; GFX9-NEXT: v_subrev_u32_e32 v3, s2, v0
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v0 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v0
; GFX9-NEXT: v_subrev_u32_e32 v4, s5, v1 ; GFX9-NEXT: v_subrev_u32_e32 v4, s3, v1
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s5, v1 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y %shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y
%r = urem <2 x i32> %x, %shl.y %r = urem <2 x i32> %x, %shl.y
store <2 x i32> %r, <2 x i32> addrspace(1)* %out store <2 x i32> %r, <2 x i32> addrspace(1)* %out
ret void ret void
} }
▲ Show 20 Lines • Show All 363 Lines • ▼ Show 20 Lines
; CHECK-NEXT: [[TMP80:%.*]] = xor i32 [[TMP79]], [[TMP46]] ; CHECK-NEXT: [[TMP80:%.*]] = xor i32 [[TMP79]], [[TMP46]]
; CHECK-NEXT: [[TMP81:%.*]] = sub i32 [[TMP80]], [[TMP46]] ; CHECK-NEXT: [[TMP81:%.*]] = sub i32 [[TMP80]], [[TMP46]]
; CHECK-NEXT: [[TMP82:%.*]] = insertelement <2 x i32> [[TMP41]], i32 [[TMP81]], i64 1 ; CHECK-NEXT: [[TMP82:%.*]] = insertelement <2 x i32> [[TMP41]], i32 [[TMP81]], i64 1
; CHECK-NEXT: store <2 x i32> [[TMP82]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8 ; CHECK-NEXT: store <2 x i32> [[TMP82]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; GFX6-LABEL: sdiv_v2i32_pow2_shl_denom: ; GFX6-LABEL: sdiv_v2i32_pow2_shl_denom:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd ; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
; GFX6-NEXT: s_movk_i32 s10, 0x1000 ; GFX6-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9
; GFX6-NEXT: s_movk_i32 s2, 0x1000
; GFX6-NEXT: s_mov_b32 s12, 0x4f7ffffe ; GFX6-NEXT: s_mov_b32 s12, 0x4f7ffffe
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; GFX6-NEXT: s_mov_b32 s11, 0xf000
; GFX6-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xb
; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_lshl_b32 s2, s10, s2 ; GFX6-NEXT: s_lshl_b32 s3, s2, s6
; GFX6-NEXT: s_ashr_i32 s11, s2, 31 ; GFX6-NEXT: s_ashr_i32 s6, s3, 31
; GFX6-NEXT: s_add_i32 s2, s2, s11 ; GFX6-NEXT: s_add_i32 s3, s3, s6
; GFX6-NEXT: s_xor_b32 s2, s2, s11 ; GFX6-NEXT: s_xor_b32 s3, s3, s6
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s2 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s3
; GFX6-NEXT: s_lshl_b32 s0, s10, s3 ; GFX6-NEXT: s_lshl_b32 s0, s2, s7
; GFX6-NEXT: s_sub_i32 s10, 0, s2 ; GFX6-NEXT: s_sub_i32 s7, 0, s3
; GFX6-NEXT: s_ashr_i32 s3, s0, 31 ; GFX6-NEXT: s_ashr_i32 s2, s0, 31
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX6-NEXT: s_add_i32 s0, s0, s3 ; GFX6-NEXT: s_add_i32 s0, s0, s2
; GFX6-NEXT: s_ashr_i32 s1, s8, 31 ; GFX6-NEXT: s_ashr_i32 s1, s4, 31
; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: s_mov_b32 s10, -1
; GFX6-NEXT: v_mul_f32_e32 v0, s12, v0 ; GFX6-NEXT: v_mul_f32_e32 v0, s12, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: v_mul_lo_u32 v1, s10, v0 ; GFX6-NEXT: v_mul_lo_u32 v1, s7, v0
; GFX6-NEXT: s_xor_b32 s10, s0, s3 ; GFX6-NEXT: s_xor_b32 s7, s0, s2
; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s10 ; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s7
; GFX6-NEXT: s_add_i32 s0, s8, s1 ; GFX6-NEXT: s_add_i32 s0, s4, s1
; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX6-NEXT: s_xor_b32 s0, s0, s1 ; GFX6-NEXT: s_xor_b32 s0, s0, s1
; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX6-NEXT: s_xor_b32 s8, s1, s11 ; GFX6-NEXT: s_xor_b32 s4, s1, s6
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s0, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s0, v0
; GFX6-NEXT: v_mul_f32_e32 v1, s12, v2 ; GFX6-NEXT: v_mul_f32_e32 v1, s12, v2
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: v_mul_lo_u32 v2, v0, s2 ; GFX6-NEXT: v_mul_lo_u32 v2, v0, s3
; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v0 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v0
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s0, v2 ; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s0, v2
; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v2 ; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v2
; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1]
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s2, v2 ; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s3, v2
; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
; GFX6-NEXT: s_sub_i32 s0, 0, s10 ; GFX6-NEXT: s_sub_i32 s0, 0, s7
; GFX6-NEXT: v_mul_lo_u32 v3, s0, v1 ; GFX6-NEXT: v_mul_lo_u32 v3, s0, v1
; GFX6-NEXT: s_ashr_i32 s0, s9, 31 ; GFX6-NEXT: s_ashr_i32 s0, s5, 31
; GFX6-NEXT: s_add_i32 s1, s9, s0 ; GFX6-NEXT: s_add_i32 s1, s5, s0
; GFX6-NEXT: s_xor_b32 s1, s1, s0 ; GFX6-NEXT: s_xor_b32 s1, s1, s0
; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v0 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v0
; GFX6-NEXT: s_xor_b32 s2, s0, s2
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v3, v1 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v3, v1
; GFX6-NEXT: v_mul_hi_u32 v1, s1, v1 ; GFX6-NEXT: v_mul_hi_u32 v1, s1, v1
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s2, v2 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v2
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX6-NEXT: s_xor_b32 s2, s0, s3 ; GFX6-NEXT: v_xor_b32_e32 v0, s4, v0
; GFX6-NEXT: v_mul_lo_u32 v2, v1, s10 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, s7
; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v1 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v1
; GFX6-NEXT: v_xor_b32_e32 v0, s8, v0 ; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s4, v0
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s1, v2 ; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s1, v2
; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v2 ; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s7, v2
; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s10, v2 ; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s7, v2
; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s8, v0
; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v1 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v1
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s10, v2 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s7, v2
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX6-NEXT: v_xor_b32_e32 v1, s2, v1 ; GFX6-NEXT: v_xor_b32_e32 v1, s2, v1
; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s2, v1 ; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s2, v1
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: sdiv_v2i32_pow2_shl_denom: ; GFX9-LABEL: sdiv_v2i32_pow2_shl_denom:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
; GFX9-NEXT: s_movk_i32 s8, 0x1000 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX9-NEXT: s_movk_i32 s0, 0x1000
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x2c
; GFX9-NEXT: s_mov_b32 s10, 0x4f7ffffe ; GFX9-NEXT: s_mov_b32 s10, 0x4f7ffffe
; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshl_b32 s2, s8, s2 ; GFX9-NEXT: s_lshl_b32 s1, s0, s6
; GFX9-NEXT: s_ashr_i32 s9, s2, 31 ; GFX9-NEXT: s_ashr_i32 s6, s1, 31
; GFX9-NEXT: s_add_i32 s2, s2, s9 ; GFX9-NEXT: s_add_i32 s1, s1, s6
; GFX9-NEXT: s_xor_b32 s2, s2, s9 ; GFX9-NEXT: s_xor_b32 s1, s1, s6
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s2 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s1
; GFX9-NEXT: s_lshl_b32 s0, s8, s3 ; GFX9-NEXT: s_lshl_b32 s0, s0, s7
; GFX9-NEXT: s_ashr_i32 s1, s0, 31 ; GFX9-NEXT: s_ashr_i32 s8, s0, 31
; GFX9-NEXT: s_add_i32 s0, s0, s1 ; GFX9-NEXT: s_add_i32 s0, s0, s8
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: s_xor_b32 s0, s0, s1 ; GFX9-NEXT: s_xor_b32 s0, s0, s8
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s0 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s0
; GFX9-NEXT: s_sub_i32 s3, 0, s2 ; GFX9-NEXT: s_sub_i32 s9, 0, s1
; GFX9-NEXT: v_mul_f32_e32 v0, s10, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, s10, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX9-NEXT: s_sub_i32 s8, 0, s0 ; GFX9-NEXT: s_ashr_i32 s7, s4, 31
; GFX9-NEXT: v_mul_lo_u32 v3, s3, v0 ; GFX9-NEXT: s_add_i32 s4, s4, s7
; GFX9-NEXT: v_mul_lo_u32 v3, s9, v0
; GFX9-NEXT: v_mul_f32_e32 v1, s10, v1 ; GFX9-NEXT: v_mul_f32_e32 v1, s10, v1
; GFX9-NEXT: s_ashr_i32 s3, s6, 31
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: s_xor_b32 s4, s4, s7
; GFX9-NEXT: v_mul_hi_u32 v3, v0, v3 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, v3
; GFX9-NEXT: s_add_i32 s6, s6, s3 ; GFX9-NEXT: s_sub_i32 s10, 0, s0
; GFX9-NEXT: s_xor_b32 s6, s6, s3 ; GFX9-NEXT: s_ashr_i32 s9, s5, 31
; GFX9-NEXT: s_xor_b32 s3, s3, s9 ; GFX9-NEXT: s_add_i32 s5, s5, s9
; GFX9-NEXT: v_add_u32_e32 v0, v0, v3 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v3
; GFX9-NEXT: v_mul_hi_u32 v0, s6, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX9-NEXT: v_mul_lo_u32 v3, s8, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, s10, v1
; GFX9-NEXT: s_ashr_i32 s8, s7, 31 ; GFX9-NEXT: s_xor_b32 s6, s7, s6
; GFX9-NEXT: s_xor_b32 s1, s8, s1 ; GFX9-NEXT: v_mul_lo_u32 v4, v0, s1
; GFX9-NEXT: v_mul_lo_u32 v4, v0, s2
; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX9-NEXT: v_add_u32_e32 v5, 1, v0 ; GFX9-NEXT: v_add_u32_e32 v5, 1, v0
; GFX9-NEXT: v_sub_u32_e32 v4, s6, v4 ; GFX9-NEXT: v_sub_u32_e32 v4, s4, v4
; GFX9-NEXT: s_add_i32 s6, s7, s8 ; GFX9-NEXT: s_xor_b32 s4, s5, s9
; GFX9-NEXT: s_xor_b32 s6, s6, s8
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v4 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s1, v4
; GFX9-NEXT: v_mul_hi_u32 v1, s6, v1 ; GFX9-NEXT: v_mul_hi_u32 v1, s4, v1
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
; GFX9-NEXT: v_subrev_u32_e32 v5, s2, v4 ; GFX9-NEXT: v_subrev_u32_e32 v5, s1, v4
; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
; GFX9-NEXT: v_add_u32_e32 v3, 1, v0 ; GFX9-NEXT: v_add_u32_e32 v3, 1, v0
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v4 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s1, v4
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: v_mul_lo_u32 v3, v1, s0 ; GFX9-NEXT: v_mul_lo_u32 v3, v1, s0
; GFX9-NEXT: v_add_u32_e32 v4, 1, v1 ; GFX9-NEXT: v_add_u32_e32 v4, 1, v1
; GFX9-NEXT: v_xor_b32_e32 v0, s3, v0 ; GFX9-NEXT: s_xor_b32 s1, s9, s8
; GFX9-NEXT: v_subrev_u32_e32 v0, s3, v0 ; GFX9-NEXT: v_xor_b32_e32 v0, s6, v0
; GFX9-NEXT: v_sub_u32_e32 v3, s6, v3 ; GFX9-NEXT: v_sub_u32_e32 v3, s4, v3
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s0, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s0, v3
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX9-NEXT: v_subrev_u32_e32 v4, s0, v3 ; GFX9-NEXT: v_subrev_u32_e32 v4, s0, v3
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX9-NEXT: v_add_u32_e32 v4, 1, v1 ; GFX9-NEXT: v_add_u32_e32 v4, 1, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s0, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s0, v3
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX9-NEXT: v_xor_b32_e32 v1, s1, v1 ; GFX9-NEXT: v_xor_b32_e32 v1, s1, v1
; GFX9-NEXT: v_subrev_u32_e32 v0, s6, v0
; GFX9-NEXT: v_subrev_u32_e32 v1, s1, v1 ; GFX9-NEXT: v_subrev_u32_e32 v1, s1, v1
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5] ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y %shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y
%r = sdiv <2 x i32> %x, %shl.y %r = sdiv <2 x i32> %x, %shl.y
store <2 x i32> %r, <2 x i32> addrspace(1)* %out store <2 x i32> %r, <2 x i32> addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @srem_i32_oddk_denom(i32 addrspace(1)* %out, i32 %x) { define amdgpu_kernel void @srem_i32_oddk_denom(i32 addrspace(1)* %out, i32 %x) {
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; CHECK-NEXT: [[TMP74:%.*]] = xor i32 [[TMP73]], [[TMP41]] ; CHECK-NEXT: [[TMP74:%.*]] = xor i32 [[TMP73]], [[TMP41]]
; CHECK-NEXT: [[TMP75:%.*]] = sub i32 [[TMP74]], [[TMP41]] ; CHECK-NEXT: [[TMP75:%.*]] = sub i32 [[TMP74]], [[TMP41]]
; CHECK-NEXT: [[TMP76:%.*]] = insertelement <2 x i32> [[TMP38]], i32 [[TMP75]], i64 1 ; CHECK-NEXT: [[TMP76:%.*]] = insertelement <2 x i32> [[TMP38]], i32 [[TMP75]], i64 1
; CHECK-NEXT: store <2 x i32> [[TMP76]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8 ; CHECK-NEXT: store <2 x i32> [[TMP76]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; GFX6-LABEL: srem_v2i32_pow2_shl_denom: ; GFX6-LABEL: srem_v2i32_pow2_shl_denom:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd ; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
; GFX6-NEXT: s_movk_i32 s6, 0x1000 ; GFX6-NEXT: s_movk_i32 s8, 0x1000
; GFX6-NEXT: s_mov_b32 s10, 0x4f7ffffe ; GFX6-NEXT: s_mov_b32 s11, 0x4f7ffffe
; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_lshl_b32 s2, s6, s2 ; GFX6-NEXT: s_lshl_b32 s2, s8, s6
; GFX6-NEXT: s_ashr_i32 s4, s2, 31 ; GFX6-NEXT: s_ashr_i32 s3, s2, 31
; GFX6-NEXT: s_add_i32 s2, s2, s4 ; GFX6-NEXT: s_add_i32 s2, s2, s3
; GFX6-NEXT: s_xor_b32 s2, s2, s4 ; GFX6-NEXT: s_xor_b32 s6, s2, s3
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s2 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s6
; GFX6-NEXT: s_lshl_b32 s3, s6, s3 ; GFX6-NEXT: s_lshl_b32 s7, s8, s7
; GFX6-NEXT: s_ashr_i32 s6, s3, 31 ; GFX6-NEXT: s_ashr_i32 s9, s7, 31
; GFX6-NEXT: s_add_i32 s3, s3, s6 ; GFX6-NEXT: s_add_i32 s7, s7, s9
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX6-NEXT: s_sub_i32 s9, 0, s2 ; GFX6-NEXT: s_sub_i32 s10, 0, s6
; GFX6-NEXT: s_xor_b32 s3, s3, s6 ; GFX6-NEXT: s_xor_b32 s7, s7, s9
; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s3 ; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s7
; GFX6-NEXT: v_mul_f32_e32 v0, s10, v0 ; GFX6-NEXT: v_mul_f32_e32 v0, s11, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; GFX6-NEXT: s_ashr_i32 s8, s4, 31
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: s_add_i32 s4, s4, s8
; GFX6-NEXT: v_mul_lo_u32 v1, s9, v0 ; GFX6-NEXT: v_mul_lo_u32 v1, s10, v0
; GFX6-NEXT: s_sub_i32 s9, 0, s3 ; GFX6-NEXT: s_xor_b32 s4, s4, s8
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_sub_i32 s10, 0, s7
; GFX6-NEXT: s_ashr_i32 s8, s0, 31 ; GFX6-NEXT: s_ashr_i32 s9, s5, 31
; GFX6-NEXT: s_add_i32 s0, s0, s8
; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX6-NEXT: s_xor_b32 s0, s0, s8 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
; GFX6-NEXT: v_mul_f32_e32 v1, s10, v2 ; GFX6-NEXT: v_mul_f32_e32 v1, s11, v2
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: v_mul_hi_u32 v0, s0, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX6-NEXT: v_mul_lo_u32 v2, s9, v1 ; GFX6-NEXT: v_mul_lo_u32 v2, s10, v1
; GFX6-NEXT: v_mul_lo_u32 v0, v0, s2 ; GFX6-NEXT: v_mul_lo_u32 v0, v0, s6
; GFX6-NEXT: v_mul_hi_u32 v2, v1, v2 ; GFX6-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0 ; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s2, v0 ; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s6, v0
; GFX6-NEXT: s_ashr_i32 s0, s1, 31 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s2, v0 ; GFX6-NEXT: s_add_i32 s4, s5, s9
; GFX6-NEXT: s_add_i32 s1, s1, s0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX6-NEXT: s_xor_b32 s1, s1, s0 ; GFX6-NEXT: s_xor_b32 s4, s4, s9
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GFX6-NEXT: v_mul_hi_u32 v1, s1, v1 ; GFX6-NEXT: v_mul_hi_u32 v1, s4, v1
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s2, v0 ; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s6, v0
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s2, v0 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
; GFX6-NEXT: v_mul_lo_u32 v1, v1, s3 ; GFX6-NEXT: v_mul_lo_u32 v1, v1, s7
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX6-NEXT: v_xor_b32_e32 v0, s8, v0 ; GFX6-NEXT: v_xor_b32_e32 v0, s8, v0
; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s8, v0 ; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s8, v0
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s1, v1 ; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s4, v1
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s3, v1 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s7, v1
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v1 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s3, v1 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s7, v1
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v1 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX6-NEXT: v_xor_b32_e32 v1, s0, v1 ; GFX6-NEXT: v_xor_b32_e32 v1, s9, v1
; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s0, v1 ; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s9, v1
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: srem_v2i32_pow2_shl_denom: ; GFX9-LABEL: srem_v2i32_pow2_shl_denom:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x2c
; GFX9-NEXT: s_movk_i32 s0, 0x1000 ; GFX9-NEXT: s_movk_i32 s0, 0x1000
; GFX9-NEXT: s_mov_b32 s8, 0x4f7ffffe ; GFX9-NEXT: s_mov_b32 s8, 0x4f7ffffe
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshl_b32 s1, s0, s2 ; GFX9-NEXT: s_lshl_b32 s1, s0, s6
; GFX9-NEXT: s_ashr_i32 s2, s1, 31 ; GFX9-NEXT: s_ashr_i32 s6, s1, 31
; GFX9-NEXT: s_add_i32 s1, s1, s2 ; GFX9-NEXT: s_add_i32 s1, s1, s6
; GFX9-NEXT: s_xor_b32 s1, s1, s2 ; GFX9-NEXT: s_xor_b32 s1, s1, s6
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s1 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s1
; GFX9-NEXT: s_lshl_b32 s0, s0, s3 ; GFX9-NEXT: s_lshl_b32 s0, s0, s7
; GFX9-NEXT: s_ashr_i32 s2, s0, 31 ; GFX9-NEXT: s_ashr_i32 s6, s0, 31
; GFX9-NEXT: s_add_i32 s0, s0, s2 ; GFX9-NEXT: s_add_i32 s0, s0, s6
; GFX9-NEXT: s_xor_b32 s0, s0, s2 ; GFX9-NEXT: s_xor_b32 s0, s0, s6
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s0 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s0
; GFX9-NEXT: s_sub_i32 s3, 0, s1 ; GFX9-NEXT: s_sub_i32 s7, 0, s1
; GFX9-NEXT: s_ashr_i32 s2, s6, 31 ; GFX9-NEXT: s_ashr_i32 s6, s4, 31
; GFX9-NEXT: v_mul_f32_e32 v0, s8, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, s8, v0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: s_add_i32 s4, s4, s6
; GFX9-NEXT: s_xor_b32 s4, s4, s6
; GFX9-NEXT: v_mul_f32_e32 v1, s8, v1 ; GFX9-NEXT: v_mul_f32_e32 v1, s8, v1
; GFX9-NEXT: v_mul_lo_u32 v3, s3, v0 ; GFX9-NEXT: v_mul_lo_u32 v3, s7, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: s_add_i32 s3, s6, s2 ; GFX9-NEXT: s_sub_i32 s7, 0, s0
; GFX9-NEXT: s_sub_i32 s6, 0, s0
; GFX9-NEXT: v_mul_hi_u32 v3, v0, v3 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, v3
; GFX9-NEXT: v_mul_lo_u32 v4, s6, v1 ; GFX9-NEXT: v_mul_lo_u32 v4, s7, v1
; GFX9-NEXT: s_xor_b32 s3, s3, s2 ; GFX9-NEXT: s_ashr_i32 s7, s5, 31
; GFX9-NEXT: s_ashr_i32 s6, s7, 31 ; GFX9-NEXT: s_add_i32 s5, s5, s7
; GFX9-NEXT: v_add_u32_e32 v0, v0, v3 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v3
; GFX9-NEXT: v_mul_hi_u32 v3, v1, v4 ; GFX9-NEXT: v_mul_hi_u32 v3, v1, v4
; GFX9-NEXT: v_mul_hi_u32 v0, s3, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX9-NEXT: s_add_i32 s7, s7, s6 ; GFX9-NEXT: s_xor_b32 s5, s5, s7
; GFX9-NEXT: s_xor_b32 s7, s7, s6
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_mul_hi_u32 v1, s7, v1 ; GFX9-NEXT: v_mul_hi_u32 v1, s5, v1
; GFX9-NEXT: v_mul_lo_u32 v0, v0, s1 ; GFX9-NEXT: v_mul_lo_u32 v0, v0, s1
; GFX9-NEXT: v_mul_lo_u32 v1, v1, s0 ; GFX9-NEXT: v_mul_lo_u32 v1, v1, s0
; GFX9-NEXT: v_sub_u32_e32 v0, s3, v0 ; GFX9-NEXT: v_sub_u32_e32 v0, s4, v0
; GFX9-NEXT: v_subrev_u32_e32 v3, s1, v0 ; GFX9-NEXT: v_subrev_u32_e32 v3, s1, v0
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s1, v0 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s1, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: v_subrev_u32_e32 v3, s1, v0 ; GFX9-NEXT: v_subrev_u32_e32 v3, s1, v0
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s1, v0 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s1, v0
; GFX9-NEXT: v_sub_u32_e32 v1, s7, v1 ; GFX9-NEXT: v_sub_u32_e32 v1, s5, v1
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: v_subrev_u32_e32 v3, s0, v1 ; GFX9-NEXT: v_subrev_u32_e32 v3, s0, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s0, v1 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s0, v1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX9-NEXT: v_subrev_u32_e32 v3, s0, v1 ; GFX9-NEXT: v_subrev_u32_e32 v3, s0, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s0, v1 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s0, v1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0 ; GFX9-NEXT: v_xor_b32_e32 v0, s6, v0
; GFX9-NEXT: v_xor_b32_e32 v1, s6, v1 ; GFX9-NEXT: v_xor_b32_e32 v1, s7, v1
; GFX9-NEXT: v_subrev_u32_e32 v0, s2, v0 ; GFX9-NEXT: v_subrev_u32_e32 v0, s6, v0
; GFX9-NEXT: v_subrev_u32_e32 v1, s6, v1 ; GFX9-NEXT: v_subrev_u32_e32 v1, s7, v1
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5] ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y %shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y
%r = srem <2 x i32> %x, %shl.y %r = srem <2 x i32> %x, %shl.y
store <2 x i32> %r, <2 x i32> addrspace(1)* %out store <2 x i32> %r, <2 x i32> addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @udiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { define amdgpu_kernel void @udiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) {
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; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 1 ; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 1
; CHECK-NEXT: [[TMP7:%.*]] = udiv i64 [[TMP5]], [[TMP6]] ; CHECK-NEXT: [[TMP7:%.*]] = udiv i64 [[TMP5]], [[TMP6]]
; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP7]], i64 1 ; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP7]], i64 1
; CHECK-NEXT: store <2 x i64> [[TMP8]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16 ; CHECK-NEXT: store <2 x i64> [[TMP8]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; GFX6-LABEL: udiv_v2i64_pow2_shl_denom: ; GFX6-LABEL: udiv_v2i64_pow2_shl_denom:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x11 ; GFX6-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd
; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_mov_b32 s2, -1 ; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_add_i32 s4, s4, 12 ; GFX6-NEXT: s_add_i32 s8, s8, 12
; GFX6-NEXT: s_add_i32 s6, s6, 12 ; GFX6-NEXT: s_add_i32 s9, s10, 12
; GFX6-NEXT: s_lshr_b64 s[4:5], s[8:9], s4 ; GFX6-NEXT: s_lshr_b64 s[4:5], s[4:5], s8
; GFX6-NEXT: s_lshr_b64 s[6:7], s[10:11], s6 ; GFX6-NEXT: s_lshr_b64 s[6:7], s[6:7], s9
; GFX6-NEXT: v_mov_b32_e32 v0, s4 ; GFX6-NEXT: v_mov_b32_e32 v0, s4
; GFX6-NEXT: v_mov_b32_e32 v1, s5 ; GFX6-NEXT: v_mov_b32_e32 v1, s5
; GFX6-NEXT: v_mov_b32_e32 v2, s6 ; GFX6-NEXT: v_mov_b32_e32 v2, s6
; GFX6-NEXT: v_mov_b32_e32 v3, s7 ; GFX6-NEXT: v_mov_b32_e32 v3, s7
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: udiv_v2i64_pow2_shl_denom: ; GFX9-LABEL: udiv_v2i64_pow2_shl_denom:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x44 ; GFX9-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
; GFX9-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x34
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_add_i32 s0, s4, 12 ; GFX9-NEXT: s_add_i32 s2, s8, 12
; GFX9-NEXT: s_add_i32 s4, s6, 12 ; GFX9-NEXT: s_add_i32 s8, s10, 12
; GFX9-NEXT: s_lshr_b64 s[0:1], s[8:9], s0 ; GFX9-NEXT: s_lshr_b64 s[2:3], s[4:5], s2
; GFX9-NEXT: s_lshr_b64 s[4:5], s[10:11], s4 ; GFX9-NEXT: s_lshr_b64 s[4:5], s[6:7], s8
; GFX9-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: v_mov_b32_e32 v2, s4 ; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_mov_b32_e32 v3, s5 ; GFX9-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3] ; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y %shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
%r = udiv <2 x i64> %x, %shl.y %r = udiv <2 x i64> %x, %shl.y
store <2 x i64> %r, <2 x i64> addrspace(1)* %out store <2 x i64> %r, <2 x i64> addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @urem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { define amdgpu_kernel void @urem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) {
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; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 1 ; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 1
; CHECK-NEXT: [[TMP7:%.*]] = urem i64 [[TMP5]], [[TMP6]] ; CHECK-NEXT: [[TMP7:%.*]] = urem i64 [[TMP5]], [[TMP6]]
; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP7]], i64 1 ; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP7]], i64 1
; CHECK-NEXT: store <2 x i64> [[TMP8]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16 ; CHECK-NEXT: store <2 x i64> [[TMP8]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; GFX6-LABEL: urem_v2i64_pow2_shl_denom: ; GFX6-LABEL: urem_v2i64_pow2_shl_denom:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; GFX6-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9
; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd ; GFX6-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0xd
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x11
; GFX6-NEXT: s_mov_b64 s[12:13], 0x1000 ; GFX6-NEXT: s_mov_b64 s[12:13], 0x1000
; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: s_mov_b32 s11, 0xf000
; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: s_mov_b32 s10, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_lshl_b64 s[2:3], s[12:13], s2 ; GFX6-NEXT: s_lshl_b64 s[6:7], s[12:13], s6
; GFX6-NEXT: s_lshl_b64 s[0:1], s[12:13], s0 ; GFX6-NEXT: s_lshl_b64 s[4:5], s[12:13], s4
; GFX6-NEXT: s_add_u32 s0, s0, -1 ; GFX6-NEXT: s_add_u32 s4, s4, -1
; GFX6-NEXT: s_addc_u32 s1, s1, -1 ; GFX6-NEXT: s_addc_u32 s5, s5, -1
; GFX6-NEXT: s_and_b64 s[0:1], s[8:9], s[0:1] ; GFX6-NEXT: s_and_b64 s[0:1], s[0:1], s[4:5]
; GFX6-NEXT: s_add_u32 s2, s2, -1 ; GFX6-NEXT: s_add_u32 s4, s6, -1
; GFX6-NEXT: s_addc_u32 s3, s3, -1 ; GFX6-NEXT: s_addc_u32 s5, s7, -1
; GFX6-NEXT: s_and_b64 s[2:3], s[10:11], s[2:3] ; GFX6-NEXT: s_and_b64 s[2:3], s[2:3], s[4:5]
; GFX6-NEXT: v_mov_b32_e32 v0, s0 ; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: v_mov_b32_e32 v1, s1 ; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s2 ; GFX6-NEXT: v_mov_b32_e32 v2, s2
; GFX6-NEXT: v_mov_b32_e32 v3, s3 ; GFX6-NEXT: v_mov_b32_e32 v3, s3
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: urem_v2i64_pow2_shl_denom: ; GFX9-LABEL: urem_v2i64_pow2_shl_denom:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x44 ; GFX9-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX9-NEXT: s_mov_b64 s[2:3], 0x1000
; GFX9-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: s_mov_b64 s[0:1], 0x1000
; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshl_b64 s[6:7], s[0:1], s6 ; GFX9-NEXT: s_lshl_b64 s[10:11], s[2:3], s10
; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], s4 ; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], s8
; GFX9-NEXT: s_add_u32 s0, s0, -1 ; GFX9-NEXT: s_add_u32 s2, s2, -1
; GFX9-NEXT: s_addc_u32 s1, s1, -1 ; GFX9-NEXT: s_addc_u32 s3, s3, -1
; GFX9-NEXT: s_and_b64 s[0:1], s[8:9], s[0:1] ; GFX9-NEXT: s_and_b64 s[2:3], s[4:5], s[2:3]
; GFX9-NEXT: s_add_u32 s4, s6, -1 ; GFX9-NEXT: s_add_u32 s4, s10, -1
; GFX9-NEXT: s_addc_u32 s5, s7, -1 ; GFX9-NEXT: s_addc_u32 s5, s11, -1
; GFX9-NEXT: s_and_b64 s[4:5], s[10:11], s[4:5] ; GFX9-NEXT: s_and_b64 s[4:5], s[6:7], s[4:5]
; GFX9-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: v_mov_b32_e32 v2, s4 ; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_mov_b32_e32 v3, s5 ; GFX9-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3] ; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y %shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
%r = urem <2 x i64> %x, %shl.y %r = urem <2 x i64> %x, %shl.y
store <2 x i64> %r, <2 x i64> addrspace(1)* %out store <2 x i64> %r, <2 x i64> addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @sdiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { define amdgpu_kernel void @sdiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) {
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; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 1 ; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 1
; CHECK-NEXT: [[TMP7:%.*]] = sdiv i64 [[TMP5]], [[TMP6]] ; CHECK-NEXT: [[TMP7:%.*]] = sdiv i64 [[TMP5]], [[TMP6]]
; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP7]], i64 1 ; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP7]], i64 1
; CHECK-NEXT: store <2 x i64> [[TMP8]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16 ; CHECK-NEXT: store <2 x i64> [[TMP8]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; GFX6-LABEL: sdiv_v2i64_pow2_shl_denom: ; GFX6-LABEL: sdiv_v2i64_pow2_shl_denom:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x11 ; GFX6-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd
; GFX6-NEXT: s_mov_b64 s[2:3], 0x1000 ; GFX6-NEXT: s_mov_b64 s[12:13], 0x1000
; GFX6-NEXT: s_mov_b32 s18, 0x4f800000 ; GFX6-NEXT: s_mov_b32 s18, 0x4f800000
; GFX6-NEXT: s_mov_b32 s19, 0x5f7ffffc ; GFX6-NEXT: s_mov_b32 s19, 0x5f7ffffc
; GFX6-NEXT: s_mov_b32 s20, 0x2f800000 ; GFX6-NEXT: s_mov_b32 s20, 0x2f800000
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_lshl_b64 s[8:9], s[2:3], s6 ; GFX6-NEXT: s_lshl_b64 s[8:9], s[12:13], s8
; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], s4 ; GFX6-NEXT: s_lshl_b64 s[2:3], s[12:13], s10
; GFX6-NEXT: s_ashr_i32 s12, s3, 31 ; GFX6-NEXT: s_ashr_i32 s14, s9, 31
; GFX6-NEXT: s_add_u32 s2, s2, s12 ; GFX6-NEXT: s_add_u32 s8, s8, s14
; GFX6-NEXT: s_mov_b32 s13, s12 ; GFX6-NEXT: s_mov_b32 s15, s14
; GFX6-NEXT: s_addc_u32 s3, s3, s12 ; GFX6-NEXT: s_addc_u32 s9, s9, s14
; GFX6-NEXT: s_xor_b64 s[10:11], s[2:3], s[12:13] ; GFX6-NEXT: s_xor_b64 s[12:13], s[8:9], s[14:15]
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s10 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s12
; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s11 ; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s13
; GFX6-NEXT: s_mov_b32 s21, 0xcf800000 ; GFX6-NEXT: s_mov_b32 s21, 0xcf800000
; GFX6-NEXT: s_sub_u32 s6, 0, s10 ; GFX6-NEXT: s_sub_u32 s10, 0, s12
; GFX6-NEXT: s_subb_u32 s7, 0, s11 ; GFX6-NEXT: s_subb_u32 s11, 0, s13
; GFX6-NEXT: v_mac_f32_e32 v0, s18, v1 ; GFX6-NEXT: v_mac_f32_e32 v0, s18, v1
; GFX6-NEXT: v_rcp_f32_e32 v0, v0 ; GFX6-NEXT: v_rcp_f32_e32 v0, v0
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; GFX6-NEXT: s_ashr_i32 s16, s5, 31
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd ; GFX6-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9
; GFX6-NEXT: s_add_u32 s0, s4, s16
; GFX6-NEXT: v_mul_f32_e32 v0, s19, v0 ; GFX6-NEXT: v_mul_f32_e32 v0, s19, v0
; GFX6-NEXT: v_mul_f32_e32 v1, s20, v0 ; GFX6-NEXT: v_mul_f32_e32 v1, s20, v0
; GFX6-NEXT: v_trunc_f32_e32 v1, v1 ; GFX6-NEXT: v_trunc_f32_e32 v1, v1
; GFX6-NEXT: v_mac_f32_e32 v0, s21, v1 ; GFX6-NEXT: v_mac_f32_e32 v0, s21, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v0
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_mov_b32 s17, s16
; GFX6-NEXT: s_ashr_i32 s14, s1, 31 ; GFX6-NEXT: s_addc_u32 s1, s5, s16
; GFX6-NEXT: s_add_u32 s0, s0, s14 ; GFX6-NEXT: v_mul_lo_u32 v0, s10, v1
; GFX6-NEXT: v_mul_lo_u32 v0, s6, v1 ; GFX6-NEXT: v_mul_hi_u32 v3, s10, v2
; GFX6-NEXT: v_mul_hi_u32 v3, s6, v2 ; GFX6-NEXT: v_mul_lo_u32 v4, s11, v2
; GFX6-NEXT: v_mul_lo_u32 v4, s7, v2 ; GFX6-NEXT: v_mul_lo_u32 v5, s10, v2
; GFX6-NEXT: v_mul_lo_u32 v5, s6, v2 ; GFX6-NEXT: s_xor_b64 s[4:5], s[0:1], s[16:17]
; GFX6-NEXT: s_mov_b32 s15, s14
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v3, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v3, v0
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v0, v4 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v0, v4
; GFX6-NEXT: v_mul_lo_u32 v0, v2, v3 ; GFX6-NEXT: v_mul_lo_u32 v0, v2, v3
; GFX6-NEXT: v_mul_hi_u32 v4, v2, v5 ; GFX6-NEXT: v_mul_hi_u32 v4, v2, v5
; GFX6-NEXT: v_mul_hi_u32 v6, v2, v3 ; GFX6-NEXT: v_mul_hi_u32 v6, v2, v3
; GFX6-NEXT: v_mul_hi_u32 v7, v1, v3 ; GFX6-NEXT: v_mul_hi_u32 v7, v1, v3
; GFX6-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX6-NEXT: v_mul_lo_u32 v3, v1, v3
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v4, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v4, v0
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v6, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v6, vcc
; GFX6-NEXT: v_mul_lo_u32 v6, v1, v5 ; GFX6-NEXT: v_mul_lo_u32 v6, v1, v5
; GFX6-NEXT: v_mul_hi_u32 v5, v1, v5 ; GFX6-NEXT: v_mul_hi_u32 v5, v1, v5
; GFX6-NEXT: s_addc_u32 s1, s1, s14 ; GFX6-NEXT: s_xor_b64 s[14:15], s[16:17], s[14:15]
; GFX6-NEXT: s_xor_b64 s[16:17], s[0:1], s[14:15]
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v6 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v6
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v4, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v4, v5, vcc
; GFX6-NEXT: v_mov_b32_e32 v0, 0 ; GFX6-NEXT: v_mov_b32_e32 v0, 0
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v0, vcc
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v3, s6, v1 ; GFX6-NEXT: v_mul_lo_u32 v3, s10, v1
; GFX6-NEXT: v_mul_hi_u32 v4, s6, v2 ; GFX6-NEXT: v_mul_hi_u32 v4, s10, v2
; GFX6-NEXT: v_mul_lo_u32 v5, s7, v2 ; GFX6-NEXT: v_mul_lo_u32 v5, s11, v2
; GFX6-NEXT: s_xor_b64 s[14:15], s[14:15], s[12:13] ; GFX6-NEXT: s_mov_b32 s11, 0xf000
; GFX6-NEXT: s_ashr_i32 s12, s9, 31
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GFX6-NEXT: v_mul_lo_u32 v4, s6, v2 ; GFX6-NEXT: v_mul_lo_u32 v4, s10, v2
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v5, v3 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v5, v3
; GFX6-NEXT: v_mul_lo_u32 v7, v2, v3 ; GFX6-NEXT: v_mul_lo_u32 v7, v2, v3
; GFX6-NEXT: v_mul_hi_u32 v8, v2, v4 ; GFX6-NEXT: v_mul_hi_u32 v8, v2, v4
; GFX6-NEXT: v_mul_hi_u32 v9, v2, v3 ; GFX6-NEXT: v_mul_hi_u32 v9, v2, v3
; GFX6-NEXT: v_mul_hi_u32 v6, v1, v4 ; GFX6-NEXT: v_mul_hi_u32 v6, v1, v4
; GFX6-NEXT: v_mul_lo_u32 v4, v1, v4 ; GFX6-NEXT: v_mul_lo_u32 v4, v1, v4
; GFX6-NEXT: v_mul_hi_u32 v5, v1, v3 ; GFX6-NEXT: v_mul_hi_u32 v5, v1, v3
; GFX6-NEXT: v_add_i32_e32 v7, vcc, v8, v7 ; GFX6-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; GFX6-NEXT: v_addc_u32_e32 v8, vcc, 0, v9, vcc ; GFX6-NEXT: v_addc_u32_e32 v8, vcc, 0, v9, vcc
; GFX6-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX6-NEXT: v_mul_lo_u32 v3, v1, v3
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v7, v4 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v7, v4
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v6, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v6, vcc
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v5, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v5, v0, vcc
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v3, s16, v1 ; GFX6-NEXT: v_mul_lo_u32 v3, s4, v1
; GFX6-NEXT: v_mul_hi_u32 v4, s16, v2 ; GFX6-NEXT: v_mul_hi_u32 v4, s4, v2
; GFX6-NEXT: v_mul_hi_u32 v5, s16, v1 ; GFX6-NEXT: v_mul_hi_u32 v5, s4, v1
; GFX6-NEXT: v_mul_hi_u32 v6, s17, v1 ; GFX6-NEXT: v_mul_hi_u32 v6, s5, v1
; GFX6-NEXT: v_mul_lo_u32 v1, s17, v1 ; GFX6-NEXT: v_mul_lo_u32 v1, s5, v1
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc
; GFX6-NEXT: v_mul_lo_u32 v5, s17, v2 ; GFX6-NEXT: v_mul_lo_u32 v5, s5, v2
; GFX6-NEXT: v_mul_hi_u32 v2, s17, v2 ; GFX6-NEXT: v_mul_hi_u32 v2, s5, v2
; GFX6-NEXT: s_add_u32 s8, s8, s12 ; GFX6-NEXT: s_mov_b32 s10, -1
; GFX6-NEXT: s_mov_b32 s13, s12
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v4, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v4, v2, vcc
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v0, vcc
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc
; GFX6-NEXT: v_mul_lo_u32 v3, s10, v2 ; GFX6-NEXT: v_mul_lo_u32 v3, s12, v2
; GFX6-NEXT: v_mul_hi_u32 v4, s10, v1 ; GFX6-NEXT: v_mul_hi_u32 v4, s12, v1
; GFX6-NEXT: v_mul_lo_u32 v5, s11, v1 ; GFX6-NEXT: v_mul_lo_u32 v5, s13, v1
; GFX6-NEXT: v_mov_b32_e32 v6, s11 ; GFX6-NEXT: v_mov_b32_e32 v6, s13
; GFX6-NEXT: s_addc_u32 s9, s9, s12
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GFX6-NEXT: v_mul_lo_u32 v4, s10, v1 ; GFX6-NEXT: v_mul_lo_u32 v4, s12, v1
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, s17, v3 ; GFX6-NEXT: v_sub_i32_e32 v5, vcc, s5, v3
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s16, v4 ; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s4, v4
; GFX6-NEXT: v_subb_u32_e64 v5, s[0:1], v5, v6, vcc ; GFX6-NEXT: v_subb_u32_e64 v5, s[0:1], v5, v6, vcc
; GFX6-NEXT: v_subrev_i32_e64 v6, s[0:1], s10, v4 ; GFX6-NEXT: v_subrev_i32_e64 v6, s[0:1], s12, v4
; GFX6-NEXT: v_subbrev_u32_e64 v5, s[0:1], 0, v5, s[0:1] ; GFX6-NEXT: v_subbrev_u32_e64 v5, s[0:1], 0, v5, s[0:1]
; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v5 ; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v5
; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1]
; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v6 ; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s12, v6
; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1]
; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v5 ; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], s13, v5
; GFX6-NEXT: v_cndmask_b32_e64 v5, v7, v6, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v5, v7, v6, s[0:1]
; GFX6-NEXT: v_add_i32_e64 v6, s[0:1], 2, v1 ; GFX6-NEXT: v_add_i32_e64 v6, s[0:1], 2, v1
; GFX6-NEXT: v_addc_u32_e64 v7, s[0:1], 0, v2, s[0:1] ; GFX6-NEXT: v_addc_u32_e64 v7, s[0:1], 0, v2, s[0:1]
; GFX6-NEXT: v_add_i32_e64 v8, s[0:1], 1, v1 ; GFX6-NEXT: v_add_i32_e64 v8, s[0:1], 1, v1
; GFX6-NEXT: v_addc_u32_e64 v9, s[0:1], 0, v2, s[0:1] ; GFX6-NEXT: v_addc_u32_e64 v9, s[0:1], 0, v2, s[0:1]
; GFX6-NEXT: s_ashr_i32 s4, s3, 31
; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5 ; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5
; GFX6-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13] ; GFX6-NEXT: s_add_u32 s2, s2, s4
; GFX6-NEXT: v_cndmask_b32_e64 v5, v9, v7, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v5, v9, v7, s[0:1]
; GFX6-NEXT: v_mov_b32_e32 v7, s17 ; GFX6-NEXT: v_mov_b32_e32 v7, s5
; GFX6-NEXT: v_cvt_f32_u32_e32 v9, s8 ; GFX6-NEXT: s_mov_b32 s5, s4
; GFX6-NEXT: v_cvt_f32_u32_e32 v10, s9 ; GFX6-NEXT: s_addc_u32 s3, s3, s4
; GFX6-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5]
; GFX6-NEXT: v_cvt_f32_u32_e32 v9, s2
; GFX6-NEXT: v_cvt_f32_u32_e32 v10, s3
; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v7, v3, vcc ; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v7, v3, vcc
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s11, v3 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s13, v3
; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s10, v4 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s12, v4
; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s11, v3 ; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s13, v3
; GFX6-NEXT: v_mac_f32_e32 v9, s18, v10 ; GFX6-NEXT: v_mac_f32_e32 v9, s18, v10
; GFX6-NEXT: v_cndmask_b32_e32 v3, v7, v4, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v7, v4, vcc
; GFX6-NEXT: v_rcp_f32_e32 v4, v9 ; GFX6-NEXT: v_rcp_f32_e32 v4, v9
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v3, v8, v6, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v3, v8, v6, s[0:1]
; GFX6-NEXT: v_mul_f32_e32 v4, s19, v4 ; GFX6-NEXT: v_mul_f32_e32 v4, s19, v4
; GFX6-NEXT: v_mul_f32_e32 v5, s20, v4 ; GFX6-NEXT: v_mul_f32_e32 v5, s20, v4
; GFX6-NEXT: v_trunc_f32_e32 v5, v5 ; GFX6-NEXT: v_trunc_f32_e32 v5, v5
; GFX6-NEXT: v_mac_f32_e32 v4, s21, v5 ; GFX6-NEXT: v_mac_f32_e32 v4, s21, v5
; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v4 ; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v4
; GFX6-NEXT: v_cvt_u32_f32_e32 v5, v5 ; GFX6-NEXT: v_cvt_u32_f32_e32 v5, v5
; GFX6-NEXT: s_sub_u32 s0, 0, s8 ; GFX6-NEXT: s_sub_u32 s0, 0, s2
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX6-NEXT: v_mul_hi_u32 v3, s0, v4 ; GFX6-NEXT: v_mul_hi_u32 v3, s0, v4
; GFX6-NEXT: v_mul_lo_u32 v6, s0, v5 ; GFX6-NEXT: v_mul_lo_u32 v6, s0, v5
; GFX6-NEXT: s_subb_u32 s1, 0, s9 ; GFX6-NEXT: s_subb_u32 s1, 0, s3
; GFX6-NEXT: v_mul_lo_u32 v7, s1, v4 ; GFX6-NEXT: v_mul_lo_u32 v7, s1, v4
; GFX6-NEXT: s_ashr_i32 s10, s3, 31 ; GFX6-NEXT: s_ashr_i32 s12, s7, 31
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6
; GFX6-NEXT: v_mul_lo_u32 v6, s0, v4 ; GFX6-NEXT: v_mul_lo_u32 v6, s0, v4
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v7 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v7
; GFX6-NEXT: v_mul_lo_u32 v7, v4, v3 ; GFX6-NEXT: v_mul_lo_u32 v7, v4, v3
; GFX6-NEXT: v_mul_hi_u32 v8, v4, v6 ; GFX6-NEXT: v_mul_hi_u32 v8, v4, v6
; GFX6-NEXT: v_mul_hi_u32 v9, v4, v3 ; GFX6-NEXT: v_mul_hi_u32 v9, v4, v3
; GFX6-NEXT: v_mul_hi_u32 v10, v5, v3 ; GFX6-NEXT: v_mul_hi_u32 v10, v5, v3
; GFX6-NEXT: v_mul_lo_u32 v3, v5, v3 ; GFX6-NEXT: v_mul_lo_u32 v3, v5, v3
; GFX6-NEXT: v_add_i32_e32 v7, vcc, v8, v7 ; GFX6-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; GFX6-NEXT: v_addc_u32_e32 v8, vcc, 0, v9, vcc ; GFX6-NEXT: v_addc_u32_e32 v8, vcc, 0, v9, vcc
; GFX6-NEXT: v_mul_lo_u32 v9, v5, v6 ; GFX6-NEXT: v_mul_lo_u32 v9, v5, v6
; GFX6-NEXT: v_mul_hi_u32 v6, v5, v6 ; GFX6-NEXT: v_mul_hi_u32 v6, v5, v6
; GFX6-NEXT: s_mov_b32 s11, s10 ; GFX6-NEXT: s_mov_b32 s13, s12
; GFX6-NEXT: v_xor_b32_e32 v1, s14, v1 ; GFX6-NEXT: v_xor_b32_e32 v1, s14, v1
; GFX6-NEXT: v_add_i32_e32 v7, vcc, v7, v9 ; GFX6-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; GFX6-NEXT: v_addc_u32_e32 v6, vcc, v8, v6, vcc ; GFX6-NEXT: v_addc_u32_e32 v6, vcc, v8, v6, vcc
; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v10, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v10, v0, vcc
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v6, v3 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v6, v3
; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v7, vcc ; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v5, v6, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v5, v6, vcc
; GFX6-NEXT: v_mul_lo_u32 v5, s0, v4 ; GFX6-NEXT: v_mul_lo_u32 v5, s0, v4
; GFX6-NEXT: v_mul_hi_u32 v6, s0, v3 ; GFX6-NEXT: v_mul_hi_u32 v6, s0, v3
; GFX6-NEXT: v_mul_lo_u32 v7, s1, v3 ; GFX6-NEXT: v_mul_lo_u32 v7, s1, v3
; GFX6-NEXT: v_xor_b32_e32 v2, s15, v2 ; GFX6-NEXT: v_xor_b32_e32 v2, s15, v2
; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GFX6-NEXT: v_mul_lo_u32 v6, s0, v3 ; GFX6-NEXT: v_mul_lo_u32 v6, s0, v3
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v7, v5 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v7, v5
; GFX6-NEXT: v_mul_lo_u32 v9, v3, v5 ; GFX6-NEXT: v_mul_lo_u32 v9, v3, v5
; GFX6-NEXT: v_mul_hi_u32 v10, v3, v6 ; GFX6-NEXT: v_mul_hi_u32 v10, v3, v6
; GFX6-NEXT: v_mul_hi_u32 v11, v3, v5 ; GFX6-NEXT: v_mul_hi_u32 v11, v3, v5
; GFX6-NEXT: v_mul_hi_u32 v8, v4, v6 ; GFX6-NEXT: v_mul_hi_u32 v8, v4, v6
; GFX6-NEXT: v_mul_lo_u32 v6, v4, v6 ; GFX6-NEXT: v_mul_lo_u32 v6, v4, v6
; GFX6-NEXT: v_mul_hi_u32 v7, v4, v5 ; GFX6-NEXT: v_mul_hi_u32 v7, v4, v5
; GFX6-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; GFX6-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GFX6-NEXT: v_addc_u32_e32 v10, vcc, 0, v11, vcc ; GFX6-NEXT: v_addc_u32_e32 v10, vcc, 0, v11, vcc
; GFX6-NEXT: v_mul_lo_u32 v5, v4, v5 ; GFX6-NEXT: v_mul_lo_u32 v5, v4, v5
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v9, v6 ; GFX6-NEXT: v_add_i32_e32 v6, vcc, v9, v6
; GFX6-NEXT: v_addc_u32_e32 v6, vcc, v10, v8, vcc ; GFX6-NEXT: v_addc_u32_e32 v6, vcc, v10, v8, vcc
; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v7, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v7, v0, vcc
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v7, vcc ; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v7, vcc
; GFX6-NEXT: s_add_u32 s0, s2, s10 ; GFX6-NEXT: s_add_u32 s0, s6, s12
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GFX6-NEXT: s_addc_u32 s1, s3, s10 ; GFX6-NEXT: s_addc_u32 s1, s7, s12
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v4, v6, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v4, v6, vcc
; GFX6-NEXT: s_xor_b64 s[2:3], s[0:1], s[10:11] ; GFX6-NEXT: s_xor_b64 s[6:7], s[0:1], s[12:13]
; GFX6-NEXT: v_mul_lo_u32 v5, s2, v4 ; GFX6-NEXT: v_mul_lo_u32 v5, s6, v4
; GFX6-NEXT: v_mul_hi_u32 v6, s2, v3 ; GFX6-NEXT: v_mul_hi_u32 v6, s6, v3
; GFX6-NEXT: v_mul_hi_u32 v8, s2, v4 ; GFX6-NEXT: v_mul_hi_u32 v8, s6, v4
; GFX6-NEXT: v_mul_hi_u32 v9, s3, v4 ; GFX6-NEXT: v_mul_hi_u32 v9, s7, v4
; GFX6-NEXT: v_mul_lo_u32 v4, s3, v4 ; GFX6-NEXT: v_mul_lo_u32 v4, s7, v4
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v8, vcc ; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v8, vcc
; GFX6-NEXT: v_mul_lo_u32 v8, s3, v3 ; GFX6-NEXT: v_mul_lo_u32 v8, s7, v3
; GFX6-NEXT: v_mul_hi_u32 v3, s3, v3 ; GFX6-NEXT: v_mul_hi_u32 v3, s7, v3
; GFX6-NEXT: v_mov_b32_e32 v7, s15 ; GFX6-NEXT: v_mov_b32_e32 v7, s15
; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v8 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v3, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v3, vcc
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v9, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v9, v0, vcc
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v0, vcc
; GFX6-NEXT: v_mul_lo_u32 v5, s8, v4 ; GFX6-NEXT: v_mul_lo_u32 v5, s2, v4
; GFX6-NEXT: v_mul_hi_u32 v6, s8, v3 ; GFX6-NEXT: v_mul_hi_u32 v6, s2, v3
; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s14, v1 ; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s14, v1
; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v2, v7, vcc ; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v2, v7, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, s9, v3 ; GFX6-NEXT: v_mul_lo_u32 v2, s3, v3
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GFX6-NEXT: v_mov_b32_e32 v7, s9 ; GFX6-NEXT: v_mov_b32_e32 v7, s3
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v2
; GFX6-NEXT: v_mul_lo_u32 v5, s8, v3 ; GFX6-NEXT: v_mul_lo_u32 v5, s2, v3
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, s3, v2 ; GFX6-NEXT: v_sub_i32_e32 v6, vcc, s7, v2
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, s2, v5 ; GFX6-NEXT: v_sub_i32_e32 v5, vcc, s6, v5
; GFX6-NEXT: v_subb_u32_e64 v6, s[0:1], v6, v7, vcc ; GFX6-NEXT: v_subb_u32_e64 v6, s[0:1], v6, v7, vcc
; GFX6-NEXT: v_subrev_i32_e64 v7, s[0:1], s8, v5 ; GFX6-NEXT: v_subrev_i32_e64 v7, s[0:1], s2, v5
; GFX6-NEXT: v_subbrev_u32_e64 v6, s[0:1], 0, v6, s[0:1] ; GFX6-NEXT: v_subbrev_u32_e64 v6, s[0:1], 0, v6, s[0:1]
; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v6 ; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v6
; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1]
; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v7 ; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v7
; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1]
; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v6 ; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v6
; GFX6-NEXT: v_cndmask_b32_e64 v6, v8, v7, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v6, v8, v7, s[0:1]
; GFX6-NEXT: v_add_i32_e64 v7, s[0:1], 2, v3 ; GFX6-NEXT: v_add_i32_e64 v7, s[0:1], 2, v3
; GFX6-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v4, s[0:1] ; GFX6-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v4, s[0:1]
; GFX6-NEXT: v_add_i32_e64 v9, s[0:1], 1, v3 ; GFX6-NEXT: v_add_i32_e64 v9, s[0:1], 1, v3
; GFX6-NEXT: v_addc_u32_e64 v10, s[0:1], 0, v4, s[0:1] ; GFX6-NEXT: v_addc_u32_e64 v10, s[0:1], 0, v4, s[0:1]
; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6 ; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6
; GFX6-NEXT: v_cndmask_b32_e64 v6, v10, v8, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v6, v10, v8, s[0:1]
; GFX6-NEXT: v_mov_b32_e32 v8, s3 ; GFX6-NEXT: v_mov_b32_e32 v8, s7
; GFX6-NEXT: v_subb_u32_e32 v2, vcc, v8, v2, vcc ; GFX6-NEXT: v_subb_u32_e32 v2, vcc, v8, v2, vcc
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s9, v2 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v2
; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v5 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s2, v5
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s9, v2 ; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s3, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v8, v5, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v2, v8, v5, vcc
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v4, v9, v7, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v4, v9, v7, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX6-NEXT: s_xor_b64 s[0:1], s[10:11], s[12:13] ; GFX6-NEXT: s_xor_b64 s[0:1], s[12:13], s[4:5]
; GFX6-NEXT: v_xor_b32_e32 v3, s0, v3 ; GFX6-NEXT: v_xor_b32_e32 v3, s0, v3
; GFX6-NEXT: v_xor_b32_e32 v4, s1, v2 ; GFX6-NEXT: v_xor_b32_e32 v4, s1, v2
; GFX6-NEXT: v_mov_b32_e32 v5, s1 ; GFX6-NEXT: v_mov_b32_e32 v5, s1
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s0, v3 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s0, v3
; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v4, v5, vcc ; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v4, v5, vcc
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: sdiv_v2i64_pow2_shl_denom: ; GFX9-LABEL: sdiv_v2i64_pow2_shl_denom:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x44 ; GFX9-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
; GFX9-NEXT: s_mov_b64 s[2:3], 0x1000 ; GFX9-NEXT: s_mov_b64 s[2:3], 0x1000
; GFX9-NEXT: s_mov_b32 s16, 0x4f800000 ; GFX9-NEXT: s_mov_b32 s16, 0x4f800000
; GFX9-NEXT: s_mov_b32 s17, 0x5f7ffffc ; GFX9-NEXT: s_mov_b32 s17, 0x5f7ffffc
; GFX9-NEXT: s_mov_b32 s18, 0x2f800000 ; GFX9-NEXT: s_mov_b32 s18, 0x2f800000
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshl_b64 s[8:9], s[2:3], s6 ; GFX9-NEXT: s_lshl_b64 s[10:11], s[2:3], s10
; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], s4 ; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], s8
; GFX9-NEXT: s_ashr_i32 s12, s3, 31 ; GFX9-NEXT: s_ashr_i32 s12, s3, 31
; GFX9-NEXT: s_add_u32 s2, s2, s12 ; GFX9-NEXT: s_add_u32 s2, s2, s12
; GFX9-NEXT: s_mov_b32 s13, s12 ; GFX9-NEXT: s_mov_b32 s13, s12
; GFX9-NEXT: s_addc_u32 s3, s3, s12 ; GFX9-NEXT: s_addc_u32 s3, s3, s12
; GFX9-NEXT: s_xor_b64 s[10:11], s[2:3], s[12:13] ; GFX9-NEXT: s_xor_b64 s[8:9], s[2:3], s[12:13]
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s10 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s8
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s11 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s9
; GFX9-NEXT: s_mov_b32 s19, 0xcf800000 ; GFX9-NEXT: s_mov_b32 s19, 0xcf800000
; GFX9-NEXT: s_sub_u32 s2, 0, s10 ; GFX9-NEXT: s_sub_u32 s2, 0, s8
; GFX9-NEXT: s_subb_u32 s3, 0, s11 ; GFX9-NEXT: s_subb_u32 s3, 0, s9
; GFX9-NEXT: v_mac_f32_e32 v0, s16, v1 ; GFX9-NEXT: v_mac_f32_e32 v0, s16, v1
; GFX9-NEXT: v_rcp_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_f32_e32 v0, v0
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 ; GFX9-NEXT: s_ashr_i32 s14, s5, 31
; GFX9-NEXT: s_mov_b32 s15, s14
; GFX9-NEXT: v_mul_f32_e32 v0, s17, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, s17, v0
; GFX9-NEXT: v_mul_f32_e32 v1, s18, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, s18, v0
; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1
; GFX9-NEXT: v_mac_f32_e32 v0, s19, v1 ; GFX9-NEXT: v_mac_f32_e32 v0, s19, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_ashr_i32 s14, s5, 31
; GFX9-NEXT: s_mov_b32 s15, s14
; GFX9-NEXT: v_mul_lo_u32 v0, s2, v1 ; GFX9-NEXT: v_mul_lo_u32 v0, s2, v1
; GFX9-NEXT: v_mul_hi_u32 v3, s2, v2 ; GFX9-NEXT: v_mul_hi_u32 v3, s2, v2
; GFX9-NEXT: v_mul_lo_u32 v5, s3, v2 ; GFX9-NEXT: v_mul_lo_u32 v5, s3, v2
; GFX9-NEXT: v_mul_lo_u32 v4, s2, v2 ; GFX9-NEXT: v_mul_lo_u32 v4, s2, v2
; GFX9-NEXT: v_add_u32_e32 v0, v3, v0 ; GFX9-NEXT: v_add_u32_e32 v0, v3, v0
; GFX9-NEXT: v_add_u32_e32 v5, v0, v5 ; GFX9-NEXT: v_add_u32_e32 v5, v0, v5
; GFX9-NEXT: v_mul_hi_u32 v3, v2, v4 ; GFX9-NEXT: v_mul_hi_u32 v3, v2, v4
; GFX9-NEXT: v_mul_lo_u32 v6, v2, v5 ; GFX9-NEXT: v_mul_lo_u32 v6, v2, v5
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_mul_hi_u32 v2, s5, v2 ; GFX9-NEXT: v_mul_hi_u32 v2, s5, v2
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX9-NEXT: s_xor_b64 s[12:13], s[14:15], s[12:13] ; GFX9-NEXT: s_xor_b64 s[12:13], s[14:15], s[12:13]
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v4, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v4, v2, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v0, vcc
; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v2, v1 ; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v2, v1
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v3, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v3, vcc
; GFX9-NEXT: v_mul_lo_u32 v3, s10, v2 ; GFX9-NEXT: v_mul_lo_u32 v3, s8, v2
; GFX9-NEXT: v_mul_hi_u32 v4, s10, v1 ; GFX9-NEXT: v_mul_hi_u32 v4, s8, v1
; GFX9-NEXT: v_mul_lo_u32 v5, s11, v1 ; GFX9-NEXT: v_mul_lo_u32 v5, s9, v1
; GFX9-NEXT: v_mov_b32_e32 v6, s11 ; GFX9-NEXT: v_mov_b32_e32 v6, s9
; GFX9-NEXT: v_add_u32_e32 v3, v4, v3 ; GFX9-NEXT: v_add_u32_e32 v3, v4, v3
; GFX9-NEXT: v_mul_lo_u32 v4, s10, v1 ; GFX9-NEXT: v_mul_lo_u32 v4, s8, v1
; GFX9-NEXT: v_add_u32_e32 v3, v3, v5 ; GFX9-NEXT: v_add_u32_e32 v3, v3, v5
; GFX9-NEXT: v_sub_u32_e32 v5, s5, v3 ; GFX9-NEXT: v_sub_u32_e32 v5, s5, v3
; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, s4, v4 ; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, s4, v4
; GFX9-NEXT: v_subb_co_u32_e64 v5, s[0:1], v5, v6, vcc ; GFX9-NEXT: v_subb_co_u32_e64 v5, s[0:1], v5, v6, vcc
; GFX9-NEXT: v_subrev_co_u32_e64 v6, s[0:1], s10, v4 ; GFX9-NEXT: v_subrev_co_u32_e64 v6, s[0:1], s8, v4
; GFX9-NEXT: v_subbrev_co_u32_e64 v5, s[0:1], 0, v5, s[0:1] ; GFX9-NEXT: v_subbrev_co_u32_e64 v5, s[0:1], 0, v5, s[0:1]
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v5 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v5
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v6 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v6
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v5 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v5
; GFX9-NEXT: v_cndmask_b32_e64 v5, v7, v6, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v5, v7, v6, s[0:1]
; GFX9-NEXT: v_add_co_u32_e64 v6, s[0:1], 2, v1 ; GFX9-NEXT: v_add_co_u32_e64 v6, s[0:1], 2, v1
; GFX9-NEXT: v_addc_co_u32_e64 v7, s[0:1], 0, v2, s[0:1] ; GFX9-NEXT: v_addc_co_u32_e64 v7, s[0:1], 0, v2, s[0:1]
; GFX9-NEXT: v_add_co_u32_e64 v8, s[0:1], 1, v1 ; GFX9-NEXT: v_add_co_u32_e64 v8, s[0:1], 1, v1
; GFX9-NEXT: v_addc_co_u32_e64 v9, s[0:1], 0, v2, s[0:1] ; GFX9-NEXT: v_addc_co_u32_e64 v9, s[0:1], 0, v2, s[0:1]
; GFX9-NEXT: s_ashr_i32 s4, s9, 31 ; GFX9-NEXT: s_ashr_i32 s4, s11, 31
; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5 ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5
; GFX9-NEXT: s_add_u32 s8, s8, s4 ; GFX9-NEXT: s_add_u32 s10, s10, s4
; GFX9-NEXT: v_cndmask_b32_e64 v5, v9, v7, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v5, v9, v7, s[0:1]
; GFX9-NEXT: v_mov_b32_e32 v7, s5 ; GFX9-NEXT: v_mov_b32_e32 v7, s5
; GFX9-NEXT: s_mov_b32 s5, s4 ; GFX9-NEXT: s_mov_b32 s5, s4
; GFX9-NEXT: s_addc_u32 s9, s9, s4 ; GFX9-NEXT: s_addc_u32 s11, s11, s4
; GFX9-NEXT: s_xor_b64 s[8:9], s[8:9], s[4:5] ; GFX9-NEXT: s_xor_b64 s[10:11], s[10:11], s[4:5]
; GFX9-NEXT: v_cvt_f32_u32_e32 v9, s8 ; GFX9-NEXT: v_cvt_f32_u32_e32 v9, s10
; GFX9-NEXT: v_cvt_f32_u32_e32 v10, s9 ; GFX9-NEXT: v_cvt_f32_u32_e32 v10, s11
; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v7, v3, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v7, v3, vcc
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v3
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v4 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v4
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s11, v3 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s9, v3
; GFX9-NEXT: v_mac_f32_e32 v9, s16, v10 ; GFX9-NEXT: v_mac_f32_e32 v9, s16, v10
; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v4, vcc
; GFX9-NEXT: v_rcp_f32_e32 v4, v9 ; GFX9-NEXT: v_rcp_f32_e32 v4, v9
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v3, v8, v6, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v3, v8, v6, s[0:1]
; GFX9-NEXT: v_mul_f32_e32 v4, s17, v4 ; GFX9-NEXT: v_mul_f32_e32 v4, s17, v4
; GFX9-NEXT: v_mul_f32_e32 v5, s18, v4 ; GFX9-NEXT: v_mul_f32_e32 v5, s18, v4
; GFX9-NEXT: v_trunc_f32_e32 v5, v5 ; GFX9-NEXT: v_trunc_f32_e32 v5, v5
; GFX9-NEXT: v_mac_f32_e32 v4, s19, v5 ; GFX9-NEXT: v_mac_f32_e32 v4, s19, v5
; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4 ; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4
; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5 ; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5
; GFX9-NEXT: s_sub_u32 s0, 0, s8 ; GFX9-NEXT: s_sub_u32 s0, 0, s10
; GFX9-NEXT: s_subb_u32 s1, 0, s9 ; GFX9-NEXT: s_subb_u32 s1, 0, s11
; GFX9-NEXT: v_mul_hi_u32 v6, s0, v4 ; GFX9-NEXT: v_mul_hi_u32 v6, s0, v4
; GFX9-NEXT: v_mul_lo_u32 v7, s0, v5 ; GFX9-NEXT: v_mul_lo_u32 v7, s0, v5
; GFX9-NEXT: v_mul_lo_u32 v8, s1, v4 ; GFX9-NEXT: v_mul_lo_u32 v8, s1, v4
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX9-NEXT: v_mul_lo_u32 v3, s0, v4 ; GFX9-NEXT: v_mul_lo_u32 v3, s0, v4
; GFX9-NEXT: v_add_u32_e32 v6, v6, v7 ; GFX9-NEXT: v_add_u32_e32 v6, v6, v7
; GFX9-NEXT: v_add_u32_e32 v6, v6, v8 ; GFX9-NEXT: v_add_u32_e32 v6, v6, v8
; GFX9-NEXT: v_mul_lo_u32 v7, v4, v6 ; GFX9-NEXT: v_mul_lo_u32 v7, v4, v6
; GFX9-NEXT: v_mul_hi_u32 v8, v4, v3 ; GFX9-NEXT: v_mul_hi_u32 v8, v4, v3
; GFX9-NEXT: v_mul_hi_u32 v9, v4, v6 ; GFX9-NEXT: v_mul_hi_u32 v9, v4, v6
; GFX9-NEXT: v_mul_hi_u32 v10, v5, v6 ; GFX9-NEXT: v_mul_hi_u32 v10, v5, v6
; GFX9-NEXT: v_mul_lo_u32 v6, v5, v6 ; GFX9-NEXT: v_mul_lo_u32 v6, v5, v6
; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7 ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v9, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
; GFX9-NEXT: v_mul_lo_u32 v9, v5, v3 ; GFX9-NEXT: v_mul_lo_u32 v9, v5, v3
; GFX9-NEXT: v_mul_hi_u32 v3, v5, v3 ; GFX9-NEXT: v_mul_hi_u32 v3, v5, v3
; GFX9-NEXT: s_ashr_i32 s10, s7, 31 ; GFX9-NEXT: s_ashr_i32 s8, s7, 31
; GFX9-NEXT: s_mov_b32 s11, s10 ; GFX9-NEXT: s_mov_b32 s9, s8
; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v9 ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v9
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v3, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v3, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v10, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v10, v0, vcc
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v7, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v7, vcc
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v5, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v5, v6, vcc
; GFX9-NEXT: v_mul_lo_u32 v5, s0, v4 ; GFX9-NEXT: v_mul_lo_u32 v5, s0, v4
; GFX9-NEXT: v_mul_hi_u32 v6, s0, v3 ; GFX9-NEXT: v_mul_hi_u32 v6, s0, v3
; GFX9-NEXT: v_mul_lo_u32 v7, s1, v3 ; GFX9-NEXT: v_mul_lo_u32 v7, s1, v3
; GFX9-NEXT: v_mul_lo_u32 v8, s0, v3 ; GFX9-NEXT: v_mul_lo_u32 v8, s0, v3
; GFX9-NEXT: s_add_u32 s0, s6, s10 ; GFX9-NEXT: s_add_u32 s0, s6, s8
; GFX9-NEXT: v_add_u32_e32 v5, v6, v5 ; GFX9-NEXT: v_add_u32_e32 v5, v6, v5
; GFX9-NEXT: v_add_u32_e32 v5, v5, v7 ; GFX9-NEXT: v_add_u32_e32 v5, v5, v7
; GFX9-NEXT: v_mul_lo_u32 v9, v3, v5 ; GFX9-NEXT: v_mul_lo_u32 v9, v3, v5
; GFX9-NEXT: v_mul_hi_u32 v10, v3, v8 ; GFX9-NEXT: v_mul_hi_u32 v10, v3, v8
; GFX9-NEXT: v_mul_hi_u32 v11, v3, v5 ; GFX9-NEXT: v_mul_hi_u32 v11, v3, v5
; GFX9-NEXT: v_mul_hi_u32 v7, v4, v8 ; GFX9-NEXT: v_mul_hi_u32 v7, v4, v8
; GFX9-NEXT: v_mul_lo_u32 v8, v4, v8 ; GFX9-NEXT: v_mul_lo_u32 v8, v4, v8
; GFX9-NEXT: v_mul_hi_u32 v6, v4, v5 ; GFX9-NEXT: v_mul_hi_u32 v6, v4, v5
; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v10, v9 ; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v10, v9
; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, 0, v11, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, 0, v11, vcc
; GFX9-NEXT: v_mul_lo_u32 v5, v4, v5 ; GFX9-NEXT: v_mul_lo_u32 v5, v4, v5
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8 ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v10, v7, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v10, v7, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v6, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v6, v0, vcc
; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5 ; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
; GFX9-NEXT: s_addc_u32 s1, s7, s10 ; GFX9-NEXT: s_addc_u32 s1, s7, s8
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v6, vcc
; GFX9-NEXT: s_xor_b64 s[6:7], s[0:1], s[10:11] ; GFX9-NEXT: s_xor_b64 s[6:7], s[0:1], s[8:9]
; GFX9-NEXT: v_mul_lo_u32 v5, s6, v4 ; GFX9-NEXT: v_mul_lo_u32 v5, s6, v4
; GFX9-NEXT: v_mul_hi_u32 v6, s6, v3 ; GFX9-NEXT: v_mul_hi_u32 v6, s6, v3
; GFX9-NEXT: v_mul_hi_u32 v8, s6, v4 ; GFX9-NEXT: v_mul_hi_u32 v8, s6, v4
; GFX9-NEXT: v_mul_hi_u32 v9, s7, v4 ; GFX9-NEXT: v_mul_hi_u32 v9, s7, v4
; GFX9-NEXT: v_mul_lo_u32 v4, s7, v4 ; GFX9-NEXT: v_mul_lo_u32 v4, s7, v4
; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v6, v5 ; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v6, v5
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v8, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
; GFX9-NEXT: v_mul_lo_u32 v8, s7, v3 ; GFX9-NEXT: v_mul_lo_u32 v8, s7, v3
; GFX9-NEXT: v_mul_hi_u32 v3, s7, v3 ; GFX9-NEXT: v_mul_hi_u32 v3, s7, v3
; GFX9-NEXT: v_xor_b32_e32 v1, s12, v1 ; GFX9-NEXT: v_xor_b32_e32 v1, s12, v1
; GFX9-NEXT: v_xor_b32_e32 v2, s13, v2 ; GFX9-NEXT: v_xor_b32_e32 v2, s13, v2
; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v5, v8 ; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v5, v8
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v3, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v3, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v0, vcc
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
; GFX9-NEXT: v_mul_lo_u32 v5, s8, v4 ; GFX9-NEXT: v_mul_lo_u32 v5, s10, v4
; GFX9-NEXT: v_mul_hi_u32 v6, s8, v3 ; GFX9-NEXT: v_mul_hi_u32 v6, s10, v3
; GFX9-NEXT: v_mul_lo_u32 v8, s9, v3 ; GFX9-NEXT: v_mul_lo_u32 v8, s11, v3
; GFX9-NEXT: v_mov_b32_e32 v7, s13 ; GFX9-NEXT: v_mov_b32_e32 v7, s13
; GFX9-NEXT: v_subrev_co_u32_e32 v1, vcc, s12, v1 ; GFX9-NEXT: v_subrev_co_u32_e32 v1, vcc, s12, v1
; GFX9-NEXT: v_add_u32_e32 v5, v6, v5 ; GFX9-NEXT: v_add_u32_e32 v5, v6, v5
; GFX9-NEXT: v_mul_lo_u32 v6, s8, v3 ; GFX9-NEXT: v_mul_lo_u32 v6, s10, v3
; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v7, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v7, vcc
; GFX9-NEXT: v_add_u32_e32 v5, v5, v8 ; GFX9-NEXT: v_add_u32_e32 v5, v5, v8
; GFX9-NEXT: v_sub_u32_e32 v7, s7, v5 ; GFX9-NEXT: v_sub_u32_e32 v7, s7, v5
; GFX9-NEXT: v_mov_b32_e32 v8, s9 ; GFX9-NEXT: v_mov_b32_e32 v8, s11
; GFX9-NEXT: v_sub_co_u32_e32 v6, vcc, s6, v6 ; GFX9-NEXT: v_sub_co_u32_e32 v6, vcc, s6, v6
; GFX9-NEXT: v_subb_co_u32_e64 v7, s[0:1], v7, v8, vcc ; GFX9-NEXT: v_subb_co_u32_e64 v7, s[0:1], v7, v8, vcc
; GFX9-NEXT: v_subrev_co_u32_e64 v8, s[0:1], s8, v6 ; GFX9-NEXT: v_subrev_co_u32_e64 v8, s[0:1], s10, v6
; GFX9-NEXT: v_subbrev_co_u32_e64 v7, s[0:1], 0, v7, s[0:1] ; GFX9-NEXT: v_subbrev_co_u32_e64 v7, s[0:1], 0, v7, s[0:1]
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v7 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v7
; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v8 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v8
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v7 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v7
; GFX9-NEXT: v_cndmask_b32_e64 v7, v9, v8, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v7, v9, v8, s[0:1]
; GFX9-NEXT: v_add_co_u32_e64 v8, s[0:1], 2, v3 ; GFX9-NEXT: v_add_co_u32_e64 v8, s[0:1], 2, v3
; GFX9-NEXT: v_addc_co_u32_e64 v9, s[0:1], 0, v4, s[0:1] ; GFX9-NEXT: v_addc_co_u32_e64 v9, s[0:1], 0, v4, s[0:1]
; GFX9-NEXT: v_add_co_u32_e64 v10, s[0:1], 1, v3 ; GFX9-NEXT: v_add_co_u32_e64 v10, s[0:1], 1, v3
; GFX9-NEXT: v_addc_co_u32_e64 v11, s[0:1], 0, v4, s[0:1] ; GFX9-NEXT: v_addc_co_u32_e64 v11, s[0:1], 0, v4, s[0:1]
; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v7 ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v7
; GFX9-NEXT: v_cndmask_b32_e64 v7, v11, v9, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v7, v11, v9, s[0:1]
; GFX9-NEXT: v_mov_b32_e32 v9, s7 ; GFX9-NEXT: v_mov_b32_e32 v9, s7
; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v9, v5, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v9, v5, vcc
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v5 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v5
; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v6 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v6
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s9, v5 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s11, v5
; GFX9-NEXT: v_cndmask_b32_e32 v5, v9, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v5, v9, v6, vcc
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GFX9-NEXT: v_cndmask_b32_e64 v5, v10, v8, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v5, v10, v8, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX9-NEXT: s_xor_b64 s[0:1], s[10:11], s[4:5] ; GFX9-NEXT: s_xor_b64 s[0:1], s[8:9], s[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
; GFX9-NEXT: v_xor_b32_e32 v3, s0, v3 ; GFX9-NEXT: v_xor_b32_e32 v3, s0, v3
; GFX9-NEXT: v_xor_b32_e32 v4, s1, v4 ; GFX9-NEXT: v_xor_b32_e32 v4, s1, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s1 ; GFX9-NEXT: v_mov_b32_e32 v5, s1
; GFX9-NEXT: v_subrev_co_u32_e32 v3, vcc, s0, v3 ; GFX9-NEXT: v_subrev_co_u32_e32 v3, vcc, s0, v3
; GFX9-NEXT: v_subb_co_u32_e32 v4, vcc, v4, v5, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v4, vcc, v4, v5, vcc
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] ; GFX9-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3]
▲ Show 20 Lines • Show All 650 Lines • ▼ Show 20 Lines
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 1 ; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 1
; CHECK-NEXT: [[TMP7:%.*]] = srem i64 [[TMP5]], [[TMP6]] ; CHECK-NEXT: [[TMP7:%.*]] = srem i64 [[TMP5]], [[TMP6]]
; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP7]], i64 1 ; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP7]], i64 1
; CHECK-NEXT: store <2 x i64> [[TMP8]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16 ; CHECK-NEXT: store <2 x i64> [[TMP8]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; GFX6-LABEL: srem_v2i64_pow2_shl_denom: ; GFX6-LABEL: srem_v2i64_pow2_shl_denom:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x11 ; GFX6-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd
; GFX6-NEXT: s_mov_b64 s[2:3], 0x1000 ; GFX6-NEXT: s_mov_b64 s[2:3], 0x1000
; GFX6-NEXT: s_mov_b32 s18, 0x4f800000 ; GFX6-NEXT: s_mov_b32 s18, 0x4f800000
; GFX6-NEXT: s_mov_b32 s19, 0x5f7ffffc ; GFX6-NEXT: s_mov_b32 s19, 0x5f7ffffc
; GFX6-NEXT: s_mov_b32 s20, 0x2f800000 ; GFX6-NEXT: s_mov_b32 s20, 0x2f800000
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_lshl_b64 s[14:15], s[2:3], s6 ; GFX6-NEXT: s_lshl_b64 s[14:15], s[2:3], s10
; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], s4 ; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], s8
; GFX6-NEXT: s_ashr_i32 s4, s3, 31 ; GFX6-NEXT: s_ashr_i32 s8, s3, 31
; GFX6-NEXT: s_add_u32 s2, s2, s4 ; GFX6-NEXT: s_add_u32 s2, s2, s8
; GFX6-NEXT: s_mov_b32 s5, s4 ; GFX6-NEXT: s_mov_b32 s9, s8
; GFX6-NEXT: s_addc_u32 s3, s3, s4 ; GFX6-NEXT: s_addc_u32 s3, s3, s8
; GFX6-NEXT: s_xor_b64 s[16:17], s[2:3], s[4:5] ; GFX6-NEXT: s_xor_b64 s[16:17], s[2:3], s[8:9]
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s16 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s16
; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s17 ; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s17
; GFX6-NEXT: s_mov_b32 s21, 0xcf800000 ; GFX6-NEXT: s_mov_b32 s21, 0xcf800000
; GFX6-NEXT: s_sub_u32 s2, 0, s16 ; GFX6-NEXT: s_sub_u32 s2, 0, s16
; GFX6-NEXT: s_subb_u32 s3, 0, s17 ; GFX6-NEXT: s_subb_u32 s3, 0, s17
; GFX6-NEXT: v_mac_f32_e32 v0, s18, v1 ; GFX6-NEXT: v_mac_f32_e32 v0, s18, v1
; GFX6-NEXT: v_rcp_f32_e32 v0, v0 ; GFX6-NEXT: v_rcp_f32_e32 v0, v0
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; GFX6-NEXT: s_ashr_i32 s12, s5, 31
; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd ; GFX6-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9
; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: s_add_u32 s0, s4, s12
; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: v_mul_f32_e32 v0, s19, v0 ; GFX6-NEXT: v_mul_f32_e32 v0, s19, v0
; GFX6-NEXT: v_mul_f32_e32 v1, s20, v0 ; GFX6-NEXT: v_mul_f32_e32 v1, s20, v0
; GFX6-NEXT: v_trunc_f32_e32 v1, v1 ; GFX6-NEXT: v_trunc_f32_e32 v1, v1
; GFX6-NEXT: v_mac_f32_e32 v0, s21, v1 ; GFX6-NEXT: v_mac_f32_e32 v0, s21, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v0
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_mov_b32 s13, s12
; GFX6-NEXT: s_ashr_i32 s12, s9, 31 ; GFX6-NEXT: s_addc_u32 s1, s5, s12
; GFX6-NEXT: s_add_u32 s0, s8, s12
; GFX6-NEXT: v_mul_lo_u32 v0, s2, v1 ; GFX6-NEXT: v_mul_lo_u32 v0, s2, v1
; GFX6-NEXT: v_mul_hi_u32 v3, s2, v2 ; GFX6-NEXT: v_mul_hi_u32 v3, s2, v2
; GFX6-NEXT: v_mul_lo_u32 v4, s3, v2 ; GFX6-NEXT: v_mul_lo_u32 v4, s3, v2
; GFX6-NEXT: v_mul_lo_u32 v5, s2, v2 ; GFX6-NEXT: v_mul_lo_u32 v5, s2, v2
; GFX6-NEXT: s_mov_b32 s13, s12 ; GFX6-NEXT: s_xor_b64 s[4:5], s[0:1], s[12:13]
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v3, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v3, v0
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v0, v4 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v0, v4
; GFX6-NEXT: v_mul_lo_u32 v0, v2, v3 ; GFX6-NEXT: v_mul_lo_u32 v0, v2, v3
; GFX6-NEXT: v_mul_hi_u32 v4, v2, v5 ; GFX6-NEXT: v_mul_hi_u32 v4, v2, v5
; GFX6-NEXT: v_mul_hi_u32 v6, v2, v3 ; GFX6-NEXT: v_mul_hi_u32 v6, v2, v3
; GFX6-NEXT: v_mul_hi_u32 v7, v1, v3 ; GFX6-NEXT: v_mul_hi_u32 v7, v1, v3
; GFX6-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX6-NEXT: v_mul_lo_u32 v3, v1, v3
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v4, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v4, v0
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v6, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v6, vcc
; GFX6-NEXT: v_mul_lo_u32 v6, v1, v5 ; GFX6-NEXT: v_mul_lo_u32 v6, v1, v5
; GFX6-NEXT: v_mul_hi_u32 v5, v1, v5 ; GFX6-NEXT: v_mul_hi_u32 v5, v1, v5
; GFX6-NEXT: s_addc_u32 s1, s9, s12 ; GFX6-NEXT: s_mov_b32 s11, 0xf000
; GFX6-NEXT: s_xor_b64 s[8:9], s[0:1], s[12:13] ; GFX6-NEXT: s_mov_b32 s10, -1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v6 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v6
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v4, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v4, v5, vcc
; GFX6-NEXT: v_mov_b32_e32 v0, 0 ; GFX6-NEXT: v_mov_b32_e32 v0, 0
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v0, vcc
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc
Show All 14 Lines
; GFX6-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX6-NEXT: v_mul_lo_u32 v3, v1, v3
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v7, v4 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v7, v4
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v6, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v6, vcc
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v5, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v5, v0, vcc
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v3, s8, v1 ; GFX6-NEXT: v_mul_lo_u32 v3, s4, v1
; GFX6-NEXT: v_mul_hi_u32 v4, s8, v2 ; GFX6-NEXT: v_mul_hi_u32 v4, s4, v2
; GFX6-NEXT: v_mul_hi_u32 v5, s8, v1 ; GFX6-NEXT: v_mul_hi_u32 v5, s4, v1
; GFX6-NEXT: v_mul_hi_u32 v6, s9, v1 ; GFX6-NEXT: v_mul_hi_u32 v6, s5, v1
; GFX6-NEXT: v_mul_lo_u32 v1, s9, v1 ; GFX6-NEXT: v_mul_lo_u32 v1, s5, v1
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc
; GFX6-NEXT: v_mul_lo_u32 v5, s9, v2 ; GFX6-NEXT: v_mul_lo_u32 v5, s5, v2
; GFX6-NEXT: v_mul_hi_u32 v2, s9, v2 ; GFX6-NEXT: v_mul_hi_u32 v2, s5, v2
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v4, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v4, v2, vcc
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v0, vcc
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, s16, v2 ; GFX6-NEXT: v_mul_lo_u32 v2, s16, v2
; GFX6-NEXT: v_mul_hi_u32 v3, s16, v1 ; GFX6-NEXT: v_mul_hi_u32 v3, s16, v1
; GFX6-NEXT: v_mul_lo_u32 v4, s17, v1 ; GFX6-NEXT: v_mul_lo_u32 v4, s17, v1
; GFX6-NEXT: v_mul_lo_u32 v1, s16, v1 ; GFX6-NEXT: v_mul_lo_u32 v1, s16, v1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s9, v2 ; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s5, v2
; GFX6-NEXT: v_mov_b32_e32 v4, s17 ; GFX6-NEXT: v_mov_b32_e32 v4, s17
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s8, v1 ; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s4, v1
; GFX6-NEXT: v_subb_u32_e64 v3, s[0:1], v3, v4, vcc ; GFX6-NEXT: v_subb_u32_e64 v3, s[0:1], v3, v4, vcc
; GFX6-NEXT: v_subrev_i32_e64 v5, s[0:1], s16, v1 ; GFX6-NEXT: v_subrev_i32_e64 v5, s[0:1], s16, v1
; GFX6-NEXT: v_subbrev_u32_e64 v6, s[2:3], 0, v3, s[0:1] ; GFX6-NEXT: v_subbrev_u32_e64 v6, s[2:3], 0, v3, s[0:1]
; GFX6-NEXT: v_cmp_le_u32_e64 s[2:3], s17, v6 ; GFX6-NEXT: v_cmp_le_u32_e64 s[2:3], s17, v6
; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[2:3] ; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[2:3]
; GFX6-NEXT: v_cmp_le_u32_e64 s[2:3], s16, v5 ; GFX6-NEXT: v_cmp_le_u32_e64 s[2:3], s16, v5
; GFX6-NEXT: v_subb_u32_e64 v3, s[0:1], v3, v4, s[0:1] ; GFX6-NEXT: v_subb_u32_e64 v3, s[0:1], v3, v4, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[2:3] ; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[2:3]
; GFX6-NEXT: v_cmp_eq_u32_e64 s[2:3], s17, v6 ; GFX6-NEXT: v_cmp_eq_u32_e64 s[2:3], s17, v6
; GFX6-NEXT: v_subrev_i32_e64 v4, s[0:1], s16, v5 ; GFX6-NEXT: v_subrev_i32_e64 v4, s[0:1], s16, v5
; GFX6-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[2:3] ; GFX6-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[2:3]
; GFX6-NEXT: v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1] ; GFX6-NEXT: v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1]
; GFX6-NEXT: s_ashr_i32 s2, s15, 31 ; GFX6-NEXT: s_ashr_i32 s2, s15, 31
; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v7 ; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v7
; GFX6-NEXT: s_add_u32 s8, s14, s2 ; GFX6-NEXT: s_add_u32 s4, s14, s2
; GFX6-NEXT: v_cndmask_b32_e64 v3, v6, v3, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v3, v6, v3, s[0:1]
; GFX6-NEXT: v_mov_b32_e32 v6, s9 ; GFX6-NEXT: v_mov_b32_e32 v6, s5
; GFX6-NEXT: s_mov_b32 s3, s2 ; GFX6-NEXT: s_mov_b32 s3, s2
; GFX6-NEXT: s_addc_u32 s9, s15, s2 ; GFX6-NEXT: s_addc_u32 s5, s15, s2
; GFX6-NEXT: s_xor_b64 s[8:9], s[8:9], s[2:3] ; GFX6-NEXT: s_xor_b64 s[4:5], s[4:5], s[2:3]
; GFX6-NEXT: v_cvt_f32_u32_e32 v7, s8 ; GFX6-NEXT: v_cvt_f32_u32_e32 v7, s4
; GFX6-NEXT: v_cvt_f32_u32_e32 v8, s9 ; GFX6-NEXT: v_cvt_f32_u32_e32 v8, s5
; GFX6-NEXT: v_subb_u32_e32 v2, vcc, v6, v2, vcc ; GFX6-NEXT: v_subb_u32_e32 v2, vcc, v6, v2, vcc
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s17, v2 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s17, v2
; GFX6-NEXT: v_mac_f32_e32 v7, s18, v8 ; GFX6-NEXT: v_mac_f32_e32 v7, s18, v8
; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s16, v1 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s16, v1
; GFX6-NEXT: v_rcp_f32_e32 v7, v7 ; GFX6-NEXT: v_rcp_f32_e32 v7, v7
; GFX6-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s17, v2 ; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s17, v2
; GFX6-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v3, v5, v4, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v3, v5, v4, s[0:1]
; GFX6-NEXT: v_mul_f32_e32 v4, s19, v7 ; GFX6-NEXT: v_mul_f32_e32 v4, s19, v7
; GFX6-NEXT: v_mul_f32_e32 v5, s20, v4 ; GFX6-NEXT: v_mul_f32_e32 v5, s20, v4
; GFX6-NEXT: v_trunc_f32_e32 v5, v5 ; GFX6-NEXT: v_trunc_f32_e32 v5, v5
; GFX6-NEXT: v_mac_f32_e32 v4, s21, v5 ; GFX6-NEXT: v_mac_f32_e32 v4, s21, v5
; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v4 ; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v4
; GFX6-NEXT: v_cvt_u32_f32_e32 v5, v5 ; GFX6-NEXT: v_cvt_u32_f32_e32 v5, v5
; GFX6-NEXT: s_sub_u32 s0, 0, s8 ; GFX6-NEXT: s_sub_u32 s0, 0, s4
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX6-NEXT: v_mul_hi_u32 v3, s0, v4 ; GFX6-NEXT: v_mul_hi_u32 v3, s0, v4
; GFX6-NEXT: v_mul_lo_u32 v6, s0, v5 ; GFX6-NEXT: v_mul_lo_u32 v6, s0, v5
; GFX6-NEXT: s_subb_u32 s1, 0, s9 ; GFX6-NEXT: s_subb_u32 s1, 0, s5
; GFX6-NEXT: v_mul_lo_u32 v7, s1, v4 ; GFX6-NEXT: v_mul_lo_u32 v7, s1, v4
; GFX6-NEXT: s_ashr_i32 s14, s11, 31 ; GFX6-NEXT: s_ashr_i32 s14, s7, 31
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6
; GFX6-NEXT: v_mul_lo_u32 v6, s0, v4 ; GFX6-NEXT: v_mul_lo_u32 v6, s0, v4
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v7 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v7
; GFX6-NEXT: v_mul_lo_u32 v7, v4, v3 ; GFX6-NEXT: v_mul_lo_u32 v7, v4, v3
; GFX6-NEXT: v_mul_hi_u32 v8, v4, v6 ; GFX6-NEXT: v_mul_hi_u32 v8, v4, v6
; GFX6-NEXT: v_mul_hi_u32 v9, v4, v3 ; GFX6-NEXT: v_mul_hi_u32 v9, v4, v3
; GFX6-NEXT: v_mul_hi_u32 v10, v5, v3 ; GFX6-NEXT: v_mul_hi_u32 v10, v5, v3
; GFX6-NEXT: v_mul_lo_u32 v3, v5, v3 ; GFX6-NEXT: v_mul_lo_u32 v3, v5, v3
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; GFX6-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; GFX6-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GFX6-NEXT: v_addc_u32_e32 v10, vcc, 0, v11, vcc ; GFX6-NEXT: v_addc_u32_e32 v10, vcc, 0, v11, vcc
; GFX6-NEXT: v_mul_lo_u32 v5, v4, v5 ; GFX6-NEXT: v_mul_lo_u32 v5, v4, v5
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v9, v6 ; GFX6-NEXT: v_add_i32_e32 v6, vcc, v9, v6
; GFX6-NEXT: v_addc_u32_e32 v6, vcc, v10, v8, vcc ; GFX6-NEXT: v_addc_u32_e32 v6, vcc, v10, v8, vcc
; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v7, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v7, v0, vcc
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v7, vcc ; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v7, vcc
; GFX6-NEXT: s_add_u32 s0, s10, s14 ; GFX6-NEXT: s_add_u32 s0, s6, s14
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GFX6-NEXT: s_addc_u32 s1, s11, s14 ; GFX6-NEXT: s_addc_u32 s1, s7, s14
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v4, v6, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v4, v6, vcc
; GFX6-NEXT: s_xor_b64 s[10:11], s[0:1], s[14:15] ; GFX6-NEXT: s_xor_b64 s[6:7], s[0:1], s[14:15]
; GFX6-NEXT: v_mul_lo_u32 v5, s10, v4 ; GFX6-NEXT: v_mul_lo_u32 v5, s6, v4
; GFX6-NEXT: v_mul_hi_u32 v6, s10, v3 ; GFX6-NEXT: v_mul_hi_u32 v6, s6, v3
; GFX6-NEXT: v_mul_hi_u32 v8, s10, v4 ; GFX6-NEXT: v_mul_hi_u32 v8, s6, v4
; GFX6-NEXT: v_mul_hi_u32 v9, s11, v4 ; GFX6-NEXT: v_mul_hi_u32 v9, s7, v4
; GFX6-NEXT: v_mul_lo_u32 v4, s11, v4 ; GFX6-NEXT: v_mul_lo_u32 v4, s7, v4
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v8, vcc ; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v8, vcc
; GFX6-NEXT: v_mul_lo_u32 v8, s11, v3 ; GFX6-NEXT: v_mul_lo_u32 v8, s7, v3
; GFX6-NEXT: v_mul_hi_u32 v3, s11, v3 ; GFX6-NEXT: v_mul_hi_u32 v3, s7, v3
; GFX6-NEXT: v_mov_b32_e32 v7, s12 ; GFX6-NEXT: v_mov_b32_e32 v7, s12
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v8 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v3, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v3, vcc
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v9, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v9, v0, vcc
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v0, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, s8, v0 ; GFX6-NEXT: v_mul_lo_u32 v4, s4, v0
; GFX6-NEXT: v_mul_hi_u32 v5, s8, v3 ; GFX6-NEXT: v_mul_hi_u32 v5, s4, v3
; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s12, v1 ; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s12, v1
; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v2, v7, vcc ; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v2, v7, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, s9, v3 ; GFX6-NEXT: v_mul_lo_u32 v2, s5, v3
; GFX6-NEXT: v_mul_lo_u32 v3, s8, v3 ; GFX6-NEXT: v_mul_lo_u32 v3, s4, v3
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v4, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v4, v2
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s11, v2 ; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s7, v2
; GFX6-NEXT: v_mov_b32_e32 v5, s9 ; GFX6-NEXT: v_mov_b32_e32 v5, s5
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s10, v3 ; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s6, v3
; GFX6-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc ; GFX6-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
; GFX6-NEXT: v_subrev_i32_e64 v6, s[0:1], s8, v3 ; GFX6-NEXT: v_subrev_i32_e64 v6, s[0:1], s4, v3
; GFX6-NEXT: v_subbrev_u32_e64 v7, s[2:3], 0, v4, s[0:1] ; GFX6-NEXT: v_subbrev_u32_e64 v7, s[2:3], 0, v4, s[0:1]
; GFX6-NEXT: v_cmp_le_u32_e64 s[2:3], s9, v7 ; GFX6-NEXT: v_cmp_le_u32_e64 s[2:3], s5, v7
; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[2:3] ; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[2:3]
; GFX6-NEXT: v_cmp_le_u32_e64 s[2:3], s8, v6 ; GFX6-NEXT: v_cmp_le_u32_e64 s[2:3], s4, v6
; GFX6-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, s[0:1] ; GFX6-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[2:3] ; GFX6-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[2:3]
; GFX6-NEXT: v_cmp_eq_u32_e64 s[2:3], s9, v7 ; GFX6-NEXT: v_cmp_eq_u32_e64 s[2:3], s5, v7
; GFX6-NEXT: v_subrev_i32_e64 v5, s[0:1], s8, v6 ; GFX6-NEXT: v_subrev_i32_e64 v5, s[0:1], s4, v6
; GFX6-NEXT: v_cndmask_b32_e64 v8, v8, v9, s[2:3] ; GFX6-NEXT: v_cndmask_b32_e64 v8, v8, v9, s[2:3]
; GFX6-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1] ; GFX6-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v8 ; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v8
; GFX6-NEXT: v_cndmask_b32_e64 v4, v7, v4, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v4, v7, v4, s[0:1]
; GFX6-NEXT: v_mov_b32_e32 v7, s11 ; GFX6-NEXT: v_mov_b32_e32 v7, s7
; GFX6-NEXT: v_subb_u32_e32 v2, vcc, v7, v2, vcc ; GFX6-NEXT: v_subb_u32_e32 v2, vcc, v7, v2, vcc
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s9, v2 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s5, v2
; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v3 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s4, v3
; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s9, v2 ; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s5, v2
; GFX6-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX6-NEXT: v_xor_b32_e32 v3, s14, v3 ; GFX6-NEXT: v_xor_b32_e32 v3, s14, v3
; GFX6-NEXT: v_xor_b32_e32 v4, s14, v2 ; GFX6-NEXT: v_xor_b32_e32 v4, s14, v2
; GFX6-NEXT: v_mov_b32_e32 v5, s14 ; GFX6-NEXT: v_mov_b32_e32 v5, s14
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s14, v3 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s14, v3
; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v4, v5, vcc ; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v4, v5, vcc
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: srem_v2i64_pow2_shl_denom: ; GFX9-LABEL: srem_v2i64_pow2_shl_denom:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x44 ; GFX9-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
; GFX9-NEXT: s_mov_b64 s[2:3], 0x1000 ; GFX9-NEXT: s_mov_b64 s[2:3], 0x1000
; GFX9-NEXT: s_mov_b32 s16, 0x4f800000 ; GFX9-NEXT: s_mov_b32 s16, 0x4f800000
; GFX9-NEXT: s_mov_b32 s17, 0x5f7ffffc ; GFX9-NEXT: s_mov_b32 s17, 0x5f7ffffc
; GFX9-NEXT: s_mov_b32 s18, 0x2f800000 ; GFX9-NEXT: s_mov_b32 s18, 0x2f800000
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshl_b64 s[10:11], s[2:3], s6 ; GFX9-NEXT: s_lshl_b64 s[10:11], s[2:3], s10
; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], s4 ; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], s8
; GFX9-NEXT: s_ashr_i32 s4, s3, 31 ; GFX9-NEXT: s_ashr_i32 s8, s3, 31
; GFX9-NEXT: s_add_u32 s2, s2, s4 ; GFX9-NEXT: s_add_u32 s2, s2, s8
; GFX9-NEXT: s_mov_b32 s5, s4 ; GFX9-NEXT: s_mov_b32 s9, s8
; GFX9-NEXT: s_addc_u32 s3, s3, s4 ; GFX9-NEXT: s_addc_u32 s3, s3, s8
; GFX9-NEXT: s_xor_b64 s[12:13], s[2:3], s[4:5] ; GFX9-NEXT: s_xor_b64 s[12:13], s[2:3], s[8:9]
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s12 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s12
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s13 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s13
; GFX9-NEXT: s_mov_b32 s19, 0xcf800000 ; GFX9-NEXT: s_mov_b32 s19, 0xcf800000
; GFX9-NEXT: s_sub_u32 s2, 0, s12 ; GFX9-NEXT: s_sub_u32 s2, 0, s12
; GFX9-NEXT: s_subb_u32 s3, 0, s13 ; GFX9-NEXT: s_subb_u32 s3, 0, s13
; GFX9-NEXT: v_mac_f32_e32 v0, s16, v1 ; GFX9-NEXT: v_mac_f32_e32 v0, s16, v1
; GFX9-NEXT: v_rcp_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_f32_e32 v0, v0
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 ; GFX9-NEXT: s_ashr_i32 s8, s5, 31
; GFX9-NEXT: s_mov_b32 s9, s8
; GFX9-NEXT: v_mul_f32_e32 v0, s17, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, s17, v0
; GFX9-NEXT: v_mul_f32_e32 v1, s18, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, s18, v0
; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1
; GFX9-NEXT: v_mac_f32_e32 v0, s19, v1 ; GFX9-NEXT: v_mac_f32_e32 v0, s19, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_ashr_i32 s8, s5, 31
; GFX9-NEXT: s_mov_b32 s9, s8
; GFX9-NEXT: v_mul_lo_u32 v0, s2, v1 ; GFX9-NEXT: v_mul_lo_u32 v0, s2, v1
; GFX9-NEXT: v_mul_hi_u32 v3, s2, v2 ; GFX9-NEXT: v_mul_hi_u32 v3, s2, v2
; GFX9-NEXT: v_mul_lo_u32 v5, s3, v2 ; GFX9-NEXT: v_mul_lo_u32 v5, s3, v2
; GFX9-NEXT: v_mul_lo_u32 v4, s2, v2 ; GFX9-NEXT: v_mul_lo_u32 v4, s2, v2
; GFX9-NEXT: v_add_u32_e32 v0, v3, v0 ; GFX9-NEXT: v_add_u32_e32 v0, v3, v0
; GFX9-NEXT: v_add_u32_e32 v5, v0, v5 ; GFX9-NEXT: v_add_u32_e32 v5, v0, v5
; GFX9-NEXT: v_mul_hi_u32 v3, v2, v4 ; GFX9-NEXT: v_mul_hi_u32 v3, v2, v4
; GFX9-NEXT: v_mul_lo_u32 v6, v2, v5 ; GFX9-NEXT: v_mul_lo_u32 v6, v2, v5
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llvm/test/CodeGen/AMDGPU/ashr.v2i16.ll

Show All 23 Lines
define amdgpu_kernel void @s_ashr_v2i16(<2 x i16> addrspace(1)* %out, i32, <2 x i16> %lhs, i32, <2 x i16> %rhs) #0 { define amdgpu_kernel void @s_ashr_v2i16(<2 x i16> addrspace(1)* %out, i32, <2 x i16> %lhs, i32, <2 x i16> %rhs) #0 {
%result = ashr <2 x i16> %lhs, %rhs %result = ashr <2 x i16> %lhs, %rhs
store <2 x i16> %result, <2 x i16> addrspace(1)* %out store <2 x i16> %result, <2 x i16> addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}v_ashr_v2i16: ; GCN-LABEL: {{^}}v_ashr_v2i16:
; GCN: {{buffer|flat|global}}_load_dword [[LHS:v[0-9]+]] ; GCN: {{buffer|flat|global}}_load_dwordx2 v[[[LHS:[0-9]+]]:[[RHS:[0-9]+]]]
; GCN: {{buffer|flat|global}}_load_dword [[RHS:v[0-9]+]] ; GFX9: v_pk_ashrrev_i16 [[RESULT:v[0-9]+]], v[[RHS]], v[[LHS]]
; GFX9: v_pk_ashrrev_i16 [[RESULT:v[0-9]+]], [[RHS]], [[LHS]]
; VI: v_ashrrev_i16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; VI: v_ashrrev_i16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
; VI: v_ashrrev_i16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI: v_ashrrev_i16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; VI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
; CI-DAG: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 16 ; CI-DAG: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 16
; CI: v_ashrrev_i32_e32 v{{[0-9]+}}, 16, [[LHS]] ; CI: v_ashrrev_i32_e32 v{{[0-9]+}}, 16, v[[LHS]]
; CI: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}} ; CI: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
; CI: v_ashrrev_i32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; CI: v_ashrrev_i32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
; CI: v_ashrrev_i32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; CI: v_ashrrev_i32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
; CI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}} ; CI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
; CI: v_and_b32_e32 v{{[0-9]+}}, 0xffff, v{{[0-9]+}} ; CI: v_and_b32_e32 v{{[0-9]+}}, 0xffff, v{{[0-9]+}}
; CI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; CI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @v_ashr_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { define amdgpu_kernel void @v_ashr_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @ashr_v_imm_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 {
%out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
%vgpr = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep %vgpr = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
%result = ashr <2 x i16> %vgpr, <i16 8, i16 8> %result = ashr <2 x i16> %vgpr, <i16 8, i16 8>
store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep
ret void ret void
} }
; GCN-LABEL: {{^}}v_ashr_v4i16: ; GCN-LABEL: {{^}}v_ashr_v4i16:
; GCN: {{buffer|flat|global}}_load_dwordx2 ; GCN: {{buffer|flat|global}}_load_dwordx4
; GCN: {{buffer|flat|global}}_load_dwordx2
; GFX9: v_pk_ashrrev_i16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; GFX9: v_pk_ashrrev_i16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
; GFX9: v_pk_ashrrev_i16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; GFX9: v_pk_ashrrev_i16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
; VI: v_ashrrev_i16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; VI: v_ashrrev_i16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
; VI: v_ashrrev_i16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI: v_ashrrev_i16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI: v_ashrrev_i16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; VI: v_ashrrev_i16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
; VI: v_ashrrev_i16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI: v_ashrrev_i16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; VI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
Show All 36 Lines

llvm/test/CodeGen/AMDGPU/fmax_legacy.ll

Show First 20 Lines • Show All 151 Lines • ▼ Show 20 Lines
; GCN-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]] ; GCN-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
; EG: MAX ; EG: MAX
define amdgpu_kernel void @test_fmax_legacy_ogt_v1f32(<1 x float> addrspace(1)* %out, <1 x float> addrspace(1)* %in) #0 { define amdgpu_kernel void @test_fmax_legacy_ogt_v1f32(<1 x float> addrspace(1)* %out, <1 x float> addrspace(1)* %in) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
%gep.0 = getelementptr <1 x float>, <1 x float> addrspace(1)* %in, i32 %tid %gep.0 = getelementptr <1 x float>, <1 x float> addrspace(1)* %in, i32 %tid
%gep.1 = getelementptr <1 x float>, <1 x float> addrspace(1)* %gep.0, i32 1 %gep.1 = getelementptr <1 x float>, <1 x float> addrspace(1)* %gep.0, i32 1
%a = load <1 x float>, <1 x float> addrspace(1)* %gep.0 %a = load volatile <1 x float>, <1 x float> addrspace(1)* %gep.0
%b = load <1 x float>, <1 x float> addrspace(1)* %gep.1 %b = load volatile <1 x float>, <1 x float> addrspace(1)* %gep.1
%cmp = fcmp ogt <1 x float> %a, %b %cmp = fcmp ogt <1 x float> %a, %b
%val = select <1 x i1> %cmp, <1 x float> %a, <1 x float> %b %val = select <1 x i1> %cmp, <1 x float> %a, <1 x float> %b
store <1 x float> %val, <1 x float> addrspace(1)* %out store <1 x float> %val, <1 x float> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}test_fmax_legacy_ogt_v3f32: ; FUNC-LABEL: {{^}}test_fmax_legacy_ogt_v3f32:
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llvm/test/CodeGen/AMDGPU/fmin_legacy.ll

Show First 20 Lines • Show All 181 Lines • ▼ Show 20 Lines
; VI-SAFE: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]] ; VI-SAFE: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]
; GCN-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]] ; GCN-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
define amdgpu_kernel void @test_fmin_legacy_ult_v1f32(<1 x float> addrspace(1)* %out, <1 x float> addrspace(1)* %in) #0 { define amdgpu_kernel void @test_fmin_legacy_ult_v1f32(<1 x float> addrspace(1)* %out, <1 x float> addrspace(1)* %in) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
%gep.0 = getelementptr <1 x float>, <1 x float> addrspace(1)* %in, i32 %tid %gep.0 = getelementptr <1 x float>, <1 x float> addrspace(1)* %in, i32 %tid
%gep.1 = getelementptr <1 x float>, <1 x float> addrspace(1)* %gep.0, i32 1 %gep.1 = getelementptr <1 x float>, <1 x float> addrspace(1)* %gep.0, i32 1
%a = load <1 x float>, <1 x float> addrspace(1)* %gep.0 %a = load volatile <1 x float>, <1 x float> addrspace(1)* %gep.0
%b = load <1 x float>, <1 x float> addrspace(1)* %gep.1 %b = load volatile <1 x float>, <1 x float> addrspace(1)* %gep.1
%cmp = fcmp ult <1 x float> %a, %b %cmp = fcmp ult <1 x float> %a, %b
%val = select <1 x i1> %cmp, <1 x float> %a, <1 x float> %b %val = select <1 x i1> %cmp, <1 x float> %a, <1 x float> %b
store <1 x float> %val, <1 x float> addrspace(1)* %out store <1 x float> %val, <1 x float> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}test_fmin_legacy_ult_v2f32: ; FUNC-LABEL: {{^}}test_fmin_legacy_ult_v2f32:
Show All 9 Lines
; GCN-NONAN: v_min_f32_e32 ; GCN-NONAN: v_min_f32_e32
; GCN-NONAN: v_min_f32_e32 ; GCN-NONAN: v_min_f32_e32
define amdgpu_kernel void @test_fmin_legacy_ult_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in) #0 { define amdgpu_kernel void @test_fmin_legacy_ult_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
%gep.0 = getelementptr <2 x float>, <2 x float> addrspace(1)* %in, i32 %tid %gep.0 = getelementptr <2 x float>, <2 x float> addrspace(1)* %in, i32 %tid
%gep.1 = getelementptr <2 x float>, <2 x float> addrspace(1)* %gep.0, i32 1 %gep.1 = getelementptr <2 x float>, <2 x float> addrspace(1)* %gep.0, i32 1
%a = load <2 x float>, <2 x float> addrspace(1)* %gep.0 %a = load volatile <2 x float>, <2 x float> addrspace(1)* %gep.0
%b = load <2 x float>, <2 x float> addrspace(1)* %gep.1 %b = load volatile <2 x float>, <2 x float> addrspace(1)* %gep.1
%cmp = fcmp ult <2 x float> %a, %b %cmp = fcmp ult <2 x float> %a, %b
%val = select <2 x i1> %cmp, <2 x float> %a, <2 x float> %b %val = select <2 x i1> %cmp, <2 x float> %a, <2 x float> %b
store <2 x float> %val, <2 x float> addrspace(1)* %out store <2 x float> %val, <2 x float> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}test_fmin_legacy_ult_v3f32: ; FUNC-LABEL: {{^}}test_fmin_legacy_ult_v3f32:
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llvm/test/CodeGen/AMDGPU/fshl.ll

Show First 20 Lines • Show All 155 Lines • ▼ Show 20 Linesentry:
%0 = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 7) %0 = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 7)
store i32 %0, i32 addrspace(1)* %in store i32 %0, i32 addrspace(1)* %in
ret void ret void
} }
define amdgpu_kernel void @fshl_v2i32(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y, <2 x i32> %z) { define amdgpu_kernel void @fshl_v2i32(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y, <2 x i32> %z) {
; SI-LABEL: fshl_v2i32: ; SI-LABEL: fshl_v2i32:
; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9
; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xb
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xf ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xf
; SI-NEXT: s_mov_b32 s7, 0xf000 ; SI-NEXT: s_mov_b32 s11, 0xf000
; SI-NEXT: s_mov_b32 s10, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s3 ; SI-NEXT: v_mov_b32_e32 v0, s7
; SI-NEXT: s_mov_b32 s6, -1 ; SI-NEXT: v_alignbit_b32 v0, s5, v0, 1
; SI-NEXT: v_alignbit_b32 v0, s9, v0, 1
; SI-NEXT: s_not_b32 s1, s1 ; SI-NEXT: s_not_b32 s1, s1
; SI-NEXT: s_lshr_b32 s3, s9, 1 ; SI-NEXT: s_lshr_b32 s2, s5, 1
; SI-NEXT: v_mov_b32_e32 v1, s1 ; SI-NEXT: v_mov_b32_e32 v1, s1
; SI-NEXT: v_alignbit_b32 v1, s3, v0, v1 ; SI-NEXT: v_alignbit_b32 v1, s2, v0, v1
; SI-NEXT: v_mov_b32_e32 v0, s2 ; SI-NEXT: v_mov_b32_e32 v0, s6
; SI-NEXT: s_not_b32 s0, s0 ; SI-NEXT: s_not_b32 s0, s0
; SI-NEXT: v_alignbit_b32 v0, s8, v0, 1 ; SI-NEXT: v_alignbit_b32 v0, s4, v0, 1
; SI-NEXT: s_lshr_b32 s1, s8, 1 ; SI-NEXT: s_lshr_b32 s1, s4, 1
; SI-NEXT: v_mov_b32_e32 v2, s0 ; SI-NEXT: v_mov_b32_e32 v2, s0
; SI-NEXT: v_alignbit_b32 v0, s1, v0, v2 ; SI-NEXT: v_alignbit_b32 v0, s1, v0, v2
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: fshl_v2i32: ; VI-LABEL: fshl_v2i32:
; VI: ; %bb.0: ; %entry ; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c ; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x3c
; VI-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x3c
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s3 ; VI-NEXT: v_mov_b32_e32 v0, s7
; VI-NEXT: s_lshr_b32 s3, s5, 1 ; VI-NEXT: s_not_b32 s3, s3
; VI-NEXT: s_lshr_b32 s7, s5, 1
; VI-NEXT: v_alignbit_b32 v0, s5, v0, 1 ; VI-NEXT: v_alignbit_b32 v0, s5, v0, 1
; VI-NEXT: s_not_b32 s5, s7 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_mov_b32_e32 v1, s5 ; VI-NEXT: v_alignbit_b32 v1, s7, v0, v1
; VI-NEXT: v_alignbit_b32 v1, s3, v0, v1 ; VI-NEXT: v_mov_b32_e32 v0, s6
; VI-NEXT: v_mov_b32_e32 v0, s2 ; VI-NEXT: s_not_b32 s2, s2
; VI-NEXT: s_not_b32 s3, s6
; VI-NEXT: v_alignbit_b32 v0, s4, v0, 1 ; VI-NEXT: v_alignbit_b32 v0, s4, v0, 1
; VI-NEXT: s_lshr_b32 s2, s4, 1 ; VI-NEXT: s_lshr_b32 s3, s4, 1
; VI-NEXT: v_mov_b32_e32 v2, s3 ; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_alignbit_b32 v0, s2, v0, v2 ; VI-NEXT: v_alignbit_b32 v0, s3, v0, v2
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0 ; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: fshl_v2i32: ; GFX9-LABEL: fshl_v2i32:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x3c ; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x3c
; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s3 ; GFX9-NEXT: v_mov_b32_e32 v0, s7
; GFX9-NEXT: v_alignbit_b32 v0, s5, v0, 1
; GFX9-NEXT: s_lshr_b32 s0, s5, 1 ; GFX9-NEXT: s_lshr_b32 s0, s5, 1
; GFX9-NEXT: s_not_b32 s1, s9 ; GFX9-NEXT: s_not_b32 s1, s9
; GFX9-NEXT: v_alignbit_b32 v0, s5, v0, 1
; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_alignbit_b32 v1, s0, v0, v1 ; GFX9-NEXT: v_alignbit_b32 v1, s0, v0, v1
; GFX9-NEXT: v_mov_b32_e32 v0, s2 ; GFX9-NEXT: v_mov_b32_e32 v0, s6
; GFX9-NEXT: s_not_b32 s1, s8 ; GFX9-NEXT: s_not_b32 s1, s8
; GFX9-NEXT: v_alignbit_b32 v0, s4, v0, 1 ; GFX9-NEXT: v_alignbit_b32 v0, s4, v0, 1
; GFX9-NEXT: s_lshr_b32 s0, s4, 1 ; GFX9-NEXT: s_lshr_b32 s0, s4, 1
; GFX9-NEXT: v_mov_b32_e32 v3, s1 ; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_alignbit_b32 v0, s0, v0, v3 ; GFX9-NEXT: v_alignbit_b32 v0, s0, v0, v3
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7] ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; R600-LABEL: fshl_v2i32: ; R600-LABEL: fshl_v2i32:
; R600: ; %bb.0: ; %entry ; R600: ; %bb.0: ; %entry
; R600-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[] ; R600-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; R600-NEXT: ALU clause starting at 4: ; R600-NEXT: ALU clause starting at 4:
; R600-NEXT: LSHR T0.Z, KC0[3].X, 1, ; R600-NEXT: LSHR T0.Z, KC0[3].X, 1,
; R600-NEXT: BIT_ALIGN_INT * T0.W, KC0[3].X, KC0[3].Z, 1, ; R600-NEXT: BIT_ALIGN_INT * T0.W, KC0[3].X, KC0[3].Z, 1,
; R600-NEXT: NOT_INT * T1.W, KC0[4].X, ; R600-NEXT: NOT_INT * T1.W, KC0[4].X,
; R600-NEXT: BIT_ALIGN_INT T0.Y, T0.Z, T0.W, PV.W, ; R600-NEXT: BIT_ALIGN_INT T0.Y, T0.Z, T0.W, PV.W,
; R600-NEXT: LSHR T0.Z, KC0[2].W, 1, ; R600-NEXT: LSHR T0.Z, KC0[2].W, 1,
; R600-NEXT: BIT_ALIGN_INT * T0.W, KC0[2].W, KC0[3].Y, 1, ; R600-NEXT: BIT_ALIGN_INT * T0.W, KC0[2].W, KC0[3].Y, 1,
; R600-NEXT: NOT_INT * T1.W, KC0[3].W, ; R600-NEXT: NOT_INT * T1.W, KC0[3].W,
; R600-NEXT: BIT_ALIGN_INT T0.X, T0.Z, T0.W, PV.W, ; R600-NEXT: BIT_ALIGN_INT T0.X, T0.Z, T0.W, PV.W,
; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00) ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
; ;
; GFX10-LABEL: fshl_v2i32: ; GFX10-LABEL: fshl_v2i32:
; GFX10: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_clause 0x3 ; GFX10-NEXT: s_clause 0x2
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
; GFX10-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34 ; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x3c
; GFX10-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x3c
; GFX10-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x24
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_lshr_b32 s0, s3, 1 ; GFX10-NEXT: v_alignbit_b32 v0, s5, s7, 1
; GFX10-NEXT: v_alignbit_b32 v0, s3, s5, 1 ; GFX10-NEXT: v_alignbit_b32 v3, s4, s6, 1
; GFX10-NEXT: v_alignbit_b32 v3, s2, s4, 1 ; GFX10-NEXT: s_lshr_b32 s0, s5, 1
; GFX10-NEXT: s_not_b32 s1, s7 ; GFX10-NEXT: s_not_b32 s1, s3
; GFX10-NEXT: s_lshr_b32 s2, s2, 1 ; GFX10-NEXT: s_lshr_b32 s3, s4, 1
; GFX10-NEXT: s_not_b32 s3, s6 ; GFX10-NEXT: s_not_b32 s2, s2
; GFX10-NEXT: v_alignbit_b32 v1, s0, v0, s1 ; GFX10-NEXT: v_alignbit_b32 v1, s0, v0, s1
; GFX10-NEXT: v_alignbit_b32 v0, s2, v3, s3 ; GFX10-NEXT: v_alignbit_b32 v0, s3, v3, s2
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9] ; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
entry: entry:
%0 = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z) %0 = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z)
store <2 x i32> %0, <2 x i32> addrspace(1)* %in store <2 x i32> %0, <2 x i32> addrspace(1)* %in
ret void ret void
} }
define amdgpu_kernel void @fshl_v2i32_imm(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y) { define amdgpu_kernel void @fshl_v2i32_imm(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y) {
; SI-LABEL: fshl_v2i32_imm: ; SI-LABEL: fshl_v2i32_imm:
; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
; SI-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0xb
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s5 ; SI-NEXT: v_mov_b32_e32 v0, s7
; SI-NEXT: v_alignbit_b32 v1, s7, v0, 23 ; SI-NEXT: v_mov_b32_e32 v2, s6
; SI-NEXT: v_mov_b32_e32 v0, s4 ; SI-NEXT: v_alignbit_b32 v1, s5, v0, 23
; SI-NEXT: v_alignbit_b32 v0, s6, v0, 25 ; SI-NEXT: v_alignbit_b32 v0, s4, v2, 25
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: fshl_v2i32_imm: ; VI-LABEL: fshl_v2i32_imm:
; VI: ; %bb.0: ; %entry ; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s3 ; VI-NEXT: v_mov_b32_e32 v0, s7
; VI-NEXT: v_mov_b32_e32 v2, s2 ; VI-NEXT: v_mov_b32_e32 v2, s6
; VI-NEXT: v_alignbit_b32 v1, s5, v0, 23 ; VI-NEXT: v_alignbit_b32 v1, s5, v0, 23
; VI-NEXT: v_alignbit_b32 v0, s4, v2, 25 ; VI-NEXT: v_alignbit_b32 v0, s4, v2, 25
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0 ; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: fshl_v2i32_imm: ; GFX9-LABEL: fshl_v2i32_imm:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x24
; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s3 ; GFX9-NEXT: v_mov_b32_e32 v0, s7
; GFX9-NEXT: v_mov_b32_e32 v3, s2 ; GFX9-NEXT: v_mov_b32_e32 v3, s6
; GFX9-NEXT: v_alignbit_b32 v1, s5, v0, 23 ; GFX9-NEXT: v_alignbit_b32 v1, s5, v0, 23
; GFX9-NEXT: v_alignbit_b32 v0, s4, v3, 25 ; GFX9-NEXT: v_alignbit_b32 v0, s4, v3, 25
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7] ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; R600-LABEL: fshl_v2i32_imm: ; R600-LABEL: fshl_v2i32_imm:
; R600: ; %bb.0: ; %entry ; R600: ; %bb.0: ; %entry
; R600-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[] ; R600-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; R600-NEXT: ALU clause starting at 4: ; R600-NEXT: ALU clause starting at 4:
; R600-NEXT: BIT_ALIGN_INT * T0.Y, KC0[3].X, KC0[3].Z, literal.x, ; R600-NEXT: BIT_ALIGN_INT * T0.Y, KC0[3].X, KC0[3].Z, literal.x,
; R600-NEXT: 23(3.222986e-44), 0(0.000000e+00) ; R600-NEXT: 23(3.222986e-44), 0(0.000000e+00)
; R600-NEXT: BIT_ALIGN_INT * T0.X, KC0[2].W, KC0[3].Y, literal.x, ; R600-NEXT: BIT_ALIGN_INT * T0.X, KC0[2].W, KC0[3].Y, literal.x,
; R600-NEXT: 25(3.503246e-44), 0(0.000000e+00) ; R600-NEXT: 25(3.503246e-44), 0(0.000000e+00)
; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00) ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
; ;
; GFX10-LABEL: fshl_v2i32_imm: ; GFX10-LABEL: fshl_v2i32_imm:
; GFX10: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_clause 0x2 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
; GFX10-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34 ; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX10-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x24
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_alignbit_b32 v1, s3, s5, 23 ; GFX10-NEXT: v_alignbit_b32 v1, s5, s7, 23
; GFX10-NEXT: v_alignbit_b32 v0, s2, s4, 25 ; GFX10-NEXT: v_alignbit_b32 v0, s4, s6, 25
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7] ; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
entry: entry:
%0 = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> <i32 7, i32 9>) %0 = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> <i32 7, i32 9>)
store <2 x i32> %0, <2 x i32> addrspace(1)* %in store <2 x i32> %0, <2 x i32> addrspace(1)* %in
ret void ret void
} }
define amdgpu_kernel void @fshl_v4i32(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y, <4 x i32> %z) { define amdgpu_kernel void @fshl_v4i32(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {
; SI-LABEL: fshl_v4i32: ; SI-LABEL: fshl_v4i32:
; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x11 ; SI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd
; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0x15
; SI-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0xd ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x15 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s11, 0xf000 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s7 ; SI-NEXT: v_mov_b32_e32 v0, s11
; SI-NEXT: s_mov_b32 s10, -1 ; SI-NEXT: s_not_b32 s11, s15
; SI-NEXT: v_alignbit_b32 v0, s15, v0, 1 ; SI-NEXT: v_alignbit_b32 v0, s7, v0, 1
; SI-NEXT: s_not_b32 s3, s3 ; SI-NEXT: s_lshr_b32 s7, s7, 1
; SI-NEXT: s_lshr_b32 s7, s15, 1 ; SI-NEXT: v_mov_b32_e32 v1, s11
; SI-NEXT: v_mov_b32_e32 v1, s3
; SI-NEXT: v_alignbit_b32 v3, s7, v0, v1 ; SI-NEXT: v_alignbit_b32 v3, s7, v0, v1
; SI-NEXT: v_mov_b32_e32 v0, s6 ; SI-NEXT: v_mov_b32_e32 v0, s10
; SI-NEXT: s_not_b32 s2, s2 ; SI-NEXT: s_not_b32 s7, s14
; SI-NEXT: v_alignbit_b32 v0, s14, v0, 1 ; SI-NEXT: v_alignbit_b32 v0, s6, v0, 1
; SI-NEXT: s_lshr_b32 s3, s14, 1 ; SI-NEXT: s_lshr_b32 s6, s6, 1
; SI-NEXT: v_mov_b32_e32 v1, s2 ; SI-NEXT: v_mov_b32_e32 v1, s7
; SI-NEXT: v_alignbit_b32 v2, s3, v0, v1 ; SI-NEXT: v_alignbit_b32 v2, s6, v0, v1
; SI-NEXT: v_mov_b32_e32 v0, s5 ; SI-NEXT: v_mov_b32_e32 v0, s9
; SI-NEXT: s_not_b32 s1, s1 ; SI-NEXT: s_not_b32 s6, s13
; SI-NEXT: v_alignbit_b32 v0, s13, v0, 1 ; SI-NEXT: v_alignbit_b32 v0, s5, v0, 1
; SI-NEXT: s_lshr_b32 s2, s13, 1 ; SI-NEXT: s_lshr_b32 s5, s5, 1
; SI-NEXT: v_mov_b32_e32 v1, s1 ; SI-NEXT: v_mov_b32_e32 v1, s6
; SI-NEXT: v_alignbit_b32 v1, s2, v0, v1 ; SI-NEXT: v_alignbit_b32 v1, s5, v0, v1
; SI-NEXT: v_mov_b32_e32 v0, s4 ; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: s_not_b32 s0, s0 ; SI-NEXT: s_not_b32 s5, s12
; SI-NEXT: v_alignbit_b32 v0, s12, v0, 1 ; SI-NEXT: v_alignbit_b32 v0, s4, v0, 1
; SI-NEXT: s_lshr_b32 s1, s12, 1 ; SI-NEXT: s_lshr_b32 s4, s4, 1
; SI-NEXT: v_mov_b32_e32 v4, s0 ; SI-NEXT: v_mov_b32_e32 v4, s5
; SI-NEXT: v_alignbit_b32 v0, s1, v0, v4 ; SI-NEXT: v_alignbit_b32 v0, s4, v0, v4
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: fshl_v4i32: ; VI-LABEL: fshl_v4i32:
; VI: ; %bb.0: ; %entry ; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x44 ; VI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
; VI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x34
; VI-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0x54 ; VI-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0x54
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s7 ; VI-NEXT: v_mov_b32_e32 v0, s11
; VI-NEXT: s_lshr_b32 s2, s11, 1
; VI-NEXT: s_not_b32 s3, s15 ; VI-NEXT: s_not_b32 s3, s15
; VI-NEXT: v_alignbit_b32 v0, s11, v0, 1 ; VI-NEXT: s_lshr_b32 s2, s7, 1
; VI-NEXT: v_alignbit_b32 v0, s7, v0, 1
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_alignbit_b32 v3, s2, v0, v1 ; VI-NEXT: v_alignbit_b32 v3, s2, v0, v1
; VI-NEXT: v_mov_b32_e32 v0, s6 ; VI-NEXT: v_mov_b32_e32 v0, s10
; VI-NEXT: s_not_b32 s3, s14 ; VI-NEXT: s_not_b32 s3, s14
; VI-NEXT: v_alignbit_b32 v0, s10, v0, 1 ; VI-NEXT: v_alignbit_b32 v0, s6, v0, 1
; VI-NEXT: s_lshr_b32 s2, s10, 1 ; VI-NEXT: s_lshr_b32 s2, s6, 1
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_alignbit_b32 v2, s2, v0, v1 ; VI-NEXT: v_alignbit_b32 v2, s2, v0, v1
; VI-NEXT: v_mov_b32_e32 v0, s5 ; VI-NEXT: v_mov_b32_e32 v0, s9
; VI-NEXT: s_not_b32 s3, s13 ; VI-NEXT: s_not_b32 s3, s13
; VI-NEXT: v_alignbit_b32 v0, s9, v0, 1 ; VI-NEXT: v_alignbit_b32 v0, s5, v0, 1
; VI-NEXT: s_lshr_b32 s2, s9, 1 ; VI-NEXT: s_lshr_b32 s2, s5, 1
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_alignbit_b32 v1, s2, v0, v1 ; VI-NEXT: v_alignbit_b32 v1, s2, v0, v1
; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v0, s8
; VI-NEXT: s_not_b32 s3, s12 ; VI-NEXT: s_not_b32 s3, s12
; VI-NEXT: v_alignbit_b32 v0, s8, v0, 1 ; VI-NEXT: v_alignbit_b32 v0, s4, v0, 1
; VI-NEXT: s_lshr_b32 s2, s8, 1 ; VI-NEXT: s_lshr_b32 s2, s4, 1
; VI-NEXT: v_mov_b32_e32 v4, s3 ; VI-NEXT: v_mov_b32_e32 v4, s3
; VI-NEXT: v_alignbit_b32 v0, s2, v0, v4 ; VI-NEXT: v_alignbit_b32 v0, s2, v0, v4
; VI-NEXT: v_mov_b32_e32 v5, s1 ; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v4, s0 ; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] ; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: fshl_v4i32: ; GFX9-LABEL: fshl_v4i32:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x44 ; GFX9-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
; GFX9-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x34
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0x54 ; GFX9-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0x54
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s7
; GFX9-NEXT: v_alignbit_b32 v0, s11, v0, 1
; GFX9-NEXT: s_lshr_b32 s0, s11, 1
; GFX9-NEXT: s_not_b32 s1, s15 ; GFX9-NEXT: s_not_b32 s1, s15
; GFX9-NEXT: v_mov_b32_e32 v0, s11
; GFX9-NEXT: s_lshr_b32 s0, s7, 1
; GFX9-NEXT: v_alignbit_b32 v0, s7, v0, 1
; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_alignbit_b32 v3, s0, v0, v1 ; GFX9-NEXT: v_alignbit_b32 v3, s0, v0, v1
; GFX9-NEXT: v_mov_b32_e32 v0, s6 ; GFX9-NEXT: v_mov_b32_e32 v0, s10
; GFX9-NEXT: s_not_b32 s1, s14 ; GFX9-NEXT: s_not_b32 s1, s14
; GFX9-NEXT: v_alignbit_b32 v0, s10, v0, 1 ; GFX9-NEXT: v_alignbit_b32 v0, s6, v0, 1
; GFX9-NEXT: s_lshr_b32 s0, s10, 1 ; GFX9-NEXT: s_lshr_b32 s0, s6, 1
; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_alignbit_b32 v2, s0, v0, v1 ; GFX9-NEXT: v_alignbit_b32 v2, s0, v0, v1
; GFX9-NEXT: v_mov_b32_e32 v0, s5 ; GFX9-NEXT: v_mov_b32_e32 v0, s9
; GFX9-NEXT: s_not_b32 s1, s13 ; GFX9-NEXT: s_not_b32 s1, s13
; GFX9-NEXT: v_alignbit_b32 v0, s9, v0, 1 ; GFX9-NEXT: v_alignbit_b32 v0, s5, v0, 1
; GFX9-NEXT: s_lshr_b32 s0, s9, 1 ; GFX9-NEXT: s_lshr_b32 s0, s5, 1
; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_alignbit_b32 v1, s0, v0, v1 ; GFX9-NEXT: v_alignbit_b32 v1, s0, v0, v1
; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: v_mov_b32_e32 v0, s8
; GFX9-NEXT: s_not_b32 s1, s12 ; GFX9-NEXT: s_not_b32 s1, s12
; GFX9-NEXT: v_alignbit_b32 v0, s8, v0, 1 ; GFX9-NEXT: v_alignbit_b32 v0, s4, v0, 1
; GFX9-NEXT: s_lshr_b32 s0, s8, 1 ; GFX9-NEXT: s_lshr_b32 s0, s4, 1
; GFX9-NEXT: v_mov_b32_e32 v5, s1 ; GFX9-NEXT: v_mov_b32_e32 v5, s1
; GFX9-NEXT: v_alignbit_b32 v0, s0, v0, v5 ; GFX9-NEXT: v_alignbit_b32 v0, s0, v0, v5
; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3] ; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; R600-LABEL: fshl_v4i32: ; R600-LABEL: fshl_v4i32:
; R600: ; %bb.0: ; %entry ; R600: ; %bb.0: ; %entry
; R600-NEXT: ALU 17, @4, KC0[CB0:0-32], KC1[] ; R600-NEXT: ALU 17, @4, KC0[CB0:0-32], KC1[]
Show All 17 Lines
; R600-NEXT: BIT_ALIGN_INT * T1.W, KC0[3].Y, KC0[4].Y, 1, ; R600-NEXT: BIT_ALIGN_INT * T1.W, KC0[3].Y, KC0[4].Y, 1,
; R600-NEXT: NOT_INT * T2.W, KC0[5].Y, ; R600-NEXT: NOT_INT * T2.W, KC0[5].Y,
; R600-NEXT: BIT_ALIGN_INT T0.X, T1.Z, T1.W, PV.W, ; R600-NEXT: BIT_ALIGN_INT T0.X, T1.Z, T1.W, PV.W,
; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00) ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
; ;
; GFX10-LABEL: fshl_v4i32: ; GFX10-LABEL: fshl_v4i32:
; GFX10: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_clause 0x3 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 ; GFX10-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
; GFX10-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x44
; GFX10-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0x54 ; GFX10-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0x54
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX10-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_lshr_b32 s0, s7, 1
; GFX10-NEXT: v_alignbit_b32 v0, s7, s11, 1 ; GFX10-NEXT: v_alignbit_b32 v0, s7, s11, 1
; GFX10-NEXT: v_alignbit_b32 v1, s6, s10, 1 ; GFX10-NEXT: v_alignbit_b32 v1, s6, s10, 1
; GFX10-NEXT: v_alignbit_b32 v5, s5, s9, 1 ; GFX10-NEXT: v_alignbit_b32 v5, s5, s9, 1
; GFX10-NEXT: v_alignbit_b32 v6, s4, s8, 1 ; GFX10-NEXT: v_alignbit_b32 v6, s4, s8, 1
; GFX10-NEXT: s_not_b32 s1, s15 ; GFX10-NEXT: s_lshr_b32 s2, s7, 1
; GFX10-NEXT: s_not_b32 s3, s15
; GFX10-NEXT: s_lshr_b32 s6, s6, 1 ; GFX10-NEXT: s_lshr_b32 s6, s6, 1
; GFX10-NEXT: s_not_b32 s7, s14 ; GFX10-NEXT: s_not_b32 s7, s14
; GFX10-NEXT: s_lshr_b32 s5, s5, 1 ; GFX10-NEXT: s_lshr_b32 s5, s5, 1
; GFX10-NEXT: s_not_b32 s9, s13 ; GFX10-NEXT: s_not_b32 s9, s13
; GFX10-NEXT: s_lshr_b32 s4, s4, 1 ; GFX10-NEXT: s_lshr_b32 s4, s4, 1
; GFX10-NEXT: s_not_b32 s8, s12 ; GFX10-NEXT: s_not_b32 s8, s12
; GFX10-NEXT: v_alignbit_b32 v3, s0, v0, s1 ; GFX10-NEXT: v_alignbit_b32 v3, s2, v0, s3
; GFX10-NEXT: v_alignbit_b32 v2, s6, v1, s7 ; GFX10-NEXT: v_alignbit_b32 v2, s6, v1, s7
; GFX10-NEXT: v_alignbit_b32 v1, s5, v5, s9 ; GFX10-NEXT: v_alignbit_b32 v1, s5, v5, s9
; GFX10-NEXT: v_alignbit_b32 v0, s4, v6, s8 ; GFX10-NEXT: v_alignbit_b32 v0, s4, v6, s8
; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3] ; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
entry: entry:
%0 = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) %0 = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z)
store <4 x i32> %0, <4 x i32> addrspace(1)* %in store <4 x i32> %0, <4 x i32> addrspace(1)* %in
ret void ret void
} }
define amdgpu_kernel void @fshl_v4i32_imm(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y) { define amdgpu_kernel void @fshl_v4i32_imm(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y) {
; SI-LABEL: fshl_v4i32_imm: ; SI-LABEL: fshl_v4i32_imm:
; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x11 ; SI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd
; SI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s7 ; SI-NEXT: v_mov_b32_e32 v0, s11
; SI-NEXT: v_alignbit_b32 v3, s11, v0, 31 ; SI-NEXT: v_mov_b32_e32 v1, s10
; SI-NEXT: v_mov_b32_e32 v0, s6 ; SI-NEXT: v_alignbit_b32 v3, s7, v0, 31
; SI-NEXT: v_alignbit_b32 v2, s10, v0, 23 ; SI-NEXT: v_mov_b32_e32 v0, s9
; SI-NEXT: v_mov_b32_e32 v0, s5 ; SI-NEXT: v_alignbit_b32 v2, s6, v1, 23
; SI-NEXT: v_alignbit_b32 v1, s9, v0, 25 ; SI-NEXT: v_alignbit_b32 v1, s5, v0, 25
; SI-NEXT: v_mov_b32_e32 v0, s4 ; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_alignbit_b32 v0, s8, v0, 31 ; SI-NEXT: v_alignbit_b32 v0, s4, v0, 31
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: fshl_v4i32_imm: ; VI-LABEL: fshl_v4i32_imm:
; VI: ; %bb.0: ; %entry ; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x44 ; VI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
; VI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x34
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s7 ; VI-NEXT: v_mov_b32_e32 v0, s11
; VI-NEXT: v_mov_b32_e32 v1, s6 ; VI-NEXT: v_mov_b32_e32 v1, s10
; VI-NEXT: v_alignbit_b32 v3, s11, v0, 31 ; VI-NEXT: v_mov_b32_e32 v4, s9
; VI-NEXT: v_mov_b32_e32 v0, s5 ; VI-NEXT: v_alignbit_b32 v3, s7, v0, 31
; VI-NEXT: v_alignbit_b32 v2, s10, v1, 23 ; VI-NEXT: v_alignbit_b32 v2, s6, v1, 23
; VI-NEXT: v_alignbit_b32 v1, s9, v0, 25 ; VI-NEXT: v_alignbit_b32 v1, s5, v4, 25
; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v0, s8
; VI-NEXT: v_mov_b32_e32 v5, s1 ; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_alignbit_b32 v0, s8, v0, 31 ; VI-NEXT: v_alignbit_b32 v0, s4, v0, 31
; VI-NEXT: v_mov_b32_e32 v4, s0 ; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] ; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: fshl_v4i32_imm: ; GFX9-LABEL: fshl_v4i32_imm:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x44 ; GFX9-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
; GFX9-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x34
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s7 ; GFX9-NEXT: v_mov_b32_e32 v0, s11
; GFX9-NEXT: v_mov_b32_e32 v1, s6 ; GFX9-NEXT: v_mov_b32_e32 v1, s10
; GFX9-NEXT: v_alignbit_b32 v3, s11, v0, 31 ; GFX9-NEXT: v_alignbit_b32 v3, s7, v0, 31
; GFX9-NEXT: v_mov_b32_e32 v0, s5 ; GFX9-NEXT: v_mov_b32_e32 v0, s9
; GFX9-NEXT: v_alignbit_b32 v2, s10, v1, 23 ; GFX9-NEXT: v_alignbit_b32 v2, s6, v1, 23
; GFX9-NEXT: v_alignbit_b32 v1, s9, v0, 25 ; GFX9-NEXT: v_alignbit_b32 v1, s5, v0, 25
; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: v_mov_b32_e32 v0, s8
; GFX9-NEXT: v_alignbit_b32 v0, s8, v0, 31 ; GFX9-NEXT: v_alignbit_b32 v0, s4, v0, 31
; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3] ; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; R600-LABEL: fshl_v4i32_imm: ; R600-LABEL: fshl_v4i32_imm:
; R600: ; %bb.0: ; %entry ; R600: ; %bb.0: ; %entry
; R600-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[] ; R600-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; R600-NEXT: ALU clause starting at 4: ; R600-NEXT: ALU clause starting at 4:
; R600-NEXT: BIT_ALIGN_INT * T0.W, KC0[4].X, KC0[5].X, literal.x, ; R600-NEXT: BIT_ALIGN_INT * T0.W, KC0[4].X, KC0[5].X, literal.x,
; R600-NEXT: 31(4.344025e-44), 0(0.000000e+00) ; R600-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; R600-NEXT: BIT_ALIGN_INT * T0.Z, KC0[3].W, KC0[4].W, literal.x, ; R600-NEXT: BIT_ALIGN_INT * T0.Z, KC0[3].W, KC0[4].W, literal.x,
; R600-NEXT: 23(3.222986e-44), 0(0.000000e+00) ; R600-NEXT: 23(3.222986e-44), 0(0.000000e+00)
; R600-NEXT: BIT_ALIGN_INT * T0.Y, KC0[3].Z, KC0[4].Z, literal.x, ; R600-NEXT: BIT_ALIGN_INT * T0.Y, KC0[3].Z, KC0[4].Z, literal.x,
; R600-NEXT: 25(3.503246e-44), 0(0.000000e+00) ; R600-NEXT: 25(3.503246e-44), 0(0.000000e+00)
; R600-NEXT: BIT_ALIGN_INT * T0.X, KC0[3].Y, KC0[4].Y, literal.x, ; R600-NEXT: BIT_ALIGN_INT * T0.X, KC0[3].Y, KC0[4].Y, literal.x,
; R600-NEXT: 31(4.344025e-44), 0(0.000000e+00) ; R600-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00) ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
; ;
; GFX10-LABEL: fshl_v4i32_imm: ; GFX10-LABEL: fshl_v4i32_imm:
; GFX10: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_clause 0x2 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 ; GFX10-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
; GFX10-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x44
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX10-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_alignbit_b32 v3, s7, s11, 31 ; GFX10-NEXT: v_alignbit_b32 v3, s7, s11, 31
; GFX10-NEXT: v_alignbit_b32 v2, s6, s10, 23 ; GFX10-NEXT: v_alignbit_b32 v2, s6, s10, 23
; GFX10-NEXT: v_alignbit_b32 v1, s5, s9, 25 ; GFX10-NEXT: v_alignbit_b32 v1, s5, s9, 25
; GFX10-NEXT: v_alignbit_b32 v0, s4, s8, 31 ; GFX10-NEXT: v_alignbit_b32 v0, s4, s8, 31
; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3] ; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
entry: entry:
%0 = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 1, i32 7, i32 9, i32 33>) %0 = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 1, i32 7, i32 9, i32 33>)
store <4 x i32> %0, <4 x i32> addrspace(1)* %in store <4 x i32> %0, <4 x i32> addrspace(1)* %in
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/fshr.ll

Show First 20 Lines • Show All 150 Lines • ▼ Show 20 Linesentry:
%0 = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 7) %0 = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 7)
store i32 %0, i32 addrspace(1)* %in store i32 %0, i32 addrspace(1)* %in
ret void ret void
} }
define amdgpu_kernel void @fshr_v2i32(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y, <2 x i32> %z) { define amdgpu_kernel void @fshr_v2i32(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y, <2 x i32> %z) {
; SI-LABEL: fshr_v2i32: ; SI-LABEL: fshr_v2i32:
; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xf ; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xf
; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s7, 0xf000 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s3 ; SI-NEXT: v_mov_b32_e32 v0, s7
; SI-NEXT: v_mov_b32_e32 v1, s9 ; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: v_alignbit_b32 v1, s5, v0, v1
; SI-NEXT: v_mov_b32_e32 v0, s6
; SI-NEXT: v_mov_b32_e32 v2, s8 ; SI-NEXT: v_mov_b32_e32 v2, s8
; SI-NEXT: v_alignbit_b32 v1, s1, v0, v1 ; SI-NEXT: v_alignbit_b32 v0, s4, v0, v2
; SI-NEXT: v_mov_b32_e32 v0, s2 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: v_alignbit_b32 v0, s0, v0, v2
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: fshr_v2i32: ; VI-LABEL: fshr_v2i32:
; VI: ; %bb.0: ; %entry ; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x3c ; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x3c
; VI-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x2c
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s3 ; VI-NEXT: v_mov_b32_e32 v0, s7
; VI-NEXT: v_mov_b32_e32 v1, s5 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_alignbit_b32 v1, s7, v0, v1 ; VI-NEXT: v_mov_b32_e32 v2, s6
; VI-NEXT: v_alignbit_b32 v1, s5, v0, v1
; VI-NEXT: v_mov_b32_e32 v0, s2 ; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v2, s4 ; VI-NEXT: v_alignbit_b32 v0, s4, v2, v0
; VI-NEXT: v_alignbit_b32 v0, s6, v0, v2
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0 ; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: fshr_v2i32: ; GFX9-LABEL: fshr_v2i32:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x3c ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x3c
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x2c
; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x24
; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s3 ; GFX9-NEXT: v_mov_b32_e32 v0, s7
; GFX9-NEXT: v_mov_b32_e32 v1, s5 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: v_alignbit_b32 v1, s7, v0, v1 ; GFX9-NEXT: v_alignbit_b32 v1, s5, v0, v1
; GFX9-NEXT: v_mov_b32_e32 v0, s2 ; GFX9-NEXT: v_mov_b32_e32 v0, s6
; GFX9-NEXT: v_mov_b32_e32 v3, s4 ; GFX9-NEXT: v_mov_b32_e32 v3, s2
; GFX9-NEXT: v_alignbit_b32 v0, s6, v0, v3 ; GFX9-NEXT: v_alignbit_b32 v0, s4, v0, v3
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9] ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; R600-LABEL: fshr_v2i32: ; R600-LABEL: fshr_v2i32:
; R600: ; %bb.0: ; %entry ; R600: ; %bb.0: ; %entry
; R600-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[] ; R600-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; R600-NEXT: ALU clause starting at 4: ; R600-NEXT: ALU clause starting at 4:
; R600-NEXT: MOV * T0.W, KC0[4].X, ; R600-NEXT: MOV * T0.W, KC0[4].X,
; R600-NEXT: BIT_ALIGN_INT T0.Y, KC0[3].X, KC0[3].Z, PV.W, ; R600-NEXT: BIT_ALIGN_INT T0.Y, KC0[3].X, KC0[3].Z, PV.W,
; R600-NEXT: MOV * T0.W, KC0[3].W, ; R600-NEXT: MOV * T0.W, KC0[3].W,
; R600-NEXT: BIT_ALIGN_INT * T0.X, KC0[2].W, KC0[3].Y, PV.W, ; R600-NEXT: BIT_ALIGN_INT * T0.X, KC0[2].W, KC0[3].Y, PV.W,
; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00) ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
; ;
; GFX10-LABEL: fshr_v2i32: ; GFX10-LABEL: fshr_v2i32:
; GFX10: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_clause 0x3 ; GFX10-NEXT: s_clause 0x2
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x3c ; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x3c
; GFX10-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
; GFX10-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x34
; GFX10-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x24
; GFX10-NEXT: v_mov_b32_e32 v3, 0 ; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s3 ; GFX10-NEXT: v_mov_b32_e32 v0, s3
; GFX10-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-NEXT: v_mov_b32_e32 v2, s2
; GFX10-NEXT: v_alignbit_b32 v1, s5, s7, v0 ; GFX10-NEXT: v_alignbit_b32 v1, s5, s7, v0
; GFX10-NEXT: v_alignbit_b32 v0, s4, s6, v2 ; GFX10-NEXT: v_alignbit_b32 v0, s4, s6, v2
; GFX10-NEXT: global_store_dwordx2 v3, v[0:1], s[8:9] ; GFX10-NEXT: global_store_dwordx2 v3, v[0:1], s[8:9]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
entry: entry:
%0 = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z) %0 = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z)
store <2 x i32> %0, <2 x i32> addrspace(1)* %in store <2 x i32> %0, <2 x i32> addrspace(1)* %in
ret void ret void
} }
define amdgpu_kernel void @fshr_v2i32_imm(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y) { define amdgpu_kernel void @fshr_v2i32_imm(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y) {
; SI-LABEL: fshr_v2i32_imm: ; SI-LABEL: fshr_v2i32_imm:
; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
; SI-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0xb
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s5 ; SI-NEXT: v_mov_b32_e32 v0, s7
; SI-NEXT: v_alignbit_b32 v1, s7, v0, 9 ; SI-NEXT: v_mov_b32_e32 v2, s6
; SI-NEXT: v_mov_b32_e32 v0, s4 ; SI-NEXT: v_alignbit_b32 v1, s5, v0, 9
; SI-NEXT: v_alignbit_b32 v0, s6, v0, 7 ; SI-NEXT: v_alignbit_b32 v0, s4, v2, 7
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: fshr_v2i32_imm: ; VI-LABEL: fshr_v2i32_imm:
; VI: ; %bb.0: ; %entry ; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s3 ; VI-NEXT: v_mov_b32_e32 v0, s7
; VI-NEXT: v_mov_b32_e32 v2, s2 ; VI-NEXT: v_mov_b32_e32 v2, s6
; VI-NEXT: v_alignbit_b32 v1, s5, v0, 9 ; VI-NEXT: v_alignbit_b32 v1, s5, v0, 9
; VI-NEXT: v_alignbit_b32 v0, s4, v2, 7 ; VI-NEXT: v_alignbit_b32 v0, s4, v2, 7
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0 ; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: fshr_v2i32_imm: ; GFX9-LABEL: fshr_v2i32_imm:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x24
; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s3 ; GFX9-NEXT: v_mov_b32_e32 v0, s7
; GFX9-NEXT: v_mov_b32_e32 v3, s2 ; GFX9-NEXT: v_mov_b32_e32 v3, s6
; GFX9-NEXT: v_alignbit_b32 v1, s5, v0, 9 ; GFX9-NEXT: v_alignbit_b32 v1, s5, v0, 9
; GFX9-NEXT: v_alignbit_b32 v0, s4, v3, 7 ; GFX9-NEXT: v_alignbit_b32 v0, s4, v3, 7
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7] ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; R600-LABEL: fshr_v2i32_imm: ; R600-LABEL: fshr_v2i32_imm:
; R600: ; %bb.0: ; %entry ; R600: ; %bb.0: ; %entry
; R600-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[] ; R600-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; R600-NEXT: ALU clause starting at 4: ; R600-NEXT: ALU clause starting at 4:
; R600-NEXT: BIT_ALIGN_INT * T0.Y, KC0[3].X, KC0[3].Z, literal.x, ; R600-NEXT: BIT_ALIGN_INT * T0.Y, KC0[3].X, KC0[3].Z, literal.x,
; R600-NEXT: 9(1.261169e-44), 0(0.000000e+00) ; R600-NEXT: 9(1.261169e-44), 0(0.000000e+00)
; R600-NEXT: BIT_ALIGN_INT * T0.X, KC0[2].W, KC0[3].Y, literal.x, ; R600-NEXT: BIT_ALIGN_INT * T0.X, KC0[2].W, KC0[3].Y, literal.x,
; R600-NEXT: 7(9.809089e-45), 0(0.000000e+00) ; R600-NEXT: 7(9.809089e-45), 0(0.000000e+00)
; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00) ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
; ;
; GFX10-LABEL: fshr_v2i32_imm: ; GFX10-LABEL: fshr_v2i32_imm:
; GFX10: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_clause 0x2 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
; GFX10-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34 ; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX10-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x24
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_alignbit_b32 v1, s3, s5, 9 ; GFX10-NEXT: v_alignbit_b32 v1, s5, s7, 9
; GFX10-NEXT: v_alignbit_b32 v0, s2, s4, 7 ; GFX10-NEXT: v_alignbit_b32 v0, s4, s6, 7
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7] ; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
entry: entry:
%0 = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> <i32 7, i32 9>) %0 = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> <i32 7, i32 9>)
store <2 x i32> %0, <2 x i32> addrspace(1)* %in store <2 x i32> %0, <2 x i32> addrspace(1)* %in
ret void ret void
} }
define amdgpu_kernel void @fshr_v4i32(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y, <4 x i32> %z) { define amdgpu_kernel void @fshr_v4i32(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {
; SI-LABEL: fshr_v4i32: ; SI-LABEL: fshr_v4i32:
; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x11 ; SI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd
; SI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x15 ; SI-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0x15
; SI-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s15, 0xf000 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s7 ; SI-NEXT: v_mov_b32_e32 v0, s11
; SI-NEXT: v_mov_b32_e32 v1, s11 ; SI-NEXT: v_mov_b32_e32 v1, s15
; SI-NEXT: v_mov_b32_e32 v4, s8 ; SI-NEXT: v_alignbit_b32 v3, s7, v0, v1
; SI-NEXT: v_alignbit_b32 v3, s3, v0, v1 ; SI-NEXT: v_mov_b32_e32 v0, s10
; SI-NEXT: v_mov_b32_e32 v0, s6 ; SI-NEXT: v_mov_b32_e32 v1, s14
; SI-NEXT: v_mov_b32_e32 v1, s10 ; SI-NEXT: v_alignbit_b32 v2, s6, v0, v1
; SI-NEXT: v_alignbit_b32 v2, s2, v0, v1 ; SI-NEXT: v_mov_b32_e32 v0, s9
; SI-NEXT: v_mov_b32_e32 v0, s5 ; SI-NEXT: v_mov_b32_e32 v1, s13
; SI-NEXT: v_mov_b32_e32 v1, s9 ; SI-NEXT: v_alignbit_b32 v1, s5, v0, v1
; SI-NEXT: v_alignbit_b32 v1, s1, v0, v1 ; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v0, s4 ; SI-NEXT: v_mov_b32_e32 v4, s12
; SI-NEXT: s_mov_b32 s14, -1 ; SI-NEXT: v_alignbit_b32 v0, s4, v0, v4
; SI-NEXT: v_alignbit_b32 v0, s0, v0, v4 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: fshr_v4i32: ; VI-LABEL: fshr_v4i32:
; VI: ; %bb.0: ; %entry ; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x44 ; VI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
; VI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x54 ; VI-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0x54
; VI-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0x34
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s7 ; VI-NEXT: v_mov_b32_e32 v0, s11
; VI-NEXT: v_mov_b32_e32 v1, s11 ; VI-NEXT: v_mov_b32_e32 v1, s15
; VI-NEXT: v_alignbit_b32 v3, s15, v0, v1 ; VI-NEXT: v_mov_b32_e32 v2, s10
; VI-NEXT: v_mov_b32_e32 v0, s6 ; VI-NEXT: v_alignbit_b32 v3, s7, v0, v1
; VI-NEXT: v_mov_b32_e32 v1, s10 ; VI-NEXT: v_mov_b32_e32 v0, s14
; VI-NEXT: v_alignbit_b32 v2, s14, v0, v1 ; VI-NEXT: v_alignbit_b32 v2, s6, v2, v0
; VI-NEXT: v_mov_b32_e32 v0, s5 ; VI-NEXT: v_mov_b32_e32 v0, s9
; VI-NEXT: v_mov_b32_e32 v1, s9 ; VI-NEXT: v_mov_b32_e32 v1, s13
; VI-NEXT: v_alignbit_b32 v1, s13, v0, v1 ; VI-NEXT: v_alignbit_b32 v1, s5, v0, v1
; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v0, s8
; VI-NEXT: v_mov_b32_e32 v4, s8 ; VI-NEXT: v_mov_b32_e32 v4, s12
; VI-NEXT: v_alignbit_b32 v0, s12, v0, v4 ; VI-NEXT: v_alignbit_b32 v0, s4, v0, v4
; VI-NEXT: v_mov_b32_e32 v5, s1 ; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v4, s0 ; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] ; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: fshr_v4i32: ; GFX9-LABEL: fshr_v4i32:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x44 ; GFX9-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
; GFX9-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x54 ; GFX9-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0x54
; GFX9-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0x34
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s7 ; GFX9-NEXT: v_mov_b32_e32 v0, s11
; GFX9-NEXT: v_mov_b32_e32 v1, s11 ; GFX9-NEXT: v_mov_b32_e32 v1, s15
; GFX9-NEXT: v_alignbit_b32 v3, s15, v0, v1 ; GFX9-NEXT: v_alignbit_b32 v3, s7, v0, v1
; GFX9-NEXT: v_mov_b32_e32 v0, s6 ; GFX9-NEXT: v_mov_b32_e32 v0, s10
; GFX9-NEXT: v_mov_b32_e32 v1, s10 ; GFX9-NEXT: v_mov_b32_e32 v1, s14
; GFX9-NEXT: v_alignbit_b32 v2, s14, v0, v1 ; GFX9-NEXT: v_alignbit_b32 v2, s6, v0, v1
; GFX9-NEXT: v_mov_b32_e32 v0, s5 ; GFX9-NEXT: v_mov_b32_e32 v0, s9
; GFX9-NEXT: v_mov_b32_e32 v1, s9 ; GFX9-NEXT: v_mov_b32_e32 v1, s13
; GFX9-NEXT: v_alignbit_b32 v1, s13, v0, v1 ; GFX9-NEXT: v_alignbit_b32 v1, s5, v0, v1
; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: v_mov_b32_e32 v0, s8
; GFX9-NEXT: v_mov_b32_e32 v5, s8 ; GFX9-NEXT: v_mov_b32_e32 v5, s12
; GFX9-NEXT: v_alignbit_b32 v0, s12, v0, v5 ; GFX9-NEXT: v_alignbit_b32 v0, s4, v0, v5
; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3] ; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; R600-LABEL: fshr_v4i32: ; R600-LABEL: fshr_v4i32:
; R600: ; %bb.0: ; %entry ; R600: ; %bb.0: ; %entry
; R600-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[] ; R600-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; R600-NEXT: ALU clause starting at 4: ; R600-NEXT: ALU clause starting at 4:
; R600-NEXT: MOV * T0.W, KC0[6].X, ; R600-NEXT: MOV * T0.W, KC0[6].X,
; R600-NEXT: BIT_ALIGN_INT * T0.W, KC0[4].X, KC0[5].X, PV.W, ; R600-NEXT: BIT_ALIGN_INT * T0.W, KC0[4].X, KC0[5].X, PV.W,
; R600-NEXT: MOV * T1.W, KC0[5].W, ; R600-NEXT: MOV * T1.W, KC0[5].W,
; R600-NEXT: BIT_ALIGN_INT * T0.Z, KC0[3].W, KC0[4].W, PV.W, ; R600-NEXT: BIT_ALIGN_INT * T0.Z, KC0[3].W, KC0[4].W, PV.W,
; R600-NEXT: MOV * T1.W, KC0[5].Z, ; R600-NEXT: MOV * T1.W, KC0[5].Z,
; R600-NEXT: BIT_ALIGN_INT * T0.Y, KC0[3].Z, KC0[4].Z, PV.W, ; R600-NEXT: BIT_ALIGN_INT * T0.Y, KC0[3].Z, KC0[4].Z, PV.W,
; R600-NEXT: MOV * T1.W, KC0[5].Y, ; R600-NEXT: MOV * T1.W, KC0[5].Y,
; R600-NEXT: BIT_ALIGN_INT * T0.X, KC0[3].Y, KC0[4].Y, PV.W, ; R600-NEXT: BIT_ALIGN_INT * T0.X, KC0[3].Y, KC0[4].Y, PV.W,
; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00) ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
; ;
; GFX10-LABEL: fshr_v4i32: ; GFX10-LABEL: fshr_v4i32:
; GFX10: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_clause 0x3 ; GFX10-NEXT: s_clause 0x2
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x54 ; GFX10-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0x54
; GFX10-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x44 ; GFX10-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
; GFX10-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0x34
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX10-NEXT: v_mov_b32_e32 v6, 0 ; GFX10-NEXT: v_mov_b32_e32 v6, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s7 ; GFX10-NEXT: v_mov_b32_e32 v0, s15
; GFX10-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-NEXT: v_mov_b32_e32 v1, s14
; GFX10-NEXT: v_mov_b32_e32 v4, s5 ; GFX10-NEXT: v_mov_b32_e32 v4, s13
; GFX10-NEXT: v_mov_b32_e32 v5, s4 ; GFX10-NEXT: v_mov_b32_e32 v5, s12
; GFX10-NEXT: v_alignbit_b32 v3, s15, s11, v0 ; GFX10-NEXT: v_alignbit_b32 v3, s7, s11, v0
; GFX10-NEXT: v_alignbit_b32 v2, s14, s10, v1 ; GFX10-NEXT: v_alignbit_b32 v2, s6, s10, v1
; GFX10-NEXT: v_alignbit_b32 v1, s13, s9, v4 ; GFX10-NEXT: v_alignbit_b32 v1, s5, s9, v4
; GFX10-NEXT: v_alignbit_b32 v0, s12, s8, v5 ; GFX10-NEXT: v_alignbit_b32 v0, s4, s8, v5
; GFX10-NEXT: global_store_dwordx4 v6, v[0:3], s[2:3] ; GFX10-NEXT: global_store_dwordx4 v6, v[0:3], s[2:3]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
entry: entry:
%0 = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) %0 = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z)
store <4 x i32> %0, <4 x i32> addrspace(1)* %in store <4 x i32> %0, <4 x i32> addrspace(1)* %in
ret void ret void
} }
define amdgpu_kernel void @fshr_v4i32_imm(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y) { define amdgpu_kernel void @fshr_v4i32_imm(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y) {
; SI-LABEL: fshr_v4i32_imm: ; SI-LABEL: fshr_v4i32_imm:
; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x11 ; SI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd
; SI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s7 ; SI-NEXT: v_mov_b32_e32 v0, s11
; SI-NEXT: v_alignbit_b32 v3, s11, v0, 1 ; SI-NEXT: v_mov_b32_e32 v1, s10
; SI-NEXT: v_mov_b32_e32 v0, s6 ; SI-NEXT: v_alignbit_b32 v3, s7, v0, 1
; SI-NEXT: v_alignbit_b32 v2, s10, v0, 9 ; SI-NEXT: v_mov_b32_e32 v0, s9
; SI-NEXT: v_mov_b32_e32 v0, s5 ; SI-NEXT: v_alignbit_b32 v2, s6, v1, 9
; SI-NEXT: v_alignbit_b32 v1, s9, v0, 7 ; SI-NEXT: v_alignbit_b32 v1, s5, v0, 7
; SI-NEXT: v_mov_b32_e32 v0, s4 ; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_alignbit_b32 v0, s8, v0, 1 ; SI-NEXT: v_alignbit_b32 v0, s4, v0, 1
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: fshr_v4i32_imm: ; VI-LABEL: fshr_v4i32_imm:
; VI: ; %bb.0: ; %entry ; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x44 ; VI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
; VI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x34
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s7 ; VI-NEXT: v_mov_b32_e32 v0, s11
; VI-NEXT: v_mov_b32_e32 v1, s6 ; VI-NEXT: v_mov_b32_e32 v1, s10
; VI-NEXT: v_alignbit_b32 v3, s11, v0, 1 ; VI-NEXT: v_mov_b32_e32 v4, s9
; VI-NEXT: v_mov_b32_e32 v0, s5 ; VI-NEXT: v_alignbit_b32 v3, s7, v0, 1
; VI-NEXT: v_alignbit_b32 v2, s10, v1, 9 ; VI-NEXT: v_alignbit_b32 v2, s6, v1, 9
; VI-NEXT: v_alignbit_b32 v1, s9, v0, 7 ; VI-NEXT: v_alignbit_b32 v1, s5, v4, 7
; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v0, s8
; VI-NEXT: v_mov_b32_e32 v5, s1 ; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_alignbit_b32 v0, s8, v0, 1 ; VI-NEXT: v_alignbit_b32 v0, s4, v0, 1
; VI-NEXT: v_mov_b32_e32 v4, s0 ; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] ; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: fshr_v4i32_imm: ; GFX9-LABEL: fshr_v4i32_imm:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x44 ; GFX9-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
; GFX9-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x34
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s7 ; GFX9-NEXT: v_mov_b32_e32 v0, s11
; GFX9-NEXT: v_mov_b32_e32 v1, s6 ; GFX9-NEXT: v_mov_b32_e32 v1, s10
; GFX9-NEXT: v_alignbit_b32 v3, s11, v0, 1 ; GFX9-NEXT: v_alignbit_b32 v3, s7, v0, 1
; GFX9-NEXT: v_mov_b32_e32 v0, s5 ; GFX9-NEXT: v_mov_b32_e32 v0, s9
; GFX9-NEXT: v_alignbit_b32 v2, s10, v1, 9 ; GFX9-NEXT: v_alignbit_b32 v2, s6, v1, 9
; GFX9-NEXT: v_alignbit_b32 v1, s9, v0, 7 ; GFX9-NEXT: v_alignbit_b32 v1, s5, v0, 7
; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: v_mov_b32_e32 v0, s8
; GFX9-NEXT: v_alignbit_b32 v0, s8, v0, 1 ; GFX9-NEXT: v_alignbit_b32 v0, s4, v0, 1
; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3] ; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; R600-LABEL: fshr_v4i32_imm: ; R600-LABEL: fshr_v4i32_imm:
; R600: ; %bb.0: ; %entry ; R600: ; %bb.0: ; %entry
; R600-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[] ; R600-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; R600-NEXT: ALU clause starting at 4: ; R600-NEXT: ALU clause starting at 4:
; R600-NEXT: BIT_ALIGN_INT * T0.W, KC0[4].X, KC0[5].X, 1, ; R600-NEXT: BIT_ALIGN_INT * T0.W, KC0[4].X, KC0[5].X, 1,
; R600-NEXT: BIT_ALIGN_INT * T0.Z, KC0[3].W, KC0[4].W, literal.x, ; R600-NEXT: BIT_ALIGN_INT * T0.Z, KC0[3].W, KC0[4].W, literal.x,
; R600-NEXT: 9(1.261169e-44), 0(0.000000e+00) ; R600-NEXT: 9(1.261169e-44), 0(0.000000e+00)
; R600-NEXT: BIT_ALIGN_INT * T0.Y, KC0[3].Z, KC0[4].Z, literal.x, ; R600-NEXT: BIT_ALIGN_INT * T0.Y, KC0[3].Z, KC0[4].Z, literal.x,
; R600-NEXT: 7(9.809089e-45), 0(0.000000e+00) ; R600-NEXT: 7(9.809089e-45), 0(0.000000e+00)
; R600-NEXT: BIT_ALIGN_INT * T0.X, KC0[3].Y, KC0[4].Y, 1, ; R600-NEXT: BIT_ALIGN_INT * T0.X, KC0[3].Y, KC0[4].Y, 1,
; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00) ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
; ;
; GFX10-LABEL: fshr_v4i32_imm: ; GFX10-LABEL: fshr_v4i32_imm:
; GFX10: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_clause 0x2 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 ; GFX10-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
; GFX10-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x44
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX10-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_alignbit_b32 v3, s7, s11, 1 ; GFX10-NEXT: v_alignbit_b32 v3, s7, s11, 1
; GFX10-NEXT: v_alignbit_b32 v2, s6, s10, 9 ; GFX10-NEXT: v_alignbit_b32 v2, s6, s10, 9
; GFX10-NEXT: v_alignbit_b32 v1, s5, s9, 7 ; GFX10-NEXT: v_alignbit_b32 v1, s5, s9, 7
; GFX10-NEXT: v_alignbit_b32 v0, s4, s8, 1 ; GFX10-NEXT: v_alignbit_b32 v0, s4, s8, 1
; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3] ; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]
▲ Show 20 Lines • Show All 743 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/half.ll

Show First 20 Lines • Show All 1,891 Lines • ▼ Show 20 Lines; VI-NEXT: s_endpgm
%add = fadd half %a, %b %add = fadd half %a, %b
store half %add, half addrspace(1)* %out, align 4 store half %add, half addrspace(1)* %out, align 4
ret void ret void
} }
define amdgpu_kernel void @fadd_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %a, <2 x half> %b) #0 { define amdgpu_kernel void @fadd_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %a, <2 x half> %b) #0 {
; SI-LABEL: fadd_v2f16: ; SI-LABEL: fadd_v2f16:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dword s0, s[4:5], 0x2 ; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2
; SI-NEXT: s_load_dword s1, s[4:5], 0x3
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_lshr_b32 s2, s0, 16 ; SI-NEXT: s_lshr_b32 s2, s0, 16
; SI-NEXT: v_cvt_f32_f16_e32 v0, s0 ; SI-NEXT: v_cvt_f32_f16_e32 v0, s0
; SI-NEXT: s_lshr_b32 s0, s1, 16 ; SI-NEXT: s_lshr_b32 s0, s1, 16
; SI-NEXT: v_cvt_f32_f16_e32 v1, s1 ; SI-NEXT: v_cvt_f32_f16_e32 v1, s1
; SI-NEXT: v_cvt_f32_f16_e32 v2, s2 ; SI-NEXT: v_cvt_f32_f16_e32 v2, s2
; SI-NEXT: v_cvt_f32_f16_e32 v3, s0 ; SI-NEXT: v_cvt_f32_f16_e32 v3, s0
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; SI-NEXT: v_add_f32_e32 v0, v0, v1 ; SI-NEXT: v_add_f32_e32 v0, v0, v1
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0 ; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: v_add_f32_e32 v1, v2, v3 ; SI-NEXT: v_add_f32_e32 v1, v2, v3
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 ; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v2, v0, v1 ; SI-NEXT: v_or_b32_e32 v2, v0, v1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s0 ; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: v_mov_b32_e32 v1, s1 ; SI-NEXT: v_mov_b32_e32 v1, s1
; SI-NEXT: flat_store_dword v[0:1], v2 ; SI-NEXT: flat_store_dword v[0:1], v2
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: fadd_v2f16: ; VI-LABEL: fadd_v2f16:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dword s2, s[4:5], 0xc ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
; VI-NEXT: s_load_dword s3, s[4:5], 0x8 ; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x0
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_lshr_b32 s4, s2, 16 ; VI-NEXT: s_lshr_b32 s4, s1, 16
; VI-NEXT: s_lshr_b32 s5, s3, 16 ; VI-NEXT: s_lshr_b32 s5, s0, 16
; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v0, s1
; VI-NEXT: v_mov_b32_e32 v1, s5 ; VI-NEXT: v_mov_b32_e32 v1, s4
; VI-NEXT: v_add_f16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI-NEXT: v_mov_b32_e32 v2, s5
; VI-NEXT: v_mov_b32_e32 v1, s2 ; VI-NEXT: v_add_f16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v1, s3, v1 ; VI-NEXT: v_add_f16_e32 v0, s0, v0
; VI-NEXT: v_or_b32_e32 v2, v1, v0 ; VI-NEXT: v_or_b32_e32 v2, v0, v1
; VI-NEXT: v_mov_b32_e32 v0, s0 ; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s1 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: flat_store_dword v[0:1], v2 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%add = fadd <2 x half> %a, %b %add = fadd <2 x half> %a, %b
store <2 x half> %add, <2 x half> addrspace(1)* %out, align 8 store <2 x half> %add, <2 x half> addrspace(1)* %out, align 8
ret void ret void
} }
define amdgpu_kernel void @fadd_v4f16(<4 x half> addrspace(1)* %out, <4 x half> addrspace(1)* %in) #0 { define amdgpu_kernel void @fadd_v4f16(<4 x half> addrspace(1)* %out, <4 x half> addrspace(1)* %in) #0 {
; SI-LABEL: fadd_v4f16: ; SI-LABEL: fadd_v4f16:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s2 ; SI-NEXT: v_mov_b32_e32 v0, s2
; SI-NEXT: v_mov_b32_e32 v1, s3 ; SI-NEXT: v_mov_b32_e32 v1, s3
; SI-NEXT: s_add_u32 s2, s2, 8 ; SI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; SI-NEXT: s_addc_u32 s3, s3, 0
; SI-NEXT: v_mov_b32_e32 v2, s2
; SI-NEXT: v_mov_b32_e32 v3, s3
; SI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; SI-NEXT: flat_load_dwordx2 v[2:3], v[2:3]
; SI-NEXT: v_mov_b32_e32 v4, s0 ; SI-NEXT: v_mov_b32_e32 v4, s0
; SI-NEXT: v_mov_b32_e32 v5, s1 ; SI-NEXT: v_mov_b32_e32 v5, s1
; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v6, v0 ; SI-NEXT: v_cvt_f32_f16_e32 v6, v0
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; SI-NEXT: v_cvt_f32_f16_e32 v7, v1 ; SI-NEXT: v_cvt_f32_f16_e32 v7, v1
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v8, v2 ; SI-NEXT: v_cvt_f32_f16_e32 v8, v2
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 ; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; SI-NEXT: v_cvt_f32_f16_e32 v9, v3 ; SI-NEXT: v_cvt_f32_f16_e32 v9, v3
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3 ; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0 ; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1 ; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: v_cvt_f32_f16_e32 v3, v3 ; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 ; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
Show All 11 Lines
; SI-NEXT: v_or_b32_e32 v0, v3, v0 ; SI-NEXT: v_or_b32_e32 v0, v3, v0
; SI-NEXT: flat_store_dwordx2 v[4:5], v[0:1] ; SI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: fadd_v4f16: ; VI-LABEL: fadd_v4f16:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_add_u32 s4, s2, 8
; VI-NEXT: v_mov_b32_e32 v0, s2 ; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: s_addc_u32 s5, s3, 0
; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_mov_b32_e32 v3, s5 ; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; VI-NEXT: flat_load_dwordx2 v[2:3], v[2:3]
; VI-NEXT: v_mov_b32_e32 v4, s0 ; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: v_mov_b32_e32 v5, s1 ; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_add_f16_sdwa v6, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-NEXT: v_add_f16_sdwa v6, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-NEXT: v_add_f16_e32 v1, v1, v3 ; VI-NEXT: v_add_f16_e32 v1, v1, v3
; VI-NEXT: v_add_f16_sdwa v3, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-NEXT: v_add_f16_sdwa v3, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-NEXT: v_add_f16_e32 v0, v0, v2 ; VI-NEXT: v_add_f16_e32 v0, v0, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v6 ; VI-NEXT: v_or_b32_e32 v1, v1, v6
▲ Show 20 Lines • Show All 157 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll

Show First 20 Lines • Show All 180 Lines • ▼ Show 20 Linesbb:
%c.2 = load <4 x half>, <4 x half> addrspace(1)* %c2p %c.2 = load <4 x half>, <4 x half> addrspace(1)* %c2p
%mai.1 = tail call <16 x float> @llvm.amdgcn.mfma.f32.16x16x4f16(<4 x half> %c.1, <4 x half> %c.2, <16 x float> %in.1, i32 1, i32 2, i32 3) %mai.1 = tail call <16 x float> @llvm.amdgcn.mfma.f32.16x16x4f16(<4 x half> %c.1, <4 x half> %c.2, <16 x float> %in.1, i32 1, i32 2, i32 3)
store <16 x float> %mai.1, <16 x float> addrspace(1)* %arg store <16 x float> %mai.1, <16 x float> addrspace(1)* %arg
ret void ret void
} }
; GCN-LABEL: {{^}}test_mfma_f32_4x4x4f16: ; GCN-LABEL: {{^}}test_mfma_f32_4x4x4f16:
; GCN: s_load_dwordx4 ; GCN: s_load_dwordx4
; GCN: s_load_dwordx2 ; GCN: s_load_dwordx4
; GCN: s_load_dwordx2
; GFX908_A-COUNT-4: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}} ; GFX908_A-COUNT-4: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
; GFX908_A: v_mfma_f32_4x4x4f16 [[RES:a\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3 ; GFX908_A: v_mfma_f32_4x4x4f16 [[RES:a\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
; GFX908-COUNT-4: v_accvgpr_read_b32 ; GFX908-COUNT-4: v_accvgpr_read_b32
; GFX908: global_store_dwordx4 ; GFX908: global_store_dwordx4
; GFX90A-NOT: v_accvgpr_read_b32 ; GFX90A-NOT: v_accvgpr_read_b32
; GFX90A: global_store_dwordx4 {{v[0-9]+}}, [[RES]], ; GFX90A: global_store_dwordx4 {{v[0-9]+}}, [[RES]],
define amdgpu_kernel void @test_mfma_f32_4x4x4f16(<4 x float> addrspace(1)* %arg, <4 x half> addrspace(1)* %c) { define amdgpu_kernel void @test_mfma_f32_4x4x4f16(<4 x float> addrspace(1)* %arg, <4 x half> addrspace(1)* %c) {
bb: bb:
▲ Show 20 Lines • Show All 426 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX9 %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX9 %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=VI %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=VI %s
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=CI %s ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=CI %s
; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX10 %s ; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX10 %s
define amdgpu_kernel void @s_lshr_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %lhs, <2 x i16> %rhs) #0 { define amdgpu_kernel void @s_lshr_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %lhs, <2 x i16> %rhs) #0 {
; GFX9-LABEL: s_lshr_v2i16: ; GFX9-LABEL: s_lshr_v2i16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
; GFX9-NEXT: s_load_dword s5, s[0:1], 0x30 ; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, s4 ; GFX9-NEXT: v_mov_b32_e32 v1, s2
; GFX9-NEXT: v_pk_lshrrev_b16 v1, s5, v1 ; GFX9-NEXT: v_pk_lshrrev_b16 v1, s3, v1
; GFX9-NEXT: global_store_dword v0, v1, s[2:3] ; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: s_lshr_v2i16: ; VI-LABEL: s_lshr_v2i16:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dword s2, s[0:1], 0x2c ; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
; VI-NEXT: s_load_dword s3, s[0:1], 0x30
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_and_b32 s4, s2, 0xffff ; VI-NEXT: s_and_b32 s4, s2, 0xffff
; VI-NEXT: s_lshr_b32 s2, s2, 16 ; VI-NEXT: s_lshr_b32 s2, s2, 16
; VI-NEXT: s_lshr_b32 s5, s3, 16 ; VI-NEXT: s_lshr_b32 s5, s3, 16
; VI-NEXT: s_lshr_b32 s2, s2, s5 ; VI-NEXT: s_lshr_b32 s2, s2, s5
; VI-NEXT: s_lshr_b32 s3, s4, s3 ; VI-NEXT: s_lshr_b32 s3, s4, s3
; VI-NEXT: s_lshl_b32 s2, s2, 16 ; VI-NEXT: s_lshl_b32 s2, s2, 16
; VI-NEXT: s_or_b32 s2, s3, s2 ; VI-NEXT: s_or_b32 s2, s3, s2
; VI-NEXT: v_mov_b32_e32 v0, s0 ; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v2, s2 ; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: flat_store_dword v[0:1], v2 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; CI-LABEL: s_lshr_v2i16: ; CI-LABEL: s_lshr_v2i16:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dword s2, s[0:1], 0xb ; CI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb
; CI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; CI-NEXT: s_load_dword s0, s[0:1], 0xc ; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s7, 0xf000 ; CI-NEXT: s_mov_b32 s2, -1
; CI-NEXT: s_mov_b32 s6, -1
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_and_b32 s1, s2, 0xffff ; CI-NEXT: s_and_b32 s6, s4, 0xffff
; CI-NEXT: s_lshr_b32 s2, s2, 16 ; CI-NEXT: s_lshr_b32 s4, s4, 16
; CI-NEXT: s_lshr_b32 s3, s0, 16 ; CI-NEXT: s_lshr_b32 s7, s5, 16
; CI-NEXT: s_lshr_b32 s2, s2, s3 ; CI-NEXT: s_lshr_b32 s4, s4, s7
; CI-NEXT: s_lshl_b32 s2, s2, 16 ; CI-NEXT: s_lshl_b32 s4, s4, 16
; CI-NEXT: s_lshr_b32 s0, s1, s0 ; CI-NEXT: s_lshr_b32 s5, s6, s5
; CI-NEXT: s_or_b32 s0, s0, s2 ; CI-NEXT: s_or_b32 s4, s5, s4
; CI-NEXT: v_mov_b32_e32 v0, s0 ; CI-NEXT: v_mov_b32_e32 v0, s4
; CI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; GFX10-LABEL: s_lshr_v2i16: ; GFX10-LABEL: s_lshr_v2i16:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_clause 0x2 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c ; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
; GFX10-NEXT: s_load_dword s5, s[0:1], 0x30 ; GFX10-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_pk_lshrrev_b16 v1, s5, s4 ; GFX10-NEXT: v_pk_lshrrev_b16 v1, s3, s2
; GFX10-NEXT: global_store_dword v0, v1, s[2:3] ; GFX10-NEXT: global_store_dword v0, v1, s[4:5]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%result = lshr <2 x i16> %lhs, %rhs %result = lshr <2 x i16> %lhs, %rhs
store <2 x i16> %result, <2 x i16> addrspace(1)* %out store <2 x i16> %result, <2 x i16> addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @v_lshr_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { define amdgpu_kernel void @v_lshr_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 {
; GFX9-LABEL: v_lshr_v2i16: ; GFX9-LABEL: v_lshr_v2i16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dword v1, v0, s[2:3] ; GFX9-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3]
; GFX9-NEXT: global_load_dword v2, v0, s[2:3] offset:4
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_pk_lshrrev_b16 v1, v2, v1 ; GFX9-NEXT: v_pk_lshrrev_b16 v0, v1, v0
; GFX9-NEXT: global_store_dword v0, v1, s[0:1] ; GFX9-NEXT: global_store_dword v2, v0, s[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: v_lshr_v2i16: ; VI-LABEL: v_lshr_v2i16:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v5, v[0:1]
; VI-NEXT: flat_load_dword v2, v[2:3]
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v4
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshrrev_b16_e32 v3, v2, v5 ; VI-NEXT: v_lshrrev_b16_e32 v4, v1, v0
; VI-NEXT: v_lshrrev_b16_sdwa v2, v2, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-NEXT: v_or_b32_e32 v2, v3, v2 ; VI-NEXT: v_or_b32_e32 v0, v4, v0
; VI-NEXT: flat_store_dword v[0:1], v2 ; VI-NEXT: flat_store_dword v[2:3], v0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; CI-LABEL: v_lshr_v2i16: ; CI-LABEL: v_lshr_v2i16:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; CI-NEXT: s_mov_b32 s7, 0xf000 ; CI-NEXT: s_mov_b32 s7, 0xf000
; CI-NEXT: s_mov_b32 s6, 0 ; CI-NEXT: s_mov_b32 s6, 0
; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; CI-NEXT: v_mov_b32_e32 v1, 0 ; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_mov_b64 s[4:5], s[2:3] ; CI-NEXT: s_mov_b64 s[4:5], s[2:3]
; CI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 ; CI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
; CI-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 offset:4
; CI-NEXT: s_mov_b64 s[2:3], s[6:7] ; CI-NEXT: s_mov_b64 s[2:3], s[6:7]
; CI-NEXT: s_waitcnt vmcnt(1) ; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_lshrrev_b32_e32 v4, 16, v2 ; CI-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; CI-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; CI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_lshrrev_b32_e32 v5, 16, v3 ; CI-NEXT: v_lshrrev_b32_e32 v5, 16, v3
; CI-NEXT: v_lshrrev_b32_e32 v2, v3, v2 ; CI-NEXT: v_lshrrev_b32_e32 v2, v3, v2
; CI-NEXT: v_lshrrev_b32_e32 v3, v5, v4 ; CI-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; CI-NEXT: v_or_b32_e32 v2, v2, v3 ; CI-NEXT: v_or_b32_e32 v2, v2, v3
; CI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 ; CI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; GFX10-LABEL: v_lshr_v2i16: ; GFX10-LABEL: v_lshr_v2i16:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3]
; GFX10-NEXT: global_load_dword v1, v0, s[2:3]
; GFX10-NEXT: global_load_dword v2, v0, s[2:3] offset:4
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_pk_lshrrev_b16 v1, v2, v1 ; GFX10-NEXT: v_pk_lshrrev_b16 v0, v1, v0
; GFX10-NEXT: global_store_dword v0, v1, s[0:1] ; GFX10-NEXT: global_store_dword v2, v0, s[0:1]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
%out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
%b_ptr = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %in.gep, i32 1 %b_ptr = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %in.gep, i32 1
%a = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep %a = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
%b = load <2 x i16>, <2 x i16> addrspace(1)* %b_ptr %b = load <2 x i16>, <2 x i16> addrspace(1)* %b_ptr
▲ Show 20 Lines • Show All 301 Lines • ▼ Show 20 Lines
} }
define amdgpu_kernel void @v_lshr_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) #0 { define amdgpu_kernel void @v_lshr_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) #0 {
; GFX9-LABEL: v_lshr_v4i16: ; GFX9-LABEL: v_lshr_v4i16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 3, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v4, 3, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dwordx2 v[0:1], v4, s[2:3] ; GFX9-NEXT: global_load_dwordx4 v[0:3], v4, s[2:3]
; GFX9-NEXT: global_load_dwordx2 v[2:3], v4, s[2:3] offset:8
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_pk_lshrrev_b16 v1, v3, v1 ; GFX9-NEXT: v_pk_lshrrev_b16 v1, v3, v1
; GFX9-NEXT: v_pk_lshrrev_b16 v0, v2, v0 ; GFX9-NEXT: v_pk_lshrrev_b16 v0, v2, v0
; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1] ; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: v_lshr_v4i16: ; VI-LABEL: v_lshr_v4i16:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v4, 3, v0 ; VI-NEXT: v_lshlrev_b32_e32 v4, 3, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0 ; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; VI-NEXT: flat_load_dwordx2 v[2:3], v[2:3]
; VI-NEXT: v_mov_b32_e32 v5, s1 ; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_add_u32_e32 v4, vcc, s0, v4 ; VI-NEXT: v_add_u32_e32 v4, vcc, s0, v4
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshrrev_b16_e32 v6, v3, v1 ; VI-NEXT: v_lshrrev_b16_e32 v6, v3, v1
; VI-NEXT: v_lshrrev_b16_sdwa v1, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-NEXT: v_lshrrev_b16_sdwa v1, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-NEXT: v_lshrrev_b16_e32 v3, v2, v0 ; VI-NEXT: v_lshrrev_b16_e32 v3, v2, v0
; VI-NEXT: v_lshrrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-NEXT: v_lshrrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-NEXT: v_or_b32_e32 v1, v6, v1 ; VI-NEXT: v_or_b32_e32 v1, v6, v1
; VI-NEXT: v_or_b32_e32 v0, v3, v0 ; VI-NEXT: v_or_b32_e32 v0, v3, v0
; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1] ; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; CI-LABEL: v_lshr_v4i16: ; CI-LABEL: v_lshr_v4i16:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; CI-NEXT: s_mov_b32 s7, 0xf000 ; CI-NEXT: s_mov_b32 s7, 0xf000
; CI-NEXT: s_mov_b32 s6, 0 ; CI-NEXT: s_mov_b32 s6, 0
; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 ; CI-NEXT: v_lshlrev_b32_e32 v4, 3, v0
; CI-NEXT: v_mov_b32_e32 v1, 0 ; CI-NEXT: v_mov_b32_e32 v5, 0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_mov_b64 s[4:5], s[2:3] ; CI-NEXT: s_mov_b64 s[4:5], s[2:3]
; CI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 ; CI-NEXT: buffer_load_dwordx4 v[0:3], v[4:5], s[4:7], 0 addr64
; CI-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[4:7], 0 addr64 offset:8
; CI-NEXT: s_mov_b32 s4, 0xffff ; CI-NEXT: s_mov_b32 s4, 0xffff
; CI-NEXT: s_mov_b64 s[2:3], s[6:7] ; CI-NEXT: s_mov_b64 s[2:3], s[6:7]
; CI-NEXT: s_waitcnt vmcnt(1)
; CI-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; CI-NEXT: v_and_b32_e32 v2, s4, v2
; CI-NEXT: v_lshrrev_b32_e32 v7, 16, v3
; CI-NEXT: v_and_b32_e32 v3, s4, v3
; CI-NEXT: s_waitcnt vmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_lshrrev_b32_e32 v8, 16, v4 ; CI-NEXT: v_lshrrev_b32_e32 v6, 16, v0
; CI-NEXT: v_lshrrev_b32_e32 v9, 16, v5 ; CI-NEXT: v_and_b32_e32 v0, s4, v0
; CI-NEXT: v_lshrrev_b32_e32 v3, v5, v3 ; CI-NEXT: v_lshrrev_b32_e32 v7, 16, v1
; CI-NEXT: v_lshrrev_b32_e32 v5, v9, v7 ; CI-NEXT: v_and_b32_e32 v1, s4, v1
; CI-NEXT: v_lshrrev_b32_e32 v2, v4, v2 ; CI-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; CI-NEXT: v_lshrrev_b32_e32 v4, v8, v6 ; CI-NEXT: v_lshrrev_b32_e32 v9, 16, v3
; CI-NEXT: v_lshlrev_b32_e32 v5, 16, v5 ; CI-NEXT: v_lshrrev_b32_e32 v1, v3, v1
; CI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; CI-NEXT: v_lshrrev_b32_e32 v3, v9, v7
; CI-NEXT: v_or_b32_e32 v3, v3, v5 ; CI-NEXT: v_lshrrev_b32_e32 v0, v2, v0
; CI-NEXT: v_or_b32_e32 v2, v2, v4 ; CI-NEXT: v_lshrrev_b32_e32 v2, v8, v6
; CI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 ; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; CI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; CI-NEXT: v_or_b32_e32 v1, v1, v3
; CI-NEXT: v_or_b32_e32 v0, v0, v2
; CI-NEXT: buffer_store_dwordx2 v[0:1], v[4:5], s[0:3], 0 addr64
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; GFX10-LABEL: v_lshr_v4i16: ; GFX10-LABEL: v_lshr_v4i16:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-NEXT: v_lshlrev_b32_e32 v4, 3, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v4, 3, v0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: global_load_dwordx4 v[0:3], v4, s[2:3]
; GFX10-NEXT: global_load_dwordx2 v[0:1], v4, s[2:3]
; GFX10-NEXT: global_load_dwordx2 v[2:3], v4, s[2:3] offset:8
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_pk_lshrrev_b16 v1, v3, v1 ; GFX10-NEXT: v_pk_lshrrev_b16 v1, v3, v1
; GFX10-NEXT: v_pk_lshrrev_b16 v0, v2, v0 ; GFX10-NEXT: v_pk_lshrrev_b16 v0, v2, v0
; GFX10-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1] ; GFX10-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%in.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %in, i64 %tid.ext %in.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %in, i64 %tid.ext
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llvm/test/CodeGen/AMDGPU/memory_clause.ll

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Linesbb:
store <4 x i32> %tmp12, <4 x i32> addrspace(1)* %tmp13, align 16 store <4 x i32> %tmp12, <4 x i32> addrspace(1)* %tmp13, align 16
store <4 x i32> %tmp16, <4 x i32> addrspace(1)* %tmp17, align 16 store <4 x i32> %tmp16, <4 x i32> addrspace(1)* %tmp17, align 16
ret void ret void
} }
define amdgpu_kernel void @scalar_clause(<4 x i32> addrspace(1)* noalias nocapture readonly %arg, <4 x i32> addrspace(1)* noalias nocapture %arg1) { define amdgpu_kernel void @scalar_clause(<4 x i32> addrspace(1)* noalias nocapture readonly %arg, <4 x i32> addrspace(1)* noalias nocapture %arg1) {
; GCN-LABEL: scalar_clause: ; GCN-LABEL: scalar_clause:
; GCN: ; %bb.0: ; %bb ; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x24 ; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GCN-NEXT: s_load_dwordx2 s[16:17], s[0:1], 0x2c ; GCN-NEXT: s_load_dwordx2 s[16:17], s[0:1], 0x2c
; GCN-NEXT: v_mov_b32_e32 v12, 0 ; GCN-NEXT: v_mov_b32_e32 v16, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_load_dwordx4 s[0:3], s[12:13], 0x0 ; GCN-NEXT: s_load_dwordx16 s[0:15], s[2:3], 0x0
; GCN-NEXT: s_load_dwordx4 s[4:7], s[12:13], 0x10
; GCN-NEXT: s_load_dwordx4 s[8:11], s[12:13], 0x20
; GCN-NEXT: s_nop 0
; GCN-NEXT: s_load_dwordx4 s[12:15], s[12:13], 0x30
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, s0 ; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1 ; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: v_mov_b32_e32 v2, s2 ; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v3, s3 ; GCN-NEXT: v_mov_b32_e32 v3, s3
; GCN-NEXT: v_mov_b32_e32 v4, s4 ; GCN-NEXT: v_mov_b32_e32 v4, s4
; GCN-NEXT: v_mov_b32_e32 v8, s8
; GCN-NEXT: v_mov_b32_e32 v5, s5 ; GCN-NEXT: v_mov_b32_e32 v5, s5
; GCN-NEXT: v_mov_b32_e32 v6, s6 ; GCN-NEXT: v_mov_b32_e32 v6, s6
; GCN-NEXT: v_mov_b32_e32 v7, s7 ; GCN-NEXT: v_mov_b32_e32 v7, s7
; GCN-NEXT: v_mov_b32_e32 v8, s8
; GCN-NEXT: v_mov_b32_e32 v9, s9 ; GCN-NEXT: v_mov_b32_e32 v9, s9
; GCN-NEXT: v_mov_b32_e32 v10, s10 ; GCN-NEXT: v_mov_b32_e32 v10, s10
; GCN-NEXT: v_mov_b32_e32 v11, s11 ; GCN-NEXT: v_mov_b32_e32 v11, s11
; GCN-NEXT: global_store_dwordx4 v12, v[0:3], s[16:17] ; GCN-NEXT: v_mov_b32_e32 v12, s12
; GCN-NEXT: global_store_dwordx4 v12, v[4:7], s[16:17] offset:16 ; GCN-NEXT: v_mov_b32_e32 v13, s13
; GCN-NEXT: global_store_dwordx4 v12, v[8:11], s[16:17] offset:32 ; GCN-NEXT: v_mov_b32_e32 v14, s14
; GCN-NEXT: v_mov_b32_e32 v0, s12 ; GCN-NEXT: v_mov_b32_e32 v15, s15
; GCN-NEXT: v_mov_b32_e32 v1, s13 ; GCN-NEXT: global_store_dwordx4 v16, v[0:3], s[16:17]
; GCN-NEXT: v_mov_b32_e32 v2, s14 ; GCN-NEXT: global_store_dwordx4 v16, v[4:7], s[16:17] offset:16
; GCN-NEXT: v_mov_b32_e32 v3, s15 ; GCN-NEXT: global_store_dwordx4 v16, v[8:11], s[16:17] offset:32
; GCN-NEXT: global_store_dwordx4 v12, v[0:3], s[16:17] offset:48 ; GCN-NEXT: global_store_dwordx4 v16, v[12:15], s[16:17] offset:48
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GCN-SCRATCH-LABEL: scalar_clause: ; GCN-SCRATCH-LABEL: scalar_clause:
; GCN-SCRATCH: ; %bb.0: ; %bb ; GCN-SCRATCH: ; %bb.0: ; %bb
; GCN-SCRATCH-NEXT: s_clause 0x1 ; GCN-SCRATCH-NEXT: s_clause 0x1
; GCN-SCRATCH-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x24 ; GCN-SCRATCH-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GCN-SCRATCH-NEXT: s_load_dwordx2 s[16:17], s[0:1], 0x2c ; GCN-SCRATCH-NEXT: s_load_dwordx2 s[16:17], s[0:1], 0x2c
; GCN-SCRATCH-NEXT: v_mov_b32_e32 v16, 0 ; GCN-SCRATCH-NEXT: v_mov_b32_e32 v16, 0
; GCN-SCRATCH-NEXT: s_waitcnt lgkmcnt(0) ; GCN-SCRATCH-NEXT: s_waitcnt lgkmcnt(0)
; GCN-SCRATCH-NEXT: s_clause 0x3 ; GCN-SCRATCH-NEXT: s_load_dwordx16 s[0:15], s[2:3], 0x0
; GCN-SCRATCH-NEXT: s_load_dwordx4 s[0:3], s[12:13], 0x0
; GCN-SCRATCH-NEXT: s_load_dwordx4 s[4:7], s[12:13], 0x10
; GCN-SCRATCH-NEXT: s_load_dwordx4 s[8:11], s[12:13], 0x20
; GCN-SCRATCH-NEXT: s_load_dwordx4 s[12:15], s[12:13], 0x30
; GCN-SCRATCH-NEXT: s_waitcnt lgkmcnt(0) ; GCN-SCRATCH-NEXT: s_waitcnt lgkmcnt(0)
; GCN-SCRATCH-NEXT: v_mov_b32_e32 v0, s0 ; GCN-SCRATCH-NEXT: v_mov_b32_e32 v0, s0
; GCN-SCRATCH-NEXT: v_mov_b32_e32 v1, s1 ; GCN-SCRATCH-NEXT: v_mov_b32_e32 v1, s1
; GCN-SCRATCH-NEXT: v_mov_b32_e32 v2, s2 ; GCN-SCRATCH-NEXT: v_mov_b32_e32 v2, s2
; GCN-SCRATCH-NEXT: v_mov_b32_e32 v3, s3 ; GCN-SCRATCH-NEXT: v_mov_b32_e32 v3, s3
; GCN-SCRATCH-NEXT: v_mov_b32_e32 v4, s4 ; GCN-SCRATCH-NEXT: v_mov_b32_e32 v4, s4
; GCN-SCRATCH-NEXT: v_mov_b32_e32 v5, s5 ; GCN-SCRATCH-NEXT: v_mov_b32_e32 v5, s5
; GCN-SCRATCH-NEXT: v_mov_b32_e32 v6, s6 ; GCN-SCRATCH-NEXT: v_mov_b32_e32 v6, s6
▲ Show 20 Lines • Show All 408 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/min.ll

Show First 20 Lines • Show All 101 Lines • ▼ Show 20 Lines
define amdgpu_kernel void @s_test_imin_sle_v4i8(<4 x i8> addrspace(1)* %out, [8 x i32], <4 x i8> %a, [8 x i32], <4 x i8> %b) #0 { define amdgpu_kernel void @s_test_imin_sle_v4i8(<4 x i8> addrspace(1)* %out, [8 x i32], <4 x i8> %a, [8 x i32], <4 x i8> %b) #0 {
%cmp = icmp sle <4 x i8> %a, %b %cmp = icmp sle <4 x i8> %a, %b
%val = select <4 x i1> %cmp, <4 x i8> %a, <4 x i8> %b %val = select <4 x i1> %cmp, <4 x i8> %a, <4 x i8> %b
store <4 x i8> %val, <4 x i8> addrspace(1)* %out store <4 x i8> %val, <4 x i8> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}s_test_imin_sle_v2i16: ; FUNC-LABEL: {{^}}s_test_imin_sle_v2i16:
; GCN: s_load_dword s ; GCN: s_load_dwordx2 s
; GCN: s_load_dword s ; GCN: s_load_dwordx2 s
; SI: s_ashr_i32 ; SI: s_ashr_i32
; SI: s_sext_i32_i16 ; SI: s_sext_i32_i16
; SI: s_ashr_i32 ; SI: s_ashr_i32
; SI: s_sext_i32_i16 ; SI: s_sext_i32_i16
; SI: s_min_i32 ; SI: s_min_i32
; SI: s_min_i32 ; SI: s_min_i32
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llvm/test/CodeGen/AMDGPU/mul_int24.ll

Show First 20 Lines • Show All 703 Lines • ▼ Show 20 Lines
; SI: ; %bb.0: ; %bb ; SI: ; %bb.0: ; %bb
; SI-NEXT: s_load_dword s2, s[0:1], 0xb ; SI-NEXT: s_load_dword s2, s[0:1], 0xb
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_cmp_lg_u32 s2, 0 ; SI-NEXT: s_cmp_lg_u32 s2, 0
; SI-NEXT: s_cbranch_scc0 .LBB8_2 ; SI-NEXT: s_cbranch_scc0 .LBB8_2
; SI-NEXT: ; %bb.1: ; %bb7 ; SI-NEXT: ; %bb.1: ; %bb7
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; SI-NEXT: .LBB8_2: ; %bb11 ; SI-NEXT: .LBB8_2: ; %bb11
; SI-NEXT: s_load_dword s2, s[0:1], 0xd ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd
; SI-NEXT: s_load_dword s4, s[0:1], 0xf
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_bfe_i32 s2, s2, 0x180000 ; SI-NEXT: s_bfe_i32 s2, s4, 0x180000
; SI-NEXT: s_bfe_i32 s4, s4, 0x180000 ; SI-NEXT: s_bfe_i32 s4, s6, 0x180000
; SI-NEXT: s_mul_i32 s4, s2, s4 ; SI-NEXT: s_mul_i32 s4, s2, s4
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: v_mov_b32_e32 v0, s4 ; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s4 ; SI-NEXT: v_mov_b32_e32 v1, s4
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: simplify_i24_crash: ; VI-LABEL: simplify_i24_crash:
; VI: ; %bb.0: ; %bb ; VI: ; %bb.0: ; %bb
; VI-NEXT: s_load_dword s2, s[0:1], 0x2c ; VI-NEXT: s_load_dword s2, s[0:1], 0x2c
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_cmp_lg_u32 s2, 0 ; VI-NEXT: s_cmp_lg_u32 s2, 0
; VI-NEXT: s_cbranch_scc0 .LBB8_2 ; VI-NEXT: s_cbranch_scc0 .LBB8_2
; VI-NEXT: ; %bb.1: ; %bb7 ; VI-NEXT: ; %bb.1: ; %bb7
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; VI-NEXT: .LBB8_2: ; %bb11 ; VI-NEXT: .LBB8_2: ; %bb11
; VI-NEXT: s_load_dword s4, s[0:1], 0x34 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
; VI-NEXT: s_load_dword s5, s[0:1], 0x3c
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_bfe_i32 s4, s4, 0x180000 ; VI-NEXT: s_bfe_i32 s4, s4, 0x180000
; VI-NEXT: s_bfe_i32 s5, s5, 0x180000 ; VI-NEXT: s_bfe_i32 s5, s6, 0x180000
; VI-NEXT: s_mul_i32 s4, s4, s5 ; VI-NEXT: s_mul_i32 s4, s4, s5
; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s4 ; VI-NEXT: v_mov_b32_e32 v1, s4
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: simplify_i24_crash: ; GFX9-LABEL: simplify_i24_crash:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_load_dword s2, s[0:1], 0x2c ; GFX9-NEXT: s_load_dword s2, s[0:1], 0x2c
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_cmp_lg_u32 s2, 0 ; GFX9-NEXT: s_cmp_lg_u32 s2, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB8_2 ; GFX9-NEXT: s_cbranch_scc0 .LBB8_2
; GFX9-NEXT: ; %bb.1: ; %bb7 ; GFX9-NEXT: ; %bb.1: ; %bb7
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; GFX9-NEXT: .LBB8_2: ; %bb11 ; GFX9-NEXT: .LBB8_2: ; %bb11
; GFX9-NEXT: s_load_dword s2, s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
; GFX9-NEXT: s_load_dword s3, s[0:1], 0x3c ; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX9-NEXT: s_mov_b32 s11, 0xf000
; GFX9-NEXT: s_mov_b32 s7, 0xf000 ; GFX9-NEXT: s_mov_b32 s10, -1
; GFX9-NEXT: s_mov_b32 s6, -1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_bfe_i32 s0, s2, 0x180000 ; GFX9-NEXT: s_bfe_i32 s0, s4, 0x180000
; GFX9-NEXT: s_bfe_i32 s1, s3, 0x180000 ; GFX9-NEXT: s_bfe_i32 s1, s6, 0x180000
; GFX9-NEXT: s_mul_i32 s0, s0, s1 ; GFX9-NEXT: s_mul_i32 s0, s0, s1
; GFX9-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s0 ; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; EG-LABEL: simplify_i24_crash: ; EG-LABEL: simplify_i24_crash:
; EG: ; %bb.0: ; %bb ; EG: ; %bb.0: ; %bb
; EG-NEXT: ALU_PUSH_BEFORE 1, @6, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU_PUSH_BEFORE 1, @6, KC0[CB0:0-32], KC1[]
; EG-NEXT: JUMP @5 POP:1 ; EG-NEXT: JUMP @5 POP:1
; EG-NEXT: ALU 10, @8, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 10, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 0 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 0
▲ Show 20 Lines • Show All 64 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/sdiv.ll

Show First 20 Lines • Show All 434 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_mul_hi_u32 v6, v7, v11 ; GCN-NEXT: v_mul_hi_u32 v6, v7, v11
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5
; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v7 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v7
; GCN-NEXT: v_mul_hi_u32 v4, v0, v4 ; GCN-NEXT: v_mul_hi_u32 v4, v0, v4
; GCN-NEXT: v_mul_hi_u32 v5, v1, v5 ; GCN-NEXT: v_mul_hi_u32 v5, v1, v5
; GCN-NEXT: v_mul_lo_u32 v6, v4, v2 ; GCN-NEXT: v_mul_lo_u32 v6, v4, v2
; GCN-NEXT: v_mul_lo_u32 v10, v5, v3 ; GCN-NEXT: v_mul_lo_u32 v10, v5, v3
; GCN-NEXT: v_add_i32_e32 v7, vcc, 1, v4 ; GCN-NEXT: v_add_i32_e32 v7, vcc, 1, v4
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v6, v0 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v6
; GCN-NEXT: v_subrev_i32_e32 v1, vcc, v10, v1 ; GCN-NEXT: v_sub_i32_e32 v1, vcc, v1, v10
; GCN-NEXT: v_add_i32_e32 v11, vcc, 1, v5 ; GCN-NEXT: v_add_i32_e32 v11, vcc, 1, v5
; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v2 ; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v2
; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v1, v3 ; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v1, v3
; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[0:1]
; GCN-NEXT: v_subrev_i32_e32 v6, vcc, v2, v0 ; GCN-NEXT: v_sub_i32_e32 v6, vcc, v0, v2
; GCN-NEXT: v_cndmask_b32_e64 v5, v5, v11, s[2:3] ; GCN-NEXT: v_cndmask_b32_e64 v5, v5, v11, s[2:3]
; GCN-NEXT: v_subrev_i32_e32 v7, vcc, v3, v1 ; GCN-NEXT: v_sub_i32_e32 v7, vcc, v1, v3
; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[0:1]
; GCN-NEXT: v_add_i32_e32 v6, vcc, 1, v4 ; GCN-NEXT: v_add_i32_e32 v6, vcc, 1, v4
; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[2:3] ; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[2:3]
; GCN-NEXT: v_add_i32_e32 v7, vcc, 1, v5 ; GCN-NEXT: v_add_i32_e32 v7, vcc, 1, v5
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
; GCN-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc ; GCN-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc
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; TONGA-NEXT: v_mul_hi_u32 v6, v7, v11 ; TONGA-NEXT: v_mul_hi_u32 v6, v7, v11
; TONGA-NEXT: v_add_u32_e32 v4, vcc, v4, v5 ; TONGA-NEXT: v_add_u32_e32 v4, vcc, v4, v5
; TONGA-NEXT: v_add_u32_e32 v5, vcc, v6, v7 ; TONGA-NEXT: v_add_u32_e32 v5, vcc, v6, v7
; TONGA-NEXT: v_mul_hi_u32 v4, v0, v4 ; TONGA-NEXT: v_mul_hi_u32 v4, v0, v4
; TONGA-NEXT: v_mul_hi_u32 v5, v1, v5 ; TONGA-NEXT: v_mul_hi_u32 v5, v1, v5
; TONGA-NEXT: v_mul_lo_u32 v6, v4, v2 ; TONGA-NEXT: v_mul_lo_u32 v6, v4, v2
; TONGA-NEXT: v_mul_lo_u32 v10, v5, v3 ; TONGA-NEXT: v_mul_lo_u32 v10, v5, v3
; TONGA-NEXT: v_add_u32_e32 v7, vcc, 1, v4 ; TONGA-NEXT: v_add_u32_e32 v7, vcc, 1, v4
; TONGA-NEXT: v_subrev_u32_e32 v0, vcc, v6, v0 ; TONGA-NEXT: v_sub_u32_e32 v0, vcc, v0, v6
; TONGA-NEXT: v_subrev_u32_e32 v1, vcc, v10, v1 ; TONGA-NEXT: v_sub_u32_e32 v1, vcc, v1, v10
; TONGA-NEXT: v_add_u32_e32 v11, vcc, 1, v5 ; TONGA-NEXT: v_add_u32_e32 v11, vcc, 1, v5
; TONGA-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v2 ; TONGA-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v2
; TONGA-NEXT: v_cmp_ge_u32_e64 s[2:3], v1, v3 ; TONGA-NEXT: v_cmp_ge_u32_e64 s[2:3], v1, v3
; TONGA-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[0:1] ; TONGA-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[0:1]
; TONGA-NEXT: v_subrev_u32_e32 v6, vcc, v2, v0 ; TONGA-NEXT: v_sub_u32_e32 v6, vcc, v0, v2
; TONGA-NEXT: v_cndmask_b32_e64 v5, v5, v11, s[2:3] ; TONGA-NEXT: v_cndmask_b32_e64 v5, v5, v11, s[2:3]
; TONGA-NEXT: v_subrev_u32_e32 v7, vcc, v3, v1 ; TONGA-NEXT: v_sub_u32_e32 v7, vcc, v1, v3
; TONGA-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[0:1] ; TONGA-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[0:1]
; TONGA-NEXT: v_add_u32_e32 v6, vcc, 1, v4 ; TONGA-NEXT: v_add_u32_e32 v6, vcc, 1, v4
; TONGA-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[2:3] ; TONGA-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[2:3]
; TONGA-NEXT: v_add_u32_e32 v7, vcc, 1, v5 ; TONGA-NEXT: v_add_u32_e32 v7, vcc, 1, v5
; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 ; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
; TONGA-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc ; TONGA-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc
; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3 ; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
; TONGA-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc ; TONGA-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc
; TONGA-NEXT: v_xor_b32_e32 v0, v0, v8 ; TONGA-NEXT: v_xor_b32_e32 v0, v0, v8
; TONGA-NEXT: v_xor_b32_e32 v1, v1, v9 ; TONGA-NEXT: v_xor_b32_e32 v1, v1, v9
; TONGA-NEXT: v_sub_u32_e32 v0, vcc, v0, v8 ; TONGA-NEXT: v_subrev_u32_e32 v0, vcc, v8, v0
; TONGA-NEXT: v_sub_u32_e32 v1, vcc, v1, v9 ; TONGA-NEXT: v_subrev_u32_e32 v1, vcc, v9, v1
; TONGA-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; TONGA-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; TONGA-NEXT: s_endpgm ; TONGA-NEXT: s_endpgm
; ;
; GFX9-LABEL: sdiv_v2i32: ; GFX9-LABEL: sdiv_v2i32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: s_mov_b32 s7, 0xf000 ; GFX9-NEXT: s_mov_b32 s7, 0xf000
; GFX9-NEXT: s_mov_b32 s6, -1 ; GFX9-NEXT: s_mov_b32 s6, -1
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; GFX9-NEXT: v_xor_b32_e32 v1, v1, v5 ; GFX9-NEXT: v_xor_b32_e32 v1, v1, v5
; GFX9-NEXT: v_sub_u32_e32 v0, v0, v4 ; GFX9-NEXT: v_sub_u32_e32 v0, v0, v4
; GFX9-NEXT: v_sub_u32_e32 v1, v1, v5 ; GFX9-NEXT: v_sub_u32_e32 v1, v1, v5
; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; EG-LABEL: sdiv_v2i32: ; EG-LABEL: sdiv_v2i32:
; EG: ; %bb.0: ; EG: ; %bb.0:
; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 1 @6 ; EG-NEXT: TEX 0 @6
; EG-NEXT: ALU 51, @11, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 51, @9, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
; EG-NEXT: CF_END ; EG-NEXT: CF_END
; EG-NEXT: PAD ; EG-NEXT: PAD
; EG-NEXT: Fetch clause starting at 6: ; EG-NEXT: Fetch clause starting at 6:
; EG-NEXT: VTX_READ_64 T1.XY, T0.X, 8, #1 ; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1 ; EG-NEXT: ALU clause starting at 8:
; EG-NEXT: ALU clause starting at 10:
; EG-NEXT: MOV * T0.X, KC0[2].Z, ; EG-NEXT: MOV * T0.X, KC0[2].Z,
; EG-NEXT: ALU clause starting at 11: ; EG-NEXT: ALU clause starting at 9:
; EG-NEXT: SETGT_INT * T0.W, 0.0, T1.Y, ; EG-NEXT: SETGT_INT * T1.W, 0.0, T0.W,
; EG-NEXT: ADD_INT T1.W, T1.Y, PV.W, ; EG-NEXT: ADD_INT T0.W, T0.W, PV.W,
; EG-NEXT: SETGT_INT * T2.W, 0.0, T1.X, ; EG-NEXT: SETGT_INT * T2.W, 0.0, T0.Z,
; EG-NEXT: XOR_INT * T1.W, PV.W, T0.W, ; EG-NEXT: XOR_INT * T0.W, PV.W, T1.W,
; EG-NEXT: SUB_INT T0.Z, 0.0, PV.W, ; EG-NEXT: SUB_INT T1.Z, 0.0, PV.W,
; EG-NEXT: ADD_INT T3.W, T1.X, T2.W, ; EG-NEXT: ADD_INT T3.W, T0.Z, T2.W,
; EG-NEXT: RECIP_UINT * T1.X, PV.W, ; EG-NEXT: RECIP_UINT * T0.Z, PV.W,
; EG-NEXT: XOR_INT T3.W, PV.W, T2.W, ; EG-NEXT: XOR_INT T3.W, PV.W, T2.W,
; EG-NEXT: MULLO_INT * T0.Z, PV.Z, PS, ; EG-NEXT: MULLO_INT * T1.X, PV.Z, PS,
; EG-NEXT: SUB_INT T4.W, 0.0, PV.W, ; EG-NEXT: SUB_INT T4.W, 0.0, PV.W,
; EG-NEXT: RECIP_UINT * T1.Y, PV.W, ; EG-NEXT: RECIP_UINT * T1.Y, PV.W,
; EG-NEXT: SETGT_INT T5.W, 0.0, T0.X, ; EG-NEXT: SETGT_INT T5.W, 0.0, T0.X,
; EG-NEXT: MULLO_INT * T1.Z, PV.W, PS, ; EG-NEXT: MULLO_INT * T1.Z, PV.W, PS,
; EG-NEXT: SETGT_INT T2.Z, 0.0, T0.Y, ; EG-NEXT: SETGT_INT T2.Z, 0.0, T0.Y,
; EG-NEXT: ADD_INT T4.W, T0.X, PV.W, ; EG-NEXT: ADD_INT T4.W, T0.X, PV.W,
; EG-NEXT: MULHI * T0.X, T1.Y, PS, ; EG-NEXT: MULHI * T0.X, T1.Y, PS,
; EG-NEXT: ADD_INT T1.Y, T1.Y, PS, ; EG-NEXT: ADD_INT T1.Y, T1.Y, PS,
; EG-NEXT: XOR_INT T1.Z, PV.W, T5.W, ; EG-NEXT: XOR_INT T1.Z, PV.W, T5.W,
; EG-NEXT: ADD_INT T4.W, T0.Y, PV.Z, BS:VEC_120/SCL_212 ; EG-NEXT: ADD_INT T4.W, T0.Y, PV.Z, BS:VEC_120/SCL_212
; EG-NEXT: MULHI * T0.X, T1.X, T0.Z, ; EG-NEXT: MULHI * T0.X, T0.Z, T1.X,
; EG-NEXT: ADD_INT T0.Z, T1.X, PS, ; EG-NEXT: ADD_INT T0.Z, T0.Z, PS,
; EG-NEXT: XOR_INT T4.W, PV.W, T2.Z, ; EG-NEXT: XOR_INT T4.W, PV.W, T2.Z,
; EG-NEXT: MULHI * T0.X, PV.Z, PV.Y, ; EG-NEXT: MULHI * T0.X, PV.Z, PV.Y,
; EG-NEXT: MULHI * T0.Y, PV.W, PV.Z, ; EG-NEXT: MULHI * T0.Y, PV.W, PV.Z,
; EG-NEXT: MULLO_INT * T0.Z, PS, T1.W, ; EG-NEXT: MULLO_INT * T0.Z, PS, T0.W,
; EG-NEXT: SUB_INT T4.W, T4.W, PS, ; EG-NEXT: SUB_INT T4.W, T4.W, PS,
; EG-NEXT: MULLO_INT * T0.Z, T0.X, T3.W, ; EG-NEXT: MULLO_INT * T0.Z, T0.X, T3.W,
; EG-NEXT: SUB_INT T1.Y, T1.Z, PS, ; EG-NEXT: SUB_INT T1.Y, T1.Z, PS,
; EG-NEXT: ADD_INT T0.Z, T0.Y, 1, ; EG-NEXT: ADD_INT T0.Z, T0.Y, 1,
; EG-NEXT: SETGE_UINT T6.W, PV.W, T1.W, ; EG-NEXT: SETGE_UINT T6.W, PV.W, T0.W,
; EG-NEXT: SUB_INT * T7.W, PV.W, T1.W, ; EG-NEXT: SUB_INT * T7.W, PV.W, T0.W,
; EG-NEXT: CNDE_INT T1.X, PV.W, T4.W, PS, BS:VEC_021/SCL_122 ; EG-NEXT: CNDE_INT T1.X, PV.W, T4.W, PS, BS:VEC_021/SCL_122
; EG-NEXT: CNDE_INT T0.Y, PV.W, T0.Y, PV.Z, ; EG-NEXT: CNDE_INT T0.Y, PV.W, T0.Y, PV.Z,
; EG-NEXT: ADD_INT T0.Z, T0.X, 1, ; EG-NEXT: ADD_INT T0.Z, T0.X, 1,
; EG-NEXT: SETGE_UINT T4.W, PV.Y, T3.W, ; EG-NEXT: SETGE_UINT T4.W, PV.Y, T3.W,
; EG-NEXT: SUB_INT * T6.W, PV.Y, T3.W, ; EG-NEXT: SUB_INT * T6.W, PV.Y, T3.W,
; EG-NEXT: CNDE_INT T1.Y, PV.W, T1.Y, PS, ; EG-NEXT: CNDE_INT T1.Y, PV.W, T1.Y, PS,
; EG-NEXT: CNDE_INT T0.Z, PV.W, T0.X, PV.Z, ; EG-NEXT: CNDE_INT T0.Z, PV.W, T0.X, PV.Z,
; EG-NEXT: ADD_INT T4.W, PV.Y, 1, ; EG-NEXT: ADD_INT T4.W, PV.Y, 1,
; EG-NEXT: SETGE_UINT * T1.W, PV.X, T1.W, ; EG-NEXT: SETGE_UINT * T0.W, PV.X, T0.W,
; EG-NEXT: CNDE_INT T0.Y, PS, T0.Y, PV.W, ; EG-NEXT: CNDE_INT T0.Y, PS, T0.Y, PV.W,
; EG-NEXT: XOR_INT T1.Z, T2.Z, T0.W, BS:VEC_021/SCL_122 ; EG-NEXT: XOR_INT T1.Z, T2.Z, T1.W, BS:VEC_021/SCL_122
; EG-NEXT: ADD_INT T0.W, PV.Z, 1, ; EG-NEXT: ADD_INT T0.W, PV.Z, 1,
; EG-NEXT: SETGE_UINT * T1.W, PV.Y, T3.W, ; EG-NEXT: SETGE_UINT * T1.W, PV.Y, T3.W,
; EG-NEXT: CNDE_INT T0.Z, PS, T0.Z, PV.W, ; EG-NEXT: CNDE_INT T0.Z, PS, T0.Z, PV.W,
; EG-NEXT: XOR_INT T0.W, T5.W, T2.W, ; EG-NEXT: XOR_INT T0.W, T5.W, T2.W,
; EG-NEXT: XOR_INT * T1.W, PV.Y, PV.Z, ; EG-NEXT: XOR_INT * T1.W, PV.Y, PV.Z,
; EG-NEXT: SUB_INT T0.Y, PS, T1.Z, ; EG-NEXT: SUB_INT T0.Y, PS, T1.Z,
; EG-NEXT: XOR_INT * T1.W, PV.Z, PV.W, ; EG-NEXT: XOR_INT * T1.W, PV.Z, PV.W,
; EG-NEXT: SUB_INT T0.X, PV.W, T0.W, ; EG-NEXT: SUB_INT T0.X, PV.W, T0.W,
▲ Show 20 Lines • Show All 1,676 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/sdiv64.ll

Show First 20 Lines • Show All 848 Lines • ▼ Show 20 Lines; GCN-IR-NEXT: s_endpgm
%result = sdiv i64 %1, %2 %result = sdiv i64 %1, %2
store i64 %result, i64 addrspace(1)* %out store i64 %result, i64 addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @s_test_sdiv24_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) { define amdgpu_kernel void @s_test_sdiv24_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
; GCN-LABEL: s_test_sdiv24_v2i64: ; GCN-LABEL: s_test_sdiv24_v2i64:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd ; GCN-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd
; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x11
; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_ashr_i64 s[4:5], s[4:5], 40
; GCN-NEXT: s_ashr_i64 s[8:9], s[8:9], 40 ; GCN-NEXT: s_ashr_i64 s[8:9], s[8:9], 40
; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8 ; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8
; GCN-NEXT: s_ashr_i64 s[4:5], s[4:5], 40
; GCN-NEXT: v_cvt_f32_i32_e32 v1, s4 ; GCN-NEXT: v_cvt_f32_i32_e32 v1, s4
; GCN-NEXT: s_xor_b32 s4, s4, s8 ; GCN-NEXT: s_xor_b32 s4, s4, s8
; GCN-NEXT: s_ashr_i32 s4, s4, 30
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 ; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
; GCN-NEXT: s_ashr_i32 s4, s4, 30
; GCN-NEXT: s_or_b32 s4, s4, 1 ; GCN-NEXT: s_or_b32 s4, s4, 1
; GCN-NEXT: v_mov_b32_e32 v3, s4 ; GCN-NEXT: v_mov_b32_e32 v3, s4
; GCN-NEXT: s_ashr_i64 s[10:11], s[10:11], 40
; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
; GCN-NEXT: v_trunc_f32_e32 v2, v2 ; GCN-NEXT: v_trunc_f32_e32 v2, v2
; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| ; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
; GCN-NEXT: s_ashr_i64 s[10:11], s[10:11], 40
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; GCN-NEXT: s_ashr_i64 s[6:7], s[6:7], 40
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GCN-NEXT: v_cvt_f32_i32_e32 v2, s10 ; GCN-NEXT: v_cvt_f32_i32_e32 v2, s10
; GCN-NEXT: s_ashr_i64 s[6:7], s[6:7], 40
; GCN-NEXT: v_cvt_f32_i32_e32 v3, s6 ; GCN-NEXT: v_cvt_f32_i32_e32 v3, s6
; GCN-NEXT: s_xor_b32 s4, s6, s10 ; GCN-NEXT: s_xor_b32 s4, s6, s10
; GCN-NEXT: s_ashr_i32 s4, s4, 30
; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v2 ; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v2
; GCN-NEXT: s_ashr_i32 s4, s4, 30
; GCN-NEXT: s_or_b32 s4, s4, 1 ; GCN-NEXT: s_or_b32 s4, s4, 1
; GCN-NEXT: v_mov_b32_e32 v5, s4 ; GCN-NEXT: v_mov_b32_e32 v5, s4
; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
; GCN-NEXT: v_mul_f32_e32 v4, v3, v4 ; GCN-NEXT: v_mul_f32_e32 v4, v3, v4
; GCN-NEXT: v_trunc_f32_e32 v4, v4 ; GCN-NEXT: v_trunc_f32_e32 v4, v4
; GCN-NEXT: v_mad_f32 v3, -v4, v2, v3 ; GCN-NEXT: v_mad_f32 v3, -v4, v2, v3
; GCN-NEXT: v_cvt_i32_f32_e32 v4, v4 ; GCN-NEXT: v_cvt_i32_f32_e32 v4, v4
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v2| ; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v2|
; GCN-NEXT: v_cndmask_b32_e32 v2, 0, v5, vcc ; GCN-NEXT: v_cndmask_b32_e32 v2, 0, v5, vcc
; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GCN-NEXT: v_bfe_i32 v2, v2, 0, 24 ; GCN-NEXT: v_bfe_i32 v2, v2, 0, 24
; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-NEXT: v_ashrrev_i32_e32 v3, 31, v2 ; GCN-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GCN-IR-LABEL: s_test_sdiv24_v2i64: ; GCN-IR-LABEL: s_test_sdiv24_v2i64:
; GCN-IR: ; %bb.0: ; GCN-IR: ; %bb.0:
; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd ; GCN-IR-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd
; GCN-IR-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x11
; GCN-IR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: s_mov_b32 s2, -1
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[4:5], 40
; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[8:9], 40 ; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[8:9], 40
; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s8 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s8
; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[4:5], 40
; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s4 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s4
; GCN-IR-NEXT: s_xor_b32 s4, s4, s8 ; GCN-IR-NEXT: s_xor_b32 s4, s4, s8
; GCN-IR-NEXT: s_ashr_i32 s4, s4, 30
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0
; GCN-IR-NEXT: s_ashr_i32 s4, s4, 30
; GCN-IR-NEXT: s_or_b32 s4, s4, 1 ; GCN-IR-NEXT: s_or_b32 s4, s4, 1
; GCN-IR-NEXT: v_mov_b32_e32 v3, s4 ; GCN-IR-NEXT: v_mov_b32_e32 v3, s4
; GCN-IR-NEXT: s_ashr_i64 s[10:11], s[10:11], 40
; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2
; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1
; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2
; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
; GCN-IR-NEXT: s_ashr_i64 s[10:11], s[10:11], 40
; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc ; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[6:7], 40
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GCN-IR-NEXT: v_cvt_f32_i32_e32 v2, s10 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v2, s10
; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[6:7], 40
; GCN-IR-NEXT: v_cvt_f32_i32_e32 v3, s6 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v3, s6
; GCN-IR-NEXT: s_xor_b32 s4, s6, s10 ; GCN-IR-NEXT: s_xor_b32 s4, s6, s10
; GCN-IR-NEXT: s_ashr_i32 s4, s4, 30
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v4, v2 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v4, v2
; GCN-IR-NEXT: s_ashr_i32 s4, s4, 30
; GCN-IR-NEXT: s_or_b32 s4, s4, 1 ; GCN-IR-NEXT: s_or_b32 s4, s4, 1
; GCN-IR-NEXT: v_mov_b32_e32 v5, s4 ; GCN-IR-NEXT: v_mov_b32_e32 v5, s4
; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24
; GCN-IR-NEXT: v_mul_f32_e32 v4, v3, v4 ; GCN-IR-NEXT: v_mul_f32_e32 v4, v3, v4
; GCN-IR-NEXT: v_trunc_f32_e32 v4, v4 ; GCN-IR-NEXT: v_trunc_f32_e32 v4, v4
; GCN-IR-NEXT: v_mad_f32 v3, -v4, v2, v3 ; GCN-IR-NEXT: v_mad_f32 v3, -v4, v2, v3
; GCN-IR-NEXT: v_cvt_i32_f32_e32 v4, v4 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v4, v4
; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v2| ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v2|
; GCN-IR-NEXT: v_cndmask_b32_e32 v2, 0, v5, vcc ; GCN-IR-NEXT: v_cndmask_b32_e32 v2, 0, v5, vcc
; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24
; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GCN-IR-NEXT: v_bfe_i32 v2, v2, 0, 24 ; GCN-IR-NEXT: v_bfe_i32 v2, v2, 0, 24
; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-IR-NEXT: v_ashrrev_i32_e32 v3, 31, v2 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GCN-IR-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; GCN-IR-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GCN-IR-NEXT: s_endpgm ; GCN-IR-NEXT: s_endpgm
%1 = ashr <2 x i64> %x, <i64 40, i64 40> %1 = ashr <2 x i64> %x, <i64 40, i64 40>
%2 = ashr <2 x i64> %y, <i64 40, i64 40> %2 = ashr <2 x i64> %y, <i64 40, i64 40>
%result = sdiv <2 x i64> %1, %2 %result = sdiv <2 x i64> %1, %2
store <2 x i64> %result, <2 x i64> addrspace(1)* %out store <2 x i64> %result, <2 x i64> addrspace(1)* %out
ret void ret void
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llvm/test/CodeGen/AMDGPU/select-vectors.ll

Show First 20 Lines • Show All 210 Lines • ▼ Show 20 Lines
define amdgpu_kernel void @select_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> %b, i32 %c) #0 { define amdgpu_kernel void @select_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> %b, i32 %c) #0 {
%cmp = icmp eq i32 %c, 0 %cmp = icmp eq i32 %c, 0
%select = select i1 %cmp, <8 x i32> %a, <8 x i32> %b %select = select i1 %cmp, <8 x i32> %a, <8 x i32> %b
store <8 x i32> %select, <8 x i32> addrspace(1)* %out, align 16 store <8 x i32> %select, <8 x i32> addrspace(1)* %out, align 16
ret void ret void
} }
; GCN-LABEL: {{^}}s_select_v2f32: ; GCN-LABEL: {{^}}s_select_v2f32:
; GCN-DAG: s_load_dwordx2 s{{\[}}[[ALO:[0-9]+]]:[[AHI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}} ; GCN-DAG: s_load_dwordx4 s{{\[}}[[ALO:[0-9]+]]:[[BHI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}}
; GCN-DAG: s_load_dwordx2 s{{\[}}[[BLO:[0-9]+]]:[[BHI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xd|0x34}}
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[AHI]]
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[BHI]] ; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[BHI]]
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[ALO]] ; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[ALO]]
; GCN-DAG: s_cmp_eq_u32 s{{[0-9]+}}, 0{{$}} ; GCN-DAG: s_cmp_eq_u32 s{{[0-9]+}}, 0{{$}}
; GCN-DAG: v_cndmask_b32_e32 ; GCN-DAG: v_cndmask_b32_e32
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[BLO]] ; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}
; GCN-DAG: v_cndmask_b32_e32 ; GCN-DAG: v_cndmask_b32_e32
; GCN: buffer_store_dwordx2 ; GCN: buffer_store_dwordx2
define amdgpu_kernel void @s_select_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b, i32 %c) #0 { define amdgpu_kernel void @s_select_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b, i32 %c) #0 {
%cmp = icmp eq i32 %c, 0 %cmp = icmp eq i32 %c, 0
%select = select i1 %cmp, <2 x float> %a, <2 x float> %b %select = select i1 %cmp, <2 x float> %a, <2 x float> %b
store <2 x float> %select, <2 x float> addrspace(1)* %out, align 16 store <2 x float> %select, <2 x float> addrspace(1)* %out, align 16
ret void ret void
} }
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define amdgpu_kernel void @s_select_v3f32(<3 x float> addrspace(1)* %out, <3 x float> %a, <3 x float> %b, i32 %c) #0 { define amdgpu_kernel void @s_select_v3f32(<3 x float> addrspace(1)* %out, <3 x float> %a, <3 x float> %b, i32 %c) #0 {
%cmp = icmp eq i32 %c, 0 %cmp = icmp eq i32 %c, 0
%select = select i1 %cmp, <3 x float> %a, <3 x float> %b %select = select i1 %cmp, <3 x float> %a, <3 x float> %b
store <3 x float> %select, <3 x float> addrspace(1)* %out, align 16 store <3 x float> %select, <3 x float> addrspace(1)* %out, align 16
ret void ret void
} }
; GCN-LABEL: {{^}}s_select_v4f32: ; GCN-LABEL: {{^}}s_select_v4f32:
; GCN: s_load_dwordx4 ; GCN: s_load_dwordx8
; GCN: s_load_dwordx4
; GCN: s_cmp_eq_u32 s{{[0-9]+}}, 0{{$}} ; GCN: s_cmp_eq_u32 s{{[0-9]+}}, 0{{$}}
; GCN: v_cndmask_b32_e32 ; GCN: v_cndmask_b32_e32
; GCN: v_cndmask_b32_e32 ; GCN: v_cndmask_b32_e32
; GCN: v_cndmask_b32_e32 ; GCN: v_cndmask_b32_e32
; GCN: v_cndmask_b32_e32 ; GCN: v_cndmask_b32_e32
; GCN: buffer_store_dwordx4 ; GCN: buffer_store_dwordx4
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llvm/test/CodeGen/AMDGPU/shift-i128.ll

Show First 20 Lines • Show All 445 Lines • ▼ Show 20 Lines
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
%shl = ashr <2 x i128> %lhs, %rhs %shl = ashr <2 x i128> %lhs, %rhs
ret <2 x i128> %shl ret <2 x i128> %shl
} }
define amdgpu_kernel void @s_shl_v2i128ss(<2 x i128> %lhs, <2 x i128> %rhs) { define amdgpu_kernel void @s_shl_v2i128ss(<2 x i128> %lhs, <2 x i128> %rhs) {
; GCN-LABEL: s_shl_v2i128ss: ; GCN-LABEL: s_shl_v2i128ss:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x8 ; GCN-NEXT: s_load_dwordx16 s[4:19], s[4:5], 0x0
; GCN-NEXT: s_load_dwordx8 s[16:23], s[4:5], 0x0
; GCN-NEXT: v_mov_b32_e32 v10, 16 ; GCN-NEXT: v_mov_b32_e32 v10, 16
; GCN-NEXT: v_mov_b32_e32 v8, 0 ; GCN-NEXT: v_mov_b32_e32 v8, 0
; GCN-NEXT: v_mov_b32_e32 v11, 0 ; GCN-NEXT: v_mov_b32_e32 v11, 0
; GCN-NEXT: v_mov_b32_e32 v9, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_cmp_lt_u64_e64 s[0:1], s[8:9], 64 ; GCN-NEXT: v_cmp_lt_u64_e64 s[0:1], s[12:13], 64
; GCN-NEXT: v_cmp_eq_u64_e64 s[2:3], s[10:11], 0 ; GCN-NEXT: v_cmp_eq_u64_e64 s[2:3], s[14:15], 0
; GCN-NEXT: s_sub_i32 s6, 64, s8 ; GCN-NEXT: s_sub_i32 s22, 64, s12
; GCN-NEXT: s_sub_i32 s4, s8, 64 ; GCN-NEXT: s_sub_i32 s20, s12, 64
; GCN-NEXT: s_lshr_b64 s[6:7], s[16:17], s6 ; GCN-NEXT: s_lshr_b64 s[22:23], s[4:5], s22
; GCN-NEXT: s_lshl_b64 s[24:25], s[18:19], s8 ; GCN-NEXT: s_lshl_b64 s[24:25], s[6:7], s12
; GCN-NEXT: s_lshl_b64 s[4:5], s[16:17], s4 ; GCN-NEXT: s_lshl_b64 s[20:21], s[4:5], s20
; GCN-NEXT: s_or_b64 s[6:7], s[24:25], s[6:7] ; GCN-NEXT: s_or_b64 s[22:23], s[24:25], s[22:23]
; GCN-NEXT: s_and_b64 vcc, s[2:3], s[0:1] ; GCN-NEXT: s_and_b64 vcc, s[2:3], s[0:1]
; GCN-NEXT: s_or_b64 s[0:1], s[8:9], s[10:11] ; GCN-NEXT: s_or_b64 s[0:1], s[12:13], s[14:15]
; GCN-NEXT: v_mov_b32_e32 v0, s5 ; GCN-NEXT: v_mov_b32_e32 v0, s21
; GCN-NEXT: v_mov_b32_e32 v1, s7 ; GCN-NEXT: v_mov_b32_e32 v1, s23
; GCN-NEXT: v_cmp_eq_u64_e64 s[0:1], s[0:1], 0 ; GCN-NEXT: v_cmp_eq_u64_e64 s[0:1], s[0:1], 0
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GCN-NEXT: v_mov_b32_e32 v1, s19 ; GCN-NEXT: v_mov_b32_e32 v1, s7
; GCN-NEXT: v_cndmask_b32_e64 v3, v0, v1, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v3, v0, v1, s[0:1]
; GCN-NEXT: v_mov_b32_e32 v0, s4 ; GCN-NEXT: v_mov_b32_e32 v0, s20
; GCN-NEXT: v_mov_b32_e32 v1, s6 ; GCN-NEXT: v_mov_b32_e32 v1, s22
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GCN-NEXT: v_mov_b32_e32 v1, s18 ; GCN-NEXT: v_mov_b32_e32 v1, s6
; GCN-NEXT: v_cndmask_b32_e64 v2, v0, v1, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v2, v0, v1, s[0:1]
; GCN-NEXT: v_cmp_lt_u64_e64 s[0:1], s[12:13], 64 ; GCN-NEXT: v_cmp_lt_u64_e64 s[0:1], s[16:17], 64
; GCN-NEXT: v_cmp_eq_u64_e64 s[2:3], s[14:15], 0 ; GCN-NEXT: v_cmp_eq_u64_e64 s[2:3], s[18:19], 0
; GCN-NEXT: s_sub_i32 s6, 64, s12 ; GCN-NEXT: s_sub_i32 s13, 64, s16
; GCN-NEXT: s_sub_i32 s4, s12, 64 ; GCN-NEXT: s_sub_i32 s6, s16, 64
; GCN-NEXT: s_lshr_b64 s[6:7], s[20:21], s6 ; GCN-NEXT: s_lshr_b64 s[14:15], s[8:9], s13
; GCN-NEXT: s_lshl_b64 s[10:11], s[22:23], s12 ; GCN-NEXT: s_lshl_b64 s[20:21], s[10:11], s16
; GCN-NEXT: s_lshl_b64 s[4:5], s[20:21], s4 ; GCN-NEXT: s_lshl_b64 s[6:7], s[8:9], s6
; GCN-NEXT: s_or_b64 s[6:7], s[10:11], s[6:7] ; GCN-NEXT: s_or_b64 s[14:15], s[20:21], s[14:15]
; GCN-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1] ; GCN-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]
; GCN-NEXT: s_or_b64 s[2:3], s[12:13], s[14:15] ; GCN-NEXT: s_or_b64 s[2:3], s[16:17], s[18:19]
; GCN-NEXT: v_mov_b32_e32 v0, s5 ; GCN-NEXT: v_mov_b32_e32 v0, s7
; GCN-NEXT: v_mov_b32_e32 v1, s7 ; GCN-NEXT: v_mov_b32_e32 v1, s15
; GCN-NEXT: v_cmp_eq_u64_e64 s[2:3], s[2:3], 0 ; GCN-NEXT: v_cmp_eq_u64_e64 s[2:3], s[2:3], 0
; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1]
; GCN-NEXT: v_mov_b32_e32 v1, s23 ; GCN-NEXT: v_mov_b32_e32 v1, s11
; GCN-NEXT: v_cndmask_b32_e64 v7, v0, v1, s[2:3] ; GCN-NEXT: v_cndmask_b32_e64 v7, v0, v1, s[2:3]
; GCN-NEXT: v_mov_b32_e32 v0, s4 ; GCN-NEXT: v_mov_b32_e32 v0, s6
; GCN-NEXT: v_mov_b32_e32 v1, s6 ; GCN-NEXT: v_mov_b32_e32 v1, s14
; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1]
; GCN-NEXT: v_mov_b32_e32 v1, s22 ; GCN-NEXT: v_mov_b32_e32 v1, s10
; GCN-NEXT: v_cndmask_b32_e64 v6, v0, v1, s[2:3] ; GCN-NEXT: v_cndmask_b32_e64 v6, v0, v1, s[2:3]
; GCN-NEXT: s_lshl_b64 s[2:3], s[16:17], s8 ; GCN-NEXT: s_lshl_b64 s[2:3], s[4:5], s12
; GCN-NEXT: v_mov_b32_e32 v0, s3 ; GCN-NEXT: v_mov_b32_e32 v0, s3
; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v0, vcc ; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v0, vcc
; GCN-NEXT: v_mov_b32_e32 v0, s2 ; GCN-NEXT: v_mov_b32_e32 v0, s2
; GCN-NEXT: s_lshl_b64 s[2:3], s[20:21], s12 ; GCN-NEXT: s_lshl_b64 s[2:3], s[8:9], s16
; GCN-NEXT: v_mov_b32_e32 v4, s3 ; GCN-NEXT: v_mov_b32_e32 v4, s3
; GCN-NEXT: v_cndmask_b32_e64 v5, 0, v4, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v5, 0, v4, s[0:1]
; GCN-NEXT: v_mov_b32_e32 v4, s2 ; GCN-NEXT: v_mov_b32_e32 v4, s2
; GCN-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[0:1]
; GCN-NEXT: v_mov_b32_e32 v9, 0
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; GCN-NEXT: flat_store_dwordx4 v[10:11], v[4:7] ; GCN-NEXT: flat_store_dwordx4 v[10:11], v[4:7]
; GCN-NEXT: flat_store_dwordx4 v[8:9], v[0:3] ; GCN-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
%shift = shl <2 x i128> %lhs, %rhs %shift = shl <2 x i128> %lhs, %rhs
store <2 x i128> %shift, <2 x i128> addrspace(1)* null store <2 x i128> %shift, <2 x i128> addrspace(1)* null
ret void ret void
} }
define amdgpu_kernel void @s_lshr_v2i128_ss(<2 x i128> %lhs, <2 x i128> %rhs) { define amdgpu_kernel void @s_lshr_v2i128_ss(<2 x i128> %lhs, <2 x i128> %rhs) {
; GCN-LABEL: s_lshr_v2i128_ss: ; GCN-LABEL: s_lshr_v2i128_ss:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x8 ; GCN-NEXT: s_load_dwordx16 s[4:19], s[4:5], 0x0
; GCN-NEXT: s_load_dwordx8 s[16:23], s[4:5], 0x0
; GCN-NEXT: v_mov_b32_e32 v10, 16 ; GCN-NEXT: v_mov_b32_e32 v10, 16
; GCN-NEXT: v_mov_b32_e32 v8, 0 ; GCN-NEXT: v_mov_b32_e32 v8, 0
; GCN-NEXT: v_mov_b32_e32 v11, 0 ; GCN-NEXT: v_mov_b32_e32 v11, 0
; GCN-NEXT: v_mov_b32_e32 v9, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_cmp_lt_u64_e64 s[0:1], s[8:9], 64 ; GCN-NEXT: v_cmp_lt_u64_e64 s[0:1], s[12:13], 64
; GCN-NEXT: v_cmp_eq_u64_e64 s[2:3], s[10:11], 0 ; GCN-NEXT: v_cmp_eq_u64_e64 s[2:3], s[14:15], 0
; GCN-NEXT: s_sub_i32 s6, 64, s8 ; GCN-NEXT: s_sub_i32 s22, 64, s12
; GCN-NEXT: s_sub_i32 s4, s8, 64 ; GCN-NEXT: s_sub_i32 s20, s12, 64
; GCN-NEXT: s_lshl_b64 s[6:7], s[18:19], s6 ; GCN-NEXT: s_lshl_b64 s[22:23], s[6:7], s22
; GCN-NEXT: s_lshr_b64 s[24:25], s[16:17], s8 ; GCN-NEXT: s_lshr_b64 s[24:25], s[4:5], s12
; GCN-NEXT: s_lshr_b64 s[4:5], s[18:19], s4 ; GCN-NEXT: s_lshr_b64 s[20:21], s[6:7], s20
; GCN-NEXT: s_or_b64 s[6:7], s[24:25], s[6:7] ; GCN-NEXT: s_or_b64 s[22:23], s[24:25], s[22:23]
; GCN-NEXT: s_and_b64 vcc, s[2:3], s[0:1] ; GCN-NEXT: s_and_b64 vcc, s[2:3], s[0:1]
; GCN-NEXT: s_or_b64 s[0:1], s[8:9], s[10:11] ; GCN-NEXT: s_or_b64 s[0:1], s[12:13], s[14:15]
; GCN-NEXT: v_mov_b32_e32 v0, s5 ; GCN-NEXT: v_mov_b32_e32 v0, s21
; GCN-NEXT: v_mov_b32_e32 v1, s7 ; GCN-NEXT: v_mov_b32_e32 v1, s23
; GCN-NEXT: v_cmp_eq_u64_e64 s[0:1], s[0:1], 0 ; GCN-NEXT: v_cmp_eq_u64_e64 s[0:1], s[0:1], 0
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GCN-NEXT: v_mov_b32_e32 v1, s17 ; GCN-NEXT: v_mov_b32_e32 v1, s5
; GCN-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1]
; GCN-NEXT: v_mov_b32_e32 v0, s4 ; GCN-NEXT: v_mov_b32_e32 v0, s20
; GCN-NEXT: v_mov_b32_e32 v2, s6 ; GCN-NEXT: v_mov_b32_e32 v2, s22
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GCN-NEXT: v_mov_b32_e32 v2, s16 ; GCN-NEXT: v_mov_b32_e32 v2, s4
; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; GCN-NEXT: v_cmp_lt_u64_e64 s[0:1], s[12:13], 64 ; GCN-NEXT: v_cmp_lt_u64_e64 s[0:1], s[16:17], 64
; GCN-NEXT: v_cmp_eq_u64_e64 s[2:3], s[14:15], 0 ; GCN-NEXT: v_cmp_eq_u64_e64 s[2:3], s[18:19], 0
; GCN-NEXT: s_sub_i32 s6, 64, s12 ; GCN-NEXT: s_sub_i32 s13, 64, s16
; GCN-NEXT: s_sub_i32 s4, s12, 64 ; GCN-NEXT: s_sub_i32 s4, s16, 64
; GCN-NEXT: s_lshl_b64 s[6:7], s[22:23], s6 ; GCN-NEXT: s_lshl_b64 s[14:15], s[10:11], s13
; GCN-NEXT: s_lshr_b64 s[10:11], s[20:21], s12 ; GCN-NEXT: s_lshr_b64 s[20:21], s[8:9], s16
; GCN-NEXT: s_lshr_b64 s[4:5], s[22:23], s4 ; GCN-NEXT: s_lshr_b64 s[4:5], s[10:11], s4
; GCN-NEXT: s_or_b64 s[6:7], s[10:11], s[6:7] ; GCN-NEXT: s_or_b64 s[14:15], s[20:21], s[14:15]
; GCN-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1] ; GCN-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]
; GCN-NEXT: s_or_b64 s[2:3], s[12:13], s[14:15] ; GCN-NEXT: s_or_b64 s[2:3], s[16:17], s[18:19]
; GCN-NEXT: v_mov_b32_e32 v2, s5 ; GCN-NEXT: v_mov_b32_e32 v2, s5
; GCN-NEXT: v_mov_b32_e32 v3, s7 ; GCN-NEXT: v_mov_b32_e32 v3, s15
; GCN-NEXT: v_cmp_eq_u64_e64 s[2:3], s[2:3], 0 ; GCN-NEXT: v_cmp_eq_u64_e64 s[2:3], s[2:3], 0
; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
; GCN-NEXT: v_mov_b32_e32 v3, s21 ; GCN-NEXT: v_mov_b32_e32 v3, s9
; GCN-NEXT: v_cndmask_b32_e64 v5, v2, v3, s[2:3] ; GCN-NEXT: v_cndmask_b32_e64 v5, v2, v3, s[2:3]
; GCN-NEXT: v_mov_b32_e32 v2, s4 ; GCN-NEXT: v_mov_b32_e32 v2, s4
; GCN-NEXT: v_mov_b32_e32 v3, s6 ; GCN-NEXT: v_mov_b32_e32 v3, s14
; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
; GCN-NEXT: v_mov_b32_e32 v3, s20 ; GCN-NEXT: v_mov_b32_e32 v3, s8
; GCN-NEXT: v_cndmask_b32_e64 v4, v2, v3, s[2:3] ; GCN-NEXT: v_cndmask_b32_e64 v4, v2, v3, s[2:3]
; GCN-NEXT: s_lshr_b64 s[2:3], s[18:19], s8 ; GCN-NEXT: s_lshr_b64 s[2:3], s[6:7], s12
; GCN-NEXT: v_mov_b32_e32 v2, s3 ; GCN-NEXT: v_mov_b32_e32 v2, s3
; GCN-NEXT: v_cndmask_b32_e32 v3, 0, v2, vcc ; GCN-NEXT: v_cndmask_b32_e32 v3, 0, v2, vcc
; GCN-NEXT: v_mov_b32_e32 v2, s2 ; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: s_lshr_b64 s[2:3], s[22:23], s12 ; GCN-NEXT: s_lshr_b64 s[2:3], s[10:11], s16
; GCN-NEXT: v_mov_b32_e32 v6, s3 ; GCN-NEXT: v_mov_b32_e32 v6, s3
; GCN-NEXT: v_cndmask_b32_e64 v7, 0, v6, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v7, 0, v6, s[0:1]
; GCN-NEXT: v_mov_b32_e32 v6, s2 ; GCN-NEXT: v_mov_b32_e32 v6, s2
; GCN-NEXT: v_cndmask_b32_e64 v6, 0, v6, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v6, 0, v6, s[0:1]
; GCN-NEXT: v_mov_b32_e32 v9, 0
; GCN-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc ; GCN-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
; GCN-NEXT: flat_store_dwordx4 v[10:11], v[4:7] ; GCN-NEXT: flat_store_dwordx4 v[10:11], v[4:7]
; GCN-NEXT: flat_store_dwordx4 v[8:9], v[0:3] ; GCN-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
%shift = lshr <2 x i128> %lhs, %rhs %shift = lshr <2 x i128> %lhs, %rhs
store <2 x i128> %shift, <2 x i128> addrspace(1)* null store <2 x i128> %shift, <2 x i128> addrspace(1)* null
ret void ret void
} }
define amdgpu_kernel void @s_ashr_v2i128_ss(<2 x i128> %lhs, <2 x i128> %rhs) { define amdgpu_kernel void @s_ashr_v2i128_ss(<2 x i128> %lhs, <2 x i128> %rhs) {
; GCN-LABEL: s_ashr_v2i128_ss: ; GCN-LABEL: s_ashr_v2i128_ss:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x8 ; GCN-NEXT: s_load_dwordx16 s[4:19], s[4:5], 0x0
; GCN-NEXT: s_load_dwordx8 s[16:23], s[4:5], 0x0
; GCN-NEXT: v_mov_b32_e32 v10, 16 ; GCN-NEXT: v_mov_b32_e32 v10, 16
; GCN-NEXT: v_mov_b32_e32 v8, 0 ; GCN-NEXT: v_mov_b32_e32 v8, 0
; GCN-NEXT: v_mov_b32_e32 v11, 0 ; GCN-NEXT: v_mov_b32_e32 v11, 0
; GCN-NEXT: v_mov_b32_e32 v9, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_cmp_lt_u64_e64 s[0:1], s[8:9], 64 ; GCN-NEXT: v_cmp_lt_u64_e64 s[0:1], s[12:13], 64
; GCN-NEXT: v_cmp_eq_u64_e64 s[2:3], s[10:11], 0 ; GCN-NEXT: v_cmp_eq_u64_e64 s[2:3], s[14:15], 0
; GCN-NEXT: s_sub_i32 s6, 64, s8 ; GCN-NEXT: s_sub_i32 s22, 64, s12
; GCN-NEXT: s_sub_i32 s4, s8, 64 ; GCN-NEXT: s_sub_i32 s20, s12, 64
; GCN-NEXT: s_lshl_b64 s[6:7], s[18:19], s6 ; GCN-NEXT: s_lshl_b64 s[22:23], s[6:7], s22
; GCN-NEXT: s_lshr_b64 s[24:25], s[16:17], s8 ; GCN-NEXT: s_lshr_b64 s[24:25], s[4:5], s12
; GCN-NEXT: s_ashr_i64 s[4:5], s[18:19], s4 ; GCN-NEXT: s_ashr_i64 s[20:21], s[6:7], s20
; GCN-NEXT: s_or_b64 s[6:7], s[24:25], s[6:7] ; GCN-NEXT: s_or_b64 s[22:23], s[24:25], s[22:23]
; GCN-NEXT: s_and_b64 vcc, s[2:3], s[0:1] ; GCN-NEXT: s_and_b64 vcc, s[2:3], s[0:1]
; GCN-NEXT: s_or_b64 s[0:1], s[8:9], s[10:11] ; GCN-NEXT: s_or_b64 s[0:1], s[12:13], s[14:15]
; GCN-NEXT: v_mov_b32_e32 v0, s5 ; GCN-NEXT: v_mov_b32_e32 v0, s21
; GCN-NEXT: v_mov_b32_e32 v1, s7 ; GCN-NEXT: v_mov_b32_e32 v1, s23
; GCN-NEXT: v_cmp_eq_u64_e64 s[0:1], s[0:1], 0 ; GCN-NEXT: v_cmp_eq_u64_e64 s[0:1], s[0:1], 0
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GCN-NEXT: v_mov_b32_e32 v1, s17 ; GCN-NEXT: v_mov_b32_e32 v1, s5
; GCN-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1]
; GCN-NEXT: v_mov_b32_e32 v0, s4 ; GCN-NEXT: v_mov_b32_e32 v0, s20
; GCN-NEXT: v_mov_b32_e32 v2, s6 ; GCN-NEXT: v_mov_b32_e32 v2, s22
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GCN-NEXT: v_mov_b32_e32 v2, s16 ; GCN-NEXT: v_mov_b32_e32 v2, s4
; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; GCN-NEXT: v_cmp_lt_u64_e64 s[0:1], s[12:13], 64 ; GCN-NEXT: v_cmp_lt_u64_e64 s[0:1], s[16:17], 64
; GCN-NEXT: v_cmp_eq_u64_e64 s[2:3], s[14:15], 0 ; GCN-NEXT: v_cmp_eq_u64_e64 s[2:3], s[18:19], 0
; GCN-NEXT: s_sub_i32 s6, 64, s12 ; GCN-NEXT: s_sub_i32 s13, 64, s16
; GCN-NEXT: s_sub_i32 s4, s12, 64 ; GCN-NEXT: s_sub_i32 s4, s16, 64
; GCN-NEXT: s_lshl_b64 s[6:7], s[22:23], s6 ; GCN-NEXT: s_lshl_b64 s[14:15], s[10:11], s13
; GCN-NEXT: s_lshr_b64 s[10:11], s[20:21], s12 ; GCN-NEXT: s_lshr_b64 s[20:21], s[8:9], s16
; GCN-NEXT: s_ashr_i64 s[4:5], s[22:23], s4 ; GCN-NEXT: s_ashr_i64 s[4:5], s[10:11], s4
; GCN-NEXT: s_or_b64 s[6:7], s[10:11], s[6:7] ; GCN-NEXT: s_or_b64 s[14:15], s[20:21], s[14:15]
; GCN-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1] ; GCN-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]
; GCN-NEXT: s_or_b64 s[2:3], s[12:13], s[14:15] ; GCN-NEXT: s_or_b64 s[2:3], s[16:17], s[18:19]
; GCN-NEXT: v_mov_b32_e32 v2, s5 ; GCN-NEXT: v_mov_b32_e32 v2, s5
; GCN-NEXT: v_mov_b32_e32 v3, s7 ; GCN-NEXT: v_mov_b32_e32 v3, s15
; GCN-NEXT: v_cmp_eq_u64_e64 s[2:3], s[2:3], 0 ; GCN-NEXT: v_cmp_eq_u64_e64 s[2:3], s[2:3], 0
; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
; GCN-NEXT: v_mov_b32_e32 v3, s21 ; GCN-NEXT: v_mov_b32_e32 v3, s9
; GCN-NEXT: v_cndmask_b32_e64 v5, v2, v3, s[2:3] ; GCN-NEXT: v_cndmask_b32_e64 v5, v2, v3, s[2:3]
; GCN-NEXT: v_mov_b32_e32 v2, s4 ; GCN-NEXT: v_mov_b32_e32 v2, s4
; GCN-NEXT: v_mov_b32_e32 v3, s6 ; GCN-NEXT: v_mov_b32_e32 v3, s14
; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
; GCN-NEXT: v_mov_b32_e32 v3, s20 ; GCN-NEXT: v_mov_b32_e32 v3, s8
; GCN-NEXT: v_cndmask_b32_e64 v4, v2, v3, s[2:3] ; GCN-NEXT: v_cndmask_b32_e64 v4, v2, v3, s[2:3]
; GCN-NEXT: s_ashr_i32 s4, s19, 31 ; GCN-NEXT: s_ashr_i32 s4, s7, 31
; GCN-NEXT: s_ashr_i64 s[2:3], s[18:19], s8 ; GCN-NEXT: s_ashr_i64 s[2:3], s[6:7], s12
; GCN-NEXT: v_mov_b32_e32 v2, s4 ; GCN-NEXT: v_mov_b32_e32 v2, s4
; GCN-NEXT: v_mov_b32_e32 v3, s3 ; GCN-NEXT: v_mov_b32_e32 v3, s3
; GCN-NEXT: v_mov_b32_e32 v6, s2 ; GCN-NEXT: v_mov_b32_e32 v6, s2
; GCN-NEXT: s_ashr_i32 s4, s23, 31 ; GCN-NEXT: s_ashr_i32 s4, s11, 31
; GCN-NEXT: s_ashr_i64 s[2:3], s[22:23], s12 ; GCN-NEXT: s_ashr_i64 s[2:3], s[10:11], s16
; GCN-NEXT: v_cndmask_b32_e32 v3, v2, v3, vcc ; GCN-NEXT: v_cndmask_b32_e32 v3, v2, v3, vcc
; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc ; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
; GCN-NEXT: v_mov_b32_e32 v6, s4 ; GCN-NEXT: v_mov_b32_e32 v6, s4
; GCN-NEXT: v_mov_b32_e32 v7, s3 ; GCN-NEXT: v_mov_b32_e32 v7, s3
; GCN-NEXT: v_mov_b32_e32 v12, s2 ; GCN-NEXT: v_mov_b32_e32 v12, s2
; GCN-NEXT: v_cndmask_b32_e64 v7, v6, v7, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v7, v6, v7, s[0:1]
; GCN-NEXT: v_cndmask_b32_e64 v6, v6, v12, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v6, v6, v12, s[0:1]
; GCN-NEXT: v_mov_b32_e32 v9, 0
; GCN-NEXT: flat_store_dwordx4 v[10:11], v[4:7] ; GCN-NEXT: flat_store_dwordx4 v[10:11], v[4:7]
; GCN-NEXT: flat_store_dwordx4 v[8:9], v[0:3] ; GCN-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
%shift = ashr <2 x i128> %lhs, %rhs %shift = ashr <2 x i128> %lhs, %rhs
store <2 x i128> %shift, <2 x i128> addrspace(1)* null store <2 x i128> %shift, <2 x i128> addrspace(1)* null
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/shl.ll

Show All 25 Lines
; SI-NEXT: v_lshl_b32_e32 v0, v0, v2 ; SI-NEXT: v_lshl_b32_e32 v0, v0, v2
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: shl_v2i32: ; VI-LABEL: shl_v2i32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 ; VI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
; VI-NEXT: s_load_dwordx2 s[6:7], s[2:3], 0x8
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_lshl_b32 s5, s5, s7 ; VI-NEXT: s_lshl_b32 s5, s5, s7
; VI-NEXT: s_lshl_b32 s4, s4, s6 ; VI-NEXT: s_lshl_b32 s4, s4, s6
; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5 ; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; EG-LABEL: shl_v2i32: ; EG-LABEL: shl_v2i32:
; EG: ; %bb.0: ; EG: ; %bb.0:
; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 1 @6 ; EG-NEXT: TEX 0 @6
; EG-NEXT: ALU 3, @11, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
; EG-NEXT: CF_END ; EG-NEXT: CF_END
; EG-NEXT: PAD ; EG-NEXT: PAD
; EG-NEXT: Fetch clause starting at 6: ; EG-NEXT: Fetch clause starting at 6:
; EG-NEXT: VTX_READ_64 T1.XY, T0.X, 8, #1 ; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1 ; EG-NEXT: ALU clause starting at 8:
; EG-NEXT: ALU clause starting at 10:
; EG-NEXT: MOV * T0.X, KC0[2].Z, ; EG-NEXT: MOV * T0.X, KC0[2].Z,
; EG-NEXT: ALU clause starting at 11: ; EG-NEXT: ALU clause starting at 9:
; EG-NEXT: LSHL * T0.Y, T0.Y, T1.Y, ; EG-NEXT: LSHL * T0.Y, T0.Y, T0.W,
; EG-NEXT: LSHL T0.X, T0.X, T1.X, ; EG-NEXT: LSHL T0.X, T0.X, T0.Z,
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1 %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
%a = load <2 x i32>, <2 x i32> addrspace(1)* %in %a = load <2 x i32>, <2 x i32> addrspace(1)* %in
%b = load <2 x i32>, <2 x i32> addrspace(1)* %b_ptr %b = load <2 x i32>, <2 x i32> addrspace(1)* %b_ptr
%result = shl <2 x i32> %a, %b %result = shl <2 x i32> %a, %b
store <2 x i32> %result, <2 x i32> addrspace(1)* %out store <2 x i32> %result, <2 x i32> addrspace(1)* %out
ret void ret void
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; SI-NEXT: v_lshl_b32_e32 v2, v2, v6 ; SI-NEXT: v_lshl_b32_e32 v2, v2, v6
; SI-NEXT: v_lshl_b32_e32 v1, v1, v5 ; SI-NEXT: v_lshl_b32_e32 v1, v1, v5
; SI-NEXT: v_lshl_b32_e32 v0, v0, v4 ; SI-NEXT: v_lshl_b32_e32 v0, v0, v4
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: shl_v4i32: ; VI-LABEL: shl_v4i32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
; VI-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x10
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_lshl_b32 s7, s7, s11 ; VI-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
; VI-NEXT: s_lshl_b32 s6, s6, s10 ; VI-NEXT: s_mov_b32 s11, 0xf000
; VI-NEXT: s_lshl_b32 s5, s5, s9 ; VI-NEXT: s_mov_b32 s10, -1
; VI-NEXT: s_lshl_b32 s4, s4, s8 ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: s_lshl_b32 s3, s3, s7
; VI-NEXT: v_mov_b32_e32 v1, s5 ; VI-NEXT: s_lshl_b32 s2, s2, s6
; VI-NEXT: v_mov_b32_e32 v2, s6 ; VI-NEXT: s_lshl_b32 s1, s1, s5
; VI-NEXT: v_mov_b32_e32 v3, s7 ; VI-NEXT: s_lshl_b32 s0, s0, s4
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; EG-LABEL: shl_v4i32: ; EG-LABEL: shl_v4i32:
; EG: ; %bb.0: ; EG: ; %bb.0:
; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 1 @6 ; EG-NEXT: TEX 1 @6
; EG-NEXT: ALU 5, @11, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 5, @11, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
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} }
define amdgpu_kernel void @shl_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) { define amdgpu_kernel void @shl_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) {
; SI-LABEL: shl_v4i16: ; SI-LABEL: shl_v4i16:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000 ; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, 0 ; SI-NEXT: s_mov_b32 s6, 0
; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 ; SI-NEXT: v_lshlrev_b32_e32 v4, 3, v0
; SI-NEXT: v_mov_b32_e32 v1, 0 ; SI-NEXT: v_mov_b32_e32 v5, 0
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b64 s[4:5], s[2:3] ; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 ; SI-NEXT: buffer_load_dwordx4 v[0:3], v[4:5], s[4:7], 0 addr64
; SI-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[4:7], 0 addr64 offset:8
; SI-NEXT: s_mov_b32 s4, 0xffff ; SI-NEXT: s_mov_b32 s4, 0xffff
; SI-NEXT: s_mov_b64 s[2:3], s[6:7] ; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v3
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v4 ; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v0
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v5 ; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v1
; SI-NEXT: v_lshlrev_b32_e32 v3, v5, v3 ; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; SI-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v3
; SI-NEXT: v_lshlrev_b32_e32 v4, v9, v7 ; SI-NEXT: v_lshlrev_b32_e32 v1, v3, v1
; SI-NEXT: v_lshlrev_b32_e32 v5, v8, v6 ; SI-NEXT: v_lshlrev_b32_e32 v0, v2, v0
; SI-NEXT: v_and_b32_e32 v3, s4, v3 ; SI-NEXT: v_lshlrev_b32_e32 v2, v9, v7
; SI-NEXT: v_and_b32_e32 v2, s4, v2 ; SI-NEXT: v_lshlrev_b32_e32 v3, v8, v6
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; SI-NEXT: v_and_b32_e32 v1, s4, v1
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5 ; SI-NEXT: v_and_b32_e32 v0, s4, v0
; SI-NEXT: v_or_b32_e32 v3, v3, v4 ; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_or_b32_e32 v2, v2, v5 ; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 ; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v0, v3
; SI-NEXT: buffer_store_dwordx2 v[0:1], v[4:5], s[0:3], 0 addr64
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: shl_v4i16: ; VI-LABEL: shl_v4i16:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v4, 3, v0 ; VI-NEXT: v_lshlrev_b32_e32 v4, 3, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0 ; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; VI-NEXT: flat_load_dwordx2 v[2:3], v[2:3]
; VI-NEXT: v_mov_b32_e32 v5, s1 ; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_add_u32_e32 v4, vcc, s0, v4 ; VI-NEXT: v_add_u32_e32 v4, vcc, s0, v4
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshlrev_b16_e32 v6, v3, v1 ; VI-NEXT: v_lshlrev_b16_e32 v6, v3, v1
; VI-NEXT: v_lshlrev_b16_sdwa v1, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-NEXT: v_lshlrev_b16_sdwa v1, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b16_e32 v3, v2, v0 ; VI-NEXT: v_lshlrev_b16_e32 v3, v2, v0
; VI-NEXT: v_lshlrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-NEXT: v_lshlrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-NEXT: v_or_b32_e32 v1, v6, v1 ; VI-NEXT: v_or_b32_e32 v1, v6, v1
; VI-NEXT: v_or_b32_e32 v0, v3, v0 ; VI-NEXT: v_or_b32_e32 v0, v3, v0
; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1] ; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; EG-LABEL: shl_v4i16: ; EG-LABEL: shl_v4i16:
; EG: ; %bb.0: ; EG: ; %bb.0:
; EG-NEXT: ALU 2, @12, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @8 ; EG-NEXT: TEX 0 @6
; EG-NEXT: ALU 3, @15, KC0[], KC1[] ; EG-NEXT: ALU 53, @11, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @10
; EG-NEXT: ALU 49, @19, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T10.XY, T0.X, 1 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T10.XY, T0.X, 1
; EG-NEXT: CF_END ; EG-NEXT: CF_END
; EG-NEXT: PAD ; EG-NEXT: PAD
; EG-NEXT: Fetch clause starting at 8: ; EG-NEXT: Fetch clause starting at 6:
; EG-NEXT: VTX_READ_64 T10.XY, T0.X, 0, #1 ; EG-NEXT: VTX_READ_128 T10.XYZW, T0.X, 0, #1
; EG-NEXT: Fetch clause starting at 10: ; EG-NEXT: ALU clause starting at 8:
; EG-NEXT: VTX_READ_64 T10.XY, T0.X, 8, #1
; EG-NEXT: ALU clause starting at 12:
; EG-NEXT: LSHL * T0.W, T0.X, literal.x, ; EG-NEXT: LSHL * T0.W, T0.X, literal.x,
; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W, ; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,
; EG-NEXT: ALU clause starting at 15: ; EG-NEXT: ALU clause starting at 11:
; EG-NEXT: MOV T4.X, T10.X, ; EG-NEXT: MOV T4.X, T10.X,
; EG-NEXT: MOV * T5.X, T10.Y, ; EG-NEXT: MOV * T5.X, T10.Y,
; EG-NEXT: MOV T0.Y, PV.X, ; EG-NEXT: MOV T0.X, PV.X,
; EG-NEXT: MOV * T0.Z, PS, ; EG-NEXT: MOV T0.Y, PS,
; EG-NEXT: ALU clause starting at 19: ; EG-NEXT: MOV * T2.X, T10.Z,
; EG-NEXT: MOV T2.X, T10.X, ; EG-NEXT: MOV T3.X, T10.W,
; EG-NEXT: MOV * T3.X, T10.Y, ; EG-NEXT: MOV * T0.Z, T6.X,
; EG-NEXT: MOV T0.X, T6.X, ; EG-NEXT: MOV * T1.Y, T2.X,
; EG-NEXT: MOV * T1.Y, PV.X,
; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, ; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
; EG-NEXT: AND_INT * T2.W, T0.Y, literal.x, ; EG-NEXT: AND_INT * T2.W, T0.X, literal.x,
; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) ; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
; EG-NEXT: LSHL * T1.W, PS, PV.W, ; EG-NEXT: LSHL * T1.W, PS, PV.W,
; EG-NEXT: AND_INT T1.W, PV.W, literal.x, ; EG-NEXT: AND_INT T1.W, PV.W, literal.x,
; EG-NEXT: AND_INT * T2.W, T0.X, literal.y, ; EG-NEXT: AND_INT * T2.W, T0.Z, literal.y,
; EG-NEXT: 65535(9.183409e-41), -65536(nan) ; EG-NEXT: 65535(9.183409e-41), -65536(nan)
; EG-NEXT: OR_INT * T1.W, PS, PV.W, ; EG-NEXT: OR_INT * T1.W, PS, PV.W,
; EG-NEXT: MOV T0.X, T3.X, ; EG-NEXT: MOV * T0.Z, T3.X,
; EG-NEXT: MOV * T6.X, PV.W, ; EG-NEXT: MOV * T6.X, T1.W,
; EG-NEXT: MOV T1.Z, PS, ; EG-NEXT: MOV T1.Z, PV.X,
; EG-NEXT: LSHR T1.W, T1.Y, literal.x, ; EG-NEXT: LSHR T1.W, T1.Y, literal.x,
; EG-NEXT: LSHR * T2.W, T0.Y, literal.x, ; EG-NEXT: LSHR * T2.W, T0.X, literal.x,
; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
; EG-NEXT: LSHL T1.W, PS, PV.W, ; EG-NEXT: LSHL T1.W, PS, PV.W,
; EG-NEXT: AND_INT * T2.W, PV.Z, literal.x, ; EG-NEXT: AND_INT * T2.W, PV.Z, literal.x,
; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) ; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
; EG-NEXT: LSHL * T1.W, PV.W, literal.x, ; EG-NEXT: LSHL * T1.W, PV.W, literal.x,
; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
; EG-NEXT: OR_INT * T1.W, T2.W, PV.W, ; EG-NEXT: OR_INT * T1.W, T2.W, PV.W,
; EG-NEXT: MOV T6.X, PV.W, ; EG-NEXT: MOV T6.X, PV.W,
; EG-NEXT: MOV T0.Y, T7.X, ; EG-NEXT: MOV * T0.X, T7.X,
; EG-NEXT: AND_INT T1.W, T0.X, literal.x, BS:VEC_120/SCL_212 ; EG-NEXT: AND_INT T1.W, T0.Z, literal.x,
; EG-NEXT: AND_INT * T2.W, T0.Z, literal.x, ; EG-NEXT: AND_INT * T2.W, T0.Y, literal.x,
; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) ; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
; EG-NEXT: LSHL T1.W, PS, PV.W, ; EG-NEXT: LSHL T1.W, PS, PV.W,
; EG-NEXT: AND_INT * T2.W, PV.Y, literal.x, ; EG-NEXT: AND_INT * T2.W, T0.X, literal.x,
; EG-NEXT: -65536(nan), 0(0.000000e+00) ; EG-NEXT: -65536(nan), 0(0.000000e+00)
; EG-NEXT: AND_INT * T1.W, PV.W, literal.x, ; EG-NEXT: AND_INT * T1.W, PV.W, literal.x,
; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) ; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
; EG-NEXT: OR_INT * T1.W, T2.W, PV.W, ; EG-NEXT: OR_INT * T1.W, T2.W, PV.W,
; EG-NEXT: MOV * T7.X, PV.W, ; EG-NEXT: MOV * T7.X, PV.W,
; EG-NEXT: MOV T0.Y, PV.X, ; EG-NEXT: MOV T0.X, PV.X,
; EG-NEXT: LSHR T1.W, T0.X, literal.x, ; EG-NEXT: LSHR T1.W, T0.Z, literal.x,
; EG-NEXT: LSHR * T2.W, T0.Z, literal.x, ; EG-NEXT: LSHR * T2.W, T0.Y, literal.x,
; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
; EG-NEXT: LSHL * T1.W, PS, PV.W, ; EG-NEXT: LSHL * T1.W, PS, PV.W,
; EG-NEXT: AND_INT T0.Z, T0.Y, literal.x, ; EG-NEXT: AND_INT T0.Z, T0.X, literal.x,
; EG-NEXT: LSHL T1.W, PV.W, literal.y, ; EG-NEXT: LSHL T1.W, PV.W, literal.y,
; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W, ; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W,
; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) ; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44)
; EG-NEXT: LSHR T0.X, PS, literal.x, ; EG-NEXT: LSHR T0.X, PS, literal.x,
; EG-NEXT: OR_INT * T10.Y, PV.Z, PV.W, ; EG-NEXT: OR_INT * T10.Y, PV.Z, PV.W,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
; EG-NEXT: MOV T7.X, PV.Y, ; EG-NEXT: MOV T7.X, PV.Y,
; EG-NEXT: MOV * T10.X, T6.X, ; EG-NEXT: MOV * T10.X, T6.X,
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; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshl_b64 v[2:3], v[2:3], v6 ; SI-NEXT: v_lshl_b64 v[2:3], v[2:3], v6
; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], v4 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], v4
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: shl_v2i64: ; VI-LABEL: shl_v2i64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0 ; VI-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
; VI-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x10 ; VI-NEXT: s_mov_b32 s11, 0xf000
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s10, -1
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_lshl_b64 s[6:7], s[6:7], s10 ; VI-NEXT: s_lshl_b64 s[2:3], s[2:3], s6
; VI-NEXT: s_lshl_b64 s[4:5], s[4:5], s8 ; VI-NEXT: s_lshl_b64 s[0:1], s[0:1], s4
; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s5 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v2, s6 ; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s7 ; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; EG-LABEL: shl_v2i64: ; EG-LABEL: shl_v2i64:
; EG: ; %bb.0: ; EG: ; %bb.0:
; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 1 @6 ; EG-NEXT: TEX 1 @6
; EG-NEXT: ALU 22, @11, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 22, @11, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.XYZW, T0.X, 1 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.XYZW, T0.X, 1
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; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
; SI-NEXT: buffer_store_dwordx4 v[7:10], off, s[0:3], 0 ; SI-NEXT: buffer_store_dwordx4 v[7:10], off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: shl_v4i64: ; VI-LABEL: shl_v4i64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[16:19], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[16:19], s[0:1], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_load_dwordx8 s[0:7], s[18:19], 0x0 ; VI-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
; VI-NEXT: s_load_dwordx8 s[8:15], s[18:19], 0x20
; VI-NEXT: s_mov_b32 s19, 0xf000 ; VI-NEXT: s_mov_b32 s19, 0xf000
; VI-NEXT: s_mov_b32 s18, -1 ; VI-NEXT: s_mov_b32 s18, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_lshl_b64 s[6:7], s[6:7], s14 ; VI-NEXT: s_lshl_b64 s[6:7], s[6:7], s14
; VI-NEXT: s_lshl_b64 s[4:5], s[4:5], s12 ; VI-NEXT: s_lshl_b64 s[4:5], s[4:5], s12
; VI-NEXT: s_lshl_b64 s[2:3], s[2:3], s10 ; VI-NEXT: s_lshl_b64 s[2:3], s[2:3], s10
; VI-NEXT: s_lshl_b64 s[0:1], s[0:1], s8 ; VI-NEXT: s_lshl_b64 s[0:1], s[0:1], s8
; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v0, s4
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llvm/test/CodeGen/AMDGPU/shl.v2i16.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX9 %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX9 %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=VI %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=VI %s
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=CI %s ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=CI %s
; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX10 %s ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX10 %s
define amdgpu_kernel void @s_shl_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %lhs, <2 x i16> %rhs) #0 { define amdgpu_kernel void @s_shl_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %lhs, <2 x i16> %rhs) #0 {
; GFX9-LABEL: s_shl_v2i16: ; GFX9-LABEL: s_shl_v2i16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dword s2, s[0:1], 0x2c ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
; GFX9-NEXT: s_load_dword s3, s[0:1], 0x30
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; GFX9-NEXT: s_mov_b32 s7, 0xf000 ; GFX9-NEXT: s_mov_b32 s7, 0xf000
; GFX9-NEXT: s_mov_b32 s6, -1 ; GFX9-NEXT: s_mov_b32 s6, -1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s2 ; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_pk_lshlrev_b16 v0, s3, v0 ; GFX9-NEXT: v_pk_lshlrev_b16 v0, s3, v0
; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: s_shl_v2i16: ; VI-LABEL: s_shl_v2i16:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c
; VI-NEXT: s_load_dword s2, s[0:1], 0x2c ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; VI-NEXT: s_load_dword s0, s[0:1], 0x30 ; VI-NEXT: s_mov_b32 s6, 0xffff
; VI-NEXT: s_mov_b32 s1, 0xffff ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s7, 0xf000 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_mov_b32 s6, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_and_b32 s3, s2, s1 ; VI-NEXT: s_and_b32 s7, s4, s6
; VI-NEXT: s_lshr_b32 s2, s2, 16 ; VI-NEXT: s_lshr_b32 s4, s4, 16
; VI-NEXT: s_lshr_b32 s8, s0, 16 ; VI-NEXT: s_lshr_b32 s8, s5, 16
; VI-NEXT: s_lshl_b32 s2, s2, s8 ; VI-NEXT: s_lshl_b32 s4, s4, s8
; VI-NEXT: s_lshl_b32 s0, s3, s0 ; VI-NEXT: s_lshl_b32 s5, s7, s5
; VI-NEXT: s_lshl_b32 s2, s2, 16 ; VI-NEXT: s_lshl_b32 s4, s4, 16
; VI-NEXT: s_and_b32 s0, s0, s1 ; VI-NEXT: s_and_b32 s5, s5, s6
; VI-NEXT: s_or_b32 s0, s0, s2 ; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: v_mov_b32_e32 v0, s0 ; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; CI-LABEL: s_shl_v2i16: ; CI-LABEL: s_shl_v2i16:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dword s4, s[0:1], 0xb ; CI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb
; CI-NEXT: s_load_dword s5, s[0:1], 0xc
; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; CI-NEXT: s_mov_b32 s3, 0xf000 ; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, -1 ; CI-NEXT: s_mov_b32 s2, -1
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_lshr_b32 s6, s4, 16 ; CI-NEXT: s_lshr_b32 s6, s4, 16
; CI-NEXT: s_lshr_b32 s7, s5, 16 ; CI-NEXT: s_lshr_b32 s7, s5, 16
; CI-NEXT: s_lshl_b32 s6, s6, s7 ; CI-NEXT: s_lshl_b32 s6, s6, s7
; CI-NEXT: s_lshl_b32 s4, s4, s5 ; CI-NEXT: s_lshl_b32 s4, s4, s5
; CI-NEXT: s_lshl_b32 s6, s6, 16 ; CI-NEXT: s_lshl_b32 s6, s6, 16
; CI-NEXT: s_and_b32 s4, s4, 0xffff ; CI-NEXT: s_and_b32 s4, s4, 0xffff
; CI-NEXT: s_or_b32 s4, s4, s6 ; CI-NEXT: s_or_b32 s4, s4, s6
; CI-NEXT: v_mov_b32_e32 v0, s4 ; CI-NEXT: v_mov_b32_e32 v0, s4
; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; GFX10-LABEL: s_shl_v2i16: ; GFX10-LABEL: s_shl_v2i16:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_clause 0x2 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dword s2, s[0:1], 0x2c ; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
; GFX10-NEXT: s_load_dword s3, s[0:1], 0x30
; GFX10-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; GFX10-NEXT: s_mov_b32 s7, 0x31016000 ; GFX10-NEXT: s_mov_b32 s7, 0x31016000
; GFX10-NEXT: s_mov_b32 s6, -1 ; GFX10-NEXT: s_mov_b32 s6, -1
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_pk_lshlrev_b16 v0, s3, s2 ; GFX10-NEXT: v_pk_lshlrev_b16 v0, s3, s2
; GFX10-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GFX10-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%result = shl <2 x i16> %lhs, %rhs %result = shl <2 x i16> %lhs, %rhs
store <2 x i16> %result, <2 x i16> addrspace(1)* %out store <2 x i16> %result, <2 x i16> addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @v_shl_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { define amdgpu_kernel void @v_shl_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 {
; GFX9-LABEL: v_shl_v2i16: ; GFX9-LABEL: v_shl_v2i16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dword v1, v0, s[2:3] ; GFX9-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3]
; GFX9-NEXT: global_load_dword v2, v0, s[2:3] offset:4
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_pk_lshlrev_b16 v1, v2, v1 ; GFX9-NEXT: v_pk_lshlrev_b16 v0, v1, v0
; GFX9-NEXT: global_store_dword v0, v1, s[0:1] ; GFX9-NEXT: global_store_dword v2, v0, s[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: v_shl_v2i16: ; VI-LABEL: v_shl_v2i16:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v5, v[0:1]
; VI-NEXT: flat_load_dword v2, v[2:3]
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v4
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshlrev_b16_e32 v3, v2, v5 ; VI-NEXT: v_lshlrev_b16_e32 v4, v1, v0
; VI-NEXT: v_lshlrev_b16_sdwa v2, v2, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-NEXT: v_lshlrev_b16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-NEXT: v_or_b32_e32 v2, v3, v2 ; VI-NEXT: v_or_b32_e32 v0, v4, v0
; VI-NEXT: flat_store_dword v[0:1], v2 ; VI-NEXT: flat_store_dword v[2:3], v0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; CI-LABEL: v_shl_v2i16: ; CI-LABEL: v_shl_v2i16:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; CI-NEXT: s_mov_b32 s7, 0xf000 ; CI-NEXT: s_mov_b32 s7, 0xf000
; CI-NEXT: s_mov_b32 s6, 0 ; CI-NEXT: s_mov_b32 s6, 0
; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; CI-NEXT: v_mov_b32_e32 v1, 0 ; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_mov_b64 s[4:5], s[2:3] ; CI-NEXT: s_mov_b64 s[4:5], s[2:3]
; CI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 ; CI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
; CI-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 offset:4
; CI-NEXT: s_mov_b64 s[2:3], s[6:7] ; CI-NEXT: s_mov_b64 s[2:3], s[6:7]
; CI-NEXT: s_waitcnt vmcnt(1)
; CI-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; CI-NEXT: s_waitcnt vmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; CI-NEXT: v_lshrrev_b32_e32 v5, 16, v3 ; CI-NEXT: v_lshrrev_b32_e32 v5, 16, v3
; CI-NEXT: v_lshlrev_b32_e32 v2, v3, v2 ; CI-NEXT: v_lshlrev_b32_e32 v2, v3, v2
; CI-NEXT: v_lshlrev_b32_e32 v3, v5, v4 ; CI-NEXT: v_lshlrev_b32_e32 v3, v5, v4
; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; CI-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; CI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; CI-NEXT: v_or_b32_e32 v2, v2, v3 ; CI-NEXT: v_or_b32_e32 v2, v2, v3
; CI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 ; CI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; GFX10-LABEL: v_shl_v2i16: ; GFX10-LABEL: v_shl_v2i16:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3]
; GFX10-NEXT: global_load_dword v1, v0, s[2:3]
; GFX10-NEXT: global_load_dword v2, v0, s[2:3] offset:4
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_pk_lshlrev_b16 v1, v2, v1 ; GFX10-NEXT: v_pk_lshlrev_b16 v0, v1, v0
; GFX10-NEXT: global_store_dword v0, v1, s[0:1] ; GFX10-NEXT: global_store_dword v2, v0, s[0:1]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
%out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
%b_ptr = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %in.gep, i32 1 %b_ptr = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %in.gep, i32 1
%a = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep %a = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
%b = load <2 x i16>, <2 x i16> addrspace(1)* %b_ptr %b = load <2 x i16>, <2 x i16> addrspace(1)* %b_ptr
▲ Show 20 Lines • Show All 303 Lines • ▼ Show 20 Lines
} }
define amdgpu_kernel void @v_shl_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) #0 { define amdgpu_kernel void @v_shl_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) #0 {
; GFX9-LABEL: v_shl_v4i16: ; GFX9-LABEL: v_shl_v4i16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 3, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v4, 3, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dwordx2 v[0:1], v4, s[2:3] ; GFX9-NEXT: global_load_dwordx4 v[0:3], v4, s[2:3]
; GFX9-NEXT: global_load_dwordx2 v[2:3], v4, s[2:3] offset:8
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_pk_lshlrev_b16 v1, v3, v1 ; GFX9-NEXT: v_pk_lshlrev_b16 v1, v3, v1
; GFX9-NEXT: v_pk_lshlrev_b16 v0, v2, v0 ; GFX9-NEXT: v_pk_lshlrev_b16 v0, v2, v0
; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1] ; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: v_shl_v4i16: ; VI-LABEL: v_shl_v4i16:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v4, 3, v0 ; VI-NEXT: v_lshlrev_b32_e32 v4, 3, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0 ; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; VI-NEXT: flat_load_dwordx2 v[2:3], v[2:3]
; VI-NEXT: v_mov_b32_e32 v5, s1 ; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_add_u32_e32 v4, vcc, s0, v4 ; VI-NEXT: v_add_u32_e32 v4, vcc, s0, v4
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshlrev_b16_e32 v6, v3, v1 ; VI-NEXT: v_lshlrev_b16_e32 v6, v3, v1
; VI-NEXT: v_lshlrev_b16_sdwa v1, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-NEXT: v_lshlrev_b16_sdwa v1, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b16_e32 v3, v2, v0 ; VI-NEXT: v_lshlrev_b16_e32 v3, v2, v0
; VI-NEXT: v_lshlrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-NEXT: v_lshlrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-NEXT: v_or_b32_e32 v1, v6, v1 ; VI-NEXT: v_or_b32_e32 v1, v6, v1
; VI-NEXT: v_or_b32_e32 v0, v3, v0 ; VI-NEXT: v_or_b32_e32 v0, v3, v0
; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1] ; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; CI-LABEL: v_shl_v4i16: ; CI-LABEL: v_shl_v4i16:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; CI-NEXT: s_mov_b32 s7, 0xf000 ; CI-NEXT: s_mov_b32 s7, 0xf000
; CI-NEXT: s_mov_b32 s6, 0 ; CI-NEXT: s_mov_b32 s6, 0
; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 ; CI-NEXT: v_lshlrev_b32_e32 v4, 3, v0
; CI-NEXT: v_mov_b32_e32 v1, 0 ; CI-NEXT: v_mov_b32_e32 v5, 0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_mov_b64 s[4:5], s[2:3] ; CI-NEXT: s_mov_b64 s[4:5], s[2:3]
; CI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 ; CI-NEXT: buffer_load_dwordx4 v[0:3], v[4:5], s[4:7], 0 addr64
; CI-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[4:7], 0 addr64 offset:8
; CI-NEXT: s_mov_b32 s4, 0xffff ; CI-NEXT: s_mov_b32 s4, 0xffff
; CI-NEXT: s_mov_b64 s[2:3], s[6:7] ; CI-NEXT: s_mov_b64 s[2:3], s[6:7]
; CI-NEXT: s_waitcnt vmcnt(1)
; CI-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; CI-NEXT: v_lshrrev_b32_e32 v7, 16, v3
; CI-NEXT: s_waitcnt vmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_lshrrev_b32_e32 v8, 16, v4 ; CI-NEXT: v_lshrrev_b32_e32 v6, 16, v0
; CI-NEXT: v_lshrrev_b32_e32 v9, 16, v5 ; CI-NEXT: v_lshrrev_b32_e32 v7, 16, v1
; CI-NEXT: v_lshlrev_b32_e32 v3, v5, v3 ; CI-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; CI-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; CI-NEXT: v_lshrrev_b32_e32 v9, 16, v3
; CI-NEXT: v_lshlrev_b32_e32 v4, v9, v7 ; CI-NEXT: v_lshlrev_b32_e32 v1, v3, v1
; CI-NEXT: v_lshlrev_b32_e32 v5, v8, v6 ; CI-NEXT: v_lshlrev_b32_e32 v0, v2, v0
; CI-NEXT: v_and_b32_e32 v3, s4, v3 ; CI-NEXT: v_lshlrev_b32_e32 v2, v9, v7
; CI-NEXT: v_and_b32_e32 v2, s4, v2 ; CI-NEXT: v_lshlrev_b32_e32 v3, v8, v6
; CI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; CI-NEXT: v_and_b32_e32 v1, s4, v1
; CI-NEXT: v_lshlrev_b32_e32 v5, 16, v5 ; CI-NEXT: v_and_b32_e32 v0, s4, v0
; CI-NEXT: v_or_b32_e32 v3, v3, v4 ; CI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; CI-NEXT: v_or_b32_e32 v2, v2, v5 ; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; CI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 ; CI-NEXT: v_or_b32_e32 v1, v1, v2
; CI-NEXT: v_or_b32_e32 v0, v0, v3
; CI-NEXT: buffer_store_dwordx2 v[0:1], v[4:5], s[0:3], 0 addr64
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; GFX10-LABEL: v_shl_v4i16: ; GFX10-LABEL: v_shl_v4i16:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-NEXT: v_lshlrev_b32_e32 v4, 3, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v4, 3, v0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: global_load_dwordx4 v[0:3], v4, s[2:3]
; GFX10-NEXT: global_load_dwordx2 v[0:1], v4, s[2:3]
; GFX10-NEXT: global_load_dwordx2 v[2:3], v4, s[2:3] offset:8
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_pk_lshlrev_b16 v1, v3, v1 ; GFX10-NEXT: v_pk_lshlrev_b16 v1, v3, v1
; GFX10-NEXT: v_pk_lshlrev_b16 v0, v2, v0 ; GFX10-NEXT: v_pk_lshlrev_b16 v0, v2, v0
; GFX10-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1] ; GFX10-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%in.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %in, i64 %tid.ext %in.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %in, i64 %tid.ext
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llvm/test/CodeGen/AMDGPU/sra.ll

Show All 40 Lines
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_ashrrev_i32_e32 v1, v3, v1 ; VI-NEXT: v_ashrrev_i32_e32 v1, v3, v1
; VI-NEXT: v_ashrrev_i32_e32 v0, v2, v0 ; VI-NEXT: v_ashrrev_i32_e32 v0, v2, v0
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; EG-LABEL: ashr_v2i32: ; EG-LABEL: ashr_v2i32:
; EG: ; %bb.0: ; EG: ; %bb.0:
; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 1 @6 ; EG-NEXT: TEX 0 @6
; EG-NEXT: ALU 3, @11, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
; EG-NEXT: CF_END ; EG-NEXT: CF_END
; EG-NEXT: PAD ; EG-NEXT: PAD
; EG-NEXT: Fetch clause starting at 6: ; EG-NEXT: Fetch clause starting at 6:
; EG-NEXT: VTX_READ_64 T1.XY, T0.X, 8, #1 ; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1 ; EG-NEXT: ALU clause starting at 8:
; EG-NEXT: ALU clause starting at 10:
; EG-NEXT: MOV * T0.X, KC0[2].Z, ; EG-NEXT: MOV * T0.X, KC0[2].Z,
; EG-NEXT: ALU clause starting at 11: ; EG-NEXT: ALU clause starting at 9:
; EG-NEXT: ASHR * T0.Y, T0.Y, T1.Y, ; EG-NEXT: ASHR * T0.Y, T0.Y, T0.W,
; EG-NEXT: ASHR T0.X, T0.X, T1.X, ; EG-NEXT: ASHR T0.X, T0.X, T0.Z,
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1 %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
%a = load <2 x i32>, <2 x i32> addrspace(1)* %in %a = load <2 x i32>, <2 x i32> addrspace(1)* %in
%b = load <2 x i32>, <2 x i32> addrspace(1)* %b_ptr %b = load <2 x i32>, <2 x i32> addrspace(1)* %b_ptr
%result = ashr <2 x i32> %a, %b %result = ashr <2 x i32> %a, %b
store <2 x i32> %result, <2 x i32> addrspace(1)* %out store <2 x i32> %result, <2 x i32> addrspace(1)* %out
ret void ret void
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; VI-NEXT: v_ashrrev_i32_sdwa v2, sext(v1), sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0 ; VI-NEXT: v_ashrrev_i32_sdwa v2, sext(v1), sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0
; VI-NEXT: v_ashrrev_i32_sdwa v0, sext(v1), sext(v0) dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-NEXT: v_ashrrev_i32_sdwa v0, sext(v1), sext(v0) dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; EG-LABEL: ashr_v2i16: ; EG-LABEL: ashr_v2i16:
; EG: ; %bb.0: ; EG: ; %bb.0:
; EG-NEXT: ALU 1, @10, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 1 @6 ; EG-NEXT: TEX 0 @6
; EG-NEXT: ALU 14, @12, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 14, @9, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.X, T7.X, 1 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.X, T7.X, 1
; EG-NEXT: CF_END ; EG-NEXT: CF_END
; EG-NEXT: PAD ; EG-NEXT: PAD
; EG-NEXT: Fetch clause starting at 6: ; EG-NEXT: Fetch clause starting at 6:
; EG-NEXT: VTX_READ_32 T7.X, T7.X, 0, #1 ; EG-NEXT: VTX_READ_64 T6.XY, T6.X, 0, #1
; EG-NEXT: VTX_READ_32 T6.X, T6.X, 4, #1 ; EG-NEXT: ALU clause starting at 8:
; EG-NEXT: ALU clause starting at 10:
; EG-NEXT: MOV * T6.X, KC0[2].Z, ; EG-NEXT: MOV * T6.X, KC0[2].Z,
; EG-NEXT: MOV * T7.X, PV.X, ; EG-NEXT: ALU clause starting at 9:
; EG-NEXT: ALU clause starting at 12: ; EG-NEXT: LSHR * T0.W, T6.X, literal.x,
; EG-NEXT: LSHR * T0.W, T7.X, literal.x,
; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
; EG-NEXT: BFE_INT T0.Y, PV.W, 0.0, literal.x, ; EG-NEXT: BFE_INT T0.Y, PV.W, 0.0, literal.x,
; EG-NEXT: LSHR T0.Z, T6.X, literal.x, ; EG-NEXT: LSHR T0.Z, T6.Y, literal.x,
; EG-NEXT: BFE_INT T0.W, T7.X, 0.0, literal.x, BS:VEC_120/SCL_212 ; EG-NEXT: BFE_INT T0.W, T6.X, 0.0, literal.x,
; EG-NEXT: AND_INT * T1.W, T6.X, literal.y, ; EG-NEXT: AND_INT * T1.W, T6.Y, literal.y,
; EG-NEXT: 16(2.242078e-44), 65535(9.183409e-41) ; EG-NEXT: 16(2.242078e-44), 65535(9.183409e-41)
; EG-NEXT: ASHR T0.W, PV.W, PS, ; EG-NEXT: ASHR T0.W, PV.W, PS,
; EG-NEXT: ASHR * T1.W, PV.Y, PV.Z, ; EG-NEXT: ASHR * T1.W, PV.Y, PV.Z,
; EG-NEXT: LSHL T1.W, PS, literal.x, ; EG-NEXT: LSHL T1.W, PS, literal.x,
; EG-NEXT: AND_INT * T0.W, PV.W, literal.y, ; EG-NEXT: AND_INT * T0.W, PV.W, literal.y,
; EG-NEXT: 16(2.242078e-44), 65535(9.183409e-41) ; EG-NEXT: 16(2.242078e-44), 65535(9.183409e-41)
; EG-NEXT: OR_INT T6.X, PS, PV.W, ; EG-NEXT: OR_INT T6.X, PS, PV.W,
; EG-NEXT: LSHR * T7.X, KC0[2].Y, literal.x, ; EG-NEXT: LSHR * T7.X, KC0[2].Y, literal.x,
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; SI-NEXT: s_mov_b32 s5, s1 ; SI-NEXT: s_mov_b32 s5, s1
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_bfe_i32 v4, v0, 0, 16 ; SI-NEXT: v_bfe_i32 v4, v0, 0, 16
; SI-NEXT: v_ashrrev_i32_e32 v0, 16, v0 ; SI-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; SI-NEXT: v_bfe_i32 v5, v1, 0, 16 ; SI-NEXT: v_bfe_i32 v5, v1, 0, 16
; SI-NEXT: v_ashrrev_i32_e32 v1, 16, v1 ; SI-NEXT: v_ashrrev_i32_e32 v1, 16, v1
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v2 ; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v3 ; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v3
; SI-NEXT: v_ashrrev_i32_e32 v1, v7, v1 ; SI-NEXT: v_ashr_i32_e32 v1, v1, v7
; SI-NEXT: v_ashrrev_i32_e32 v3, v3, v5 ; SI-NEXT: v_ashr_i32_e32 v3, v5, v3
; SI-NEXT: v_ashrrev_i32_e32 v0, v6, v0 ; SI-NEXT: v_ashr_i32_e32 v0, v0, v6
; SI-NEXT: v_ashrrev_i32_e32 v2, v2, v4 ; SI-NEXT: v_ashr_i32_e32 v2, v4, v2
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_and_b32_e32 v3, s2, v3 ; SI-NEXT: v_and_b32_e32 v3, s2, v3
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_and_b32_e32 v2, s2, v2 ; SI-NEXT: v_and_b32_e32 v2, s2, v2
; SI-NEXT: v_or_b32_e32 v1, v3, v1 ; SI-NEXT: v_or_b32_e32 v1, v3, v1
; SI-NEXT: v_or_b32_e32 v0, v2, v0 ; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
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; VI-NEXT: v_ashrrev_i32_sdwa v1, sext(v3), sext(v1) dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-NEXT: v_ashrrev_i32_sdwa v1, sext(v3), sext(v1) dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; EG-LABEL: ashr_v4i16: ; EG-LABEL: ashr_v4i16:
; EG: ; %bb.0: ; EG: ; %bb.0:
; EG-NEXT: ALU 0, @12, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @8 ; EG-NEXT: TEX 0 @6
; EG-NEXT: ALU 3, @13, KC0[], KC1[] ; EG-NEXT: ALU 58, @9, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @10
; EG-NEXT: ALU 54, @17, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T10.XY, T9.X, 1 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T10.XY, T9.X, 1
; EG-NEXT: CF_END ; EG-NEXT: CF_END
; EG-NEXT: PAD ; EG-NEXT: PAD
; EG-NEXT: Fetch clause starting at 8: ; EG-NEXT: Fetch clause starting at 6:
; EG-NEXT: VTX_READ_64 T10.XY, T9.X, 0, #1 ; EG-NEXT: VTX_READ_128 T9.XYZW, T9.X, 0, #1
; EG-NEXT: Fetch clause starting at 10: ; EG-NEXT: ALU clause starting at 8:
; EG-NEXT: VTX_READ_64 T9.XY, T9.X, 8, #1
; EG-NEXT: ALU clause starting at 12:
; EG-NEXT: MOV * T9.X, KC0[2].Z, ; EG-NEXT: MOV * T9.X, KC0[2].Z,
; EG-NEXT: ALU clause starting at 13: ; EG-NEXT: ALU clause starting at 9:
; EG-NEXT: MOV T4.X, T10.X, ; EG-NEXT: MOV T4.X, T9.X,
; EG-NEXT: MOV * T5.X, T10.Y, ; EG-NEXT: MOV * T5.X, T9.Y,
; EG-NEXT: MOV T0.Y, PV.X, ; EG-NEXT: MOV T0.Y, PV.X,
; EG-NEXT: MOV * T0.Z, PS, ; EG-NEXT: MOV * T0.Z, PS,
; EG-NEXT: ALU clause starting at 17: ; EG-NEXT: MOV T2.X, T9.Z,
; EG-NEXT: MOV T2.X, T9.X, ; EG-NEXT: MOV * T3.X, T9.W,
; EG-NEXT: MOV * T3.X, T9.Y,
; EG-NEXT: MOV * T0.W, T6.X, ; EG-NEXT: MOV * T0.W, T6.X,
; EG-NEXT: MOV T1.Y, T2.X, ; EG-NEXT: MOV T1.Y, T2.X,
; EG-NEXT: BFE_INT * T1.W, T0.Y, 0.0, literal.x, ; EG-NEXT: BFE_INT * T1.W, T0.Y, 0.0, literal.x,
; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
; EG-NEXT: AND_INT * T2.W, PV.Y, literal.x, ; EG-NEXT: AND_INT * T2.W, PV.Y, literal.x,
; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) ; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
; EG-NEXT: ASHR * T1.W, T1.W, PV.W, ; EG-NEXT: ASHR * T1.W, T1.W, PV.W,
; EG-NEXT: AND_INT T1.W, PV.W, literal.x, ; EG-NEXT: AND_INT T1.W, PV.W, literal.x,
▲ Show 20 Lines • Show All 615 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/srl.ll

Show First 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
; SI-NEXT: v_lshr_b32_e32 v0, v0, v2 ; SI-NEXT: v_lshr_b32_e32 v0, v0, v2
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: lshr_v2i32: ; VI-LABEL: lshr_v2i32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 ; VI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
; VI-NEXT: s_load_dwordx2 s[6:7], s[2:3], 0x8
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_lshr_b32 s5, s5, s7 ; VI-NEXT: s_lshr_b32 s5, s5, s7
; VI-NEXT: s_lshr_b32 s4, s4, s6 ; VI-NEXT: s_lshr_b32 s4, s4, s6
; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5 ; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; EG-LABEL: lshr_v2i32: ; EG-LABEL: lshr_v2i32:
; EG: ; %bb.0: ; EG: ; %bb.0:
; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 1 @6 ; EG-NEXT: TEX 0 @6
; EG-NEXT: ALU 3, @11, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
; EG-NEXT: CF_END ; EG-NEXT: CF_END
; EG-NEXT: PAD ; EG-NEXT: PAD
; EG-NEXT: Fetch clause starting at 6: ; EG-NEXT: Fetch clause starting at 6:
; EG-NEXT: VTX_READ_64 T1.XY, T0.X, 8, #1 ; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1 ; EG-NEXT: ALU clause starting at 8:
; EG-NEXT: ALU clause starting at 10:
; EG-NEXT: MOV * T0.X, KC0[2].Z, ; EG-NEXT: MOV * T0.X, KC0[2].Z,
; EG-NEXT: ALU clause starting at 11: ; EG-NEXT: ALU clause starting at 9:
; EG-NEXT: LSHR * T0.Y, T0.Y, T1.Y, ; EG-NEXT: LSHR * T0.Y, T0.Y, T0.W,
; EG-NEXT: LSHR T0.X, T0.X, T1.X, ; EG-NEXT: LSHR T0.X, T0.X, T0.Z,
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1 %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
%a = load <2 x i32>, <2 x i32> addrspace(1)* %in %a = load <2 x i32>, <2 x i32> addrspace(1)* %in
%b = load <2 x i32>, <2 x i32> addrspace(1)* %b_ptr %b = load <2 x i32>, <2 x i32> addrspace(1)* %b_ptr
%result = lshr <2 x i32> %a, %b %result = lshr <2 x i32> %a, %b
store <2 x i32> %result, <2 x i32> addrspace(1)* %out store <2 x i32> %result, <2 x i32> addrspace(1)* %out
ret void ret void
Show All 19 Lines
; SI-NEXT: v_lshr_b32_e32 v2, v2, v6 ; SI-NEXT: v_lshr_b32_e32 v2, v2, v6
; SI-NEXT: v_lshr_b32_e32 v1, v1, v5 ; SI-NEXT: v_lshr_b32_e32 v1, v1, v5
; SI-NEXT: v_lshr_b32_e32 v0, v0, v4 ; SI-NEXT: v_lshr_b32_e32 v0, v0, v4
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: lshr_v4i32: ; VI-LABEL: lshr_v4i32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0 ; VI-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
; VI-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x10 ; VI-NEXT: s_mov_b32 s11, 0xf000
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s10, -1
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_lshr_b32 s3, s3, s7
; VI-NEXT: s_lshr_b32 s7, s7, s11 ; VI-NEXT: s_lshr_b32 s2, s2, s6
; VI-NEXT: s_lshr_b32 s6, s6, s10 ; VI-NEXT: s_lshr_b32 s1, s1, s5
; VI-NEXT: s_lshr_b32 s5, s5, s9 ; VI-NEXT: s_lshr_b32 s0, s0, s4
; VI-NEXT: s_lshr_b32 s4, s4, s8 ; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v1, s5 ; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v2, s6 ; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: v_mov_b32_e32 v3, s7 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; EG-LABEL: lshr_v4i32: ; EG-LABEL: lshr_v4i32:
; EG: ; %bb.0: ; EG: ; %bb.0:
; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 1 @6 ; EG-NEXT: TEX 1 @6
; EG-NEXT: ALU 5, @11, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 5, @11, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
; SI-NEXT: buffer_store_dwordx4 v[7:10], off, s[0:3], 0 ; SI-NEXT: buffer_store_dwordx4 v[7:10], off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: lshr_v4i64: ; VI-LABEL: lshr_v4i64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[16:19], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[16:19], s[0:1], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_load_dwordx8 s[0:7], s[18:19], 0x0 ; VI-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
; VI-NEXT: s_load_dwordx8 s[8:15], s[18:19], 0x20
; VI-NEXT: s_mov_b32 s19, 0xf000 ; VI-NEXT: s_mov_b32 s19, 0xf000
; VI-NEXT: s_mov_b32 s18, -1 ; VI-NEXT: s_mov_b32 s18, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_lshr_b64 s[6:7], s[6:7], s14 ; VI-NEXT: s_lshr_b64 s[6:7], s[6:7], s14
; VI-NEXT: s_lshr_b64 s[4:5], s[4:5], s12 ; VI-NEXT: s_lshr_b64 s[4:5], s[4:5], s12
; VI-NEXT: s_lshr_b64 s[2:3], s[2:3], s10 ; VI-NEXT: s_lshr_b64 s[2:3], s[2:3], s10
; VI-NEXT: s_lshr_b64 s[0:1], s[0:1], s8 ; VI-NEXT: s_lshr_b64 s[0:1], s[0:1], s8
; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v0, s4
▲ Show 20 Lines • Show All 179 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/sub.v2i16.ll

Show First 20 Lines • Show All 159 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_endpgm
store <2 x i16> %add, <2 x i16> addrspace(1)* %out store <2 x i16> %add, <2 x i16> addrspace(1)* %out
ret void ret void
} }
; FIXME: VI should not scalarize arg access. ; FIXME: VI should not scalarize arg access.
define amdgpu_kernel void @s_test_sub_v2i16_kernarg(<2 x i16> addrspace(1)* %out, <2 x i16> %a, <2 x i16> %b) #1 { define amdgpu_kernel void @s_test_sub_v2i16_kernarg(<2 x i16> addrspace(1)* %out, <2 x i16> %a, <2 x i16> %b) #1 {
; GFX9-LABEL: s_test_sub_v2i16_kernarg: ; GFX9-LABEL: s_test_sub_v2i16_kernarg:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dword s2, s[0:1], 0x30 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
; GFX9-NEXT: s_load_dword s3, s[0:1], 0x2c
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; GFX9-NEXT: s_mov_b32 s7, 0xf000 ; GFX9-NEXT: s_mov_b32 s7, 0xf000
; GFX9-NEXT: s_mov_b32 s6, -1 ; GFX9-NEXT: s_mov_b32 s6, -1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s2 ; GFX9-NEXT: v_mov_b32_e32 v0, s3
; GFX9-NEXT: v_pk_sub_i16 v0, s3, v0 ; GFX9-NEXT: v_pk_sub_i16 v0, s2, v0
; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: s_test_sub_v2i16_kernarg: ; VI-LABEL: s_test_sub_v2i16_kernarg:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dword s4, s[0:1], 0x2c ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c
; VI-NEXT: s_load_dword s5, s[0:1], 0x30
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_lshr_b32 s6, s4, 16 ; VI-NEXT: s_lshr_b32 s6, s4, 16
; VI-NEXT: s_lshr_b32 s7, s5, 16 ; VI-NEXT: s_lshr_b32 s7, s5, 16
; VI-NEXT: s_sub_i32 s6, s6, s7 ; VI-NEXT: s_sub_i32 s6, s6, s7
; VI-NEXT: s_sub_i32 s4, s4, s5 ; VI-NEXT: s_sub_i32 s4, s4, s5
; VI-NEXT: s_lshl_b32 s5, s6, 16 ; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_and_b32 s4, s4, 0xffff ; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_or_b32 s4, s4, s5 ; VI-NEXT: s_or_b32 s4, s4, s5
; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX10-LABEL: s_test_sub_v2i16_kernarg: ; GFX10-LABEL: s_test_sub_v2i16_kernarg:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_clause 0x2 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dword s2, s[0:1], 0x2c ; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
; GFX10-NEXT: s_load_dword s3, s[0:1], 0x30
; GFX10-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; GFX10-NEXT: s_mov_b32 s7, 0x31016000 ; GFX10-NEXT: s_mov_b32 s7, 0x31016000
; GFX10-NEXT: s_mov_b32 s6, -1 ; GFX10-NEXT: s_mov_b32 s6, -1
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_pk_sub_i16 v0, s2, s3 ; GFX10-NEXT: v_pk_sub_i16 v0, s2, s3
; GFX10-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GFX10-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%add = sub <2 x i16> %a, %b %add = sub <2 x i16> %a, %b
▲ Show 20 Lines • Show All 600 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/udiv.ll

Show First 20 Lines • Show All 541 Lines • ▼ Show 20 Lines
; GFX1030-NEXT: v_cndmask_b32_e32 v0, v5, v7, vcc_lo ; GFX1030-NEXT: v_cndmask_b32_e32 v0, v5, v7, vcc_lo
; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v1, v3 ; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v1, v3
; GFX1030-NEXT: v_cndmask_b32_e32 v1, v6, v8, vcc_lo ; GFX1030-NEXT: v_cndmask_b32_e32 v1, v6, v8, vcc_lo
; GFX1030-NEXT: global_store_dwordx2 v4, v[0:1], s[4:5] ; GFX1030-NEXT: global_store_dwordx2 v4, v[0:1], s[4:5]
; GFX1030-NEXT: s_endpgm ; GFX1030-NEXT: s_endpgm
; ;
; EG-LABEL: udiv_v2i32: ; EG-LABEL: udiv_v2i32:
; EG: ; %bb.0: ; EG: ; %bb.0:
; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 1 @6 ; EG-NEXT: TEX 0 @6
; EG-NEXT: ALU 33, @11, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 33, @9, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XY, T0.X, 1 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XY, T0.X, 1
; EG-NEXT: CF_END ; EG-NEXT: CF_END
; EG-NEXT: PAD ; EG-NEXT: PAD
; EG-NEXT: Fetch clause starting at 6: ; EG-NEXT: Fetch clause starting at 6:
; EG-NEXT: VTX_READ_64 T1.XY, T0.X, 8, #1 ; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1 ; EG-NEXT: ALU clause starting at 8:
; EG-NEXT: ALU clause starting at 10:
; EG-NEXT: MOV * T0.X, KC0[2].Z, ; EG-NEXT: MOV * T0.X, KC0[2].Z,
; EG-NEXT: ALU clause starting at 11: ; EG-NEXT: ALU clause starting at 9:
; EG-NEXT: SUB_INT T0.W, 0.0, T1.Y, ; EG-NEXT: SUB_INT T1.W, 0.0, T0.W,
; EG-NEXT: RECIP_UINT * T0.Z, T1.Y, ; EG-NEXT: RECIP_UINT * T1.X, T0.W,
; EG-NEXT: MULLO_INT * T0.W, PV.W, PS, ; EG-NEXT: MULLO_INT * T1.Y, PV.W, PS,
; EG-NEXT: SUB_INT T1.W, 0.0, T1.X, ; EG-NEXT: SUB_INT T1.W, 0.0, T0.Z,
; EG-NEXT: RECIP_UINT * T1.Z, T1.X, ; EG-NEXT: RECIP_UINT * T1.Z, T0.Z,
; EG-NEXT: MULLO_INT * T1.W, PV.W, PS, ; EG-NEXT: MULLO_INT * T1.W, PV.W, PS,
; EG-NEXT: MULHI * T1.W, T1.Z, PS, ; EG-NEXT: MULHI * T1.W, T1.Z, PS,
; EG-NEXT: ADD_INT T1.W, T1.Z, PS, ; EG-NEXT: ADD_INT T1.W, T1.Z, PS,
; EG-NEXT: MULHI * T0.W, T0.Z, T0.W, ; EG-NEXT: MULHI * T1.Y, T1.X, T1.Y,
; EG-NEXT: ADD_INT T0.W, T0.Z, PS, ; EG-NEXT: ADD_INT T2.W, T1.X, PS,
; EG-NEXT: MULHI * T0.Z, T0.X, PV.W, ; EG-NEXT: MULHI * T1.X, T0.X, PV.W,
; EG-NEXT: MULHI * T0.W, T0.Y, PV.W, ; EG-NEXT: MULHI * T1.Y, T0.Y, PV.W,
; EG-NEXT: MULLO_INT * T1.Z, PS, T1.Y, ; EG-NEXT: MULLO_INT * T1.Z, PS, T0.W,
; EG-NEXT: SUB_INT T1.W, T0.Y, PS, ; EG-NEXT: SUB_INT T1.W, T0.Y, PS,
; EG-NEXT: MULLO_INT * T0.Y, T0.Z, T1.X, ; EG-NEXT: MULLO_INT * T0.Y, T1.X, T0.Z,
; EG-NEXT: SUB_INT T0.Y, T0.X, PS, ; EG-NEXT: SUB_INT T0.Y, T0.X, PS,
; EG-NEXT: ADD_INT T1.Z, T0.W, 1, ; EG-NEXT: ADD_INT T1.Z, T1.Y, 1,
; EG-NEXT: SETGE_UINT T2.W, PV.W, T1.Y, ; EG-NEXT: SETGE_UINT T2.W, PV.W, T0.W,
; EG-NEXT: SUB_INT * T3.W, PV.W, T1.Y, ; EG-NEXT: SUB_INT * T3.W, PV.W, T0.W,
; EG-NEXT: CNDE_INT T0.X, PV.W, T1.W, PS, ; EG-NEXT: CNDE_INT T0.X, PV.W, T1.W, PS,
; EG-NEXT: CNDE_INT T2.Y, PV.W, T0.W, PV.Z, BS:VEC_021/SCL_122 ; EG-NEXT: CNDE_INT T1.Y, PV.W, T1.Y, PV.Z,
; EG-NEXT: ADD_INT T1.Z, T0.Z, 1, ; EG-NEXT: ADD_INT T1.Z, T1.X, 1,
; EG-NEXT: SETGE_UINT T0.W, PV.Y, T1.X, ; EG-NEXT: SETGE_UINT T1.W, PV.Y, T0.Z,
; EG-NEXT: SUB_INT * T1.W, PV.Y, T1.X, ; EG-NEXT: SUB_INT * T2.W, PV.Y, T0.Z,
; EG-NEXT: CNDE_INT T0.Y, PV.W, T0.Y, PS, BS:VEC_021/SCL_122 ; EG-NEXT: CNDE_INT T0.Y, PV.W, T0.Y, PS,
; EG-NEXT: CNDE_INT T0.Z, PV.W, T0.Z, PV.Z, ; EG-NEXT: CNDE_INT T1.Z, PV.W, T1.X, PV.Z,
; EG-NEXT: ADD_INT T0.W, PV.Y, 1, ; EG-NEXT: ADD_INT T1.W, PV.Y, 1,
; EG-NEXT: SETGE_UINT * T1.W, PV.X, T1.Y, ; EG-NEXT: SETGE_UINT * T0.W, PV.X, T0.W,
; EG-NEXT: CNDE_INT T1.Y, PS, T2.Y, PV.W, ; EG-NEXT: CNDE_INT T1.Y, PS, T1.Y, PV.W,
; EG-NEXT: ADD_INT T0.W, PV.Z, 1, ; EG-NEXT: ADD_INT T0.W, PV.Z, 1,
; EG-NEXT: SETGE_UINT * T1.W, PV.Y, T1.X, ; EG-NEXT: SETGE_UINT * T1.W, PV.Y, T0.Z,
; EG-NEXT: CNDE_INT T1.X, PS, T0.Z, PV.W, ; EG-NEXT: CNDE_INT T1.X, PS, T1.Z, PV.W,
; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x, ; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1 %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
%a = load <2 x i32>, <2 x i32> addrspace(1) * %in %a = load <2 x i32>, <2 x i32> addrspace(1) * %in
%b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr %b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr
%result = udiv <2 x i32> %a, %b %result = udiv <2 x i32> %a, %b
store <2 x i32> %result, <2 x i32> addrspace(1)* %out store <2 x i32> %result, <2 x i32> addrspace(1)* %out
ret void ret void
▲ Show 20 Lines • Show All 2,249 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/urem64.ll

Show First 20 Lines • Show All 485 Lines • ▼ Show 20 Lines; GCN-IR-NEXT: s_endpgm
%result = urem i64 %1, %2 %result = urem i64 %1, %2
store i64 %result, i64 addrspace(1)* %out store i64 %result, i64 addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @s_test_urem31_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) { define amdgpu_kernel void @s_test_urem31_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
; GCN-LABEL: s_test_urem31_v2i64: ; GCN-LABEL: s_test_urem31_v2i64:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x11 ; GCN-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd
; GCN-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd ; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_mov_b32 s11, 0xf000 ; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_mov_b32 s10, -1 ; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_lshr_b32 s0, s5, 1 ; GCN-NEXT: s_lshr_b32 s4, s5, 1
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s0 ; GCN-NEXT: s_lshr_b32 s5, s9, 1
; GCN-NEXT: s_lshr_b32 s1, s1, 1 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s5
; GCN-NEXT: v_cvt_f32_u32_e32 v1, s1 ; GCN-NEXT: v_cvt_f32_u32_e32 v2, s4
; GCN-NEXT: s_lshr_b32 s2, s3, 1 ; GCN-NEXT: s_lshr_b32 s6, s11, 1
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 ; GCN-NEXT: v_cvt_f32_u32_e32 v3, s6
; GCN-NEXT: s_lshr_b32 s3, s7, 1 ; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v0
; GCN-NEXT: v_cvt_f32_u32_e32 v4, s3 ; GCN-NEXT: s_lshr_b32 s7, s7, 1
; GCN-NEXT: v_cvt_f32_u32_e32 v3, s2 ; GCN-NEXT: v_cvt_f32_u32_e32 v5, s7
; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-NEXT: v_rcp_iflag_f32_e32 v6, v3
; GCN-NEXT: v_mul_f32_e32 v4, v2, v4
; GCN-NEXT: v_trunc_f32_e32 v4, v4
; GCN-NEXT: v_cvt_u32_f32_e32 v7, v4
; GCN-NEXT: v_mad_f32 v2, -v4, v0, v2
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0
; GCN-NEXT: v_mul_f32_e32 v2, v5, v6
; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v7, vcc
; GCN-NEXT: v_mul_lo_u32 v0, v0, s5
; GCN-NEXT: v_trunc_f32_e32 v2, v2 ; GCN-NEXT: v_trunc_f32_e32 v2, v2
; GCN-NEXT: v_cvt_u32_f32_e32 v5, v2 ; GCN-NEXT: v_cvt_u32_f32_e32 v4, v2
; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_mad_f32 v2, -v2, v3, v5
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v4 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v3
; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v5, vcc ; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v4, vcc
; GCN-NEXT: v_mul_lo_u32 v0, v0, s0 ; GCN-NEXT: v_mul_lo_u32 v2, v2, s6
; GCN-NEXT: v_mul_f32_e32 v2, v3, v2 ; GCN-NEXT: s_brev_b32 s4, -2
; GCN-NEXT: v_trunc_f32_e32 v2, v2 ; GCN-NEXT: v_and_b32_e32 v0, s4, v0
; GCN-NEXT: v_cvt_u32_f32_e32 v5, v2
; GCN-NEXT: v_sub_i32_e32 v0, vcc, s1, v0
; GCN-NEXT: v_mad_f32 v2, -v2, v4, v3
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4
; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc
; GCN-NEXT: v_mul_lo_u32 v2, v2, s3
; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_brev_b32 s0, -2
; GCN-NEXT: v_and_b32_e32 v0, s0, v0
; GCN-NEXT: v_sub_i32_e32 v2, vcc, s2, v2
; GCN-NEXT: v_and_b32_e32 v2, s0, v2
; GCN-NEXT: v_mov_b32_e32 v3, v1 ; GCN-NEXT: v_mov_b32_e32 v3, v1
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 ; GCN-NEXT: v_sub_i32_e32 v2, vcc, s7, v2
; GCN-NEXT: v_and_b32_e32 v2, s4, v2
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GCN-IR-LABEL: s_test_urem31_v2i64: ; GCN-IR-LABEL: s_test_urem31_v2i64:
; GCN-IR: ; %bb.0: ; GCN-IR: ; %bb.0:
; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x11 ; GCN-IR-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd
; GCN-IR-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
; GCN-IR-NEXT: s_mov_b32 s11, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: s_mov_b32 s10, -1 ; GCN-IR-NEXT: s_mov_b32 s2, -1
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_lshr_b32 s0, s5, 1 ; GCN-IR-NEXT: s_lshr_b32 s4, s5, 1
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s0 ; GCN-IR-NEXT: s_lshr_b32 s5, s9, 1
; GCN-IR-NEXT: s_lshr_b32 s1, s1, 1 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s5
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s1 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v2, s4
; GCN-IR-NEXT: s_lshr_b32 s2, s3, 1 ; GCN-IR-NEXT: s_lshr_b32 s6, s11, 1
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v3, s6
; GCN-IR-NEXT: s_lshr_b32 s3, s7, 1 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v4, v0
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v4, s3 ; GCN-IR-NEXT: s_lshr_b32 s7, s7, 1
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v3, s2 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v5, s7
; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v6, v3
; GCN-IR-NEXT: v_mul_f32_e32 v4, v2, v4
; GCN-IR-NEXT: v_trunc_f32_e32 v4, v4
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v7, v4
; GCN-IR-NEXT: v_mad_f32 v2, -v4, v0, v2
; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0
; GCN-IR-NEXT: v_mul_f32_e32 v2, v5, v6
; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s5
; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v5, v2 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v4, v2
; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-IR-NEXT: v_mad_f32 v2, -v2, v3, v5
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v4 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v3
; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v5, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v2, vcc, 0, v4, vcc
; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s0 ; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, s6
; GCN-IR-NEXT: v_mul_f32_e32 v2, v3, v2 ; GCN-IR-NEXT: s_brev_b32 s4, -2
; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 ; GCN-IR-NEXT: v_and_b32_e32 v0, s4, v0
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v5, v2
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s1, v0
; GCN-IR-NEXT: v_mad_f32 v2, -v2, v4, v3
; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4
; GCN-IR-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, s3
; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
; GCN-IR-NEXT: s_brev_b32 s0, -2
; GCN-IR-NEXT: v_and_b32_e32 v0, s0, v0
; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s2, v2
; GCN-IR-NEXT: v_and_b32_e32 v2, s0, v2
; GCN-IR-NEXT: v_mov_b32_e32 v3, v1 ; GCN-IR-NEXT: v_mov_b32_e32 v3, v1
; GCN-IR-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 ; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s7, v2
; GCN-IR-NEXT: v_and_b32_e32 v2, s4, v2
; GCN-IR-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GCN-IR-NEXT: s_endpgm ; GCN-IR-NEXT: s_endpgm
%1 = lshr <2 x i64> %x, <i64 33, i64 33> %1 = lshr <2 x i64> %x, <i64 33, i64 33>
%2 = lshr <2 x i64> %y, <i64 33, i64 33> %2 = lshr <2 x i64> %y, <i64 33, i64 33>
%result = urem <2 x i64> %1, %2 %result = urem <2 x i64> %1, %2
store <2 x i64> %result, <2 x i64> addrspace(1)* %out store <2 x i64> %result, <2 x i64> addrspace(1)* %out
ret void ret void
} }
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines; GCN-IR-NEXT: s_endpgm
%result = urem i64 %1, %2 %result = urem i64 %1, %2
store i64 %result, i64 addrspace(1)* %out store i64 %result, i64 addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @s_test_urem23_64_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) { define amdgpu_kernel void @s_test_urem23_64_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
; GCN-LABEL: s_test_urem23_64_v2i64: ; GCN-LABEL: s_test_urem23_64_v2i64:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x11 ; GCN-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd
; GCN-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd ; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_mov_b32 s11, 0xf000 ; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_mov_b32 s10, -1 ; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_lshr_b32 s0, s5, 1 ; GCN-NEXT: s_lshr_b32 s4, s5, 1
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s0 ; GCN-NEXT: s_lshr_b32 s5, s9, 1
; GCN-NEXT: s_lshr_b32 s1, s1, 1 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s5
; GCN-NEXT: v_cvt_f32_u32_e32 v1, s1 ; GCN-NEXT: v_cvt_f32_u32_e32 v2, s4
; GCN-NEXT: s_lshr_b32 s2, s3, 9 ; GCN-NEXT: s_lshr_b32 s6, s11, 9
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 ; GCN-NEXT: v_cvt_f32_u32_e32 v3, s6
; GCN-NEXT: s_lshr_b32 s3, s7, 9 ; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v0
; GCN-NEXT: v_cvt_f32_u32_e32 v4, s3 ; GCN-NEXT: s_lshr_b32 s7, s7, 9
; GCN-NEXT: v_cvt_f32_u32_e32 v3, s2 ; GCN-NEXT: v_cvt_f32_u32_e32 v5, s7
; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-NEXT: v_rcp_iflag_f32_e32 v6, v3
; GCN-NEXT: v_mul_f32_e32 v4, v2, v4
; GCN-NEXT: v_trunc_f32_e32 v4, v4
; GCN-NEXT: v_cvt_u32_f32_e32 v7, v4
; GCN-NEXT: v_mad_f32 v2, -v4, v0, v2
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0
; GCN-NEXT: v_mul_f32_e32 v2, v5, v6
; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v7, vcc
; GCN-NEXT: v_mul_lo_u32 v0, v0, s5
; GCN-NEXT: v_trunc_f32_e32 v2, v2 ; GCN-NEXT: v_trunc_f32_e32 v2, v2
; GCN-NEXT: v_cvt_u32_f32_e32 v5, v2 ; GCN-NEXT: v_cvt_u32_f32_e32 v4, v2
; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_mad_f32 v2, -v2, v3, v5
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v4 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v3
; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v5, vcc ; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v4, vcc
; GCN-NEXT: v_mul_lo_u32 v0, v0, s0 ; GCN-NEXT: v_mul_lo_u32 v2, v2, s6
; GCN-NEXT: v_mul_f32_e32 v2, v3, v2 ; GCN-NEXT: s_brev_b32 s4, -2
; GCN-NEXT: v_trunc_f32_e32 v2, v2 ; GCN-NEXT: v_and_b32_e32 v0, s4, v0
; GCN-NEXT: v_cvt_u32_f32_e32 v5, v2
; GCN-NEXT: v_sub_i32_e32 v0, vcc, s1, v0
; GCN-NEXT: v_mad_f32 v2, -v2, v4, v3
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4
; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc
; GCN-NEXT: v_mul_lo_u32 v2, v2, s3
; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_brev_b32 s0, -2
; GCN-NEXT: v_and_b32_e32 v0, s0, v0
; GCN-NEXT: v_sub_i32_e32 v2, vcc, s2, v2
; GCN-NEXT: v_and_b32_e32 v2, s0, v2
; GCN-NEXT: v_mov_b32_e32 v3, v1 ; GCN-NEXT: v_mov_b32_e32 v3, v1
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 ; GCN-NEXT: v_sub_i32_e32 v2, vcc, s7, v2
; GCN-NEXT: v_and_b32_e32 v2, s4, v2
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GCN-IR-LABEL: s_test_urem23_64_v2i64: ; GCN-IR-LABEL: s_test_urem23_64_v2i64:
; GCN-IR: ; %bb.0: ; GCN-IR: ; %bb.0:
; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x11 ; GCN-IR-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd
; GCN-IR-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
; GCN-IR-NEXT: s_mov_b32 s11, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: s_mov_b32 s10, -1 ; GCN-IR-NEXT: s_mov_b32 s2, -1
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_lshr_b32 s0, s5, 1 ; GCN-IR-NEXT: s_lshr_b32 s4, s5, 1
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s0 ; GCN-IR-NEXT: s_lshr_b32 s5, s9, 1
; GCN-IR-NEXT: s_lshr_b32 s1, s1, 1 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s5
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s1 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v2, s4
; GCN-IR-NEXT: s_lshr_b32 s2, s3, 9 ; GCN-IR-NEXT: s_lshr_b32 s6, s11, 9
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v3, s6
; GCN-IR-NEXT: s_lshr_b32 s3, s7, 9 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v4, v0
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v4, s3 ; GCN-IR-NEXT: s_lshr_b32 s7, s7, 9
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v3, s2 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v5, s7
; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v6, v3
; GCN-IR-NEXT: v_mul_f32_e32 v4, v2, v4
; GCN-IR-NEXT: v_trunc_f32_e32 v4, v4
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v7, v4
; GCN-IR-NEXT: v_mad_f32 v2, -v4, v0, v2
; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0
; GCN-IR-NEXT: v_mul_f32_e32 v2, v5, v6
; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s5
; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v5, v2 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v4, v2
; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-IR-NEXT: v_mad_f32 v2, -v2, v3, v5
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v4 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v3
; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v5, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v2, vcc, 0, v4, vcc
; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s0 ; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, s6
; GCN-IR-NEXT: v_mul_f32_e32 v2, v3, v2 ; GCN-IR-NEXT: s_brev_b32 s4, -2
; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 ; GCN-IR-NEXT: v_and_b32_e32 v0, s4, v0
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v5, v2
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s1, v0
; GCN-IR-NEXT: v_mad_f32 v2, -v2, v4, v3
; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4
; GCN-IR-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, s3
; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
; GCN-IR-NEXT: s_brev_b32 s0, -2
; GCN-IR-NEXT: v_and_b32_e32 v0, s0, v0
; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s2, v2
; GCN-IR-NEXT: v_and_b32_e32 v2, s0, v2
; GCN-IR-NEXT: v_mov_b32_e32 v3, v1 ; GCN-IR-NEXT: v_mov_b32_e32 v3, v1
; GCN-IR-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 ; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s7, v2
; GCN-IR-NEXT: v_and_b32_e32 v2, s4, v2
; GCN-IR-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GCN-IR-NEXT: s_endpgm ; GCN-IR-NEXT: s_endpgm
%1 = lshr <2 x i64> %x, <i64 33, i64 41> %1 = lshr <2 x i64> %x, <i64 33, i64 41>
%2 = lshr <2 x i64> %y, <i64 33, i64 41> %2 = lshr <2 x i64> %y, <i64 33, i64 41>
%result = urem <2 x i64> %1, %2 %result = urem <2 x i64> %1, %2
store <2 x i64> %result, <2 x i64> addrspace(1)* %out store <2 x i64> %result, <2 x i64> addrspace(1)* %out
ret void ret void
} }
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llvm/test/Transforms/LoadStoreVectorizer/NVPTX/4x2xhalf.ll

  • This file was added.
; RUN: opt -mtriple=nvptx64-nvidia-cuda -load-store-vectorizer -S -o - %s | FileCheck %s
define void @ldg_f16(half* nocapture align 16 %rd0) {
%in1b = bitcast half* %rd0 to <2 x half>*
%load1 = load <2 x half>, <2 x half>* %in1b, align 4
%p1 = fcmp ogt <2 x half> %load1, zeroinitializer
arsenmUnsubmitted
Done
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Should use named values in tests

arsenm: Should use named values in tests
%s1 = select <2 x i1> %p1, <2 x half> %load1, <2 x half> zeroinitializer
store <2 x half> %s1, <2 x half>* %in1b, align 4
%in2 = getelementptr half, half* %rd0, i64 2
%in2b = bitcast half* %in2 to <2 x half>*
%load2 = load <2 x half>, <2 x half>* %in2b, align 4
%p2 = fcmp ogt <2 x half> %load2, zeroinitializer
%s2 = select <2 x i1> %p2, <2 x half> %load2, <2 x half> zeroinitializer
store <2 x half> %s2, <2 x half>* %in2b, align 4
%in3 = getelementptr half, half* %rd0, i64 4
%in3b = bitcast half* %in3 to <2 x half>*
%load3 = load <2 x half>, <2 x half>* %in3b, align 4
%p3 = fcmp ogt <2 x half> %load3, zeroinitializer
%s3 = select <2 x i1> %p3, <2 x half> %load3, <2 x half> zeroinitializer
store <2 x half> %s3, <2 x half>* %in3b, align 4
%in4 = getelementptr half, half* %rd0, i64 6
%in4b = bitcast half* %in4 to <2 x half>*
%load4 = load <2 x half>, <2 x half>* %in4b, align 4
%p4 = fcmp ogt <2 x half> %load4, zeroinitializer
%s4 = select <2 x i1> %p4, <2 x half> %load4, <2 x half> zeroinitializer
store <2 x half> %s4, <2 x half>* %in4b, align 4
ret void
; CHECK-LABEL: @ldg_f16
; CHECK: %[[LD:.*]] = load <8 x half>, <8 x half>*
; CHECK: shufflevector <8 x half> %[[LD]], <8 x half> poison, <2 x i32> <i32 0, i32 1>
; CHECK: shufflevector <8 x half> %[[LD]], <8 x half> poison, <2 x i32> <i32 2, i32 3>
; CHECK: shufflevector <8 x half> %[[LD]], <8 x half> poison, <2 x i32> <i32 4, i32 5>
; CHECK: shufflevector <8 x half> %[[LD]], <8 x half> poison, <2 x i32> <i32 6, i32 7>
arsenmUnsubmitted
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Should add a larger variety of tests with more vector widths, particularly some 3 element vectors

arsenm: Should add a larger variety of tests with more vector widths, particularly some 3 element…
bkramerAuthorUnsubmitted
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Anything in particular you're looking for? Currently the pass also has the limitation of only creating vector sizes that are a power of 2, which means there is no interesting case for 3-element vectors.

bkramer: Anything in particular you're looking for? Currently the pass also has the limitation of only…
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Not handling those is of interest itself?

Vectors of pointers are always an interesting source of edge cases

arsenm: Not handling those is of interest itself? Vectors of pointers are always an interesting…
bkramerAuthorUnsubmitted
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I don't think that's a particularly valuable test, but added some.

bkramer: I don't think that's a particularly valuable test, but added some.
; CHECK: store <8 x half>
}
define void @no_nonpow2_vector(half* nocapture align 16 %rd0) {
%in1b = bitcast half* %rd0 to <3 x half>*
%load1 = load <3 x half>, <3 x half>* %in1b, align 4
%p1 = fcmp ogt <3 x half> %load1, zeroinitializer
%s1 = select <3 x i1> %p1, <3 x half> %load1, <3 x half> zeroinitializer
store <3 x half> %s1, <3 x half>* %in1b, align 4
%in2 = getelementptr half, half* %rd0, i64 3
%in2b = bitcast half* %in2 to <3 x half>*
%load2 = load <3 x half>, <3 x half>* %in2b, align 4
%p2 = fcmp ogt <3 x half> %load2, zeroinitializer
%s2 = select <3 x i1> %p2, <3 x half> %load2, <3 x half> zeroinitializer
store <3 x half> %s2, <3 x half>* %in2b, align 4
%in3 = getelementptr half, half* %rd0, i64 6
%in3b = bitcast half* %in3 to <3 x half>*
%load3 = load <3 x half>, <3 x half>* %in3b, align 4
%p3 = fcmp ogt <3 x half> %load3, zeroinitializer
%s3 = select <3 x i1> %p3, <3 x half> %load3, <3 x half> zeroinitializer
store <3 x half> %s3, <3 x half>* %in3b, align 4
%in4 = getelementptr half, half* %rd0, i64 9
%in4b = bitcast half* %in4 to <3 x half>*
%load4 = load <3 x half>, <3 x half>* %in4b, align 4
%p4 = fcmp ogt <3 x half> %load4, zeroinitializer
%s4 = select <3 x i1> %p4, <3 x half> %load4, <3 x half> zeroinitializer
store <3 x half> %s4, <3 x half>* %in4b, align 4
ret void
; CHECK-LABEL: @no_nonpow2_vector
; CHECK-NOT: shufflevector
}
define void @no_pointer_vector(half** nocapture align 16 %rd0) {
%in1b = bitcast half** %rd0 to <2 x half*>*
%load1 = load <2 x half*>, <2 x half*>* %in1b, align 4
%p1 = icmp ne <2 x half*> %load1, zeroinitializer
%s1 = select <2 x i1> %p1, <2 x half*> %load1, <2 x half*> zeroinitializer
store <2 x half*> %s1, <2 x half*>* %in1b, align 4
%in2 = getelementptr half*, half** %rd0, i64 2
%in2b = bitcast half** %in2 to <2 x half*>*
%load2 = load <2 x half*>, <2 x half*>* %in2b, align 4
%p2 = icmp ne <2 x half*> %load2, zeroinitializer
%s2 = select <2 x i1> %p2, <2 x half*> %load2, <2 x half*> zeroinitializer
store <2 x half*> %s2, <2 x half*>* %in2b, align 4
%in3 = getelementptr half*, half** %rd0, i64 4
%in3b = bitcast half** %in3 to <2 x half*>*
%load3 = load <2 x half*>, <2 x half*>* %in3b, align 4
%p3 = icmp ne <2 x half*> %load3, zeroinitializer
%s3 = select <2 x i1> %p3, <2 x half*> %load3, <2 x half*> zeroinitializer
store <2 x half*> %s3, <2 x half*>* %in3b, align 4
%in4 = getelementptr half*, half** %rd0, i64 6
%in4b = bitcast half** %in4 to <2 x half*>*
%load4 = load <2 x half*>, <2 x half*>* %in4b, align 4
%p4 = icmp ne <2 x half*> %load4, zeroinitializer
%s4 = select <2 x i1> %p4, <2 x half*> %load4, <2 x half*> zeroinitializer
store <2 x half*> %s4, <2 x half*>* %in4b, align 4
ret void
; CHECK-LABEL: @no_pointer_vector
; CHECK-NOT: shufflevector
}
arsenmUnsubmitted
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I would have expected this to vectorize

arsenm: I would have expected this to vectorize
bkramerAuthorUnsubmitted
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The pass explicitly disallows pointers of vectors. Shouldn't be hard to turn it on though, I guess it didn't really matter so far.

bkramer: The pass explicitly disallows pointers of vectors. Shouldn't be hard to turn it on though, I…