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Differential D114575

[X86] Add vector test coverage for or with no common bits tests
ClosedPublic

Authored by OmerAviram on Nov 25 2021, 1:47 AM.

Details

Reviewers
alonkom
guyblank
spatel
RKSimon
Commits
rGa7363067e69a: [X86] Add vector test coverage for or with no common bits tests
Summary

Ensure D113970 handles vector types patterns as well.

Diff Detail

Event Timeline

OmerAviram created this revision.Nov 25 2021, 1:47 AM
Herald added a subscriber: pengfei. · View Herald TranscriptNov 25 2021, 1:47 AM
OmerAviram requested review of this revision.Nov 25 2021, 1:47 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 25 2021, 1:47 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
OmerAviram added a child revision: D113970: [SelectionDAG] Add pattern to haveNoCommonBitsSet..Nov 25 2021, 1:55 AM
OmerAviram edited the summary of this revision. (Show Details)
Harbormaster completed remote builds in B136001: Diff 389692.Nov 25 2021, 2:27 AM
OmerAviram updated this revision to Diff 389759.Nov 25 2021, 6:10 AM
Harbormaster completed remote builds in B136048: Diff 389759.Nov 25 2021, 6:37 AM
OmerAviram updated this revision to Diff 389766.Nov 25 2021, 6:46 AM
Harbormaster completed remote builds in B136053: Diff 389766.Nov 25 2021, 7:22 AM
spatel accepted this revision.Nov 29 2021, 6:25 AM

LGTM

This revision is now accepted and ready to land.Nov 29 2021, 6:25 AM
OmerAviram added a comment.Nov 29 2021, 6:41 AM
In D114575#3158211, @spatel wrote:

LGTM

Can you please push the commit on my behalf? Thanks.

Closed by commit rGa7363067e69a: [X86] Add vector test coverage for or with no common bits tests (authored by OmerAviram, committed by spatel). · Explain WhyNov 29 2021, 6:59 AM
This revision was automatically updated to reflect the committed changes.
spatel added a commit: rGa7363067e69a: [X86] Add vector test coverage for or with no common bits tests.

Revision Contents

PathSize
llvm/
test/
CodeGen/
X86/
161 lines

Diff 390344

llvm/test/CodeGen/X86/vec_no-common-bits.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK
; In the following patterns, lhs and rhs of the or instruction have no common bits.
; Therefore, "add" and "or" instructions are equal.
define <2 x i32> @or_and_and_rhs_neg_vec_i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z) {
; CHECK-LABEL: or_and_and_rhs_neg_vec_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: pand %xmm1, %xmm2
; CHECK-NEXT: pandn %xmm0, %xmm1
; CHECK-NEXT: movdqa %xmm2, %xmm0
; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: paddd %xmm2, %xmm1
; CHECK-NEXT: psubd %xmm1, %xmm0
; CHECK-NEXT: retq
%and1 = and <2 x i32> %z, %y
%xor = xor <2 x i32> %y, <i32 -1, i32 -1>
%and2 = and <2 x i32> %x, %xor
%or = or <2 x i32> %and1, %and2
%add = add <2 x i32> %and1, %and2
%sub = sub <2 x i32> %or, %add
ret <2 x i32> %sub
}
define <2 x i32> @or_and_and_lhs_neg_vec_i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z) {
; CHECK-LABEL: or_and_and_lhs_neg_vec_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: pand %xmm1, %xmm2
; CHECK-NEXT: pandn %xmm0, %xmm1
; CHECK-NEXT: movdqa %xmm2, %xmm0
; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: paddd %xmm2, %xmm1
; CHECK-NEXT: psubd %xmm1, %xmm0
; CHECK-NEXT: retq
%and1 = and <2 x i32> %z, %y
%xor = xor <2 x i32> %y, <i32 -1, i32 -1>
%and2 = and <2 x i32> %xor, %x
%or = or <2 x i32> %and1, %and2
%add = add <2 x i32> %and1, %and2
%sub = sub <2 x i32> %or, %add
ret <2 x i32> %sub
}
define <2 x i32> @or_and_rhs_neg_and_vec_i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z) {
; CHECK-LABEL: or_and_rhs_neg_and_vec_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: pand %xmm1, %xmm0
; CHECK-NEXT: pandn %xmm2, %xmm1
; CHECK-NEXT: movdqa %xmm1, %xmm2
; CHECK-NEXT: por %xmm0, %xmm2
; CHECK-NEXT: paddd %xmm0, %xmm1
; CHECK-NEXT: psubd %xmm1, %xmm2
; CHECK-NEXT: movdqa %xmm2, %xmm0
; CHECK-NEXT: retq
%xor = xor <2 x i32> %y, <i32 -1, i32 -1>
%and1 = and <2 x i32> %z, %xor
%and2 = and <2 x i32> %x, %y
%or = or <2 x i32> %and1, %and2
%add = add <2 x i32> %and1, %and2
%sub = sub <2 x i32> %or, %add
ret <2 x i32> %sub
}
define <2 x i32> @or_and_lhs_neg_and_vec_i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z) {
; CHECK-LABEL: or_and_lhs_neg_and_vec_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: pand %xmm1, %xmm0
; CHECK-NEXT: pandn %xmm2, %xmm1
; CHECK-NEXT: movdqa %xmm1, %xmm2
; CHECK-NEXT: por %xmm0, %xmm2
; CHECK-NEXT: paddd %xmm0, %xmm1
; CHECK-NEXT: psubd %xmm1, %xmm2
; CHECK-NEXT: movdqa %xmm2, %xmm0
; CHECK-NEXT: retq
%xor = xor <2 x i32> %y, <i32 -1, i32 -1>
%and1 = and <2 x i32> %xor, %z
%and2 = and <2 x i32> %x, %y
%or = or <2 x i32> %and1, %and2
%add = add <2 x i32> %and1, %and2
%sub = sub <2 x i32> %or, %add
ret <2 x i32> %sub
}
define <2 x i64> @or_and_and_rhs_neg_vec_i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %z) {
; CHECK-LABEL: or_and_and_rhs_neg_vec_i64:
; CHECK: # %bb.0:
; CHECK-NEXT: pand %xmm1, %xmm2
; CHECK-NEXT: pandn %xmm0, %xmm1
; CHECK-NEXT: movdqa %xmm2, %xmm0
; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: paddq %xmm2, %xmm1
; CHECK-NEXT: psubq %xmm1, %xmm0
; CHECK-NEXT: retq
%and1 = and <2 x i64> %z, %y
%xor = xor <2 x i64> %y, <i64 -1, i64 -1>
%and2 = and <2 x i64> %x, %xor
%or = or <2 x i64> %and1, %and2
%add = add <2 x i64> %and1, %and2
%sub = sub <2 x i64> %or, %add
ret <2 x i64> %sub
}
define <2 x i64> @or_and_and_lhs_neg_vec_i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %z) {
; CHECK-LABEL: or_and_and_lhs_neg_vec_i64:
; CHECK: # %bb.0:
; CHECK-NEXT: pand %xmm1, %xmm2
; CHECK-NEXT: pandn %xmm0, %xmm1
; CHECK-NEXT: movdqa %xmm2, %xmm0
; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: paddq %xmm2, %xmm1
; CHECK-NEXT: psubq %xmm1, %xmm0
; CHECK-NEXT: retq
%and1 = and <2 x i64> %z, %y
%xor = xor <2 x i64> %y, <i64 -1, i64 -1>
%and2 = and <2 x i64> %xor, %x
%or = or <2 x i64> %and1, %and2
%add = add <2 x i64> %and1, %and2
%sub = sub <2 x i64> %or, %add
ret <2 x i64> %sub
}
define <2 x i64> @or_and_rhs_neg_and_vec_i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %z) {
; CHECK-LABEL: or_and_rhs_neg_and_vec_i64:
; CHECK: # %bb.0:
; CHECK-NEXT: pand %xmm1, %xmm0
; CHECK-NEXT: pandn %xmm2, %xmm1
; CHECK-NEXT: movdqa %xmm1, %xmm2
; CHECK-NEXT: por %xmm0, %xmm2
; CHECK-NEXT: paddq %xmm0, %xmm1
; CHECK-NEXT: psubq %xmm1, %xmm2
; CHECK-NEXT: movdqa %xmm2, %xmm0
; CHECK-NEXT: retq
%xor = xor <2 x i64> %y, <i64 -1, i64 -1>
%and1 = and <2 x i64> %z, %xor
%and2 = and <2 x i64> %x, %y
%or = or <2 x i64> %and1, %and2
%add = add <2 x i64> %and1, %and2
%sub = sub <2 x i64> %or, %add
ret <2 x i64> %sub
}
define <2 x i64> @or_and_lhs_neg_and_vec_i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %z) {
; CHECK-LABEL: or_and_lhs_neg_and_vec_i64:
; CHECK: # %bb.0:
; CHECK-NEXT: pand %xmm1, %xmm0
; CHECK-NEXT: pandn %xmm2, %xmm1
; CHECK-NEXT: movdqa %xmm1, %xmm2
; CHECK-NEXT: por %xmm0, %xmm2
; CHECK-NEXT: paddq %xmm0, %xmm1
; CHECK-NEXT: psubq %xmm1, %xmm2
; CHECK-NEXT: movdqa %xmm2, %xmm0
; CHECK-NEXT: retq
%xor = xor <2 x i64> %y, <i64 -1, i64 -1>
%and1 = and <2 x i64> %xor, %z
%and2 = and <2 x i64> %x, %y
%or = or <2 x i64> %and1, %and2
%add = add <2 x i64> %and1, %and2
%sub = sub <2 x i64> %or, %add
ret <2 x i64> %sub
}