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Differential D114273

[AMDGPU] Do not generate ELF symbols for the local branch target labels
ClosedPublic

Authored by RamNalamothu on Nov 19 2021, 12:42 PM.

Details

Reviewers
scott.linder
t-tye
tpr
sebastian-ne
arsenm
Commits
rG18f935122348: [AMDGPU] Do not generate ELF symbols for the local branch target labels
Summary

The compiler was generating symbols in the final code object for local
branch target labels. This bloats the code object, slows down the loader,
and is only used to simplify disassembly.

Use '--symbolize-operands' with llvm-objdump to improve readability of the
branch target operands in disassembly.

Fixes: SWDEV-312223

Diff Detail

Event Timeline

RamNalamothu created this revision.Nov 19 2021, 12:42 PM
Herald added subscribers: foad, wenlei, kerbowa and 10 others. · View Herald TranscriptNov 19 2021, 12:42 PM
RamNalamothu requested review of this revision.Nov 19 2021, 12:42 PM
Herald added a project: Restricted Project. · View Herald TranscriptNov 19 2021, 12:42 PM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
scott.linder accepted this revision.Nov 19 2021, 1:14 PM
This revision is now accepted and ready to land.Nov 19 2021, 1:14 PM
Harbormaster completed remote builds in B135184: Diff 388599.Nov 19 2021, 2:08 PM
This revision was landed with ongoing or failed builds.Nov 19 2021, 9:02 PM
Closed by commit rG18f935122348: [AMDGPU] Do not generate ELF symbols for the local branch target labels (authored by RamNalamothu). · Explain Why
This revision was automatically updated to reflect the committed changes.
RamNalamothu added a commit: rG18f935122348: [AMDGPU] Do not generate ELF symbols for the local branch target labels.
t-tye added a comment.Nov 20 2021, 12:59 PM

@tpr does this change break anything in LLPC?

Flakebi mentioned this in D76427: [AMDGPU][RFC] Use default value for PrivateLabelPrefix.Nov 22 2021, 1:24 AM
tpr added a subscriber: critson.Nov 22 2021, 4:58 AM
In D114273#3144825, @t-tye wrote:

@tpr does this change break anything in LLPC?

@critson identified one LLPC test that this broke because it relied on exact label names, but he has a test fix in https://github.com/GPUOpen-Drivers/llpc/pull/1533

Revision Contents

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AMDGPU/
MCTargetDesc/
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Diff 388684

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp

Show All 22 LinesAMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Triple &TT,
//===------------------------------------------------------------------===// //===------------------------------------------------------------------===//
MinInstAlignment = 4; MinInstAlignment = 4;
// This is the maximum instruction encoded size for gfx10. With a known // This is the maximum instruction encoded size for gfx10. With a known
// subtarget, it can be reduced to 8 bytes. // subtarget, it can be reduced to 8 bytes.
MaxInstLength = (TT.getArch() == Triple::amdgcn) ? 20 : 16; MaxInstLength = (TT.getArch() == Triple::amdgcn) ? 20 : 16;
SeparatorString = "\n"; SeparatorString = "\n";
CommentString = ";"; CommentString = ";";
PrivateLabelPrefix = "";
InlineAsmStart = ";#ASMSTART"; InlineAsmStart = ";#ASMSTART";
InlineAsmEnd = ";#ASMEND"; InlineAsmEnd = ";#ASMEND";
//===--- Data Emission Directives -------------------------------------===// //===--- Data Emission Directives -------------------------------------===//
SunStyleELFSectionSwitchSyntax = true; SunStyleELFSectionSwitchSyntax = true;
UsesELFSectionDirectiveForBSS = true; UsesELFSectionDirectiveForBSS = true;
//===--- Global Variable Emission Directives --------------------------===// //===--- Global Variable Emission Directives --------------------------===//
Show All 32 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll

Show All 28 Lines
; ;
; GCN-LABEL: atomic_add: ; GCN-LABEL: atomic_add:
; GCN: ; %bb.0: ; %.entry ; GCN: ; %bb.0: ; %.entry
; GCN-NEXT: s_mov_b64 s[4:5], exec ; GCN-NEXT: s_mov_b64 s[4:5], exec
; GCN-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s4, 0 ; GCN-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s4, 0
; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s5, v0 ; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s5, v0
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GCN-NEXT: s_and_saveexec_b64 s[6:7], vcc ; GCN-NEXT: s_and_saveexec_b64 s[6:7], vcc
; GCN-NEXT: s_cbranch_execz BB0_2 ; GCN-NEXT: s_cbranch_execz .LBB0_2
; GCN-NEXT: ; %bb.1: ; GCN-NEXT: ; %bb.1:
; GCN-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GCN-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v0, s4 ; GCN-NEXT: v_mov_b32_e32 v0, s4
; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: buffer_atomic_add v0, v1, s[0:3], 0 idxen glc ; GCN-NEXT: buffer_atomic_add v0, v1, s[0:3], 0 idxen glc
; GCN-NEXT: BB0_2: ; GCN-NEXT: .LBB0_2:
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
.entry: .entry:
call i32 @llvm.amdgcn.struct.buffer.atomic.add.i32(i32 1, <4 x i32> %arg, i32 0, i32 0, i32 0, i32 0) call i32 @llvm.amdgcn.struct.buffer.atomic.add.i32(i32 1, <4 x i32> %arg, i32 0, i32 0, i32 0, i32 0)
ret void ret void
} }
define amdgpu_cs void @atomic_add_and_format(<4 x i32> inreg %arg) { define amdgpu_cs void @atomic_add_and_format(<4 x i32> inreg %arg) {
; IR-LABEL: @atomic_add_and_format( ; IR-LABEL: @atomic_add_and_format(
Show All 21 Lines
; GCN-LABEL: atomic_add_and_format: ; GCN-LABEL: atomic_add_and_format:
; GCN: ; %bb.0: ; %.entry ; GCN: ; %bb.0: ; %.entry
; GCN-NEXT: s_mov_b64 s[6:7], exec ; GCN-NEXT: s_mov_b64 s[6:7], exec
; GCN-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0 ; GCN-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0
; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s7, v0 ; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s7, v0
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GCN-NEXT: ; implicit-def: $vgpr1 ; GCN-NEXT: ; implicit-def: $vgpr1
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_cbranch_execz BB1_2 ; GCN-NEXT: s_cbranch_execz .LBB1_2
; GCN-NEXT: ; %bb.1: ; GCN-NEXT: ; %bb.1:
; GCN-NEXT: s_bcnt1_i32_b64 s6, s[6:7] ; GCN-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
; GCN-NEXT: v_mov_b32_e32 v1, s6 ; GCN-NEXT: v_mov_b32_e32 v1, s6
; GCN-NEXT: v_mov_b32_e32 v2, 0 ; GCN-NEXT: v_mov_b32_e32 v2, 0
; GCN-NEXT: buffer_atomic_add v1, v2, s[0:3], 0 idxen glc ; GCN-NEXT: buffer_atomic_add v1, v2, s[0:3], 0 idxen glc
; GCN-NEXT: BB1_2: ; GCN-NEXT: .LBB1_2:
; GCN-NEXT: s_or_b64 exec, exec, s[4:5] ; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_readfirstlane_b32 s4, v1 ; GCN-NEXT: v_readfirstlane_b32 s4, v1
; GCN-NEXT: v_add_i32_e32 v4, vcc, s4, v0 ; GCN-NEXT: v_add_i32_e32 v4, vcc, s4, v0
; GCN-NEXT: s_waitcnt expcnt(0) ; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, s0 ; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1 ; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: v_mov_b32_e32 v2, s2 ; GCN-NEXT: v_mov_b32_e32 v2, s2
Show All 27 Lines
; ;
; GCN-LABEL: atomic_sub: ; GCN-LABEL: atomic_sub:
; GCN: ; %bb.0: ; %.entry ; GCN: ; %bb.0: ; %.entry
; GCN-NEXT: s_mov_b64 s[4:5], exec ; GCN-NEXT: s_mov_b64 s[4:5], exec
; GCN-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s4, 0 ; GCN-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s4, 0
; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s5, v0 ; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s5, v0
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GCN-NEXT: s_and_saveexec_b64 s[6:7], vcc ; GCN-NEXT: s_and_saveexec_b64 s[6:7], vcc
; GCN-NEXT: s_cbranch_execz BB2_2 ; GCN-NEXT: s_cbranch_execz .LBB2_2
; GCN-NEXT: ; %bb.1: ; GCN-NEXT: ; %bb.1:
; GCN-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GCN-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v0, s4 ; GCN-NEXT: v_mov_b32_e32 v0, s4
; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: buffer_atomic_sub v0, v1, s[0:3], 0 idxen glc ; GCN-NEXT: buffer_atomic_sub v0, v1, s[0:3], 0 idxen glc
; GCN-NEXT: BB2_2: ; GCN-NEXT: .LBB2_2:
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
.entry: .entry:
call i32 @llvm.amdgcn.struct.buffer.atomic.sub.i32(i32 1, <4 x i32> %arg, i32 0, i32 0, i32 0, i32 0) call i32 @llvm.amdgcn.struct.buffer.atomic.sub.i32(i32 1, <4 x i32> %arg, i32 0, i32 0, i32 0, i32 0)
ret void ret void
} }
define amdgpu_cs void @atomic_sub_and_format(<4 x i32> inreg %arg) { define amdgpu_cs void @atomic_sub_and_format(<4 x i32> inreg %arg) {
; IR-LABEL: @atomic_sub_and_format( ; IR-LABEL: @atomic_sub_and_format(
Show All 21 Lines
; GCN-LABEL: atomic_sub_and_format: ; GCN-LABEL: atomic_sub_and_format:
; GCN: ; %bb.0: ; %.entry ; GCN: ; %bb.0: ; %.entry
; GCN-NEXT: s_mov_b64 s[6:7], exec ; GCN-NEXT: s_mov_b64 s[6:7], exec
; GCN-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0 ; GCN-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0
; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s7, v0 ; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s7, v0
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GCN-NEXT: ; implicit-def: $vgpr1 ; GCN-NEXT: ; implicit-def: $vgpr1
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_cbranch_execz BB3_2 ; GCN-NEXT: s_cbranch_execz .LBB3_2
; GCN-NEXT: ; %bb.1: ; GCN-NEXT: ; %bb.1:
; GCN-NEXT: s_bcnt1_i32_b64 s6, s[6:7] ; GCN-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
; GCN-NEXT: v_mov_b32_e32 v1, s6 ; GCN-NEXT: v_mov_b32_e32 v1, s6
; GCN-NEXT: v_mov_b32_e32 v2, 0 ; GCN-NEXT: v_mov_b32_e32 v2, 0
; GCN-NEXT: buffer_atomic_sub v1, v2, s[0:3], 0 idxen glc ; GCN-NEXT: buffer_atomic_sub v1, v2, s[0:3], 0 idxen glc
; GCN-NEXT: BB3_2: ; GCN-NEXT: .LBB3_2:
; GCN-NEXT: s_or_b64 exec, exec, s[4:5] ; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_readfirstlane_b32 s4, v1 ; GCN-NEXT: v_readfirstlane_b32 s4, v1
; GCN-NEXT: v_sub_i32_e32 v4, vcc, s4, v0 ; GCN-NEXT: v_sub_i32_e32 v4, vcc, s4, v0
; GCN-NEXT: s_waitcnt expcnt(0) ; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, s0 ; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1 ; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: v_mov_b32_e32 v2, s2 ; GCN-NEXT: v_mov_b32_e32 v2, s2
Show All 28 Lines
; ;
; GCN-LABEL: atomic_xor: ; GCN-LABEL: atomic_xor:
; GCN: ; %bb.0: ; %.entry ; GCN: ; %bb.0: ; %.entry
; GCN-NEXT: s_mov_b64 s[4:5], exec ; GCN-NEXT: s_mov_b64 s[4:5], exec
; GCN-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s4, 0 ; GCN-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s4, 0
; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s5, v0 ; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s5, v0
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GCN-NEXT: s_and_saveexec_b64 s[6:7], vcc ; GCN-NEXT: s_and_saveexec_b64 s[6:7], vcc
; GCN-NEXT: s_cbranch_execz BB4_2 ; GCN-NEXT: s_cbranch_execz .LBB4_2
; GCN-NEXT: ; %bb.1: ; GCN-NEXT: ; %bb.1:
; GCN-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GCN-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
; GCN-NEXT: s_and_b32 s4, s4, 1 ; GCN-NEXT: s_and_b32 s4, s4, 1
; GCN-NEXT: v_mov_b32_e32 v0, s4 ; GCN-NEXT: v_mov_b32_e32 v0, s4
; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: buffer_atomic_xor v0, v1, s[0:3], 0 idxen glc ; GCN-NEXT: buffer_atomic_xor v0, v1, s[0:3], 0 idxen glc
; GCN-NEXT: BB4_2: ; GCN-NEXT: .LBB4_2:
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
.entry: .entry:
call i32 @llvm.amdgcn.struct.buffer.atomic.xor.i32(i32 1, <4 x i32> %arg, i32 0, i32 0, i32 0, i32 0) call i32 @llvm.amdgcn.struct.buffer.atomic.xor.i32(i32 1, <4 x i32> %arg, i32 0, i32 0, i32 0, i32 0)
ret void ret void
} }
define amdgpu_cs void @atomic_xor_and_format(<4 x i32> inreg %arg) { define amdgpu_cs void @atomic_xor_and_format(<4 x i32> inreg %arg) {
; IR-LABEL: @atomic_xor_and_format( ; IR-LABEL: @atomic_xor_and_format(
Show All 23 Lines
; GCN-LABEL: atomic_xor_and_format: ; GCN-LABEL: atomic_xor_and_format:
; GCN: ; %bb.0: ; %.entry ; GCN: ; %bb.0: ; %.entry
; GCN-NEXT: s_mov_b64 s[6:7], exec ; GCN-NEXT: s_mov_b64 s[6:7], exec
; GCN-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0 ; GCN-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0
; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s7, v0 ; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s7, v0
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GCN-NEXT: ; implicit-def: $vgpr1 ; GCN-NEXT: ; implicit-def: $vgpr1
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_cbranch_execz BB5_2 ; GCN-NEXT: s_cbranch_execz .LBB5_2
; GCN-NEXT: ; %bb.1: ; GCN-NEXT: ; %bb.1:
; GCN-NEXT: s_bcnt1_i32_b64 s6, s[6:7] ; GCN-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
; GCN-NEXT: s_and_b32 s6, s6, 1 ; GCN-NEXT: s_and_b32 s6, s6, 1
; GCN-NEXT: v_mov_b32_e32 v1, s6 ; GCN-NEXT: v_mov_b32_e32 v1, s6
; GCN-NEXT: v_mov_b32_e32 v2, 0 ; GCN-NEXT: v_mov_b32_e32 v2, 0
; GCN-NEXT: buffer_atomic_xor v1, v2, s[0:3], 0 idxen glc ; GCN-NEXT: buffer_atomic_xor v1, v2, s[0:3], 0 idxen glc
; GCN-NEXT: BB5_2: ; GCN-NEXT: .LBB5_2:
; GCN-NEXT: s_or_b64 exec, exec, s[4:5] ; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_readfirstlane_b32 s4, v1 ; GCN-NEXT: v_readfirstlane_b32 s4, v1
; GCN-NEXT: v_and_b32_e32 v0, 1, v0 ; GCN-NEXT: v_and_b32_e32 v0, 1, v0
; GCN-NEXT: v_xor_b32_e32 v4, s4, v0 ; GCN-NEXT: v_xor_b32_e32 v4, s4, v0
; GCN-NEXT: s_waitcnt expcnt(0) ; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, s0 ; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1 ; GCN-NEXT: v_mov_b32_e32 v1, s1
Show All 9 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
define amdgpu_kernel void @sgpr_trunc_brcond(i32 %cond) { define amdgpu_kernel void @sgpr_trunc_brcond(i32 %cond) {
; GCN-LABEL: sgpr_trunc_brcond: ; GCN-LABEL: sgpr_trunc_brcond:
; GCN: ; %bb.0: ; %entry ; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_load_dword s0, s[0:1], 0x9 ; GCN-NEXT: s_load_dword s0, s[0:1], 0x9
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_xor_b32 s0, s0, -1 ; GCN-NEXT: s_xor_b32 s0, s0, -1
; GCN-NEXT: s_and_b32 s0, s0, 1 ; GCN-NEXT: s_and_b32 s0, s0, 1
; GCN-NEXT: s_cmp_lg_u32 s0, 0 ; GCN-NEXT: s_cmp_lg_u32 s0, 0
; GCN-NEXT: s_cbranch_scc1 BB3_2 ; GCN-NEXT: s_cbranch_scc1 .LBB3_2
; GCN-NEXT: ; %bb.1: ; %bb0 ; GCN-NEXT: ; %bb.1: ; %bb0
; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: flat_store_dword v[0:1], v0 ; GCN-NEXT: flat_store_dword v[0:1], v0
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: BB3_2: ; %bb1 ; GCN-NEXT: .LBB3_2: ; %bb1
; GCN-NEXT: v_mov_b32_e32 v0, 1 ; GCN-NEXT: v_mov_b32_e32 v0, 1
; GCN-NEXT: flat_store_dword v[0:1], v0 ; GCN-NEXT: flat_store_dword v[0:1], v0
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
entry: entry:
%trunc = trunc i32 %cond to i1 %trunc = trunc i32 %cond to i1
br i1 %trunc, label %bb0, label %bb1 br i1 %trunc, label %bb0, label %bb1
bb0: bb0:
Show All 9 Lines
; GCN-LABEL: brcond_sgpr_trunc_and: ; GCN-LABEL: brcond_sgpr_trunc_and:
; GCN: ; %bb.0: ; %entry ; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_and_b32 s0, s0, s1 ; GCN-NEXT: s_and_b32 s0, s0, s1
; GCN-NEXT: s_xor_b32 s0, s0, -1 ; GCN-NEXT: s_xor_b32 s0, s0, -1
; GCN-NEXT: s_and_b32 s0, s0, 1 ; GCN-NEXT: s_and_b32 s0, s0, 1
; GCN-NEXT: s_cmp_lg_u32 s0, 0 ; GCN-NEXT: s_cmp_lg_u32 s0, 0
; GCN-NEXT: s_cbranch_scc1 BB4_2 ; GCN-NEXT: s_cbranch_scc1 .LBB4_2
; GCN-NEXT: ; %bb.1: ; %bb0 ; GCN-NEXT: ; %bb.1: ; %bb0
; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: flat_store_dword v[0:1], v0 ; GCN-NEXT: flat_store_dword v[0:1], v0
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: BB4_2: ; %bb1 ; GCN-NEXT: .LBB4_2: ; %bb1
; GCN-NEXT: v_mov_b32_e32 v0, 1 ; GCN-NEXT: v_mov_b32_e32 v0, 1
; GCN-NEXT: flat_store_dword v[0:1], v0 ; GCN-NEXT: flat_store_dword v[0:1], v0
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
entry: entry:
%trunc0 = trunc i32 %cond0 to i1 %trunc0 = trunc i32 %cond0 to i1
%trunc1 = trunc i32 %cond1 to i1 %trunc1 = trunc i32 %cond1 to i1
%and = and i1 %trunc0, %trunc1 %and = and i1 %trunc0, %trunc1
br i1 %and, label %bb0, label %bb1 br i1 %and, label %bb0, label %bb1
Show All 9 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -amdgpu-global-isel-risky-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -global-isel -amdgpu-global-isel-risky-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s
; Make sure the branch targets are correct after lowering llvm.amdgcn.if ; Make sure the branch targets are correct after lowering llvm.amdgcn.if
define i32 @divergent_if_swap_brtarget_order0(i32 %value) { define i32 @divergent_if_swap_brtarget_order0(i32 %value) {
; CHECK-LABEL: divergent_if_swap_brtarget_order0: ; CHECK-LABEL: divergent_if_swap_brtarget_order0:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; CHECK-NEXT: ; implicit-def: $vgpr0 ; CHECK-NEXT: ; implicit-def: $vgpr0
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CHECK-NEXT: s_cbranch_execz BB0_2 ; CHECK-NEXT: s_cbranch_execz .LBB0_2
; CHECK-NEXT: ; %bb.1: ; %if.true ; CHECK-NEXT: ; %bb.1: ; %if.true
; CHECK-NEXT: global_load_dword v0, v[0:1], off glc ; CHECK-NEXT: global_load_dword v0, v[0:1], off glc
; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: BB0_2: ; %endif ; CHECK-NEXT: .LBB0_2: ; %endif
; CHECK-NEXT: s_or_b64 exec, exec, s[4:5] ; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: s_setpc_b64 s[30:31] ; CHECK-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%c = icmp ne i32 %value, 0 %c = icmp ne i32 %value, 0
br i1 %c, label %if.true, label %endif br i1 %c, label %if.true, label %endif
if.true: if.true:
%val = load volatile i32, i32 addrspace(1)* undef %val = load volatile i32, i32 addrspace(1)* undef
br label %endif br label %endif
endif: endif:
%v = phi i32 [ %val, %if.true ], [ undef, %entry ] %v = phi i32 [ %val, %if.true ], [ undef, %entry ]
ret i32 %v ret i32 %v
} }
define i32 @divergent_if_swap_brtarget_order1(i32 %value) { define i32 @divergent_if_swap_brtarget_order1(i32 %value) {
; CHECK-LABEL: divergent_if_swap_brtarget_order1: ; CHECK-LABEL: divergent_if_swap_brtarget_order1:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; CHECK-NEXT: ; implicit-def: $vgpr0 ; CHECK-NEXT: ; implicit-def: $vgpr0
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CHECK-NEXT: s_cbranch_execz BB1_2 ; CHECK-NEXT: s_cbranch_execz .LBB1_2
; CHECK-NEXT: ; %bb.1: ; %if.true ; CHECK-NEXT: ; %bb.1: ; %if.true
; CHECK-NEXT: global_load_dword v0, v[0:1], off glc ; CHECK-NEXT: global_load_dword v0, v[0:1], off glc
; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: BB1_2: ; %endif ; CHECK-NEXT: .LBB1_2: ; %endif
; CHECK-NEXT: s_or_b64 exec, exec, s[4:5] ; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: s_setpc_b64 s[30:31] ; CHECK-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%c = icmp ne i32 %value, 0 %c = icmp ne i32 %value, 0
br i1 %c, label %if.true, label %endif br i1 %c, label %if.true, label %endif
endif: endif:
Show All 9 Lines
define i32 @divergent_if_nonboolean_condition0(i32 %value) { define i32 @divergent_if_nonboolean_condition0(i32 %value) {
; CHECK-LABEL: divergent_if_nonboolean_condition0: ; CHECK-LABEL: divergent_if_nonboolean_condition0:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_and_b32_e32 v0, 1, v0 ; CHECK-NEXT: v_and_b32_e32 v0, 1, v0
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; CHECK-NEXT: ; implicit-def: $vgpr0 ; CHECK-NEXT: ; implicit-def: $vgpr0
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CHECK-NEXT: s_cbranch_execz BB2_2 ; CHECK-NEXT: s_cbranch_execz .LBB2_2
; CHECK-NEXT: ; %bb.1: ; %if.true ; CHECK-NEXT: ; %bb.1: ; %if.true
; CHECK-NEXT: global_load_dword v0, v[0:1], off glc ; CHECK-NEXT: global_load_dword v0, v[0:1], off glc
; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: BB2_2: ; %endif ; CHECK-NEXT: .LBB2_2: ; %endif
; CHECK-NEXT: s_or_b64 exec, exec, s[4:5] ; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: s_setpc_b64 s[30:31] ; CHECK-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%c = trunc i32 %value to i1 %c = trunc i32 %value to i1
br i1 %c, label %if.true, label %endif br i1 %c, label %if.true, label %endif
if.true: if.true:
Show All 11 Lines
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: global_load_dword v0, v[0:1], off ; CHECK-NEXT: global_load_dword v0, v[0:1], off
; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: v_and_b32_e32 v0, 1, v0 ; CHECK-NEXT: v_and_b32_e32 v0, 1, v0
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; CHECK-NEXT: ; implicit-def: $vgpr0 ; CHECK-NEXT: ; implicit-def: $vgpr0
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CHECK-NEXT: s_cbranch_execz BB3_2 ; CHECK-NEXT: s_cbranch_execz .LBB3_2
; CHECK-NEXT: ; %bb.1: ; %if.true ; CHECK-NEXT: ; %bb.1: ; %if.true
; CHECK-NEXT: global_load_dword v0, v[0:1], off glc ; CHECK-NEXT: global_load_dword v0, v[0:1], off glc
; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: BB3_2: ; %endif ; CHECK-NEXT: .LBB3_2: ; %endif
; CHECK-NEXT: s_or_b64 exec, exec, s[4:5] ; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: s_setpc_b64 s[30:31] ; CHECK-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%value = load i32, i32 addrspace(1)* %ptr %value = load i32, i32 addrspace(1)* %ptr
%c = trunc i32 %value to i1 %c = trunc i32 %value to i1
br i1 %c, label %if.true, label %endif br i1 %c, label %if.true, label %endif
Show All 18 Lines
; CHECK-NEXT: s_getpc_b64 s[4:5] ; CHECK-NEXT: s_getpc_b64 s[4:5]
; CHECK-NEXT: s_add_u32 s4, s4, external_constant@gotpcrel32@lo+4 ; CHECK-NEXT: s_add_u32 s4, s4, external_constant@gotpcrel32@lo+4
; CHECK-NEXT: s_addc_u32 s5, s5, external_constant@gotpcrel32@hi+12 ; CHECK-NEXT: s_addc_u32 s5, s5, external_constant@gotpcrel32@hi+12
; CHECK-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 ; CHECK-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
; CHECK-NEXT: s_waitcnt lgkmcnt(0) ; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: s_load_dword s4, s[4:5], 0x0 ; CHECK-NEXT: s_load_dword s4, s[4:5], 0x0
; CHECK-NEXT: s_waitcnt lgkmcnt(0) ; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: s_cmp_lg_u32 s4, 0 ; CHECK-NEXT: s_cmp_lg_u32 s4, 0
; CHECK-NEXT: s_cbranch_scc1 BB4_4 ; CHECK-NEXT: s_cbranch_scc1 .LBB4_4
; CHECK-NEXT: ; %bb.1: ; %bb2 ; CHECK-NEXT: ; %bb.1: ; %bb2
; CHECK-NEXT: s_getpc_b64 s[6:7] ; CHECK-NEXT: s_getpc_b64 s[6:7]
; CHECK-NEXT: s_add_u32 s6, s6, const.ptr@gotpcrel32@lo+4 ; CHECK-NEXT: s_add_u32 s6, s6, const.ptr@gotpcrel32@lo+4
; CHECK-NEXT: s_addc_u32 s7, s7, const.ptr@gotpcrel32@hi+12 ; CHECK-NEXT: s_addc_u32 s7, s7, const.ptr@gotpcrel32@hi+12
; CHECK-NEXT: s_load_dwordx2 s[6:7], s[6:7], 0x0 ; CHECK-NEXT: s_load_dwordx2 s[6:7], s[6:7], 0x0
; CHECK-NEXT: v_mov_b32_e32 v0, 0 ; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: s_mov_b32 s4, -1 ; CHECK-NEXT: s_mov_b32 s4, -1
; CHECK-NEXT: s_waitcnt lgkmcnt(0) ; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: s_load_dwordx2 s[6:7], s[6:7], 0x0 ; CHECK-NEXT: s_load_dwordx2 s[6:7], s[6:7], 0x0
; CHECK-NEXT: s_waitcnt lgkmcnt(0) ; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: global_load_dword v0, v0, s[6:7] ; CHECK-NEXT: global_load_dword v0, v0, s[6:7]
; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: v_cmp_gt_f32_e32 vcc, 1.0, v0 ; CHECK-NEXT: v_cmp_gt_f32_e32 vcc, 1.0, v0
; CHECK-NEXT: s_cbranch_vccnz BB4_3 ; CHECK-NEXT: s_cbranch_vccnz .LBB4_3
; CHECK-NEXT: ; %bb.2: ; %bb7 ; CHECK-NEXT: ; %bb.2: ; %bb7
; CHECK-NEXT: s_mov_b32 s4, 0 ; CHECK-NEXT: s_mov_b32 s4, 0
; CHECK-NEXT: BB4_3: ; %bb8 ; CHECK-NEXT: .LBB4_3: ; %bb8
; CHECK-NEXT: s_cmp_lg_u32 s4, 0 ; CHECK-NEXT: s_cmp_lg_u32 s4, 0
; CHECK-NEXT: s_cbranch_scc0 BB4_5 ; CHECK-NEXT: s_cbranch_scc0 .LBB4_5
; CHECK-NEXT: BB4_4: ; %bb12 ; CHECK-NEXT: .LBB4_4: ; %bb12
; CHECK-NEXT: s_setpc_b64 s[30:31] ; CHECK-NEXT: s_setpc_b64 s[30:31]
; CHECK-NEXT: BB4_5: ; %bb11 ; CHECK-NEXT: .LBB4_5: ; %bb11
; CHECK-NEXT: v_mov_b32_e32 v0, 4.0 ; CHECK-NEXT: v_mov_b32_e32 v0, 4.0
; CHECK-NEXT: buffer_store_dword v0, v0, s[0:3], 0 offen ; CHECK-NEXT: buffer_store_dword v0, v0, s[0:3], 0 offen
; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: s_setpc_b64 s[30:31] ; CHECK-NEXT: s_setpc_b64 s[30:31]
bb: bb:
%tmp = load i32, i32 addrspace(4)* @external_constant %tmp = load i32, i32 addrspace(4)* @external_constant
%ptr = load float*, float* addrspace(4)* @const.ptr %ptr = load float*, float* addrspace(4)* @const.ptr
%tmp1 = icmp ne i32 %tmp, 0 %tmp1 = icmp ne i32 %tmp, 0
Show All 24 Lines
define amdgpu_kernel void @break_loop(i32 %arg) { define amdgpu_kernel void @break_loop(i32 %arg) {
; CHECK-LABEL: break_loop: ; CHECK-LABEL: break_loop:
; CHECK: ; %bb.0: ; %bb ; CHECK: ; %bb.0: ; %bb
; CHECK-NEXT: s_load_dword s2, s[4:5], 0x0 ; CHECK-NEXT: s_load_dword s2, s[4:5], 0x0
; CHECK-NEXT: s_mov_b64 s[0:1], 0 ; CHECK-NEXT: s_mov_b64 s[0:1], 0
; CHECK-NEXT: ; implicit-def: $vgpr1 ; CHECK-NEXT: ; implicit-def: $vgpr1
; CHECK-NEXT: s_waitcnt lgkmcnt(0) ; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_subrev_u32_e32 v0, s2, v0 ; CHECK-NEXT: v_subrev_u32_e32 v0, s2, v0
; CHECK-NEXT: s_branch BB5_2 ; CHECK-NEXT: s_branch .LBB5_2
; CHECK-NEXT: BB5_1: ; %Flow ; CHECK-NEXT: .LBB5_1: ; %Flow
; CHECK-NEXT: ; in Loop: Header=BB5_2 Depth=1 ; CHECK-NEXT: ; in Loop: Header=BB5_2 Depth=1
; CHECK-NEXT: s_and_b64 s[2:3], exec, s[2:3] ; CHECK-NEXT: s_and_b64 s[2:3], exec, s[2:3]
; CHECK-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1] ; CHECK-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
; CHECK-NEXT: s_andn2_b64 exec, exec, s[0:1] ; CHECK-NEXT: s_andn2_b64 exec, exec, s[0:1]
; CHECK-NEXT: s_cbranch_execz BB5_4 ; CHECK-NEXT: s_cbranch_execz .LBB5_4
; CHECK-NEXT: BB5_2: ; %bb1 ; CHECK-NEXT: .LBB5_2: ; %bb1
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: v_add_u32_e32 v1, 1, v1 ; CHECK-NEXT: v_add_u32_e32 v1, 1, v1
; CHECK-NEXT: v_cmp_le_i32_e32 vcc, 0, v1 ; CHECK-NEXT: v_cmp_le_i32_e32 vcc, 0, v1
; CHECK-NEXT: s_mov_b64 s[2:3], -1 ; CHECK-NEXT: s_mov_b64 s[2:3], -1
; CHECK-NEXT: s_cbranch_vccnz BB5_1 ; CHECK-NEXT: s_cbranch_vccnz .LBB5_1
; CHECK-NEXT: ; %bb.3: ; %bb4 ; CHECK-NEXT: ; %bb.3: ; %bb4
; CHECK-NEXT: ; in Loop: Header=BB5_2 Depth=1 ; CHECK-NEXT: ; in Loop: Header=BB5_2 Depth=1
; CHECK-NEXT: global_load_dword v2, v[0:1], off glc ; CHECK-NEXT: global_load_dword v2, v[0:1], off glc
; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: v_cmp_ge_i32_e64 s[2:3], v0, v2 ; CHECK-NEXT: v_cmp_ge_i32_e64 s[2:3], v0, v2
; CHECK-NEXT: s_branch BB5_1 ; CHECK-NEXT: s_branch .LBB5_1
; CHECK-NEXT: BB5_4: ; %bb9 ; CHECK-NEXT: .LBB5_4: ; %bb9
; CHECK-NEXT: s_endpgm ; CHECK-NEXT: s_endpgm
bb: bb:
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%tmp = sub i32 %id, %arg %tmp = sub i32 %id, %arg
br label %bb1 br label %bb1
bb1: bb1:
%lsr.iv = phi i32 [ undef, %bb ], [ %lsr.iv.next, %bb4 ] %lsr.iv = phi i32 [ undef, %bb ], [ %lsr.iv.next, %bb4 ]
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llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll

Show First 20 Lines • Show All 943 Lines • ▼ Show 20 Lines
; GFX7-NEXT: v_mov_b32_e32 v2, 0 ; GFX7-NEXT: v_mov_b32_e32 v2, 0
; GFX7-NEXT: s_mov_b32 s10, 0 ; GFX7-NEXT: s_mov_b32 s10, 0
; GFX7-NEXT: s_mov_b32 s11, 0xf000 ; GFX7-NEXT: s_mov_b32 s11, 0xf000
; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: buffer_load_dwordx3 v[1:3], v[1:2], s[8:11], 0 addr64 ; GFX7-NEXT: buffer_load_dwordx3 v[1:3], v[1:2], s[8:11], 0 addr64
; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s6, 0
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX7-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX7-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX7-NEXT: s_cbranch_execz BB13_2 ; GFX7-NEXT: s_cbranch_execz .LBB13_2
; GFX7-NEXT: ; %bb.1: ; %bb ; GFX7-NEXT: ; %bb.1: ; %bb
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x1d ; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x1d
; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX7-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_cmp_lg_u32 s0, 0 ; GFX7-NEXT: s_cmp_lg_u32 s0, 0
; GFX7-NEXT: s_cselect_b32 s6, 1, 0 ; GFX7-NEXT: s_cselect_b32 s6, 1, 0
; GFX7-NEXT: BB13_2: ; %exit ; GFX7-NEXT: .LBB13_2: ; %exit
; GFX7-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX7-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX7-NEXT: s_and_b32 s0, 1, s6 ; GFX7-NEXT: s_and_b32 s0, 1, s6
; GFX7-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 ; GFX7-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GFX7-NEXT: s_mov_b32 s10, -1 ; GFX7-NEXT: s_mov_b32 s10, -1
; GFX7-NEXT: s_mov_b64 s[6:7], s[10:11] ; GFX7-NEXT: s_mov_b64 s[6:7], s[10:11]
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_nop 0 ; GFX7-NEXT: s_nop 0
; GFX7-NEXT: v_div_fmas_f32 v0, v1, v2, v3 ; GFX7-NEXT: v_div_fmas_f32 v0, v1, v2, v3
Show All 9 Lines
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v1, s4 ; GFX8-NEXT: v_mov_b32_e32 v1, s4
; GFX8-NEXT: v_mov_b32_e32 v2, s5 ; GFX8-NEXT: v_mov_b32_e32 v2, s5
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v3 ; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v3
; GFX8-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc ; GFX8-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc
; GFX8-NEXT: flat_load_dwordx3 v[1:3], v[1:2] ; GFX8-NEXT: flat_load_dwordx3 v[1:3], v[1:2]
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX8-NEXT: s_cbranch_execz BB13_2 ; GFX8-NEXT: s_cbranch_execz .LBB13_2
; GFX8-NEXT: ; %bb.1: ; %bb ; GFX8-NEXT: ; %bb.1: ; %bb
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x74 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x74
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX8-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_cmp_lg_u32 s0, 0 ; GFX8-NEXT: s_cmp_lg_u32 s0, 0
; GFX8-NEXT: s_cselect_b32 s6, 1, 0 ; GFX8-NEXT: s_cselect_b32 s6, 1, 0
; GFX8-NEXT: BB13_2: ; %exit ; GFX8-NEXT: .LBB13_2: ; %exit
; GFX8-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX8-NEXT: s_add_u32 s0, s2, 8 ; GFX8-NEXT: s_add_u32 s0, s2, 8
; GFX8-NEXT: s_addc_u32 s1, s3, 0 ; GFX8-NEXT: s_addc_u32 s1, s3, 0
; GFX8-NEXT: s_and_b32 s2, 1, s6 ; GFX8-NEXT: s_and_b32 s2, 1, s6
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2 ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_nop 2 ; GFX8-NEXT: s_nop 2
; GFX8-NEXT: v_div_fmas_f32 v2, v1, v2, v3 ; GFX8-NEXT: v_div_fmas_f32 v2, v1, v2, v3
; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_store_dword v[0:1], v2 ; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX10_W32-LABEL: test_div_fmas_f32_i1_phi_vcc: ; GFX10_W32-LABEL: test_div_fmas_f32_i1_phi_vcc:
; GFX10_W32: ; %bb.0: ; %entry ; GFX10_W32: ; %bb.0: ; %entry
; GFX10_W32-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x4c ; GFX10_W32-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x4c
; GFX10_W32-NEXT: v_lshlrev_b32_e32 v1, 2, v0 ; GFX10_W32-NEXT: v_lshlrev_b32_e32 v1, 2, v0
; GFX10_W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX10_W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX10_W32-NEXT: s_mov_b32 s5, 0 ; GFX10_W32-NEXT: s_mov_b32 s5, 0
; GFX10_W32-NEXT: s_waitcnt lgkmcnt(0) ; GFX10_W32-NEXT: s_waitcnt lgkmcnt(0)
; GFX10_W32-NEXT: global_load_dwordx3 v[1:3], v1, s[2:3] ; GFX10_W32-NEXT: global_load_dwordx3 v[1:3], v1, s[2:3]
; GFX10_W32-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10_W32-NEXT: s_waitcnt_depctr 0xffe3
; GFX10_W32-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX10_W32-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX10_W32-NEXT: s_and_saveexec_b32 s4, vcc_lo ; GFX10_W32-NEXT: s_and_saveexec_b32 s4, vcc_lo
; GFX10_W32-NEXT: s_cbranch_execz BB13_2 ; GFX10_W32-NEXT: s_cbranch_execz .LBB13_2
; GFX10_W32-NEXT: ; %bb.1: ; %bb ; GFX10_W32-NEXT: ; %bb.1: ; %bb
; GFX10_W32-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x74 ; GFX10_W32-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x74
; GFX10_W32-NEXT: s_waitcnt lgkmcnt(0) ; GFX10_W32-NEXT: s_waitcnt lgkmcnt(0)
; GFX10_W32-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX10_W32-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10_W32-NEXT: s_waitcnt lgkmcnt(0) ; GFX10_W32-NEXT: s_waitcnt lgkmcnt(0)
; GFX10_W32-NEXT: s_cmp_lg_u32 s0, 0 ; GFX10_W32-NEXT: s_cmp_lg_u32 s0, 0
; GFX10_W32-NEXT: s_cselect_b32 s5, 1, 0 ; GFX10_W32-NEXT: s_cselect_b32 s5, 1, 0
; GFX10_W32-NEXT: BB13_2: ; %exit ; GFX10_W32-NEXT: .LBB13_2: ; %exit
; GFX10_W32-NEXT: s_or_b32 exec_lo, exec_lo, s4 ; GFX10_W32-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10_W32-NEXT: s_and_b32 s0, 1, s5 ; GFX10_W32-NEXT: s_and_b32 s0, 1, s5
; GFX10_W32-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 ; GFX10_W32-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; GFX10_W32-NEXT: s_waitcnt vmcnt(0) ; GFX10_W32-NEXT: s_waitcnt vmcnt(0)
; GFX10_W32-NEXT: v_div_fmas_f32 v0, v1, v2, v3 ; GFX10_W32-NEXT: v_div_fmas_f32 v0, v1, v2, v3
; GFX10_W32-NEXT: v_mov_b32_e32 v1, 0 ; GFX10_W32-NEXT: v_mov_b32_e32 v1, 0
; GFX10_W32-NEXT: s_waitcnt lgkmcnt(0) ; GFX10_W32-NEXT: s_waitcnt lgkmcnt(0)
; GFX10_W32-NEXT: global_store_dword v1, v0, s[2:3] offset:8 ; GFX10_W32-NEXT: global_store_dword v1, v0, s[2:3] offset:8
; GFX10_W32-NEXT: s_endpgm ; GFX10_W32-NEXT: s_endpgm
; ;
; GFX10_W64-LABEL: test_div_fmas_f32_i1_phi_vcc: ; GFX10_W64-LABEL: test_div_fmas_f32_i1_phi_vcc:
; GFX10_W64: ; %bb.0: ; %entry ; GFX10_W64: ; %bb.0: ; %entry
; GFX10_W64-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x4c ; GFX10_W64-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x4c
; GFX10_W64-NEXT: v_lshlrev_b32_e32 v1, 2, v0 ; GFX10_W64-NEXT: v_lshlrev_b32_e32 v1, 2, v0
; GFX10_W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX10_W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX10_W64-NEXT: s_mov_b32 s6, 0 ; GFX10_W64-NEXT: s_mov_b32 s6, 0
; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10_W64-NEXT: global_load_dwordx3 v[1:3], v1, s[2:3] ; GFX10_W64-NEXT: global_load_dwordx3 v[1:3], v1, s[2:3]
; GFX10_W64-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10_W64-NEXT: s_waitcnt_depctr 0xffe3
; GFX10_W64-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX10_W64-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX10_W64-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX10_W64-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX10_W64-NEXT: s_cbranch_execz BB13_2 ; GFX10_W64-NEXT: s_cbranch_execz .LBB13_2
; GFX10_W64-NEXT: ; %bb.1: ; %bb ; GFX10_W64-NEXT: ; %bb.1: ; %bb
; GFX10_W64-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x74 ; GFX10_W64-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x74
; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10_W64-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX10_W64-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10_W64-NEXT: s_cmp_lg_u32 s0, 0 ; GFX10_W64-NEXT: s_cmp_lg_u32 s0, 0
; GFX10_W64-NEXT: s_cselect_b32 s6, 1, 0 ; GFX10_W64-NEXT: s_cselect_b32 s6, 1, 0
; GFX10_W64-NEXT: BB13_2: ; %exit ; GFX10_W64-NEXT: .LBB13_2: ; %exit
; GFX10_W64-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX10_W64-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX10_W64-NEXT: s_and_b32 s0, 1, s6 ; GFX10_W64-NEXT: s_and_b32 s0, 1, s6
; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 ; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GFX10_W64-NEXT: s_waitcnt vmcnt(0) ; GFX10_W64-NEXT: s_waitcnt vmcnt(0)
; GFX10_W64-NEXT: v_div_fmas_f32 v0, v1, v2, v3 ; GFX10_W64-NEXT: v_div_fmas_f32 v0, v1, v2, v3
; GFX10_W64-NEXT: v_mov_b32_e32 v1, 0 ; GFX10_W64-NEXT: v_mov_b32_e32 v1, 0
; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10_W64-NEXT: global_store_dword v1, v0, s[2:3] offset:8 ; GFX10_W64-NEXT: global_store_dword v1, v0, s[2:3] offset:8
Show All 32 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
define amdgpu_kernel void @test_wave32(i32 %arg0, [8 x i32], i32 %saved) { define amdgpu_kernel void @test_wave32(i32 %arg0, [8 x i32], i32 %saved) {
; GCN-LABEL: test_wave32: ; GCN-LABEL: test_wave32:
; GCN: ; %bb.0: ; %entry ; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_clause 0x1 ; GCN-NEXT: s_clause 0x1
; GCN-NEXT: s_load_dword s1, s[4:5], 0x0 ; GCN-NEXT: s_load_dword s1, s[4:5], 0x0
; GCN-NEXT: s_load_dword s0, s[4:5], 0x24 ; GCN-NEXT: s_load_dword s0, s[4:5], 0x24
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_cmp_lg_u32 s1, 0 ; GCN-NEXT: s_cmp_lg_u32 s1, 0
; GCN-NEXT: s_cbranch_scc1 BB0_2 ; GCN-NEXT: s_cbranch_scc1 .LBB0_2
; GCN-NEXT: ; %bb.1: ; %mid ; GCN-NEXT: ; %bb.1: ; %mid
; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: global_store_dword v[0:1], v0, off ; GCN-NEXT: global_store_dword v[0:1], v0, off
; GCN-NEXT: s_waitcnt_vscnt null, 0x0 ; GCN-NEXT: s_waitcnt_vscnt null, 0x0
; GCN-NEXT: BB0_2: ; %bb ; GCN-NEXT: .LBB0_2: ; %bb
; GCN-NEXT: s_waitcnt_depctr 0xffe3 ; GCN-NEXT: s_waitcnt_depctr 0xffe3
; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s0 ; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: global_store_dword v[0:1], v0, off ; GCN-NEXT: global_store_dword v[0:1], v0, off
; GCN-NEXT: s_waitcnt_vscnt null, 0x0 ; GCN-NEXT: s_waitcnt_vscnt null, 0x0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
entry: entry:
%cond = icmp eq i32 %arg0, 0 %cond = icmp eq i32 %arg0, 0
Show All 13 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
define amdgpu_kernel void @test_wave64(i32 %arg0, i64 %saved) { define amdgpu_kernel void @test_wave64(i32 %arg0, i64 %saved) {
; GCN-LABEL: test_wave64: ; GCN-LABEL: test_wave64:
; GCN: ; %bb.0: ; %entry ; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_load_dword s2, s[4:5], 0x0 ; GCN-NEXT: s_load_dword s2, s[4:5], 0x0
; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8 ; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_cmp_lg_u32 s2, 0 ; GCN-NEXT: s_cmp_lg_u32 s2, 0
; GCN-NEXT: s_cbranch_scc1 BB0_2 ; GCN-NEXT: s_cbranch_scc1 .LBB0_2
; GCN-NEXT: ; %bb.1: ; %mid ; GCN-NEXT: ; %bb.1: ; %mid
; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: global_store_dword v[0:1], v0, off ; GCN-NEXT: global_store_dword v[0:1], v0, off
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: BB0_2: ; %bb ; GCN-NEXT: .LBB0_2: ; %bb
; GCN-NEXT: s_or_b64 exec, exec, s[0:1] ; GCN-NEXT: s_or_b64 exec, exec, s[0:1]
; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: global_store_dword v[0:1], v0, off ; GCN-NEXT: global_store_dword v[0:1], v0, off
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
entry: entry:
%cond = icmp eq i32 %arg0, 0 %cond = icmp eq i32 %arg0, 0
br i1 %cond, label %mid, label %bb br i1 %cond, label %mid, label %bb
Show All 12 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll

Show First 20 Lines • Show All 153 Lines • ▼ Show 20 Lines
; GFX1030-NEXT: v_mov_b32_e32 v22, v4 ; GFX1030-NEXT: v_mov_b32_e32 v22, v4
; GFX1030-NEXT: v_mov_b32_e32 v23, v6 ; GFX1030-NEXT: v_mov_b32_e32 v23, v6
; GFX1030-NEXT: v_mov_b32_e32 v24, v7 ; GFX1030-NEXT: v_mov_b32_e32 v24, v7
; GFX1030-NEXT: v_mov_b32_e32 v25, v8 ; GFX1030-NEXT: v_mov_b32_e32 v25, v8
; GFX1030-NEXT: v_mov_b32_e32 v26, v10 ; GFX1030-NEXT: v_mov_b32_e32 v26, v10
; GFX1030-NEXT: v_mov_b32_e32 v27, v11 ; GFX1030-NEXT: v_mov_b32_e32 v27, v11
; GFX1030-NEXT: v_mov_b32_e32 v28, v12 ; GFX1030-NEXT: v_mov_b32_e32 v28, v12
; GFX1030-NEXT: s_mov_b32 s1, exec_lo ; GFX1030-NEXT: s_mov_b32 s1, exec_lo
; GFX1030-NEXT: BB6_1: ; =>This Inner Loop Header: Depth=1 ; GFX1030-NEXT: .LBB6_1: ; =>This Inner Loop Header: Depth=1
; GFX1030-NEXT: v_readfirstlane_b32 s4, v14 ; GFX1030-NEXT: v_readfirstlane_b32 s4, v14
; GFX1030-NEXT: v_readfirstlane_b32 s5, v15 ; GFX1030-NEXT: v_readfirstlane_b32 s5, v15
; GFX1030-NEXT: v_readfirstlane_b32 s6, v16 ; GFX1030-NEXT: v_readfirstlane_b32 s6, v16
; GFX1030-NEXT: v_readfirstlane_b32 s7, v17 ; GFX1030-NEXT: v_readfirstlane_b32 s7, v17
; GFX1030-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[14:15] ; GFX1030-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[14:15]
; GFX1030-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[16:17] ; GFX1030-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[16:17]
; GFX1030-NEXT: s_and_b32 s0, s0, vcc_lo ; GFX1030-NEXT: s_and_b32 s0, s0, vcc_lo
; GFX1030-NEXT: s_and_saveexec_b32 s0, s0 ; GFX1030-NEXT: s_and_saveexec_b32 s0, s0
; GFX1030-NEXT: image_bvh_intersect_ray v[0:3], v[18:33], s[4:7] ; GFX1030-NEXT: image_bvh_intersect_ray v[0:3], v[18:33], s[4:7]
; GFX1030-NEXT: ; implicit-def: $vgpr14_vgpr15 ; GFX1030-NEXT: ; implicit-def: $vgpr14_vgpr15
; GFX1030-NEXT: ; implicit-def: $vgpr18 ; GFX1030-NEXT: ; implicit-def: $vgpr18
; GFX1030-NEXT: ; implicit-def: $vgpr19 ; GFX1030-NEXT: ; implicit-def: $vgpr19
; GFX1030-NEXT: ; implicit-def: $vgpr20 ; GFX1030-NEXT: ; implicit-def: $vgpr20
; GFX1030-NEXT: ; implicit-def: $vgpr21 ; GFX1030-NEXT: ; implicit-def: $vgpr21
; GFX1030-NEXT: ; implicit-def: $vgpr22 ; GFX1030-NEXT: ; implicit-def: $vgpr22
; GFX1030-NEXT: ; implicit-def: $vgpr23 ; GFX1030-NEXT: ; implicit-def: $vgpr23
; GFX1030-NEXT: ; implicit-def: $vgpr24 ; GFX1030-NEXT: ; implicit-def: $vgpr24
; GFX1030-NEXT: ; implicit-def: $vgpr25 ; GFX1030-NEXT: ; implicit-def: $vgpr25
; GFX1030-NEXT: ; implicit-def: $vgpr26 ; GFX1030-NEXT: ; implicit-def: $vgpr26
; GFX1030-NEXT: ; implicit-def: $vgpr27 ; GFX1030-NEXT: ; implicit-def: $vgpr27
; GFX1030-NEXT: ; implicit-def: $vgpr28 ; GFX1030-NEXT: ; implicit-def: $vgpr28
; GFX1030-NEXT: ; implicit-def: $vgpr14_vgpr15_vgpr16_vgpr17 ; GFX1030-NEXT: ; implicit-def: $vgpr14_vgpr15_vgpr16_vgpr17
; GFX1030-NEXT: s_xor_b32 exec_lo, exec_lo, s0 ; GFX1030-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX1030-NEXT: s_cbranch_execnz BB6_1 ; GFX1030-NEXT: s_cbranch_execnz .LBB6_1
; GFX1030-NEXT: ; %bb.2: ; GFX1030-NEXT: ; %bb.2:
; GFX1030-NEXT: s_mov_b32 exec_lo, s1 ; GFX1030-NEXT: s_mov_b32 exec_lo, s1
; GFX1030-NEXT: s_waitcnt vmcnt(0) ; GFX1030-NEXT: s_waitcnt vmcnt(0)
; GFX1030-NEXT: ; return to shader part epilog ; GFX1030-NEXT: ; return to shader part epilog
; ;
; GFX1013-LABEL: image_bvh_intersect_ray_vgpr_descr: ; GFX1013-LABEL: image_bvh_intersect_ray_vgpr_descr:
; GFX1013: ; %bb.0: ; GFX1013: ; %bb.0:
; GFX1013-NEXT: v_mov_b32_e32 v5, v6 ; GFX1013-NEXT: v_mov_b32_e32 v5, v6
; GFX1013-NEXT: v_mov_b32_e32 v6, v7 ; GFX1013-NEXT: v_mov_b32_e32 v6, v7
; GFX1013-NEXT: v_mov_b32_e32 v7, v8 ; GFX1013-NEXT: v_mov_b32_e32 v7, v8
; GFX1013-NEXT: v_mov_b32_e32 v8, v10 ; GFX1013-NEXT: v_mov_b32_e32 v8, v10
; GFX1013-NEXT: v_mov_b32_e32 v9, v11 ; GFX1013-NEXT: v_mov_b32_e32 v9, v11
; GFX1013-NEXT: v_mov_b32_e32 v10, v12 ; GFX1013-NEXT: v_mov_b32_e32 v10, v12
; GFX1013-NEXT: v_mov_b32_e32 v18, v14 ; GFX1013-NEXT: v_mov_b32_e32 v18, v14
; GFX1013-NEXT: v_mov_b32_e32 v19, v15 ; GFX1013-NEXT: v_mov_b32_e32 v19, v15
; GFX1013-NEXT: s_mov_b32 s1, exec_lo ; GFX1013-NEXT: s_mov_b32 s1, exec_lo
; GFX1013-NEXT: BB6_1: ; =>This Inner Loop Header: Depth=1 ; GFX1013-NEXT: .LBB6_1: ; =>This Inner Loop Header: Depth=1
; GFX1013-NEXT: v_readfirstlane_b32 s4, v18 ; GFX1013-NEXT: v_readfirstlane_b32 s4, v18
; GFX1013-NEXT: v_readfirstlane_b32 s5, v19 ; GFX1013-NEXT: v_readfirstlane_b32 s5, v19
; GFX1013-NEXT: v_readfirstlane_b32 s6, v16 ; GFX1013-NEXT: v_readfirstlane_b32 s6, v16
; GFX1013-NEXT: v_readfirstlane_b32 s7, v17 ; GFX1013-NEXT: v_readfirstlane_b32 s7, v17
; GFX1013-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[18:19] ; GFX1013-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[18:19]
; GFX1013-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[16:17] ; GFX1013-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[16:17]
; GFX1013-NEXT: s_and_b32 s0, s0, vcc_lo ; GFX1013-NEXT: s_and_b32 s0, s0, vcc_lo
; GFX1013-NEXT: s_and_saveexec_b32 s0, s0 ; GFX1013-NEXT: s_and_saveexec_b32 s0, s0
; GFX1013-NEXT: image_bvh_intersect_ray v[20:23], v[0:15], s[4:7] ; GFX1013-NEXT: image_bvh_intersect_ray v[20:23], v[0:15], s[4:7]
; GFX1013-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX1013-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX1013-NEXT: ; implicit-def: $vgpr18_vgpr19 ; GFX1013-NEXT: ; implicit-def: $vgpr18_vgpr19
; GFX1013-NEXT: ; implicit-def: $vgpr14_vgpr15_vgpr16_vgpr17 ; GFX1013-NEXT: ; implicit-def: $vgpr14_vgpr15_vgpr16_vgpr17
; GFX1013-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1013-NEXT: s_waitcnt_depctr 0xffe3
; GFX1013-NEXT: s_xor_b32 exec_lo, exec_lo, s0 ; GFX1013-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX1013-NEXT: s_cbranch_execnz BB6_1 ; GFX1013-NEXT: s_cbranch_execnz .LBB6_1
; GFX1013-NEXT: ; %bb.2: ; GFX1013-NEXT: ; %bb.2:
; GFX1013-NEXT: s_mov_b32 exec_lo, s1 ; GFX1013-NEXT: s_mov_b32 exec_lo, s1
; GFX1013-NEXT: s_waitcnt vmcnt(0) ; GFX1013-NEXT: s_waitcnt vmcnt(0)
; GFX1013-NEXT: v_mov_b32_e32 v0, v20 ; GFX1013-NEXT: v_mov_b32_e32 v0, v20
; GFX1013-NEXT: v_mov_b32_e32 v1, v21 ; GFX1013-NEXT: v_mov_b32_e32 v1, v21
; GFX1013-NEXT: v_mov_b32_e32 v2, v22 ; GFX1013-NEXT: v_mov_b32_e32 v2, v22
; GFX1013-NEXT: v_mov_b32_e32 v3, v23 ; GFX1013-NEXT: v_mov_b32_e32 v3, v23
; GFX1013-NEXT: ; return to shader part epilog ; GFX1013-NEXT: ; return to shader part epilog
Show All 16 Lines
; GFX1030-NEXT: v_lshlrev_b32_e32 v0, 16, v0 ; GFX1030-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX1030-NEXT: v_and_b32_e32 v3, s0, v9 ; GFX1030-NEXT: v_and_b32_e32 v3, s0, v9
; GFX1030-NEXT: v_mov_b32_e32 v18, v4 ; GFX1030-NEXT: v_mov_b32_e32 v18, v4
; GFX1030-NEXT: s_mov_b32 s1, exec_lo ; GFX1030-NEXT: s_mov_b32 s1, exec_lo
; GFX1030-NEXT: v_and_or_b32 v19, v6, s0, v0 ; GFX1030-NEXT: v_and_or_b32 v19, v6, s0, v0
; GFX1030-NEXT: v_and_or_b32 v20, v7, s0, v1 ; GFX1030-NEXT: v_and_or_b32 v20, v7, s0, v1
; GFX1030-NEXT: v_lshl_or_b32 v21, v3, 16, v2 ; GFX1030-NEXT: v_lshl_or_b32 v21, v3, 16, v2
; GFX1030-NEXT: BB7_1: ; =>This Inner Loop Header: Depth=1 ; GFX1030-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1
; GFX1030-NEXT: v_readfirstlane_b32 s4, v10 ; GFX1030-NEXT: v_readfirstlane_b32 s4, v10
; GFX1030-NEXT: v_readfirstlane_b32 s5, v11 ; GFX1030-NEXT: v_readfirstlane_b32 s5, v11
; GFX1030-NEXT: v_readfirstlane_b32 s6, v12 ; GFX1030-NEXT: v_readfirstlane_b32 s6, v12
; GFX1030-NEXT: v_readfirstlane_b32 s7, v13 ; GFX1030-NEXT: v_readfirstlane_b32 s7, v13
; GFX1030-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[10:11] ; GFX1030-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[10:11]
; GFX1030-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[12:13] ; GFX1030-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[12:13]
; GFX1030-NEXT: s_and_b32 s0, s0, vcc_lo ; GFX1030-NEXT: s_and_b32 s0, s0, vcc_lo
; GFX1030-NEXT: s_and_saveexec_b32 s0, s0 ; GFX1030-NEXT: s_and_saveexec_b32 s0, s0
; GFX1030-NEXT: image_bvh_intersect_ray v[0:3], v[14:21], s[4:7] a16 ; GFX1030-NEXT: image_bvh_intersect_ray v[0:3], v[14:21], s[4:7] a16
; GFX1030-NEXT: ; implicit-def: $vgpr10_vgpr11 ; GFX1030-NEXT: ; implicit-def: $vgpr10_vgpr11
; GFX1030-NEXT: ; implicit-def: $vgpr14 ; GFX1030-NEXT: ; implicit-def: $vgpr14
; GFX1030-NEXT: ; implicit-def: $vgpr15 ; GFX1030-NEXT: ; implicit-def: $vgpr15
; GFX1030-NEXT: ; implicit-def: $vgpr16 ; GFX1030-NEXT: ; implicit-def: $vgpr16
; GFX1030-NEXT: ; implicit-def: $vgpr17 ; GFX1030-NEXT: ; implicit-def: $vgpr17
; GFX1030-NEXT: ; implicit-def: $vgpr18 ; GFX1030-NEXT: ; implicit-def: $vgpr18
; GFX1030-NEXT: ; implicit-def: $vgpr19 ; GFX1030-NEXT: ; implicit-def: $vgpr19
; GFX1030-NEXT: ; implicit-def: $vgpr20 ; GFX1030-NEXT: ; implicit-def: $vgpr20
; GFX1030-NEXT: ; implicit-def: $vgpr21 ; GFX1030-NEXT: ; implicit-def: $vgpr21
; GFX1030-NEXT: ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13 ; GFX1030-NEXT: ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13
; GFX1030-NEXT: s_xor_b32 exec_lo, exec_lo, s0 ; GFX1030-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX1030-NEXT: s_cbranch_execnz BB7_1 ; GFX1030-NEXT: s_cbranch_execnz .LBB7_1
; GFX1030-NEXT: ; %bb.2: ; GFX1030-NEXT: ; %bb.2:
; GFX1030-NEXT: s_mov_b32 exec_lo, s1 ; GFX1030-NEXT: s_mov_b32 exec_lo, s1
; GFX1030-NEXT: s_waitcnt vmcnt(0) ; GFX1030-NEXT: s_waitcnt vmcnt(0)
; GFX1030-NEXT: ; return to shader part epilog ; GFX1030-NEXT: ; return to shader part epilog
; ;
; GFX1013-LABEL: image_bvh_intersect_ray_a16_vgpr_descr: ; GFX1013-LABEL: image_bvh_intersect_ray_a16_vgpr_descr:
; GFX1013: ; %bb.0: ; GFX1013: ; %bb.0:
; GFX1013-NEXT: s_mov_b32 s0, 0xffff ; GFX1013-NEXT: s_mov_b32 s0, 0xffff
; GFX1013-NEXT: v_lshrrev_b32_e32 v5, 16, v6 ; GFX1013-NEXT: v_lshrrev_b32_e32 v5, 16, v6
; GFX1013-NEXT: v_and_b32_e32 v14, s0, v8 ; GFX1013-NEXT: v_and_b32_e32 v14, s0, v8
; GFX1013-NEXT: v_lshrrev_b32_e32 v8, 16, v8 ; GFX1013-NEXT: v_lshrrev_b32_e32 v8, 16, v8
; GFX1013-NEXT: v_and_b32_e32 v9, s0, v9 ; GFX1013-NEXT: v_and_b32_e32 v9, s0, v9
; GFX1013-NEXT: s_mov_b32 s1, exec_lo ; GFX1013-NEXT: s_mov_b32 s1, exec_lo
; GFX1013-NEXT: v_lshlrev_b32_e32 v5, 16, v5 ; GFX1013-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX1013-NEXT: v_lshlrev_b32_e32 v14, 16, v14 ; GFX1013-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX1013-NEXT: v_and_or_b32 v5, v6, s0, v5 ; GFX1013-NEXT: v_and_or_b32 v5, v6, s0, v5
; GFX1013-NEXT: v_and_or_b32 v6, v7, s0, v14 ; GFX1013-NEXT: v_and_or_b32 v6, v7, s0, v14
; GFX1013-NEXT: v_lshl_or_b32 v7, v9, 16, v8 ; GFX1013-NEXT: v_lshl_or_b32 v7, v9, 16, v8
; GFX1013-NEXT: BB7_1: ; =>This Inner Loop Header: Depth=1 ; GFX1013-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1
; GFX1013-NEXT: v_readfirstlane_b32 s4, v10 ; GFX1013-NEXT: v_readfirstlane_b32 s4, v10
; GFX1013-NEXT: v_readfirstlane_b32 s5, v11 ; GFX1013-NEXT: v_readfirstlane_b32 s5, v11
; GFX1013-NEXT: v_readfirstlane_b32 s6, v12 ; GFX1013-NEXT: v_readfirstlane_b32 s6, v12
; GFX1013-NEXT: v_readfirstlane_b32 s7, v13 ; GFX1013-NEXT: v_readfirstlane_b32 s7, v13
; GFX1013-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[10:11] ; GFX1013-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[10:11]
; GFX1013-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[12:13] ; GFX1013-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[12:13]
; GFX1013-NEXT: s_and_b32 s0, s0, vcc_lo ; GFX1013-NEXT: s_and_b32 s0, s0, vcc_lo
; GFX1013-NEXT: s_and_saveexec_b32 s0, s0 ; GFX1013-NEXT: s_and_saveexec_b32 s0, s0
; GFX1013-NEXT: image_bvh_intersect_ray v[14:17], v[0:7], s[4:7] a16 ; GFX1013-NEXT: image_bvh_intersect_ray v[14:17], v[0:7], s[4:7] a16
; GFX1013-NEXT: ; implicit-def: $vgpr10_vgpr11 ; GFX1013-NEXT: ; implicit-def: $vgpr10_vgpr11
; GFX1013-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX1013-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX1013-NEXT: ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13 ; GFX1013-NEXT: ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13
; GFX1013-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1013-NEXT: s_waitcnt_depctr 0xffe3
; GFX1013-NEXT: s_xor_b32 exec_lo, exec_lo, s0 ; GFX1013-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX1013-NEXT: s_cbranch_execnz BB7_1 ; GFX1013-NEXT: s_cbranch_execnz .LBB7_1
; GFX1013-NEXT: ; %bb.2: ; GFX1013-NEXT: ; %bb.2:
; GFX1013-NEXT: s_mov_b32 exec_lo, s1 ; GFX1013-NEXT: s_mov_b32 exec_lo, s1
; GFX1013-NEXT: s_waitcnt vmcnt(0) ; GFX1013-NEXT: s_waitcnt vmcnt(0)
; GFX1013-NEXT: v_mov_b32_e32 v0, v14 ; GFX1013-NEXT: v_mov_b32_e32 v0, v14
; GFX1013-NEXT: v_mov_b32_e32 v1, v15 ; GFX1013-NEXT: v_mov_b32_e32 v1, v15
; GFX1013-NEXT: v_mov_b32_e32 v2, v16 ; GFX1013-NEXT: v_mov_b32_e32 v2, v16
; GFX1013-NEXT: v_mov_b32_e32 v3, v17 ; GFX1013-NEXT: v_mov_b32_e32 v3, v17
; GFX1013-NEXT: ; return to shader part epilog ; GFX1013-NEXT: ; return to shader part epilog
Show All 13 Lines
; GFX1030-NEXT: v_mov_b32_e32 v24, v5 ; GFX1030-NEXT: v_mov_b32_e32 v24, v5
; GFX1030-NEXT: v_mov_b32_e32 v25, v7 ; GFX1030-NEXT: v_mov_b32_e32 v25, v7
; GFX1030-NEXT: v_mov_b32_e32 v26, v8 ; GFX1030-NEXT: v_mov_b32_e32 v26, v8
; GFX1030-NEXT: v_mov_b32_e32 v27, v9 ; GFX1030-NEXT: v_mov_b32_e32 v27, v9
; GFX1030-NEXT: v_mov_b32_e32 v28, v11 ; GFX1030-NEXT: v_mov_b32_e32 v28, v11
; GFX1030-NEXT: v_mov_b32_e32 v29, v12 ; GFX1030-NEXT: v_mov_b32_e32 v29, v12
; GFX1030-NEXT: v_mov_b32_e32 v30, v13 ; GFX1030-NEXT: v_mov_b32_e32 v30, v13
; GFX1030-NEXT: s_mov_b32 s1, exec_lo ; GFX1030-NEXT: s_mov_b32 s1, exec_lo
; GFX1030-NEXT: BB8_1: ; =>This Inner Loop Header: Depth=1 ; GFX1030-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
; GFX1030-NEXT: v_readfirstlane_b32 s4, v15 ; GFX1030-NEXT: v_readfirstlane_b32 s4, v15
; GFX1030-NEXT: v_readfirstlane_b32 s5, v16 ; GFX1030-NEXT: v_readfirstlane_b32 s5, v16
; GFX1030-NEXT: v_readfirstlane_b32 s6, v17 ; GFX1030-NEXT: v_readfirstlane_b32 s6, v17
; GFX1030-NEXT: v_readfirstlane_b32 s7, v18 ; GFX1030-NEXT: v_readfirstlane_b32 s7, v18
; GFX1030-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[15:16] ; GFX1030-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[15:16]
; GFX1030-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[17:18] ; GFX1030-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[17:18]
; GFX1030-NEXT: s_and_b32 s0, s0, vcc_lo ; GFX1030-NEXT: s_and_b32 s0, s0, vcc_lo
; GFX1030-NEXT: s_and_saveexec_b32 s0, s0 ; GFX1030-NEXT: s_and_saveexec_b32 s0, s0
; GFX1030-NEXT: image_bvh64_intersect_ray v[0:3], v[19:34], s[4:7] ; GFX1030-NEXT: image_bvh64_intersect_ray v[0:3], v[19:34], s[4:7]
; GFX1030-NEXT: ; implicit-def: $vgpr15_vgpr16 ; GFX1030-NEXT: ; implicit-def: $vgpr15_vgpr16
; GFX1030-NEXT: ; implicit-def: $vgpr19 ; GFX1030-NEXT: ; implicit-def: $vgpr19
; GFX1030-NEXT: ; implicit-def: $vgpr20 ; GFX1030-NEXT: ; implicit-def: $vgpr20
; GFX1030-NEXT: ; implicit-def: $vgpr21 ; GFX1030-NEXT: ; implicit-def: $vgpr21
; GFX1030-NEXT: ; implicit-def: $vgpr22 ; GFX1030-NEXT: ; implicit-def: $vgpr22
; GFX1030-NEXT: ; implicit-def: $vgpr23 ; GFX1030-NEXT: ; implicit-def: $vgpr23
; GFX1030-NEXT: ; implicit-def: $vgpr24 ; GFX1030-NEXT: ; implicit-def: $vgpr24
; GFX1030-NEXT: ; implicit-def: $vgpr25 ; GFX1030-NEXT: ; implicit-def: $vgpr25
; GFX1030-NEXT: ; implicit-def: $vgpr26 ; GFX1030-NEXT: ; implicit-def: $vgpr26
; GFX1030-NEXT: ; implicit-def: $vgpr27 ; GFX1030-NEXT: ; implicit-def: $vgpr27
; GFX1030-NEXT: ; implicit-def: $vgpr28 ; GFX1030-NEXT: ; implicit-def: $vgpr28
; GFX1030-NEXT: ; implicit-def: $vgpr29 ; GFX1030-NEXT: ; implicit-def: $vgpr29
; GFX1030-NEXT: ; implicit-def: $vgpr30 ; GFX1030-NEXT: ; implicit-def: $vgpr30
; GFX1030-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18 ; GFX1030-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18
; GFX1030-NEXT: s_xor_b32 exec_lo, exec_lo, s0 ; GFX1030-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX1030-NEXT: s_cbranch_execnz BB8_1 ; GFX1030-NEXT: s_cbranch_execnz .LBB8_1
; GFX1030-NEXT: ; %bb.2: ; GFX1030-NEXT: ; %bb.2:
; GFX1030-NEXT: s_mov_b32 exec_lo, s1 ; GFX1030-NEXT: s_mov_b32 exec_lo, s1
; GFX1030-NEXT: s_waitcnt vmcnt(0) ; GFX1030-NEXT: s_waitcnt vmcnt(0)
; GFX1030-NEXT: ; return to shader part epilog ; GFX1030-NEXT: ; return to shader part epilog
; ;
; GFX1013-LABEL: image_bvh64_intersect_ray_vgpr_descr: ; GFX1013-LABEL: image_bvh64_intersect_ray_vgpr_descr:
; GFX1013: ; %bb.0: ; GFX1013: ; %bb.0:
; GFX1013-NEXT: v_mov_b32_e32 v6, v7 ; GFX1013-NEXT: v_mov_b32_e32 v6, v7
; GFX1013-NEXT: v_mov_b32_e32 v7, v8 ; GFX1013-NEXT: v_mov_b32_e32 v7, v8
; GFX1013-NEXT: v_mov_b32_e32 v8, v9 ; GFX1013-NEXT: v_mov_b32_e32 v8, v9
; GFX1013-NEXT: v_mov_b32_e32 v9, v11 ; GFX1013-NEXT: v_mov_b32_e32 v9, v11
; GFX1013-NEXT: v_mov_b32_e32 v10, v12 ; GFX1013-NEXT: v_mov_b32_e32 v10, v12
; GFX1013-NEXT: v_mov_b32_e32 v11, v13 ; GFX1013-NEXT: v_mov_b32_e32 v11, v13
; GFX1013-NEXT: v_mov_b32_e32 v19, v15 ; GFX1013-NEXT: v_mov_b32_e32 v19, v15
; GFX1013-NEXT: v_mov_b32_e32 v20, v16 ; GFX1013-NEXT: v_mov_b32_e32 v20, v16
; GFX1013-NEXT: s_mov_b32 s1, exec_lo ; GFX1013-NEXT: s_mov_b32 s1, exec_lo
; GFX1013-NEXT: BB8_1: ; =>This Inner Loop Header: Depth=1 ; GFX1013-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
; GFX1013-NEXT: v_readfirstlane_b32 s4, v19 ; GFX1013-NEXT: v_readfirstlane_b32 s4, v19
; GFX1013-NEXT: v_readfirstlane_b32 s5, v20 ; GFX1013-NEXT: v_readfirstlane_b32 s5, v20
; GFX1013-NEXT: v_readfirstlane_b32 s6, v17 ; GFX1013-NEXT: v_readfirstlane_b32 s6, v17
; GFX1013-NEXT: v_readfirstlane_b32 s7, v18 ; GFX1013-NEXT: v_readfirstlane_b32 s7, v18
; GFX1013-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[19:20] ; GFX1013-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[19:20]
; GFX1013-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[17:18] ; GFX1013-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[17:18]
; GFX1013-NEXT: s_and_b32 s0, s0, vcc_lo ; GFX1013-NEXT: s_and_b32 s0, s0, vcc_lo
; GFX1013-NEXT: s_and_saveexec_b32 s0, s0 ; GFX1013-NEXT: s_and_saveexec_b32 s0, s0
; GFX1013-NEXT: image_bvh64_intersect_ray v[21:24], v[0:15], s[4:7] ; GFX1013-NEXT: image_bvh64_intersect_ray v[21:24], v[0:15], s[4:7]
; GFX1013-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX1013-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX1013-NEXT: ; implicit-def: $vgpr19_vgpr20 ; GFX1013-NEXT: ; implicit-def: $vgpr19_vgpr20
; GFX1013-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18 ; GFX1013-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18
; GFX1013-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1013-NEXT: s_waitcnt_depctr 0xffe3
; GFX1013-NEXT: s_xor_b32 exec_lo, exec_lo, s0 ; GFX1013-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX1013-NEXT: s_cbranch_execnz BB8_1 ; GFX1013-NEXT: s_cbranch_execnz .LBB8_1
; GFX1013-NEXT: ; %bb.2: ; GFX1013-NEXT: ; %bb.2:
; GFX1013-NEXT: s_mov_b32 exec_lo, s1 ; GFX1013-NEXT: s_mov_b32 exec_lo, s1
; GFX1013-NEXT: s_waitcnt vmcnt(0) ; GFX1013-NEXT: s_waitcnt vmcnt(0)
; GFX1013-NEXT: v_mov_b32_e32 v0, v21 ; GFX1013-NEXT: v_mov_b32_e32 v0, v21
; GFX1013-NEXT: v_mov_b32_e32 v1, v22 ; GFX1013-NEXT: v_mov_b32_e32 v1, v22
; GFX1013-NEXT: v_mov_b32_e32 v2, v23 ; GFX1013-NEXT: v_mov_b32_e32 v2, v23
; GFX1013-NEXT: v_mov_b32_e32 v3, v24 ; GFX1013-NEXT: v_mov_b32_e32 v3, v24
; GFX1013-NEXT: ; return to shader part epilog ; GFX1013-NEXT: ; return to shader part epilog
Show All 17 Lines
; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX1030-NEXT: v_and_b32_e32 v3, s0, v10 ; GFX1030-NEXT: v_and_b32_e32 v3, s0, v10
; GFX1030-NEXT: v_mov_b32_e32 v19, v4 ; GFX1030-NEXT: v_mov_b32_e32 v19, v4
; GFX1030-NEXT: v_mov_b32_e32 v20, v5 ; GFX1030-NEXT: v_mov_b32_e32 v20, v5
; GFX1030-NEXT: v_and_or_b32 v21, v7, s0, v0 ; GFX1030-NEXT: v_and_or_b32 v21, v7, s0, v0
; GFX1030-NEXT: v_and_or_b32 v22, v8, s0, v1 ; GFX1030-NEXT: v_and_or_b32 v22, v8, s0, v1
; GFX1030-NEXT: v_lshl_or_b32 v23, v3, 16, v2 ; GFX1030-NEXT: v_lshl_or_b32 v23, v3, 16, v2
; GFX1030-NEXT: s_mov_b32 s1, exec_lo ; GFX1030-NEXT: s_mov_b32 s1, exec_lo
; GFX1030-NEXT: BB9_1: ; =>This Inner Loop Header: Depth=1 ; GFX1030-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1
; GFX1030-NEXT: v_readfirstlane_b32 s4, v11 ; GFX1030-NEXT: v_readfirstlane_b32 s4, v11
; GFX1030-NEXT: v_readfirstlane_b32 s5, v12 ; GFX1030-NEXT: v_readfirstlane_b32 s5, v12
; GFX1030-NEXT: v_readfirstlane_b32 s6, v13 ; GFX1030-NEXT: v_readfirstlane_b32 s6, v13
; GFX1030-NEXT: v_readfirstlane_b32 s7, v14 ; GFX1030-NEXT: v_readfirstlane_b32 s7, v14
; GFX1030-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[11:12] ; GFX1030-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[11:12]
; GFX1030-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[13:14] ; GFX1030-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[13:14]
; GFX1030-NEXT: s_and_b32 s0, s0, vcc_lo ; GFX1030-NEXT: s_and_b32 s0, s0, vcc_lo
; GFX1030-NEXT: s_and_saveexec_b32 s0, s0 ; GFX1030-NEXT: s_and_saveexec_b32 s0, s0
; GFX1030-NEXT: image_bvh64_intersect_ray v[0:3], v[15:30], s[4:7] a16 ; GFX1030-NEXT: image_bvh64_intersect_ray v[0:3], v[15:30], s[4:7] a16
; GFX1030-NEXT: ; implicit-def: $vgpr11_vgpr12 ; GFX1030-NEXT: ; implicit-def: $vgpr11_vgpr12
; GFX1030-NEXT: ; implicit-def: $vgpr15 ; GFX1030-NEXT: ; implicit-def: $vgpr15
; GFX1030-NEXT: ; implicit-def: $vgpr16 ; GFX1030-NEXT: ; implicit-def: $vgpr16
; GFX1030-NEXT: ; implicit-def: $vgpr17 ; GFX1030-NEXT: ; implicit-def: $vgpr17
; GFX1030-NEXT: ; implicit-def: $vgpr18 ; GFX1030-NEXT: ; implicit-def: $vgpr18
; GFX1030-NEXT: ; implicit-def: $vgpr19 ; GFX1030-NEXT: ; implicit-def: $vgpr19
; GFX1030-NEXT: ; implicit-def: $vgpr20 ; GFX1030-NEXT: ; implicit-def: $vgpr20
; GFX1030-NEXT: ; implicit-def: $vgpr21 ; GFX1030-NEXT: ; implicit-def: $vgpr21
; GFX1030-NEXT: ; implicit-def: $vgpr22 ; GFX1030-NEXT: ; implicit-def: $vgpr22
; GFX1030-NEXT: ; implicit-def: $vgpr23 ; GFX1030-NEXT: ; implicit-def: $vgpr23
; GFX1030-NEXT: ; implicit-def: $vgpr11_vgpr12_vgpr13_vgpr14 ; GFX1030-NEXT: ; implicit-def: $vgpr11_vgpr12_vgpr13_vgpr14
; GFX1030-NEXT: s_xor_b32 exec_lo, exec_lo, s0 ; GFX1030-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX1030-NEXT: s_cbranch_execnz BB9_1 ; GFX1030-NEXT: s_cbranch_execnz .LBB9_1
; GFX1030-NEXT: ; %bb.2: ; GFX1030-NEXT: ; %bb.2:
; GFX1030-NEXT: s_mov_b32 exec_lo, s1 ; GFX1030-NEXT: s_mov_b32 exec_lo, s1
; GFX1030-NEXT: s_waitcnt vmcnt(0) ; GFX1030-NEXT: s_waitcnt vmcnt(0)
; GFX1030-NEXT: ; return to shader part epilog ; GFX1030-NEXT: ; return to shader part epilog
; ;
; GFX1013-LABEL: image_bvh64_intersect_ray_a16_vgpr_descr: ; GFX1013-LABEL: image_bvh64_intersect_ray_a16_vgpr_descr:
; GFX1013: ; %bb.0: ; GFX1013: ; %bb.0:
; GFX1013-NEXT: s_mov_b32 s0, 0xffff ; GFX1013-NEXT: s_mov_b32 s0, 0xffff
; GFX1013-NEXT: v_mov_b32_e32 v16, v11 ; GFX1013-NEXT: v_mov_b32_e32 v16, v11
; GFX1013-NEXT: v_lshrrev_b32_e32 v6, 16, v7 ; GFX1013-NEXT: v_lshrrev_b32_e32 v6, 16, v7
; GFX1013-NEXT: v_and_b32_e32 v11, s0, v9 ; GFX1013-NEXT: v_and_b32_e32 v11, s0, v9
; GFX1013-NEXT: v_lshrrev_b32_e32 v9, 16, v9 ; GFX1013-NEXT: v_lshrrev_b32_e32 v9, 16, v9
; GFX1013-NEXT: v_and_b32_e32 v10, s0, v10 ; GFX1013-NEXT: v_and_b32_e32 v10, s0, v10
; GFX1013-NEXT: v_mov_b32_e32 v17, v12 ; GFX1013-NEXT: v_mov_b32_e32 v17, v12
; GFX1013-NEXT: v_lshlrev_b32_e32 v6, 16, v6 ; GFX1013-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX1013-NEXT: v_lshlrev_b32_e32 v11, 16, v11 ; GFX1013-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GFX1013-NEXT: v_mov_b32_e32 v18, v13 ; GFX1013-NEXT: v_mov_b32_e32 v18, v13
; GFX1013-NEXT: v_mov_b32_e32 v19, v14 ; GFX1013-NEXT: v_mov_b32_e32 v19, v14
; GFX1013-NEXT: s_mov_b32 s1, exec_lo ; GFX1013-NEXT: s_mov_b32 s1, exec_lo
; GFX1013-NEXT: v_and_or_b32 v6, v7, s0, v6 ; GFX1013-NEXT: v_and_or_b32 v6, v7, s0, v6
; GFX1013-NEXT: v_and_or_b32 v7, v8, s0, v11 ; GFX1013-NEXT: v_and_or_b32 v7, v8, s0, v11
; GFX1013-NEXT: v_lshl_or_b32 v8, v10, 16, v9 ; GFX1013-NEXT: v_lshl_or_b32 v8, v10, 16, v9
; GFX1013-NEXT: BB9_1: ; =>This Inner Loop Header: Depth=1 ; GFX1013-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1
; GFX1013-NEXT: v_readfirstlane_b32 s4, v16 ; GFX1013-NEXT: v_readfirstlane_b32 s4, v16
; GFX1013-NEXT: v_readfirstlane_b32 s5, v17 ; GFX1013-NEXT: v_readfirstlane_b32 s5, v17
; GFX1013-NEXT: v_readfirstlane_b32 s6, v18 ; GFX1013-NEXT: v_readfirstlane_b32 s6, v18
; GFX1013-NEXT: v_readfirstlane_b32 s7, v19 ; GFX1013-NEXT: v_readfirstlane_b32 s7, v19
; GFX1013-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[16:17] ; GFX1013-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[16:17]
; GFX1013-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[18:19] ; GFX1013-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[18:19]
; GFX1013-NEXT: s_and_b32 s0, s0, vcc_lo ; GFX1013-NEXT: s_and_b32 s0, s0, vcc_lo
; GFX1013-NEXT: s_and_saveexec_b32 s0, s0 ; GFX1013-NEXT: s_and_saveexec_b32 s0, s0
; GFX1013-NEXT: image_bvh64_intersect_ray v[20:23], v[0:15], s[4:7] a16 ; GFX1013-NEXT: image_bvh64_intersect_ray v[20:23], v[0:15], s[4:7] a16
; GFX1013-NEXT: ; implicit-def: $vgpr16_vgpr17 ; GFX1013-NEXT: ; implicit-def: $vgpr16_vgpr17
; GFX1013-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX1013-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX1013-NEXT: ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19 ; GFX1013-NEXT: ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19
; GFX1013-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1013-NEXT: s_waitcnt_depctr 0xffe3
; GFX1013-NEXT: s_xor_b32 exec_lo, exec_lo, s0 ; GFX1013-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX1013-NEXT: s_cbranch_execnz BB9_1 ; GFX1013-NEXT: s_cbranch_execnz .LBB9_1
; GFX1013-NEXT: ; %bb.2: ; GFX1013-NEXT: ; %bb.2:
; GFX1013-NEXT: s_mov_b32 exec_lo, s1 ; GFX1013-NEXT: s_mov_b32 exec_lo, s1
; GFX1013-NEXT: s_waitcnt vmcnt(0) ; GFX1013-NEXT: s_waitcnt vmcnt(0)
; GFX1013-NEXT: v_mov_b32_e32 v0, v20 ; GFX1013-NEXT: v_mov_b32_e32 v0, v20
; GFX1013-NEXT: v_mov_b32_e32 v1, v21 ; GFX1013-NEXT: v_mov_b32_e32 v1, v21
; GFX1013-NEXT: v_mov_b32_e32 v2, v22 ; GFX1013-NEXT: v_mov_b32_e32 v2, v22
; GFX1013-NEXT: v_mov_b32_e32 v3, v23 ; GFX1013-NEXT: v_mov_b32_e32 v3, v23
; GFX1013-NEXT: ; return to shader part epilog ; GFX1013-NEXT: ; return to shader part epilog
▲ Show 20 Lines • Show All 380 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.private.ll

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
define amdgpu_kernel void @is_private_sgpr(i8* %ptr) { define amdgpu_kernel void @is_private_sgpr(i8* %ptr) {
; CI-LABEL: is_private_sgpr: ; CI-LABEL: is_private_sgpr:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 ; CI-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_load_dword s0, s[4:5], 0x11 ; CI-NEXT: s_load_dword s0, s[4:5], 0x11
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_cmp_lg_u32 s1, s0 ; CI-NEXT: s_cmp_lg_u32 s1, s0
; CI-NEXT: s_cbranch_scc1 BB1_2 ; CI-NEXT: s_cbranch_scc1 .LBB1_2
; CI-NEXT: ; %bb.1: ; %bb0 ; CI-NEXT: ; %bb.1: ; %bb0
; CI-NEXT: v_mov_b32_e32 v0, 0 ; CI-NEXT: v_mov_b32_e32 v0, 0
; CI-NEXT: flat_store_dword v[0:1], v0 ; CI-NEXT: flat_store_dword v[0:1], v0
; CI-NEXT: s_waitcnt vmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: BB1_2: ; %bb1 ; CI-NEXT: .LBB1_2: ; %bb1
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; GFX9-LABEL: is_private_sgpr: ; GFX9-LABEL: is_private_sgpr:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 0, 16) ; GFX9-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 0, 16)
; GFX9-NEXT: s_lshl_b32 s0, s0, 16 ; GFX9-NEXT: s_lshl_b32 s0, s0, 16
; GFX9-NEXT: s_cmp_lg_u32 s1, s0 ; GFX9-NEXT: s_cmp_lg_u32 s1, s0
; GFX9-NEXT: s_cbranch_scc1 BB1_2 ; GFX9-NEXT: s_cbranch_scc1 .LBB1_2
; GFX9-NEXT: ; %bb.1: ; %bb0 ; GFX9-NEXT: ; %bb.1: ; %bb0
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: global_store_dword v[0:1], v0, off ; GFX9-NEXT: global_store_dword v[0:1], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: BB1_2: ; %bb1 ; GFX9-NEXT: .LBB1_2: ; %bb1
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: is_private_sgpr: ; GFX10-LABEL: is_private_sgpr:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 0, 16) ; GFX10-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 0, 16)
; GFX10-NEXT: s_lshl_b32 s0, s0, 16 ; GFX10-NEXT: s_lshl_b32 s0, s0, 16
; GFX10-NEXT: s_cmp_lg_u32 s1, s0 ; GFX10-NEXT: s_cmp_lg_u32 s1, s0
; GFX10-NEXT: s_cbranch_scc1 BB1_2 ; GFX10-NEXT: s_cbranch_scc1 .LBB1_2
; GFX10-NEXT: ; %bb.1: ; %bb0 ; GFX10-NEXT: ; %bb.1: ; %bb0
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: global_store_dword v[0:1], v0, off ; GFX10-NEXT: global_store_dword v[0:1], v0, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: BB1_2: ; %bb1 ; GFX10-NEXT: .LBB1_2: ; %bb1
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%val = call i1 @llvm.amdgcn.is.private(i8* %ptr) %val = call i1 @llvm.amdgcn.is.private(i8* %ptr)
br i1 %val, label %bb0, label %bb1 br i1 %val, label %bb0, label %bb1
bb0: bb0:
store volatile i32 0, i32 addrspace(1)* undef store volatile i32 0, i32 addrspace(1)* undef
br label %bb1 br label %bb1
bb1: bb1:
ret void ret void
} }
declare i32 @llvm.amdgcn.workitem.id.x() #0 declare i32 @llvm.amdgcn.workitem.id.x() #0
declare i1 @llvm.amdgcn.is.private(i8* nocapture) #0 declare i1 @llvm.amdgcn.is.private(i8* nocapture) #0
attributes #0 = { nounwind readnone speculatable } attributes #0 = { nounwind readnone speculatable }

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.shared.ll

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
define amdgpu_kernel void @is_local_sgpr(i8* %ptr) { define amdgpu_kernel void @is_local_sgpr(i8* %ptr) {
; CI-LABEL: is_local_sgpr: ; CI-LABEL: is_local_sgpr:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 ; CI-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_load_dword s0, s[4:5], 0x10 ; CI-NEXT: s_load_dword s0, s[4:5], 0x10
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_cmp_lg_u32 s1, s0 ; CI-NEXT: s_cmp_lg_u32 s1, s0
; CI-NEXT: s_cbranch_scc1 BB1_2 ; CI-NEXT: s_cbranch_scc1 .LBB1_2
; CI-NEXT: ; %bb.1: ; %bb0 ; CI-NEXT: ; %bb.1: ; %bb0
; CI-NEXT: v_mov_b32_e32 v0, 0 ; CI-NEXT: v_mov_b32_e32 v0, 0
; CI-NEXT: flat_store_dword v[0:1], v0 ; CI-NEXT: flat_store_dword v[0:1], v0
; CI-NEXT: s_waitcnt vmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: BB1_2: ; %bb1 ; CI-NEXT: .LBB1_2: ; %bb1
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; GFX9-LABEL: is_local_sgpr: ; GFX9-LABEL: is_local_sgpr:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 16, 16) ; GFX9-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 16, 16)
; GFX9-NEXT: s_lshl_b32 s0, s0, 16 ; GFX9-NEXT: s_lshl_b32 s0, s0, 16
; GFX9-NEXT: s_cmp_lg_u32 s1, s0 ; GFX9-NEXT: s_cmp_lg_u32 s1, s0
; GFX9-NEXT: s_cbranch_scc1 BB1_2 ; GFX9-NEXT: s_cbranch_scc1 .LBB1_2
; GFX9-NEXT: ; %bb.1: ; %bb0 ; GFX9-NEXT: ; %bb.1: ; %bb0
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: global_store_dword v[0:1], v0, off ; GFX9-NEXT: global_store_dword v[0:1], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: BB1_2: ; %bb1 ; GFX9-NEXT: .LBB1_2: ; %bb1
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: is_local_sgpr: ; GFX10-LABEL: is_local_sgpr:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 16, 16) ; GFX10-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 16, 16)
; GFX10-NEXT: s_lshl_b32 s0, s0, 16 ; GFX10-NEXT: s_lshl_b32 s0, s0, 16
; GFX10-NEXT: s_cmp_lg_u32 s1, s0 ; GFX10-NEXT: s_cmp_lg_u32 s1, s0
; GFX10-NEXT: s_cbranch_scc1 BB1_2 ; GFX10-NEXT: s_cbranch_scc1 .LBB1_2
; GFX10-NEXT: ; %bb.1: ; %bb0 ; GFX10-NEXT: ; %bb.1: ; %bb0
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: global_store_dword v[0:1], v0, off ; GFX10-NEXT: global_store_dword v[0:1], v0, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: BB1_2: ; %bb1 ; GFX10-NEXT: .LBB1_2: ; %bb1
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%val = call i1 @llvm.amdgcn.is.shared(i8* %ptr) %val = call i1 @llvm.amdgcn.is.shared(i8* %ptr)
br i1 %val, label %bb0, label %bb1 br i1 %val, label %bb0, label %bb1
bb0: bb0:
store volatile i32 0, i32 addrspace(1)* undef store volatile i32 0, i32 addrspace(1)* undef
br label %bb1 br label %bb1
bb1: bb1:
ret void ret void
} }
declare i32 @llvm.amdgcn.workitem.id.x() #0 declare i32 @llvm.amdgcn.workitem.id.x() #0
declare i1 @llvm.amdgcn.is.shared(i8* nocapture) #0 declare i1 @llvm.amdgcn.is.shared(i8* nocapture) #0
attributes #0 = { nounwind readnone speculatable } attributes #0 = { nounwind readnone speculatable }

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_mov_b32_e32 v0, s0 ; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_cmp_lg_u32 s1, 56 ; GCN-NEXT: s_cmp_lg_u32 s1, 56
; GCN-NEXT: s_cselect_b32 s0, 1, 0 ; GCN-NEXT: s_cselect_b32 s0, 1, 0
; GCN-NEXT: s_not_b64 exec, exec ; GCN-NEXT: s_not_b64 exec, exec
; GCN-NEXT: v_mov_b32_e32 v0, 42 ; GCN-NEXT: v_mov_b32_e32 v0, 42
; GCN-NEXT: s_not_b64 exec, exec ; GCN-NEXT: s_not_b64 exec, exec
; GCN-NEXT: s_cmp_lg_u32 s0, 0 ; GCN-NEXT: s_cmp_lg_u32 s0, 0
; GCN-NEXT: s_cbranch_scc0 BB2_2 ; GCN-NEXT: s_cbranch_scc0 .LBB2_2
; GCN-NEXT: ; %bb.1: ; %.one ; GCN-NEXT: ; %bb.1: ; %.one
; GCN-NEXT: v_add_u32_e32 v1, vcc, 1, v0 ; GCN-NEXT: v_add_u32_e32 v1, vcc, 1, v0
; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s0, 0 ; GCN-NEXT: s_mov_b32 s0, 0
; GCN-NEXT: buffer_store_dword v1, off, s[4:7], 0 ; GCN-NEXT: buffer_store_dword v1, off, s[4:7], 0
; GCN-NEXT: s_branch BB2_3 ; GCN-NEXT: s_branch .LBB2_3
; GCN-NEXT: BB2_2: ; GCN-NEXT: .LBB2_2:
; GCN-NEXT: s_mov_b32 s0, -1 ; GCN-NEXT: s_mov_b32 s0, -1
; GCN-NEXT: BB2_3: ; %Flow ; GCN-NEXT: .LBB2_3: ; %Flow
; GCN-NEXT: s_xor_b32 s0, s0, -1 ; GCN-NEXT: s_xor_b32 s0, s0, -1
; GCN-NEXT: s_and_b32 s0, s0, 1 ; GCN-NEXT: s_and_b32 s0, s0, 1
; GCN-NEXT: s_cmp_lg_u32 s0, 0 ; GCN-NEXT: s_cmp_lg_u32 s0, 0
; GCN-NEXT: s_cbranch_scc1 BB2_5 ; GCN-NEXT: s_cbranch_scc1 .LBB2_5
; GCN-NEXT: ; %bb.4: ; %.zero ; GCN-NEXT: ; %bb.4: ; %.zero
; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GCN-NEXT: BB2_5: ; %.exit ; GCN-NEXT: .LBB2_5: ; %.exit
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
%val = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 0, i32 0) %val = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 0, i32 0)
%cmp = icmp eq i32 %val, 56 %cmp = icmp eq i32 %val, 56
%tmp = call i32 @llvm.amdgcn.set.inactive.i32(i32 %in, i32 42) #0 %tmp = call i32 @llvm.amdgcn.set.inactive.i32(i32 %in, i32 42) #0
br i1 %cmp, label %.zero, label %.one br i1 %cmp, label %.zero, label %.one
.zero: .zero:
store i32 %tmp, i32 addrspace(1)* %out store i32 %tmp, i32 addrspace(1)* %out
Show All 16 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -global-isel -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 %s ; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 %s
; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10-32 %s ; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10-32 %s
; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10-64 %s ; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10-64 %s
define amdgpu_ps void @static_exact(float %arg0, float %arg1) { define amdgpu_ps void @static_exact(float %arg0, float %arg1) {
; SI-LABEL: static_exact: ; SI-LABEL: static_exact:
; SI: ; %bb.0: ; %.entry ; SI: ; %bb.0: ; %.entry
; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0 ; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0
; SI-NEXT: s_andn2_b64 exec, exec, exec ; SI-NEXT: s_andn2_b64 exec, exec, exec
; SI-NEXT: s_cbranch_scc0 BB0_2 ; SI-NEXT: s_cbranch_scc0 .LBB0_2
; SI-NEXT: ; %bb.1: ; %.entry ; SI-NEXT: ; %bb.1: ; %.entry
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc ; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc
; SI-NEXT: exp mrt1 v0, v0, v0, v0 done vm ; SI-NEXT: exp mrt1 v0, v0, v0, v0 done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; SI-NEXT: BB0_2: ; SI-NEXT: .LBB0_2:
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: exp null off, off, off, off done vm ; SI-NEXT: exp null off, off, off, off done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; GFX9-LABEL: static_exact: ; GFX9-LABEL: static_exact:
; GFX9: ; %bb.0: ; %.entry ; GFX9: ; %bb.0: ; %.entry
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0
; GFX9-NEXT: s_andn2_b64 exec, exec, exec ; GFX9-NEXT: s_andn2_b64 exec, exec, exec
; GFX9-NEXT: s_cbranch_scc0 BB0_2 ; GFX9-NEXT: s_cbranch_scc0 .LBB0_2
; GFX9-NEXT: ; %bb.1: ; %.entry ; GFX9-NEXT: ; %bb.1: ; %.entry
; GFX9-NEXT: s_mov_b64 exec, 0 ; GFX9-NEXT: s_mov_b64 exec, 0
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc
; GFX9-NEXT: exp mrt1 v0, v0, v0, v0 done vm ; GFX9-NEXT: exp mrt1 v0, v0, v0, v0 done vm
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; GFX9-NEXT: BB0_2: ; GFX9-NEXT: .LBB0_2:
; GFX9-NEXT: s_mov_b64 exec, 0 ; GFX9-NEXT: s_mov_b64 exec, 0
; GFX9-NEXT: exp null off, off, off, off done vm ; GFX9-NEXT: exp null off, off, off, off done vm
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-32-LABEL: static_exact: ; GFX10-32-LABEL: static_exact:
; GFX10-32: ; %bb.0: ; %.entry ; GFX10-32: ; %bb.0: ; %.entry
; GFX10-32-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v0 ; GFX10-32-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v0
; GFX10-32-NEXT: s_andn2_b32 exec_lo, exec_lo, exec_lo ; GFX10-32-NEXT: s_andn2_b32 exec_lo, exec_lo, exec_lo
; GFX10-32-NEXT: s_cbranch_scc0 BB0_2 ; GFX10-32-NEXT: s_cbranch_scc0 .LBB0_2
; GFX10-32-NEXT: ; %bb.1: ; %.entry ; GFX10-32-NEXT: ; %bb.1: ; %.entry
; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-32-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo ; GFX10-32-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
; GFX10-32-NEXT: exp mrt1 v0, v0, v0, v0 done vm ; GFX10-32-NEXT: exp mrt1 v0, v0, v0, v0 done vm
; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: s_endpgm
; GFX10-32-NEXT: BB0_2: ; GFX10-32-NEXT: .LBB0_2:
; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-32-NEXT: exp null off, off, off, off done vm ; GFX10-32-NEXT: exp null off, off, off, off done vm
; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: s_endpgm
; ;
; GFX10-64-LABEL: static_exact: ; GFX10-64-LABEL: static_exact:
; GFX10-64: ; %bb.0: ; %.entry ; GFX10-64: ; %bb.0: ; %.entry
; GFX10-64-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0 ; GFX10-64-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0
; GFX10-64-NEXT: s_andn2_b64 exec, exec, exec ; GFX10-64-NEXT: s_andn2_b64 exec, exec, exec
; GFX10-64-NEXT: s_cbranch_scc0 BB0_2 ; GFX10-64-NEXT: s_cbranch_scc0 .LBB0_2
; GFX10-64-NEXT: ; %bb.1: ; %.entry ; GFX10-64-NEXT: ; %bb.1: ; %.entry
; GFX10-64-NEXT: s_mov_b64 exec, 0 ; GFX10-64-NEXT: s_mov_b64 exec, 0
; GFX10-64-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc ; GFX10-64-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc
; GFX10-64-NEXT: exp mrt1 v0, v0, v0, v0 done vm ; GFX10-64-NEXT: exp mrt1 v0, v0, v0, v0 done vm
; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: s_endpgm
; GFX10-64-NEXT: BB0_2: ; GFX10-64-NEXT: .LBB0_2:
; GFX10-64-NEXT: s_mov_b64 exec, 0 ; GFX10-64-NEXT: s_mov_b64 exec, 0
; GFX10-64-NEXT: exp null off, off, off, off done vm ; GFX10-64-NEXT: exp null off, off, off, off done vm
; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: s_endpgm
.entry: .entry:
%c0 = fcmp olt float %arg0, 0.000000e+00 %c0 = fcmp olt float %arg0, 0.000000e+00
%c1 = fcmp oge float %arg1, 0.0 %c1 = fcmp oge float %arg1, 0.0
call void @llvm.amdgcn.wqm.demote(i1 false) call void @llvm.amdgcn.wqm.demote(i1 false)
%tmp1 = select i1 %c0, float 1.000000e+00, float 0.000000e+00 %tmp1 = select i1 %c0, float 1.000000e+00, float 0.000000e+00
call void @llvm.amdgcn.exp.f32(i32 1, i32 15, float %tmp1, float %tmp1, float %tmp1, float %tmp1, i1 true, i1 true) #0 call void @llvm.amdgcn.exp.f32(i32 1, i32 15, float %tmp1, float %tmp1, float %tmp1, float %tmp1, i1 true, i1 true) #0
ret void ret void
} }
define amdgpu_ps void @dynamic_exact(float %arg0, float %arg1) { define amdgpu_ps void @dynamic_exact(float %arg0, float %arg1) {
; SI-LABEL: dynamic_exact: ; SI-LABEL: dynamic_exact:
; SI: ; %bb.0: ; %.entry ; SI: ; %bb.0: ; %.entry
; SI-NEXT: v_cmp_le_f32_e64 s[0:1], 0, v1 ; SI-NEXT: v_cmp_le_f32_e64 s[0:1], 0, v1
; SI-NEXT: s_mov_b64 s[2:3], exec ; SI-NEXT: s_mov_b64 s[2:3], exec
; SI-NEXT: s_xor_b64 s[0:1], s[0:1], exec ; SI-NEXT: s_xor_b64 s[0:1], s[0:1], exec
; SI-NEXT: s_andn2_b64 s[2:3], s[2:3], s[0:1] ; SI-NEXT: s_andn2_b64 s[2:3], s[2:3], s[0:1]
; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0 ; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0
; SI-NEXT: s_cbranch_scc0 BB1_2 ; SI-NEXT: s_cbranch_scc0 .LBB1_2
; SI-NEXT: ; %bb.1: ; %.entry ; SI-NEXT: ; %bb.1: ; %.entry
; SI-NEXT: s_and_b64 exec, exec, s[2:3] ; SI-NEXT: s_and_b64 exec, exec, s[2:3]
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc ; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc
; SI-NEXT: exp mrt1 v0, v0, v0, v0 done vm ; SI-NEXT: exp mrt1 v0, v0, v0, v0 done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; SI-NEXT: BB1_2: ; SI-NEXT: .LBB1_2:
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: exp null off, off, off, off done vm ; SI-NEXT: exp null off, off, off, off done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; GFX9-LABEL: dynamic_exact: ; GFX9-LABEL: dynamic_exact:
; GFX9: ; %bb.0: ; %.entry ; GFX9: ; %bb.0: ; %.entry
; GFX9-NEXT: v_cmp_le_f32_e64 s[0:1], 0, v1 ; GFX9-NEXT: v_cmp_le_f32_e64 s[0:1], 0, v1
; GFX9-NEXT: s_mov_b64 s[2:3], exec ; GFX9-NEXT: s_mov_b64 s[2:3], exec
; GFX9-NEXT: s_xor_b64 s[0:1], s[0:1], exec ; GFX9-NEXT: s_xor_b64 s[0:1], s[0:1], exec
; GFX9-NEXT: s_andn2_b64 s[2:3], s[2:3], s[0:1] ; GFX9-NEXT: s_andn2_b64 s[2:3], s[2:3], s[0:1]
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0
; GFX9-NEXT: s_cbranch_scc0 BB1_2 ; GFX9-NEXT: s_cbranch_scc0 .LBB1_2
; GFX9-NEXT: ; %bb.1: ; %.entry ; GFX9-NEXT: ; %bb.1: ; %.entry
; GFX9-NEXT: s_and_b64 exec, exec, s[2:3] ; GFX9-NEXT: s_and_b64 exec, exec, s[2:3]
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc
; GFX9-NEXT: exp mrt1 v0, v0, v0, v0 done vm ; GFX9-NEXT: exp mrt1 v0, v0, v0, v0 done vm
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; GFX9-NEXT: BB1_2: ; GFX9-NEXT: .LBB1_2:
; GFX9-NEXT: s_mov_b64 exec, 0 ; GFX9-NEXT: s_mov_b64 exec, 0
; GFX9-NEXT: exp null off, off, off, off done vm ; GFX9-NEXT: exp null off, off, off, off done vm
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-32-LABEL: dynamic_exact: ; GFX10-32-LABEL: dynamic_exact:
; GFX10-32: ; %bb.0: ; %.entry ; GFX10-32: ; %bb.0: ; %.entry
; GFX10-32-NEXT: v_cmp_le_f32_e64 s0, 0, v1 ; GFX10-32-NEXT: v_cmp_le_f32_e64 s0, 0, v1
; GFX10-32-NEXT: s_mov_b32 s1, exec_lo ; GFX10-32-NEXT: s_mov_b32 s1, exec_lo
; GFX10-32-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v0 ; GFX10-32-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v0
; GFX10-32-NEXT: s_xor_b32 s0, s0, exec_lo ; GFX10-32-NEXT: s_xor_b32 s0, s0, exec_lo
; GFX10-32-NEXT: s_andn2_b32 s1, s1, s0 ; GFX10-32-NEXT: s_andn2_b32 s1, s1, s0
; GFX10-32-NEXT: s_cbranch_scc0 BB1_2 ; GFX10-32-NEXT: s_cbranch_scc0 .LBB1_2
; GFX10-32-NEXT: ; %bb.1: ; %.entry ; GFX10-32-NEXT: ; %bb.1: ; %.entry
; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s1 ; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s1
; GFX10-32-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo ; GFX10-32-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
; GFX10-32-NEXT: exp mrt1 v0, v0, v0, v0 done vm ; GFX10-32-NEXT: exp mrt1 v0, v0, v0, v0 done vm
; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: s_endpgm
; GFX10-32-NEXT: BB1_2: ; GFX10-32-NEXT: .LBB1_2:
; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-32-NEXT: exp null off, off, off, off done vm ; GFX10-32-NEXT: exp null off, off, off, off done vm
; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: s_endpgm
; ;
; GFX10-64-LABEL: dynamic_exact: ; GFX10-64-LABEL: dynamic_exact:
; GFX10-64: ; %bb.0: ; %.entry ; GFX10-64: ; %bb.0: ; %.entry
; GFX10-64-NEXT: v_cmp_le_f32_e64 s[0:1], 0, v1 ; GFX10-64-NEXT: v_cmp_le_f32_e64 s[0:1], 0, v1
; GFX10-64-NEXT: s_mov_b64 s[2:3], exec ; GFX10-64-NEXT: s_mov_b64 s[2:3], exec
; GFX10-64-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0 ; GFX10-64-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0
; GFX10-64-NEXT: s_xor_b64 s[0:1], s[0:1], exec ; GFX10-64-NEXT: s_xor_b64 s[0:1], s[0:1], exec
; GFX10-64-NEXT: s_andn2_b64 s[2:3], s[2:3], s[0:1] ; GFX10-64-NEXT: s_andn2_b64 s[2:3], s[2:3], s[0:1]
; GFX10-64-NEXT: s_cbranch_scc0 BB1_2 ; GFX10-64-NEXT: s_cbranch_scc0 .LBB1_2
; GFX10-64-NEXT: ; %bb.1: ; %.entry ; GFX10-64-NEXT: ; %bb.1: ; %.entry
; GFX10-64-NEXT: s_and_b64 exec, exec, s[2:3] ; GFX10-64-NEXT: s_and_b64 exec, exec, s[2:3]
; GFX10-64-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc ; GFX10-64-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc
; GFX10-64-NEXT: exp mrt1 v0, v0, v0, v0 done vm ; GFX10-64-NEXT: exp mrt1 v0, v0, v0, v0 done vm
; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: s_endpgm
; GFX10-64-NEXT: BB1_2: ; GFX10-64-NEXT: .LBB1_2:
; GFX10-64-NEXT: s_mov_b64 exec, 0 ; GFX10-64-NEXT: s_mov_b64 exec, 0
; GFX10-64-NEXT: exp null off, off, off, off done vm ; GFX10-64-NEXT: exp null off, off, off, off done vm
; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: s_endpgm
.entry: .entry:
%c0 = fcmp olt float %arg0, 0.000000e+00 %c0 = fcmp olt float %arg0, 0.000000e+00
%c1 = fcmp oge float %arg1, 0.0 %c1 = fcmp oge float %arg1, 0.0
call void @llvm.amdgcn.wqm.demote(i1 %c1) call void @llvm.amdgcn.wqm.demote(i1 %c1)
%tmp1 = select i1 %c0, float 1.000000e+00, float 0.000000e+00 %tmp1 = select i1 %c0, float 1.000000e+00, float 0.000000e+00
call void @llvm.amdgcn.exp.f32(i32 1, i32 15, float %tmp1, float %tmp1, float %tmp1, float %tmp1, i1 true, i1 true) #0 call void @llvm.amdgcn.exp.f32(i32 1, i32 15, float %tmp1, float %tmp1, float %tmp1, float %tmp1, i1 true, i1 true) #0
ret void ret void
} }
define amdgpu_ps void @branch(float %arg0, float %arg1) { define amdgpu_ps void @branch(float %arg0, float %arg1) {
; SI-LABEL: branch: ; SI-LABEL: branch:
; SI: ; %bb.0: ; %.entry ; SI: ; %bb.0: ; %.entry
; SI-NEXT: v_cvt_i32_f32_e32 v0, v0 ; SI-NEXT: v_cvt_i32_f32_e32 v0, v0
; SI-NEXT: v_cvt_i32_f32_e32 v1, v1 ; SI-NEXT: v_cvt_i32_f32_e32 v1, v1
; SI-NEXT: s_mov_b64 s[0:1], exec ; SI-NEXT: s_mov_b64 s[0:1], exec
; SI-NEXT: v_or_b32_e32 v0, v0, v1 ; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v0, 1, v0 ; SI-NEXT: v_and_b32_e32 v0, 1, v0
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; SI-NEXT: s_xor_b64 s[2:3], vcc, -1 ; SI-NEXT: s_xor_b64 s[2:3], vcc, -1
; SI-NEXT: s_and_saveexec_b64 s[4:5], s[2:3] ; SI-NEXT: s_and_saveexec_b64 s[4:5], s[2:3]
; SI-NEXT: s_xor_b64 s[2:3], exec, s[4:5] ; SI-NEXT: s_xor_b64 s[2:3], exec, s[4:5]
; SI-NEXT: s_cbranch_execz BB2_3 ; SI-NEXT: s_cbranch_execz .LBB2_3
; SI-NEXT: ; %bb.1: ; %.demote ; SI-NEXT: ; %bb.1: ; %.demote
; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; SI-NEXT: s_cbranch_scc0 BB2_4 ; SI-NEXT: s_cbranch_scc0 .LBB2_4
; SI-NEXT: ; %bb.2: ; %.demote ; SI-NEXT: ; %bb.2: ; %.demote
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: BB2_3: ; %.continue ; SI-NEXT: .LBB2_3: ; %.continue
; SI-NEXT: s_or_b64 exec, exec, s[2:3] ; SI-NEXT: s_or_b64 exec, exec, s[2:3]
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc ; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc
; SI-NEXT: exp mrt1 v0, v0, v0, v0 done vm ; SI-NEXT: exp mrt1 v0, v0, v0, v0 done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; SI-NEXT: BB2_4: ; SI-NEXT: .LBB2_4:
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: exp null off, off, off, off done vm ; SI-NEXT: exp null off, off, off, off done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; GFX9-LABEL: branch: ; GFX9-LABEL: branch:
; GFX9: ; %bb.0: ; %.entry ; GFX9: ; %bb.0: ; %.entry
; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_i32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX9-NEXT: s_mov_b64 s[0:1], exec ; GFX9-NEXT: s_mov_b64 s[0:1], exec
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-NEXT: s_xor_b64 s[2:3], vcc, -1 ; GFX9-NEXT: s_xor_b64 s[2:3], vcc, -1
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], s[2:3] ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], s[2:3]
; GFX9-NEXT: s_xor_b64 s[2:3], exec, s[4:5] ; GFX9-NEXT: s_xor_b64 s[2:3], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz BB2_3 ; GFX9-NEXT: s_cbranch_execz .LBB2_3
; GFX9-NEXT: ; %bb.1: ; %.demote ; GFX9-NEXT: ; %bb.1: ; %.demote
; GFX9-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; GFX9-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; GFX9-NEXT: s_cbranch_scc0 BB2_4 ; GFX9-NEXT: s_cbranch_scc0 .LBB2_4
; GFX9-NEXT: ; %bb.2: ; %.demote ; GFX9-NEXT: ; %bb.2: ; %.demote
; GFX9-NEXT: s_mov_b64 exec, 0 ; GFX9-NEXT: s_mov_b64 exec, 0
; GFX9-NEXT: BB2_3: ; %.continue ; GFX9-NEXT: .LBB2_3: ; %.continue
; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX9-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc
; GFX9-NEXT: exp mrt1 v0, v0, v0, v0 done vm ; GFX9-NEXT: exp mrt1 v0, v0, v0, v0 done vm
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; GFX9-NEXT: BB2_4: ; GFX9-NEXT: .LBB2_4:
; GFX9-NEXT: s_mov_b64 exec, 0 ; GFX9-NEXT: s_mov_b64 exec, 0
; GFX9-NEXT: exp null off, off, off, off done vm ; GFX9-NEXT: exp null off, off, off, off done vm
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-32-LABEL: branch: ; GFX10-32-LABEL: branch:
; GFX10-32: ; %bb.0: ; %.entry ; GFX10-32: ; %bb.0: ; %.entry
; GFX10-32-NEXT: v_cvt_i32_f32_e32 v0, v0 ; GFX10-32-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX10-32-NEXT: v_cvt_i32_f32_e32 v1, v1 ; GFX10-32-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX10-32-NEXT: s_mov_b32 s0, exec_lo ; GFX10-32-NEXT: s_mov_b32 s0, exec_lo
; GFX10-32-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX10-32-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-32-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX10-32-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX10-32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX10-32-NEXT: s_xor_b32 s1, vcc_lo, -1 ; GFX10-32-NEXT: s_xor_b32 s1, vcc_lo, -1
; GFX10-32-NEXT: s_and_saveexec_b32 s2, s1 ; GFX10-32-NEXT: s_and_saveexec_b32 s2, s1
; GFX10-32-NEXT: s_xor_b32 s1, exec_lo, s2 ; GFX10-32-NEXT: s_xor_b32 s1, exec_lo, s2
; GFX10-32-NEXT: s_cbranch_execz BB2_3 ; GFX10-32-NEXT: s_cbranch_execz .LBB2_3
; GFX10-32-NEXT: ; %bb.1: ; %.demote ; GFX10-32-NEXT: ; %bb.1: ; %.demote
; GFX10-32-NEXT: s_andn2_b32 s0, s0, exec_lo ; GFX10-32-NEXT: s_andn2_b32 s0, s0, exec_lo
; GFX10-32-NEXT: s_cbranch_scc0 BB2_4 ; GFX10-32-NEXT: s_cbranch_scc0 .LBB2_4
; GFX10-32-NEXT: ; %bb.2: ; %.demote ; GFX10-32-NEXT: ; %bb.2: ; %.demote
; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-32-NEXT: BB2_3: ; %.continue ; GFX10-32-NEXT: .LBB2_3: ; %.continue
; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s1 ; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX10-32-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo ; GFX10-32-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
; GFX10-32-NEXT: exp mrt1 v0, v0, v0, v0 done vm ; GFX10-32-NEXT: exp mrt1 v0, v0, v0, v0 done vm
; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: s_endpgm
; GFX10-32-NEXT: BB2_4: ; GFX10-32-NEXT: .LBB2_4:
; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-32-NEXT: exp null off, off, off, off done vm ; GFX10-32-NEXT: exp null off, off, off, off done vm
; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: s_endpgm
; ;
; GFX10-64-LABEL: branch: ; GFX10-64-LABEL: branch:
; GFX10-64: ; %bb.0: ; %.entry ; GFX10-64: ; %bb.0: ; %.entry
; GFX10-64-NEXT: v_cvt_i32_f32_e32 v0, v0 ; GFX10-64-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX10-64-NEXT: v_cvt_i32_f32_e32 v1, v1 ; GFX10-64-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX10-64-NEXT: s_mov_b64 s[0:1], exec ; GFX10-64-NEXT: s_mov_b64 s[0:1], exec
; GFX10-64-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX10-64-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-64-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX10-64-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX10-64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX10-64-NEXT: s_xor_b64 s[2:3], vcc, -1 ; GFX10-64-NEXT: s_xor_b64 s[2:3], vcc, -1
; GFX10-64-NEXT: s_and_saveexec_b64 s[4:5], s[2:3] ; GFX10-64-NEXT: s_and_saveexec_b64 s[4:5], s[2:3]
; GFX10-64-NEXT: s_xor_b64 s[2:3], exec, s[4:5] ; GFX10-64-NEXT: s_xor_b64 s[2:3], exec, s[4:5]
; GFX10-64-NEXT: s_cbranch_execz BB2_3 ; GFX10-64-NEXT: s_cbranch_execz .LBB2_3
; GFX10-64-NEXT: ; %bb.1: ; %.demote ; GFX10-64-NEXT: ; %bb.1: ; %.demote
; GFX10-64-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; GFX10-64-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; GFX10-64-NEXT: s_cbranch_scc0 BB2_4 ; GFX10-64-NEXT: s_cbranch_scc0 .LBB2_4
; GFX10-64-NEXT: ; %bb.2: ; %.demote ; GFX10-64-NEXT: ; %bb.2: ; %.demote
; GFX10-64-NEXT: s_mov_b64 exec, 0 ; GFX10-64-NEXT: s_mov_b64 exec, 0
; GFX10-64-NEXT: BB2_3: ; %.continue ; GFX10-64-NEXT: .LBB2_3: ; %.continue
; GFX10-64-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX10-64-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX10-64-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc ; GFX10-64-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc
; GFX10-64-NEXT: exp mrt1 v0, v0, v0, v0 done vm ; GFX10-64-NEXT: exp mrt1 v0, v0, v0, v0 done vm
; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: s_endpgm
; GFX10-64-NEXT: BB2_4: ; GFX10-64-NEXT: .LBB2_4:
; GFX10-64-NEXT: s_mov_b64 exec, 0 ; GFX10-64-NEXT: s_mov_b64 exec, 0
; GFX10-64-NEXT: exp null off, off, off, off done vm ; GFX10-64-NEXT: exp null off, off, off, off done vm
; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: s_endpgm
.entry: .entry:
%i0 = fptosi float %arg0 to i32 %i0 = fptosi float %arg0 to i32
%i1 = fptosi float %arg1 to i32 %i1 = fptosi float %arg1 to i32
%c0 = or i32 %i0, %i1 %c0 = or i32 %i0, %i1
%c1 = and i32 %c0, 1 %c1 = and i32 %c0, 1
Show All 13 Lines
define amdgpu_ps <4 x float> @wqm_demote_1(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, i32 %idx, float %data, float %coord, float %coord2, float %z) { define amdgpu_ps <4 x float> @wqm_demote_1(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, i32 %idx, float %data, float %coord, float %coord2, float %z) {
; SI-LABEL: wqm_demote_1: ; SI-LABEL: wqm_demote_1:
; SI: ; %bb.0: ; %.entry ; SI: ; %bb.0: ; %.entry
; SI-NEXT: s_mov_b64 s[12:13], exec ; SI-NEXT: s_mov_b64 s[12:13], exec
; SI-NEXT: s_wqm_b64 exec, exec ; SI-NEXT: s_wqm_b64 exec, exec
; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v1 ; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v1
; SI-NEXT: s_and_saveexec_b64 s[14:15], vcc ; SI-NEXT: s_and_saveexec_b64 s[14:15], vcc
; SI-NEXT: s_xor_b64 s[14:15], exec, s[14:15] ; SI-NEXT: s_xor_b64 s[14:15], exec, s[14:15]
; SI-NEXT: s_cbranch_execz BB3_3 ; SI-NEXT: s_cbranch_execz .LBB3_3
; SI-NEXT: ; %bb.1: ; %.demote ; SI-NEXT: ; %bb.1: ; %.demote
; SI-NEXT: s_andn2_b64 s[12:13], s[12:13], exec ; SI-NEXT: s_andn2_b64 s[12:13], s[12:13], exec
; SI-NEXT: s_cbranch_scc0 BB3_4 ; SI-NEXT: s_cbranch_scc0 .LBB3_4
; SI-NEXT: ; %bb.2: ; %.demote ; SI-NEXT: ; %bb.2: ; %.demote
; SI-NEXT: s_wqm_b64 s[16:17], s[12:13] ; SI-NEXT: s_wqm_b64 s[16:17], s[12:13]
; SI-NEXT: s_and_b64 exec, exec, s[16:17] ; SI-NEXT: s_and_b64 exec, exec, s[16:17]
; SI-NEXT: BB3_3: ; %.continue ; SI-NEXT: .LBB3_3: ; %.continue
; SI-NEXT: s_or_b64 exec, exec, s[14:15] ; SI-NEXT: s_or_b64 exec, exec, s[14:15]
; SI-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf ; SI-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_f32_e32 v0, v0, v0 ; SI-NEXT: v_add_f32_e32 v0, v0, v0
; SI-NEXT: s_and_b64 exec, exec, s[12:13] ; SI-NEXT: s_and_b64 exec, exec, s[12:13]
; SI-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf ; SI-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_branch BB3_5 ; SI-NEXT: s_branch .LBB3_5
; SI-NEXT: BB3_4: ; SI-NEXT: .LBB3_4:
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: exp null off, off, off, off done vm ; SI-NEXT: exp null off, off, off, off done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; SI-NEXT: BB3_5: ; SI-NEXT: .LBB3_5:
; ;
; GFX9-LABEL: wqm_demote_1: ; GFX9-LABEL: wqm_demote_1:
; GFX9: ; %bb.0: ; %.entry ; GFX9: ; %bb.0: ; %.entry
; GFX9-NEXT: s_mov_b64 s[12:13], exec ; GFX9-NEXT: s_mov_b64 s[12:13], exec
; GFX9-NEXT: s_wqm_b64 exec, exec ; GFX9-NEXT: s_wqm_b64 exec, exec
; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v1 ; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v1
; GFX9-NEXT: s_and_saveexec_b64 s[14:15], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[14:15], vcc
; GFX9-NEXT: s_xor_b64 s[14:15], exec, s[14:15] ; GFX9-NEXT: s_xor_b64 s[14:15], exec, s[14:15]
; GFX9-NEXT: s_cbranch_execz BB3_3 ; GFX9-NEXT: s_cbranch_execz .LBB3_3
; GFX9-NEXT: ; %bb.1: ; %.demote ; GFX9-NEXT: ; %bb.1: ; %.demote
; GFX9-NEXT: s_andn2_b64 s[12:13], s[12:13], exec ; GFX9-NEXT: s_andn2_b64 s[12:13], s[12:13], exec
; GFX9-NEXT: s_cbranch_scc0 BB3_4 ; GFX9-NEXT: s_cbranch_scc0 .LBB3_4
; GFX9-NEXT: ; %bb.2: ; %.demote ; GFX9-NEXT: ; %bb.2: ; %.demote
; GFX9-NEXT: s_wqm_b64 s[16:17], s[12:13] ; GFX9-NEXT: s_wqm_b64 s[16:17], s[12:13]
; GFX9-NEXT: s_and_b64 exec, exec, s[16:17] ; GFX9-NEXT: s_and_b64 exec, exec, s[16:17]
; GFX9-NEXT: BB3_3: ; %.continue ; GFX9-NEXT: .LBB3_3: ; %.continue
; GFX9-NEXT: s_or_b64 exec, exec, s[14:15] ; GFX9-NEXT: s_or_b64 exec, exec, s[14:15]
; GFX9-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf ; GFX9-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_f32_e32 v0, v0, v0 ; GFX9-NEXT: v_add_f32_e32 v0, v0, v0
; GFX9-NEXT: s_and_b64 exec, exec, s[12:13] ; GFX9-NEXT: s_and_b64 exec, exec, s[12:13]
; GFX9-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf ; GFX9-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_branch BB3_5 ; GFX9-NEXT: s_branch .LBB3_5
; GFX9-NEXT: BB3_4: ; GFX9-NEXT: .LBB3_4:
; GFX9-NEXT: s_mov_b64 exec, 0 ; GFX9-NEXT: s_mov_b64 exec, 0
; GFX9-NEXT: exp null off, off, off, off done vm ; GFX9-NEXT: exp null off, off, off, off done vm
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; GFX9-NEXT: BB3_5: ; GFX9-NEXT: .LBB3_5:
; ;
; GFX10-32-LABEL: wqm_demote_1: ; GFX10-32-LABEL: wqm_demote_1:
; GFX10-32: ; %bb.0: ; %.entry ; GFX10-32: ; %bb.0: ; %.entry
; GFX10-32-NEXT: s_mov_b32 s12, exec_lo ; GFX10-32-NEXT: s_mov_b32 s12, exec_lo
; GFX10-32-NEXT: s_wqm_b32 exec_lo, exec_lo ; GFX10-32-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX10-32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v1 ; GFX10-32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v1
; GFX10-32-NEXT: s_and_saveexec_b32 s13, vcc_lo ; GFX10-32-NEXT: s_and_saveexec_b32 s13, vcc_lo
; GFX10-32-NEXT: s_xor_b32 s13, exec_lo, s13 ; GFX10-32-NEXT: s_xor_b32 s13, exec_lo, s13
; GFX10-32-NEXT: s_cbranch_execz BB3_3 ; GFX10-32-NEXT: s_cbranch_execz .LBB3_3
; GFX10-32-NEXT: ; %bb.1: ; %.demote ; GFX10-32-NEXT: ; %bb.1: ; %.demote
; GFX10-32-NEXT: s_andn2_b32 s12, s12, exec_lo ; GFX10-32-NEXT: s_andn2_b32 s12, s12, exec_lo
; GFX10-32-NEXT: s_cbranch_scc0 BB3_4 ; GFX10-32-NEXT: s_cbranch_scc0 .LBB3_4
; GFX10-32-NEXT: ; %bb.2: ; %.demote ; GFX10-32-NEXT: ; %bb.2: ; %.demote
; GFX10-32-NEXT: s_wqm_b32 s14, s12 ; GFX10-32-NEXT: s_wqm_b32 s14, s12
; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s14 ; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s14
; GFX10-32-NEXT: BB3_3: ; %.continue ; GFX10-32-NEXT: .LBB3_3: ; %.continue
; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s13 ; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s13
; GFX10-32-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; GFX10-32-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10-32-NEXT: s_waitcnt vmcnt(0) ; GFX10-32-NEXT: s_waitcnt vmcnt(0)
; GFX10-32-NEXT: v_add_f32_e32 v0, v0, v0 ; GFX10-32-NEXT: v_add_f32_e32 v0, v0, v0
; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s12
; GFX10-32-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; GFX10-32-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10-32-NEXT: s_waitcnt vmcnt(0) ; GFX10-32-NEXT: s_waitcnt vmcnt(0)
; GFX10-32-NEXT: s_branch BB3_5 ; GFX10-32-NEXT: s_branch .LBB3_5
; GFX10-32-NEXT: BB3_4: ; GFX10-32-NEXT: .LBB3_4:
; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-32-NEXT: exp null off, off, off, off done vm ; GFX10-32-NEXT: exp null off, off, off, off done vm
; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: s_endpgm
; GFX10-32-NEXT: BB3_5: ; GFX10-32-NEXT: .LBB3_5:
; ;
; GFX10-64-LABEL: wqm_demote_1: ; GFX10-64-LABEL: wqm_demote_1:
; GFX10-64: ; %bb.0: ; %.entry ; GFX10-64: ; %bb.0: ; %.entry
; GFX10-64-NEXT: s_mov_b64 s[12:13], exec ; GFX10-64-NEXT: s_mov_b64 s[12:13], exec
; GFX10-64-NEXT: s_wqm_b64 exec, exec ; GFX10-64-NEXT: s_wqm_b64 exec, exec
; GFX10-64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v1 ; GFX10-64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v1
; GFX10-64-NEXT: s_and_saveexec_b64 s[14:15], vcc ; GFX10-64-NEXT: s_and_saveexec_b64 s[14:15], vcc
; GFX10-64-NEXT: s_xor_b64 s[14:15], exec, s[14:15] ; GFX10-64-NEXT: s_xor_b64 s[14:15], exec, s[14:15]
; GFX10-64-NEXT: s_cbranch_execz BB3_3 ; GFX10-64-NEXT: s_cbranch_execz .LBB3_3
; GFX10-64-NEXT: ; %bb.1: ; %.demote ; GFX10-64-NEXT: ; %bb.1: ; %.demote
; GFX10-64-NEXT: s_andn2_b64 s[12:13], s[12:13], exec ; GFX10-64-NEXT: s_andn2_b64 s[12:13], s[12:13], exec
; GFX10-64-NEXT: s_cbranch_scc0 BB3_4 ; GFX10-64-NEXT: s_cbranch_scc0 .LBB3_4
; GFX10-64-NEXT: ; %bb.2: ; %.demote ; GFX10-64-NEXT: ; %bb.2: ; %.demote
; GFX10-64-NEXT: s_wqm_b64 s[16:17], s[12:13] ; GFX10-64-NEXT: s_wqm_b64 s[16:17], s[12:13]
; GFX10-64-NEXT: s_and_b64 exec, exec, s[16:17] ; GFX10-64-NEXT: s_and_b64 exec, exec, s[16:17]
; GFX10-64-NEXT: BB3_3: ; %.continue ; GFX10-64-NEXT: .LBB3_3: ; %.continue
; GFX10-64-NEXT: s_or_b64 exec, exec, s[14:15] ; GFX10-64-NEXT: s_or_b64 exec, exec, s[14:15]
; GFX10-64-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; GFX10-64-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10-64-NEXT: s_waitcnt vmcnt(0) ; GFX10-64-NEXT: s_waitcnt vmcnt(0)
; GFX10-64-NEXT: v_add_f32_e32 v0, v0, v0 ; GFX10-64-NEXT: v_add_f32_e32 v0, v0, v0
; GFX10-64-NEXT: s_and_b64 exec, exec, s[12:13] ; GFX10-64-NEXT: s_and_b64 exec, exec, s[12:13]
; GFX10-64-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; GFX10-64-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10-64-NEXT: s_waitcnt vmcnt(0) ; GFX10-64-NEXT: s_waitcnt vmcnt(0)
; GFX10-64-NEXT: s_branch BB3_5 ; GFX10-64-NEXT: s_branch .LBB3_5
; GFX10-64-NEXT: BB3_4: ; GFX10-64-NEXT: .LBB3_4:
; GFX10-64-NEXT: s_mov_b64 exec, 0 ; GFX10-64-NEXT: s_mov_b64 exec, 0
; GFX10-64-NEXT: exp null off, off, off, off done vm ; GFX10-64-NEXT: exp null off, off, off, off done vm
; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: s_endpgm
; GFX10-64-NEXT: BB3_5: ; GFX10-64-NEXT: .LBB3_5:
.entry: .entry:
%z.cmp = fcmp olt float %z, 0.0 %z.cmp = fcmp olt float %z, 0.0
br i1 %z.cmp, label %.continue, label %.demote br i1 %z.cmp, label %.continue, label %.demote
.demote: .demote:
call void @llvm.amdgcn.wqm.demote(i1 false) call void @llvm.amdgcn.wqm.demote(i1 false)
br label %.continue br label %.continue
Show All 12 Lines
; SI: ; %bb.0: ; %.entry ; SI: ; %bb.0: ; %.entry
; SI-NEXT: s_mov_b64 s[12:13], exec ; SI-NEXT: s_mov_b64 s[12:13], exec
; SI-NEXT: s_wqm_b64 exec, exec ; SI-NEXT: s_wqm_b64 exec, exec
; SI-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf ; SI-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0 ; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0
; SI-NEXT: s_and_saveexec_b64 s[14:15], vcc ; SI-NEXT: s_and_saveexec_b64 s[14:15], vcc
; SI-NEXT: s_xor_b64 s[14:15], exec, s[14:15] ; SI-NEXT: s_xor_b64 s[14:15], exec, s[14:15]
; SI-NEXT: s_cbranch_execz BB4_3 ; SI-NEXT: s_cbranch_execz .LBB4_3
; SI-NEXT: ; %bb.1: ; %.demote ; SI-NEXT: ; %bb.1: ; %.demote
; SI-NEXT: s_andn2_b64 s[12:13], s[12:13], exec ; SI-NEXT: s_andn2_b64 s[12:13], s[12:13], exec
; SI-NEXT: s_cbranch_scc0 BB4_4 ; SI-NEXT: s_cbranch_scc0 .LBB4_4
; SI-NEXT: ; %bb.2: ; %.demote ; SI-NEXT: ; %bb.2: ; %.demote
; SI-NEXT: s_wqm_b64 s[16:17], s[12:13] ; SI-NEXT: s_wqm_b64 s[16:17], s[12:13]
; SI-NEXT: s_and_b64 exec, exec, s[16:17] ; SI-NEXT: s_and_b64 exec, exec, s[16:17]
; SI-NEXT: BB4_3: ; %.continue ; SI-NEXT: .LBB4_3: ; %.continue
; SI-NEXT: s_or_b64 exec, exec, s[14:15] ; SI-NEXT: s_or_b64 exec, exec, s[14:15]
; SI-NEXT: v_add_f32_e32 v0, v0, v0 ; SI-NEXT: v_add_f32_e32 v0, v0, v0
; SI-NEXT: s_and_b64 exec, exec, s[12:13] ; SI-NEXT: s_and_b64 exec, exec, s[12:13]
; SI-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf ; SI-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_branch BB4_5 ; SI-NEXT: s_branch .LBB4_5
; SI-NEXT: BB4_4: ; SI-NEXT: .LBB4_4:
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: exp null off, off, off, off done vm ; SI-NEXT: exp null off, off, off, off done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; SI-NEXT: BB4_5: ; SI-NEXT: .LBB4_5:
; ;
; GFX9-LABEL: wqm_demote_2: ; GFX9-LABEL: wqm_demote_2:
; GFX9: ; %bb.0: ; %.entry ; GFX9: ; %bb.0: ; %.entry
; GFX9-NEXT: s_mov_b64 s[12:13], exec ; GFX9-NEXT: s_mov_b64 s[12:13], exec
; GFX9-NEXT: s_wqm_b64 exec, exec ; GFX9-NEXT: s_wqm_b64 exec, exec
; GFX9-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf ; GFX9-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0
; GFX9-NEXT: s_and_saveexec_b64 s[14:15], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[14:15], vcc
; GFX9-NEXT: s_xor_b64 s[14:15], exec, s[14:15] ; GFX9-NEXT: s_xor_b64 s[14:15], exec, s[14:15]
; GFX9-NEXT: s_cbranch_execz BB4_3 ; GFX9-NEXT: s_cbranch_execz .LBB4_3
; GFX9-NEXT: ; %bb.1: ; %.demote ; GFX9-NEXT: ; %bb.1: ; %.demote
; GFX9-NEXT: s_andn2_b64 s[12:13], s[12:13], exec ; GFX9-NEXT: s_andn2_b64 s[12:13], s[12:13], exec
; GFX9-NEXT: s_cbranch_scc0 BB4_4 ; GFX9-NEXT: s_cbranch_scc0 .LBB4_4
; GFX9-NEXT: ; %bb.2: ; %.demote ; GFX9-NEXT: ; %bb.2: ; %.demote
; GFX9-NEXT: s_wqm_b64 s[16:17], s[12:13] ; GFX9-NEXT: s_wqm_b64 s[16:17], s[12:13]
; GFX9-NEXT: s_and_b64 exec, exec, s[16:17] ; GFX9-NEXT: s_and_b64 exec, exec, s[16:17]
; GFX9-NEXT: BB4_3: ; %.continue ; GFX9-NEXT: .LBB4_3: ; %.continue
; GFX9-NEXT: s_or_b64 exec, exec, s[14:15] ; GFX9-NEXT: s_or_b64 exec, exec, s[14:15]
; GFX9-NEXT: v_add_f32_e32 v0, v0, v0 ; GFX9-NEXT: v_add_f32_e32 v0, v0, v0
; GFX9-NEXT: s_and_b64 exec, exec, s[12:13] ; GFX9-NEXT: s_and_b64 exec, exec, s[12:13]
; GFX9-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf ; GFX9-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_branch BB4_5 ; GFX9-NEXT: s_branch .LBB4_5
; GFX9-NEXT: BB4_4: ; GFX9-NEXT: .LBB4_4:
; GFX9-NEXT: s_mov_b64 exec, 0 ; GFX9-NEXT: s_mov_b64 exec, 0
; GFX9-NEXT: exp null off, off, off, off done vm ; GFX9-NEXT: exp null off, off, off, off done vm
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; GFX9-NEXT: BB4_5: ; GFX9-NEXT: .LBB4_5:
; ;
; GFX10-32-LABEL: wqm_demote_2: ; GFX10-32-LABEL: wqm_demote_2:
; GFX10-32: ; %bb.0: ; %.entry ; GFX10-32: ; %bb.0: ; %.entry
; GFX10-32-NEXT: s_mov_b32 s12, exec_lo ; GFX10-32-NEXT: s_mov_b32 s12, exec_lo
; GFX10-32-NEXT: s_wqm_b32 exec_lo, exec_lo ; GFX10-32-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX10-32-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; GFX10-32-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10-32-NEXT: s_waitcnt vmcnt(0) ; GFX10-32-NEXT: s_waitcnt vmcnt(0)
; GFX10-32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v0 ; GFX10-32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v0
; GFX10-32-NEXT: s_and_saveexec_b32 s13, vcc_lo ; GFX10-32-NEXT: s_and_saveexec_b32 s13, vcc_lo
; GFX10-32-NEXT: s_xor_b32 s13, exec_lo, s13 ; GFX10-32-NEXT: s_xor_b32 s13, exec_lo, s13
; GFX10-32-NEXT: s_cbranch_execz BB4_3 ; GFX10-32-NEXT: s_cbranch_execz .LBB4_3
; GFX10-32-NEXT: ; %bb.1: ; %.demote ; GFX10-32-NEXT: ; %bb.1: ; %.demote
; GFX10-32-NEXT: s_andn2_b32 s12, s12, exec_lo ; GFX10-32-NEXT: s_andn2_b32 s12, s12, exec_lo
; GFX10-32-NEXT: s_cbranch_scc0 BB4_4 ; GFX10-32-NEXT: s_cbranch_scc0 .LBB4_4
; GFX10-32-NEXT: ; %bb.2: ; %.demote ; GFX10-32-NEXT: ; %bb.2: ; %.demote
; GFX10-32-NEXT: s_wqm_b32 s14, s12 ; GFX10-32-NEXT: s_wqm_b32 s14, s12
; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s14 ; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s14
; GFX10-32-NEXT: BB4_3: ; %.continue ; GFX10-32-NEXT: .LBB4_3: ; %.continue
; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s13 ; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s13
; GFX10-32-NEXT: v_add_f32_e32 v0, v0, v0 ; GFX10-32-NEXT: v_add_f32_e32 v0, v0, v0
; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s12
; GFX10-32-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; GFX10-32-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10-32-NEXT: s_waitcnt vmcnt(0) ; GFX10-32-NEXT: s_waitcnt vmcnt(0)
; GFX10-32-NEXT: s_branch BB4_5 ; GFX10-32-NEXT: s_branch .LBB4_5
; GFX10-32-NEXT: BB4_4: ; GFX10-32-NEXT: .LBB4_4:
; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-32-NEXT: exp null off, off, off, off done vm ; GFX10-32-NEXT: exp null off, off, off, off done vm
; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: s_endpgm
; GFX10-32-NEXT: BB4_5: ; GFX10-32-NEXT: .LBB4_5:
; ;
; GFX10-64-LABEL: wqm_demote_2: ; GFX10-64-LABEL: wqm_demote_2:
; GFX10-64: ; %bb.0: ; %.entry ; GFX10-64: ; %bb.0: ; %.entry
; GFX10-64-NEXT: s_mov_b64 s[12:13], exec ; GFX10-64-NEXT: s_mov_b64 s[12:13], exec
; GFX10-64-NEXT: s_wqm_b64 exec, exec ; GFX10-64-NEXT: s_wqm_b64 exec, exec
; GFX10-64-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; GFX10-64-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10-64-NEXT: s_waitcnt vmcnt(0) ; GFX10-64-NEXT: s_waitcnt vmcnt(0)
; GFX10-64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0 ; GFX10-64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0
; GFX10-64-NEXT: s_and_saveexec_b64 s[14:15], vcc ; GFX10-64-NEXT: s_and_saveexec_b64 s[14:15], vcc
; GFX10-64-NEXT: s_xor_b64 s[14:15], exec, s[14:15] ; GFX10-64-NEXT: s_xor_b64 s[14:15], exec, s[14:15]
; GFX10-64-NEXT: s_cbranch_execz BB4_3 ; GFX10-64-NEXT: s_cbranch_execz .LBB4_3
; GFX10-64-NEXT: ; %bb.1: ; %.demote ; GFX10-64-NEXT: ; %bb.1: ; %.demote
; GFX10-64-NEXT: s_andn2_b64 s[12:13], s[12:13], exec ; GFX10-64-NEXT: s_andn2_b64 s[12:13], s[12:13], exec
; GFX10-64-NEXT: s_cbranch_scc0 BB4_4 ; GFX10-64-NEXT: s_cbranch_scc0 .LBB4_4
; GFX10-64-NEXT: ; %bb.2: ; %.demote ; GFX10-64-NEXT: ; %bb.2: ; %.demote
; GFX10-64-NEXT: s_wqm_b64 s[16:17], s[12:13] ; GFX10-64-NEXT: s_wqm_b64 s[16:17], s[12:13]
; GFX10-64-NEXT: s_and_b64 exec, exec, s[16:17] ; GFX10-64-NEXT: s_and_b64 exec, exec, s[16:17]
; GFX10-64-NEXT: BB4_3: ; %.continue ; GFX10-64-NEXT: .LBB4_3: ; %.continue
; GFX10-64-NEXT: s_or_b64 exec, exec, s[14:15] ; GFX10-64-NEXT: s_or_b64 exec, exec, s[14:15]
; GFX10-64-NEXT: v_add_f32_e32 v0, v0, v0 ; GFX10-64-NEXT: v_add_f32_e32 v0, v0, v0
; GFX10-64-NEXT: s_and_b64 exec, exec, s[12:13] ; GFX10-64-NEXT: s_and_b64 exec, exec, s[12:13]
; GFX10-64-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; GFX10-64-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10-64-NEXT: s_waitcnt vmcnt(0) ; GFX10-64-NEXT: s_waitcnt vmcnt(0)
; GFX10-64-NEXT: s_branch BB4_5 ; GFX10-64-NEXT: s_branch .LBB4_5
; GFX10-64-NEXT: BB4_4: ; GFX10-64-NEXT: .LBB4_4:
; GFX10-64-NEXT: s_mov_b64 exec, 0 ; GFX10-64-NEXT: s_mov_b64 exec, 0
; GFX10-64-NEXT: exp null off, off, off, off done vm ; GFX10-64-NEXT: exp null off, off, off, off done vm
; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: s_endpgm
; GFX10-64-NEXT: BB4_5: ; GFX10-64-NEXT: .LBB4_5:
.entry: .entry:
%tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %coord, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0 %tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %coord, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0
%tex0 = extractelement <4 x float> %tex, i32 0 %tex0 = extractelement <4 x float> %tex, i32 0
%tex1 = extractelement <4 x float> %tex, i32 0 %tex1 = extractelement <4 x float> %tex, i32 0
%z.cmp = fcmp olt float %tex0, 0.0 %z.cmp = fcmp olt float %tex0, 0.0
br i1 %z.cmp, label %.continue, label %.demote br i1 %z.cmp, label %.continue, label %.demote
.demote: .demote:
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; SI: ; %bb.0: ; %.entry ; SI: ; %bb.0: ; %.entry
; SI-NEXT: s_mov_b64 s[12:13], exec ; SI-NEXT: s_mov_b64 s[12:13], exec
; SI-NEXT: s_wqm_b64 exec, exec ; SI-NEXT: s_wqm_b64 exec, exec
; SI-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf ; SI-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0 ; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0
; SI-NEXT: s_xor_b64 s[14:15], vcc, exec ; SI-NEXT: s_xor_b64 s[14:15], vcc, exec
; SI-NEXT: s_andn2_b64 s[12:13], s[12:13], s[14:15] ; SI-NEXT: s_andn2_b64 s[12:13], s[12:13], s[14:15]
; SI-NEXT: s_cbranch_scc0 BB5_2 ; SI-NEXT: s_cbranch_scc0 .LBB5_2
; SI-NEXT: ; %bb.1: ; %.entry ; SI-NEXT: ; %bb.1: ; %.entry
; SI-NEXT: s_wqm_b64 s[14:15], s[12:13] ; SI-NEXT: s_wqm_b64 s[14:15], s[12:13]
; SI-NEXT: s_and_b64 exec, exec, s[14:15] ; SI-NEXT: s_and_b64 exec, exec, s[14:15]
; SI-NEXT: v_add_f32_e32 v0, v0, v0 ; SI-NEXT: v_add_f32_e32 v0, v0, v0
; SI-NEXT: s_and_b64 exec, exec, s[12:13] ; SI-NEXT: s_and_b64 exec, exec, s[12:13]
; SI-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf ; SI-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_branch BB5_3 ; SI-NEXT: s_branch .LBB5_3
; SI-NEXT: BB5_2: ; SI-NEXT: .LBB5_2:
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: exp null off, off, off, off done vm ; SI-NEXT: exp null off, off, off, off done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; SI-NEXT: BB5_3: ; SI-NEXT: .LBB5_3:
; ;
; GFX9-LABEL: wqm_demote_dynamic: ; GFX9-LABEL: wqm_demote_dynamic:
; GFX9: ; %bb.0: ; %.entry ; GFX9: ; %bb.0: ; %.entry
; GFX9-NEXT: s_mov_b64 s[12:13], exec ; GFX9-NEXT: s_mov_b64 s[12:13], exec
; GFX9-NEXT: s_wqm_b64 exec, exec ; GFX9-NEXT: s_wqm_b64 exec, exec
; GFX9-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf ; GFX9-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0
; GFX9-NEXT: s_xor_b64 s[14:15], vcc, exec ; GFX9-NEXT: s_xor_b64 s[14:15], vcc, exec
; GFX9-NEXT: s_andn2_b64 s[12:13], s[12:13], s[14:15] ; GFX9-NEXT: s_andn2_b64 s[12:13], s[12:13], s[14:15]
; GFX9-NEXT: s_cbranch_scc0 BB5_2 ; GFX9-NEXT: s_cbranch_scc0 .LBB5_2
; GFX9-NEXT: ; %bb.1: ; %.entry ; GFX9-NEXT: ; %bb.1: ; %.entry
; GFX9-NEXT: s_wqm_b64 s[14:15], s[12:13] ; GFX9-NEXT: s_wqm_b64 s[14:15], s[12:13]
; GFX9-NEXT: s_and_b64 exec, exec, s[14:15] ; GFX9-NEXT: s_and_b64 exec, exec, s[14:15]
; GFX9-NEXT: v_add_f32_e32 v0, v0, v0 ; GFX9-NEXT: v_add_f32_e32 v0, v0, v0
; GFX9-NEXT: s_and_b64 exec, exec, s[12:13] ; GFX9-NEXT: s_and_b64 exec, exec, s[12:13]
; GFX9-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf ; GFX9-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_branch BB5_3 ; GFX9-NEXT: s_branch .LBB5_3
; GFX9-NEXT: BB5_2: ; GFX9-NEXT: .LBB5_2:
; GFX9-NEXT: s_mov_b64 exec, 0 ; GFX9-NEXT: s_mov_b64 exec, 0
; GFX9-NEXT: exp null off, off, off, off done vm ; GFX9-NEXT: exp null off, off, off, off done vm
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; GFX9-NEXT: BB5_3: ; GFX9-NEXT: .LBB5_3:
; ;
; GFX10-32-LABEL: wqm_demote_dynamic: ; GFX10-32-LABEL: wqm_demote_dynamic:
; GFX10-32: ; %bb.0: ; %.entry ; GFX10-32: ; %bb.0: ; %.entry
; GFX10-32-NEXT: s_mov_b32 s12, exec_lo ; GFX10-32-NEXT: s_mov_b32 s12, exec_lo
; GFX10-32-NEXT: s_wqm_b32 exec_lo, exec_lo ; GFX10-32-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX10-32-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; GFX10-32-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10-32-NEXT: s_waitcnt vmcnt(0) ; GFX10-32-NEXT: s_waitcnt vmcnt(0)
; GFX10-32-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v0 ; GFX10-32-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v0
; GFX10-32-NEXT: s_xor_b32 s13, vcc_lo, exec_lo ; GFX10-32-NEXT: s_xor_b32 s13, vcc_lo, exec_lo
; GFX10-32-NEXT: s_andn2_b32 s12, s12, s13 ; GFX10-32-NEXT: s_andn2_b32 s12, s12, s13
; GFX10-32-NEXT: s_cbranch_scc0 BB5_2 ; GFX10-32-NEXT: s_cbranch_scc0 .LBB5_2
; GFX10-32-NEXT: ; %bb.1: ; %.entry ; GFX10-32-NEXT: ; %bb.1: ; %.entry
; GFX10-32-NEXT: s_wqm_b32 s13, s12 ; GFX10-32-NEXT: s_wqm_b32 s13, s12
; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s13 ; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s13
; GFX10-32-NEXT: v_add_f32_e32 v0, v0, v0 ; GFX10-32-NEXT: v_add_f32_e32 v0, v0, v0
; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s12
; GFX10-32-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; GFX10-32-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10-32-NEXT: s_waitcnt vmcnt(0) ; GFX10-32-NEXT: s_waitcnt vmcnt(0)
; GFX10-32-NEXT: s_branch BB5_3 ; GFX10-32-NEXT: s_branch .LBB5_3
; GFX10-32-NEXT: BB5_2: ; GFX10-32-NEXT: .LBB5_2:
; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-32-NEXT: exp null off, off, off, off done vm ; GFX10-32-NEXT: exp null off, off, off, off done vm
; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: s_endpgm
; GFX10-32-NEXT: BB5_3: ; GFX10-32-NEXT: .LBB5_3:
; ;
; GFX10-64-LABEL: wqm_demote_dynamic: ; GFX10-64-LABEL: wqm_demote_dynamic:
; GFX10-64: ; %bb.0: ; %.entry ; GFX10-64: ; %bb.0: ; %.entry
; GFX10-64-NEXT: s_mov_b64 s[12:13], exec ; GFX10-64-NEXT: s_mov_b64 s[12:13], exec
; GFX10-64-NEXT: s_wqm_b64 exec, exec ; GFX10-64-NEXT: s_wqm_b64 exec, exec
; GFX10-64-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; GFX10-64-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10-64-NEXT: s_waitcnt vmcnt(0) ; GFX10-64-NEXT: s_waitcnt vmcnt(0)
; GFX10-64-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0 ; GFX10-64-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0
; GFX10-64-NEXT: s_xor_b64 s[14:15], vcc, exec ; GFX10-64-NEXT: s_xor_b64 s[14:15], vcc, exec
; GFX10-64-NEXT: s_andn2_b64 s[12:13], s[12:13], s[14:15] ; GFX10-64-NEXT: s_andn2_b64 s[12:13], s[12:13], s[14:15]
; GFX10-64-NEXT: s_cbranch_scc0 BB5_2 ; GFX10-64-NEXT: s_cbranch_scc0 .LBB5_2
; GFX10-64-NEXT: ; %bb.1: ; %.entry ; GFX10-64-NEXT: ; %bb.1: ; %.entry
; GFX10-64-NEXT: s_wqm_b64 s[14:15], s[12:13] ; GFX10-64-NEXT: s_wqm_b64 s[14:15], s[12:13]
; GFX10-64-NEXT: s_and_b64 exec, exec, s[14:15] ; GFX10-64-NEXT: s_and_b64 exec, exec, s[14:15]
; GFX10-64-NEXT: v_add_f32_e32 v0, v0, v0 ; GFX10-64-NEXT: v_add_f32_e32 v0, v0, v0
; GFX10-64-NEXT: s_and_b64 exec, exec, s[12:13] ; GFX10-64-NEXT: s_and_b64 exec, exec, s[12:13]
; GFX10-64-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; GFX10-64-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10-64-NEXT: s_waitcnt vmcnt(0) ; GFX10-64-NEXT: s_waitcnt vmcnt(0)
; GFX10-64-NEXT: s_branch BB5_3 ; GFX10-64-NEXT: s_branch .LBB5_3
; GFX10-64-NEXT: BB5_2: ; GFX10-64-NEXT: .LBB5_2:
; GFX10-64-NEXT: s_mov_b64 exec, 0 ; GFX10-64-NEXT: s_mov_b64 exec, 0
; GFX10-64-NEXT: exp null off, off, off, off done vm ; GFX10-64-NEXT: exp null off, off, off, off done vm
; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: s_endpgm
; GFX10-64-NEXT: BB5_3: ; GFX10-64-NEXT: .LBB5_3:
.entry: .entry:
%tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %coord, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0 %tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %coord, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0
%tex0 = extractelement <4 x float> %tex, i32 0 %tex0 = extractelement <4 x float> %tex, i32 0
%tex1 = extractelement <4 x float> %tex, i32 0 %tex1 = extractelement <4 x float> %tex, i32 0
%z.cmp = fcmp olt float %tex0, 0.0 %z.cmp = fcmp olt float %tex0, 0.0
call void @llvm.amdgcn.wqm.demote(i1 %z.cmp) call void @llvm.amdgcn.wqm.demote(i1 %z.cmp)
%coord1 = fadd float %tex0, %tex1 %coord1 = fadd float %tex0, %tex1
%rtex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %coord1, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0 %rtex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %coord1, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0
Show All 12 Lines
; SI-NEXT: s_bfe_u32 s2, s2, 0x100000 ; SI-NEXT: s_bfe_u32 s2, s2, 0x100000
; SI-NEXT: s_lshl_b32 s4, s3, 16 ; SI-NEXT: s_lshl_b32 s4, s3, 16
; SI-NEXT: s_or_b32 s4, s2, s4 ; SI-NEXT: s_or_b32 s4, s2, s4
; SI-NEXT: s_lshl_b32 s2, s2, 16 ; SI-NEXT: s_lshl_b32 s2, s2, 16
; SI-NEXT: s_or_b32 s5, s3, s2 ; SI-NEXT: s_or_b32 s5, s3, s2
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: s_and_saveexec_b64 s[2:3], vcc ; SI-NEXT: s_and_saveexec_b64 s[2:3], vcc
; SI-NEXT: s_xor_b64 s[2:3], exec, s[2:3] ; SI-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; SI-NEXT: s_cbranch_execz BB6_3 ; SI-NEXT: s_cbranch_execz .LBB6_3
; SI-NEXT: ; %bb.1: ; %.demote0 ; SI-NEXT: ; %bb.1: ; %.demote0
; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; SI-NEXT: s_cbranch_scc0 BB6_7 ; SI-NEXT: s_cbranch_scc0 .LBB6_7
; SI-NEXT: ; %bb.2: ; %.demote0 ; SI-NEXT: ; %bb.2: ; %.demote0
; SI-NEXT: s_wqm_b64 s[6:7], s[0:1] ; SI-NEXT: s_wqm_b64 s[6:7], s[0:1]
; SI-NEXT: s_and_b64 exec, exec, s[6:7] ; SI-NEXT: s_and_b64 exec, exec, s[6:7]
; SI-NEXT: BB6_3: ; %.continue0 ; SI-NEXT: .LBB6_3: ; %.continue0
; SI-NEXT: s_or_b64 exec, exec, s[2:3] ; SI-NEXT: s_or_b64 exec, exec, s[2:3]
; SI-NEXT: s_mov_b64 s[2:3], s[0:1] ; SI-NEXT: s_mov_b64 s[2:3], s[0:1]
; SI-NEXT: v_cndmask_b32_e64 v0, 1.0, 0, s[2:3] ; SI-NEXT: v_cndmask_b32_e64 v0, 1.0, 0, s[2:3]
; SI-NEXT: v_mov_b32_e32 v1, v0 ; SI-NEXT: v_mov_b32_e32 v1, v0
; SI-NEXT: s_nop 1 ; SI-NEXT: s_nop 1
; SI-NEXT: v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; SI-NEXT: v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
; SI-NEXT: s_nop 1 ; SI-NEXT: s_nop 1
; SI-NEXT: v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; SI-NEXT: v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
; SI-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $exec ; SI-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $exec
; SI-NEXT: s_and_b64 exec, exec, s[0:1] ; SI-NEXT: s_and_b64 exec, exec, s[0:1]
; SI-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0 ; SI-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0
; SI-NEXT: s_and_b64 s[2:3], s[0:1], vcc ; SI-NEXT: s_and_b64 s[2:3], s[0:1], vcc
; SI-NEXT: s_xor_b64 s[2:3], s[2:3], -1 ; SI-NEXT: s_xor_b64 s[2:3], s[2:3], -1
; SI-NEXT: s_and_saveexec_b64 s[6:7], s[2:3] ; SI-NEXT: s_and_saveexec_b64 s[6:7], s[2:3]
; SI-NEXT: s_xor_b64 s[2:3], exec, s[6:7] ; SI-NEXT: s_xor_b64 s[2:3], exec, s[6:7]
; SI-NEXT: s_cbranch_execz BB6_6 ; SI-NEXT: s_cbranch_execz .LBB6_6
; SI-NEXT: ; %bb.4: ; %.demote1 ; SI-NEXT: ; %bb.4: ; %.demote1
; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; SI-NEXT: s_cbranch_scc0 BB6_7 ; SI-NEXT: s_cbranch_scc0 .LBB6_7
; SI-NEXT: ; %bb.5: ; %.demote1 ; SI-NEXT: ; %bb.5: ; %.demote1
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: BB6_6: ; %.continue1 ; SI-NEXT: .LBB6_6: ; %.continue1
; SI-NEXT: s_or_b64 exec, exec, s[2:3] ; SI-NEXT: s_or_b64 exec, exec, s[2:3]
; SI-NEXT: v_mov_b32_e32 v0, s4 ; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5 ; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm ; SI-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; SI-NEXT: BB6_7: ; SI-NEXT: .LBB6_7:
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: exp null off, off, off, off done vm ; SI-NEXT: exp null off, off, off, off done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; GFX9-LABEL: wqm_deriv: ; GFX9-LABEL: wqm_deriv:
; GFX9: ; %bb.0: ; %.entry ; GFX9: ; %bb.0: ; %.entry
; GFX9-NEXT: s_mov_b64 s[0:1], exec ; GFX9-NEXT: s_mov_b64 s[0:1], exec
; GFX9-NEXT: s_wqm_b64 exec, exec ; GFX9-NEXT: s_wqm_b64 exec, exec
; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-NEXT: s_xor_b64 s[2:3], exec, s[2:3] ; GFX9-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX9-NEXT: s_cbranch_execz BB6_3 ; GFX9-NEXT: s_cbranch_execz .LBB6_3
; GFX9-NEXT: ; %bb.1: ; %.demote0 ; GFX9-NEXT: ; %bb.1: ; %.demote0
; GFX9-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; GFX9-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; GFX9-NEXT: s_cbranch_scc0 BB6_7 ; GFX9-NEXT: s_cbranch_scc0 .LBB6_7
; GFX9-NEXT: ; %bb.2: ; %.demote0 ; GFX9-NEXT: ; %bb.2: ; %.demote0
; GFX9-NEXT: s_wqm_b64 s[4:5], s[0:1] ; GFX9-NEXT: s_wqm_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_and_b64 exec, exec, s[4:5] ; GFX9-NEXT: s_and_b64 exec, exec, s[4:5]
; GFX9-NEXT: BB6_3: ; %.continue0 ; GFX9-NEXT: .LBB6_3: ; %.continue0
; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX9-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX9-NEXT: s_mov_b64 s[2:3], s[0:1] ; GFX9-NEXT: s_mov_b64 s[2:3], s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v0, 1.0, 0, s[2:3] ; GFX9-NEXT: v_cndmask_b32_e64 v0, 1.0, 0, s[2:3]
; GFX9-NEXT: v_mov_b32_e32 v1, v0 ; GFX9-NEXT: v_mov_b32_e32 v1, v0
; GFX9-NEXT: s_nop 1 ; GFX9-NEXT: s_nop 1
; GFX9-NEXT: v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX9-NEXT: v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9-NEXT: s_nop 1 ; GFX9-NEXT: s_nop 1
; GFX9-NEXT: v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX9-NEXT: v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $exec ; GFX9-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $exec
; GFX9-NEXT: s_and_b64 exec, exec, s[0:1] ; GFX9-NEXT: s_and_b64 exec, exec, s[0:1]
; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0
; GFX9-NEXT: s_and_b64 s[2:3], s[0:1], vcc ; GFX9-NEXT: s_and_b64 s[2:3], s[0:1], vcc
; GFX9-NEXT: s_xor_b64 s[2:3], s[2:3], -1 ; GFX9-NEXT: s_xor_b64 s[2:3], s[2:3], -1
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], s[2:3] ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], s[2:3]
; GFX9-NEXT: s_xor_b64 s[2:3], exec, s[4:5] ; GFX9-NEXT: s_xor_b64 s[2:3], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz BB6_6 ; GFX9-NEXT: s_cbranch_execz .LBB6_6
; GFX9-NEXT: ; %bb.4: ; %.demote1 ; GFX9-NEXT: ; %bb.4: ; %.demote1
; GFX9-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; GFX9-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; GFX9-NEXT: s_cbranch_scc0 BB6_7 ; GFX9-NEXT: s_cbranch_scc0 .LBB6_7
; GFX9-NEXT: ; %bb.5: ; %.demote1 ; GFX9-NEXT: ; %bb.5: ; %.demote1
; GFX9-NEXT: s_mov_b64 exec, 0 ; GFX9-NEXT: s_mov_b64 exec, 0
; GFX9-NEXT: BB6_6: ; %.continue1 ; GFX9-NEXT: .LBB6_6: ; %.continue1
; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX9-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX9-NEXT: v_mov_b32_e32 v0, 0x3c00 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x3c00
; GFX9-NEXT: v_bfrev_b32_e32 v1, 60 ; GFX9-NEXT: v_bfrev_b32_e32 v1, 60
; GFX9-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm ; GFX9-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; GFX9-NEXT: BB6_7: ; GFX9-NEXT: .LBB6_7:
; GFX9-NEXT: s_mov_b64 exec, 0 ; GFX9-NEXT: s_mov_b64 exec, 0
; GFX9-NEXT: exp null off, off, off, off done vm ; GFX9-NEXT: exp null off, off, off, off done vm
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-32-LABEL: wqm_deriv: ; GFX10-32-LABEL: wqm_deriv:
; GFX10-32: ; %bb.0: ; %.entry ; GFX10-32: ; %bb.0: ; %.entry
; GFX10-32-NEXT: s_mov_b32 s0, exec_lo ; GFX10-32-NEXT: s_mov_b32 s0, exec_lo
; GFX10-32-NEXT: s_wqm_b32 exec_lo, exec_lo ; GFX10-32-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX10-32-NEXT: v_cvt_i32_f32_e32 v0, v0 ; GFX10-32-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX10-32-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 ; GFX10-32-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX10-32-NEXT: s_and_saveexec_b32 s1, vcc_lo ; GFX10-32-NEXT: s_and_saveexec_b32 s1, vcc_lo
; GFX10-32-NEXT: s_xor_b32 s1, exec_lo, s1 ; GFX10-32-NEXT: s_xor_b32 s1, exec_lo, s1
; GFX10-32-NEXT: s_cbranch_execz BB6_3 ; GFX10-32-NEXT: s_cbranch_execz .LBB6_3
; GFX10-32-NEXT: ; %bb.1: ; %.demote0 ; GFX10-32-NEXT: ; %bb.1: ; %.demote0
; GFX10-32-NEXT: s_andn2_b32 s0, s0, exec_lo ; GFX10-32-NEXT: s_andn2_b32 s0, s0, exec_lo
; GFX10-32-NEXT: s_cbranch_scc0 BB6_7 ; GFX10-32-NEXT: s_cbranch_scc0 .LBB6_7
; GFX10-32-NEXT: ; %bb.2: ; %.demote0 ; GFX10-32-NEXT: ; %bb.2: ; %.demote0
; GFX10-32-NEXT: s_wqm_b32 s2, s0 ; GFX10-32-NEXT: s_wqm_b32 s2, s0
; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s2 ; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s2
; GFX10-32-NEXT: BB6_3: ; %.continue0 ; GFX10-32-NEXT: .LBB6_3: ; %.continue0
; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s1 ; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX10-32-NEXT: s_mov_b32 s1, s0 ; GFX10-32-NEXT: s_mov_b32 s1, s0
; GFX10-32-NEXT: v_cndmask_b32_e64 v0, 1.0, 0, s1 ; GFX10-32-NEXT: v_cndmask_b32_e64 v0, 1.0, 0, s1
; GFX10-32-NEXT: v_mov_b32_e32 v1, v0 ; GFX10-32-NEXT: v_mov_b32_e32 v1, v0
; GFX10-32-NEXT: v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX10-32-NEXT: v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX10-32-NEXT: v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX10-32-NEXT: v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX10-32-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $exec ; GFX10-32-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $exec
; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s0 ; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s0
; GFX10-32-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0 ; GFX10-32-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0
; GFX10-32-NEXT: s_and_b32 s1, s0, vcc_lo ; GFX10-32-NEXT: s_and_b32 s1, s0, vcc_lo
; GFX10-32-NEXT: s_xor_b32 s1, s1, -1 ; GFX10-32-NEXT: s_xor_b32 s1, s1, -1
; GFX10-32-NEXT: s_and_saveexec_b32 s2, s1 ; GFX10-32-NEXT: s_and_saveexec_b32 s2, s1
; GFX10-32-NEXT: s_xor_b32 s1, exec_lo, s2 ; GFX10-32-NEXT: s_xor_b32 s1, exec_lo, s2
; GFX10-32-NEXT: s_cbranch_execz BB6_6 ; GFX10-32-NEXT: s_cbranch_execz .LBB6_6
; GFX10-32-NEXT: ; %bb.4: ; %.demote1 ; GFX10-32-NEXT: ; %bb.4: ; %.demote1
; GFX10-32-NEXT: s_andn2_b32 s0, s0, exec_lo ; GFX10-32-NEXT: s_andn2_b32 s0, s0, exec_lo
; GFX10-32-NEXT: s_cbranch_scc0 BB6_7 ; GFX10-32-NEXT: s_cbranch_scc0 .LBB6_7
; GFX10-32-NEXT: ; %bb.5: ; %.demote1 ; GFX10-32-NEXT: ; %bb.5: ; %.demote1
; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-32-NEXT: BB6_6: ; %.continue1 ; GFX10-32-NEXT: .LBB6_6: ; %.continue1
; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s1 ; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX10-32-NEXT: v_mov_b32_e32 v0, 0x3c00 ; GFX10-32-NEXT: v_mov_b32_e32 v0, 0x3c00
; GFX10-32-NEXT: v_bfrev_b32_e32 v1, 60 ; GFX10-32-NEXT: v_bfrev_b32_e32 v1, 60
; GFX10-32-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm ; GFX10-32-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm
; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: s_endpgm
; GFX10-32-NEXT: BB6_7: ; GFX10-32-NEXT: .LBB6_7:
; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-32-NEXT: exp null off, off, off, off done vm ; GFX10-32-NEXT: exp null off, off, off, off done vm
; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: s_endpgm
; ;
; GFX10-64-LABEL: wqm_deriv: ; GFX10-64-LABEL: wqm_deriv:
; GFX10-64: ; %bb.0: ; %.entry ; GFX10-64: ; %bb.0: ; %.entry
; GFX10-64-NEXT: s_mov_b64 s[0:1], exec ; GFX10-64-NEXT: s_mov_b64 s[0:1], exec
; GFX10-64-NEXT: s_wqm_b64 exec, exec ; GFX10-64-NEXT: s_wqm_b64 exec, exec
; GFX10-64-NEXT: v_cvt_i32_f32_e32 v0, v0 ; GFX10-64-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX10-64-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX10-64-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX10-64-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX10-64-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX10-64-NEXT: s_xor_b64 s[2:3], exec, s[2:3] ; GFX10-64-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX10-64-NEXT: s_cbranch_execz BB6_3 ; GFX10-64-NEXT: s_cbranch_execz .LBB6_3
; GFX10-64-NEXT: ; %bb.1: ; %.demote0 ; GFX10-64-NEXT: ; %bb.1: ; %.demote0
; GFX10-64-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; GFX10-64-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; GFX10-64-NEXT: s_cbranch_scc0 BB6_7 ; GFX10-64-NEXT: s_cbranch_scc0 .LBB6_7
; GFX10-64-NEXT: ; %bb.2: ; %.demote0 ; GFX10-64-NEXT: ; %bb.2: ; %.demote0
; GFX10-64-NEXT: s_wqm_b64 s[4:5], s[0:1] ; GFX10-64-NEXT: s_wqm_b64 s[4:5], s[0:1]
; GFX10-64-NEXT: s_and_b64 exec, exec, s[4:5] ; GFX10-64-NEXT: s_and_b64 exec, exec, s[4:5]
; GFX10-64-NEXT: BB6_3: ; %.continue0 ; GFX10-64-NEXT: .LBB6_3: ; %.continue0
; GFX10-64-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX10-64-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX10-64-NEXT: s_mov_b64 s[2:3], s[0:1] ; GFX10-64-NEXT: s_mov_b64 s[2:3], s[0:1]
; GFX10-64-NEXT: v_cndmask_b32_e64 v0, 1.0, 0, s[2:3] ; GFX10-64-NEXT: v_cndmask_b32_e64 v0, 1.0, 0, s[2:3]
; GFX10-64-NEXT: v_mov_b32_e32 v1, v0 ; GFX10-64-NEXT: v_mov_b32_e32 v1, v0
; GFX10-64-NEXT: v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX10-64-NEXT: v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX10-64-NEXT: v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX10-64-NEXT: v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX10-64-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $exec ; GFX10-64-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $exec
; GFX10-64-NEXT: s_and_b64 exec, exec, s[0:1] ; GFX10-64-NEXT: s_and_b64 exec, exec, s[0:1]
; GFX10-64-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0 ; GFX10-64-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0
; GFX10-64-NEXT: s_and_b64 s[2:3], s[0:1], vcc ; GFX10-64-NEXT: s_and_b64 s[2:3], s[0:1], vcc
; GFX10-64-NEXT: s_xor_b64 s[2:3], s[2:3], -1 ; GFX10-64-NEXT: s_xor_b64 s[2:3], s[2:3], -1
; GFX10-64-NEXT: s_and_saveexec_b64 s[4:5], s[2:3] ; GFX10-64-NEXT: s_and_saveexec_b64 s[4:5], s[2:3]
; GFX10-64-NEXT: s_xor_b64 s[2:3], exec, s[4:5] ; GFX10-64-NEXT: s_xor_b64 s[2:3], exec, s[4:5]
; GFX10-64-NEXT: s_cbranch_execz BB6_6 ; GFX10-64-NEXT: s_cbranch_execz .LBB6_6
; GFX10-64-NEXT: ; %bb.4: ; %.demote1 ; GFX10-64-NEXT: ; %bb.4: ; %.demote1
; GFX10-64-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; GFX10-64-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; GFX10-64-NEXT: s_cbranch_scc0 BB6_7 ; GFX10-64-NEXT: s_cbranch_scc0 .LBB6_7
; GFX10-64-NEXT: ; %bb.5: ; %.demote1 ; GFX10-64-NEXT: ; %bb.5: ; %.demote1
; GFX10-64-NEXT: s_mov_b64 exec, 0 ; GFX10-64-NEXT: s_mov_b64 exec, 0
; GFX10-64-NEXT: BB6_6: ; %.continue1 ; GFX10-64-NEXT: .LBB6_6: ; %.continue1
; GFX10-64-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX10-64-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX10-64-NEXT: v_mov_b32_e32 v0, 0x3c00 ; GFX10-64-NEXT: v_mov_b32_e32 v0, 0x3c00
; GFX10-64-NEXT: v_bfrev_b32_e32 v1, 60 ; GFX10-64-NEXT: v_bfrev_b32_e32 v1, 60
; GFX10-64-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm ; GFX10-64-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm
; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: s_endpgm
; GFX10-64-NEXT: BB6_7: ; GFX10-64-NEXT: .LBB6_7:
; GFX10-64-NEXT: s_mov_b64 exec, 0 ; GFX10-64-NEXT: s_mov_b64 exec, 0
; GFX10-64-NEXT: exp null off, off, off, off done vm ; GFX10-64-NEXT: exp null off, off, off, off done vm
; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: s_endpgm
.entry: .entry:
%p0 = extractelement <2 x float> %input, i32 0 %p0 = extractelement <2 x float> %input, i32 0
%p1 = extractelement <2 x float> %input, i32 1 %p1 = extractelement <2 x float> %input, i32 1
%x0 = call float @llvm.amdgcn.interp.p1(float %p0, i32 immarg 0, i32 immarg 0, i32 %index) #2 %x0 = call float @llvm.amdgcn.interp.p1(float %p0, i32 immarg 0, i32 immarg 0, i32 %index) #2
%x1 = call float @llvm.amdgcn.interp.p2(float %x0, float %p1, i32 immarg 0, i32 immarg 0, i32 %index) #2 %x1 = call float @llvm.amdgcn.interp.p2(float %x0, float %p1, i32 immarg 0, i32 immarg 0, i32 %index) #2
Show All 39 Lines
; SI-NEXT: s_lshl_b32 s4, s3, 16 ; SI-NEXT: s_lshl_b32 s4, s3, 16
; SI-NEXT: s_or_b32 s6, s2, s4 ; SI-NEXT: s_or_b32 s6, s2, s4
; SI-NEXT: s_lshl_b32 s2, s2, 16 ; SI-NEXT: s_lshl_b32 s2, s2, 16
; SI-NEXT: s_or_b32 s7, s3, s2 ; SI-NEXT: s_or_b32 s7, s3, s2
; SI-NEXT: s_mov_b32 s4, 0 ; SI-NEXT: s_mov_b32 s4, 0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: s_and_saveexec_b64 s[2:3], vcc ; SI-NEXT: s_and_saveexec_b64 s[2:3], vcc
; SI-NEXT: s_xor_b64 s[2:3], exec, s[2:3] ; SI-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; SI-NEXT: s_cbranch_execz BB7_3 ; SI-NEXT: s_cbranch_execz .LBB7_3
; SI-NEXT: ; %bb.1: ; %.demote0 ; SI-NEXT: ; %bb.1: ; %.demote0
; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; SI-NEXT: s_cbranch_scc0 BB7_9 ; SI-NEXT: s_cbranch_scc0 .LBB7_9
; SI-NEXT: ; %bb.2: ; %.demote0 ; SI-NEXT: ; %bb.2: ; %.demote0
; SI-NEXT: s_wqm_b64 s[8:9], s[0:1] ; SI-NEXT: s_wqm_b64 s[8:9], s[0:1]
; SI-NEXT: s_and_b64 exec, exec, s[8:9] ; SI-NEXT: s_and_b64 exec, exec, s[8:9]
; SI-NEXT: BB7_3: ; %.continue0.preheader ; SI-NEXT: .LBB7_3: ; %.continue0.preheader
; SI-NEXT: s_or_b64 exec, exec, s[2:3] ; SI-NEXT: s_or_b64 exec, exec, s[2:3]
; SI-NEXT: s_mov_b64 s[2:3], 0 ; SI-NEXT: s_mov_b64 s[2:3], 0
; SI-NEXT: v_mov_b32_e32 v0, s4 ; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: s_branch BB7_5 ; SI-NEXT: s_branch .LBB7_5
; SI-NEXT: BB7_4: ; %.continue1 ; SI-NEXT: .LBB7_4: ; %.continue1
; SI-NEXT: ; in Loop: Header=BB7_5 Depth=1 ; SI-NEXT: ; in Loop: Header=BB7_5 Depth=1
; SI-NEXT: s_or_b64 exec, exec, s[4:5] ; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: v_add_u32_e32 v0, vcc, 1, v0 ; SI-NEXT: v_add_u32_e32 v0, vcc, 1, v0
; SI-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1 ; SI-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1
; SI-NEXT: s_or_b64 s[2:3], vcc, s[2:3] ; SI-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; SI-NEXT: s_andn2_b64 exec, exec, s[2:3] ; SI-NEXT: s_andn2_b64 exec, exec, s[2:3]
; SI-NEXT: s_cbranch_execz BB7_8 ; SI-NEXT: s_cbranch_execz .LBB7_8
; SI-NEXT: BB7_5: ; %.continue0 ; SI-NEXT: .LBB7_5: ; %.continue0
; SI-NEXT: ; =>This Inner Loop Header: Depth=1 ; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_mov_b64 s[4:5], s[0:1] ; SI-NEXT: s_mov_b64 s[4:5], s[0:1]
; SI-NEXT: v_cndmask_b32_e64 v2, v0, 0, s[4:5] ; SI-NEXT: v_cndmask_b32_e64 v2, v0, 0, s[4:5]
; SI-NEXT: v_mov_b32_e32 v3, v2 ; SI-NEXT: v_mov_b32_e32 v3, v2
; SI-NEXT: s_nop 1 ; SI-NEXT: s_nop 1
; SI-NEXT: v_mov_b32_dpp v3, v3 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; SI-NEXT: v_mov_b32_dpp v3, v3 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
; SI-NEXT: s_nop 1 ; SI-NEXT: s_nop 1
; SI-NEXT: v_subrev_f32_dpp v2, v2, v3 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; SI-NEXT: v_subrev_f32_dpp v2, v2, v3 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
; SI-NEXT: ; kill: def $vgpr2 killed $vgpr2 killed $exec ; SI-NEXT: ; kill: def $vgpr2 killed $vgpr2 killed $exec
; SI-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 ; SI-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2
; SI-NEXT: s_and_b64 s[4:5], s[0:1], vcc ; SI-NEXT: s_and_b64 s[4:5], s[0:1], vcc
; SI-NEXT: s_xor_b64 s[4:5], s[4:5], -1 ; SI-NEXT: s_xor_b64 s[4:5], s[4:5], -1
; SI-NEXT: s_and_saveexec_b64 s[8:9], s[4:5] ; SI-NEXT: s_and_saveexec_b64 s[8:9], s[4:5]
; SI-NEXT: s_xor_b64 s[4:5], exec, s[8:9] ; SI-NEXT: s_xor_b64 s[4:5], exec, s[8:9]
; SI-NEXT: s_cbranch_execz BB7_4 ; SI-NEXT: s_cbranch_execz .LBB7_4
; SI-NEXT: ; %bb.6: ; %.demote1 ; SI-NEXT: ; %bb.6: ; %.demote1
; SI-NEXT: ; in Loop: Header=BB7_5 Depth=1 ; SI-NEXT: ; in Loop: Header=BB7_5 Depth=1
; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; SI-NEXT: s_cbranch_scc0 BB7_9 ; SI-NEXT: s_cbranch_scc0 .LBB7_9
; SI-NEXT: ; %bb.7: ; %.demote1 ; SI-NEXT: ; %bb.7: ; %.demote1
; SI-NEXT: ; in Loop: Header=BB7_5 Depth=1 ; SI-NEXT: ; in Loop: Header=BB7_5 Depth=1
; SI-NEXT: s_wqm_b64 s[8:9], s[0:1] ; SI-NEXT: s_wqm_b64 s[8:9], s[0:1]
; SI-NEXT: s_and_b64 exec, exec, s[8:9] ; SI-NEXT: s_and_b64 exec, exec, s[8:9]
; SI-NEXT: s_branch BB7_4 ; SI-NEXT: s_branch .LBB7_4
; SI-NEXT: BB7_8: ; %.return ; SI-NEXT: .LBB7_8: ; %.return
; SI-NEXT: s_or_b64 exec, exec, s[2:3] ; SI-NEXT: s_or_b64 exec, exec, s[2:3]
; SI-NEXT: s_and_b64 exec, exec, s[0:1] ; SI-NEXT: s_and_b64 exec, exec, s[0:1]
; SI-NEXT: v_mov_b32_e32 v0, s6 ; SI-NEXT: v_mov_b32_e32 v0, s6
; SI-NEXT: v_mov_b32_e32 v1, s7 ; SI-NEXT: v_mov_b32_e32 v1, s7
; SI-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm ; SI-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; SI-NEXT: BB7_9: ; SI-NEXT: .LBB7_9:
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: exp null off, off, off, off done vm ; SI-NEXT: exp null off, off, off, off done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; GFX9-LABEL: wqm_deriv_loop: ; GFX9-LABEL: wqm_deriv_loop:
; GFX9: ; %bb.0: ; %.entry ; GFX9: ; %bb.0: ; %.entry
; GFX9-NEXT: s_mov_b64 s[0:1], exec ; GFX9-NEXT: s_mov_b64 s[0:1], exec
; GFX9-NEXT: s_wqm_b64 exec, exec ; GFX9-NEXT: s_wqm_b64 exec, exec
; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX9-NEXT: s_mov_b32 s4, 0 ; GFX9-NEXT: s_mov_b32 s4, 0
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-NEXT: s_xor_b64 s[2:3], exec, s[2:3] ; GFX9-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX9-NEXT: s_cbranch_execz BB7_3 ; GFX9-NEXT: s_cbranch_execz .LBB7_3
; GFX9-NEXT: ; %bb.1: ; %.demote0 ; GFX9-NEXT: ; %bb.1: ; %.demote0
; GFX9-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; GFX9-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; GFX9-NEXT: s_cbranch_scc0 BB7_9 ; GFX9-NEXT: s_cbranch_scc0 .LBB7_9
; GFX9-NEXT: ; %bb.2: ; %.demote0 ; GFX9-NEXT: ; %bb.2: ; %.demote0
; GFX9-NEXT: s_wqm_b64 s[6:7], s[0:1] ; GFX9-NEXT: s_wqm_b64 s[6:7], s[0:1]
; GFX9-NEXT: s_and_b64 exec, exec, s[6:7] ; GFX9-NEXT: s_and_b64 exec, exec, s[6:7]
; GFX9-NEXT: BB7_3: ; %.continue0.preheader ; GFX9-NEXT: .LBB7_3: ; %.continue0.preheader
; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX9-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX9-NEXT: s_mov_b64 s[2:3], 0 ; GFX9-NEXT: s_mov_b64 s[2:3], 0
; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: s_branch BB7_5 ; GFX9-NEXT: s_branch .LBB7_5
; GFX9-NEXT: BB7_4: ; %.continue1 ; GFX9-NEXT: .LBB7_4: ; %.continue1
; GFX9-NEXT: ; in Loop: Header=BB7_5 Depth=1 ; GFX9-NEXT: ; in Loop: Header=BB7_5 Depth=1
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: v_add_u32_e32 v0, 1, v0 ; GFX9-NEXT: v_add_u32_e32 v0, 1, v0
; GFX9-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1 ; GFX9-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1
; GFX9-NEXT: s_or_b64 s[2:3], vcc, s[2:3] ; GFX9-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX9-NEXT: s_andn2_b64 exec, exec, s[2:3] ; GFX9-NEXT: s_andn2_b64 exec, exec, s[2:3]
; GFX9-NEXT: s_cbranch_execz BB7_8 ; GFX9-NEXT: s_cbranch_execz .LBB7_8
; GFX9-NEXT: BB7_5: ; %.continue0 ; GFX9-NEXT: .LBB7_5: ; %.continue0
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1] ; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v2, v0, 0, s[4:5] ; GFX9-NEXT: v_cndmask_b32_e64 v2, v0, 0, s[4:5]
; GFX9-NEXT: v_mov_b32_e32 v3, v2 ; GFX9-NEXT: v_mov_b32_e32 v3, v2
; GFX9-NEXT: s_nop 1 ; GFX9-NEXT: s_nop 1
; GFX9-NEXT: v_mov_b32_dpp v3, v3 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX9-NEXT: v_mov_b32_dpp v3, v3 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9-NEXT: s_nop 1 ; GFX9-NEXT: s_nop 1
; GFX9-NEXT: v_subrev_f32_dpp v2, v2, v3 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX9-NEXT: v_subrev_f32_dpp v2, v2, v3 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9-NEXT: ; kill: def $vgpr2 killed $vgpr2 killed $exec ; GFX9-NEXT: ; kill: def $vgpr2 killed $vgpr2 killed $exec
; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 ; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2
; GFX9-NEXT: s_and_b64 s[4:5], s[0:1], vcc ; GFX9-NEXT: s_and_b64 s[4:5], s[0:1], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], -1 ; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], -1
; GFX9-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GFX9-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[6:7] ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[6:7]
; GFX9-NEXT: s_cbranch_execz BB7_4 ; GFX9-NEXT: s_cbranch_execz .LBB7_4
; GFX9-NEXT: ; %bb.6: ; %.demote1 ; GFX9-NEXT: ; %bb.6: ; %.demote1
; GFX9-NEXT: ; in Loop: Header=BB7_5 Depth=1 ; GFX9-NEXT: ; in Loop: Header=BB7_5 Depth=1
; GFX9-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; GFX9-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; GFX9-NEXT: s_cbranch_scc0 BB7_9 ; GFX9-NEXT: s_cbranch_scc0 .LBB7_9
; GFX9-NEXT: ; %bb.7: ; %.demote1 ; GFX9-NEXT: ; %bb.7: ; %.demote1
; GFX9-NEXT: ; in Loop: Header=BB7_5 Depth=1 ; GFX9-NEXT: ; in Loop: Header=BB7_5 Depth=1
; GFX9-NEXT: s_wqm_b64 s[6:7], s[0:1] ; GFX9-NEXT: s_wqm_b64 s[6:7], s[0:1]
; GFX9-NEXT: s_and_b64 exec, exec, s[6:7] ; GFX9-NEXT: s_and_b64 exec, exec, s[6:7]
; GFX9-NEXT: s_branch BB7_4 ; GFX9-NEXT: s_branch .LBB7_4
; GFX9-NEXT: BB7_8: ; %.return ; GFX9-NEXT: .LBB7_8: ; %.return
; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX9-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX9-NEXT: s_and_b64 exec, exec, s[0:1] ; GFX9-NEXT: s_and_b64 exec, exec, s[0:1]
; GFX9-NEXT: v_mov_b32_e32 v0, 0x3c00 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x3c00
; GFX9-NEXT: v_bfrev_b32_e32 v1, 60 ; GFX9-NEXT: v_bfrev_b32_e32 v1, 60
; GFX9-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm ; GFX9-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; GFX9-NEXT: BB7_9: ; GFX9-NEXT: .LBB7_9:
; GFX9-NEXT: s_mov_b64 exec, 0 ; GFX9-NEXT: s_mov_b64 exec, 0
; GFX9-NEXT: exp null off, off, off, off done vm ; GFX9-NEXT: exp null off, off, off, off done vm
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-32-LABEL: wqm_deriv_loop: ; GFX10-32-LABEL: wqm_deriv_loop:
; GFX10-32: ; %bb.0: ; %.entry ; GFX10-32: ; %bb.0: ; %.entry
; GFX10-32-NEXT: s_mov_b32 s0, exec_lo ; GFX10-32-NEXT: s_mov_b32 s0, exec_lo
; GFX10-32-NEXT: s_wqm_b32 exec_lo, exec_lo ; GFX10-32-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX10-32-NEXT: v_cvt_i32_f32_e32 v0, v0 ; GFX10-32-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX10-32-NEXT: s_mov_b32 s1, 0 ; GFX10-32-NEXT: s_mov_b32 s1, 0
; GFX10-32-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 ; GFX10-32-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX10-32-NEXT: s_and_saveexec_b32 s2, vcc_lo ; GFX10-32-NEXT: s_and_saveexec_b32 s2, vcc_lo
; GFX10-32-NEXT: s_xor_b32 s2, exec_lo, s2 ; GFX10-32-NEXT: s_xor_b32 s2, exec_lo, s2
; GFX10-32-NEXT: s_cbranch_execz BB7_3 ; GFX10-32-NEXT: s_cbranch_execz .LBB7_3
; GFX10-32-NEXT: ; %bb.1: ; %.demote0 ; GFX10-32-NEXT: ; %bb.1: ; %.demote0
; GFX10-32-NEXT: s_andn2_b32 s0, s0, exec_lo ; GFX10-32-NEXT: s_andn2_b32 s0, s0, exec_lo
; GFX10-32-NEXT: s_cbranch_scc0 BB7_9 ; GFX10-32-NEXT: s_cbranch_scc0 .LBB7_9
; GFX10-32-NEXT: ; %bb.2: ; %.demote0 ; GFX10-32-NEXT: ; %bb.2: ; %.demote0
; GFX10-32-NEXT: s_wqm_b32 s3, s0 ; GFX10-32-NEXT: s_wqm_b32 s3, s0
; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s3 ; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s3
; GFX10-32-NEXT: BB7_3: ; %.continue0.preheader ; GFX10-32-NEXT: .LBB7_3: ; %.continue0.preheader
; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s2 ; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX10-32-NEXT: v_mov_b32_e32 v0, s1 ; GFX10-32-NEXT: v_mov_b32_e32 v0, s1
; GFX10-32-NEXT: s_branch BB7_5 ; GFX10-32-NEXT: s_branch .LBB7_5
; GFX10-32-NEXT: BB7_4: ; %.continue1 ; GFX10-32-NEXT: .LBB7_4: ; %.continue1
; GFX10-32-NEXT: ; in Loop: Header=BB7_5 Depth=1 ; GFX10-32-NEXT: ; in Loop: Header=BB7_5 Depth=1
; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s2 ; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX10-32-NEXT: v_add_nc_u32_e32 v0, 1, v0 ; GFX10-32-NEXT: v_add_nc_u32_e32 v0, 1, v0
; GFX10-32-NEXT: v_cmp_ge_i32_e32 vcc_lo, v0, v1 ; GFX10-32-NEXT: v_cmp_ge_i32_e32 vcc_lo, v0, v1
; GFX10-32-NEXT: s_or_b32 s1, vcc_lo, s1 ; GFX10-32-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX10-32-NEXT: s_andn2_b32 exec_lo, exec_lo, s1 ; GFX10-32-NEXT: s_andn2_b32 exec_lo, exec_lo, s1
; GFX10-32-NEXT: s_cbranch_execz BB7_8 ; GFX10-32-NEXT: s_cbranch_execz .LBB7_8
; GFX10-32-NEXT: BB7_5: ; %.continue0 ; GFX10-32-NEXT: .LBB7_5: ; %.continue0
; GFX10-32-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-32-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-32-NEXT: s_mov_b32 s2, s0 ; GFX10-32-NEXT: s_mov_b32 s2, s0
; GFX10-32-NEXT: v_cndmask_b32_e64 v2, v0, 0, s2 ; GFX10-32-NEXT: v_cndmask_b32_e64 v2, v0, 0, s2
; GFX10-32-NEXT: v_mov_b32_e32 v3, v2 ; GFX10-32-NEXT: v_mov_b32_e32 v3, v2
; GFX10-32-NEXT: v_mov_b32_dpp v3, v3 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX10-32-NEXT: v_mov_b32_dpp v3, v3 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX10-32-NEXT: v_subrev_f32_dpp v2, v2, v3 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX10-32-NEXT: v_subrev_f32_dpp v2, v2, v3 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX10-32-NEXT: ; kill: def $vgpr2 killed $vgpr2 killed $exec ; GFX10-32-NEXT: ; kill: def $vgpr2 killed $vgpr2 killed $exec
; GFX10-32-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 ; GFX10-32-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2
; GFX10-32-NEXT: s_and_b32 s2, s0, vcc_lo ; GFX10-32-NEXT: s_and_b32 s2, s0, vcc_lo
; GFX10-32-NEXT: s_xor_b32 s2, s2, -1 ; GFX10-32-NEXT: s_xor_b32 s2, s2, -1
; GFX10-32-NEXT: s_and_saveexec_b32 s3, s2 ; GFX10-32-NEXT: s_and_saveexec_b32 s3, s2
; GFX10-32-NEXT: s_xor_b32 s2, exec_lo, s3 ; GFX10-32-NEXT: s_xor_b32 s2, exec_lo, s3
; GFX10-32-NEXT: s_cbranch_execz BB7_4 ; GFX10-32-NEXT: s_cbranch_execz .LBB7_4
; GFX10-32-NEXT: ; %bb.6: ; %.demote1 ; GFX10-32-NEXT: ; %bb.6: ; %.demote1
; GFX10-32-NEXT: ; in Loop: Header=BB7_5 Depth=1 ; GFX10-32-NEXT: ; in Loop: Header=BB7_5 Depth=1
; GFX10-32-NEXT: s_andn2_b32 s0, s0, exec_lo ; GFX10-32-NEXT: s_andn2_b32 s0, s0, exec_lo
; GFX10-32-NEXT: s_cbranch_scc0 BB7_9 ; GFX10-32-NEXT: s_cbranch_scc0 .LBB7_9
; GFX10-32-NEXT: ; %bb.7: ; %.demote1 ; GFX10-32-NEXT: ; %bb.7: ; %.demote1
; GFX10-32-NEXT: ; in Loop: Header=BB7_5 Depth=1 ; GFX10-32-NEXT: ; in Loop: Header=BB7_5 Depth=1
; GFX10-32-NEXT: s_wqm_b32 s3, s0 ; GFX10-32-NEXT: s_wqm_b32 s3, s0
; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s3 ; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s3
; GFX10-32-NEXT: s_branch BB7_4 ; GFX10-32-NEXT: s_branch .LBB7_4
; GFX10-32-NEXT: BB7_8: ; %.return ; GFX10-32-NEXT: .LBB7_8: ; %.return
; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s1 ; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s0 ; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s0
; GFX10-32-NEXT: v_mov_b32_e32 v0, 0x3c00 ; GFX10-32-NEXT: v_mov_b32_e32 v0, 0x3c00
; GFX10-32-NEXT: v_bfrev_b32_e32 v1, 60 ; GFX10-32-NEXT: v_bfrev_b32_e32 v1, 60
; GFX10-32-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm ; GFX10-32-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm
; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: s_endpgm
; GFX10-32-NEXT: BB7_9: ; GFX10-32-NEXT: .LBB7_9:
; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-32-NEXT: exp null off, off, off, off done vm ; GFX10-32-NEXT: exp null off, off, off, off done vm
; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: s_endpgm
; ;
; GFX10-64-LABEL: wqm_deriv_loop: ; GFX10-64-LABEL: wqm_deriv_loop:
; GFX10-64: ; %bb.0: ; %.entry ; GFX10-64: ; %bb.0: ; %.entry
; GFX10-64-NEXT: s_mov_b64 s[0:1], exec ; GFX10-64-NEXT: s_mov_b64 s[0:1], exec
; GFX10-64-NEXT: s_wqm_b64 exec, exec ; GFX10-64-NEXT: s_wqm_b64 exec, exec
; GFX10-64-NEXT: v_cvt_i32_f32_e32 v0, v0 ; GFX10-64-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX10-64-NEXT: s_mov_b32 s4, 0 ; GFX10-64-NEXT: s_mov_b32 s4, 0
; GFX10-64-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX10-64-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX10-64-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX10-64-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX10-64-NEXT: s_xor_b64 s[2:3], exec, s[2:3] ; GFX10-64-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX10-64-NEXT: s_cbranch_execz BB7_3 ; GFX10-64-NEXT: s_cbranch_execz .LBB7_3
; GFX10-64-NEXT: ; %bb.1: ; %.demote0 ; GFX10-64-NEXT: ; %bb.1: ; %.demote0
; GFX10-64-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; GFX10-64-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; GFX10-64-NEXT: s_cbranch_scc0 BB7_9 ; GFX10-64-NEXT: s_cbranch_scc0 .LBB7_9
; GFX10-64-NEXT: ; %bb.2: ; %.demote0 ; GFX10-64-NEXT: ; %bb.2: ; %.demote0
; GFX10-64-NEXT: s_wqm_b64 s[6:7], s[0:1] ; GFX10-64-NEXT: s_wqm_b64 s[6:7], s[0:1]
; GFX10-64-NEXT: s_and_b64 exec, exec, s[6:7] ; GFX10-64-NEXT: s_and_b64 exec, exec, s[6:7]
; GFX10-64-NEXT: BB7_3: ; %.continue0.preheader ; GFX10-64-NEXT: .LBB7_3: ; %.continue0.preheader
; GFX10-64-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX10-64-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX10-64-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-64-NEXT: v_mov_b32_e32 v0, s4
; GFX10-64-NEXT: s_mov_b64 s[2:3], 0 ; GFX10-64-NEXT: s_mov_b64 s[2:3], 0
; GFX10-64-NEXT: s_branch BB7_5 ; GFX10-64-NEXT: s_branch .LBB7_5
; GFX10-64-NEXT: BB7_4: ; %.continue1 ; GFX10-64-NEXT: .LBB7_4: ; %.continue1
; GFX10-64-NEXT: ; in Loop: Header=BB7_5 Depth=1 ; GFX10-64-NEXT: ; in Loop: Header=BB7_5 Depth=1
; GFX10-64-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX10-64-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX10-64-NEXT: v_add_nc_u32_e32 v0, 1, v0 ; GFX10-64-NEXT: v_add_nc_u32_e32 v0, 1, v0
; GFX10-64-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1 ; GFX10-64-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1
; GFX10-64-NEXT: s_or_b64 s[2:3], vcc, s[2:3] ; GFX10-64-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX10-64-NEXT: s_andn2_b64 exec, exec, s[2:3] ; GFX10-64-NEXT: s_andn2_b64 exec, exec, s[2:3]
; GFX10-64-NEXT: s_cbranch_execz BB7_8 ; GFX10-64-NEXT: s_cbranch_execz .LBB7_8
; GFX10-64-NEXT: BB7_5: ; %.continue0 ; GFX10-64-NEXT: .LBB7_5: ; %.continue0
; GFX10-64-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-64-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-64-NEXT: s_mov_b64 s[4:5], s[0:1] ; GFX10-64-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX10-64-NEXT: v_cndmask_b32_e64 v2, v0, 0, s[4:5] ; GFX10-64-NEXT: v_cndmask_b32_e64 v2, v0, 0, s[4:5]
; GFX10-64-NEXT: v_mov_b32_e32 v3, v2 ; GFX10-64-NEXT: v_mov_b32_e32 v3, v2
; GFX10-64-NEXT: v_mov_b32_dpp v3, v3 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX10-64-NEXT: v_mov_b32_dpp v3, v3 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX10-64-NEXT: v_subrev_f32_dpp v2, v2, v3 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX10-64-NEXT: v_subrev_f32_dpp v2, v2, v3 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX10-64-NEXT: ; kill: def $vgpr2 killed $vgpr2 killed $exec ; GFX10-64-NEXT: ; kill: def $vgpr2 killed $vgpr2 killed $exec
; GFX10-64-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 ; GFX10-64-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2
; GFX10-64-NEXT: s_and_b64 s[4:5], s[0:1], vcc ; GFX10-64-NEXT: s_and_b64 s[4:5], s[0:1], vcc
; GFX10-64-NEXT: s_xor_b64 s[4:5], s[4:5], -1 ; GFX10-64-NEXT: s_xor_b64 s[4:5], s[4:5], -1
; GFX10-64-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GFX10-64-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GFX10-64-NEXT: s_xor_b64 s[4:5], exec, s[6:7] ; GFX10-64-NEXT: s_xor_b64 s[4:5], exec, s[6:7]
; GFX10-64-NEXT: s_cbranch_execz BB7_4 ; GFX10-64-NEXT: s_cbranch_execz .LBB7_4
; GFX10-64-NEXT: ; %bb.6: ; %.demote1 ; GFX10-64-NEXT: ; %bb.6: ; %.demote1
; GFX10-64-NEXT: ; in Loop: Header=BB7_5 Depth=1 ; GFX10-64-NEXT: ; in Loop: Header=BB7_5 Depth=1
; GFX10-64-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; GFX10-64-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; GFX10-64-NEXT: s_cbranch_scc0 BB7_9 ; GFX10-64-NEXT: s_cbranch_scc0 .LBB7_9
; GFX10-64-NEXT: ; %bb.7: ; %.demote1 ; GFX10-64-NEXT: ; %bb.7: ; %.demote1
; GFX10-64-NEXT: ; in Loop: Header=BB7_5 Depth=1 ; GFX10-64-NEXT: ; in Loop: Header=BB7_5 Depth=1
; GFX10-64-NEXT: s_wqm_b64 s[6:7], s[0:1] ; GFX10-64-NEXT: s_wqm_b64 s[6:7], s[0:1]
; GFX10-64-NEXT: s_and_b64 exec, exec, s[6:7] ; GFX10-64-NEXT: s_and_b64 exec, exec, s[6:7]
; GFX10-64-NEXT: s_branch BB7_4 ; GFX10-64-NEXT: s_branch .LBB7_4
; GFX10-64-NEXT: BB7_8: ; %.return ; GFX10-64-NEXT: .LBB7_8: ; %.return
; GFX10-64-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX10-64-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX10-64-NEXT: s_and_b64 exec, exec, s[0:1] ; GFX10-64-NEXT: s_and_b64 exec, exec, s[0:1]
; GFX10-64-NEXT: v_mov_b32_e32 v0, 0x3c00 ; GFX10-64-NEXT: v_mov_b32_e32 v0, 0x3c00
; GFX10-64-NEXT: v_bfrev_b32_e32 v1, 60 ; GFX10-64-NEXT: v_bfrev_b32_e32 v1, 60
; GFX10-64-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm ; GFX10-64-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm
; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: s_endpgm
; GFX10-64-NEXT: BB7_9: ; GFX10-64-NEXT: .LBB7_9:
; GFX10-64-NEXT: s_mov_b64 exec, 0 ; GFX10-64-NEXT: s_mov_b64 exec, 0
; GFX10-64-NEXT: exp null off, off, off, off done vm ; GFX10-64-NEXT: exp null off, off, off, off done vm
; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: s_endpgm
.entry: .entry:
%p0 = extractelement <2 x float> %input, i32 0 %p0 = extractelement <2 x float> %input, i32 0
%p1 = extractelement <2 x float> %input, i32 1 %p1 = extractelement <2 x float> %input, i32 1
%x0 = call float @llvm.amdgcn.interp.p1(float %p0, i32 immarg 0, i32 immarg 0, i32 %index) #2 %x0 = call float @llvm.amdgcn.interp.p1(float %p0, i32 immarg 0, i32 immarg 0, i32 %index) #2
%x1 = call float @llvm.amdgcn.interp.p2(float %x0, float %p1, i32 immarg 0, i32 immarg 0, i32 %index) #2 %x1 = call float @llvm.amdgcn.interp.p2(float %x0, float %p1, i32 immarg 0, i32 immarg 0, i32 %index) #2
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llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.ll

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; LOOP-NEXT: s_mov_b32 s6, 0 ; LOOP-NEXT: s_mov_b32 s6, 0
; LOOP-NEXT: s_mov_b32 s7, 0xf000 ; LOOP-NEXT: s_mov_b32 s7, 0xf000
; LOOP-NEXT: s_mov_b64 s[4:5], 0 ; LOOP-NEXT: s_mov_b64 s[4:5], 0
; LOOP-NEXT: v_mov_b32_e32 v5, v3 ; LOOP-NEXT: v_mov_b32_e32 v5, v3
; LOOP-NEXT: v_mov_b32_e32 v4, v2 ; LOOP-NEXT: v_mov_b32_e32 v4, v2
; LOOP-NEXT: v_mov_b32_e32 v7, v1 ; LOOP-NEXT: v_mov_b32_e32 v7, v1
; LOOP-NEXT: v_mov_b32_e32 v6, v0 ; LOOP-NEXT: v_mov_b32_e32 v6, v0
; LOOP-NEXT: v_mov_b32_e32 v8, s6 ; LOOP-NEXT: v_mov_b32_e32 v8, s6
; LOOP-NEXT: BB0_1: ; %load-store-loop ; LOOP-NEXT: .LBB0_1: ; %load-store-loop
; LOOP-NEXT: ; =>This Inner Loop Header: Depth=1 ; LOOP-NEXT: ; =>This Inner Loop Header: Depth=1
; LOOP-NEXT: buffer_load_ubyte v9, v[4:5], s[4:7], 0 addr64 ; LOOP-NEXT: buffer_load_ubyte v9, v[4:5], s[4:7], 0 addr64
; LOOP-NEXT: buffer_load_ubyte v10, v[4:5], s[4:7], 0 addr64 offset:1 ; LOOP-NEXT: buffer_load_ubyte v10, v[4:5], s[4:7], 0 addr64 offset:1
; LOOP-NEXT: buffer_load_ubyte v11, v[4:5], s[4:7], 0 addr64 offset:2 ; LOOP-NEXT: buffer_load_ubyte v11, v[4:5], s[4:7], 0 addr64 offset:2
; LOOP-NEXT: buffer_load_ubyte v12, v[4:5], s[4:7], 0 addr64 offset:3 ; LOOP-NEXT: buffer_load_ubyte v12, v[4:5], s[4:7], 0 addr64 offset:3
; LOOP-NEXT: buffer_load_ubyte v13, v[4:5], s[4:7], 0 addr64 offset:4 ; LOOP-NEXT: buffer_load_ubyte v13, v[4:5], s[4:7], 0 addr64 offset:4
; LOOP-NEXT: buffer_load_ubyte v14, v[4:5], s[4:7], 0 addr64 offset:5 ; LOOP-NEXT: buffer_load_ubyte v14, v[4:5], s[4:7], 0 addr64 offset:5
; LOOP-NEXT: buffer_load_ubyte v15, v[4:5], s[4:7], 0 addr64 offset:6 ; LOOP-NEXT: buffer_load_ubyte v15, v[4:5], s[4:7], 0 addr64 offset:6
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; LOOP-NEXT: buffer_store_byte v22, v[6:7], s[4:7], 0 addr64 offset:13 ; LOOP-NEXT: buffer_store_byte v22, v[6:7], s[4:7], 0 addr64 offset:13
; LOOP-NEXT: s_waitcnt vmcnt(14) ; LOOP-NEXT: s_waitcnt vmcnt(14)
; LOOP-NEXT: buffer_store_byte v23, v[6:7], s[4:7], 0 addr64 offset:14 ; LOOP-NEXT: buffer_store_byte v23, v[6:7], s[4:7], 0 addr64 offset:14
; LOOP-NEXT: buffer_store_byte v24, v[6:7], s[4:7], 0 addr64 offset:15 ; LOOP-NEXT: buffer_store_byte v24, v[6:7], s[4:7], 0 addr64 offset:15
; LOOP-NEXT: v_add_i32_e64 v6, s[0:1], 16, v6 ; LOOP-NEXT: v_add_i32_e64 v6, s[0:1], 16, v6
; LOOP-NEXT: v_addc_u32_e64 v7, s[0:1], 0, v7, s[0:1] ; LOOP-NEXT: v_addc_u32_e64 v7, s[0:1], 0, v7, s[0:1]
; LOOP-NEXT: v_add_i32_e64 v4, s[0:1], 16, v4 ; LOOP-NEXT: v_add_i32_e64 v4, s[0:1], 16, v4
; LOOP-NEXT: v_addc_u32_e64 v5, s[0:1], 0, v5, s[0:1] ; LOOP-NEXT: v_addc_u32_e64 v5, s[0:1], 0, v5, s[0:1]
; LOOP-NEXT: s_cbranch_vccnz BB0_1 ; LOOP-NEXT: s_cbranch_vccnz .LBB0_1
; LOOP-NEXT: ; %bb.2: ; %memcpy-split ; LOOP-NEXT: ; %bb.2: ; %memcpy-split
; LOOP-NEXT: s_mov_b32 s2, 0 ; LOOP-NEXT: s_mov_b32 s2, 0
; LOOP-NEXT: s_mov_b32 s3, 0xf000 ; LOOP-NEXT: s_mov_b32 s3, 0xf000
; LOOP-NEXT: s_mov_b64 s[0:1], 0 ; LOOP-NEXT: s_mov_b64 s[0:1], 0
; LOOP-NEXT: buffer_load_ubyte v4, v[2:3], s[0:3], 0 addr64 offset:16 ; LOOP-NEXT: buffer_load_ubyte v4, v[2:3], s[0:3], 0 addr64 offset:16
; LOOP-NEXT: buffer_load_ubyte v5, v[2:3], s[0:3], 0 addr64 offset:17 ; LOOP-NEXT: buffer_load_ubyte v5, v[2:3], s[0:3], 0 addr64 offset:17
; LOOP-NEXT: buffer_load_ubyte v6, v[2:3], s[0:3], 0 addr64 offset:18 ; LOOP-NEXT: buffer_load_ubyte v6, v[2:3], s[0:3], 0 addr64 offset:18
; LOOP-NEXT: buffer_load_ubyte v2, v[2:3], s[0:3], 0 addr64 offset:19 ; LOOP-NEXT: buffer_load_ubyte v2, v[2:3], s[0:3], 0 addr64 offset:19
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llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memmove.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -march=amdgcn -verify-machineinstrs -amdgpu-mem-intrinsic-expand-size=3 %s -o - | FileCheck -check-prefix=LOOP %s ; RUN: llc -global-isel -march=amdgcn -verify-machineinstrs -amdgpu-mem-intrinsic-expand-size=3 %s -o - | FileCheck -check-prefix=LOOP %s
; RUN: llc -global-isel -march=amdgcn -verify-machineinstrs -amdgpu-mem-intrinsic-expand-size=5 %s -o - | FileCheck -check-prefix=UNROLL %s ; RUN: llc -global-isel -march=amdgcn -verify-machineinstrs -amdgpu-mem-intrinsic-expand-size=5 %s -o - | FileCheck -check-prefix=UNROLL %s
declare void @llvm.memmove.p1i8.p1i8.i32(i8 addrspace(1)*, i8 addrspace(1)*, i32, i1) declare void @llvm.memmove.p1i8.p1i8.i32(i8 addrspace(1)*, i8 addrspace(1)*, i32, i1)
define amdgpu_cs void @memmove_p1i8(i8 addrspace(1)* %dst, i8 addrspace(1)* %src) { define amdgpu_cs void @memmove_p1i8(i8 addrspace(1)* %dst, i8 addrspace(1)* %src) {
; LOOP-LABEL: memmove_p1i8: ; LOOP-LABEL: memmove_p1i8:
; LOOP: ; %bb.0: ; LOOP: ; %bb.0:
; LOOP-NEXT: v_cmp_ge_u64_e32 vcc, v[2:3], v[0:1] ; LOOP-NEXT: v_cmp_ge_u64_e32 vcc, v[2:3], v[0:1]
; LOOP-NEXT: s_and_saveexec_b64 s[0:1], vcc ; LOOP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; LOOP-NEXT: s_xor_b64 s[4:5], exec, s[0:1] ; LOOP-NEXT: s_xor_b64 s[4:5], exec, s[0:1]
; LOOP-NEXT: s_cbranch_execz BB0_3 ; LOOP-NEXT: s_cbranch_execz .LBB0_3
; LOOP-NEXT: ; %bb.1: ; %copy_forward ; LOOP-NEXT: ; %bb.1: ; %copy_forward
; LOOP-NEXT: s_mov_b64 s[0:1], 0 ; LOOP-NEXT: s_mov_b64 s[0:1], 0
; LOOP-NEXT: s_mov_b32 s2, 0 ; LOOP-NEXT: s_mov_b32 s2, 0
; LOOP-NEXT: s_mov_b32 s3, 0xf000 ; LOOP-NEXT: s_mov_b32 s3, 0xf000
; LOOP-NEXT: v_mov_b32_e32 v5, s1 ; LOOP-NEXT: v_mov_b32_e32 v5, s1
; LOOP-NEXT: v_mov_b32_e32 v4, s0 ; LOOP-NEXT: v_mov_b32_e32 v4, s0
; LOOP-NEXT: BB0_2: ; %copy_forward_loop ; LOOP-NEXT: .LBB0_2: ; %copy_forward_loop
; LOOP-NEXT: ; =>This Inner Loop Header: Depth=1 ; LOOP-NEXT: ; =>This Inner Loop Header: Depth=1
; LOOP-NEXT: v_add_i32_e32 v6, vcc, v2, v4 ; LOOP-NEXT: v_add_i32_e32 v6, vcc, v2, v4
; LOOP-NEXT: v_addc_u32_e32 v7, vcc, v3, v5, vcc ; LOOP-NEXT: v_addc_u32_e32 v7, vcc, v3, v5, vcc
; LOOP-NEXT: s_waitcnt expcnt(0) ; LOOP-NEXT: s_waitcnt expcnt(0)
; LOOP-NEXT: buffer_load_ubyte v8, v[6:7], s[0:3], 0 addr64 ; LOOP-NEXT: buffer_load_ubyte v8, v[6:7], s[0:3], 0 addr64
; LOOP-NEXT: v_add_i32_e32 v6, vcc, v0, v4 ; LOOP-NEXT: v_add_i32_e32 v6, vcc, v0, v4
; LOOP-NEXT: v_addc_u32_e32 v7, vcc, v1, v5, vcc ; LOOP-NEXT: v_addc_u32_e32 v7, vcc, v1, v5, vcc
; LOOP-NEXT: v_add_i32_e32 v4, vcc, 1, v4 ; LOOP-NEXT: v_add_i32_e32 v4, vcc, 1, v4
; LOOP-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc ; LOOP-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; LOOP-NEXT: v_cmp_ne_u32_e32 vcc, 4, v4 ; LOOP-NEXT: v_cmp_ne_u32_e32 vcc, 4, v4
; LOOP-NEXT: s_waitcnt vmcnt(0) ; LOOP-NEXT: s_waitcnt vmcnt(0)
; LOOP-NEXT: buffer_store_byte v8, v[6:7], s[0:3], 0 addr64 ; LOOP-NEXT: buffer_store_byte v8, v[6:7], s[0:3], 0 addr64
; LOOP-NEXT: s_cbranch_vccnz BB0_2 ; LOOP-NEXT: s_cbranch_vccnz .LBB0_2
; LOOP-NEXT: BB0_3: ; %Flow14 ; LOOP-NEXT: .LBB0_3: ; %Flow14
; LOOP-NEXT: s_or_saveexec_b64 s[0:1], s[4:5] ; LOOP-NEXT: s_or_saveexec_b64 s[0:1], s[4:5]
; LOOP-NEXT: s_xor_b64 exec, exec, s[0:1] ; LOOP-NEXT: s_xor_b64 exec, exec, s[0:1]
; LOOP-NEXT: s_cbranch_execz BB0_6 ; LOOP-NEXT: s_cbranch_execz .LBB0_6
; LOOP-NEXT: ; %bb.4: ; %copy_backwards ; LOOP-NEXT: ; %bb.4: ; %copy_backwards
; LOOP-NEXT: s_mov_b64 s[4:5], 3 ; LOOP-NEXT: s_mov_b64 s[4:5], 3
; LOOP-NEXT: s_mov_b32 s2, 0 ; LOOP-NEXT: s_mov_b32 s2, 0
; LOOP-NEXT: s_mov_b32 s3, 0xf000 ; LOOP-NEXT: s_mov_b32 s3, 0xf000
; LOOP-NEXT: s_mov_b64 s[0:1], 0 ; LOOP-NEXT: s_mov_b64 s[0:1], 0
; LOOP-NEXT: v_mov_b32_e32 v4, s4 ; LOOP-NEXT: v_mov_b32_e32 v4, s4
; LOOP-NEXT: v_mov_b32_e32 v5, s5 ; LOOP-NEXT: v_mov_b32_e32 v5, s5
; LOOP-NEXT: BB0_5: ; %copy_backwards_loop ; LOOP-NEXT: .LBB0_5: ; %copy_backwards_loop
; LOOP-NEXT: ; =>This Inner Loop Header: Depth=1 ; LOOP-NEXT: ; =>This Inner Loop Header: Depth=1
; LOOP-NEXT: v_add_i32_e32 v6, vcc, v2, v4 ; LOOP-NEXT: v_add_i32_e32 v6, vcc, v2, v4
; LOOP-NEXT: v_addc_u32_e32 v7, vcc, v3, v5, vcc ; LOOP-NEXT: v_addc_u32_e32 v7, vcc, v3, v5, vcc
; LOOP-NEXT: s_waitcnt expcnt(0) ; LOOP-NEXT: s_waitcnt expcnt(0)
; LOOP-NEXT: buffer_load_ubyte v8, v[6:7], s[0:3], 0 addr64 ; LOOP-NEXT: buffer_load_ubyte v8, v[6:7], s[0:3], 0 addr64
; LOOP-NEXT: v_add_i32_e32 v6, vcc, v0, v4 ; LOOP-NEXT: v_add_i32_e32 v6, vcc, v0, v4
; LOOP-NEXT: v_addc_u32_e32 v7, vcc, v1, v5, vcc ; LOOP-NEXT: v_addc_u32_e32 v7, vcc, v1, v5, vcc
; LOOP-NEXT: v_add_i32_e32 v4, vcc, -1, v4 ; LOOP-NEXT: v_add_i32_e32 v4, vcc, -1, v4
; LOOP-NEXT: v_addc_u32_e32 v5, vcc, -1, v5, vcc ; LOOP-NEXT: v_addc_u32_e32 v5, vcc, -1, v5, vcc
; LOOP-NEXT: v_cmp_eq_u32_e32 vcc, -1, v4 ; LOOP-NEXT: v_cmp_eq_u32_e32 vcc, -1, v4
; LOOP-NEXT: s_waitcnt vmcnt(0) ; LOOP-NEXT: s_waitcnt vmcnt(0)
; LOOP-NEXT: buffer_store_byte v8, v[6:7], s[0:3], 0 addr64 ; LOOP-NEXT: buffer_store_byte v8, v[6:7], s[0:3], 0 addr64
; LOOP-NEXT: s_cbranch_vccz BB0_5 ; LOOP-NEXT: s_cbranch_vccz .LBB0_5
; LOOP-NEXT: BB0_6: ; %memmove_done ; LOOP-NEXT: .LBB0_6: ; %memmove_done
; LOOP-NEXT: s_endpgm ; LOOP-NEXT: s_endpgm
; ;
; UNROLL-LABEL: memmove_p1i8: ; UNROLL-LABEL: memmove_p1i8:
; UNROLL: ; %bb.0: ; UNROLL: ; %bb.0:
; UNROLL-NEXT: s_mov_b32 s2, 0 ; UNROLL-NEXT: s_mov_b32 s2, 0
; UNROLL-NEXT: s_mov_b32 s3, 0xf000 ; UNROLL-NEXT: s_mov_b32 s3, 0xf000
; UNROLL-NEXT: s_mov_b64 s[0:1], 0 ; UNROLL-NEXT: s_mov_b64 s[0:1], 0
; UNROLL-NEXT: buffer_load_ubyte v4, v[2:3], s[0:3], 0 addr64 ; UNROLL-NEXT: buffer_load_ubyte v4, v[2:3], s[0:3], 0 addr64
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llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -march=amdgcn -verify-machineinstrs -amdgpu-mem-intrinsic-expand-size=3 %s -o - | FileCheck -check-prefix=LOOP %s ; RUN: llc -global-isel -march=amdgcn -verify-machineinstrs -amdgpu-mem-intrinsic-expand-size=3 %s -o - | FileCheck -check-prefix=LOOP %s
; RUN: llc -global-isel -march=amdgcn -verify-machineinstrs -amdgpu-mem-intrinsic-expand-size=5 %s -o - | FileCheck -check-prefix=UNROLL %s ; RUN: llc -global-isel -march=amdgcn -verify-machineinstrs -amdgpu-mem-intrinsic-expand-size=5 %s -o - | FileCheck -check-prefix=UNROLL %s
declare void @llvm.memset.p1i8.i32(i8 addrspace(1)*, i8, i32, i1) declare void @llvm.memset.p1i8.i32(i8 addrspace(1)*, i8, i32, i1)
define amdgpu_cs void @memset_p1i8(i8 addrspace(1)* %dst, i8 %val) { define amdgpu_cs void @memset_p1i8(i8 addrspace(1)* %dst, i8 %val) {
; LOOP-LABEL: memset_p1i8: ; LOOP-LABEL: memset_p1i8:
; LOOP: ; %bb.0: ; %loadstoreloop.preheader ; LOOP: ; %bb.0: ; %loadstoreloop.preheader
; LOOP-NEXT: s_mov_b64 s[0:1], 0 ; LOOP-NEXT: s_mov_b64 s[0:1], 0
; LOOP-NEXT: s_mov_b32 s2, 0 ; LOOP-NEXT: s_mov_b32 s2, 0
; LOOP-NEXT: s_mov_b32 s3, 0xf000 ; LOOP-NEXT: s_mov_b32 s3, 0xf000
; LOOP-NEXT: v_mov_b32_e32 v4, s1 ; LOOP-NEXT: v_mov_b32_e32 v4, s1
; LOOP-NEXT: v_mov_b32_e32 v3, s0 ; LOOP-NEXT: v_mov_b32_e32 v3, s0
; LOOP-NEXT: BB0_1: ; %loadstoreloop ; LOOP-NEXT: .LBB0_1: ; %loadstoreloop
; LOOP-NEXT: ; =>This Inner Loop Header: Depth=1 ; LOOP-NEXT: ; =>This Inner Loop Header: Depth=1
; LOOP-NEXT: v_add_i32_e32 v5, vcc, v0, v3 ; LOOP-NEXT: v_add_i32_e32 v5, vcc, v0, v3
; LOOP-NEXT: v_addc_u32_e32 v6, vcc, v1, v4, vcc ; LOOP-NEXT: v_addc_u32_e32 v6, vcc, v1, v4, vcc
; LOOP-NEXT: v_add_i32_e32 v3, vcc, 1, v3 ; LOOP-NEXT: v_add_i32_e32 v3, vcc, 1, v3
; LOOP-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc ; LOOP-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc
; LOOP-NEXT: v_cmp_gt_u32_e32 vcc, 4, v3 ; LOOP-NEXT: v_cmp_gt_u32_e32 vcc, 4, v3
; LOOP-NEXT: buffer_store_byte v2, v[5:6], s[0:3], 0 addr64 ; LOOP-NEXT: buffer_store_byte v2, v[5:6], s[0:3], 0 addr64
; LOOP-NEXT: s_cbranch_vccnz BB0_1 ; LOOP-NEXT: s_cbranch_vccnz .LBB0_1
; LOOP-NEXT: ; %bb.2: ; %split ; LOOP-NEXT: ; %bb.2: ; %split
; LOOP-NEXT: s_endpgm ; LOOP-NEXT: s_endpgm
; ;
; UNROLL-LABEL: memset_p1i8: ; UNROLL-LABEL: memset_p1i8:
; UNROLL: ; %bb.0: ; UNROLL: ; %bb.0:
; UNROLL-NEXT: s_mov_b32 s2, 0 ; UNROLL-NEXT: s_mov_b32 s2, 0
; UNROLL-NEXT: s_mov_b32 s3, 0xf000 ; UNROLL-NEXT: s_mov_b32 s3, 0xf000
; UNROLL-NEXT: s_mov_b64 s[0:1], 0 ; UNROLL-NEXT: s_mov_b64 s[0:1], 0
; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 ; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64
; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:1 ; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:1
; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:2 ; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:2
; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:3 ; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:3
; UNROLL-NEXT: s_endpgm ; UNROLL-NEXT: s_endpgm
call void @llvm.memset.p1i8.i32(i8 addrspace(1)* %dst, i8 %val, i32 4, i1 false) call void @llvm.memset.p1i8.i32(i8 addrspace(1)* %dst, i8 %val, i32 4, i1 false)
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
; Test the localizer did something and we don't materialize all ; Test the localizer did something and we don't materialize all
; constants in SGPRs in the entry block. ; constants in SGPRs in the entry block.
define amdgpu_kernel void @localize_constants(i1 %cond) { define amdgpu_kernel void @localize_constants(i1 %cond) {
; GFX9-LABEL: localize_constants: ; GFX9-LABEL: localize_constants:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dword s1, s[4:5], 0x0 ; GFX9-NEXT: s_load_dword s1, s[4:5], 0x0
; GFX9-NEXT: s_mov_b32 s0, -1 ; GFX9-NEXT: s_mov_b32 s0, -1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_xor_b32 s1, s1, -1 ; GFX9-NEXT: s_xor_b32 s1, s1, -1
; GFX9-NEXT: s_and_b32 s1, s1, 1 ; GFX9-NEXT: s_and_b32 s1, s1, 1
; GFX9-NEXT: s_cmp_lg_u32 s1, 0 ; GFX9-NEXT: s_cmp_lg_u32 s1, 0
; GFX9-NEXT: s_cbranch_scc0 BB0_2 ; GFX9-NEXT: s_cbranch_scc0 .LBB0_2
; GFX9-NEXT: ; %bb.1: ; %bb1 ; GFX9-NEXT: ; %bb.1: ; %bb1
; GFX9-NEXT: v_mov_b32_e32 v0, 0x5be6 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x5be6
; GFX9-NEXT: global_store_dword v[0:1], v0, off ; GFX9-NEXT: global_store_dword v[0:1], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, 0x1c7 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x1c7
; GFX9-NEXT: global_store_dword v[0:1], v0, off ; GFX9-NEXT: global_store_dword v[0:1], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, 0x3e8 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x3e8
; GFX9-NEXT: global_store_dword v[0:1], v0, off ; GFX9-NEXT: global_store_dword v[0:1], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, 0x1c8 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x1c8
; GFX9-NEXT: global_store_dword v[0:1], v0, off ; GFX9-NEXT: global_store_dword v[0:1], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, 0x3e7 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x3e7
; GFX9-NEXT: global_store_dword v[0:1], v0, off ; GFX9-NEXT: global_store_dword v[0:1], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, 0x7b ; GFX9-NEXT: v_mov_b32_e32 v0, 0x7b
; GFX9-NEXT: s_mov_b32 s0, 0 ; GFX9-NEXT: s_mov_b32 s0, 0
; GFX9-NEXT: global_store_dword v[0:1], v0, off ; GFX9-NEXT: global_store_dword v[0:1], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: BB0_2: ; %Flow ; GFX9-NEXT: .LBB0_2: ; %Flow
; GFX9-NEXT: s_xor_b32 s0, s0, -1 ; GFX9-NEXT: s_xor_b32 s0, s0, -1
; GFX9-NEXT: s_and_b32 s0, s0, 1 ; GFX9-NEXT: s_and_b32 s0, s0, 1
; GFX9-NEXT: s_cmp_lg_u32 s0, 0 ; GFX9-NEXT: s_cmp_lg_u32 s0, 0
; GFX9-NEXT: s_cbranch_scc1 BB0_4 ; GFX9-NEXT: s_cbranch_scc1 .LBB0_4
; GFX9-NEXT: ; %bb.3: ; %bb0 ; GFX9-NEXT: ; %bb.3: ; %bb0
; GFX9-NEXT: v_mov_b32_e32 v0, 0x7b ; GFX9-NEXT: v_mov_b32_e32 v0, 0x7b
; GFX9-NEXT: global_store_dword v[0:1], v0, off ; GFX9-NEXT: global_store_dword v[0:1], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, 0x1c8 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x1c8
; GFX9-NEXT: global_store_dword v[0:1], v0, off ; GFX9-NEXT: global_store_dword v[0:1], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, 0x3e7 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x3e7
; GFX9-NEXT: global_store_dword v[0:1], v0, off ; GFX9-NEXT: global_store_dword v[0:1], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, 0x3e8 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x3e8
; GFX9-NEXT: global_store_dword v[0:1], v0, off ; GFX9-NEXT: global_store_dword v[0:1], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, 0x1c7 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x1c7
; GFX9-NEXT: global_store_dword v[0:1], v0, off ; GFX9-NEXT: global_store_dword v[0:1], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, 0x5be6 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x5be6
; GFX9-NEXT: global_store_dword v[0:1], v0, off ; GFX9-NEXT: global_store_dword v[0:1], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: BB0_4: ; %bb2 ; GFX9-NEXT: .LBB0_4: ; %bb2
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
entry: entry:
br i1 %cond, label %bb0, label %bb1 br i1 %cond, label %bb0, label %bb1
bb0: bb0:
store volatile i32 123, i32 addrspace(1)* undef store volatile i32 123, i32 addrspace(1)* undef
store volatile i32 456, i32 addrspace(1)* undef store volatile i32 456, i32 addrspace(1)* undef
store volatile i32 999, i32 addrspace(1)* undef store volatile i32 999, i32 addrspace(1)* undef
Show All 26 Lines
; GFX9-LABEL: localize_globals: ; GFX9-LABEL: localize_globals:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dword s1, s[4:5], 0x0 ; GFX9-NEXT: s_load_dword s1, s[4:5], 0x0
; GFX9-NEXT: s_mov_b32 s0, -1 ; GFX9-NEXT: s_mov_b32 s0, -1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_xor_b32 s1, s1, -1 ; GFX9-NEXT: s_xor_b32 s1, s1, -1
; GFX9-NEXT: s_and_b32 s1, s1, 1 ; GFX9-NEXT: s_and_b32 s1, s1, 1
; GFX9-NEXT: s_cmp_lg_u32 s1, 0 ; GFX9-NEXT: s_cmp_lg_u32 s1, 0
; GFX9-NEXT: s_cbranch_scc0 BB1_2 ; GFX9-NEXT: s_cbranch_scc0 .LBB1_2
; GFX9-NEXT: ; %bb.1: ; %bb1 ; GFX9-NEXT: ; %bb.1: ; %bb1
; GFX9-NEXT: s_getpc_b64 s[0:1] ; GFX9-NEXT: s_getpc_b64 s[0:1]
; GFX9-NEXT: s_add_u32 s0, s0, gv2@gotpcrel32@lo+4 ; GFX9-NEXT: s_add_u32 s0, s0, gv2@gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s1, s1, gv2@gotpcrel32@hi+12 ; GFX9-NEXT: s_addc_u32 s1, s1, gv2@gotpcrel32@hi+12
; GFX9-NEXT: s_getpc_b64 s[2:3] ; GFX9-NEXT: s_getpc_b64 s[2:3]
; GFX9-NEXT: s_add_u32 s2, s2, gv3@gotpcrel32@lo+4 ; GFX9-NEXT: s_add_u32 s2, s2, gv3@gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s3, s3, gv3@gotpcrel32@hi+12 ; GFX9-NEXT: s_addc_u32 s3, s3, gv3@gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0 ; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[2:3], 0x0 ; GFX9-NEXT: s_load_dwordx2 s[6:7], s[2:3], 0x0
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v1, 1 ; GFX9-NEXT: v_mov_b32_e32 v1, 1
; GFX9-NEXT: s_mov_b32 s0, 0 ; GFX9-NEXT: s_mov_b32 s0, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dword v0, v0, s[4:5] ; GFX9-NEXT: global_store_dword v0, v0, s[4:5]
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_store_dword v0, v1, s[6:7] ; GFX9-NEXT: global_store_dword v0, v1, s[6:7]
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: BB1_2: ; %Flow ; GFX9-NEXT: .LBB1_2: ; %Flow
; GFX9-NEXT: s_xor_b32 s0, s0, -1 ; GFX9-NEXT: s_xor_b32 s0, s0, -1
; GFX9-NEXT: s_and_b32 s0, s0, 1 ; GFX9-NEXT: s_and_b32 s0, s0, 1
; GFX9-NEXT: s_cmp_lg_u32 s0, 0 ; GFX9-NEXT: s_cmp_lg_u32 s0, 0
; GFX9-NEXT: s_cbranch_scc1 BB1_4 ; GFX9-NEXT: s_cbranch_scc1 .LBB1_4
; GFX9-NEXT: ; %bb.3: ; %bb0 ; GFX9-NEXT: ; %bb.3: ; %bb0
; GFX9-NEXT: s_getpc_b64 s[0:1] ; GFX9-NEXT: s_getpc_b64 s[0:1]
; GFX9-NEXT: s_add_u32 s0, s0, gv0@gotpcrel32@lo+4 ; GFX9-NEXT: s_add_u32 s0, s0, gv0@gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s1, s1, gv0@gotpcrel32@hi+12 ; GFX9-NEXT: s_addc_u32 s1, s1, gv0@gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX9-NEXT: s_getpc_b64 s[2:3] ; GFX9-NEXT: s_getpc_b64 s[2:3]
; GFX9-NEXT: s_add_u32 s2, s2, gv1@gotpcrel32@lo+4 ; GFX9-NEXT: s_add_u32 s2, s2, gv1@gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s3, s3, gv1@gotpcrel32@hi+12 ; GFX9-NEXT: s_addc_u32 s3, s3, gv1@gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v1, 1 ; GFX9-NEXT: v_mov_b32_e32 v1, 1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dword v0, v0, s[0:1] ; GFX9-NEXT: global_store_dword v0, v0, s[0:1]
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_store_dword v0, v1, s[2:3] ; GFX9-NEXT: global_store_dword v0, v1, s[2:3]
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: BB1_4: ; %bb2 ; GFX9-NEXT: .LBB1_4: ; %bb2
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
entry: entry:
br i1 %cond, label %bb0, label %bb1 br i1 %cond, label %bb0, label %bb1
bb0: bb0:
store volatile i32 0, i32 addrspace(1)* @gv0 store volatile i32 0, i32 addrspace(1)* @gv0
store volatile i32 1, i32 addrspace(1)* @gv1 store volatile i32 1, i32 addrspace(1)* @gv1
br label %bb2 br label %bb2
Show All 16 Lines
; GFX9-LABEL: localize_internal_globals: ; GFX9-LABEL: localize_internal_globals:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT: s_xor_b64 s[4:5], vcc, -1 ; GFX9-NEXT: s_xor_b64 s[4:5], vcc, -1
; GFX9-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GFX9-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[6:7] ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[6:7]
; GFX9-NEXT: s_cbranch_execz BB2_2 ; GFX9-NEXT: s_cbranch_execz .LBB2_2
; GFX9-NEXT: ; %bb.1: ; %bb1 ; GFX9-NEXT: ; %bb.1: ; %bb1
; GFX9-NEXT: s_getpc_b64 s[6:7] ; GFX9-NEXT: s_getpc_b64 s[6:7]
; GFX9-NEXT: s_add_u32 s6, s6, static.gv2@rel32@lo+4 ; GFX9-NEXT: s_add_u32 s6, s6, static.gv2@rel32@lo+4
; GFX9-NEXT: s_addc_u32 s7, s7, static.gv2@rel32@hi+12 ; GFX9-NEXT: s_addc_u32 s7, s7, static.gv2@rel32@hi+12
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: global_store_dword v0, v0, s[6:7] ; GFX9-NEXT: global_store_dword v0, v0, s[6:7]
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_getpc_b64 s[6:7] ; GFX9-NEXT: s_getpc_b64 s[6:7]
; GFX9-NEXT: s_add_u32 s6, s6, static.gv3@rel32@lo+4 ; GFX9-NEXT: s_add_u32 s6, s6, static.gv3@rel32@lo+4
; GFX9-NEXT: s_addc_u32 s7, s7, static.gv3@rel32@hi+12 ; GFX9-NEXT: s_addc_u32 s7, s7, static.gv3@rel32@hi+12
; GFX9-NEXT: v_mov_b32_e32 v1, 1 ; GFX9-NEXT: v_mov_b32_e32 v1, 1
; GFX9-NEXT: global_store_dword v0, v1, s[6:7] ; GFX9-NEXT: global_store_dword v0, v1, s[6:7]
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: BB2_2: ; %Flow ; GFX9-NEXT: .LBB2_2: ; %Flow
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], s[4:5] ; GFX9-NEXT: s_or_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_xor_b64 exec, exec, s[4:5] ; GFX9-NEXT: s_xor_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz BB2_4 ; GFX9-NEXT: s_cbranch_execz .LBB2_4
; GFX9-NEXT: ; %bb.3: ; %bb0 ; GFX9-NEXT: ; %bb.3: ; %bb0
; GFX9-NEXT: s_getpc_b64 s[6:7] ; GFX9-NEXT: s_getpc_b64 s[6:7]
; GFX9-NEXT: s_add_u32 s6, s6, static.gv0@rel32@lo+4 ; GFX9-NEXT: s_add_u32 s6, s6, static.gv0@rel32@lo+4
; GFX9-NEXT: s_addc_u32 s7, s7, static.gv0@rel32@hi+12 ; GFX9-NEXT: s_addc_u32 s7, s7, static.gv0@rel32@hi+12
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: global_store_dword v0, v0, s[6:7] ; GFX9-NEXT: global_store_dword v0, v0, s[6:7]
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_getpc_b64 s[6:7] ; GFX9-NEXT: s_getpc_b64 s[6:7]
; GFX9-NEXT: s_add_u32 s6, s6, static.gv1@rel32@lo+4 ; GFX9-NEXT: s_add_u32 s6, s6, static.gv1@rel32@lo+4
; GFX9-NEXT: s_addc_u32 s7, s7, static.gv1@rel32@hi+12 ; GFX9-NEXT: s_addc_u32 s7, s7, static.gv1@rel32@hi+12
; GFX9-NEXT: v_mov_b32_e32 v1, 1 ; GFX9-NEXT: v_mov_b32_e32 v1, 1
; GFX9-NEXT: global_store_dword v0, v1, s[6:7] ; GFX9-NEXT: global_store_dword v0, v1, s[6:7]
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: BB2_4: ; %bb2 ; GFX9-NEXT: .LBB2_4: ; %bb2
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
entry: entry:
br i1 %cond, label %bb0, label %bb1 br i1 %cond, label %bb0, label %bb1
bb0: bb0:
store volatile i32 0, i32 addrspace(1)* @static.gv0 store volatile i32 0, i32 addrspace(1)* @static.gv0
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llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll

Show All 14 Lines
; GCN: ; %bb.0: ; %entry ; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_load_dword s6, s[4:5], 0x8 ; GCN-NEXT: s_load_dword s6, s[4:5], 0x8
; GCN-NEXT: s_add_u32 s0, s0, s9 ; GCN-NEXT: s_add_u32 s0, s0, s9
; GCN-NEXT: s_addc_u32 s1, s1, 0 ; GCN-NEXT: s_addc_u32 s1, s1, 0
; GCN-NEXT: s_movk_i32 s32, 0x400 ; GCN-NEXT: s_movk_i32 s32, 0x400
; GCN-NEXT: s_mov_b32 s33, 0 ; GCN-NEXT: s_mov_b32 s33, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_cmp_lg_u32 s6, 0 ; GCN-NEXT: s_cmp_lg_u32 s6, 0
; GCN-NEXT: s_cbranch_scc1 BB0_3 ; GCN-NEXT: s_cbranch_scc1 .LBB0_3
; GCN-NEXT: ; %bb.1: ; %bb.0 ; GCN-NEXT: ; %bb.1: ; %bb.0
; GCN-NEXT: s_load_dword s6, s[4:5], 0xc ; GCN-NEXT: s_load_dword s6, s[4:5], 0xc
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_cmp_lg_u32 s6, 0 ; GCN-NEXT: s_cmp_lg_u32 s6, 0
; GCN-NEXT: s_cbranch_scc1 BB0_3 ; GCN-NEXT: s_cbranch_scc1 .LBB0_3
; GCN-NEXT: ; %bb.2: ; %bb.1 ; GCN-NEXT: ; %bb.2: ; %bb.1
; GCN-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x0 ; GCN-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x0
; GCN-NEXT: s_load_dword s8, s[4:5], 0x10 ; GCN-NEXT: s_load_dword s8, s[4:5], 0x10
; GCN-NEXT: s_add_u32 s4, s32, 0x1000 ; GCN-NEXT: s_add_u32 s4, s32, 0x1000
; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: v_mov_b32_e32 v2, s4 ; GCN-NEXT: v_mov_b32_e32 v2, s4
; GCN-NEXT: v_mov_b32_e32 v3, 1 ; GCN-NEXT: v_mov_b32_e32 v3, 1
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_lshl_b32 s5, s8, 2 ; GCN-NEXT: s_lshl_b32 s5, s8, 2
; GCN-NEXT: s_add_u32 s4, s4, s5 ; GCN-NEXT: s_add_u32 s4, s4, s5
; GCN-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; GCN-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; GCN-NEXT: buffer_store_dword v3, v2, s[0:3], 0 offen offset:4 ; GCN-NEXT: buffer_store_dword v3, v2, s[0:3], 0 offen offset:4
; GCN-NEXT: v_mov_b32_e32 v2, s4 ; GCN-NEXT: v_mov_b32_e32 v2, s4
; GCN-NEXT: buffer_load_dword v2, v2, s[0:3], 0 offen ; GCN-NEXT: buffer_load_dword v2, v2, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_add_u32_e32 v0, v2, v0 ; GCN-NEXT: v_add_u32_e32 v0, v2, v0
; GCN-NEXT: global_store_dword v1, v0, s[6:7] ; GCN-NEXT: global_store_dword v1, v0, s[6:7]
; GCN-NEXT: BB0_3: ; %bb.2 ; GCN-NEXT: .LBB0_3: ; %bb.2
; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: global_store_dword v[0:1], v0, off ; GCN-NEXT: global_store_dword v[0:1], v0, off
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
entry: entry:
%cond0 = icmp eq i32 %arg.cond0, 0 %cond0 = icmp eq i32 %arg.cond0, 0
br i1 %cond0, label %bb.0, label %bb.2 br i1 %cond0, label %bb.0, label %bb.2
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; GCN: ; %bb.0: ; %entry ; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_load_dword s6, s[4:5], 0x8 ; GCN-NEXT: s_load_dword s6, s[4:5], 0x8
; GCN-NEXT: s_add_u32 s0, s0, s9 ; GCN-NEXT: s_add_u32 s0, s0, s9
; GCN-NEXT: s_addc_u32 s1, s1, 0 ; GCN-NEXT: s_addc_u32 s1, s1, 0
; GCN-NEXT: s_movk_i32 s32, 0x1000 ; GCN-NEXT: s_movk_i32 s32, 0x1000
; GCN-NEXT: s_mov_b32 s33, 0 ; GCN-NEXT: s_mov_b32 s33, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_cmp_lg_u32 s6, 0 ; GCN-NEXT: s_cmp_lg_u32 s6, 0
; GCN-NEXT: s_cbranch_scc1 BB1_2 ; GCN-NEXT: s_cbranch_scc1 .LBB1_2
; GCN-NEXT: ; %bb.1: ; %bb.0 ; GCN-NEXT: ; %bb.1: ; %bb.0
; GCN-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x0 ; GCN-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x0
; GCN-NEXT: s_load_dword s8, s[4:5], 0xc ; GCN-NEXT: s_load_dword s8, s[4:5], 0xc
; GCN-NEXT: s_add_u32 s4, s32, 0x1000 ; GCN-NEXT: s_add_u32 s4, s32, 0x1000
; GCN-NEXT: s_and_b32 s4, s4, 0xfffff000 ; GCN-NEXT: s_and_b32 s4, s4, 0xfffff000
; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: v_mov_b32_e32 v2, s4 ; GCN-NEXT: v_mov_b32_e32 v2, s4
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_lshl_b32 s5, s8, 2 ; GCN-NEXT: s_lshl_b32 s5, s8, 2
; GCN-NEXT: v_mov_b32_e32 v3, 1 ; GCN-NEXT: v_mov_b32_e32 v3, 1
; GCN-NEXT: s_add_u32 s4, s4, s5 ; GCN-NEXT: s_add_u32 s4, s4, s5
; GCN-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; GCN-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; GCN-NEXT: buffer_store_dword v3, v2, s[0:3], 0 offen offset:4 ; GCN-NEXT: buffer_store_dword v3, v2, s[0:3], 0 offen offset:4
; GCN-NEXT: v_mov_b32_e32 v2, s4 ; GCN-NEXT: v_mov_b32_e32 v2, s4
; GCN-NEXT: buffer_load_dword v2, v2, s[0:3], 0 offen ; GCN-NEXT: buffer_load_dword v2, v2, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_add_u32_e32 v0, v2, v0 ; GCN-NEXT: v_add_u32_e32 v0, v2, v0
; GCN-NEXT: global_store_dword v1, v0, s[6:7] ; GCN-NEXT: global_store_dword v1, v0, s[6:7]
; GCN-NEXT: BB1_2: ; %bb.1 ; GCN-NEXT: .LBB1_2: ; %bb.1
; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: global_store_dword v[0:1], v0, off ; GCN-NEXT: global_store_dword v[0:1], v0, off
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
entry: entry:
%cond = icmp eq i32 %arg.cond, 0 %cond = icmp eq i32 %arg.cond, 0
br i1 %cond, label %bb.0, label %bb.1 br i1 %cond, label %bb.0, label %bb.1
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; GCN-LABEL: func_non_entry_block_static_alloca_align4: ; GCN-LABEL: func_non_entry_block_static_alloca_align4:
; GCN: ; %bb.0: ; %entry ; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s7, s33 ; GCN-NEXT: s_mov_b32 s7, s33
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GCN-NEXT: s_mov_b32 s33, s32 ; GCN-NEXT: s_mov_b32 s33, s32
; GCN-NEXT: s_addk_i32 s32, 0x400 ; GCN-NEXT: s_addk_i32 s32, 0x400
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_cbranch_execz BB2_3 ; GCN-NEXT: s_cbranch_execz .LBB2_3
; GCN-NEXT: ; %bb.1: ; %bb.0 ; GCN-NEXT: ; %bb.1: ; %bb.0
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; GCN-NEXT: s_and_b64 exec, exec, vcc ; GCN-NEXT: s_and_b64 exec, exec, vcc
; GCN-NEXT: s_cbranch_execz BB2_3 ; GCN-NEXT: s_cbranch_execz .LBB2_3
; GCN-NEXT: ; %bb.2: ; %bb.1 ; GCN-NEXT: ; %bb.2: ; %bb.1
; GCN-NEXT: s_add_u32 s6, s32, 0x1000 ; GCN-NEXT: s_add_u32 s6, s32, 0x1000
; GCN-NEXT: v_mov_b32_e32 v2, 0 ; GCN-NEXT: v_mov_b32_e32 v2, 0
; GCN-NEXT: v_mov_b32_e32 v3, s6 ; GCN-NEXT: v_mov_b32_e32 v3, s6
; GCN-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen ; GCN-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; GCN-NEXT: v_mov_b32_e32 v2, 1 ; GCN-NEXT: v_mov_b32_e32 v2, 1
; GCN-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen offset:4 ; GCN-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen offset:4
; GCN-NEXT: v_lshlrev_b32_e32 v2, 2, v4 ; GCN-NEXT: v_lshlrev_b32_e32 v2, 2, v4
; GCN-NEXT: v_add_u32_e32 v2, s6, v2 ; GCN-NEXT: v_add_u32_e32 v2, s6, v2
; GCN-NEXT: buffer_load_dword v2, v2, s[0:3], 0 offen ; GCN-NEXT: buffer_load_dword v2, v2, s[0:3], 0 offen
; GCN-NEXT: v_and_b32_e32 v3, 0x3ff, v5 ; GCN-NEXT: v_and_b32_e32 v3, 0x3ff, v5
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_add_u32_e32 v2, v2, v3 ; GCN-NEXT: v_add_u32_e32 v2, v2, v3
; GCN-NEXT: global_store_dword v[0:1], v2, off ; GCN-NEXT: global_store_dword v[0:1], v2, off
; GCN-NEXT: BB2_3: ; %bb.2 ; GCN-NEXT: .LBB2_3: ; %bb.2
; GCN-NEXT: s_or_b64 exec, exec, s[4:5] ; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: global_store_dword v[0:1], v0, off ; GCN-NEXT: global_store_dword v[0:1], v0, off
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_addk_i32 s32, 0xfc00 ; GCN-NEXT: s_addk_i32 s32, 0xfc00
; GCN-NEXT: s_mov_b32 s33, s7 ; GCN-NEXT: s_mov_b32 s33, s7
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
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; GCN: ; %bb.0: ; %entry ; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s7, s33 ; GCN-NEXT: s_mov_b32 s7, s33
; GCN-NEXT: s_add_i32 s33, s32, 0xfc0 ; GCN-NEXT: s_add_i32 s33, s32, 0xfc0
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GCN-NEXT: s_and_b32 s33, s33, 0xfffff000 ; GCN-NEXT: s_and_b32 s33, s33, 0xfffff000
; GCN-NEXT: s_addk_i32 s32, 0x2000 ; GCN-NEXT: s_addk_i32 s32, 0x2000
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_cbranch_execz BB3_2 ; GCN-NEXT: s_cbranch_execz .LBB3_2
; GCN-NEXT: ; %bb.1: ; %bb.0 ; GCN-NEXT: ; %bb.1: ; %bb.0
; GCN-NEXT: s_add_u32 s6, s32, 0x1000 ; GCN-NEXT: s_add_u32 s6, s32, 0x1000
; GCN-NEXT: s_and_b32 s6, s6, 0xfffff000 ; GCN-NEXT: s_and_b32 s6, s6, 0xfffff000
; GCN-NEXT: v_mov_b32_e32 v2, 0 ; GCN-NEXT: v_mov_b32_e32 v2, 0
; GCN-NEXT: v_mov_b32_e32 v5, s6 ; GCN-NEXT: v_mov_b32_e32 v5, s6
; GCN-NEXT: buffer_store_dword v2, v5, s[0:3], 0 offen ; GCN-NEXT: buffer_store_dword v2, v5, s[0:3], 0 offen
; GCN-NEXT: v_mov_b32_e32 v2, 1 ; GCN-NEXT: v_mov_b32_e32 v2, 1
; GCN-NEXT: buffer_store_dword v2, v5, s[0:3], 0 offen offset:4 ; GCN-NEXT: buffer_store_dword v2, v5, s[0:3], 0 offen offset:4
; GCN-NEXT: v_lshlrev_b32_e32 v2, 2, v3 ; GCN-NEXT: v_lshlrev_b32_e32 v2, 2, v3
; GCN-NEXT: v_add_u32_e32 v2, s6, v2 ; GCN-NEXT: v_add_u32_e32 v2, s6, v2
; GCN-NEXT: buffer_load_dword v2, v2, s[0:3], 0 offen ; GCN-NEXT: buffer_load_dword v2, v2, s[0:3], 0 offen
; GCN-NEXT: v_and_b32_e32 v3, 0x3ff, v4 ; GCN-NEXT: v_and_b32_e32 v3, 0x3ff, v4
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_add_u32_e32 v2, v2, v3 ; GCN-NEXT: v_add_u32_e32 v2, v2, v3
; GCN-NEXT: global_store_dword v[0:1], v2, off ; GCN-NEXT: global_store_dword v[0:1], v2, off
; GCN-NEXT: BB3_2: ; %bb.1 ; GCN-NEXT: .LBB3_2: ; %bb.1
; GCN-NEXT: s_or_b64 exec, exec, s[4:5] ; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: global_store_dword v[0:1], v0, off ; GCN-NEXT: global_store_dword v[0:1], v0, off
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_addk_i32 s32, 0xe000 ; GCN-NEXT: s_addk_i32 s32, 0xe000
; GCN-NEXT: s_mov_b32 s33, s7 ; GCN-NEXT: s_mov_b32 s33, s7
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
entry: entry:
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llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll

Show All 10 Lines
; CHECK-NEXT: v_mov_b32_e32 v5, v1 ; CHECK-NEXT: v_mov_b32_e32 v5, v1
; CHECK-NEXT: v_mov_b32_e32 v4, v0 ; CHECK-NEXT: v_mov_b32_e32 v4, v0
; CHECK-NEXT: v_or_b32_e32 v1, v5, v3 ; CHECK-NEXT: v_or_b32_e32 v1, v5, v3
; CHECK-NEXT: v_mov_b32_e32 v0, 0 ; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] ; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1 ; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[4:5] ; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CHECK-NEXT: s_cbranch_execz BB0_2 ; CHECK-NEXT: s_cbranch_execz .LBB0_2
; CHECK-NEXT: ; %bb.1: ; CHECK-NEXT: ; %bb.1:
; CHECK-NEXT: v_ashrrev_i32_e32 v0, 31, v3 ; CHECK-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; CHECK-NEXT: v_add_i32_e32 v1, vcc, v2, v0 ; CHECK-NEXT: v_add_i32_e32 v1, vcc, v2, v0
; CHECK-NEXT: v_addc_u32_e32 v2, vcc, v3, v0, vcc ; CHECK-NEXT: v_addc_u32_e32 v2, vcc, v3, v0, vcc
; CHECK-NEXT: v_xor_b32_e32 v1, v1, v0 ; CHECK-NEXT: v_xor_b32_e32 v1, v1, v0
; CHECK-NEXT: v_xor_b32_e32 v2, v2, v0 ; CHECK-NEXT: v_xor_b32_e32 v2, v2, v0
; CHECK-NEXT: v_cvt_f32_u32_e32 v3, v1 ; CHECK-NEXT: v_cvt_f32_u32_e32 v3, v1
; CHECK-NEXT: v_cvt_f32_u32_e32 v6, v2 ; CHECK-NEXT: v_cvt_f32_u32_e32 v6, v2
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; CHECK-NEXT: v_xor_b32_e32 v3, v7, v0 ; CHECK-NEXT: v_xor_b32_e32 v3, v7, v0
; CHECK-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
; CHECK-NEXT: v_xor_b32_e32 v0, v1, v3 ; CHECK-NEXT: v_xor_b32_e32 v0, v1, v3
; CHECK-NEXT: v_xor_b32_e32 v1, v2, v3 ; CHECK-NEXT: v_xor_b32_e32 v1, v2, v3
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v3 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
; CHECK-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc ; CHECK-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
; CHECK-NEXT: ; implicit-def: $vgpr2 ; CHECK-NEXT: ; implicit-def: $vgpr2
; CHECK-NEXT: ; implicit-def: $vgpr4 ; CHECK-NEXT: ; implicit-def: $vgpr4
; CHECK-NEXT: BB0_2: ; %Flow ; CHECK-NEXT: .LBB0_2: ; %Flow
; CHECK-NEXT: s_or_saveexec_b64 s[6:7], s[6:7] ; CHECK-NEXT: s_or_saveexec_b64 s[6:7], s[6:7]
; CHECK-NEXT: s_xor_b64 exec, exec, s[6:7] ; CHECK-NEXT: s_xor_b64 exec, exec, s[6:7]
; CHECK-NEXT: s_cbranch_execz BB0_4 ; CHECK-NEXT: s_cbranch_execz .LBB0_4
; CHECK-NEXT: ; %bb.3: ; CHECK-NEXT: ; %bb.3:
; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v2 ; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v2
; CHECK-NEXT: v_sub_i32_e32 v1, vcc, 0, v2 ; CHECK-NEXT: v_sub_i32_e32 v1, vcc, 0, v2
; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CHECK-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; CHECK-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0 ; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
; CHECK-NEXT: v_mul_lo_u32 v1, v1, v0 ; CHECK-NEXT: v_mul_lo_u32 v1, v1, v0
; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1 ; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; CHECK-NEXT: v_mul_hi_u32 v0, v4, v0 ; CHECK-NEXT: v_mul_hi_u32 v0, v4, v0
; CHECK-NEXT: v_mul_lo_u32 v1, v0, v2 ; CHECK-NEXT: v_mul_lo_u32 v1, v0, v2
; CHECK-NEXT: v_add_i32_e32 v3, vcc, 1, v0 ; CHECK-NEXT: v_add_i32_e32 v3, vcc, 1, v0
; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v4, v1 ; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v4, v1
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2 ; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; CHECK-NEXT: v_sub_i32_e64 v3, s[4:5], v1, v2 ; CHECK-NEXT: v_sub_i32_e64 v3, s[4:5], v1, v2
; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; CHECK-NEXT: v_add_i32_e32 v3, vcc, 1, v0 ; CHECK-NEXT: v_add_i32_e32 v3, vcc, 1, v0
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2 ; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; CHECK-NEXT: v_mov_b32_e32 v1, 0 ; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: BB0_4: ; CHECK-NEXT: .LBB0_4:
; CHECK-NEXT: s_or_b64 exec, exec, s[6:7] ; CHECK-NEXT: s_or_b64 exec, exec, s[6:7]
; CHECK-NEXT: s_setpc_b64 s[30:31] ; CHECK-NEXT: s_setpc_b64 s[30:31]
%result = sdiv i64 %num, %den %result = sdiv i64 %num, %den
ret i64 %result ret i64 %result
} }
; FIXME: This is a workaround for not handling uniform VGPR case. ; FIXME: This is a workaround for not handling uniform VGPR case.
declare i32 @llvm.amdgcn.readfirstlane(i32) declare i32 @llvm.amdgcn.readfirstlane(i32)
define amdgpu_ps i64 @s_sdiv_i64(i64 inreg %num, i64 inreg %den) { define amdgpu_ps i64 @s_sdiv_i64(i64 inreg %num, i64 inreg %den) {
; CHECK-LABEL: s_sdiv_i64: ; CHECK-LABEL: s_sdiv_i64:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: s_or_b64 s[6:7], s[2:3], s[4:5] ; CHECK-NEXT: s_or_b64 s[6:7], s[2:3], s[4:5]
; CHECK-NEXT: s_mov_b32 s0, 0 ; CHECK-NEXT: s_mov_b32 s0, 0
; CHECK-NEXT: s_mov_b32 s1, -1 ; CHECK-NEXT: s_mov_b32 s1, -1
; CHECK-NEXT: s_and_b64 s[6:7], s[6:7], s[0:1] ; CHECK-NEXT: s_and_b64 s[6:7], s[6:7], s[0:1]
; CHECK-NEXT: v_cmp_ne_u64_e64 vcc, s[6:7], 0 ; CHECK-NEXT: v_cmp_ne_u64_e64 vcc, s[6:7], 0
; CHECK-NEXT: s_cbranch_vccz BB1_2 ; CHECK-NEXT: s_cbranch_vccz .LBB1_2
; CHECK-NEXT: ; %bb.1: ; CHECK-NEXT: ; %bb.1:
; CHECK-NEXT: s_ashr_i32 s6, s3, 31 ; CHECK-NEXT: s_ashr_i32 s6, s3, 31
; CHECK-NEXT: s_ashr_i32 s8, s5, 31 ; CHECK-NEXT: s_ashr_i32 s8, s5, 31
; CHECK-NEXT: s_add_u32 s0, s2, s6 ; CHECK-NEXT: s_add_u32 s0, s2, s6
; CHECK-NEXT: s_cselect_b32 s1, 1, 0 ; CHECK-NEXT: s_cselect_b32 s1, 1, 0
; CHECK-NEXT: s_and_b32 s1, s1, 1 ; CHECK-NEXT: s_and_b32 s1, s1, 1
; CHECK-NEXT: s_cmp_lg_u32 s1, 0 ; CHECK-NEXT: s_cmp_lg_u32 s1, 0
; CHECK-NEXT: s_addc_u32 s1, s3, s6 ; CHECK-NEXT: s_addc_u32 s1, s3, s6
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; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
; CHECK-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; CHECK-NEXT: s_xor_b64 s[0:1], s[6:7], s[8:9] ; CHECK-NEXT: s_xor_b64 s[0:1], s[6:7], s[8:9]
; CHECK-NEXT: v_xor_b32_e32 v0, s0, v0 ; CHECK-NEXT: v_xor_b32_e32 v0, s0, v0
; CHECK-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0 ; CHECK-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
; CHECK-NEXT: s_mov_b32 s1, 0 ; CHECK-NEXT: s_mov_b32 s1, 0
; CHECK-NEXT: s_branch BB1_3 ; CHECK-NEXT: s_branch .LBB1_3
; CHECK-NEXT: BB1_2: ; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1 ; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
; CHECK-NEXT: BB1_3: ; %Flow ; CHECK-NEXT: .LBB1_3: ; %Flow
; CHECK-NEXT: s_xor_b32 s0, s1, -1 ; CHECK-NEXT: s_xor_b32 s0, s1, -1
; CHECK-NEXT: s_and_b32 s0, s0, 1 ; CHECK-NEXT: s_and_b32 s0, s0, 1
; CHECK-NEXT: s_cmp_lg_u32 s0, 0 ; CHECK-NEXT: s_cmp_lg_u32 s0, 0
; CHECK-NEXT: s_cbranch_scc1 BB1_5 ; CHECK-NEXT: s_cbranch_scc1 .LBB1_5
; CHECK-NEXT: ; %bb.4: ; CHECK-NEXT: ; %bb.4:
; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s4 ; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s4
; CHECK-NEXT: s_sub_i32 s0, 0, s4 ; CHECK-NEXT: s_sub_i32 s0, 0, s4
; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CHECK-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; CHECK-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0 ; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
; CHECK-NEXT: v_mul_lo_u32 v1, s0, v0 ; CHECK-NEXT: v_mul_lo_u32 v1, s0, v0
; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1 ; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; CHECK-NEXT: v_mul_hi_u32 v0, s2, v0 ; CHECK-NEXT: v_mul_hi_u32 v0, s2, v0
; CHECK-NEXT: v_mul_lo_u32 v1, v0, s4 ; CHECK-NEXT: v_mul_lo_u32 v1, v0, s4
; CHECK-NEXT: v_add_i32_e32 v2, vcc, 1, v0 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, 1, v0
; CHECK-NEXT: v_sub_i32_e32 v1, vcc, s2, v1 ; CHECK-NEXT: v_sub_i32_e32 v1, vcc, s2, v1
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v1 ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v1
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CHECK-NEXT: v_subrev_i32_e64 v2, s[0:1], s4, v1 ; CHECK-NEXT: v_subrev_i32_e64 v2, s[0:1], s4, v1
; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; CHECK-NEXT: v_add_i32_e32 v2, vcc, 1, v0 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, 1, v0
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v1 ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v1
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CHECK-NEXT: BB1_5: ; CHECK-NEXT: .LBB1_5:
; CHECK-NEXT: v_readfirstlane_b32 s0, v0 ; CHECK-NEXT: v_readfirstlane_b32 s0, v0
; CHECK-NEXT: s_mov_b32 s1, s0 ; CHECK-NEXT: s_mov_b32 s1, s0
; CHECK-NEXT: ; return to shader part epilog ; CHECK-NEXT: ; return to shader part epilog
%result = sdiv i64 %num, %den %result = sdiv i64 %num, %den
%cast = bitcast i64 %result to <2 x i32> %cast = bitcast i64 %result to <2 x i32>
%elt.0 = extractelement <2 x i32> %cast, i32 0 %elt.0 = extractelement <2 x i32> %cast, i32 0
%elt.1 = extractelement <2 x i32> %cast, i32 1 %elt.1 = extractelement <2 x i32> %cast, i32 1
%res.0 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt.0) %res.0 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt.0)
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; CGP-NEXT: v_or_b32_e32 v1, v11, v5 ; CGP-NEXT: v_or_b32_e32 v1, v11, v5
; CGP-NEXT: v_mov_b32_e32 v0, 0 ; CGP-NEXT: v_mov_b32_e32 v0, 0
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] ; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; CGP-NEXT: v_mov_b32_e32 v8, v2 ; CGP-NEXT: v_mov_b32_e32 v8, v2
; CGP-NEXT: v_mov_b32_e32 v9, v3 ; CGP-NEXT: v_mov_b32_e32 v9, v3
; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1 ; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5] ; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CGP-NEXT: s_cbranch_execz BB2_2 ; CGP-NEXT: s_cbranch_execz .LBB2_2
; CGP-NEXT: ; %bb.1: ; CGP-NEXT: ; %bb.1:
; CGP-NEXT: v_ashrrev_i32_e32 v0, 31, v5 ; CGP-NEXT: v_ashrrev_i32_e32 v0, 31, v5
; CGP-NEXT: v_add_i32_e32 v1, vcc, v4, v0 ; CGP-NEXT: v_add_i32_e32 v1, vcc, v4, v0
; CGP-NEXT: v_addc_u32_e32 v2, vcc, v5, v0, vcc ; CGP-NEXT: v_addc_u32_e32 v2, vcc, v5, v0, vcc
; CGP-NEXT: v_xor_b32_e32 v1, v1, v0 ; CGP-NEXT: v_xor_b32_e32 v1, v1, v0
; CGP-NEXT: v_xor_b32_e32 v2, v2, v0 ; CGP-NEXT: v_xor_b32_e32 v2, v2, v0
; CGP-NEXT: v_cvt_f32_u32_e32 v3, v1 ; CGP-NEXT: v_cvt_f32_u32_e32 v3, v1
; CGP-NEXT: v_cvt_f32_u32_e32 v4, v2 ; CGP-NEXT: v_cvt_f32_u32_e32 v4, v2
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; CGP-NEXT: v_xor_b32_e32 v3, v5, v0 ; CGP-NEXT: v_xor_b32_e32 v3, v5, v0
; CGP-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc
; CGP-NEXT: v_xor_b32_e32 v0, v1, v3 ; CGP-NEXT: v_xor_b32_e32 v0, v1, v3
; CGP-NEXT: v_xor_b32_e32 v1, v2, v3 ; CGP-NEXT: v_xor_b32_e32 v1, v2, v3
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v3 ; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
; CGP-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc ; CGP-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
; CGP-NEXT: ; implicit-def: $vgpr4 ; CGP-NEXT: ; implicit-def: $vgpr4
; CGP-NEXT: ; implicit-def: $vgpr10 ; CGP-NEXT: ; implicit-def: $vgpr10
; CGP-NEXT: BB2_2: ; %Flow2 ; CGP-NEXT: .LBB2_2: ; %Flow2
; CGP-NEXT: s_or_saveexec_b64 s[6:7], s[6:7] ; CGP-NEXT: s_or_saveexec_b64 s[6:7], s[6:7]
; CGP-NEXT: s_xor_b64 exec, exec, s[6:7] ; CGP-NEXT: s_xor_b64 exec, exec, s[6:7]
; CGP-NEXT: s_cbranch_execz BB2_4 ; CGP-NEXT: s_cbranch_execz .LBB2_4
; CGP-NEXT: ; %bb.3: ; CGP-NEXT: ; %bb.3:
; CGP-NEXT: v_cvt_f32_u32_e32 v0, v4 ; CGP-NEXT: v_cvt_f32_u32_e32 v0, v4
; CGP-NEXT: v_sub_i32_e32 v1, vcc, 0, v4 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, 0, v4
; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CGP-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; CGP-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; CGP-NEXT: v_cvt_u32_f32_e32 v0, v0 ; CGP-NEXT: v_cvt_u32_f32_e32 v0, v0
; CGP-NEXT: v_mul_lo_u32 v1, v1, v0 ; CGP-NEXT: v_mul_lo_u32 v1, v1, v0
; CGP-NEXT: v_mul_hi_u32 v1, v0, v1 ; CGP-NEXT: v_mul_hi_u32 v1, v0, v1
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; CGP-NEXT: v_mul_hi_u32 v0, v10, v0 ; CGP-NEXT: v_mul_hi_u32 v0, v10, v0
; CGP-NEXT: v_mul_lo_u32 v1, v0, v4 ; CGP-NEXT: v_mul_lo_u32 v1, v0, v4
; CGP-NEXT: v_add_i32_e32 v2, vcc, 1, v0 ; CGP-NEXT: v_add_i32_e32 v2, vcc, 1, v0
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v10, v1 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, v10, v1
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v4 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v4
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CGP-NEXT: v_sub_i32_e64 v2, s[4:5], v1, v4 ; CGP-NEXT: v_sub_i32_e64 v2, s[4:5], v1, v4
; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; CGP-NEXT: v_add_i32_e32 v2, vcc, 1, v0 ; CGP-NEXT: v_add_i32_e32 v2, vcc, 1, v0
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v4 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v4
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CGP-NEXT: v_mov_b32_e32 v1, 0 ; CGP-NEXT: v_mov_b32_e32 v1, 0
; CGP-NEXT: BB2_4: ; CGP-NEXT: .LBB2_4:
; CGP-NEXT: s_or_b64 exec, exec, s[6:7] ; CGP-NEXT: s_or_b64 exec, exec, s[6:7]
; CGP-NEXT: v_or_b32_e32 v3, v9, v7 ; CGP-NEXT: v_or_b32_e32 v3, v9, v7
; CGP-NEXT: v_mov_b32_e32 v2, 0 ; CGP-NEXT: v_mov_b32_e32 v2, 0
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3] ; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3 ; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5] ; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CGP-NEXT: s_cbranch_execz BB2_6 ; CGP-NEXT: s_cbranch_execz .LBB2_6
; CGP-NEXT: ; %bb.5: ; CGP-NEXT: ; %bb.5:
; CGP-NEXT: v_ashrrev_i32_e32 v2, 31, v7 ; CGP-NEXT: v_ashrrev_i32_e32 v2, 31, v7
; CGP-NEXT: v_add_i32_e32 v3, vcc, v6, v2 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v6, v2
; CGP-NEXT: v_addc_u32_e32 v4, vcc, v7, v2, vcc ; CGP-NEXT: v_addc_u32_e32 v4, vcc, v7, v2, vcc
; CGP-NEXT: v_xor_b32_e32 v3, v3, v2 ; CGP-NEXT: v_xor_b32_e32 v3, v3, v2
; CGP-NEXT: v_xor_b32_e32 v4, v4, v2 ; CGP-NEXT: v_xor_b32_e32 v4, v4, v2
; CGP-NEXT: v_cvt_f32_u32_e32 v5, v3 ; CGP-NEXT: v_cvt_f32_u32_e32 v5, v3
; CGP-NEXT: v_cvt_f32_u32_e32 v6, v4 ; CGP-NEXT: v_cvt_f32_u32_e32 v6, v4
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; CGP-NEXT: v_xor_b32_e32 v5, v7, v2 ; CGP-NEXT: v_xor_b32_e32 v5, v7, v2
; CGP-NEXT: v_cndmask_b32_e32 v4, v9, v4, vcc ; CGP-NEXT: v_cndmask_b32_e32 v4, v9, v4, vcc
; CGP-NEXT: v_xor_b32_e32 v2, v3, v5 ; CGP-NEXT: v_xor_b32_e32 v2, v3, v5
; CGP-NEXT: v_xor_b32_e32 v3, v4, v5 ; CGP-NEXT: v_xor_b32_e32 v3, v4, v5
; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v5 ; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v5
; CGP-NEXT: v_subb_u32_e32 v3, vcc, v3, v5, vcc ; CGP-NEXT: v_subb_u32_e32 v3, vcc, v3, v5, vcc
; CGP-NEXT: ; implicit-def: $vgpr6 ; CGP-NEXT: ; implicit-def: $vgpr6
; CGP-NEXT: ; implicit-def: $vgpr8 ; CGP-NEXT: ; implicit-def: $vgpr8
; CGP-NEXT: BB2_6: ; %Flow ; CGP-NEXT: .LBB2_6: ; %Flow
; CGP-NEXT: s_or_saveexec_b64 s[6:7], s[6:7] ; CGP-NEXT: s_or_saveexec_b64 s[6:7], s[6:7]
; CGP-NEXT: s_xor_b64 exec, exec, s[6:7] ; CGP-NEXT: s_xor_b64 exec, exec, s[6:7]
; CGP-NEXT: s_cbranch_execz BB2_8 ; CGP-NEXT: s_cbranch_execz .LBB2_8
; CGP-NEXT: ; %bb.7: ; CGP-NEXT: ; %bb.7:
; CGP-NEXT: v_cvt_f32_u32_e32 v2, v6 ; CGP-NEXT: v_cvt_f32_u32_e32 v2, v6
; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v6 ; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v6
; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2 ; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2 ; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2
; CGP-NEXT: v_mul_lo_u32 v3, v3, v2 ; CGP-NEXT: v_mul_lo_u32 v3, v3, v2
; CGP-NEXT: v_mul_hi_u32 v3, v2, v3 ; CGP-NEXT: v_mul_hi_u32 v3, v2, v3
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; CGP-NEXT: v_mul_hi_u32 v2, v8, v2 ; CGP-NEXT: v_mul_hi_u32 v2, v8, v2
; CGP-NEXT: v_mul_lo_u32 v3, v2, v6 ; CGP-NEXT: v_mul_lo_u32 v3, v2, v6
; CGP-NEXT: v_add_i32_e32 v4, vcc, 1, v2 ; CGP-NEXT: v_add_i32_e32 v4, vcc, 1, v2
; CGP-NEXT: v_sub_i32_e32 v3, vcc, v8, v3 ; CGP-NEXT: v_sub_i32_e32 v3, vcc, v8, v3
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v3, v6 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v3, v6
; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; CGP-NEXT: v_sub_i32_e64 v4, s[4:5], v3, v6 ; CGP-NEXT: v_sub_i32_e64 v4, s[4:5], v3, v6
; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; CGP-NEXT: v_add_i32_e32 v4, vcc, 1, v2 ; CGP-NEXT: v_add_i32_e32 v4, vcc, 1, v2
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v3, v6 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v3, v6
; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; CGP-NEXT: v_mov_b32_e32 v3, 0 ; CGP-NEXT: v_mov_b32_e32 v3, 0
; CGP-NEXT: BB2_8: ; CGP-NEXT: .LBB2_8:
; CGP-NEXT: s_or_b64 exec, exec, s[6:7] ; CGP-NEXT: s_or_b64 exec, exec, s[6:7]
; CGP-NEXT: s_setpc_b64 s[30:31] ; CGP-NEXT: s_setpc_b64 s[30:31]
%result = sdiv <2 x i64> %num, %den %result = sdiv <2 x i64> %num, %den
ret <2 x i64> %result ret <2 x i64> %result
} }
define i64 @v_sdiv_i64_pow2k_denom(i64 %num) { define i64 @v_sdiv_i64_pow2k_denom(i64 %num) {
; CHECK-LABEL: v_sdiv_i64_pow2k_denom: ; CHECK-LABEL: v_sdiv_i64_pow2k_denom:
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; CHECK-NEXT: v_mov_b32_e32 v4, v1 ; CHECK-NEXT: v_mov_b32_e32 v4, v1
; CHECK-NEXT: v_mov_b32_e32 v3, v0 ; CHECK-NEXT: v_mov_b32_e32 v3, v0
; CHECK-NEXT: v_or_b32_e32 v1, v4, v6 ; CHECK-NEXT: v_or_b32_e32 v1, v4, v6
; CHECK-NEXT: v_mov_b32_e32 v0, 0 ; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] ; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1 ; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[4:5] ; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CHECK-NEXT: s_cbranch_execz BB7_2 ; CHECK-NEXT: s_cbranch_execz .LBB7_2
; CHECK-NEXT: ; %bb.1: ; CHECK-NEXT: ; %bb.1:
; CHECK-NEXT: v_ashrrev_i32_e32 v0, 31, v6 ; CHECK-NEXT: v_ashrrev_i32_e32 v0, 31, v6
; CHECK-NEXT: v_add_i32_e32 v1, vcc, v5, v0 ; CHECK-NEXT: v_add_i32_e32 v1, vcc, v5, v0
; CHECK-NEXT: v_addc_u32_e32 v2, vcc, v6, v0, vcc ; CHECK-NEXT: v_addc_u32_e32 v2, vcc, v6, v0, vcc
; CHECK-NEXT: v_xor_b32_e32 v1, v1, v0 ; CHECK-NEXT: v_xor_b32_e32 v1, v1, v0
; CHECK-NEXT: v_xor_b32_e32 v2, v2, v0 ; CHECK-NEXT: v_xor_b32_e32 v2, v2, v0
; CHECK-NEXT: v_cvt_f32_u32_e32 v5, v1 ; CHECK-NEXT: v_cvt_f32_u32_e32 v5, v1
; CHECK-NEXT: v_cvt_f32_u32_e32 v6, v2 ; CHECK-NEXT: v_cvt_f32_u32_e32 v6, v2
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; CHECK-NEXT: v_xor_b32_e32 v3, v7, v0 ; CHECK-NEXT: v_xor_b32_e32 v3, v7, v0
; CHECK-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
; CHECK-NEXT: v_xor_b32_e32 v0, v1, v3 ; CHECK-NEXT: v_xor_b32_e32 v0, v1, v3
; CHECK-NEXT: v_xor_b32_e32 v1, v2, v3 ; CHECK-NEXT: v_xor_b32_e32 v1, v2, v3
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v3 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
; CHECK-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc ; CHECK-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
; CHECK-NEXT: ; implicit-def: $vgpr5_vgpr6 ; CHECK-NEXT: ; implicit-def: $vgpr5_vgpr6
; CHECK-NEXT: ; implicit-def: $vgpr3 ; CHECK-NEXT: ; implicit-def: $vgpr3
; CHECK-NEXT: BB7_2: ; %Flow ; CHECK-NEXT: .LBB7_2: ; %Flow
; CHECK-NEXT: s_or_saveexec_b64 s[6:7], s[6:7] ; CHECK-NEXT: s_or_saveexec_b64 s[6:7], s[6:7]
; CHECK-NEXT: s_xor_b64 exec, exec, s[6:7] ; CHECK-NEXT: s_xor_b64 exec, exec, s[6:7]
; CHECK-NEXT: s_cbranch_execz BB7_4 ; CHECK-NEXT: s_cbranch_execz .LBB7_4
; CHECK-NEXT: ; %bb.3: ; CHECK-NEXT: ; %bb.3:
; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v5 ; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v5
; CHECK-NEXT: v_sub_i32_e32 v1, vcc, 0, v5 ; CHECK-NEXT: v_sub_i32_e32 v1, vcc, 0, v5
; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CHECK-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; CHECK-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0 ; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
; CHECK-NEXT: v_mul_lo_u32 v1, v1, v0 ; CHECK-NEXT: v_mul_lo_u32 v1, v1, v0
; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1 ; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; CHECK-NEXT: v_mul_hi_u32 v0, v3, v0 ; CHECK-NEXT: v_mul_hi_u32 v0, v3, v0
; CHECK-NEXT: v_mul_lo_u32 v1, v0, v5 ; CHECK-NEXT: v_mul_lo_u32 v1, v0, v5
; CHECK-NEXT: v_add_i32_e32 v2, vcc, 1, v0 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, 1, v0
; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v3, v1 ; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v3, v1
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v1, v5 ; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v1, v5
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CHECK-NEXT: v_sub_i32_e64 v2, s[4:5], v1, v5 ; CHECK-NEXT: v_sub_i32_e64 v2, s[4:5], v1, v5
; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; CHECK-NEXT: v_add_i32_e32 v2, vcc, 1, v0 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, 1, v0
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v1, v5 ; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v1, v5
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CHECK-NEXT: v_mov_b32_e32 v1, 0 ; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: BB7_4: ; CHECK-NEXT: .LBB7_4:
; CHECK-NEXT: s_or_b64 exec, exec, s[6:7] ; CHECK-NEXT: s_or_b64 exec, exec, s[6:7]
; CHECK-NEXT: s_setpc_b64 s[30:31] ; CHECK-NEXT: s_setpc_b64 s[30:31]
%shl.y = shl i64 4096, %y %shl.y = shl i64 4096, %y
%r = sdiv i64 %x, %shl.y %r = sdiv i64 %x, %shl.y
ret i64 %r ret i64 %r
} }
define <2 x i64> @v_sdiv_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) { define <2 x i64> @v_sdiv_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
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; CGP-NEXT: v_mov_b32_e32 v8, v0 ; CGP-NEXT: v_mov_b32_e32 v8, v0
; CGP-NEXT: v_or_b32_e32 v1, v9, v3 ; CGP-NEXT: v_or_b32_e32 v1, v9, v3
; CGP-NEXT: v_mov_b32_e32 v0, 0 ; CGP-NEXT: v_mov_b32_e32 v0, 0
; CGP-NEXT: v_lshl_b64 v[10:11], s[4:5], v6 ; CGP-NEXT: v_lshl_b64 v[10:11], s[4:5], v6
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] ; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1 ; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5] ; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CGP-NEXT: s_cbranch_execz BB8_2 ; CGP-NEXT: s_cbranch_execz .LBB8_2
; CGP-NEXT: ; %bb.1: ; CGP-NEXT: ; %bb.1:
; CGP-NEXT: v_ashrrev_i32_e32 v0, 31, v3 ; CGP-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; CGP-NEXT: v_add_i32_e32 v1, vcc, v2, v0 ; CGP-NEXT: v_add_i32_e32 v1, vcc, v2, v0
; CGP-NEXT: v_addc_u32_e32 v2, vcc, v3, v0, vcc ; CGP-NEXT: v_addc_u32_e32 v2, vcc, v3, v0, vcc
; CGP-NEXT: v_xor_b32_e32 v1, v1, v0 ; CGP-NEXT: v_xor_b32_e32 v1, v1, v0
; CGP-NEXT: v_xor_b32_e32 v2, v2, v0 ; CGP-NEXT: v_xor_b32_e32 v2, v2, v0
; CGP-NEXT: v_cvt_f32_u32_e32 v3, v1 ; CGP-NEXT: v_cvt_f32_u32_e32 v3, v1
; CGP-NEXT: v_cvt_f32_u32_e32 v4, v2 ; CGP-NEXT: v_cvt_f32_u32_e32 v4, v2
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; CGP-NEXT: v_xor_b32_e32 v3, v6, v0 ; CGP-NEXT: v_xor_b32_e32 v3, v6, v0
; CGP-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc
; CGP-NEXT: v_xor_b32_e32 v0, v1, v3 ; CGP-NEXT: v_xor_b32_e32 v0, v1, v3
; CGP-NEXT: v_xor_b32_e32 v1, v2, v3 ; CGP-NEXT: v_xor_b32_e32 v1, v2, v3
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v3 ; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
; CGP-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc ; CGP-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3 ; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3
; CGP-NEXT: ; implicit-def: $vgpr8 ; CGP-NEXT: ; implicit-def: $vgpr8
; CGP-NEXT: BB8_2: ; %Flow2 ; CGP-NEXT: .LBB8_2: ; %Flow2
; CGP-NEXT: s_or_saveexec_b64 s[6:7], s[6:7] ; CGP-NEXT: s_or_saveexec_b64 s[6:7], s[6:7]
; CGP-NEXT: s_xor_b64 exec, exec, s[6:7] ; CGP-NEXT: s_xor_b64 exec, exec, s[6:7]
; CGP-NEXT: s_cbranch_execz BB8_4 ; CGP-NEXT: s_cbranch_execz .LBB8_4
; CGP-NEXT: ; %bb.3: ; CGP-NEXT: ; %bb.3:
; CGP-NEXT: v_cvt_f32_u32_e32 v0, v2 ; CGP-NEXT: v_cvt_f32_u32_e32 v0, v2
; CGP-NEXT: v_sub_i32_e32 v1, vcc, 0, v2 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, 0, v2
; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CGP-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; CGP-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; CGP-NEXT: v_cvt_u32_f32_e32 v0, v0 ; CGP-NEXT: v_cvt_u32_f32_e32 v0, v0
; CGP-NEXT: v_mul_lo_u32 v1, v1, v0 ; CGP-NEXT: v_mul_lo_u32 v1, v1, v0
; CGP-NEXT: v_mul_hi_u32 v1, v0, v1 ; CGP-NEXT: v_mul_hi_u32 v1, v0, v1
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; CGP-NEXT: v_mul_hi_u32 v0, v8, v0 ; CGP-NEXT: v_mul_hi_u32 v0, v8, v0
; CGP-NEXT: v_mul_lo_u32 v1, v0, v2 ; CGP-NEXT: v_mul_lo_u32 v1, v0, v2
; CGP-NEXT: v_add_i32_e32 v3, vcc, 1, v0 ; CGP-NEXT: v_add_i32_e32 v3, vcc, 1, v0
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v8, v1 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, v8, v1
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v1, v2 ; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v1, v2
; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; CGP-NEXT: v_add_i32_e32 v3, vcc, 1, v0 ; CGP-NEXT: v_add_i32_e32 v3, vcc, 1, v0
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; CGP-NEXT: v_mov_b32_e32 v1, 0 ; CGP-NEXT: v_mov_b32_e32 v1, 0
; CGP-NEXT: BB8_4: ; CGP-NEXT: .LBB8_4:
; CGP-NEXT: s_or_b64 exec, exec, s[6:7] ; CGP-NEXT: s_or_b64 exec, exec, s[6:7]
; CGP-NEXT: v_or_b32_e32 v3, v7, v11 ; CGP-NEXT: v_or_b32_e32 v3, v7, v11
; CGP-NEXT: v_mov_b32_e32 v2, 0 ; CGP-NEXT: v_mov_b32_e32 v2, 0
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3] ; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3 ; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5] ; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CGP-NEXT: s_cbranch_execz BB8_6 ; CGP-NEXT: s_cbranch_execz .LBB8_6
; CGP-NEXT: ; %bb.5: ; CGP-NEXT: ; %bb.5:
; CGP-NEXT: v_ashrrev_i32_e32 v2, 31, v11 ; CGP-NEXT: v_ashrrev_i32_e32 v2, 31, v11
; CGP-NEXT: v_add_i32_e32 v3, vcc, v10, v2 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v10, v2
; CGP-NEXT: v_addc_u32_e32 v4, vcc, v11, v2, vcc ; CGP-NEXT: v_addc_u32_e32 v4, vcc, v11, v2, vcc
; CGP-NEXT: v_xor_b32_e32 v3, v3, v2 ; CGP-NEXT: v_xor_b32_e32 v3, v3, v2
; CGP-NEXT: v_xor_b32_e32 v4, v4, v2 ; CGP-NEXT: v_xor_b32_e32 v4, v4, v2
; CGP-NEXT: v_cvt_f32_u32_e32 v6, v3 ; CGP-NEXT: v_cvt_f32_u32_e32 v6, v3
; CGP-NEXT: v_cvt_f32_u32_e32 v8, v4 ; CGP-NEXT: v_cvt_f32_u32_e32 v8, v4
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; CGP-NEXT: v_xor_b32_e32 v5, v9, v2 ; CGP-NEXT: v_xor_b32_e32 v5, v9, v2
; CGP-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc ; CGP-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc
; CGP-NEXT: v_xor_b32_e32 v2, v3, v5 ; CGP-NEXT: v_xor_b32_e32 v2, v3, v5
; CGP-NEXT: v_xor_b32_e32 v3, v4, v5 ; CGP-NEXT: v_xor_b32_e32 v3, v4, v5
; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v5 ; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v5
; CGP-NEXT: v_subb_u32_e32 v3, vcc, v3, v5, vcc ; CGP-NEXT: v_subb_u32_e32 v3, vcc, v3, v5, vcc
; CGP-NEXT: ; implicit-def: $vgpr10_vgpr11 ; CGP-NEXT: ; implicit-def: $vgpr10_vgpr11
; CGP-NEXT: ; implicit-def: $vgpr5 ; CGP-NEXT: ; implicit-def: $vgpr5
; CGP-NEXT: BB8_6: ; %Flow ; CGP-NEXT: .LBB8_6: ; %Flow
; CGP-NEXT: s_or_saveexec_b64 s[6:7], s[6:7] ; CGP-NEXT: s_or_saveexec_b64 s[6:7], s[6:7]
; CGP-NEXT: s_xor_b64 exec, exec, s[6:7] ; CGP-NEXT: s_xor_b64 exec, exec, s[6:7]
; CGP-NEXT: s_cbranch_execz BB8_8 ; CGP-NEXT: s_cbranch_execz .LBB8_8
; CGP-NEXT: ; %bb.7: ; CGP-NEXT: ; %bb.7:
; CGP-NEXT: v_cvt_f32_u32_e32 v2, v10 ; CGP-NEXT: v_cvt_f32_u32_e32 v2, v10
; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v10 ; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v10
; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2 ; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2 ; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2
; CGP-NEXT: v_mul_lo_u32 v3, v3, v2 ; CGP-NEXT: v_mul_lo_u32 v3, v3, v2
; CGP-NEXT: v_mul_hi_u32 v3, v2, v3 ; CGP-NEXT: v_mul_hi_u32 v3, v2, v3
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; CGP-NEXT: v_mul_hi_u32 v2, v5, v2 ; CGP-NEXT: v_mul_hi_u32 v2, v5, v2
; CGP-NEXT: v_mul_lo_u32 v3, v2, v10 ; CGP-NEXT: v_mul_lo_u32 v3, v2, v10
; CGP-NEXT: v_add_i32_e32 v4, vcc, 1, v2 ; CGP-NEXT: v_add_i32_e32 v4, vcc, 1, v2
; CGP-NEXT: v_sub_i32_e32 v3, vcc, v5, v3 ; CGP-NEXT: v_sub_i32_e32 v3, vcc, v5, v3
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v3, v10 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v3, v10
; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; CGP-NEXT: v_sub_i32_e64 v4, s[4:5], v3, v10 ; CGP-NEXT: v_sub_i32_e64 v4, s[4:5], v3, v10
; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; CGP-NEXT: v_add_i32_e32 v4, vcc, 1, v2 ; CGP-NEXT: v_add_i32_e32 v4, vcc, 1, v2
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v3, v10 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v3, v10
; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; CGP-NEXT: v_mov_b32_e32 v3, 0 ; CGP-NEXT: v_mov_b32_e32 v3, 0
; CGP-NEXT: BB8_8: ; CGP-NEXT: .LBB8_8:
; CGP-NEXT: s_or_b64 exec, exec, s[6:7] ; CGP-NEXT: s_or_b64 exec, exec, s[6:7]
; CGP-NEXT: s_setpc_b64 s[30:31] ; CGP-NEXT: s_setpc_b64 s[30:31]
%shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y %shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
%r = sdiv <2 x i64> %x, %shl.y %r = sdiv <2 x i64> %x, %shl.y
ret <2 x i64> %r ret <2 x i64> %r
} }
define i64 @v_sdiv_i64_24bit(i64 %num, i64 %den) { define i64 @v_sdiv_i64_24bit(i64 %num, i64 %den) {
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llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll

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; CHECK-NEXT: v_mov_b32_e32 v5, v1 ; CHECK-NEXT: v_mov_b32_e32 v5, v1
; CHECK-NEXT: v_mov_b32_e32 v4, v0 ; CHECK-NEXT: v_mov_b32_e32 v4, v0
; CHECK-NEXT: v_or_b32_e32 v1, v5, v3 ; CHECK-NEXT: v_or_b32_e32 v1, v5, v3
; CHECK-NEXT: v_mov_b32_e32 v0, 0 ; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] ; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1 ; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[4:5] ; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CHECK-NEXT: s_cbranch_execz BB0_2 ; CHECK-NEXT: s_cbranch_execz .LBB0_2
; CHECK-NEXT: ; %bb.1: ; CHECK-NEXT: ; %bb.1:
; CHECK-NEXT: v_ashrrev_i32_e32 v0, 31, v3 ; CHECK-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; CHECK-NEXT: v_add_i32_e32 v1, vcc, v2, v0 ; CHECK-NEXT: v_add_i32_e32 v1, vcc, v2, v0
; CHECK-NEXT: v_addc_u32_e32 v2, vcc, v3, v0, vcc ; CHECK-NEXT: v_addc_u32_e32 v2, vcc, v3, v0, vcc
; CHECK-NEXT: v_xor_b32_e32 v1, v1, v0 ; CHECK-NEXT: v_xor_b32_e32 v1, v1, v0
; CHECK-NEXT: v_xor_b32_e32 v0, v2, v0 ; CHECK-NEXT: v_xor_b32_e32 v0, v2, v0
; CHECK-NEXT: v_cvt_f32_u32_e32 v2, v1 ; CHECK-NEXT: v_cvt_f32_u32_e32 v2, v1
; CHECK-NEXT: v_cvt_f32_u32_e32 v3, v0 ; CHECK-NEXT: v_cvt_f32_u32_e32 v3, v0
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; CHECK-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; CHECK-NEXT: v_xor_b32_e32 v1, v1, v6 ; CHECK-NEXT: v_xor_b32_e32 v1, v1, v6
; CHECK-NEXT: v_xor_b32_e32 v2, v0, v6 ; CHECK-NEXT: v_xor_b32_e32 v2, v0, v6
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v1, v6 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v1, v6
; CHECK-NEXT: v_subb_u32_e32 v1, vcc, v2, v6, vcc ; CHECK-NEXT: v_subb_u32_e32 v1, vcc, v2, v6, vcc
; CHECK-NEXT: ; implicit-def: $vgpr2 ; CHECK-NEXT: ; implicit-def: $vgpr2
; CHECK-NEXT: ; implicit-def: $vgpr4 ; CHECK-NEXT: ; implicit-def: $vgpr4
; CHECK-NEXT: BB0_2: ; %Flow ; CHECK-NEXT: .LBB0_2: ; %Flow
; CHECK-NEXT: s_or_saveexec_b64 s[4:5], s[6:7] ; CHECK-NEXT: s_or_saveexec_b64 s[4:5], s[6:7]
; CHECK-NEXT: s_xor_b64 exec, exec, s[4:5] ; CHECK-NEXT: s_xor_b64 exec, exec, s[4:5]
; CHECK-NEXT: s_cbranch_execz BB0_4 ; CHECK-NEXT: s_cbranch_execz .LBB0_4
; CHECK-NEXT: ; %bb.3: ; CHECK-NEXT: ; %bb.3:
; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v2 ; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v2
; CHECK-NEXT: v_sub_i32_e32 v1, vcc, 0, v2 ; CHECK-NEXT: v_sub_i32_e32 v1, vcc, 0, v2
; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CHECK-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; CHECK-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0 ; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
; CHECK-NEXT: v_mul_lo_u32 v1, v1, v0 ; CHECK-NEXT: v_mul_lo_u32 v1, v1, v0
; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1 ; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; CHECK-NEXT: v_mul_hi_u32 v0, v4, v0 ; CHECK-NEXT: v_mul_hi_u32 v0, v4, v0
; CHECK-NEXT: v_mul_lo_u32 v0, v0, v2 ; CHECK-NEXT: v_mul_lo_u32 v0, v0, v2
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v4, v0 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v4, v0
; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v0, v2 ; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v0, v2
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 ; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v0, v2 ; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v0, v2
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 ; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; CHECK-NEXT: v_mov_b32_e32 v1, 0 ; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: BB0_4: ; CHECK-NEXT: .LBB0_4:
; CHECK-NEXT: s_or_b64 exec, exec, s[4:5] ; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
; CHECK-NEXT: s_setpc_b64 s[30:31] ; CHECK-NEXT: s_setpc_b64 s[30:31]
%result = srem i64 %num, %den %result = srem i64 %num, %den
ret i64 %result ret i64 %result
} }
; FIXME: This is a workaround for not handling uniform VGPR case. ; FIXME: This is a workaround for not handling uniform VGPR case.
declare i32 @llvm.amdgcn.readfirstlane(i32) declare i32 @llvm.amdgcn.readfirstlane(i32)
define amdgpu_ps i64 @s_srem_i64(i64 inreg %num, i64 inreg %den) { define amdgpu_ps i64 @s_srem_i64(i64 inreg %num, i64 inreg %den) {
; CHECK-LABEL: s_srem_i64: ; CHECK-LABEL: s_srem_i64:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: s_or_b64 s[6:7], s[2:3], s[4:5] ; CHECK-NEXT: s_or_b64 s[6:7], s[2:3], s[4:5]
; CHECK-NEXT: s_mov_b32 s0, 0 ; CHECK-NEXT: s_mov_b32 s0, 0
; CHECK-NEXT: s_mov_b32 s1, -1 ; CHECK-NEXT: s_mov_b32 s1, -1
; CHECK-NEXT: s_and_b64 s[6:7], s[6:7], s[0:1] ; CHECK-NEXT: s_and_b64 s[6:7], s[6:7], s[0:1]
; CHECK-NEXT: v_cmp_ne_u64_e64 vcc, s[6:7], 0 ; CHECK-NEXT: v_cmp_ne_u64_e64 vcc, s[6:7], 0
; CHECK-NEXT: s_cbranch_vccz BB1_2 ; CHECK-NEXT: s_cbranch_vccz .LBB1_2
; CHECK-NEXT: ; %bb.1: ; CHECK-NEXT: ; %bb.1:
; CHECK-NEXT: s_ashr_i32 s6, s3, 31 ; CHECK-NEXT: s_ashr_i32 s6, s3, 31
; CHECK-NEXT: s_ashr_i32 s0, s5, 31 ; CHECK-NEXT: s_ashr_i32 s0, s5, 31
; CHECK-NEXT: s_add_u32 s10, s2, s6 ; CHECK-NEXT: s_add_u32 s10, s2, s6
; CHECK-NEXT: s_cselect_b32 s7, 1, 0 ; CHECK-NEXT: s_cselect_b32 s7, 1, 0
; CHECK-NEXT: s_and_b32 s7, s7, 1 ; CHECK-NEXT: s_and_b32 s7, s7, 1
; CHECK-NEXT: s_cmp_lg_u32 s7, 0 ; CHECK-NEXT: s_cmp_lg_u32 s7, 0
; CHECK-NEXT: s_addc_u32 s11, s3, s6 ; CHECK-NEXT: s_addc_u32 s11, s3, s6
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; CHECK-NEXT: v_subrev_i32_e32 v4, vcc, s8, v3 ; CHECK-NEXT: v_subrev_i32_e32 v4, vcc, s8, v3
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; CHECK-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; CHECK-NEXT: v_xor_b32_e32 v0, s6, v0 ; CHECK-NEXT: v_xor_b32_e32 v0, s6, v0
; CHECK-NEXT: v_subrev_i32_e32 v0, vcc, s6, v0 ; CHECK-NEXT: v_subrev_i32_e32 v0, vcc, s6, v0
; CHECK-NEXT: s_mov_b32 s1, 0 ; CHECK-NEXT: s_mov_b32 s1, 0
; CHECK-NEXT: s_branch BB1_3 ; CHECK-NEXT: s_branch .LBB1_3
; CHECK-NEXT: BB1_2: ; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1 ; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
; CHECK-NEXT: BB1_3: ; %Flow ; CHECK-NEXT: .LBB1_3: ; %Flow
; CHECK-NEXT: s_xor_b32 s0, s1, -1 ; CHECK-NEXT: s_xor_b32 s0, s1, -1
; CHECK-NEXT: s_and_b32 s0, s0, 1 ; CHECK-NEXT: s_and_b32 s0, s0, 1
; CHECK-NEXT: s_cmp_lg_u32 s0, 0 ; CHECK-NEXT: s_cmp_lg_u32 s0, 0
; CHECK-NEXT: s_cbranch_scc1 BB1_5 ; CHECK-NEXT: s_cbranch_scc1 .LBB1_5
; CHECK-NEXT: ; %bb.4: ; CHECK-NEXT: ; %bb.4:
; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s4 ; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s4
; CHECK-NEXT: s_sub_i32 s0, 0, s4 ; CHECK-NEXT: s_sub_i32 s0, 0, s4
; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CHECK-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; CHECK-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0 ; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
; CHECK-NEXT: v_mul_lo_u32 v1, s0, v0 ; CHECK-NEXT: v_mul_lo_u32 v1, s0, v0
; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1 ; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; CHECK-NEXT: v_mul_hi_u32 v0, s2, v0 ; CHECK-NEXT: v_mul_hi_u32 v0, s2, v0
; CHECK-NEXT: v_mul_lo_u32 v0, v0, s4 ; CHECK-NEXT: v_mul_lo_u32 v0, v0, s4
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, s2, v0 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
; CHECK-NEXT: v_subrev_i32_e32 v1, vcc, s4, v0 ; CHECK-NEXT: v_subrev_i32_e32 v1, vcc, s4, v0
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v0 ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; CHECK-NEXT: v_subrev_i32_e32 v1, vcc, s4, v0 ; CHECK-NEXT: v_subrev_i32_e32 v1, vcc, s4, v0
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v0 ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; CHECK-NEXT: BB1_5: ; CHECK-NEXT: .LBB1_5:
; CHECK-NEXT: v_readfirstlane_b32 s0, v0 ; CHECK-NEXT: v_readfirstlane_b32 s0, v0
; CHECK-NEXT: s_mov_b32 s1, s0 ; CHECK-NEXT: s_mov_b32 s1, s0
; CHECK-NEXT: ; return to shader part epilog ; CHECK-NEXT: ; return to shader part epilog
%result = srem i64 %num, %den %result = srem i64 %num, %den
%cast = bitcast i64 %result to <2 x i32> %cast = bitcast i64 %result to <2 x i32>
%elt.0 = extractelement <2 x i32> %cast, i32 0 %elt.0 = extractelement <2 x i32> %cast, i32 0
%elt.1 = extractelement <2 x i32> %cast, i32 1 %elt.1 = extractelement <2 x i32> %cast, i32 1
%res.0 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt.0) %res.0 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt.0)
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; CGP-NEXT: v_or_b32_e32 v1, v11, v5 ; CGP-NEXT: v_or_b32_e32 v1, v11, v5
; CGP-NEXT: v_mov_b32_e32 v0, 0 ; CGP-NEXT: v_mov_b32_e32 v0, 0
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] ; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; CGP-NEXT: v_mov_b32_e32 v8, v2 ; CGP-NEXT: v_mov_b32_e32 v8, v2
; CGP-NEXT: v_mov_b32_e32 v9, v3 ; CGP-NEXT: v_mov_b32_e32 v9, v3
; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1 ; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5] ; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CGP-NEXT: s_cbranch_execz BB2_2 ; CGP-NEXT: s_cbranch_execz .LBB2_2
; CGP-NEXT: ; %bb.1: ; CGP-NEXT: ; %bb.1:
; CGP-NEXT: v_ashrrev_i32_e32 v0, 31, v5 ; CGP-NEXT: v_ashrrev_i32_e32 v0, 31, v5
; CGP-NEXT: v_add_i32_e32 v1, vcc, v4, v0 ; CGP-NEXT: v_add_i32_e32 v1, vcc, v4, v0
; CGP-NEXT: v_addc_u32_e32 v2, vcc, v5, v0, vcc ; CGP-NEXT: v_addc_u32_e32 v2, vcc, v5, v0, vcc
; CGP-NEXT: v_xor_b32_e32 v1, v1, v0 ; CGP-NEXT: v_xor_b32_e32 v1, v1, v0
; CGP-NEXT: v_xor_b32_e32 v0, v2, v0 ; CGP-NEXT: v_xor_b32_e32 v0, v2, v0
; CGP-NEXT: v_cvt_f32_u32_e32 v2, v1 ; CGP-NEXT: v_cvt_f32_u32_e32 v2, v1
; CGP-NEXT: v_cvt_f32_u32_e32 v3, v0 ; CGP-NEXT: v_cvt_f32_u32_e32 v3, v0
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; CGP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; CGP-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc
; CGP-NEXT: v_xor_b32_e32 v1, v1, v4 ; CGP-NEXT: v_xor_b32_e32 v1, v1, v4
; CGP-NEXT: v_xor_b32_e32 v2, v0, v4 ; CGP-NEXT: v_xor_b32_e32 v2, v0, v4
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v1, v4 ; CGP-NEXT: v_sub_i32_e32 v0, vcc, v1, v4
; CGP-NEXT: v_subb_u32_e32 v1, vcc, v2, v4, vcc ; CGP-NEXT: v_subb_u32_e32 v1, vcc, v2, v4, vcc
; CGP-NEXT: ; implicit-def: $vgpr4 ; CGP-NEXT: ; implicit-def: $vgpr4
; CGP-NEXT: ; implicit-def: $vgpr10 ; CGP-NEXT: ; implicit-def: $vgpr10
; CGP-NEXT: BB2_2: ; %Flow2 ; CGP-NEXT: .LBB2_2: ; %Flow2
; CGP-NEXT: s_or_saveexec_b64 s[4:5], s[6:7] ; CGP-NEXT: s_or_saveexec_b64 s[4:5], s[6:7]
; CGP-NEXT: s_xor_b64 exec, exec, s[4:5] ; CGP-NEXT: s_xor_b64 exec, exec, s[4:5]
; CGP-NEXT: s_cbranch_execz BB2_4 ; CGP-NEXT: s_cbranch_execz .LBB2_4
; CGP-NEXT: ; %bb.3: ; CGP-NEXT: ; %bb.3:
; CGP-NEXT: v_cvt_f32_u32_e32 v0, v4 ; CGP-NEXT: v_cvt_f32_u32_e32 v0, v4
; CGP-NEXT: v_sub_i32_e32 v1, vcc, 0, v4 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, 0, v4
; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CGP-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; CGP-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; CGP-NEXT: v_cvt_u32_f32_e32 v0, v0 ; CGP-NEXT: v_cvt_u32_f32_e32 v0, v0
; CGP-NEXT: v_mul_lo_u32 v1, v1, v0 ; CGP-NEXT: v_mul_lo_u32 v1, v1, v0
; CGP-NEXT: v_mul_hi_u32 v1, v0, v1 ; CGP-NEXT: v_mul_hi_u32 v1, v0, v1
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; CGP-NEXT: v_mul_hi_u32 v0, v10, v0 ; CGP-NEXT: v_mul_hi_u32 v0, v10, v0
; CGP-NEXT: v_mul_lo_u32 v0, v0, v4 ; CGP-NEXT: v_mul_lo_u32 v0, v0, v4
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v10, v0 ; CGP-NEXT: v_sub_i32_e32 v0, vcc, v10, v0
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v0, v4 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, v0, v4
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v4 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v4
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v0, v4 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, v0, v4
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v4 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v4
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; CGP-NEXT: v_mov_b32_e32 v1, 0 ; CGP-NEXT: v_mov_b32_e32 v1, 0
; CGP-NEXT: BB2_4: ; CGP-NEXT: .LBB2_4:
; CGP-NEXT: s_or_b64 exec, exec, s[4:5] ; CGP-NEXT: s_or_b64 exec, exec, s[4:5]
; CGP-NEXT: v_or_b32_e32 v3, v9, v7 ; CGP-NEXT: v_or_b32_e32 v3, v9, v7
; CGP-NEXT: v_mov_b32_e32 v2, 0 ; CGP-NEXT: v_mov_b32_e32 v2, 0
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3] ; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3 ; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5] ; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CGP-NEXT: s_cbranch_execz BB2_6 ; CGP-NEXT: s_cbranch_execz .LBB2_6
; CGP-NEXT: ; %bb.5: ; CGP-NEXT: ; %bb.5:
; CGP-NEXT: v_ashrrev_i32_e32 v2, 31, v7 ; CGP-NEXT: v_ashrrev_i32_e32 v2, 31, v7
; CGP-NEXT: v_add_i32_e32 v3, vcc, v6, v2 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v6, v2
; CGP-NEXT: v_addc_u32_e32 v4, vcc, v7, v2, vcc ; CGP-NEXT: v_addc_u32_e32 v4, vcc, v7, v2, vcc
; CGP-NEXT: v_xor_b32_e32 v3, v3, v2 ; CGP-NEXT: v_xor_b32_e32 v3, v3, v2
; CGP-NEXT: v_xor_b32_e32 v2, v4, v2 ; CGP-NEXT: v_xor_b32_e32 v2, v4, v2
; CGP-NEXT: v_cvt_f32_u32_e32 v4, v3 ; CGP-NEXT: v_cvt_f32_u32_e32 v4, v3
; CGP-NEXT: v_cvt_f32_u32_e32 v5, v2 ; CGP-NEXT: v_cvt_f32_u32_e32 v5, v2
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; CGP-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc ; CGP-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; CGP-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc
; CGP-NEXT: v_xor_b32_e32 v3, v3, v6 ; CGP-NEXT: v_xor_b32_e32 v3, v3, v6
; CGP-NEXT: v_xor_b32_e32 v4, v2, v6 ; CGP-NEXT: v_xor_b32_e32 v4, v2, v6
; CGP-NEXT: v_sub_i32_e32 v2, vcc, v3, v6 ; CGP-NEXT: v_sub_i32_e32 v2, vcc, v3, v6
; CGP-NEXT: v_subb_u32_e32 v3, vcc, v4, v6, vcc ; CGP-NEXT: v_subb_u32_e32 v3, vcc, v4, v6, vcc
; CGP-NEXT: ; implicit-def: $vgpr6 ; CGP-NEXT: ; implicit-def: $vgpr6
; CGP-NEXT: ; implicit-def: $vgpr8 ; CGP-NEXT: ; implicit-def: $vgpr8
; CGP-NEXT: BB2_6: ; %Flow ; CGP-NEXT: .LBB2_6: ; %Flow
; CGP-NEXT: s_or_saveexec_b64 s[4:5], s[6:7] ; CGP-NEXT: s_or_saveexec_b64 s[4:5], s[6:7]
; CGP-NEXT: s_xor_b64 exec, exec, s[4:5] ; CGP-NEXT: s_xor_b64 exec, exec, s[4:5]
; CGP-NEXT: s_cbranch_execz BB2_8 ; CGP-NEXT: s_cbranch_execz .LBB2_8
; CGP-NEXT: ; %bb.7: ; CGP-NEXT: ; %bb.7:
; CGP-NEXT: v_cvt_f32_u32_e32 v2, v6 ; CGP-NEXT: v_cvt_f32_u32_e32 v2, v6
; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v6 ; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v6
; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2 ; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2 ; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2
; CGP-NEXT: v_mul_lo_u32 v3, v3, v2 ; CGP-NEXT: v_mul_lo_u32 v3, v3, v2
; CGP-NEXT: v_mul_hi_u32 v3, v2, v3 ; CGP-NEXT: v_mul_hi_u32 v3, v2, v3
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; CGP-NEXT: v_mul_hi_u32 v2, v8, v2 ; CGP-NEXT: v_mul_hi_u32 v2, v8, v2
; CGP-NEXT: v_mul_lo_u32 v2, v2, v6 ; CGP-NEXT: v_mul_lo_u32 v2, v2, v6
; CGP-NEXT: v_sub_i32_e32 v2, vcc, v8, v2 ; CGP-NEXT: v_sub_i32_e32 v2, vcc, v8, v2
; CGP-NEXT: v_sub_i32_e32 v3, vcc, v2, v6 ; CGP-NEXT: v_sub_i32_e32 v3, vcc, v2, v6
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v6 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v6
; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; CGP-NEXT: v_sub_i32_e32 v3, vcc, v2, v6 ; CGP-NEXT: v_sub_i32_e32 v3, vcc, v2, v6
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v6 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v6
; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; CGP-NEXT: v_mov_b32_e32 v3, 0 ; CGP-NEXT: v_mov_b32_e32 v3, 0
; CGP-NEXT: BB2_8: ; CGP-NEXT: .LBB2_8:
; CGP-NEXT: s_or_b64 exec, exec, s[4:5] ; CGP-NEXT: s_or_b64 exec, exec, s[4:5]
; CGP-NEXT: s_setpc_b64 s[30:31] ; CGP-NEXT: s_setpc_b64 s[30:31]
%result = srem <2 x i64> %num, %den %result = srem <2 x i64> %num, %den
ret <2 x i64> %result ret <2 x i64> %result
} }
define i64 @v_srem_i64_pow2k_denom(i64 %num) { define i64 @v_srem_i64_pow2k_denom(i64 %num) {
; CHECK-LABEL: v_srem_i64_pow2k_denom: ; CHECK-LABEL: v_srem_i64_pow2k_denom:
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; CHECK-NEXT: v_mov_b32_e32 v4, v1 ; CHECK-NEXT: v_mov_b32_e32 v4, v1
; CHECK-NEXT: v_mov_b32_e32 v3, v0 ; CHECK-NEXT: v_mov_b32_e32 v3, v0
; CHECK-NEXT: v_or_b32_e32 v1, v4, v6 ; CHECK-NEXT: v_or_b32_e32 v1, v4, v6
; CHECK-NEXT: v_mov_b32_e32 v0, 0 ; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] ; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1 ; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[4:5] ; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CHECK-NEXT: s_cbranch_execz BB7_2 ; CHECK-NEXT: s_cbranch_execz .LBB7_2
; CHECK-NEXT: ; %bb.1: ; CHECK-NEXT: ; %bb.1:
; CHECK-NEXT: v_ashrrev_i32_e32 v0, 31, v6 ; CHECK-NEXT: v_ashrrev_i32_e32 v0, 31, v6
; CHECK-NEXT: v_add_i32_e32 v1, vcc, v5, v0 ; CHECK-NEXT: v_add_i32_e32 v1, vcc, v5, v0
; CHECK-NEXT: v_addc_u32_e32 v2, vcc, v6, v0, vcc ; CHECK-NEXT: v_addc_u32_e32 v2, vcc, v6, v0, vcc
; CHECK-NEXT: v_xor_b32_e32 v1, v1, v0 ; CHECK-NEXT: v_xor_b32_e32 v1, v1, v0
; CHECK-NEXT: v_xor_b32_e32 v0, v2, v0 ; CHECK-NEXT: v_xor_b32_e32 v0, v2, v0
; CHECK-NEXT: v_cvt_f32_u32_e32 v2, v1 ; CHECK-NEXT: v_cvt_f32_u32_e32 v2, v1
; CHECK-NEXT: v_cvt_f32_u32_e32 v5, v0 ; CHECK-NEXT: v_cvt_f32_u32_e32 v5, v0
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; CHECK-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; CHECK-NEXT: v_xor_b32_e32 v1, v1, v6 ; CHECK-NEXT: v_xor_b32_e32 v1, v1, v6
; CHECK-NEXT: v_xor_b32_e32 v2, v0, v6 ; CHECK-NEXT: v_xor_b32_e32 v2, v0, v6
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v1, v6 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v1, v6
; CHECK-NEXT: v_subb_u32_e32 v1, vcc, v2, v6, vcc ; CHECK-NEXT: v_subb_u32_e32 v1, vcc, v2, v6, vcc
; CHECK-NEXT: ; implicit-def: $vgpr5_vgpr6 ; CHECK-NEXT: ; implicit-def: $vgpr5_vgpr6
; CHECK-NEXT: ; implicit-def: $vgpr3 ; CHECK-NEXT: ; implicit-def: $vgpr3
; CHECK-NEXT: BB7_2: ; %Flow ; CHECK-NEXT: .LBB7_2: ; %Flow
; CHECK-NEXT: s_or_saveexec_b64 s[4:5], s[6:7] ; CHECK-NEXT: s_or_saveexec_b64 s[4:5], s[6:7]
; CHECK-NEXT: s_xor_b64 exec, exec, s[4:5] ; CHECK-NEXT: s_xor_b64 exec, exec, s[4:5]
; CHECK-NEXT: s_cbranch_execz BB7_4 ; CHECK-NEXT: s_cbranch_execz .LBB7_4
; CHECK-NEXT: ; %bb.3: ; CHECK-NEXT: ; %bb.3:
; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v5 ; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v5
; CHECK-NEXT: v_sub_i32_e32 v1, vcc, 0, v5 ; CHECK-NEXT: v_sub_i32_e32 v1, vcc, 0, v5
; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CHECK-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; CHECK-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0 ; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
; CHECK-NEXT: v_mul_lo_u32 v1, v1, v0 ; CHECK-NEXT: v_mul_lo_u32 v1, v1, v0
; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1 ; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; CHECK-NEXT: v_mul_hi_u32 v0, v3, v0 ; CHECK-NEXT: v_mul_hi_u32 v0, v3, v0
; CHECK-NEXT: v_mul_lo_u32 v0, v0, v5 ; CHECK-NEXT: v_mul_lo_u32 v0, v0, v5
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v3, v0 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v3, v0
; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v0, v5 ; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v0, v5
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v5 ; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v5
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v0, v5 ; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v0, v5
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v5 ; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v5
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; CHECK-NEXT: v_mov_b32_e32 v1, 0 ; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: BB7_4: ; CHECK-NEXT: .LBB7_4:
; CHECK-NEXT: s_or_b64 exec, exec, s[4:5] ; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
; CHECK-NEXT: s_setpc_b64 s[30:31] ; CHECK-NEXT: s_setpc_b64 s[30:31]
%shl.y = shl i64 4096, %y %shl.y = shl i64 4096, %y
%r = srem i64 %x, %shl.y %r = srem i64 %x, %shl.y
ret i64 %r ret i64 %r
} }
define <2 x i64> @v_srem_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) { define <2 x i64> @v_srem_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
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; CGP-NEXT: v_mov_b32_e32 v8, v0 ; CGP-NEXT: v_mov_b32_e32 v8, v0
; CGP-NEXT: v_or_b32_e32 v1, v9, v3 ; CGP-NEXT: v_or_b32_e32 v1, v9, v3
; CGP-NEXT: v_mov_b32_e32 v0, 0 ; CGP-NEXT: v_mov_b32_e32 v0, 0
; CGP-NEXT: v_lshl_b64 v[10:11], s[4:5], v6 ; CGP-NEXT: v_lshl_b64 v[10:11], s[4:5], v6
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] ; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1 ; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5] ; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CGP-NEXT: s_cbranch_execz BB8_2 ; CGP-NEXT: s_cbranch_execz .LBB8_2
; CGP-NEXT: ; %bb.1: ; CGP-NEXT: ; %bb.1:
; CGP-NEXT: v_ashrrev_i32_e32 v0, 31, v3 ; CGP-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; CGP-NEXT: v_add_i32_e32 v1, vcc, v2, v0 ; CGP-NEXT: v_add_i32_e32 v1, vcc, v2, v0
; CGP-NEXT: v_addc_u32_e32 v2, vcc, v3, v0, vcc ; CGP-NEXT: v_addc_u32_e32 v2, vcc, v3, v0, vcc
; CGP-NEXT: v_xor_b32_e32 v1, v1, v0 ; CGP-NEXT: v_xor_b32_e32 v1, v1, v0
; CGP-NEXT: v_xor_b32_e32 v0, v2, v0 ; CGP-NEXT: v_xor_b32_e32 v0, v2, v0
; CGP-NEXT: v_cvt_f32_u32_e32 v2, v1 ; CGP-NEXT: v_cvt_f32_u32_e32 v2, v1
; CGP-NEXT: v_cvt_f32_u32_e32 v3, v0 ; CGP-NEXT: v_cvt_f32_u32_e32 v3, v0
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; CGP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; CGP-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; CGP-NEXT: v_xor_b32_e32 v1, v1, v4 ; CGP-NEXT: v_xor_b32_e32 v1, v1, v4
; CGP-NEXT: v_xor_b32_e32 v2, v0, v4 ; CGP-NEXT: v_xor_b32_e32 v2, v0, v4
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v1, v4 ; CGP-NEXT: v_sub_i32_e32 v0, vcc, v1, v4
; CGP-NEXT: v_subb_u32_e32 v1, vcc, v2, v4, vcc ; CGP-NEXT: v_subb_u32_e32 v1, vcc, v2, v4, vcc
; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3 ; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3
; CGP-NEXT: ; implicit-def: $vgpr8 ; CGP-NEXT: ; implicit-def: $vgpr8
; CGP-NEXT: BB8_2: ; %Flow2 ; CGP-NEXT: .LBB8_2: ; %Flow2
; CGP-NEXT: s_or_saveexec_b64 s[4:5], s[6:7] ; CGP-NEXT: s_or_saveexec_b64 s[4:5], s[6:7]
; CGP-NEXT: s_xor_b64 exec, exec, s[4:5] ; CGP-NEXT: s_xor_b64 exec, exec, s[4:5]
; CGP-NEXT: s_cbranch_execz BB8_4 ; CGP-NEXT: s_cbranch_execz .LBB8_4
; CGP-NEXT: ; %bb.3: ; CGP-NEXT: ; %bb.3:
; CGP-NEXT: v_cvt_f32_u32_e32 v0, v2 ; CGP-NEXT: v_cvt_f32_u32_e32 v0, v2
; CGP-NEXT: v_sub_i32_e32 v1, vcc, 0, v2 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, 0, v2
; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CGP-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; CGP-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; CGP-NEXT: v_cvt_u32_f32_e32 v0, v0 ; CGP-NEXT: v_cvt_u32_f32_e32 v0, v0
; CGP-NEXT: v_mul_lo_u32 v1, v1, v0 ; CGP-NEXT: v_mul_lo_u32 v1, v1, v0
; CGP-NEXT: v_mul_hi_u32 v1, v0, v1 ; CGP-NEXT: v_mul_hi_u32 v1, v0, v1
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; CGP-NEXT: v_mul_hi_u32 v0, v8, v0 ; CGP-NEXT: v_mul_hi_u32 v0, v8, v0
; CGP-NEXT: v_mul_lo_u32 v0, v0, v2 ; CGP-NEXT: v_mul_lo_u32 v0, v0, v2
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v8, v0 ; CGP-NEXT: v_sub_i32_e32 v0, vcc, v8, v0
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v0, v2 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, v0, v2
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v0, v2 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, v0, v2
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; CGP-NEXT: v_mov_b32_e32 v1, 0 ; CGP-NEXT: v_mov_b32_e32 v1, 0
; CGP-NEXT: BB8_4: ; CGP-NEXT: .LBB8_4:
; CGP-NEXT: s_or_b64 exec, exec, s[4:5] ; CGP-NEXT: s_or_b64 exec, exec, s[4:5]
; CGP-NEXT: v_or_b32_e32 v3, v7, v11 ; CGP-NEXT: v_or_b32_e32 v3, v7, v11
; CGP-NEXT: v_mov_b32_e32 v2, 0 ; CGP-NEXT: v_mov_b32_e32 v2, 0
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3] ; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3 ; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5] ; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CGP-NEXT: s_cbranch_execz BB8_6 ; CGP-NEXT: s_cbranch_execz .LBB8_6
; CGP-NEXT: ; %bb.5: ; CGP-NEXT: ; %bb.5:
; CGP-NEXT: v_ashrrev_i32_e32 v2, 31, v11 ; CGP-NEXT: v_ashrrev_i32_e32 v2, 31, v11
; CGP-NEXT: v_add_i32_e32 v3, vcc, v10, v2 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v10, v2
; CGP-NEXT: v_addc_u32_e32 v4, vcc, v11, v2, vcc ; CGP-NEXT: v_addc_u32_e32 v4, vcc, v11, v2, vcc
; CGP-NEXT: v_xor_b32_e32 v3, v3, v2 ; CGP-NEXT: v_xor_b32_e32 v3, v3, v2
; CGP-NEXT: v_xor_b32_e32 v2, v4, v2 ; CGP-NEXT: v_xor_b32_e32 v2, v4, v2
; CGP-NEXT: v_cvt_f32_u32_e32 v4, v3 ; CGP-NEXT: v_cvt_f32_u32_e32 v4, v3
; CGP-NEXT: v_cvt_f32_u32_e32 v6, v2 ; CGP-NEXT: v_cvt_f32_u32_e32 v6, v2
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; CGP-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc ; CGP-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; CGP-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc
; CGP-NEXT: v_xor_b32_e32 v3, v3, v8 ; CGP-NEXT: v_xor_b32_e32 v3, v3, v8
; CGP-NEXT: v_xor_b32_e32 v4, v2, v8 ; CGP-NEXT: v_xor_b32_e32 v4, v2, v8
; CGP-NEXT: v_sub_i32_e32 v2, vcc, v3, v8 ; CGP-NEXT: v_sub_i32_e32 v2, vcc, v3, v8
; CGP-NEXT: v_subb_u32_e32 v3, vcc, v4, v8, vcc ; CGP-NEXT: v_subb_u32_e32 v3, vcc, v4, v8, vcc
; CGP-NEXT: ; implicit-def: $vgpr10_vgpr11 ; CGP-NEXT: ; implicit-def: $vgpr10_vgpr11
; CGP-NEXT: ; implicit-def: $vgpr5 ; CGP-NEXT: ; implicit-def: $vgpr5
; CGP-NEXT: BB8_6: ; %Flow ; CGP-NEXT: .LBB8_6: ; %Flow
; CGP-NEXT: s_or_saveexec_b64 s[4:5], s[6:7] ; CGP-NEXT: s_or_saveexec_b64 s[4:5], s[6:7]
; CGP-NEXT: s_xor_b64 exec, exec, s[4:5] ; CGP-NEXT: s_xor_b64 exec, exec, s[4:5]
; CGP-NEXT: s_cbranch_execz BB8_8 ; CGP-NEXT: s_cbranch_execz .LBB8_8
; CGP-NEXT: ; %bb.7: ; CGP-NEXT: ; %bb.7:
; CGP-NEXT: v_cvt_f32_u32_e32 v2, v10 ; CGP-NEXT: v_cvt_f32_u32_e32 v2, v10
; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v10 ; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v10
; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2 ; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2 ; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2
; CGP-NEXT: v_mul_lo_u32 v3, v3, v2 ; CGP-NEXT: v_mul_lo_u32 v3, v3, v2
; CGP-NEXT: v_mul_hi_u32 v3, v2, v3 ; CGP-NEXT: v_mul_hi_u32 v3, v2, v3
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; CGP-NEXT: v_mul_hi_u32 v2, v5, v2 ; CGP-NEXT: v_mul_hi_u32 v2, v5, v2
; CGP-NEXT: v_mul_lo_u32 v2, v2, v10 ; CGP-NEXT: v_mul_lo_u32 v2, v2, v10
; CGP-NEXT: v_sub_i32_e32 v2, vcc, v5, v2 ; CGP-NEXT: v_sub_i32_e32 v2, vcc, v5, v2
; CGP-NEXT: v_sub_i32_e32 v3, vcc, v2, v10 ; CGP-NEXT: v_sub_i32_e32 v3, vcc, v2, v10
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v10 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v10
; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; CGP-NEXT: v_sub_i32_e32 v3, vcc, v2, v10 ; CGP-NEXT: v_sub_i32_e32 v3, vcc, v2, v10
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v10 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v10
; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; CGP-NEXT: v_mov_b32_e32 v3, 0 ; CGP-NEXT: v_mov_b32_e32 v3, 0
; CGP-NEXT: BB8_8: ; CGP-NEXT: .LBB8_8:
; CGP-NEXT: s_or_b64 exec, exec, s[4:5] ; CGP-NEXT: s_or_b64 exec, exec, s[4:5]
; CGP-NEXT: s_setpc_b64 s[30:31] ; CGP-NEXT: s_setpc_b64 s[30:31]
%shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y %shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
%r = srem <2 x i64> %x, %shl.y %r = srem <2 x i64> %x, %shl.y
ret <2 x i64> %r ret <2 x i64> %r
} }
define i64 @v_srem_i64_24bit(i64 %num, i64 %den) { define i64 @v_srem_i64_24bit(i64 %num, i64 %den) {
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llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll

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; CHECK-NEXT: v_mov_b32_e32 v4, v0 ; CHECK-NEXT: v_mov_b32_e32 v4, v0
; CHECK-NEXT: v_mov_b32_e32 v5, v1 ; CHECK-NEXT: v_mov_b32_e32 v5, v1
; CHECK-NEXT: v_or_b32_e32 v1, v5, v3 ; CHECK-NEXT: v_or_b32_e32 v1, v5, v3
; CHECK-NEXT: v_mov_b32_e32 v0, 0 ; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] ; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1 ; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[4:5] ; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CHECK-NEXT: s_cbranch_execz BB0_2 ; CHECK-NEXT: s_cbranch_execz .LBB0_2
; CHECK-NEXT: ; %bb.1: ; CHECK-NEXT: ; %bb.1:
; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v2 ; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v2
; CHECK-NEXT: v_cvt_f32_u32_e32 v1, v3 ; CHECK-NEXT: v_cvt_f32_u32_e32 v1, v3
; CHECK-NEXT: v_sub_i32_e32 v6, vcc, 0, v2 ; CHECK-NEXT: v_sub_i32_e32 v6, vcc, 0, v2
; CHECK-NEXT: v_subb_u32_e32 v7, vcc, 0, v3, vcc ; CHECK-NEXT: v_subb_u32_e32 v7, vcc, 0, v3, vcc
; CHECK-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; CHECK-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CHECK-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; CHECK-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
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; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; CHECK-NEXT: v_cndmask_b32_e32 v2, v10, v8, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v2, v10, v8, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v3, v11, v12, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v3, v11, v12, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; CHECK-NEXT: ; implicit-def: $vgpr2 ; CHECK-NEXT: ; implicit-def: $vgpr2
; CHECK-NEXT: ; implicit-def: $vgpr4 ; CHECK-NEXT: ; implicit-def: $vgpr4
; CHECK-NEXT: BB0_2: ; %Flow ; CHECK-NEXT: .LBB0_2: ; %Flow
; CHECK-NEXT: s_or_saveexec_b64 s[6:7], s[6:7] ; CHECK-NEXT: s_or_saveexec_b64 s[6:7], s[6:7]
; CHECK-NEXT: s_xor_b64 exec, exec, s[6:7] ; CHECK-NEXT: s_xor_b64 exec, exec, s[6:7]
; CHECK-NEXT: s_cbranch_execz BB0_4 ; CHECK-NEXT: s_cbranch_execz .LBB0_4
; CHECK-NEXT: ; %bb.3: ; CHECK-NEXT: ; %bb.3:
; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v2 ; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v2
; CHECK-NEXT: v_sub_i32_e32 v1, vcc, 0, v2 ; CHECK-NEXT: v_sub_i32_e32 v1, vcc, 0, v2
; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CHECK-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; CHECK-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0 ; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
; CHECK-NEXT: v_mul_lo_u32 v1, v1, v0 ; CHECK-NEXT: v_mul_lo_u32 v1, v1, v0
; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1 ; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; CHECK-NEXT: v_mul_hi_u32 v0, v4, v0 ; CHECK-NEXT: v_mul_hi_u32 v0, v4, v0
; CHECK-NEXT: v_mul_lo_u32 v1, v0, v2 ; CHECK-NEXT: v_mul_lo_u32 v1, v0, v2
; CHECK-NEXT: v_add_i32_e32 v3, vcc, 1, v0 ; CHECK-NEXT: v_add_i32_e32 v3, vcc, 1, v0
; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v4, v1 ; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v4, v1
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2 ; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; CHECK-NEXT: v_sub_i32_e64 v3, s[4:5], v1, v2 ; CHECK-NEXT: v_sub_i32_e64 v3, s[4:5], v1, v2
; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; CHECK-NEXT: v_add_i32_e32 v3, vcc, 1, v0 ; CHECK-NEXT: v_add_i32_e32 v3, vcc, 1, v0
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2 ; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; CHECK-NEXT: v_mov_b32_e32 v1, 0 ; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: BB0_4: ; CHECK-NEXT: .LBB0_4:
; CHECK-NEXT: s_or_b64 exec, exec, s[6:7] ; CHECK-NEXT: s_or_b64 exec, exec, s[6:7]
; CHECK-NEXT: s_setpc_b64 s[30:31] ; CHECK-NEXT: s_setpc_b64 s[30:31]
%result = udiv i64 %num, %den %result = udiv i64 %num, %den
ret i64 %result ret i64 %result
} }
; FIXME: This is a workaround for not handling uniform VGPR case. ; FIXME: This is a workaround for not handling uniform VGPR case.
declare i32 @llvm.amdgcn.readfirstlane(i32) declare i32 @llvm.amdgcn.readfirstlane(i32)
define amdgpu_ps i64 @s_udiv_i64(i64 inreg %num, i64 inreg %den) { define amdgpu_ps i64 @s_udiv_i64(i64 inreg %num, i64 inreg %den) {
; CHECK-LABEL: s_udiv_i64: ; CHECK-LABEL: s_udiv_i64:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: s_or_b64 s[6:7], s[0:1], s[2:3] ; CHECK-NEXT: s_or_b64 s[6:7], s[0:1], s[2:3]
; CHECK-NEXT: s_mov_b32 s4, 0 ; CHECK-NEXT: s_mov_b32 s4, 0
; CHECK-NEXT: s_mov_b32 s5, -1 ; CHECK-NEXT: s_mov_b32 s5, -1
; CHECK-NEXT: s_and_b64 s[6:7], s[6:7], s[4:5] ; CHECK-NEXT: s_and_b64 s[6:7], s[6:7], s[4:5]
; CHECK-NEXT: v_cmp_ne_u64_e64 vcc, s[6:7], 0 ; CHECK-NEXT: v_cmp_ne_u64_e64 vcc, s[6:7], 0
; CHECK-NEXT: s_cbranch_vccz BB1_2 ; CHECK-NEXT: s_cbranch_vccz .LBB1_2
; CHECK-NEXT: ; %bb.1: ; CHECK-NEXT: ; %bb.1:
; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s2 ; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s2
; CHECK-NEXT: v_mov_b32_e32 v1, s3 ; CHECK-NEXT: v_mov_b32_e32 v1, s3
; CHECK-NEXT: v_cvt_f32_u32_e32 v2, s3 ; CHECK-NEXT: v_cvt_f32_u32_e32 v2, s3
; CHECK-NEXT: s_sub_u32 s4, 0, s2 ; CHECK-NEXT: s_sub_u32 s4, 0, s2
; CHECK-NEXT: s_cselect_b32 s5, 1, 0 ; CHECK-NEXT: s_cselect_b32 s5, 1, 0
; CHECK-NEXT: v_mov_b32_e32 v3, s1 ; CHECK-NEXT: v_mov_b32_e32 v3, s1
; CHECK-NEXT: v_mac_f32_e32 v0, 0x4f800000, v2 ; CHECK-NEXT: v_mac_f32_e32 v0, 0x4f800000, v2
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; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, s3, v1 ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, s3, v1
; CHECK-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
; CHECK-NEXT: v_cndmask_b32_e32 v1, v8, v4, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v8, v4, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; CHECK-NEXT: s_mov_b32 s5, 0 ; CHECK-NEXT: s_mov_b32 s5, 0
; CHECK-NEXT: s_branch BB1_3 ; CHECK-NEXT: s_branch .LBB1_3
; CHECK-NEXT: BB1_2: ; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1 ; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
; CHECK-NEXT: BB1_3: ; %Flow ; CHECK-NEXT: .LBB1_3: ; %Flow
; CHECK-NEXT: s_xor_b32 s1, s5, -1 ; CHECK-NEXT: s_xor_b32 s1, s5, -1
; CHECK-NEXT: s_and_b32 s1, s1, 1 ; CHECK-NEXT: s_and_b32 s1, s1, 1
; CHECK-NEXT: s_cmp_lg_u32 s1, 0 ; CHECK-NEXT: s_cmp_lg_u32 s1, 0
; CHECK-NEXT: s_cbranch_scc1 BB1_5 ; CHECK-NEXT: s_cbranch_scc1 .LBB1_5
; CHECK-NEXT: ; %bb.4: ; CHECK-NEXT: ; %bb.4:
; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s2 ; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s2
; CHECK-NEXT: s_sub_i32 s1, 0, s2 ; CHECK-NEXT: s_sub_i32 s1, 0, s2
; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CHECK-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; CHECK-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0 ; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
; CHECK-NEXT: v_mul_lo_u32 v1, s1, v0 ; CHECK-NEXT: v_mul_lo_u32 v1, s1, v0
; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1 ; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; CHECK-NEXT: v_mul_hi_u32 v0, s0, v0 ; CHECK-NEXT: v_mul_hi_u32 v0, s0, v0
; CHECK-NEXT: v_mul_lo_u32 v1, v0, s2 ; CHECK-NEXT: v_mul_lo_u32 v1, v0, s2
; CHECK-NEXT: v_add_i32_e32 v2, vcc, 1, v0 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, 1, v0
; CHECK-NEXT: v_sub_i32_e32 v1, vcc, s0, v1 ; CHECK-NEXT: v_sub_i32_e32 v1, vcc, s0, v1
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s2, v1 ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s2, v1
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CHECK-NEXT: v_subrev_i32_e64 v2, s[0:1], s2, v1 ; CHECK-NEXT: v_subrev_i32_e64 v2, s[0:1], s2, v1
; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; CHECK-NEXT: v_add_i32_e32 v2, vcc, 1, v0 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, 1, v0
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s2, v1 ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s2, v1
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CHECK-NEXT: BB1_5: ; CHECK-NEXT: .LBB1_5:
; CHECK-NEXT: v_readfirstlane_b32 s0, v0 ; CHECK-NEXT: v_readfirstlane_b32 s0, v0
; CHECK-NEXT: s_mov_b32 s1, s0 ; CHECK-NEXT: s_mov_b32 s1, s0
; CHECK-NEXT: ; return to shader part epilog ; CHECK-NEXT: ; return to shader part epilog
%result = udiv i64 %num, %den %result = udiv i64 %num, %den
%cast = bitcast i64 %result to <2 x i32> %cast = bitcast i64 %result to <2 x i32>
%elt.0 = extractelement <2 x i32> %cast, i32 0 %elt.0 = extractelement <2 x i32> %cast, i32 0
%elt.1 = extractelement <2 x i32> %cast, i32 1 %elt.1 = extractelement <2 x i32> %cast, i32 1
%res.0 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt.0) %res.0 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt.0)
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; CGP-NEXT: v_mov_b32_e32 v8, v2 ; CGP-NEXT: v_mov_b32_e32 v8, v2
; CGP-NEXT: v_mov_b32_e32 v9, v3 ; CGP-NEXT: v_mov_b32_e32 v9, v3
; CGP-NEXT: v_or_b32_e32 v1, v11, v5 ; CGP-NEXT: v_or_b32_e32 v1, v11, v5
; CGP-NEXT: v_mov_b32_e32 v0, 0 ; CGP-NEXT: v_mov_b32_e32 v0, 0
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] ; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1 ; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5] ; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CGP-NEXT: s_cbranch_execz BB2_2 ; CGP-NEXT: s_cbranch_execz .LBB2_2
; CGP-NEXT: ; %bb.1: ; CGP-NEXT: ; %bb.1:
; CGP-NEXT: v_cvt_f32_u32_e32 v0, v4 ; CGP-NEXT: v_cvt_f32_u32_e32 v0, v4
; CGP-NEXT: v_cvt_f32_u32_e32 v1, v5 ; CGP-NEXT: v_cvt_f32_u32_e32 v1, v5
; CGP-NEXT: v_sub_i32_e32 v2, vcc, 0, v4 ; CGP-NEXT: v_sub_i32_e32 v2, vcc, 0, v4
; CGP-NEXT: v_subb_u32_e32 v3, vcc, 0, v5, vcc ; CGP-NEXT: v_subb_u32_e32 v3, vcc, 0, v5, vcc
; CGP-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; CGP-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CGP-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; CGP-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
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; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; CGP-NEXT: v_cndmask_b32_e32 v2, v14, v12, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v14, v12, vcc
; CGP-NEXT: v_cndmask_b32_e32 v3, v15, v16, vcc ; CGP-NEXT: v_cndmask_b32_e32 v3, v15, v16, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; CGP-NEXT: ; implicit-def: $vgpr4 ; CGP-NEXT: ; implicit-def: $vgpr4
; CGP-NEXT: ; implicit-def: $vgpr10 ; CGP-NEXT: ; implicit-def: $vgpr10
; CGP-NEXT: BB2_2: ; %Flow2 ; CGP-NEXT: .LBB2_2: ; %Flow2
; CGP-NEXT: s_or_saveexec_b64 s[6:7], s[6:7] ; CGP-NEXT: s_or_saveexec_b64 s[6:7], s[6:7]
; CGP-NEXT: s_xor_b64 exec, exec, s[6:7] ; CGP-NEXT: s_xor_b64 exec, exec, s[6:7]
; CGP-NEXT: s_cbranch_execz BB2_4 ; CGP-NEXT: s_cbranch_execz .LBB2_4
; CGP-NEXT: ; %bb.3: ; CGP-NEXT: ; %bb.3:
; CGP-NEXT: v_cvt_f32_u32_e32 v0, v4 ; CGP-NEXT: v_cvt_f32_u32_e32 v0, v4
; CGP-NEXT: v_sub_i32_e32 v1, vcc, 0, v4 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, 0, v4
; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CGP-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; CGP-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; CGP-NEXT: v_cvt_u32_f32_e32 v0, v0 ; CGP-NEXT: v_cvt_u32_f32_e32 v0, v0
; CGP-NEXT: v_mul_lo_u32 v1, v1, v0 ; CGP-NEXT: v_mul_lo_u32 v1, v1, v0
; CGP-NEXT: v_mul_hi_u32 v1, v0, v1 ; CGP-NEXT: v_mul_hi_u32 v1, v0, v1
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; CGP-NEXT: v_mul_hi_u32 v0, v10, v0 ; CGP-NEXT: v_mul_hi_u32 v0, v10, v0
; CGP-NEXT: v_mul_lo_u32 v1, v0, v4 ; CGP-NEXT: v_mul_lo_u32 v1, v0, v4
; CGP-NEXT: v_add_i32_e32 v2, vcc, 1, v0 ; CGP-NEXT: v_add_i32_e32 v2, vcc, 1, v0
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v10, v1 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, v10, v1
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v4 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v4
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CGP-NEXT: v_sub_i32_e64 v2, s[4:5], v1, v4 ; CGP-NEXT: v_sub_i32_e64 v2, s[4:5], v1, v4
; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; CGP-NEXT: v_add_i32_e32 v2, vcc, 1, v0 ; CGP-NEXT: v_add_i32_e32 v2, vcc, 1, v0
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v4 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v4
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CGP-NEXT: v_mov_b32_e32 v1, 0 ; CGP-NEXT: v_mov_b32_e32 v1, 0
; CGP-NEXT: BB2_4: ; CGP-NEXT: .LBB2_4:
; CGP-NEXT: s_or_b64 exec, exec, s[6:7] ; CGP-NEXT: s_or_b64 exec, exec, s[6:7]
; CGP-NEXT: v_or_b32_e32 v3, v9, v7 ; CGP-NEXT: v_or_b32_e32 v3, v9, v7
; CGP-NEXT: v_mov_b32_e32 v2, 0 ; CGP-NEXT: v_mov_b32_e32 v2, 0
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3] ; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3 ; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5] ; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CGP-NEXT: s_cbranch_execz BB2_6 ; CGP-NEXT: s_cbranch_execz .LBB2_6
; CGP-NEXT: ; %bb.5: ; CGP-NEXT: ; %bb.5:
; CGP-NEXT: v_cvt_f32_u32_e32 v2, v6 ; CGP-NEXT: v_cvt_f32_u32_e32 v2, v6
; CGP-NEXT: v_cvt_f32_u32_e32 v3, v7 ; CGP-NEXT: v_cvt_f32_u32_e32 v3, v7
; CGP-NEXT: v_sub_i32_e32 v4, vcc, 0, v6 ; CGP-NEXT: v_sub_i32_e32 v4, vcc, 0, v6
; CGP-NEXT: v_subb_u32_e32 v5, vcc, 0, v7, vcc ; CGP-NEXT: v_subb_u32_e32 v5, vcc, 0, v7, vcc
; CGP-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3 ; CGP-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CGP-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 ; CGP-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
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; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; CGP-NEXT: v_cndmask_b32_e32 v4, v12, v10, vcc ; CGP-NEXT: v_cndmask_b32_e32 v4, v12, v10, vcc
; CGP-NEXT: v_cndmask_b32_e32 v5, v13, v14, vcc ; CGP-NEXT: v_cndmask_b32_e32 v5, v13, v14, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc ; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; CGP-NEXT: ; implicit-def: $vgpr6 ; CGP-NEXT: ; implicit-def: $vgpr6
; CGP-NEXT: ; implicit-def: $vgpr8 ; CGP-NEXT: ; implicit-def: $vgpr8
; CGP-NEXT: BB2_6: ; %Flow ; CGP-NEXT: .LBB2_6: ; %Flow
; CGP-NEXT: s_or_saveexec_b64 s[6:7], s[6:7] ; CGP-NEXT: s_or_saveexec_b64 s[6:7], s[6:7]
; CGP-NEXT: s_xor_b64 exec, exec, s[6:7] ; CGP-NEXT: s_xor_b64 exec, exec, s[6:7]
; CGP-NEXT: s_cbranch_execz BB2_8 ; CGP-NEXT: s_cbranch_execz .LBB2_8
; CGP-NEXT: ; %bb.7: ; CGP-NEXT: ; %bb.7:
; CGP-NEXT: v_cvt_f32_u32_e32 v2, v6 ; CGP-NEXT: v_cvt_f32_u32_e32 v2, v6
; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v6 ; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v6
; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2 ; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2 ; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2
; CGP-NEXT: v_mul_lo_u32 v3, v3, v2 ; CGP-NEXT: v_mul_lo_u32 v3, v3, v2
; CGP-NEXT: v_mul_hi_u32 v3, v2, v3 ; CGP-NEXT: v_mul_hi_u32 v3, v2, v3
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; CGP-NEXT: v_mul_hi_u32 v2, v8, v2 ; CGP-NEXT: v_mul_hi_u32 v2, v8, v2
; CGP-NEXT: v_mul_lo_u32 v3, v2, v6 ; CGP-NEXT: v_mul_lo_u32 v3, v2, v6
; CGP-NEXT: v_add_i32_e32 v4, vcc, 1, v2 ; CGP-NEXT: v_add_i32_e32 v4, vcc, 1, v2
; CGP-NEXT: v_sub_i32_e32 v3, vcc, v8, v3 ; CGP-NEXT: v_sub_i32_e32 v3, vcc, v8, v3
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v3, v6 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v3, v6
; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; CGP-NEXT: v_sub_i32_e64 v4, s[4:5], v3, v6 ; CGP-NEXT: v_sub_i32_e64 v4, s[4:5], v3, v6
; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; CGP-NEXT: v_add_i32_e32 v4, vcc, 1, v2 ; CGP-NEXT: v_add_i32_e32 v4, vcc, 1, v2
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v3, v6 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v3, v6
; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; CGP-NEXT: v_mov_b32_e32 v3, 0 ; CGP-NEXT: v_mov_b32_e32 v3, 0
; CGP-NEXT: BB2_8: ; CGP-NEXT: .LBB2_8:
; CGP-NEXT: s_or_b64 exec, exec, s[6:7] ; CGP-NEXT: s_or_b64 exec, exec, s[6:7]
; CGP-NEXT: s_setpc_b64 s[30:31] ; CGP-NEXT: s_setpc_b64 s[30:31]
%result = udiv <2 x i64> %num, %den %result = udiv <2 x i64> %num, %den
ret <2 x i64> %result ret <2 x i64> %result
} }
define i64 @v_udiv_i64_pow2k_denom(i64 %num) { define i64 @v_udiv_i64_pow2k_denom(i64 %num) {
; CHECK-LABEL: v_udiv_i64_pow2k_denom: ; CHECK-LABEL: v_udiv_i64_pow2k_denom:
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; CHECK-NEXT: s_mov_b64 s[4:5], 0x1000 ; CHECK-NEXT: s_mov_b64 s[4:5], 0x1000
; CHECK-NEXT: v_lshl_b64 v[5:6], s[4:5], v2 ; CHECK-NEXT: v_lshl_b64 v[5:6], s[4:5], v2
; CHECK-NEXT: v_or_b32_e32 v1, v4, v6 ; CHECK-NEXT: v_or_b32_e32 v1, v4, v6
; CHECK-NEXT: v_mov_b32_e32 v0, 0 ; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] ; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1 ; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[4:5] ; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CHECK-NEXT: s_cbranch_execz BB7_2 ; CHECK-NEXT: s_cbranch_execz .LBB7_2
; CHECK-NEXT: ; %bb.1: ; CHECK-NEXT: ; %bb.1:
; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v5 ; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v5
; CHECK-NEXT: v_cvt_f32_u32_e32 v1, v6 ; CHECK-NEXT: v_cvt_f32_u32_e32 v1, v6
; CHECK-NEXT: v_sub_i32_e32 v2, vcc, 0, v5 ; CHECK-NEXT: v_sub_i32_e32 v2, vcc, 0, v5
; CHECK-NEXT: v_subb_u32_e32 v7, vcc, 0, v6, vcc ; CHECK-NEXT: v_subb_u32_e32 v7, vcc, 0, v6, vcc
; CHECK-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; CHECK-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CHECK-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; CHECK-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
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; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; CHECK-NEXT: v_cndmask_b32_e32 v2, v10, v8, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v2, v10, v8, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v3, v11, v12, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v3, v11, v12, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; CHECK-NEXT: ; implicit-def: $vgpr5_vgpr6 ; CHECK-NEXT: ; implicit-def: $vgpr5_vgpr6
; CHECK-NEXT: ; implicit-def: $vgpr3 ; CHECK-NEXT: ; implicit-def: $vgpr3
; CHECK-NEXT: BB7_2: ; %Flow ; CHECK-NEXT: .LBB7_2: ; %Flow
; CHECK-NEXT: s_or_saveexec_b64 s[6:7], s[6:7] ; CHECK-NEXT: s_or_saveexec_b64 s[6:7], s[6:7]
; CHECK-NEXT: s_xor_b64 exec, exec, s[6:7] ; CHECK-NEXT: s_xor_b64 exec, exec, s[6:7]
; CHECK-NEXT: s_cbranch_execz BB7_4 ; CHECK-NEXT: s_cbranch_execz .LBB7_4
; CHECK-NEXT: ; %bb.3: ; CHECK-NEXT: ; %bb.3:
; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v5 ; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v5
; CHECK-NEXT: v_sub_i32_e32 v1, vcc, 0, v5 ; CHECK-NEXT: v_sub_i32_e32 v1, vcc, 0, v5
; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CHECK-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; CHECK-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0 ; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
; CHECK-NEXT: v_mul_lo_u32 v1, v1, v0 ; CHECK-NEXT: v_mul_lo_u32 v1, v1, v0
; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1 ; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; CHECK-NEXT: v_mul_hi_u32 v0, v3, v0 ; CHECK-NEXT: v_mul_hi_u32 v0, v3, v0
; CHECK-NEXT: v_mul_lo_u32 v1, v0, v5 ; CHECK-NEXT: v_mul_lo_u32 v1, v0, v5
; CHECK-NEXT: v_add_i32_e32 v2, vcc, 1, v0 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, 1, v0
; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v3, v1 ; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v3, v1
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v1, v5 ; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v1, v5
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CHECK-NEXT: v_sub_i32_e64 v2, s[4:5], v1, v5 ; CHECK-NEXT: v_sub_i32_e64 v2, s[4:5], v1, v5
; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; CHECK-NEXT: v_add_i32_e32 v2, vcc, 1, v0 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, 1, v0
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v1, v5 ; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v1, v5
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CHECK-NEXT: v_mov_b32_e32 v1, 0 ; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: BB7_4: ; CHECK-NEXT: .LBB7_4:
; CHECK-NEXT: s_or_b64 exec, exec, s[6:7] ; CHECK-NEXT: s_or_b64 exec, exec, s[6:7]
; CHECK-NEXT: s_setpc_b64 s[30:31] ; CHECK-NEXT: s_setpc_b64 s[30:31]
%shl.y = shl i64 4096, %y %shl.y = shl i64 4096, %y
%r = udiv i64 %x, %shl.y %r = udiv i64 %x, %shl.y
ret i64 %r ret i64 %r
} }
define <2 x i64> @v_udiv_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) { define <2 x i64> @v_udiv_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
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; CGP-NEXT: v_lshl_b64 v[2:3], s[4:5], v4 ; CGP-NEXT: v_lshl_b64 v[2:3], s[4:5], v4
; CGP-NEXT: v_lshl_b64 v[10:11], s[4:5], v6 ; CGP-NEXT: v_lshl_b64 v[10:11], s[4:5], v6
; CGP-NEXT: v_or_b32_e32 v1, v9, v3 ; CGP-NEXT: v_or_b32_e32 v1, v9, v3
; CGP-NEXT: v_mov_b32_e32 v0, 0 ; CGP-NEXT: v_mov_b32_e32 v0, 0
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] ; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1 ; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5] ; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CGP-NEXT: s_cbranch_execz BB8_2 ; CGP-NEXT: s_cbranch_execz .LBB8_2
; CGP-NEXT: ; %bb.1: ; CGP-NEXT: ; %bb.1:
; CGP-NEXT: v_cvt_f32_u32_e32 v0, v2 ; CGP-NEXT: v_cvt_f32_u32_e32 v0, v2
; CGP-NEXT: v_cvt_f32_u32_e32 v1, v3 ; CGP-NEXT: v_cvt_f32_u32_e32 v1, v3
; CGP-NEXT: v_sub_i32_e32 v4, vcc, 0, v2 ; CGP-NEXT: v_sub_i32_e32 v4, vcc, 0, v2
; CGP-NEXT: v_subb_u32_e32 v6, vcc, 0, v3, vcc ; CGP-NEXT: v_subb_u32_e32 v6, vcc, 0, v3, vcc
; CGP-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; CGP-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CGP-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; CGP-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
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; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; CGP-NEXT: v_cndmask_b32_e32 v2, v14, v12, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v14, v12, vcc
; CGP-NEXT: v_cndmask_b32_e32 v3, v15, v16, vcc ; CGP-NEXT: v_cndmask_b32_e32 v3, v15, v16, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3 ; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3
; CGP-NEXT: ; implicit-def: $vgpr8 ; CGP-NEXT: ; implicit-def: $vgpr8
; CGP-NEXT: BB8_2: ; %Flow2 ; CGP-NEXT: .LBB8_2: ; %Flow2
; CGP-NEXT: s_or_saveexec_b64 s[6:7], s[6:7] ; CGP-NEXT: s_or_saveexec_b64 s[6:7], s[6:7]
; CGP-NEXT: s_xor_b64 exec, exec, s[6:7] ; CGP-NEXT: s_xor_b64 exec, exec, s[6:7]
; CGP-NEXT: s_cbranch_execz BB8_4 ; CGP-NEXT: s_cbranch_execz .LBB8_4
; CGP-NEXT: ; %bb.3: ; CGP-NEXT: ; %bb.3:
; CGP-NEXT: v_cvt_f32_u32_e32 v0, v2 ; CGP-NEXT: v_cvt_f32_u32_e32 v0, v2
; CGP-NEXT: v_sub_i32_e32 v1, vcc, 0, v2 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, 0, v2
; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CGP-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; CGP-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; CGP-NEXT: v_cvt_u32_f32_e32 v0, v0 ; CGP-NEXT: v_cvt_u32_f32_e32 v0, v0
; CGP-NEXT: v_mul_lo_u32 v1, v1, v0 ; CGP-NEXT: v_mul_lo_u32 v1, v1, v0
; CGP-NEXT: v_mul_hi_u32 v1, v0, v1 ; CGP-NEXT: v_mul_hi_u32 v1, v0, v1
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; CGP-NEXT: v_mul_hi_u32 v0, v8, v0 ; CGP-NEXT: v_mul_hi_u32 v0, v8, v0
; CGP-NEXT: v_mul_lo_u32 v1, v0, v2 ; CGP-NEXT: v_mul_lo_u32 v1, v0, v2
; CGP-NEXT: v_add_i32_e32 v3, vcc, 1, v0 ; CGP-NEXT: v_add_i32_e32 v3, vcc, 1, v0
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v8, v1 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, v8, v1
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v1, v2 ; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v1, v2
; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; CGP-NEXT: v_add_i32_e32 v3, vcc, 1, v0 ; CGP-NEXT: v_add_i32_e32 v3, vcc, 1, v0
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; CGP-NEXT: v_mov_b32_e32 v1, 0 ; CGP-NEXT: v_mov_b32_e32 v1, 0
; CGP-NEXT: BB8_4: ; CGP-NEXT: .LBB8_4:
; CGP-NEXT: s_or_b64 exec, exec, s[6:7] ; CGP-NEXT: s_or_b64 exec, exec, s[6:7]
; CGP-NEXT: v_or_b32_e32 v3, v7, v11 ; CGP-NEXT: v_or_b32_e32 v3, v7, v11
; CGP-NEXT: v_mov_b32_e32 v2, 0 ; CGP-NEXT: v_mov_b32_e32 v2, 0
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3] ; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3 ; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5] ; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CGP-NEXT: s_cbranch_execz BB8_6 ; CGP-NEXT: s_cbranch_execz .LBB8_6
; CGP-NEXT: ; %bb.5: ; CGP-NEXT: ; %bb.5:
; CGP-NEXT: v_cvt_f32_u32_e32 v2, v10 ; CGP-NEXT: v_cvt_f32_u32_e32 v2, v10
; CGP-NEXT: v_cvt_f32_u32_e32 v3, v11 ; CGP-NEXT: v_cvt_f32_u32_e32 v3, v11
; CGP-NEXT: v_sub_i32_e32 v4, vcc, 0, v10 ; CGP-NEXT: v_sub_i32_e32 v4, vcc, 0, v10
; CGP-NEXT: v_subb_u32_e32 v6, vcc, 0, v11, vcc ; CGP-NEXT: v_subb_u32_e32 v6, vcc, 0, v11, vcc
; CGP-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3 ; CGP-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CGP-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 ; CGP-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
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; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; CGP-NEXT: v_cndmask_b32_e32 v4, v12, v8, vcc ; CGP-NEXT: v_cndmask_b32_e32 v4, v12, v8, vcc
; CGP-NEXT: v_cndmask_b32_e32 v5, v13, v14, vcc ; CGP-NEXT: v_cndmask_b32_e32 v5, v13, v14, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc ; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; CGP-NEXT: ; implicit-def: $vgpr10_vgpr11 ; CGP-NEXT: ; implicit-def: $vgpr10_vgpr11
; CGP-NEXT: ; implicit-def: $vgpr5 ; CGP-NEXT: ; implicit-def: $vgpr5
; CGP-NEXT: BB8_6: ; %Flow ; CGP-NEXT: .LBB8_6: ; %Flow
; CGP-NEXT: s_or_saveexec_b64 s[6:7], s[6:7] ; CGP-NEXT: s_or_saveexec_b64 s[6:7], s[6:7]
; CGP-NEXT: s_xor_b64 exec, exec, s[6:7] ; CGP-NEXT: s_xor_b64 exec, exec, s[6:7]
; CGP-NEXT: s_cbranch_execz BB8_8 ; CGP-NEXT: s_cbranch_execz .LBB8_8
; CGP-NEXT: ; %bb.7: ; CGP-NEXT: ; %bb.7:
; CGP-NEXT: v_cvt_f32_u32_e32 v2, v10 ; CGP-NEXT: v_cvt_f32_u32_e32 v2, v10
; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v10 ; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v10
; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2 ; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2 ; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2
; CGP-NEXT: v_mul_lo_u32 v3, v3, v2 ; CGP-NEXT: v_mul_lo_u32 v3, v3, v2
; CGP-NEXT: v_mul_hi_u32 v3, v2, v3 ; CGP-NEXT: v_mul_hi_u32 v3, v2, v3
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; CGP-NEXT: v_mul_hi_u32 v2, v5, v2 ; CGP-NEXT: v_mul_hi_u32 v2, v5, v2
; CGP-NEXT: v_mul_lo_u32 v3, v2, v10 ; CGP-NEXT: v_mul_lo_u32 v3, v2, v10
; CGP-NEXT: v_add_i32_e32 v4, vcc, 1, v2 ; CGP-NEXT: v_add_i32_e32 v4, vcc, 1, v2
; CGP-NEXT: v_sub_i32_e32 v3, vcc, v5, v3 ; CGP-NEXT: v_sub_i32_e32 v3, vcc, v5, v3
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v3, v10 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v3, v10
; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; CGP-NEXT: v_sub_i32_e64 v4, s[4:5], v3, v10 ; CGP-NEXT: v_sub_i32_e64 v4, s[4:5], v3, v10
; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; CGP-NEXT: v_add_i32_e32 v4, vcc, 1, v2 ; CGP-NEXT: v_add_i32_e32 v4, vcc, 1, v2
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v3, v10 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v3, v10
; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; CGP-NEXT: v_mov_b32_e32 v3, 0 ; CGP-NEXT: v_mov_b32_e32 v3, 0
; CGP-NEXT: BB8_8: ; CGP-NEXT: .LBB8_8:
; CGP-NEXT: s_or_b64 exec, exec, s[6:7] ; CGP-NEXT: s_or_b64 exec, exec, s[6:7]
; CGP-NEXT: s_setpc_b64 s[30:31] ; CGP-NEXT: s_setpc_b64 s[30:31]
%shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y %shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
%r = udiv <2 x i64> %x, %shl.y %r = udiv <2 x i64> %x, %shl.y
ret <2 x i64> %r ret <2 x i64> %r
} }
define i64 @v_udiv_i64_24bit(i64 %num, i64 %den) { define i64 @v_udiv_i64_24bit(i64 %num, i64 %den) {
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llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll

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; CHECK-NEXT: v_mov_b32_e32 v4, v0 ; CHECK-NEXT: v_mov_b32_e32 v4, v0
; CHECK-NEXT: v_mov_b32_e32 v5, v1 ; CHECK-NEXT: v_mov_b32_e32 v5, v1
; CHECK-NEXT: v_or_b32_e32 v1, v5, v3 ; CHECK-NEXT: v_or_b32_e32 v1, v5, v3
; CHECK-NEXT: v_mov_b32_e32 v0, 0 ; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] ; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1 ; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[4:5] ; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CHECK-NEXT: s_cbranch_execz BB0_2 ; CHECK-NEXT: s_cbranch_execz .LBB0_2
; CHECK-NEXT: ; %bb.1: ; CHECK-NEXT: ; %bb.1:
; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v2 ; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v2
; CHECK-NEXT: v_cvt_f32_u32_e32 v1, v3 ; CHECK-NEXT: v_cvt_f32_u32_e32 v1, v3
; CHECK-NEXT: v_sub_i32_e32 v6, vcc, 0, v2 ; CHECK-NEXT: v_sub_i32_e32 v6, vcc, 0, v2
; CHECK-NEXT: v_subb_u32_e32 v7, vcc, 0, v3, vcc ; CHECK-NEXT: v_subb_u32_e32 v7, vcc, 0, v3, vcc
; CHECK-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; CHECK-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CHECK-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; CHECK-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
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; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; CHECK-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v3, v7, v0, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v3, v7, v0, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; CHECK-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
; CHECK-NEXT: ; implicit-def: $vgpr2 ; CHECK-NEXT: ; implicit-def: $vgpr2
; CHECK-NEXT: ; implicit-def: $vgpr4 ; CHECK-NEXT: ; implicit-def: $vgpr4
; CHECK-NEXT: BB0_2: ; %Flow ; CHECK-NEXT: .LBB0_2: ; %Flow
; CHECK-NEXT: s_or_saveexec_b64 s[4:5], s[6:7] ; CHECK-NEXT: s_or_saveexec_b64 s[4:5], s[6:7]
; CHECK-NEXT: s_xor_b64 exec, exec, s[4:5] ; CHECK-NEXT: s_xor_b64 exec, exec, s[4:5]
; CHECK-NEXT: s_cbranch_execz BB0_4 ; CHECK-NEXT: s_cbranch_execz .LBB0_4
; CHECK-NEXT: ; %bb.3: ; CHECK-NEXT: ; %bb.3:
; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v2 ; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v2
; CHECK-NEXT: v_sub_i32_e32 v1, vcc, 0, v2 ; CHECK-NEXT: v_sub_i32_e32 v1, vcc, 0, v2
; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CHECK-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; CHECK-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0 ; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
; CHECK-NEXT: v_mul_lo_u32 v1, v1, v0 ; CHECK-NEXT: v_mul_lo_u32 v1, v1, v0
; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1 ; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; CHECK-NEXT: v_mul_hi_u32 v0, v4, v0 ; CHECK-NEXT: v_mul_hi_u32 v0, v4, v0
; CHECK-NEXT: v_mul_lo_u32 v0, v0, v2 ; CHECK-NEXT: v_mul_lo_u32 v0, v0, v2
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v4, v0 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v4, v0
; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v0, v2 ; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v0, v2
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 ; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v0, v2 ; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v0, v2
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 ; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; CHECK-NEXT: v_mov_b32_e32 v1, 0 ; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: BB0_4: ; CHECK-NEXT: .LBB0_4:
; CHECK-NEXT: s_or_b64 exec, exec, s[4:5] ; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
; CHECK-NEXT: s_setpc_b64 s[30:31] ; CHECK-NEXT: s_setpc_b64 s[30:31]
%result = urem i64 %num, %den %result = urem i64 %num, %den
ret i64 %result ret i64 %result
} }
; FIXME: This is a workaround for not handling uniform VGPR case. ; FIXME: This is a workaround for not handling uniform VGPR case.
declare i32 @llvm.amdgcn.readfirstlane(i32) declare i32 @llvm.amdgcn.readfirstlane(i32)
define amdgpu_ps i64 @s_urem_i64(i64 inreg %num, i64 inreg %den) { define amdgpu_ps i64 @s_urem_i64(i64 inreg %num, i64 inreg %den) {
; CHECK-LABEL: s_urem_i64: ; CHECK-LABEL: s_urem_i64:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: s_or_b64 s[6:7], s[0:1], s[2:3] ; CHECK-NEXT: s_or_b64 s[6:7], s[0:1], s[2:3]
; CHECK-NEXT: s_mov_b32 s4, 0 ; CHECK-NEXT: s_mov_b32 s4, 0
; CHECK-NEXT: s_mov_b32 s5, -1 ; CHECK-NEXT: s_mov_b32 s5, -1
; CHECK-NEXT: s_and_b64 s[6:7], s[6:7], s[4:5] ; CHECK-NEXT: s_and_b64 s[6:7], s[6:7], s[4:5]
; CHECK-NEXT: v_cmp_ne_u64_e64 vcc, s[6:7], 0 ; CHECK-NEXT: v_cmp_ne_u64_e64 vcc, s[6:7], 0
; CHECK-NEXT: s_cbranch_vccz BB1_2 ; CHECK-NEXT: s_cbranch_vccz .LBB1_2
; CHECK-NEXT: ; %bb.1: ; CHECK-NEXT: ; %bb.1:
; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s2 ; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s2
; CHECK-NEXT: v_mov_b32_e32 v1, s3 ; CHECK-NEXT: v_mov_b32_e32 v1, s3
; CHECK-NEXT: v_cvt_f32_u32_e32 v2, s3 ; CHECK-NEXT: v_cvt_f32_u32_e32 v2, s3
; CHECK-NEXT: s_sub_u32 s4, 0, s2 ; CHECK-NEXT: s_sub_u32 s4, 0, s2
; CHECK-NEXT: s_cselect_b32 s5, 1, 0 ; CHECK-NEXT: s_cselect_b32 s5, 1, 0
; CHECK-NEXT: v_mov_b32_e32 v3, s1 ; CHECK-NEXT: v_mov_b32_e32 v3, s1
; CHECK-NEXT: v_mac_f32_e32 v0, 0x4f800000, v2 ; CHECK-NEXT: v_mac_f32_e32 v0, 0x4f800000, v2
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; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, s3, v0 ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, s3, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v6, v4, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v6, v4, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
; CHECK-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; CHECK-NEXT: s_mov_b32 s5, 0 ; CHECK-NEXT: s_mov_b32 s5, 0
; CHECK-NEXT: s_branch BB1_3 ; CHECK-NEXT: s_branch .LBB1_3
; CHECK-NEXT: BB1_2: ; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1 ; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
; CHECK-NEXT: BB1_3: ; %Flow ; CHECK-NEXT: .LBB1_3: ; %Flow
; CHECK-NEXT: s_xor_b32 s1, s5, -1 ; CHECK-NEXT: s_xor_b32 s1, s5, -1
; CHECK-NEXT: s_and_b32 s1, s1, 1 ; CHECK-NEXT: s_and_b32 s1, s1, 1
; CHECK-NEXT: s_cmp_lg_u32 s1, 0 ; CHECK-NEXT: s_cmp_lg_u32 s1, 0
; CHECK-NEXT: s_cbranch_scc1 BB1_5 ; CHECK-NEXT: s_cbranch_scc1 .LBB1_5
; CHECK-NEXT: ; %bb.4: ; CHECK-NEXT: ; %bb.4:
; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s2 ; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s2
; CHECK-NEXT: s_sub_i32 s1, 0, s2 ; CHECK-NEXT: s_sub_i32 s1, 0, s2
; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CHECK-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; CHECK-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0 ; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
; CHECK-NEXT: v_mul_lo_u32 v1, s1, v0 ; CHECK-NEXT: v_mul_lo_u32 v1, s1, v0
; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1 ; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; CHECK-NEXT: v_mul_hi_u32 v0, s0, v0 ; CHECK-NEXT: v_mul_hi_u32 v0, s0, v0
; CHECK-NEXT: v_mul_lo_u32 v0, v0, s2 ; CHECK-NEXT: v_mul_lo_u32 v0, v0, s2
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, s0, v0 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
; CHECK-NEXT: v_subrev_i32_e32 v1, vcc, s2, v0 ; CHECK-NEXT: v_subrev_i32_e32 v1, vcc, s2, v0
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s2, v0 ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s2, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; CHECK-NEXT: v_subrev_i32_e32 v1, vcc, s2, v0 ; CHECK-NEXT: v_subrev_i32_e32 v1, vcc, s2, v0
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s2, v0 ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s2, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; CHECK-NEXT: BB1_5: ; CHECK-NEXT: .LBB1_5:
; CHECK-NEXT: v_readfirstlane_b32 s0, v0 ; CHECK-NEXT: v_readfirstlane_b32 s0, v0
; CHECK-NEXT: s_mov_b32 s1, s0 ; CHECK-NEXT: s_mov_b32 s1, s0
; CHECK-NEXT: ; return to shader part epilog ; CHECK-NEXT: ; return to shader part epilog
%result = urem i64 %num, %den %result = urem i64 %num, %den
%cast = bitcast i64 %result to <2 x i32> %cast = bitcast i64 %result to <2 x i32>
%elt.0 = extractelement <2 x i32> %cast, i32 0 %elt.0 = extractelement <2 x i32> %cast, i32 0
%elt.1 = extractelement <2 x i32> %cast, i32 1 %elt.1 = extractelement <2 x i32> %cast, i32 1
%res.0 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt.0) %res.0 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt.0)
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; CGP-NEXT: v_mov_b32_e32 v8, v2 ; CGP-NEXT: v_mov_b32_e32 v8, v2
; CGP-NEXT: v_mov_b32_e32 v9, v3 ; CGP-NEXT: v_mov_b32_e32 v9, v3
; CGP-NEXT: v_or_b32_e32 v1, v11, v5 ; CGP-NEXT: v_or_b32_e32 v1, v11, v5
; CGP-NEXT: v_mov_b32_e32 v0, 0 ; CGP-NEXT: v_mov_b32_e32 v0, 0
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] ; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1 ; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5] ; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CGP-NEXT: s_cbranch_execz BB2_2 ; CGP-NEXT: s_cbranch_execz .LBB2_2
; CGP-NEXT: ; %bb.1: ; CGP-NEXT: ; %bb.1:
; CGP-NEXT: v_cvt_f32_u32_e32 v0, v4 ; CGP-NEXT: v_cvt_f32_u32_e32 v0, v4
; CGP-NEXT: v_cvt_f32_u32_e32 v1, v5 ; CGP-NEXT: v_cvt_f32_u32_e32 v1, v5
; CGP-NEXT: v_sub_i32_e32 v2, vcc, 0, v4 ; CGP-NEXT: v_sub_i32_e32 v2, vcc, 0, v4
; CGP-NEXT: v_subb_u32_e32 v3, vcc, 0, v5, vcc ; CGP-NEXT: v_subb_u32_e32 v3, vcc, 0, v5, vcc
; CGP-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; CGP-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CGP-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; CGP-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
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; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; CGP-NEXT: v_cndmask_b32_e32 v4, v10, v4, vcc ; CGP-NEXT: v_cndmask_b32_e32 v4, v10, v4, vcc
; CGP-NEXT: v_cndmask_b32_e32 v5, v11, v0, vcc ; CGP-NEXT: v_cndmask_b32_e32 v5, v11, v0, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; CGP-NEXT: v_cndmask_b32_e32 v0, v1, v4, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v1, v4, vcc
; CGP-NEXT: v_cndmask_b32_e32 v1, v2, v5, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v2, v5, vcc
; CGP-NEXT: ; implicit-def: $vgpr4 ; CGP-NEXT: ; implicit-def: $vgpr4
; CGP-NEXT: ; implicit-def: $vgpr10 ; CGP-NEXT: ; implicit-def: $vgpr10
; CGP-NEXT: BB2_2: ; %Flow2 ; CGP-NEXT: .LBB2_2: ; %Flow2
; CGP-NEXT: s_or_saveexec_b64 s[4:5], s[6:7] ; CGP-NEXT: s_or_saveexec_b64 s[4:5], s[6:7]
; CGP-NEXT: s_xor_b64 exec, exec, s[4:5] ; CGP-NEXT: s_xor_b64 exec, exec, s[4:5]
; CGP-NEXT: s_cbranch_execz BB2_4 ; CGP-NEXT: s_cbranch_execz .LBB2_4
; CGP-NEXT: ; %bb.3: ; CGP-NEXT: ; %bb.3:
; CGP-NEXT: v_cvt_f32_u32_e32 v0, v4 ; CGP-NEXT: v_cvt_f32_u32_e32 v0, v4
; CGP-NEXT: v_sub_i32_e32 v1, vcc, 0, v4 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, 0, v4
; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CGP-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; CGP-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; CGP-NEXT: v_cvt_u32_f32_e32 v0, v0 ; CGP-NEXT: v_cvt_u32_f32_e32 v0, v0
; CGP-NEXT: v_mul_lo_u32 v1, v1, v0 ; CGP-NEXT: v_mul_lo_u32 v1, v1, v0
; CGP-NEXT: v_mul_hi_u32 v1, v0, v1 ; CGP-NEXT: v_mul_hi_u32 v1, v0, v1
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; CGP-NEXT: v_mul_hi_u32 v0, v10, v0 ; CGP-NEXT: v_mul_hi_u32 v0, v10, v0
; CGP-NEXT: v_mul_lo_u32 v0, v0, v4 ; CGP-NEXT: v_mul_lo_u32 v0, v0, v4
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v10, v0 ; CGP-NEXT: v_sub_i32_e32 v0, vcc, v10, v0
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v0, v4 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, v0, v4
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v4 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v4
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v0, v4 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, v0, v4
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v4 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v4
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; CGP-NEXT: v_mov_b32_e32 v1, 0 ; CGP-NEXT: v_mov_b32_e32 v1, 0
; CGP-NEXT: BB2_4: ; CGP-NEXT: .LBB2_4:
; CGP-NEXT: s_or_b64 exec, exec, s[4:5] ; CGP-NEXT: s_or_b64 exec, exec, s[4:5]
; CGP-NEXT: v_or_b32_e32 v3, v9, v7 ; CGP-NEXT: v_or_b32_e32 v3, v9, v7
; CGP-NEXT: v_mov_b32_e32 v2, 0 ; CGP-NEXT: v_mov_b32_e32 v2, 0
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3] ; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3 ; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5] ; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CGP-NEXT: s_cbranch_execz BB2_6 ; CGP-NEXT: s_cbranch_execz .LBB2_6
; CGP-NEXT: ; %bb.5: ; CGP-NEXT: ; %bb.5:
; CGP-NEXT: v_cvt_f32_u32_e32 v2, v6 ; CGP-NEXT: v_cvt_f32_u32_e32 v2, v6
; CGP-NEXT: v_cvt_f32_u32_e32 v3, v7 ; CGP-NEXT: v_cvt_f32_u32_e32 v3, v7
; CGP-NEXT: v_sub_i32_e32 v4, vcc, 0, v6 ; CGP-NEXT: v_sub_i32_e32 v4, vcc, 0, v6
; CGP-NEXT: v_subb_u32_e32 v5, vcc, 0, v7, vcc ; CGP-NEXT: v_subb_u32_e32 v5, vcc, 0, v7, vcc
; CGP-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3 ; CGP-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CGP-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 ; CGP-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
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; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; CGP-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc ; CGP-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc
; CGP-NEXT: v_cndmask_b32_e32 v7, v9, v2, vcc ; CGP-NEXT: v_cndmask_b32_e32 v7, v9, v2, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; CGP-NEXT: v_cndmask_b32_e32 v2, v3, v6, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v3, v6, vcc
; CGP-NEXT: v_cndmask_b32_e32 v3, v4, v7, vcc ; CGP-NEXT: v_cndmask_b32_e32 v3, v4, v7, vcc
; CGP-NEXT: ; implicit-def: $vgpr6 ; CGP-NEXT: ; implicit-def: $vgpr6
; CGP-NEXT: ; implicit-def: $vgpr8 ; CGP-NEXT: ; implicit-def: $vgpr8
; CGP-NEXT: BB2_6: ; %Flow ; CGP-NEXT: .LBB2_6: ; %Flow
; CGP-NEXT: s_or_saveexec_b64 s[4:5], s[6:7] ; CGP-NEXT: s_or_saveexec_b64 s[4:5], s[6:7]
; CGP-NEXT: s_xor_b64 exec, exec, s[4:5] ; CGP-NEXT: s_xor_b64 exec, exec, s[4:5]
; CGP-NEXT: s_cbranch_execz BB2_8 ; CGP-NEXT: s_cbranch_execz .LBB2_8
; CGP-NEXT: ; %bb.7: ; CGP-NEXT: ; %bb.7:
; CGP-NEXT: v_cvt_f32_u32_e32 v2, v6 ; CGP-NEXT: v_cvt_f32_u32_e32 v2, v6
; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v6 ; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v6
; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2 ; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2 ; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2
; CGP-NEXT: v_mul_lo_u32 v3, v3, v2 ; CGP-NEXT: v_mul_lo_u32 v3, v3, v2
; CGP-NEXT: v_mul_hi_u32 v3, v2, v3 ; CGP-NEXT: v_mul_hi_u32 v3, v2, v3
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; CGP-NEXT: v_mul_hi_u32 v2, v8, v2 ; CGP-NEXT: v_mul_hi_u32 v2, v8, v2
; CGP-NEXT: v_mul_lo_u32 v2, v2, v6 ; CGP-NEXT: v_mul_lo_u32 v2, v2, v6
; CGP-NEXT: v_sub_i32_e32 v2, vcc, v8, v2 ; CGP-NEXT: v_sub_i32_e32 v2, vcc, v8, v2
; CGP-NEXT: v_sub_i32_e32 v3, vcc, v2, v6 ; CGP-NEXT: v_sub_i32_e32 v3, vcc, v2, v6
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v6 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v6
; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; CGP-NEXT: v_sub_i32_e32 v3, vcc, v2, v6 ; CGP-NEXT: v_sub_i32_e32 v3, vcc, v2, v6
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v6 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v6
; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; CGP-NEXT: v_mov_b32_e32 v3, 0 ; CGP-NEXT: v_mov_b32_e32 v3, 0
; CGP-NEXT: BB2_8: ; CGP-NEXT: .LBB2_8:
; CGP-NEXT: s_or_b64 exec, exec, s[4:5] ; CGP-NEXT: s_or_b64 exec, exec, s[4:5]
; CGP-NEXT: s_setpc_b64 s[30:31] ; CGP-NEXT: s_setpc_b64 s[30:31]
%result = urem <2 x i64> %num, %den %result = urem <2 x i64> %num, %den
ret <2 x i64> %result ret <2 x i64> %result
} }
define i64 @v_urem_i64_pow2k_denom(i64 %num) { define i64 @v_urem_i64_pow2k_denom(i64 %num) {
; CHECK-LABEL: v_urem_i64_pow2k_denom: ; CHECK-LABEL: v_urem_i64_pow2k_denom:
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; CHECK-NEXT: s_mov_b64 s[4:5], 0x1000 ; CHECK-NEXT: s_mov_b64 s[4:5], 0x1000
; CHECK-NEXT: v_lshl_b64 v[5:6], s[4:5], v2 ; CHECK-NEXT: v_lshl_b64 v[5:6], s[4:5], v2
; CHECK-NEXT: v_or_b32_e32 v1, v4, v6 ; CHECK-NEXT: v_or_b32_e32 v1, v4, v6
; CHECK-NEXT: v_mov_b32_e32 v0, 0 ; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] ; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1 ; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[4:5] ; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CHECK-NEXT: s_cbranch_execz BB7_2 ; CHECK-NEXT: s_cbranch_execz .LBB7_2
; CHECK-NEXT: ; %bb.1: ; CHECK-NEXT: ; %bb.1:
; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v5 ; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v5
; CHECK-NEXT: v_cvt_f32_u32_e32 v1, v6 ; CHECK-NEXT: v_cvt_f32_u32_e32 v1, v6
; CHECK-NEXT: v_sub_i32_e32 v2, vcc, 0, v5 ; CHECK-NEXT: v_sub_i32_e32 v2, vcc, 0, v5
; CHECK-NEXT: v_subb_u32_e32 v7, vcc, 0, v6, vcc ; CHECK-NEXT: v_subb_u32_e32 v7, vcc, 0, v6, vcc
; CHECK-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; CHECK-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CHECK-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; CHECK-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
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; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v5, v7, v0, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v5, v7, v0, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; CHECK-NEXT: v_cndmask_b32_e32 v0, v1, v4, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v1, v4, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v1, v2, v5, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v2, v5, vcc
; CHECK-NEXT: ; implicit-def: $vgpr5_vgpr6 ; CHECK-NEXT: ; implicit-def: $vgpr5_vgpr6
; CHECK-NEXT: ; implicit-def: $vgpr3 ; CHECK-NEXT: ; implicit-def: $vgpr3
; CHECK-NEXT: BB7_2: ; %Flow ; CHECK-NEXT: .LBB7_2: ; %Flow
; CHECK-NEXT: s_or_saveexec_b64 s[4:5], s[6:7] ; CHECK-NEXT: s_or_saveexec_b64 s[4:5], s[6:7]
; CHECK-NEXT: s_xor_b64 exec, exec, s[4:5] ; CHECK-NEXT: s_xor_b64 exec, exec, s[4:5]
; CHECK-NEXT: s_cbranch_execz BB7_4 ; CHECK-NEXT: s_cbranch_execz .LBB7_4
; CHECK-NEXT: ; %bb.3: ; CHECK-NEXT: ; %bb.3:
; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v5 ; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v5
; CHECK-NEXT: v_sub_i32_e32 v1, vcc, 0, v5 ; CHECK-NEXT: v_sub_i32_e32 v1, vcc, 0, v5
; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CHECK-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; CHECK-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0 ; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
; CHECK-NEXT: v_mul_lo_u32 v1, v1, v0 ; CHECK-NEXT: v_mul_lo_u32 v1, v1, v0
; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1 ; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; CHECK-NEXT: v_mul_hi_u32 v0, v3, v0 ; CHECK-NEXT: v_mul_hi_u32 v0, v3, v0
; CHECK-NEXT: v_mul_lo_u32 v0, v0, v5 ; CHECK-NEXT: v_mul_lo_u32 v0, v0, v5
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v3, v0 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v3, v0
; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v0, v5 ; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v0, v5
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v5 ; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v5
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v0, v5 ; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v0, v5
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v5 ; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v5
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; CHECK-NEXT: v_mov_b32_e32 v1, 0 ; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: BB7_4: ; CHECK-NEXT: .LBB7_4:
; CHECK-NEXT: s_or_b64 exec, exec, s[4:5] ; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
; CHECK-NEXT: s_setpc_b64 s[30:31] ; CHECK-NEXT: s_setpc_b64 s[30:31]
%shl.y = shl i64 4096, %y %shl.y = shl i64 4096, %y
%r = urem i64 %x, %shl.y %r = urem i64 %x, %shl.y
ret i64 %r ret i64 %r
} }
define <2 x i64> @v_urem_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) { define <2 x i64> @v_urem_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
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; CGP-NEXT: v_lshl_b64 v[2:3], s[4:5], v4 ; CGP-NEXT: v_lshl_b64 v[2:3], s[4:5], v4
; CGP-NEXT: v_lshl_b64 v[10:11], s[4:5], v6 ; CGP-NEXT: v_lshl_b64 v[10:11], s[4:5], v6
; CGP-NEXT: v_or_b32_e32 v1, v9, v3 ; CGP-NEXT: v_or_b32_e32 v1, v9, v3
; CGP-NEXT: v_mov_b32_e32 v0, 0 ; CGP-NEXT: v_mov_b32_e32 v0, 0
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] ; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1 ; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5] ; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CGP-NEXT: s_cbranch_execz BB8_2 ; CGP-NEXT: s_cbranch_execz .LBB8_2
; CGP-NEXT: ; %bb.1: ; CGP-NEXT: ; %bb.1:
; CGP-NEXT: v_cvt_f32_u32_e32 v0, v2 ; CGP-NEXT: v_cvt_f32_u32_e32 v0, v2
; CGP-NEXT: v_cvt_f32_u32_e32 v1, v3 ; CGP-NEXT: v_cvt_f32_u32_e32 v1, v3
; CGP-NEXT: v_sub_i32_e32 v4, vcc, 0, v2 ; CGP-NEXT: v_sub_i32_e32 v4, vcc, 0, v2
; CGP-NEXT: v_subb_u32_e32 v6, vcc, 0, v3, vcc ; CGP-NEXT: v_subb_u32_e32 v6, vcc, 0, v3, vcc
; CGP-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; CGP-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CGP-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; CGP-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
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; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; CGP-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc
; CGP-NEXT: v_cndmask_b32_e32 v3, v9, v0, vcc ; CGP-NEXT: v_cndmask_b32_e32 v3, v9, v0, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; CGP-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
; CGP-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3 ; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3
; CGP-NEXT: ; implicit-def: $vgpr8 ; CGP-NEXT: ; implicit-def: $vgpr8
; CGP-NEXT: BB8_2: ; %Flow2 ; CGP-NEXT: .LBB8_2: ; %Flow2
; CGP-NEXT: s_or_saveexec_b64 s[4:5], s[6:7] ; CGP-NEXT: s_or_saveexec_b64 s[4:5], s[6:7]
; CGP-NEXT: s_xor_b64 exec, exec, s[4:5] ; CGP-NEXT: s_xor_b64 exec, exec, s[4:5]
; CGP-NEXT: s_cbranch_execz BB8_4 ; CGP-NEXT: s_cbranch_execz .LBB8_4
; CGP-NEXT: ; %bb.3: ; CGP-NEXT: ; %bb.3:
; CGP-NEXT: v_cvt_f32_u32_e32 v0, v2 ; CGP-NEXT: v_cvt_f32_u32_e32 v0, v2
; CGP-NEXT: v_sub_i32_e32 v1, vcc, 0, v2 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, 0, v2
; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CGP-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; CGP-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; CGP-NEXT: v_cvt_u32_f32_e32 v0, v0 ; CGP-NEXT: v_cvt_u32_f32_e32 v0, v0
; CGP-NEXT: v_mul_lo_u32 v1, v1, v0 ; CGP-NEXT: v_mul_lo_u32 v1, v1, v0
; CGP-NEXT: v_mul_hi_u32 v1, v0, v1 ; CGP-NEXT: v_mul_hi_u32 v1, v0, v1
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; CGP-NEXT: v_mul_hi_u32 v0, v8, v0 ; CGP-NEXT: v_mul_hi_u32 v0, v8, v0
; CGP-NEXT: v_mul_lo_u32 v0, v0, v2 ; CGP-NEXT: v_mul_lo_u32 v0, v0, v2
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v8, v0 ; CGP-NEXT: v_sub_i32_e32 v0, vcc, v8, v0
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v0, v2 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, v0, v2
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v0, v2 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, v0, v2
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; CGP-NEXT: v_mov_b32_e32 v1, 0 ; CGP-NEXT: v_mov_b32_e32 v1, 0
; CGP-NEXT: BB8_4: ; CGP-NEXT: .LBB8_4:
; CGP-NEXT: s_or_b64 exec, exec, s[4:5] ; CGP-NEXT: s_or_b64 exec, exec, s[4:5]
; CGP-NEXT: v_or_b32_e32 v3, v7, v11 ; CGP-NEXT: v_or_b32_e32 v3, v7, v11
; CGP-NEXT: v_mov_b32_e32 v2, 0 ; CGP-NEXT: v_mov_b32_e32 v2, 0
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3] ; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3 ; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5] ; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CGP-NEXT: s_cbranch_execz BB8_6 ; CGP-NEXT: s_cbranch_execz .LBB8_6
; CGP-NEXT: ; %bb.5: ; CGP-NEXT: ; %bb.5:
; CGP-NEXT: v_cvt_f32_u32_e32 v2, v10 ; CGP-NEXT: v_cvt_f32_u32_e32 v2, v10
; CGP-NEXT: v_cvt_f32_u32_e32 v3, v11 ; CGP-NEXT: v_cvt_f32_u32_e32 v3, v11
; CGP-NEXT: v_sub_i32_e32 v4, vcc, 0, v10 ; CGP-NEXT: v_sub_i32_e32 v4, vcc, 0, v10
; CGP-NEXT: v_subb_u32_e32 v6, vcc, 0, v11, vcc ; CGP-NEXT: v_subb_u32_e32 v6, vcc, 0, v11, vcc
; CGP-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3 ; CGP-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CGP-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 ; CGP-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
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; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; CGP-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc ; CGP-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc
; CGP-NEXT: v_cndmask_b32_e32 v7, v7, v2, vcc ; CGP-NEXT: v_cndmask_b32_e32 v7, v7, v2, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; CGP-NEXT: v_cndmask_b32_e32 v2, v3, v6, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v3, v6, vcc
; CGP-NEXT: v_cndmask_b32_e32 v3, v4, v7, vcc ; CGP-NEXT: v_cndmask_b32_e32 v3, v4, v7, vcc
; CGP-NEXT: ; implicit-def: $vgpr10_vgpr11 ; CGP-NEXT: ; implicit-def: $vgpr10_vgpr11
; CGP-NEXT: ; implicit-def: $vgpr5 ; CGP-NEXT: ; implicit-def: $vgpr5
; CGP-NEXT: BB8_6: ; %Flow ; CGP-NEXT: .LBB8_6: ; %Flow
; CGP-NEXT: s_or_saveexec_b64 s[4:5], s[6:7] ; CGP-NEXT: s_or_saveexec_b64 s[4:5], s[6:7]
; CGP-NEXT: s_xor_b64 exec, exec, s[4:5] ; CGP-NEXT: s_xor_b64 exec, exec, s[4:5]
; CGP-NEXT: s_cbranch_execz BB8_8 ; CGP-NEXT: s_cbranch_execz .LBB8_8
; CGP-NEXT: ; %bb.7: ; CGP-NEXT: ; %bb.7:
; CGP-NEXT: v_cvt_f32_u32_e32 v2, v10 ; CGP-NEXT: v_cvt_f32_u32_e32 v2, v10
; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v10 ; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v10
; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2 ; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2 ; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2
; CGP-NEXT: v_mul_lo_u32 v3, v3, v2 ; CGP-NEXT: v_mul_lo_u32 v3, v3, v2
; CGP-NEXT: v_mul_hi_u32 v3, v2, v3 ; CGP-NEXT: v_mul_hi_u32 v3, v2, v3
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; CGP-NEXT: v_mul_hi_u32 v2, v5, v2 ; CGP-NEXT: v_mul_hi_u32 v2, v5, v2
; CGP-NEXT: v_mul_lo_u32 v2, v2, v10 ; CGP-NEXT: v_mul_lo_u32 v2, v2, v10
; CGP-NEXT: v_sub_i32_e32 v2, vcc, v5, v2 ; CGP-NEXT: v_sub_i32_e32 v2, vcc, v5, v2
; CGP-NEXT: v_sub_i32_e32 v3, vcc, v2, v10 ; CGP-NEXT: v_sub_i32_e32 v3, vcc, v2, v10
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v10 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v10
; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; CGP-NEXT: v_sub_i32_e32 v3, vcc, v2, v10 ; CGP-NEXT: v_sub_i32_e32 v3, vcc, v2, v10
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v10 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v10
; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; CGP-NEXT: v_mov_b32_e32 v3, 0 ; CGP-NEXT: v_mov_b32_e32 v3, 0
; CGP-NEXT: BB8_8: ; CGP-NEXT: .LBB8_8:
; CGP-NEXT: s_or_b64 exec, exec, s[4:5] ; CGP-NEXT: s_or_b64 exec, exec, s[4:5]
; CGP-NEXT: s_setpc_b64 s[30:31] ; CGP-NEXT: s_setpc_b64 s[30:31]
%shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y %shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
%r = urem <2 x i64> %x, %shl.y %r = urem <2 x i64> %x, %shl.y
ret <2 x i64> %r ret <2 x i64> %r
} }
define i64 @v_urem_i64_24bit(i64 %num, i64 %den) { define i64 @v_urem_i64_24bit(i64 %num, i64 %den) {
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llvm/test/CodeGen/AMDGPU/amd.endpgm.ll

Show All 29 Lines
} }
define amdgpu_kernel void @test2(i32* %p, i32 %x) { define amdgpu_kernel void @test2(i32* %p, i32 %x) {
; GFX9-LABEL: test2: ; GFX9-LABEL: test2:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dword s2, s[0:1], 0x2c ; GFX9-NEXT: s_load_dword s2, s[0:1], 0x2c
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_cmp_lt_i32 s2, 1 ; GFX9-NEXT: s_cmp_lt_i32 s2, 1
; GFX9-NEXT: s_cbranch_scc0 BB2_2 ; GFX9-NEXT: s_cbranch_scc0 .LBB2_2
; GFX9-NEXT: ; %bb.1: ; %else ; GFX9-NEXT: ; %bb.1: ; %else
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: v_mov_b32_e32 v2, s2 ; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: flat_store_dword v[0:1], v2 ; GFX9-NEXT: flat_store_dword v[0:1], v2
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; GFX9-NEXT: BB2_2: ; %then ; GFX9-NEXT: .LBB2_2: ; %then
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: test2: ; GFX10-LABEL: test2:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dword s2, s[0:1], 0x2c ; GFX10-NEXT: s_load_dword s2, s[0:1], 0x2c
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_cmp_lt_i32 s2, 1 ; GFX10-NEXT: s_cmp_lt_i32 s2, 1
; GFX10-NEXT: s_cbranch_scc0 BB2_2 ; GFX10-NEXT: s_cbranch_scc0 .LBB2_2
; GFX10-NEXT: ; %bb.1: ; %else ; GFX10-NEXT: ; %bb.1: ; %else
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX10-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-NEXT: v_mov_b32_e32 v2, s2
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: flat_store_dword v[0:1], v2 ; GFX10-NEXT: flat_store_dword v[0:1], v2
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; GFX10-NEXT: BB2_2: ; %then ; GFX10-NEXT: .LBB2_2: ; %then
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%cond = icmp sgt i32 %x, 0 %cond = icmp sgt i32 %x, 0
br i1 %cond, label %then, label %else br i1 %cond, label %then, label %else
then: then:
tail call void @llvm.amdgcn.endpgm() tail call void @llvm.amdgcn.endpgm()
unreachable unreachable
else: else:
store i32 %x, i32* %p store i32 %x, i32* %p
ret void ret void
} }
declare void @llvm.amdgcn.endpgm() declare void @llvm.amdgcn.endpgm()

llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll

Show All 13 Lines
; GFX7LESS: ; %bb.0: ; %entry ; GFX7LESS: ; %bb.0: ; %entry
; GFX7LESS-NEXT: s_mov_b64 s[6:7], exec ; GFX7LESS-NEXT: s_mov_b64 s[6:7], exec
; GFX7LESS-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GFX7LESS-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0 ; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0
; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s7, v0 ; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s7, v0
; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX7LESS-NEXT: ; implicit-def: $vgpr1 ; GFX7LESS-NEXT: ; implicit-def: $vgpr1
; GFX7LESS-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX7LESS-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX7LESS-NEXT: s_cbranch_execz BB0_2 ; GFX7LESS-NEXT: s_cbranch_execz .LBB0_2
; GFX7LESS-NEXT: ; %bb.1: ; GFX7LESS-NEXT: ; %bb.1:
; GFX7LESS-NEXT: s_mov_b32 s11, 0xf000 ; GFX7LESS-NEXT: s_mov_b32 s11, 0xf000
; GFX7LESS-NEXT: s_bcnt1_i32_b64 s6, s[6:7] ; GFX7LESS-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
; GFX7LESS-NEXT: s_mul_i32 s6, s6, 5 ; GFX7LESS-NEXT: s_mul_i32 s6, s6, 5
; GFX7LESS-NEXT: s_mov_b32 s10, -1 ; GFX7LESS-NEXT: s_mov_b32 s10, -1
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: s_mov_b32 s8, s2 ; GFX7LESS-NEXT: s_mov_b32 s8, s2
; GFX7LESS-NEXT: s_mov_b32 s9, s3 ; GFX7LESS-NEXT: s_mov_b32 s9, s3
; GFX7LESS-NEXT: v_mov_b32_e32 v1, s6 ; GFX7LESS-NEXT: v_mov_b32_e32 v1, s6
; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX7LESS-NEXT: buffer_atomic_add v1, off, s[8:11], 0 glc ; GFX7LESS-NEXT: buffer_atomic_add v1, off, s[8:11], 0 glc
; GFX7LESS-NEXT: s_waitcnt vmcnt(0) ; GFX7LESS-NEXT: s_waitcnt vmcnt(0)
; GFX7LESS-NEXT: buffer_wbinvl1 ; GFX7LESS-NEXT: buffer_wbinvl1
; GFX7LESS-NEXT: BB0_2: ; GFX7LESS-NEXT: .LBB0_2:
; GFX7LESS-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX7LESS-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000 ; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000
; GFX7LESS-NEXT: s_mov_b32 s2, -1 ; GFX7LESS-NEXT: s_mov_b32 s2, -1
; GFX7LESS-NEXT: v_readfirstlane_b32 s4, v1 ; GFX7LESS-NEXT: v_readfirstlane_b32 s4, v1
; GFX7LESS-NEXT: v_mad_u32_u24 v0, v0, 5, s4 ; GFX7LESS-NEXT: v_mad_u32_u24 v0, v0, 5, s4
; GFX7LESS-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX7LESS-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7LESS-NEXT: s_endpgm ; GFX7LESS-NEXT: s_endpgm
; ;
; GFX89-LABEL: add_i32_constant: ; GFX89-LABEL: add_i32_constant:
; GFX89: ; %bb.0: ; %entry ; GFX89: ; %bb.0: ; %entry
; GFX89-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX89-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX89-NEXT: s_mov_b64 s[6:7], exec ; GFX89-NEXT: s_mov_b64 s[6:7], exec
; GFX89-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0 ; GFX89-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
; GFX89-NEXT: v_mbcnt_hi_u32_b32 v0, s7, v0 ; GFX89-NEXT: v_mbcnt_hi_u32_b32 v0, s7, v0
; GFX89-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX89-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX89-NEXT: ; implicit-def: $vgpr1 ; GFX89-NEXT: ; implicit-def: $vgpr1
; GFX89-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX89-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX89-NEXT: s_cbranch_execz BB0_2 ; GFX89-NEXT: s_cbranch_execz .LBB0_2
; GFX89-NEXT: ; %bb.1: ; GFX89-NEXT: ; %bb.1:
; GFX89-NEXT: s_waitcnt lgkmcnt(0) ; GFX89-NEXT: s_waitcnt lgkmcnt(0)
; GFX89-NEXT: s_mov_b32 s8, s2 ; GFX89-NEXT: s_mov_b32 s8, s2
; GFX89-NEXT: s_bcnt1_i32_b64 s2, s[6:7] ; GFX89-NEXT: s_bcnt1_i32_b64 s2, s[6:7]
; GFX89-NEXT: s_mul_i32 s2, s2, 5 ; GFX89-NEXT: s_mul_i32 s2, s2, 5
; GFX89-NEXT: s_mov_b32 s11, 0xf000 ; GFX89-NEXT: s_mov_b32 s11, 0xf000
; GFX89-NEXT: s_mov_b32 s10, -1 ; GFX89-NEXT: s_mov_b32 s10, -1
; GFX89-NEXT: s_mov_b32 s9, s3 ; GFX89-NEXT: s_mov_b32 s9, s3
; GFX89-NEXT: v_mov_b32_e32 v1, s2 ; GFX89-NEXT: v_mov_b32_e32 v1, s2
; GFX89-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX89-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX89-NEXT: buffer_atomic_add v1, off, s[8:11], 0 glc ; GFX89-NEXT: buffer_atomic_add v1, off, s[8:11], 0 glc
; GFX89-NEXT: s_waitcnt vmcnt(0) ; GFX89-NEXT: s_waitcnt vmcnt(0)
; GFX89-NEXT: buffer_wbinvl1_vol ; GFX89-NEXT: buffer_wbinvl1_vol
; GFX89-NEXT: BB0_2: ; GFX89-NEXT: .LBB0_2:
; GFX89-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX89-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX89-NEXT: v_readfirstlane_b32 s4, v1 ; GFX89-NEXT: v_readfirstlane_b32 s4, v1
; GFX89-NEXT: s_waitcnt lgkmcnt(0) ; GFX89-NEXT: s_waitcnt lgkmcnt(0)
; GFX89-NEXT: s_mov_b32 s3, 0xf000 ; GFX89-NEXT: s_mov_b32 s3, 0xf000
; GFX89-NEXT: s_mov_b32 s2, -1 ; GFX89-NEXT: s_mov_b32 s2, -1
; GFX89-NEXT: v_mad_u32_u24 v0, v0, 5, s4 ; GFX89-NEXT: v_mad_u32_u24 v0, v0, 5, s4
; GFX89-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX89-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX89-NEXT: s_endpgm ; GFX89-NEXT: s_endpgm
; ;
; GFX1064-LABEL: add_i32_constant: ; GFX1064-LABEL: add_i32_constant:
; GFX1064: ; %bb.0: ; %entry ; GFX1064: ; %bb.0: ; %entry
; GFX1064-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX1064-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX1064-NEXT: s_mov_b64 s[6:7], exec ; GFX1064-NEXT: s_mov_b64 s[6:7], exec
; GFX1064-NEXT: ; implicit-def: $vgpr1 ; GFX1064-NEXT: ; implicit-def: $vgpr1
; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, s7, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, s7, v0
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX1064-NEXT: s_cbranch_execz BB0_2 ; GFX1064-NEXT: s_cbranch_execz .LBB0_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: s_bcnt1_i32_b64 s6, s[6:7] ; GFX1064-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
; GFX1064-NEXT: s_mov_b32 s11, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s11, 0x31016000
; GFX1064-NEXT: s_mul_i32 s6, s6, 5 ; GFX1064-NEXT: s_mul_i32 s6, s6, 5
; GFX1064-NEXT: s_mov_b32 s10, -1 ; GFX1064-NEXT: s_mov_b32 s10, -1
; GFX1064-NEXT: v_mov_b32_e32 v1, s6 ; GFX1064-NEXT: v_mov_b32_e32 v1, s6
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: s_mov_b32 s8, s2 ; GFX1064-NEXT: s_mov_b32 s8, s2
; GFX1064-NEXT: s_mov_b32 s9, s3 ; GFX1064-NEXT: s_mov_b32 s9, s3
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: buffer_atomic_add v1, off, s[8:11], 0 glc ; GFX1064-NEXT: buffer_atomic_add v1, off, s[8:11], 0 glc
; GFX1064-NEXT: s_waitcnt vmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: buffer_gl1_inv ; GFX1064-NEXT: buffer_gl1_inv
; GFX1064-NEXT: BB0_2: ; GFX1064-NEXT: .LBB0_2:
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: v_readfirstlane_b32 s2, v1 ; GFX1064-NEXT: v_readfirstlane_b32 s2, v1
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064-NEXT: v_mad_u32_u24 v0, v0, 5, s2 ; GFX1064-NEXT: v_mad_u32_u24 v0, v0, 5, s2
; GFX1064-NEXT: s_mov_b32 s2, -1 ; GFX1064-NEXT: s_mov_b32 s2, -1
; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: s_endpgm
; ;
; GFX1032-LABEL: add_i32_constant: ; GFX1032-LABEL: add_i32_constant:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX1032-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX1032-NEXT: s_mov_b32 s5, exec_lo ; GFX1032-NEXT: s_mov_b32 s5, exec_lo
; GFX1032-NEXT: ; implicit-def: $vgpr1 ; GFX1032-NEXT: ; implicit-def: $vgpr1
; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, s5, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, s5, 0
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: s_and_saveexec_b32 s4, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s4, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB0_2 ; GFX1032-NEXT: s_cbranch_execz .LBB0_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: s_bcnt1_i32_b32 s5, s5 ; GFX1032-NEXT: s_bcnt1_i32_b32 s5, s5
; GFX1032-NEXT: s_mov_b32 s11, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s11, 0x31016000
; GFX1032-NEXT: s_mul_i32 s5, s5, 5 ; GFX1032-NEXT: s_mul_i32 s5, s5, 5
; GFX1032-NEXT: s_mov_b32 s10, -1 ; GFX1032-NEXT: s_mov_b32 s10, -1
; GFX1032-NEXT: v_mov_b32_e32 v1, s5 ; GFX1032-NEXT: v_mov_b32_e32 v1, s5
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: s_mov_b32 s8, s2 ; GFX1032-NEXT: s_mov_b32 s8, s2
; GFX1032-NEXT: s_mov_b32 s9, s3 ; GFX1032-NEXT: s_mov_b32 s9, s3
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: buffer_atomic_add v1, off, s[8:11], 0 glc ; GFX1032-NEXT: buffer_atomic_add v1, off, s[8:11], 0 glc
; GFX1032-NEXT: s_waitcnt vmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: buffer_gl1_inv ; GFX1032-NEXT: buffer_gl1_inv
; GFX1032-NEXT: BB0_2: ; GFX1032-NEXT: .LBB0_2:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: v_readfirstlane_b32 s2, v1 ; GFX1032-NEXT: v_readfirstlane_b32 s2, v1
; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s3, 0x31016000
; GFX1032-NEXT: v_mad_u32_u24 v0, v0, 5, s2 ; GFX1032-NEXT: v_mad_u32_u24 v0, v0, 5, s2
; GFX1032-NEXT: s_mov_b32 s2, -1 ; GFX1032-NEXT: s_mov_b32 s2, -1
; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX7LESS-NEXT: s_mov_b64 s[2:3], exec ; GFX7LESS-NEXT: s_mov_b64 s[2:3], exec
; GFX7LESS-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GFX7LESS-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GFX7LESS-NEXT: s_load_dword s8, s[0:1], 0xd ; GFX7LESS-NEXT: s_load_dword s8, s[0:1], 0xd
; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 ; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0
; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s3, v0 ; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s3, v0
; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX7LESS-NEXT: ; implicit-def: $vgpr1 ; GFX7LESS-NEXT: ; implicit-def: $vgpr1
; GFX7LESS-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX7LESS-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX7LESS-NEXT: s_cbranch_execz BB1_2 ; GFX7LESS-NEXT: s_cbranch_execz .LBB1_2
; GFX7LESS-NEXT: ; %bb.1: ; GFX7LESS-NEXT: ; %bb.1:
; GFX7LESS-NEXT: s_mov_b32 s15, 0xf000 ; GFX7LESS-NEXT: s_mov_b32 s15, 0xf000
; GFX7LESS-NEXT: s_bcnt1_i32_b64 s2, s[2:3] ; GFX7LESS-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: s_mul_i32 s2, s8, s2 ; GFX7LESS-NEXT: s_mul_i32 s2, s8, s2
; GFX7LESS-NEXT: s_mov_b32 s14, -1 ; GFX7LESS-NEXT: s_mov_b32 s14, -1
; GFX7LESS-NEXT: s_mov_b32 s12, s6 ; GFX7LESS-NEXT: s_mov_b32 s12, s6
; GFX7LESS-NEXT: s_mov_b32 s13, s7 ; GFX7LESS-NEXT: s_mov_b32 s13, s7
; GFX7LESS-NEXT: v_mov_b32_e32 v1, s2 ; GFX7LESS-NEXT: v_mov_b32_e32 v1, s2
; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX7LESS-NEXT: buffer_atomic_add v1, off, s[12:15], 0 glc ; GFX7LESS-NEXT: buffer_atomic_add v1, off, s[12:15], 0 glc
; GFX7LESS-NEXT: s_waitcnt vmcnt(0) ; GFX7LESS-NEXT: s_waitcnt vmcnt(0)
; GFX7LESS-NEXT: buffer_wbinvl1 ; GFX7LESS-NEXT: buffer_wbinvl1
; GFX7LESS-NEXT: BB1_2: ; GFX7LESS-NEXT: .LBB1_2:
; GFX7LESS-NEXT: s_or_b64 exec, exec, s[0:1] ; GFX7LESS-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: s_mov_b32 s7, 0xf000 ; GFX7LESS-NEXT: s_mov_b32 s7, 0xf000
; GFX7LESS-NEXT: s_mov_b32 s6, -1 ; GFX7LESS-NEXT: s_mov_b32 s6, -1
; GFX7LESS-NEXT: v_readfirstlane_b32 s0, v1 ; GFX7LESS-NEXT: v_readfirstlane_b32 s0, v1
; GFX7LESS-NEXT: v_mul_lo_u32 v0, s8, v0 ; GFX7LESS-NEXT: v_mul_lo_u32 v0, s8, v0
; GFX7LESS-NEXT: v_add_i32_e32 v0, vcc, s0, v0 ; GFX7LESS-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; GFX7LESS-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GFX7LESS-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX7LESS-NEXT: s_endpgm ; GFX7LESS-NEXT: s_endpgm
; ;
; GFX8-LABEL: add_i32_uniform: ; GFX8-LABEL: add_i32_uniform:
; GFX8: ; %bb.0: ; %entry ; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX8-NEXT: s_load_dword s8, s[0:1], 0x34 ; GFX8-NEXT: s_load_dword s8, s[0:1], 0x34
; GFX8-NEXT: s_mov_b64 s[2:3], exec ; GFX8-NEXT: s_mov_b64 s[2:3], exec
; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 ; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 ; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX8-NEXT: ; implicit-def: $vgpr1 ; GFX8-NEXT: ; implicit-def: $vgpr1
; GFX8-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX8-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX8-NEXT: s_cbranch_execz BB1_2 ; GFX8-NEXT: s_cbranch_execz .LBB1_2
; GFX8-NEXT: ; %bb.1: ; GFX8-NEXT: ; %bb.1:
; GFX8-NEXT: s_bcnt1_i32_b64 s2, s[2:3] ; GFX8-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_mul_i32 s2, s8, s2 ; GFX8-NEXT: s_mul_i32 s2, s8, s2
; GFX8-NEXT: s_mov_b32 s15, 0xf000 ; GFX8-NEXT: s_mov_b32 s15, 0xf000
; GFX8-NEXT: s_mov_b32 s14, -1 ; GFX8-NEXT: s_mov_b32 s14, -1
; GFX8-NEXT: s_mov_b32 s12, s6 ; GFX8-NEXT: s_mov_b32 s12, s6
; GFX8-NEXT: s_mov_b32 s13, s7 ; GFX8-NEXT: s_mov_b32 s13, s7
; GFX8-NEXT: v_mov_b32_e32 v1, s2 ; GFX8-NEXT: v_mov_b32_e32 v1, s2
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_atomic_add v1, off, s[12:15], 0 glc ; GFX8-NEXT: buffer_atomic_add v1, off, s[12:15], 0 glc
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1_vol ; GFX8-NEXT: buffer_wbinvl1_vol
; GFX8-NEXT: BB1_2: ; GFX8-NEXT: .LBB1_2:
; GFX8-NEXT: s_or_b64 exec, exec, s[0:1] ; GFX8-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mul_lo_u32 v0, s8, v0 ; GFX8-NEXT: v_mul_lo_u32 v0, s8, v0
; GFX8-NEXT: v_readfirstlane_b32 s0, v1 ; GFX8-NEXT: v_readfirstlane_b32 s0, v1
; GFX8-NEXT: s_mov_b32 s7, 0xf000 ; GFX8-NEXT: s_mov_b32 s7, 0xf000
; GFX8-NEXT: s_mov_b32 s6, -1 ; GFX8-NEXT: s_mov_b32 s6, -1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0
; GFX8-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GFX8-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-LABEL: add_i32_uniform: ; GFX9-LABEL: add_i32_uniform:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_load_dword s8, s[0:1], 0x34 ; GFX9-NEXT: s_load_dword s8, s[0:1], 0x34
; GFX9-NEXT: s_mov_b64 s[2:3], exec ; GFX9-NEXT: s_mov_b64 s[2:3], exec
; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 ; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 ; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-NEXT: ; implicit-def: $vgpr1 ; GFX9-NEXT: ; implicit-def: $vgpr1
; GFX9-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX9-NEXT: s_cbranch_execz BB1_2 ; GFX9-NEXT: s_cbranch_execz .LBB1_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: s_bcnt1_i32_b64 s2, s[2:3] ; GFX9-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mul_i32 s2, s8, s2 ; GFX9-NEXT: s_mul_i32 s2, s8, s2
; GFX9-NEXT: s_mov_b32 s15, 0xf000 ; GFX9-NEXT: s_mov_b32 s15, 0xf000
; GFX9-NEXT: s_mov_b32 s14, -1 ; GFX9-NEXT: s_mov_b32 s14, -1
; GFX9-NEXT: s_mov_b32 s12, s6 ; GFX9-NEXT: s_mov_b32 s12, s6
; GFX9-NEXT: s_mov_b32 s13, s7 ; GFX9-NEXT: s_mov_b32 s13, s7
; GFX9-NEXT: v_mov_b32_e32 v1, s2 ; GFX9-NEXT: v_mov_b32_e32 v1, s2
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_atomic_add v1, off, s[12:15], 0 glc ; GFX9-NEXT: buffer_atomic_add v1, off, s[12:15], 0 glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: buffer_wbinvl1_vol ; GFX9-NEXT: buffer_wbinvl1_vol
; GFX9-NEXT: BB1_2: ; GFX9-NEXT: .LBB1_2:
; GFX9-NEXT: s_or_b64 exec, exec, s[0:1] ; GFX9-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mul_lo_u32 v0, s8, v0 ; GFX9-NEXT: v_mul_lo_u32 v0, s8, v0
; GFX9-NEXT: v_readfirstlane_b32 s0, v1 ; GFX9-NEXT: v_readfirstlane_b32 s0, v1
; GFX9-NEXT: s_mov_b32 s7, 0xf000 ; GFX9-NEXT: s_mov_b32 s7, 0xf000
; GFX9-NEXT: s_mov_b32 s6, -1 ; GFX9-NEXT: s_mov_b32 s6, -1
; GFX9-NEXT: v_add_u32_e32 v0, s0, v0 ; GFX9-NEXT: v_add_u32_e32 v0, s0, v0
; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX1064-LABEL: add_i32_uniform: ; GFX1064-LABEL: add_i32_uniform:
; GFX1064: ; %bb.0: ; %entry ; GFX1064: ; %bb.0: ; %entry
; GFX1064-NEXT: s_clause 0x1 ; GFX1064-NEXT: s_clause 0x1
; GFX1064-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX1064-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX1064-NEXT: s_load_dword s8, s[0:1], 0x34 ; GFX1064-NEXT: s_load_dword s8, s[0:1], 0x34
; GFX1064-NEXT: s_mov_b64 s[2:3], exec ; GFX1064-NEXT: s_mov_b64 s[2:3], exec
; GFX1064-NEXT: ; implicit-def: $vgpr1 ; GFX1064-NEXT: ; implicit-def: $vgpr1
; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064-NEXT: s_cbranch_execz BB1_2 ; GFX1064-NEXT: s_cbranch_execz .LBB1_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: s_bcnt1_i32_b64 s2, s[2:3] ; GFX1064-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX1064-NEXT: s_mov_b32 s15, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s15, 0x31016000
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: s_mul_i32 s2, s8, s2 ; GFX1064-NEXT: s_mul_i32 s2, s8, s2
; GFX1064-NEXT: s_mov_b32 s14, -1 ; GFX1064-NEXT: s_mov_b32 s14, -1
; GFX1064-NEXT: v_mov_b32_e32 v1, s2 ; GFX1064-NEXT: v_mov_b32_e32 v1, s2
; GFX1064-NEXT: s_mov_b32 s12, s6 ; GFX1064-NEXT: s_mov_b32 s12, s6
; GFX1064-NEXT: s_mov_b32 s13, s7 ; GFX1064-NEXT: s_mov_b32 s13, s7
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: buffer_atomic_add v1, off, s[12:15], 0 glc ; GFX1064-NEXT: buffer_atomic_add v1, off, s[12:15], 0 glc
; GFX1064-NEXT: s_waitcnt vmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: buffer_gl1_inv ; GFX1064-NEXT: buffer_gl1_inv
; GFX1064-NEXT: BB1_2: ; GFX1064-NEXT: .LBB1_2:
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[0:1] ; GFX1064-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: v_mul_lo_u32 v0, s8, v0 ; GFX1064-NEXT: v_mul_lo_u32 v0, s8, v0
; GFX1064-NEXT: v_readfirstlane_b32 s0, v1 ; GFX1064-NEXT: v_readfirstlane_b32 s0, v1
; GFX1064-NEXT: s_mov_b32 s7, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s7, 0x31016000
; GFX1064-NEXT: s_mov_b32 s6, -1 ; GFX1064-NEXT: s_mov_b32 s6, -1
; GFX1064-NEXT: v_add_nc_u32_e32 v0, s0, v0 ; GFX1064-NEXT: v_add_nc_u32_e32 v0, s0, v0
; GFX1064-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GFX1064-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: s_endpgm
; ;
; GFX1032-LABEL: add_i32_uniform: ; GFX1032-LABEL: add_i32_uniform:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_clause 0x1 ; GFX1032-NEXT: s_clause 0x1
; GFX1032-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX1032-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX1032-NEXT: s_load_dword s2, s[0:1], 0x34 ; GFX1032-NEXT: s_load_dword s2, s[0:1], 0x34
; GFX1032-NEXT: s_mov_b32 s3, exec_lo ; GFX1032-NEXT: s_mov_b32 s3, exec_lo
; GFX1032-NEXT: ; implicit-def: $vgpr1 ; GFX1032-NEXT: ; implicit-def: $vgpr1
; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, s3, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, s3, 0
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: s_and_saveexec_b32 s0, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB1_2 ; GFX1032-NEXT: s_cbranch_execz .LBB1_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: s_bcnt1_i32_b32 s1, s3 ; GFX1032-NEXT: s_bcnt1_i32_b32 s1, s3
; GFX1032-NEXT: s_mov_b32 s11, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s11, 0x31016000
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: s_mul_i32 s1, s2, s1 ; GFX1032-NEXT: s_mul_i32 s1, s2, s1
; GFX1032-NEXT: s_mov_b32 s10, -1 ; GFX1032-NEXT: s_mov_b32 s10, -1
; GFX1032-NEXT: v_mov_b32_e32 v1, s1 ; GFX1032-NEXT: v_mov_b32_e32 v1, s1
; GFX1032-NEXT: s_mov_b32 s8, s6 ; GFX1032-NEXT: s_mov_b32 s8, s6
; GFX1032-NEXT: s_mov_b32 s9, s7 ; GFX1032-NEXT: s_mov_b32 s9, s7
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: buffer_atomic_add v1, off, s[8:11], 0 glc ; GFX1032-NEXT: buffer_atomic_add v1, off, s[8:11], 0 glc
; GFX1032-NEXT: s_waitcnt vmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: buffer_gl1_inv ; GFX1032-NEXT: buffer_gl1_inv
; GFX1032-NEXT: BB1_2: ; GFX1032-NEXT: .LBB1_2:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s0 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: v_mul_lo_u32 v0, s2, v0 ; GFX1032-NEXT: v_mul_lo_u32 v0, s2, v0
; GFX1032-NEXT: v_readfirstlane_b32 s0, v1 ; GFX1032-NEXT: v_readfirstlane_b32 s0, v1
; GFX1032-NEXT: s_mov_b32 s7, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s7, 0x31016000
; GFX1032-NEXT: s_mov_b32 s6, -1 ; GFX1032-NEXT: s_mov_b32 s6, -1
; GFX1032-NEXT: v_add_nc_u32_e32 v0, s0, v0 ; GFX1032-NEXT: v_add_nc_u32_e32 v0, s0, v0
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX8-NEXT: v_readlane_b32 s6, v2, 63 ; GFX8-NEXT: v_readlane_b32 s6, v2, 63
; GFX8-NEXT: s_nop 0 ; GFX8-NEXT: s_nop 0
; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf ; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX8-NEXT: s_mov_b64 exec, s[4:5] ; GFX8-NEXT: s_mov_b64 exec, s[4:5]
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX8-NEXT: ; implicit-def: $vgpr0 ; GFX8-NEXT: ; implicit-def: $vgpr0
; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX8-NEXT: s_cbranch_execz BB2_2 ; GFX8-NEXT: s_cbranch_execz .LBB2_2
; GFX8-NEXT: ; %bb.1: ; GFX8-NEXT: ; %bb.1:
; GFX8-NEXT: s_mov_b32 s11, 0xf000 ; GFX8-NEXT: s_mov_b32 s11, 0xf000
; GFX8-NEXT: s_mov_b32 s10, -1 ; GFX8-NEXT: s_mov_b32 s10, -1
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_mov_b32 s8, s2 ; GFX8-NEXT: s_mov_b32 s8, s2
; GFX8-NEXT: s_mov_b32 s9, s3 ; GFX8-NEXT: s_mov_b32 s9, s3
; GFX8-NEXT: v_mov_b32_e32 v0, s6 ; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_atomic_add v0, off, s[8:11], 0 glc ; GFX8-NEXT: buffer_atomic_add v0, off, s[8:11], 0 glc
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1_vol ; GFX8-NEXT: buffer_wbinvl1_vol
; GFX8-NEXT: BB2_2: ; GFX8-NEXT: .LBB2_2:
; GFX8-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX8-NEXT: v_readfirstlane_b32 s4, v0 ; GFX8-NEXT: v_readfirstlane_b32 s4, v0
; GFX8-NEXT: v_mov_b32_e32 v0, v1 ; GFX8-NEXT: v_mov_b32_e32 v0, v1
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_mov_b32 s3, 0xf000 ; GFX8-NEXT: s_mov_b32 s3, 0xf000
; GFX8-NEXT: s_mov_b32 s2, -1 ; GFX8-NEXT: s_mov_b32 s2, -1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v0 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v0
; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9-NEXT: v_readlane_b32 s6, v2, 63 ; GFX9-NEXT: v_readlane_b32 s6, v2, 63
; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: s_nop 0
; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf ; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX9-NEXT: s_mov_b64 exec, s[4:5] ; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-NEXT: ; implicit-def: $vgpr0 ; GFX9-NEXT: ; implicit-def: $vgpr0
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_cbranch_execz BB2_2 ; GFX9-NEXT: s_cbranch_execz .LBB2_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: s_mov_b32 s11, 0xf000 ; GFX9-NEXT: s_mov_b32 s11, 0xf000
; GFX9-NEXT: s_mov_b32 s10, -1 ; GFX9-NEXT: s_mov_b32 s10, -1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s8, s2 ; GFX9-NEXT: s_mov_b32 s8, s2
; GFX9-NEXT: s_mov_b32 s9, s3 ; GFX9-NEXT: s_mov_b32 s9, s3
; GFX9-NEXT: v_mov_b32_e32 v0, s6 ; GFX9-NEXT: v_mov_b32_e32 v0, s6
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_atomic_add v0, off, s[8:11], 0 glc ; GFX9-NEXT: buffer_atomic_add v0, off, s[8:11], 0 glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: buffer_wbinvl1_vol ; GFX9-NEXT: buffer_wbinvl1_vol
; GFX9-NEXT: BB2_2: ; GFX9-NEXT: .LBB2_2:
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: v_readfirstlane_b32 s4, v0 ; GFX9-NEXT: v_readfirstlane_b32 s4, v0
; GFX9-NEXT: v_mov_b32_e32 v0, v1 ; GFX9-NEXT: v_mov_b32_e32 v0, v1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: v_add_u32_e32 v0, s4, v0 ; GFX9-NEXT: v_add_u32_e32 v0, s4, v0
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX1064-NEXT: s_or_saveexec_b64 s[6:7], -1 ; GFX1064-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX1064-NEXT: s_mov_b32 s4, s9 ; GFX1064-NEXT: s_mov_b32 s4, s9
; GFX1064-NEXT: v_writelane_b32 v3, s8, 48 ; GFX1064-NEXT: v_writelane_b32 v3, s8, 48
; GFX1064-NEXT: s_mov_b64 exec, s[6:7] ; GFX1064-NEXT: s_mov_b64 exec, s[6:7]
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: s_mov_b32 s6, -1 ; GFX1064-NEXT: s_mov_b32 s6, -1
; GFX1064-NEXT: ; implicit-def: $vgpr0 ; GFX1064-NEXT: ; implicit-def: $vgpr0
; GFX1064-NEXT: s_and_saveexec_b64 s[8:9], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[8:9], vcc
; GFX1064-NEXT: s_cbranch_execz BB2_2 ; GFX1064-NEXT: s_cbranch_execz .LBB2_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: v_mov_b32_e32 v0, s4 ; GFX1064-NEXT: v_mov_b32_e32 v0, s4
; GFX1064-NEXT: s_mov_b32 s7, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s7, 0x31016000
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: s_mov_b32 s4, s2 ; GFX1064-NEXT: s_mov_b32 s4, s2
; GFX1064-NEXT: s_mov_b32 s5, s3 ; GFX1064-NEXT: s_mov_b32 s5, s3
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: buffer_atomic_add v0, off, s[4:7], 0 glc ; GFX1064-NEXT: buffer_atomic_add v0, off, s[4:7], 0 glc
; GFX1064-NEXT: s_waitcnt vmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: buffer_gl1_inv ; GFX1064-NEXT: buffer_gl1_inv
; GFX1064-NEXT: BB2_2: ; GFX1064-NEXT: .LBB2_2:
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[8:9] ; GFX1064-NEXT: s_or_b64 exec, exec, s[8:9]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: v_readfirstlane_b32 s2, v0 ; GFX1064-NEXT: v_readfirstlane_b32 s2, v0
; GFX1064-NEXT: v_mov_b32_e32 v0, v3 ; GFX1064-NEXT: v_mov_b32_e32 v0, v3
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064-NEXT: v_add_nc_u32_e32 v0, s2, v0 ; GFX1064-NEXT: v_add_nc_u32_e32 v0, s2, v0
; GFX1064-NEXT: s_mov_b32 s2, s6 ; GFX1064-NEXT: s_mov_b32 s2, s6
Show All 26 Lines
; GFX1032-NEXT: s_or_saveexec_b32 s4, -1 ; GFX1032-NEXT: s_or_saveexec_b32 s4, -1
; GFX1032-NEXT: v_writelane_b32 v3, s5, 16 ; GFX1032-NEXT: v_writelane_b32 v3, s5, 16
; GFX1032-NEXT: s_mov_b32 exec_lo, s4 ; GFX1032-NEXT: s_mov_b32 exec_lo, s4
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: s_mov_b32 s4, s6 ; GFX1032-NEXT: s_mov_b32 s4, s6
; GFX1032-NEXT: s_mov_b32 s6, -1 ; GFX1032-NEXT: s_mov_b32 s6, -1
; GFX1032-NEXT: ; implicit-def: $vgpr0 ; GFX1032-NEXT: ; implicit-def: $vgpr0
; GFX1032-NEXT: s_and_saveexec_b32 s8, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s8, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB2_2 ; GFX1032-NEXT: s_cbranch_execz .LBB2_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: v_mov_b32_e32 v0, s4 ; GFX1032-NEXT: v_mov_b32_e32 v0, s4
; GFX1032-NEXT: s_mov_b32 s7, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s7, 0x31016000
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: s_mov_b32 s4, s2 ; GFX1032-NEXT: s_mov_b32 s4, s2
; GFX1032-NEXT: s_mov_b32 s5, s3 ; GFX1032-NEXT: s_mov_b32 s5, s3
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: buffer_atomic_add v0, off, s[4:7], 0 glc ; GFX1032-NEXT: buffer_atomic_add v0, off, s[4:7], 0 glc
; GFX1032-NEXT: s_waitcnt vmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: buffer_gl1_inv ; GFX1032-NEXT: buffer_gl1_inv
; GFX1032-NEXT: BB2_2: ; GFX1032-NEXT: .LBB2_2:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s8 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s8
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: v_readfirstlane_b32 s2, v0 ; GFX1032-NEXT: v_readfirstlane_b32 s2, v0
; GFX1032-NEXT: v_mov_b32_e32 v0, v3 ; GFX1032-NEXT: v_mov_b32_e32 v0, v3
; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s3, 0x31016000
; GFX1032-NEXT: v_add_nc_u32_e32 v0, s2, v0 ; GFX1032-NEXT: v_add_nc_u32_e32 v0, s2, v0
; GFX1032-NEXT: s_mov_b32 s2, s6 ; GFX1032-NEXT: s_mov_b32 s2, s6
Show All 11 Lines
; GFX7LESS: ; %bb.0: ; %entry ; GFX7LESS: ; %bb.0: ; %entry
; GFX7LESS-NEXT: s_mov_b64 s[6:7], exec ; GFX7LESS-NEXT: s_mov_b64 s[6:7], exec
; GFX7LESS-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GFX7LESS-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0 ; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0
; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v2, s7, v0 ; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v2, s7, v0
; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX7LESS-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX7LESS-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX7LESS-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX7LESS-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX7LESS-NEXT: s_cbranch_execz BB3_2 ; GFX7LESS-NEXT: s_cbranch_execz .LBB3_2
; GFX7LESS-NEXT: ; %bb.1: ; GFX7LESS-NEXT: ; %bb.1:
; GFX7LESS-NEXT: s_mov_b32 s11, 0xf000 ; GFX7LESS-NEXT: s_mov_b32 s11, 0xf000
; GFX7LESS-NEXT: s_bcnt1_i32_b64 s6, s[6:7] ; GFX7LESS-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
; GFX7LESS-NEXT: s_mul_i32 s6, s6, 5 ; GFX7LESS-NEXT: s_mul_i32 s6, s6, 5
; GFX7LESS-NEXT: s_mov_b32 s10, -1 ; GFX7LESS-NEXT: s_mov_b32 s10, -1
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: s_mov_b32 s8, s2 ; GFX7LESS-NEXT: s_mov_b32 s8, s2
; GFX7LESS-NEXT: s_mov_b32 s9, s3 ; GFX7LESS-NEXT: s_mov_b32 s9, s3
; GFX7LESS-NEXT: v_mov_b32_e32 v0, s6 ; GFX7LESS-NEXT: v_mov_b32_e32 v0, s6
; GFX7LESS-NEXT: v_mov_b32_e32 v1, 0 ; GFX7LESS-NEXT: v_mov_b32_e32 v1, 0
; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX7LESS-NEXT: buffer_atomic_add_x2 v[0:1], off, s[8:11], 0 glc ; GFX7LESS-NEXT: buffer_atomic_add_x2 v[0:1], off, s[8:11], 0 glc
; GFX7LESS-NEXT: s_waitcnt vmcnt(0) ; GFX7LESS-NEXT: s_waitcnt vmcnt(0)
; GFX7LESS-NEXT: buffer_wbinvl1 ; GFX7LESS-NEXT: buffer_wbinvl1
; GFX7LESS-NEXT: BB3_2: ; GFX7LESS-NEXT: .LBB3_2:
; GFX7LESS-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX7LESS-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000 ; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000
; GFX7LESS-NEXT: s_mov_b32 s2, -1 ; GFX7LESS-NEXT: s_mov_b32 s2, -1
; GFX7LESS-NEXT: v_readfirstlane_b32 s4, v0 ; GFX7LESS-NEXT: v_readfirstlane_b32 s4, v0
; GFX7LESS-NEXT: v_readfirstlane_b32 s5, v1 ; GFX7LESS-NEXT: v_readfirstlane_b32 s5, v1
; GFX7LESS-NEXT: s_waitcnt expcnt(0) ; GFX7LESS-NEXT: s_waitcnt expcnt(0)
; GFX7LESS-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v2 ; GFX7LESS-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v2
; GFX7LESS-NEXT: v_mul_u32_u24_e32 v0, 5, v2 ; GFX7LESS-NEXT: v_mul_u32_u24_e32 v0, 5, v2
; GFX7LESS-NEXT: v_mov_b32_e32 v2, s5 ; GFX7LESS-NEXT: v_mov_b32_e32 v2, s5
; GFX7LESS-NEXT: v_add_i32_e32 v0, vcc, s4, v0 ; GFX7LESS-NEXT: v_add_i32_e32 v0, vcc, s4, v0
; GFX7LESS-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc ; GFX7LESS-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc
; GFX7LESS-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX7LESS-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX7LESS-NEXT: s_endpgm ; GFX7LESS-NEXT: s_endpgm
; ;
; GFX89-LABEL: add_i64_constant: ; GFX89-LABEL: add_i64_constant:
; GFX89: ; %bb.0: ; %entry ; GFX89: ; %bb.0: ; %entry
; GFX89-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX89-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX89-NEXT: s_mov_b64 s[6:7], exec ; GFX89-NEXT: s_mov_b64 s[6:7], exec
; GFX89-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0 ; GFX89-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
; GFX89-NEXT: v_mbcnt_hi_u32_b32 v2, s7, v0 ; GFX89-NEXT: v_mbcnt_hi_u32_b32 v2, s7, v0
; GFX89-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX89-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX89-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX89-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX89-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX89-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX89-NEXT: s_cbranch_execz BB3_2 ; GFX89-NEXT: s_cbranch_execz .LBB3_2
; GFX89-NEXT: ; %bb.1: ; GFX89-NEXT: ; %bb.1:
; GFX89-NEXT: s_waitcnt lgkmcnt(0) ; GFX89-NEXT: s_waitcnt lgkmcnt(0)
; GFX89-NEXT: s_mov_b32 s8, s2 ; GFX89-NEXT: s_mov_b32 s8, s2
; GFX89-NEXT: s_bcnt1_i32_b64 s2, s[6:7] ; GFX89-NEXT: s_bcnt1_i32_b64 s2, s[6:7]
; GFX89-NEXT: s_mul_i32 s2, s2, 5 ; GFX89-NEXT: s_mul_i32 s2, s2, 5
; GFX89-NEXT: s_mov_b32 s11, 0xf000 ; GFX89-NEXT: s_mov_b32 s11, 0xf000
; GFX89-NEXT: s_mov_b32 s10, -1 ; GFX89-NEXT: s_mov_b32 s10, -1
; GFX89-NEXT: s_mov_b32 s9, s3 ; GFX89-NEXT: s_mov_b32 s9, s3
; GFX89-NEXT: v_mov_b32_e32 v0, s2 ; GFX89-NEXT: v_mov_b32_e32 v0, s2
; GFX89-NEXT: v_mov_b32_e32 v1, 0 ; GFX89-NEXT: v_mov_b32_e32 v1, 0
; GFX89-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX89-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX89-NEXT: buffer_atomic_add_x2 v[0:1], off, s[8:11], 0 glc ; GFX89-NEXT: buffer_atomic_add_x2 v[0:1], off, s[8:11], 0 glc
; GFX89-NEXT: s_waitcnt vmcnt(0) ; GFX89-NEXT: s_waitcnt vmcnt(0)
; GFX89-NEXT: buffer_wbinvl1_vol ; GFX89-NEXT: buffer_wbinvl1_vol
; GFX89-NEXT: BB3_2: ; GFX89-NEXT: .LBB3_2:
; GFX89-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX89-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX89-NEXT: s_waitcnt lgkmcnt(0) ; GFX89-NEXT: s_waitcnt lgkmcnt(0)
; GFX89-NEXT: v_readfirstlane_b32 s2, v0 ; GFX89-NEXT: v_readfirstlane_b32 s2, v0
; GFX89-NEXT: v_readfirstlane_b32 s3, v1 ; GFX89-NEXT: v_readfirstlane_b32 s3, v1
; GFX89-NEXT: v_mov_b32_e32 v0, s2 ; GFX89-NEXT: v_mov_b32_e32 v0, s2
; GFX89-NEXT: v_mov_b32_e32 v1, s3 ; GFX89-NEXT: v_mov_b32_e32 v1, s3
; GFX89-NEXT: v_mad_u64_u32 v[0:1], s[2:3], v2, 5, v[0:1] ; GFX89-NEXT: v_mad_u64_u32 v[0:1], s[2:3], v2, 5, v[0:1]
; GFX89-NEXT: s_mov_b32 s3, 0xf000 ; GFX89-NEXT: s_mov_b32 s3, 0xf000
; GFX89-NEXT: s_mov_b32 s2, -1 ; GFX89-NEXT: s_mov_b32 s2, -1
; GFX89-NEXT: s_nop 2 ; GFX89-NEXT: s_nop 2
; GFX89-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX89-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX89-NEXT: s_endpgm ; GFX89-NEXT: s_endpgm
; ;
; GFX1064-LABEL: add_i64_constant: ; GFX1064-LABEL: add_i64_constant:
; GFX1064: ; %bb.0: ; %entry ; GFX1064: ; %bb.0: ; %entry
; GFX1064-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX1064-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX1064-NEXT: s_mov_b64 s[6:7], exec ; GFX1064-NEXT: s_mov_b64 s[6:7], exec
; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v2, s7, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v2, s7, v0
; GFX1064-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX1064-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX1064-NEXT: s_cbranch_execz BB3_2 ; GFX1064-NEXT: s_cbranch_execz .LBB3_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: s_bcnt1_i32_b64 s6, s[6:7] ; GFX1064-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
; GFX1064-NEXT: v_mov_b32_e32 v1, 0 ; GFX1064-NEXT: v_mov_b32_e32 v1, 0
; GFX1064-NEXT: s_mul_i32 s6, s6, 5 ; GFX1064-NEXT: s_mul_i32 s6, s6, 5
; GFX1064-NEXT: s_mov_b32 s11, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s11, 0x31016000
; GFX1064-NEXT: v_mov_b32_e32 v0, s6 ; GFX1064-NEXT: v_mov_b32_e32 v0, s6
; GFX1064-NEXT: s_mov_b32 s10, -1 ; GFX1064-NEXT: s_mov_b32 s10, -1
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: s_mov_b32 s8, s2 ; GFX1064-NEXT: s_mov_b32 s8, s2
; GFX1064-NEXT: s_mov_b32 s9, s3 ; GFX1064-NEXT: s_mov_b32 s9, s3
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: buffer_atomic_add_x2 v[0:1], off, s[8:11], 0 glc ; GFX1064-NEXT: buffer_atomic_add_x2 v[0:1], off, s[8:11], 0 glc
; GFX1064-NEXT: s_waitcnt vmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: buffer_gl1_inv ; GFX1064-NEXT: buffer_gl1_inv
; GFX1064-NEXT: BB3_2: ; GFX1064-NEXT: .LBB3_2:
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: v_readfirstlane_b32 s2, v0 ; GFX1064-NEXT: v_readfirstlane_b32 s2, v0
; GFX1064-NEXT: v_readfirstlane_b32 s3, v1 ; GFX1064-NEXT: v_readfirstlane_b32 s3, v1
; GFX1064-NEXT: v_mad_u64_u32 v[0:1], s[2:3], v2, 5, s[2:3] ; GFX1064-NEXT: v_mad_u64_u32 v[0:1], s[2:3], v2, 5, s[2:3]
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064-NEXT: s_mov_b32 s2, -1 ; GFX1064-NEXT: s_mov_b32 s2, -1
; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: s_endpgm
; ;
; GFX1032-LABEL: add_i64_constant: ; GFX1032-LABEL: add_i64_constant:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX1032-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX1032-NEXT: s_mov_b32 s5, exec_lo ; GFX1032-NEXT: s_mov_b32 s5, exec_lo
; GFX1032-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX1032-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v2, s5, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v2, s5, 0
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX1032-NEXT: s_and_saveexec_b32 s4, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s4, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB3_2 ; GFX1032-NEXT: s_cbranch_execz .LBB3_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: s_bcnt1_i32_b32 s5, s5 ; GFX1032-NEXT: s_bcnt1_i32_b32 s5, s5
; GFX1032-NEXT: v_mov_b32_e32 v1, 0 ; GFX1032-NEXT: v_mov_b32_e32 v1, 0
; GFX1032-NEXT: s_mul_i32 s5, s5, 5 ; GFX1032-NEXT: s_mul_i32 s5, s5, 5
; GFX1032-NEXT: s_mov_b32 s11, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s11, 0x31016000
; GFX1032-NEXT: v_mov_b32_e32 v0, s5 ; GFX1032-NEXT: v_mov_b32_e32 v0, s5
; GFX1032-NEXT: s_mov_b32 s10, -1 ; GFX1032-NEXT: s_mov_b32 s10, -1
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: s_mov_b32 s8, s2 ; GFX1032-NEXT: s_mov_b32 s8, s2
; GFX1032-NEXT: s_mov_b32 s9, s3 ; GFX1032-NEXT: s_mov_b32 s9, s3
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: buffer_atomic_add_x2 v[0:1], off, s[8:11], 0 glc ; GFX1032-NEXT: buffer_atomic_add_x2 v[0:1], off, s[8:11], 0 glc
; GFX1032-NEXT: s_waitcnt vmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: buffer_gl1_inv ; GFX1032-NEXT: buffer_gl1_inv
; GFX1032-NEXT: BB3_2: ; GFX1032-NEXT: .LBB3_2:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: v_readfirstlane_b32 s2, v0 ; GFX1032-NEXT: v_readfirstlane_b32 s2, v0
; GFX1032-NEXT: v_readfirstlane_b32 s3, v1 ; GFX1032-NEXT: v_readfirstlane_b32 s3, v1
; GFX1032-NEXT: v_mad_u64_u32 v[0:1], s2, v2, 5, s[2:3] ; GFX1032-NEXT: v_mad_u64_u32 v[0:1], s2, v2, 5, s[2:3]
; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s3, 0x31016000
; GFX1032-NEXT: s_mov_b32 s2, -1 ; GFX1032-NEXT: s_mov_b32 s2, -1
Show All 11 Lines
; GFX7LESS-NEXT: s_mov_b64 s[8:9], exec ; GFX7LESS-NEXT: s_mov_b64 s[8:9], exec
; GFX7LESS-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GFX7LESS-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd ; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s8, 0 ; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s8, 0
; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v2, s9, v0 ; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v2, s9, v0
; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX7LESS-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX7LESS-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX7LESS-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX7LESS-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX7LESS-NEXT: s_cbranch_execz BB4_2 ; GFX7LESS-NEXT: s_cbranch_execz .LBB4_2
; GFX7LESS-NEXT: ; %bb.1: ; GFX7LESS-NEXT: ; %bb.1:
; GFX7LESS-NEXT: s_mov_b32 s15, 0xf000 ; GFX7LESS-NEXT: s_mov_b32 s15, 0xf000
; GFX7LESS-NEXT: s_mov_b32 s14, -1 ; GFX7LESS-NEXT: s_mov_b32 s14, -1
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: s_mov_b32 s12, s6 ; GFX7LESS-NEXT: s_mov_b32 s12, s6
; GFX7LESS-NEXT: s_mov_b32 s13, s7 ; GFX7LESS-NEXT: s_mov_b32 s13, s7
; GFX7LESS-NEXT: s_bcnt1_i32_b64 s6, s[8:9] ; GFX7LESS-NEXT: s_bcnt1_i32_b64 s6, s[8:9]
; GFX7LESS-NEXT: s_mul_i32 s7, s1, s6 ; GFX7LESS-NEXT: s_mul_i32 s7, s1, s6
; GFX7LESS-NEXT: v_mov_b32_e32 v0, s6 ; GFX7LESS-NEXT: v_mov_b32_e32 v0, s6
; GFX7LESS-NEXT: v_mul_hi_u32 v0, s0, v0 ; GFX7LESS-NEXT: v_mul_hi_u32 v0, s0, v0
; GFX7LESS-NEXT: s_mul_i32 s6, s0, s6 ; GFX7LESS-NEXT: s_mul_i32 s6, s0, s6
; GFX7LESS-NEXT: v_add_i32_e32 v1, vcc, s7, v0 ; GFX7LESS-NEXT: v_add_i32_e32 v1, vcc, s7, v0
; GFX7LESS-NEXT: v_mov_b32_e32 v0, s6 ; GFX7LESS-NEXT: v_mov_b32_e32 v0, s6
; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX7LESS-NEXT: buffer_atomic_add_x2 v[0:1], off, s[12:15], 0 glc ; GFX7LESS-NEXT: buffer_atomic_add_x2 v[0:1], off, s[12:15], 0 glc
; GFX7LESS-NEXT: s_waitcnt vmcnt(0) ; GFX7LESS-NEXT: s_waitcnt vmcnt(0)
; GFX7LESS-NEXT: buffer_wbinvl1 ; GFX7LESS-NEXT: buffer_wbinvl1
; GFX7LESS-NEXT: BB4_2: ; GFX7LESS-NEXT: .LBB4_2:
; GFX7LESS-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX7LESS-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: s_mov_b32 s7, 0xf000 ; GFX7LESS-NEXT: s_mov_b32 s7, 0xf000
; GFX7LESS-NEXT: s_mov_b32 s6, -1 ; GFX7LESS-NEXT: s_mov_b32 s6, -1
; GFX7LESS-NEXT: v_readfirstlane_b32 s2, v0 ; GFX7LESS-NEXT: v_readfirstlane_b32 s2, v0
; GFX7LESS-NEXT: v_readfirstlane_b32 s3, v1 ; GFX7LESS-NEXT: v_readfirstlane_b32 s3, v1
; GFX7LESS-NEXT: s_waitcnt expcnt(0) ; GFX7LESS-NEXT: s_waitcnt expcnt(0)
; GFX7LESS-NEXT: v_mul_lo_u32 v0, s1, v2 ; GFX7LESS-NEXT: v_mul_lo_u32 v0, s1, v2
Show All 11 Lines
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX8-NEXT: s_mov_b64 s[8:9], exec ; GFX8-NEXT: s_mov_b64 s[8:9], exec
; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s8, 0 ; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s8, 0
; GFX8-NEXT: v_mbcnt_hi_u32_b32 v2, s9, v0 ; GFX8-NEXT: v_mbcnt_hi_u32_b32 v2, s9, v0
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX8-NEXT: s_cbranch_execz BB4_2 ; GFX8-NEXT: s_cbranch_execz .LBB4_2
; GFX8-NEXT: ; %bb.1: ; GFX8-NEXT: ; %bb.1:
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_mov_b32 s12, s6 ; GFX8-NEXT: s_mov_b32 s12, s6
; GFX8-NEXT: s_bcnt1_i32_b64 s6, s[8:9] ; GFX8-NEXT: s_bcnt1_i32_b64 s6, s[8:9]
; GFX8-NEXT: v_mov_b32_e32 v0, s6 ; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0 ; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0
; GFX8-NEXT: s_mov_b32 s13, s7 ; GFX8-NEXT: s_mov_b32 s13, s7
; GFX8-NEXT: s_mul_i32 s7, s1, s6 ; GFX8-NEXT: s_mul_i32 s7, s1, s6
; GFX8-NEXT: s_mul_i32 s6, s0, s6 ; GFX8-NEXT: s_mul_i32 s6, s0, s6
; GFX8-NEXT: s_mov_b32 s15, 0xf000 ; GFX8-NEXT: s_mov_b32 s15, 0xf000
; GFX8-NEXT: s_mov_b32 s14, -1 ; GFX8-NEXT: s_mov_b32 s14, -1
; GFX8-NEXT: v_add_u32_e32 v1, vcc, s7, v0 ; GFX8-NEXT: v_add_u32_e32 v1, vcc, s7, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s6 ; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_atomic_add_x2 v[0:1], off, s[12:15], 0 glc ; GFX8-NEXT: buffer_atomic_add_x2 v[0:1], off, s[12:15], 0 glc
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1_vol ; GFX8-NEXT: buffer_wbinvl1_vol
; GFX8-NEXT: BB4_2: ; GFX8-NEXT: .LBB4_2:
; GFX8-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX8-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX8-NEXT: v_readfirstlane_b32 s2, v0 ; GFX8-NEXT: v_readfirstlane_b32 s2, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mul_lo_u32 v0, s1, v2 ; GFX8-NEXT: v_mul_lo_u32 v0, s1, v2
; GFX8-NEXT: v_mul_hi_u32 v3, s0, v2 ; GFX8-NEXT: v_mul_hi_u32 v3, s0, v2
; GFX8-NEXT: v_readfirstlane_b32 s1, v1 ; GFX8-NEXT: v_readfirstlane_b32 s1, v1
; GFX8-NEXT: v_mul_lo_u32 v1, s0, v2 ; GFX8-NEXT: v_mul_lo_u32 v1, s0, v2
; GFX8-NEXT: s_mov_b32 s7, 0xf000 ; GFX8-NEXT: s_mov_b32 s7, 0xf000
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; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX9-NEXT: s_mov_b64 s[8:9], exec ; GFX9-NEXT: s_mov_b64 s[8:9], exec
; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s8, 0 ; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s8, 0
; GFX9-NEXT: v_mbcnt_hi_u32_b32 v2, s9, v0 ; GFX9-NEXT: v_mbcnt_hi_u32_b32 v2, s9, v0
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX9-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX9-NEXT: s_cbranch_execz BB4_2 ; GFX9-NEXT: s_cbranch_execz .LBB4_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s12, s6 ; GFX9-NEXT: s_mov_b32 s12, s6
; GFX9-NEXT: s_bcnt1_i32_b64 s6, s[8:9] ; GFX9-NEXT: s_bcnt1_i32_b64 s6, s[8:9]
; GFX9-NEXT: s_mov_b32 s13, s7 ; GFX9-NEXT: s_mov_b32 s13, s7
; GFX9-NEXT: s_mul_i32 s7, s3, s6 ; GFX9-NEXT: s_mul_i32 s7, s3, s6
; GFX9-NEXT: s_mul_hi_u32 s8, s2, s6 ; GFX9-NEXT: s_mul_hi_u32 s8, s2, s6
; GFX9-NEXT: s_add_i32 s8, s8, s7 ; GFX9-NEXT: s_add_i32 s8, s8, s7
; GFX9-NEXT: s_mul_i32 s6, s2, s6 ; GFX9-NEXT: s_mul_i32 s6, s2, s6
; GFX9-NEXT: s_mov_b32 s15, 0xf000 ; GFX9-NEXT: s_mov_b32 s15, 0xf000
; GFX9-NEXT: s_mov_b32 s14, -1 ; GFX9-NEXT: s_mov_b32 s14, -1
; GFX9-NEXT: v_mov_b32_e32 v0, s6 ; GFX9-NEXT: v_mov_b32_e32 v0, s6
; GFX9-NEXT: v_mov_b32_e32 v1, s8 ; GFX9-NEXT: v_mov_b32_e32 v1, s8
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_atomic_add_x2 v[0:1], off, s[12:15], 0 glc ; GFX9-NEXT: buffer_atomic_add_x2 v[0:1], off, s[12:15], 0 glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: buffer_wbinvl1_vol ; GFX9-NEXT: buffer_wbinvl1_vol
; GFX9-NEXT: BB4_2: ; GFX9-NEXT: .LBB4_2:
; GFX9-NEXT: s_or_b64 exec, exec, s[0:1] ; GFX9-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mul_lo_u32 v3, s3, v2 ; GFX9-NEXT: v_mul_lo_u32 v3, s3, v2
; GFX9-NEXT: v_mul_hi_u32 v4, s2, v2 ; GFX9-NEXT: v_mul_hi_u32 v4, s2, v2
; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: v_mul_lo_u32 v0, s2, v2 ; GFX9-NEXT: v_mul_lo_u32 v0, s2, v2
; GFX9-NEXT: v_readfirstlane_b32 s1, v1 ; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: v_add_u32_e32 v1, v4, v3 ; GFX9-NEXT: v_add_u32_e32 v1, v4, v3
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; GFX1064-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX1064-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX1064-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX1064-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX1064-NEXT: s_mov_b64 s[8:9], exec ; GFX1064-NEXT: s_mov_b64 s[8:9], exec
; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s8, 0 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s8, 0
; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v2, s9, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v2, s9, v0
; GFX1064-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX1064-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX1064-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064-NEXT: s_cbranch_execz BB4_2 ; GFX1064-NEXT: s_cbranch_execz .LBB4_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: s_bcnt1_i32_b64 s8, s[8:9] ; GFX1064-NEXT: s_bcnt1_i32_b64 s8, s[8:9]
; GFX1064-NEXT: s_mov_b32 s11, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s11, 0x31016000
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: s_mul_i32 s9, s3, s8 ; GFX1064-NEXT: s_mul_i32 s9, s3, s8
; GFX1064-NEXT: s_mul_hi_u32 s10, s2, s8 ; GFX1064-NEXT: s_mul_hi_u32 s10, s2, s8
; GFX1064-NEXT: s_mul_i32 s8, s2, s8 ; GFX1064-NEXT: s_mul_i32 s8, s2, s8
; GFX1064-NEXT: s_add_i32 s10, s10, s9 ; GFX1064-NEXT: s_add_i32 s10, s10, s9
; GFX1064-NEXT: v_mov_b32_e32 v0, s8 ; GFX1064-NEXT: v_mov_b32_e32 v0, s8
; GFX1064-NEXT: v_mov_b32_e32 v1, s10 ; GFX1064-NEXT: v_mov_b32_e32 v1, s10
; GFX1064-NEXT: s_mov_b32 s10, -1 ; GFX1064-NEXT: s_mov_b32 s10, -1
; GFX1064-NEXT: s_mov_b32 s8, s6 ; GFX1064-NEXT: s_mov_b32 s8, s6
; GFX1064-NEXT: s_mov_b32 s9, s7 ; GFX1064-NEXT: s_mov_b32 s9, s7
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: buffer_atomic_add_x2 v[0:1], off, s[8:11], 0 glc ; GFX1064-NEXT: buffer_atomic_add_x2 v[0:1], off, s[8:11], 0 glc
; GFX1064-NEXT: s_waitcnt vmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: buffer_gl1_inv ; GFX1064-NEXT: buffer_gl1_inv
; GFX1064-NEXT: BB4_2: ; GFX1064-NEXT: .LBB4_2:
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[0:1] ; GFX1064-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: v_mul_lo_u32 v3, s3, v2 ; GFX1064-NEXT: v_mul_lo_u32 v3, s3, v2
; GFX1064-NEXT: v_mul_hi_u32 v4, s2, v2 ; GFX1064-NEXT: v_mul_hi_u32 v4, s2, v2
; GFX1064-NEXT: v_mul_lo_u32 v2, s2, v2 ; GFX1064-NEXT: v_mul_lo_u32 v2, s2, v2
; GFX1064-NEXT: v_readfirstlane_b32 s0, v0 ; GFX1064-NEXT: v_readfirstlane_b32 s0, v0
; GFX1064-NEXT: v_readfirstlane_b32 s1, v1 ; GFX1064-NEXT: v_readfirstlane_b32 s1, v1
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; GFX1032-NEXT: s_clause 0x1 ; GFX1032-NEXT: s_clause 0x1
; GFX1032-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX1032-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX1032-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX1032-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX1032-NEXT: s_mov_b32 s8, exec_lo ; GFX1032-NEXT: s_mov_b32 s8, exec_lo
; GFX1032-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX1032-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v2, s8, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v2, s8, 0
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX1032-NEXT: s_and_saveexec_b32 s0, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB4_2 ; GFX1032-NEXT: s_cbranch_execz .LBB4_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: s_bcnt1_i32_b32 s1, s8 ; GFX1032-NEXT: s_bcnt1_i32_b32 s1, s8
; GFX1032-NEXT: s_mov_b32 s11, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s11, 0x31016000
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: s_mul_i32 s8, s3, s1 ; GFX1032-NEXT: s_mul_i32 s8, s3, s1
; GFX1032-NEXT: s_mul_hi_u32 s9, s2, s1 ; GFX1032-NEXT: s_mul_hi_u32 s9, s2, s1
; GFX1032-NEXT: s_mul_i32 s1, s2, s1 ; GFX1032-NEXT: s_mul_i32 s1, s2, s1
; GFX1032-NEXT: s_add_i32 s9, s9, s8 ; GFX1032-NEXT: s_add_i32 s9, s9, s8
; GFX1032-NEXT: v_mov_b32_e32 v0, s1 ; GFX1032-NEXT: v_mov_b32_e32 v0, s1
; GFX1032-NEXT: v_mov_b32_e32 v1, s9 ; GFX1032-NEXT: v_mov_b32_e32 v1, s9
; GFX1032-NEXT: s_mov_b32 s10, -1 ; GFX1032-NEXT: s_mov_b32 s10, -1
; GFX1032-NEXT: s_mov_b32 s8, s6 ; GFX1032-NEXT: s_mov_b32 s8, s6
; GFX1032-NEXT: s_mov_b32 s9, s7 ; GFX1032-NEXT: s_mov_b32 s9, s7
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: buffer_atomic_add_x2 v[0:1], off, s[8:11], 0 glc ; GFX1032-NEXT: buffer_atomic_add_x2 v[0:1], off, s[8:11], 0 glc
; GFX1032-NEXT: s_waitcnt vmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: buffer_gl1_inv ; GFX1032-NEXT: buffer_gl1_inv
; GFX1032-NEXT: BB4_2: ; GFX1032-NEXT: .LBB4_2:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s0 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: v_mul_lo_u32 v3, s3, v2 ; GFX1032-NEXT: v_mul_lo_u32 v3, s3, v2
; GFX1032-NEXT: v_mul_hi_u32 v4, s2, v2 ; GFX1032-NEXT: v_mul_hi_u32 v4, s2, v2
; GFX1032-NEXT: v_mul_lo_u32 v2, s2, v2 ; GFX1032-NEXT: v_mul_lo_u32 v2, s2, v2
; GFX1032-NEXT: v_readfirstlane_b32 s0, v0 ; GFX1032-NEXT: v_readfirstlane_b32 s0, v0
; GFX1032-NEXT: v_readfirstlane_b32 s1, v1 ; GFX1032-NEXT: v_readfirstlane_b32 s1, v1
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
; GFX7LESS: ; %bb.0: ; %entry ; GFX7LESS: ; %bb.0: ; %entry
; GFX7LESS-NEXT: s_mov_b64 s[6:7], exec ; GFX7LESS-NEXT: s_mov_b64 s[6:7], exec
; GFX7LESS-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GFX7LESS-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0 ; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0
; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s7, v0 ; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s7, v0
; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX7LESS-NEXT: ; implicit-def: $vgpr1 ; GFX7LESS-NEXT: ; implicit-def: $vgpr1
; GFX7LESS-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX7LESS-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX7LESS-NEXT: s_cbranch_execz BB6_2 ; GFX7LESS-NEXT: s_cbranch_execz .LBB6_2
; GFX7LESS-NEXT: ; %bb.1: ; GFX7LESS-NEXT: ; %bb.1:
; GFX7LESS-NEXT: s_mov_b32 s11, 0xf000 ; GFX7LESS-NEXT: s_mov_b32 s11, 0xf000
; GFX7LESS-NEXT: s_bcnt1_i32_b64 s6, s[6:7] ; GFX7LESS-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
; GFX7LESS-NEXT: s_mul_i32 s6, s6, 5 ; GFX7LESS-NEXT: s_mul_i32 s6, s6, 5
; GFX7LESS-NEXT: s_mov_b32 s10, -1 ; GFX7LESS-NEXT: s_mov_b32 s10, -1
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: s_mov_b32 s8, s2 ; GFX7LESS-NEXT: s_mov_b32 s8, s2
; GFX7LESS-NEXT: s_mov_b32 s9, s3 ; GFX7LESS-NEXT: s_mov_b32 s9, s3
; GFX7LESS-NEXT: v_mov_b32_e32 v1, s6 ; GFX7LESS-NEXT: v_mov_b32_e32 v1, s6
; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX7LESS-NEXT: buffer_atomic_sub v1, off, s[8:11], 0 glc ; GFX7LESS-NEXT: buffer_atomic_sub v1, off, s[8:11], 0 glc
; GFX7LESS-NEXT: s_waitcnt vmcnt(0) ; GFX7LESS-NEXT: s_waitcnt vmcnt(0)
; GFX7LESS-NEXT: buffer_wbinvl1 ; GFX7LESS-NEXT: buffer_wbinvl1
; GFX7LESS-NEXT: BB6_2: ; GFX7LESS-NEXT: .LBB6_2:
; GFX7LESS-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX7LESS-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000 ; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000
; GFX7LESS-NEXT: s_mov_b32 s2, -1 ; GFX7LESS-NEXT: s_mov_b32 s2, -1
; GFX7LESS-NEXT: v_readfirstlane_b32 s4, v1 ; GFX7LESS-NEXT: v_readfirstlane_b32 s4, v1
; GFX7LESS-NEXT: v_mul_u32_u24_e32 v0, 5, v0 ; GFX7LESS-NEXT: v_mul_u32_u24_e32 v0, 5, v0
; GFX7LESS-NEXT: v_sub_i32_e32 v0, vcc, s4, v0 ; GFX7LESS-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
; GFX7LESS-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX7LESS-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7LESS-NEXT: s_endpgm ; GFX7LESS-NEXT: s_endpgm
; ;
; GFX8-LABEL: sub_i32_constant: ; GFX8-LABEL: sub_i32_constant:
; GFX8: ; %bb.0: ; %entry ; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX8-NEXT: s_mov_b64 s[6:7], exec ; GFX8-NEXT: s_mov_b64 s[6:7], exec
; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0 ; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s7, v0 ; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s7, v0
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX8-NEXT: ; implicit-def: $vgpr1 ; GFX8-NEXT: ; implicit-def: $vgpr1
; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX8-NEXT: s_cbranch_execz BB6_2 ; GFX8-NEXT: s_cbranch_execz .LBB6_2
; GFX8-NEXT: ; %bb.1: ; GFX8-NEXT: ; %bb.1:
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_mov_b32 s8, s2 ; GFX8-NEXT: s_mov_b32 s8, s2
; GFX8-NEXT: s_bcnt1_i32_b64 s2, s[6:7] ; GFX8-NEXT: s_bcnt1_i32_b64 s2, s[6:7]
; GFX8-NEXT: s_mul_i32 s2, s2, 5 ; GFX8-NEXT: s_mul_i32 s2, s2, 5
; GFX8-NEXT: s_mov_b32 s11, 0xf000 ; GFX8-NEXT: s_mov_b32 s11, 0xf000
; GFX8-NEXT: s_mov_b32 s10, -1 ; GFX8-NEXT: s_mov_b32 s10, -1
; GFX8-NEXT: s_mov_b32 s9, s3 ; GFX8-NEXT: s_mov_b32 s9, s3
; GFX8-NEXT: v_mov_b32_e32 v1, s2 ; GFX8-NEXT: v_mov_b32_e32 v1, s2
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_atomic_sub v1, off, s[8:11], 0 glc ; GFX8-NEXT: buffer_atomic_sub v1, off, s[8:11], 0 glc
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1_vol ; GFX8-NEXT: buffer_wbinvl1_vol
; GFX8-NEXT: BB6_2: ; GFX8-NEXT: .LBB6_2:
; GFX8-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX8-NEXT: v_readfirstlane_b32 s4, v1 ; GFX8-NEXT: v_readfirstlane_b32 s4, v1
; GFX8-NEXT: v_mul_u32_u24_e32 v0, 5, v0 ; GFX8-NEXT: v_mul_u32_u24_e32 v0, 5, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_mov_b32 s3, 0xf000 ; GFX8-NEXT: s_mov_b32 s3, 0xf000
; GFX8-NEXT: s_mov_b32 s2, -1 ; GFX8-NEXT: s_mov_b32 s2, -1
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s4, v0 ; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s4, v0
; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-LABEL: sub_i32_constant: ; GFX9-LABEL: sub_i32_constant:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: s_mov_b64 s[6:7], exec ; GFX9-NEXT: s_mov_b64 s[6:7], exec
; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0 ; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s7, v0 ; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s7, v0
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-NEXT: ; implicit-def: $vgpr1 ; GFX9-NEXT: ; implicit-def: $vgpr1
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_cbranch_execz BB6_2 ; GFX9-NEXT: s_cbranch_execz .LBB6_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s8, s2 ; GFX9-NEXT: s_mov_b32 s8, s2
; GFX9-NEXT: s_bcnt1_i32_b64 s2, s[6:7] ; GFX9-NEXT: s_bcnt1_i32_b64 s2, s[6:7]
; GFX9-NEXT: s_mul_i32 s2, s2, 5 ; GFX9-NEXT: s_mul_i32 s2, s2, 5
; GFX9-NEXT: s_mov_b32 s11, 0xf000 ; GFX9-NEXT: s_mov_b32 s11, 0xf000
; GFX9-NEXT: s_mov_b32 s10, -1 ; GFX9-NEXT: s_mov_b32 s10, -1
; GFX9-NEXT: s_mov_b32 s9, s3 ; GFX9-NEXT: s_mov_b32 s9, s3
; GFX9-NEXT: v_mov_b32_e32 v1, s2 ; GFX9-NEXT: v_mov_b32_e32 v1, s2
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_atomic_sub v1, off, s[8:11], 0 glc ; GFX9-NEXT: buffer_atomic_sub v1, off, s[8:11], 0 glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: buffer_wbinvl1_vol ; GFX9-NEXT: buffer_wbinvl1_vol
; GFX9-NEXT: BB6_2: ; GFX9-NEXT: .LBB6_2:
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: v_readfirstlane_b32 s4, v1 ; GFX9-NEXT: v_readfirstlane_b32 s4, v1
; GFX9-NEXT: v_mul_u32_u24_e32 v0, 5, v0 ; GFX9-NEXT: v_mul_u32_u24_e32 v0, 5, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: v_sub_u32_e32 v0, s4, v0 ; GFX9-NEXT: v_sub_u32_e32 v0, s4, v0
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX1064-LABEL: sub_i32_constant: ; GFX1064-LABEL: sub_i32_constant:
; GFX1064: ; %bb.0: ; %entry ; GFX1064: ; %bb.0: ; %entry
; GFX1064-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX1064-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX1064-NEXT: s_mov_b64 s[6:7], exec ; GFX1064-NEXT: s_mov_b64 s[6:7], exec
; GFX1064-NEXT: ; implicit-def: $vgpr1 ; GFX1064-NEXT: ; implicit-def: $vgpr1
; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, s7, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, s7, v0
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX1064-NEXT: s_cbranch_execz BB6_2 ; GFX1064-NEXT: s_cbranch_execz .LBB6_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: s_bcnt1_i32_b64 s6, s[6:7] ; GFX1064-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
; GFX1064-NEXT: s_mov_b32 s11, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s11, 0x31016000
; GFX1064-NEXT: s_mul_i32 s6, s6, 5 ; GFX1064-NEXT: s_mul_i32 s6, s6, 5
; GFX1064-NEXT: s_mov_b32 s10, -1 ; GFX1064-NEXT: s_mov_b32 s10, -1
; GFX1064-NEXT: v_mov_b32_e32 v1, s6 ; GFX1064-NEXT: v_mov_b32_e32 v1, s6
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: s_mov_b32 s8, s2 ; GFX1064-NEXT: s_mov_b32 s8, s2
; GFX1064-NEXT: s_mov_b32 s9, s3 ; GFX1064-NEXT: s_mov_b32 s9, s3
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: buffer_atomic_sub v1, off, s[8:11], 0 glc ; GFX1064-NEXT: buffer_atomic_sub v1, off, s[8:11], 0 glc
; GFX1064-NEXT: s_waitcnt vmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: buffer_gl1_inv ; GFX1064-NEXT: buffer_gl1_inv
; GFX1064-NEXT: BB6_2: ; GFX1064-NEXT: .LBB6_2:
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: v_readfirstlane_b32 s2, v1 ; GFX1064-NEXT: v_readfirstlane_b32 s2, v1
; GFX1064-NEXT: v_mul_u32_u24_e32 v0, 5, v0 ; GFX1064-NEXT: v_mul_u32_u24_e32 v0, 5, v0
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064-NEXT: v_sub_nc_u32_e32 v0, s2, v0 ; GFX1064-NEXT: v_sub_nc_u32_e32 v0, s2, v0
; GFX1064-NEXT: s_mov_b32 s2, -1 ; GFX1064-NEXT: s_mov_b32 s2, -1
; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: s_endpgm
; ;
; GFX1032-LABEL: sub_i32_constant: ; GFX1032-LABEL: sub_i32_constant:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX1032-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX1032-NEXT: s_mov_b32 s5, exec_lo ; GFX1032-NEXT: s_mov_b32 s5, exec_lo
; GFX1032-NEXT: ; implicit-def: $vgpr1 ; GFX1032-NEXT: ; implicit-def: $vgpr1
; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, s5, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, s5, 0
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: s_and_saveexec_b32 s4, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s4, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB6_2 ; GFX1032-NEXT: s_cbranch_execz .LBB6_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: s_bcnt1_i32_b32 s5, s5 ; GFX1032-NEXT: s_bcnt1_i32_b32 s5, s5
; GFX1032-NEXT: s_mov_b32 s11, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s11, 0x31016000
; GFX1032-NEXT: s_mul_i32 s5, s5, 5 ; GFX1032-NEXT: s_mul_i32 s5, s5, 5
; GFX1032-NEXT: s_mov_b32 s10, -1 ; GFX1032-NEXT: s_mov_b32 s10, -1
; GFX1032-NEXT: v_mov_b32_e32 v1, s5 ; GFX1032-NEXT: v_mov_b32_e32 v1, s5
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: s_mov_b32 s8, s2 ; GFX1032-NEXT: s_mov_b32 s8, s2
; GFX1032-NEXT: s_mov_b32 s9, s3 ; GFX1032-NEXT: s_mov_b32 s9, s3
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: buffer_atomic_sub v1, off, s[8:11], 0 glc ; GFX1032-NEXT: buffer_atomic_sub v1, off, s[8:11], 0 glc
; GFX1032-NEXT: s_waitcnt vmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: buffer_gl1_inv ; GFX1032-NEXT: buffer_gl1_inv
; GFX1032-NEXT: BB6_2: ; GFX1032-NEXT: .LBB6_2:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: v_readfirstlane_b32 s2, v1 ; GFX1032-NEXT: v_readfirstlane_b32 s2, v1
; GFX1032-NEXT: v_mul_u32_u24_e32 v0, 5, v0 ; GFX1032-NEXT: v_mul_u32_u24_e32 v0, 5, v0
; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s3, 0x31016000
; GFX1032-NEXT: v_sub_nc_u32_e32 v0, s2, v0 ; GFX1032-NEXT: v_sub_nc_u32_e32 v0, s2, v0
; GFX1032-NEXT: s_mov_b32 s2, -1 ; GFX1032-NEXT: s_mov_b32 s2, -1
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; GFX7LESS-NEXT: s_mov_b64 s[2:3], exec ; GFX7LESS-NEXT: s_mov_b64 s[2:3], exec
; GFX7LESS-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GFX7LESS-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GFX7LESS-NEXT: s_load_dword s8, s[0:1], 0xd ; GFX7LESS-NEXT: s_load_dword s8, s[0:1], 0xd
; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 ; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0
; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s3, v0 ; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s3, v0
; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX7LESS-NEXT: ; implicit-def: $vgpr1 ; GFX7LESS-NEXT: ; implicit-def: $vgpr1
; GFX7LESS-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX7LESS-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX7LESS-NEXT: s_cbranch_execz BB7_2 ; GFX7LESS-NEXT: s_cbranch_execz .LBB7_2
; GFX7LESS-NEXT: ; %bb.1: ; GFX7LESS-NEXT: ; %bb.1:
; GFX7LESS-NEXT: s_mov_b32 s15, 0xf000 ; GFX7LESS-NEXT: s_mov_b32 s15, 0xf000
; GFX7LESS-NEXT: s_bcnt1_i32_b64 s2, s[2:3] ; GFX7LESS-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: s_mul_i32 s2, s8, s2 ; GFX7LESS-NEXT: s_mul_i32 s2, s8, s2
; GFX7LESS-NEXT: s_mov_b32 s14, -1 ; GFX7LESS-NEXT: s_mov_b32 s14, -1
; GFX7LESS-NEXT: s_mov_b32 s12, s6 ; GFX7LESS-NEXT: s_mov_b32 s12, s6
; GFX7LESS-NEXT: s_mov_b32 s13, s7 ; GFX7LESS-NEXT: s_mov_b32 s13, s7
; GFX7LESS-NEXT: v_mov_b32_e32 v1, s2 ; GFX7LESS-NEXT: v_mov_b32_e32 v1, s2
; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX7LESS-NEXT: buffer_atomic_sub v1, off, s[12:15], 0 glc ; GFX7LESS-NEXT: buffer_atomic_sub v1, off, s[12:15], 0 glc
; GFX7LESS-NEXT: s_waitcnt vmcnt(0) ; GFX7LESS-NEXT: s_waitcnt vmcnt(0)
; GFX7LESS-NEXT: buffer_wbinvl1 ; GFX7LESS-NEXT: buffer_wbinvl1
; GFX7LESS-NEXT: BB7_2: ; GFX7LESS-NEXT: .LBB7_2:
; GFX7LESS-NEXT: s_or_b64 exec, exec, s[0:1] ; GFX7LESS-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: s_mov_b32 s7, 0xf000 ; GFX7LESS-NEXT: s_mov_b32 s7, 0xf000
; GFX7LESS-NEXT: s_mov_b32 s6, -1 ; GFX7LESS-NEXT: s_mov_b32 s6, -1
; GFX7LESS-NEXT: v_readfirstlane_b32 s0, v1 ; GFX7LESS-NEXT: v_readfirstlane_b32 s0, v1
; GFX7LESS-NEXT: v_mul_lo_u32 v0, s8, v0 ; GFX7LESS-NEXT: v_mul_lo_u32 v0, s8, v0
; GFX7LESS-NEXT: v_sub_i32_e32 v0, vcc, s0, v0 ; GFX7LESS-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
; GFX7LESS-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GFX7LESS-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX7LESS-NEXT: s_endpgm ; GFX7LESS-NEXT: s_endpgm
; ;
; GFX8-LABEL: sub_i32_uniform: ; GFX8-LABEL: sub_i32_uniform:
; GFX8: ; %bb.0: ; %entry ; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX8-NEXT: s_load_dword s8, s[0:1], 0x34 ; GFX8-NEXT: s_load_dword s8, s[0:1], 0x34
; GFX8-NEXT: s_mov_b64 s[2:3], exec ; GFX8-NEXT: s_mov_b64 s[2:3], exec
; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 ; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 ; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX8-NEXT: ; implicit-def: $vgpr1 ; GFX8-NEXT: ; implicit-def: $vgpr1
; GFX8-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX8-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX8-NEXT: s_cbranch_execz BB7_2 ; GFX8-NEXT: s_cbranch_execz .LBB7_2
; GFX8-NEXT: ; %bb.1: ; GFX8-NEXT: ; %bb.1:
; GFX8-NEXT: s_bcnt1_i32_b64 s2, s[2:3] ; GFX8-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_mul_i32 s2, s8, s2 ; GFX8-NEXT: s_mul_i32 s2, s8, s2
; GFX8-NEXT: s_mov_b32 s15, 0xf000 ; GFX8-NEXT: s_mov_b32 s15, 0xf000
; GFX8-NEXT: s_mov_b32 s14, -1 ; GFX8-NEXT: s_mov_b32 s14, -1
; GFX8-NEXT: s_mov_b32 s12, s6 ; GFX8-NEXT: s_mov_b32 s12, s6
; GFX8-NEXT: s_mov_b32 s13, s7 ; GFX8-NEXT: s_mov_b32 s13, s7
; GFX8-NEXT: v_mov_b32_e32 v1, s2 ; GFX8-NEXT: v_mov_b32_e32 v1, s2
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_atomic_sub v1, off, s[12:15], 0 glc ; GFX8-NEXT: buffer_atomic_sub v1, off, s[12:15], 0 glc
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1_vol ; GFX8-NEXT: buffer_wbinvl1_vol
; GFX8-NEXT: BB7_2: ; GFX8-NEXT: .LBB7_2:
; GFX8-NEXT: s_or_b64 exec, exec, s[0:1] ; GFX8-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mul_lo_u32 v0, s8, v0 ; GFX8-NEXT: v_mul_lo_u32 v0, s8, v0
; GFX8-NEXT: v_readfirstlane_b32 s0, v1 ; GFX8-NEXT: v_readfirstlane_b32 s0, v1
; GFX8-NEXT: s_mov_b32 s7, 0xf000 ; GFX8-NEXT: s_mov_b32 s7, 0xf000
; GFX8-NEXT: s_mov_b32 s6, -1 ; GFX8-NEXT: s_mov_b32 s6, -1
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s0, v0 ; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s0, v0
; GFX8-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GFX8-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-LABEL: sub_i32_uniform: ; GFX9-LABEL: sub_i32_uniform:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_load_dword s8, s[0:1], 0x34 ; GFX9-NEXT: s_load_dword s8, s[0:1], 0x34
; GFX9-NEXT: s_mov_b64 s[2:3], exec ; GFX9-NEXT: s_mov_b64 s[2:3], exec
; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 ; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 ; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-NEXT: ; implicit-def: $vgpr1 ; GFX9-NEXT: ; implicit-def: $vgpr1
; GFX9-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX9-NEXT: s_cbranch_execz BB7_2 ; GFX9-NEXT: s_cbranch_execz .LBB7_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: s_bcnt1_i32_b64 s2, s[2:3] ; GFX9-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mul_i32 s2, s8, s2 ; GFX9-NEXT: s_mul_i32 s2, s8, s2
; GFX9-NEXT: s_mov_b32 s15, 0xf000 ; GFX9-NEXT: s_mov_b32 s15, 0xf000
; GFX9-NEXT: s_mov_b32 s14, -1 ; GFX9-NEXT: s_mov_b32 s14, -1
; GFX9-NEXT: s_mov_b32 s12, s6 ; GFX9-NEXT: s_mov_b32 s12, s6
; GFX9-NEXT: s_mov_b32 s13, s7 ; GFX9-NEXT: s_mov_b32 s13, s7
; GFX9-NEXT: v_mov_b32_e32 v1, s2 ; GFX9-NEXT: v_mov_b32_e32 v1, s2
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_atomic_sub v1, off, s[12:15], 0 glc ; GFX9-NEXT: buffer_atomic_sub v1, off, s[12:15], 0 glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: buffer_wbinvl1_vol ; GFX9-NEXT: buffer_wbinvl1_vol
; GFX9-NEXT: BB7_2: ; GFX9-NEXT: .LBB7_2:
; GFX9-NEXT: s_or_b64 exec, exec, s[0:1] ; GFX9-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mul_lo_u32 v0, s8, v0 ; GFX9-NEXT: v_mul_lo_u32 v0, s8, v0
; GFX9-NEXT: v_readfirstlane_b32 s0, v1 ; GFX9-NEXT: v_readfirstlane_b32 s0, v1
; GFX9-NEXT: s_mov_b32 s7, 0xf000 ; GFX9-NEXT: s_mov_b32 s7, 0xf000
; GFX9-NEXT: s_mov_b32 s6, -1 ; GFX9-NEXT: s_mov_b32 s6, -1
; GFX9-NEXT: v_sub_u32_e32 v0, s0, v0 ; GFX9-NEXT: v_sub_u32_e32 v0, s0, v0
; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX1064-LABEL: sub_i32_uniform: ; GFX1064-LABEL: sub_i32_uniform:
; GFX1064: ; %bb.0: ; %entry ; GFX1064: ; %bb.0: ; %entry
; GFX1064-NEXT: s_clause 0x1 ; GFX1064-NEXT: s_clause 0x1
; GFX1064-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX1064-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX1064-NEXT: s_load_dword s8, s[0:1], 0x34 ; GFX1064-NEXT: s_load_dword s8, s[0:1], 0x34
; GFX1064-NEXT: s_mov_b64 s[2:3], exec ; GFX1064-NEXT: s_mov_b64 s[2:3], exec
; GFX1064-NEXT: ; implicit-def: $vgpr1 ; GFX1064-NEXT: ; implicit-def: $vgpr1
; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064-NEXT: s_cbranch_execz BB7_2 ; GFX1064-NEXT: s_cbranch_execz .LBB7_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: s_bcnt1_i32_b64 s2, s[2:3] ; GFX1064-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX1064-NEXT: s_mov_b32 s15, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s15, 0x31016000
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: s_mul_i32 s2, s8, s2 ; GFX1064-NEXT: s_mul_i32 s2, s8, s2
; GFX1064-NEXT: s_mov_b32 s14, -1 ; GFX1064-NEXT: s_mov_b32 s14, -1
; GFX1064-NEXT: v_mov_b32_e32 v1, s2 ; GFX1064-NEXT: v_mov_b32_e32 v1, s2
; GFX1064-NEXT: s_mov_b32 s12, s6 ; GFX1064-NEXT: s_mov_b32 s12, s6
; GFX1064-NEXT: s_mov_b32 s13, s7 ; GFX1064-NEXT: s_mov_b32 s13, s7
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: buffer_atomic_sub v1, off, s[12:15], 0 glc ; GFX1064-NEXT: buffer_atomic_sub v1, off, s[12:15], 0 glc
; GFX1064-NEXT: s_waitcnt vmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: buffer_gl1_inv ; GFX1064-NEXT: buffer_gl1_inv
; GFX1064-NEXT: BB7_2: ; GFX1064-NEXT: .LBB7_2:
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[0:1] ; GFX1064-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: v_mul_lo_u32 v0, s8, v0 ; GFX1064-NEXT: v_mul_lo_u32 v0, s8, v0
; GFX1064-NEXT: v_readfirstlane_b32 s0, v1 ; GFX1064-NEXT: v_readfirstlane_b32 s0, v1
; GFX1064-NEXT: s_mov_b32 s7, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s7, 0x31016000
; GFX1064-NEXT: s_mov_b32 s6, -1 ; GFX1064-NEXT: s_mov_b32 s6, -1
; GFX1064-NEXT: v_sub_nc_u32_e32 v0, s0, v0 ; GFX1064-NEXT: v_sub_nc_u32_e32 v0, s0, v0
; GFX1064-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GFX1064-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: s_endpgm
; ;
; GFX1032-LABEL: sub_i32_uniform: ; GFX1032-LABEL: sub_i32_uniform:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_clause 0x1 ; GFX1032-NEXT: s_clause 0x1
; GFX1032-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX1032-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX1032-NEXT: s_load_dword s2, s[0:1], 0x34 ; GFX1032-NEXT: s_load_dword s2, s[0:1], 0x34
; GFX1032-NEXT: s_mov_b32 s3, exec_lo ; GFX1032-NEXT: s_mov_b32 s3, exec_lo
; GFX1032-NEXT: ; implicit-def: $vgpr1 ; GFX1032-NEXT: ; implicit-def: $vgpr1
; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, s3, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, s3, 0
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: s_and_saveexec_b32 s0, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB7_2 ; GFX1032-NEXT: s_cbranch_execz .LBB7_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: s_bcnt1_i32_b32 s1, s3 ; GFX1032-NEXT: s_bcnt1_i32_b32 s1, s3
; GFX1032-NEXT: s_mov_b32 s11, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s11, 0x31016000
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: s_mul_i32 s1, s2, s1 ; GFX1032-NEXT: s_mul_i32 s1, s2, s1
; GFX1032-NEXT: s_mov_b32 s10, -1 ; GFX1032-NEXT: s_mov_b32 s10, -1
; GFX1032-NEXT: v_mov_b32_e32 v1, s1 ; GFX1032-NEXT: v_mov_b32_e32 v1, s1
; GFX1032-NEXT: s_mov_b32 s8, s6 ; GFX1032-NEXT: s_mov_b32 s8, s6
; GFX1032-NEXT: s_mov_b32 s9, s7 ; GFX1032-NEXT: s_mov_b32 s9, s7
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: buffer_atomic_sub v1, off, s[8:11], 0 glc ; GFX1032-NEXT: buffer_atomic_sub v1, off, s[8:11], 0 glc
; GFX1032-NEXT: s_waitcnt vmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: buffer_gl1_inv ; GFX1032-NEXT: buffer_gl1_inv
; GFX1032-NEXT: BB7_2: ; GFX1032-NEXT: .LBB7_2:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s0 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: v_mul_lo_u32 v0, s2, v0 ; GFX1032-NEXT: v_mul_lo_u32 v0, s2, v0
; GFX1032-NEXT: v_readfirstlane_b32 s0, v1 ; GFX1032-NEXT: v_readfirstlane_b32 s0, v1
; GFX1032-NEXT: s_mov_b32 s7, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s7, 0x31016000
; GFX1032-NEXT: s_mov_b32 s6, -1 ; GFX1032-NEXT: s_mov_b32 s6, -1
; GFX1032-NEXT: v_sub_nc_u32_e32 v0, s0, v0 ; GFX1032-NEXT: v_sub_nc_u32_e32 v0, s0, v0
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; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX8-NEXT: v_readlane_b32 s6, v2, 63 ; GFX8-NEXT: v_readlane_b32 s6, v2, 63
; GFX8-NEXT: s_nop 0 ; GFX8-NEXT: s_nop 0
; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf ; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX8-NEXT: s_mov_b64 exec, s[4:5] ; GFX8-NEXT: s_mov_b64 exec, s[4:5]
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX8-NEXT: ; implicit-def: $vgpr0 ; GFX8-NEXT: ; implicit-def: $vgpr0
; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX8-NEXT: s_cbranch_execz BB8_2 ; GFX8-NEXT: s_cbranch_execz .LBB8_2
; GFX8-NEXT: ; %bb.1: ; GFX8-NEXT: ; %bb.1:
; GFX8-NEXT: s_mov_b32 s11, 0xf000 ; GFX8-NEXT: s_mov_b32 s11, 0xf000
; GFX8-NEXT: s_mov_b32 s10, -1 ; GFX8-NEXT: s_mov_b32 s10, -1
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_mov_b32 s8, s2 ; GFX8-NEXT: s_mov_b32 s8, s2
; GFX8-NEXT: s_mov_b32 s9, s3 ; GFX8-NEXT: s_mov_b32 s9, s3
; GFX8-NEXT: v_mov_b32_e32 v0, s6 ; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_atomic_sub v0, off, s[8:11], 0 glc ; GFX8-NEXT: buffer_atomic_sub v0, off, s[8:11], 0 glc
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1_vol ; GFX8-NEXT: buffer_wbinvl1_vol
; GFX8-NEXT: BB8_2: ; GFX8-NEXT: .LBB8_2:
; GFX8-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX8-NEXT: v_readfirstlane_b32 s4, v0 ; GFX8-NEXT: v_readfirstlane_b32 s4, v0
; GFX8-NEXT: v_mov_b32_e32 v0, v1 ; GFX8-NEXT: v_mov_b32_e32 v0, v1
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_mov_b32 s3, 0xf000 ; GFX8-NEXT: s_mov_b32 s3, 0xf000
; GFX8-NEXT: s_mov_b32 s2, -1 ; GFX8-NEXT: s_mov_b32 s2, -1
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s4, v0 ; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s4, v0
; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9-NEXT: v_readlane_b32 s6, v2, 63 ; GFX9-NEXT: v_readlane_b32 s6, v2, 63
; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: s_nop 0
; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf ; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX9-NEXT: s_mov_b64 exec, s[4:5] ; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-NEXT: ; implicit-def: $vgpr0 ; GFX9-NEXT: ; implicit-def: $vgpr0
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_cbranch_execz BB8_2 ; GFX9-NEXT: s_cbranch_execz .LBB8_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: s_mov_b32 s11, 0xf000 ; GFX9-NEXT: s_mov_b32 s11, 0xf000
; GFX9-NEXT: s_mov_b32 s10, -1 ; GFX9-NEXT: s_mov_b32 s10, -1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s8, s2 ; GFX9-NEXT: s_mov_b32 s8, s2
; GFX9-NEXT: s_mov_b32 s9, s3 ; GFX9-NEXT: s_mov_b32 s9, s3
; GFX9-NEXT: v_mov_b32_e32 v0, s6 ; GFX9-NEXT: v_mov_b32_e32 v0, s6
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_atomic_sub v0, off, s[8:11], 0 glc ; GFX9-NEXT: buffer_atomic_sub v0, off, s[8:11], 0 glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: buffer_wbinvl1_vol ; GFX9-NEXT: buffer_wbinvl1_vol
; GFX9-NEXT: BB8_2: ; GFX9-NEXT: .LBB8_2:
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: v_readfirstlane_b32 s4, v0 ; GFX9-NEXT: v_readfirstlane_b32 s4, v0
; GFX9-NEXT: v_mov_b32_e32 v0, v1 ; GFX9-NEXT: v_mov_b32_e32 v0, v1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: v_sub_u32_e32 v0, s4, v0 ; GFX9-NEXT: v_sub_u32_e32 v0, s4, v0
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX1064-NEXT: s_or_saveexec_b64 s[6:7], -1 ; GFX1064-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX1064-NEXT: s_mov_b32 s4, s9 ; GFX1064-NEXT: s_mov_b32 s4, s9
; GFX1064-NEXT: v_writelane_b32 v3, s8, 48 ; GFX1064-NEXT: v_writelane_b32 v3, s8, 48
; GFX1064-NEXT: s_mov_b64 exec, s[6:7] ; GFX1064-NEXT: s_mov_b64 exec, s[6:7]
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: s_mov_b32 s6, -1 ; GFX1064-NEXT: s_mov_b32 s6, -1
; GFX1064-NEXT: ; implicit-def: $vgpr0 ; GFX1064-NEXT: ; implicit-def: $vgpr0
; GFX1064-NEXT: s_and_saveexec_b64 s[8:9], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[8:9], vcc
; GFX1064-NEXT: s_cbranch_execz BB8_2 ; GFX1064-NEXT: s_cbranch_execz .LBB8_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: v_mov_b32_e32 v0, s4 ; GFX1064-NEXT: v_mov_b32_e32 v0, s4
; GFX1064-NEXT: s_mov_b32 s7, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s7, 0x31016000
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: s_mov_b32 s4, s2 ; GFX1064-NEXT: s_mov_b32 s4, s2
; GFX1064-NEXT: s_mov_b32 s5, s3 ; GFX1064-NEXT: s_mov_b32 s5, s3
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: buffer_atomic_sub v0, off, s[4:7], 0 glc ; GFX1064-NEXT: buffer_atomic_sub v0, off, s[4:7], 0 glc
; GFX1064-NEXT: s_waitcnt vmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: buffer_gl1_inv ; GFX1064-NEXT: buffer_gl1_inv
; GFX1064-NEXT: BB8_2: ; GFX1064-NEXT: .LBB8_2:
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[8:9] ; GFX1064-NEXT: s_or_b64 exec, exec, s[8:9]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: v_readfirstlane_b32 s2, v0 ; GFX1064-NEXT: v_readfirstlane_b32 s2, v0
; GFX1064-NEXT: v_mov_b32_e32 v0, v3 ; GFX1064-NEXT: v_mov_b32_e32 v0, v3
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064-NEXT: v_sub_nc_u32_e32 v0, s2, v0 ; GFX1064-NEXT: v_sub_nc_u32_e32 v0, s2, v0
; GFX1064-NEXT: s_mov_b32 s2, s6 ; GFX1064-NEXT: s_mov_b32 s2, s6
Show All 26 Lines
; GFX1032-NEXT: s_or_saveexec_b32 s4, -1 ; GFX1032-NEXT: s_or_saveexec_b32 s4, -1
; GFX1032-NEXT: v_writelane_b32 v3, s5, 16 ; GFX1032-NEXT: v_writelane_b32 v3, s5, 16
; GFX1032-NEXT: s_mov_b32 exec_lo, s4 ; GFX1032-NEXT: s_mov_b32 exec_lo, s4
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: s_mov_b32 s4, s6 ; GFX1032-NEXT: s_mov_b32 s4, s6
; GFX1032-NEXT: s_mov_b32 s6, -1 ; GFX1032-NEXT: s_mov_b32 s6, -1
; GFX1032-NEXT: ; implicit-def: $vgpr0 ; GFX1032-NEXT: ; implicit-def: $vgpr0
; GFX1032-NEXT: s_and_saveexec_b32 s8, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s8, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB8_2 ; GFX1032-NEXT: s_cbranch_execz .LBB8_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: v_mov_b32_e32 v0, s4 ; GFX1032-NEXT: v_mov_b32_e32 v0, s4
; GFX1032-NEXT: s_mov_b32 s7, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s7, 0x31016000
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: s_mov_b32 s4, s2 ; GFX1032-NEXT: s_mov_b32 s4, s2
; GFX1032-NEXT: s_mov_b32 s5, s3 ; GFX1032-NEXT: s_mov_b32 s5, s3
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: buffer_atomic_sub v0, off, s[4:7], 0 glc ; GFX1032-NEXT: buffer_atomic_sub v0, off, s[4:7], 0 glc
; GFX1032-NEXT: s_waitcnt vmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: buffer_gl1_inv ; GFX1032-NEXT: buffer_gl1_inv
; GFX1032-NEXT: BB8_2: ; GFX1032-NEXT: .LBB8_2:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s8 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s8
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: v_readfirstlane_b32 s2, v0 ; GFX1032-NEXT: v_readfirstlane_b32 s2, v0
; GFX1032-NEXT: v_mov_b32_e32 v0, v3 ; GFX1032-NEXT: v_mov_b32_e32 v0, v3
; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s3, 0x31016000
; GFX1032-NEXT: v_sub_nc_u32_e32 v0, s2, v0 ; GFX1032-NEXT: v_sub_nc_u32_e32 v0, s2, v0
; GFX1032-NEXT: s_mov_b32 s2, s6 ; GFX1032-NEXT: s_mov_b32 s2, s6
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; GFX7LESS: ; %bb.0: ; %entry ; GFX7LESS: ; %bb.0: ; %entry
; GFX7LESS-NEXT: s_mov_b64 s[6:7], exec ; GFX7LESS-NEXT: s_mov_b64 s[6:7], exec
; GFX7LESS-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GFX7LESS-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0 ; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0
; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v2, s7, v0 ; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v2, s7, v0
; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX7LESS-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX7LESS-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX7LESS-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX7LESS-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX7LESS-NEXT: s_cbranch_execz BB9_2 ; GFX7LESS-NEXT: s_cbranch_execz .LBB9_2
; GFX7LESS-NEXT: ; %bb.1: ; GFX7LESS-NEXT: ; %bb.1:
; GFX7LESS-NEXT: s_mov_b32 s11, 0xf000 ; GFX7LESS-NEXT: s_mov_b32 s11, 0xf000
; GFX7LESS-NEXT: s_bcnt1_i32_b64 s6, s[6:7] ; GFX7LESS-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
; GFX7LESS-NEXT: s_mul_i32 s6, s6, 5 ; GFX7LESS-NEXT: s_mul_i32 s6, s6, 5
; GFX7LESS-NEXT: s_mov_b32 s10, -1 ; GFX7LESS-NEXT: s_mov_b32 s10, -1
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: s_mov_b32 s8, s2 ; GFX7LESS-NEXT: s_mov_b32 s8, s2
; GFX7LESS-NEXT: s_mov_b32 s9, s3 ; GFX7LESS-NEXT: s_mov_b32 s9, s3
; GFX7LESS-NEXT: v_mov_b32_e32 v0, s6 ; GFX7LESS-NEXT: v_mov_b32_e32 v0, s6
; GFX7LESS-NEXT: v_mov_b32_e32 v1, 0 ; GFX7LESS-NEXT: v_mov_b32_e32 v1, 0
; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX7LESS-NEXT: buffer_atomic_sub_x2 v[0:1], off, s[8:11], 0 glc ; GFX7LESS-NEXT: buffer_atomic_sub_x2 v[0:1], off, s[8:11], 0 glc
; GFX7LESS-NEXT: s_waitcnt vmcnt(0) ; GFX7LESS-NEXT: s_waitcnt vmcnt(0)
; GFX7LESS-NEXT: buffer_wbinvl1 ; GFX7LESS-NEXT: buffer_wbinvl1
; GFX7LESS-NEXT: BB9_2: ; GFX7LESS-NEXT: .LBB9_2:
; GFX7LESS-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX7LESS-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000 ; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000
; GFX7LESS-NEXT: s_mov_b32 s2, -1 ; GFX7LESS-NEXT: s_mov_b32 s2, -1
; GFX7LESS-NEXT: v_readfirstlane_b32 s4, v0 ; GFX7LESS-NEXT: v_readfirstlane_b32 s4, v0
; GFX7LESS-NEXT: v_readfirstlane_b32 s5, v1 ; GFX7LESS-NEXT: v_readfirstlane_b32 s5, v1
; GFX7LESS-NEXT: s_waitcnt expcnt(0) ; GFX7LESS-NEXT: s_waitcnt expcnt(0)
; GFX7LESS-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v2 ; GFX7LESS-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v2
; GFX7LESS-NEXT: v_mul_u32_u24_e32 v0, 5, v2 ; GFX7LESS-NEXT: v_mul_u32_u24_e32 v0, 5, v2
; GFX7LESS-NEXT: v_mov_b32_e32 v2, s5 ; GFX7LESS-NEXT: v_mov_b32_e32 v2, s5
; GFX7LESS-NEXT: v_sub_i32_e32 v0, vcc, s4, v0 ; GFX7LESS-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
; GFX7LESS-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc ; GFX7LESS-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc
; GFX7LESS-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX7LESS-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX7LESS-NEXT: s_endpgm ; GFX7LESS-NEXT: s_endpgm
; ;
; GFX8-LABEL: sub_i64_constant: ; GFX8-LABEL: sub_i64_constant:
; GFX8: ; %bb.0: ; %entry ; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX8-NEXT: s_mov_b64 s[6:7], exec ; GFX8-NEXT: s_mov_b64 s[6:7], exec
; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0 ; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
; GFX8-NEXT: v_mbcnt_hi_u32_b32 v2, s7, v0 ; GFX8-NEXT: v_mbcnt_hi_u32_b32 v2, s7, v0
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX8-NEXT: s_cbranch_execz BB9_2 ; GFX8-NEXT: s_cbranch_execz .LBB9_2
; GFX8-NEXT: ; %bb.1: ; GFX8-NEXT: ; %bb.1:
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_mov_b32 s8, s2 ; GFX8-NEXT: s_mov_b32 s8, s2
; GFX8-NEXT: s_bcnt1_i32_b64 s2, s[6:7] ; GFX8-NEXT: s_bcnt1_i32_b64 s2, s[6:7]
; GFX8-NEXT: s_mul_i32 s2, s2, 5 ; GFX8-NEXT: s_mul_i32 s2, s2, 5
; GFX8-NEXT: s_mov_b32 s11, 0xf000 ; GFX8-NEXT: s_mov_b32 s11, 0xf000
; GFX8-NEXT: s_mov_b32 s10, -1 ; GFX8-NEXT: s_mov_b32 s10, -1
; GFX8-NEXT: s_mov_b32 s9, s3 ; GFX8-NEXT: s_mov_b32 s9, s3
; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, 0 ; GFX8-NEXT: v_mov_b32_e32 v1, 0
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_atomic_sub_x2 v[0:1], off, s[8:11], 0 glc ; GFX8-NEXT: buffer_atomic_sub_x2 v[0:1], off, s[8:11], 0 glc
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1_vol ; GFX8-NEXT: buffer_wbinvl1_vol
; GFX8-NEXT: BB9_2: ; GFX8-NEXT: .LBB9_2:
; GFX8-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX8-NEXT: v_readfirstlane_b32 s4, v0 ; GFX8-NEXT: v_readfirstlane_b32 s4, v0
; GFX8-NEXT: v_readfirstlane_b32 s5, v1 ; GFX8-NEXT: v_readfirstlane_b32 s5, v1
; GFX8-NEXT: v_mul_u32_u24_e32 v0, 5, v2 ; GFX8-NEXT: v_mul_u32_u24_e32 v0, 5, v2
; GFX8-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v2 ; GFX8-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v2
; GFX8-NEXT: v_mov_b32_e32 v2, s5 ; GFX8-NEXT: v_mov_b32_e32 v2, s5
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s4, v0 ; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s4, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_mov_b32 s3, 0xf000 ; GFX8-NEXT: s_mov_b32 s3, 0xf000
; GFX8-NEXT: s_mov_b32 s2, -1 ; GFX8-NEXT: s_mov_b32 s2, -1
; GFX8-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc ; GFX8-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc
; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-LABEL: sub_i64_constant: ; GFX9-LABEL: sub_i64_constant:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: s_mov_b64 s[6:7], exec ; GFX9-NEXT: s_mov_b64 s[6:7], exec
; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0 ; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
; GFX9-NEXT: v_mbcnt_hi_u32_b32 v2, s7, v0 ; GFX9-NEXT: v_mbcnt_hi_u32_b32 v2, s7, v0
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_cbranch_execz BB9_2 ; GFX9-NEXT: s_cbranch_execz .LBB9_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s8, s2 ; GFX9-NEXT: s_mov_b32 s8, s2
; GFX9-NEXT: s_bcnt1_i32_b64 s2, s[6:7] ; GFX9-NEXT: s_bcnt1_i32_b64 s2, s[6:7]
; GFX9-NEXT: s_mul_i32 s2, s2, 5 ; GFX9-NEXT: s_mul_i32 s2, s2, 5
; GFX9-NEXT: s_mov_b32 s11, 0xf000 ; GFX9-NEXT: s_mov_b32 s11, 0xf000
; GFX9-NEXT: s_mov_b32 s10, -1 ; GFX9-NEXT: s_mov_b32 s10, -1
; GFX9-NEXT: s_mov_b32 s9, s3 ; GFX9-NEXT: s_mov_b32 s9, s3
; GFX9-NEXT: v_mov_b32_e32 v0, s2 ; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_atomic_sub_x2 v[0:1], off, s[8:11], 0 glc ; GFX9-NEXT: buffer_atomic_sub_x2 v[0:1], off, s[8:11], 0 glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: buffer_wbinvl1_vol ; GFX9-NEXT: buffer_wbinvl1_vol
; GFX9-NEXT: BB9_2: ; GFX9-NEXT: .LBB9_2:
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: v_readfirstlane_b32 s4, v0 ; GFX9-NEXT: v_readfirstlane_b32 s4, v0
; GFX9-NEXT: v_readfirstlane_b32 s5, v1 ; GFX9-NEXT: v_readfirstlane_b32 s5, v1
; GFX9-NEXT: v_mul_u32_u24_e32 v0, 5, v2 ; GFX9-NEXT: v_mul_u32_u24_e32 v0, 5, v2
; GFX9-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v2 ; GFX9-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v2
; GFX9-NEXT: v_mov_b32_e32 v2, s5 ; GFX9-NEXT: v_mov_b32_e32 v2, s5
; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s4, v0 ; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s4, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v2, v1, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v2, v1, vcc
; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX1064-LABEL: sub_i64_constant: ; GFX1064-LABEL: sub_i64_constant:
; GFX1064: ; %bb.0: ; %entry ; GFX1064: ; %bb.0: ; %entry
; GFX1064-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX1064-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX1064-NEXT: s_mov_b64 s[6:7], exec ; GFX1064-NEXT: s_mov_b64 s[6:7], exec
; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v2, s7, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v2, s7, v0
; GFX1064-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX1064-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX1064-NEXT: s_cbranch_execz BB9_2 ; GFX1064-NEXT: s_cbranch_execz .LBB9_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: s_bcnt1_i32_b64 s6, s[6:7] ; GFX1064-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
; GFX1064-NEXT: v_mov_b32_e32 v1, 0 ; GFX1064-NEXT: v_mov_b32_e32 v1, 0
; GFX1064-NEXT: s_mul_i32 s6, s6, 5 ; GFX1064-NEXT: s_mul_i32 s6, s6, 5
; GFX1064-NEXT: s_mov_b32 s11, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s11, 0x31016000
; GFX1064-NEXT: v_mov_b32_e32 v0, s6 ; GFX1064-NEXT: v_mov_b32_e32 v0, s6
; GFX1064-NEXT: s_mov_b32 s10, -1 ; GFX1064-NEXT: s_mov_b32 s10, -1
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: s_mov_b32 s8, s2 ; GFX1064-NEXT: s_mov_b32 s8, s2
; GFX1064-NEXT: s_mov_b32 s9, s3 ; GFX1064-NEXT: s_mov_b32 s9, s3
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: buffer_atomic_sub_x2 v[0:1], off, s[8:11], 0 glc ; GFX1064-NEXT: buffer_atomic_sub_x2 v[0:1], off, s[8:11], 0 glc
; GFX1064-NEXT: s_waitcnt vmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: buffer_gl1_inv ; GFX1064-NEXT: buffer_gl1_inv
; GFX1064-NEXT: BB9_2: ; GFX1064-NEXT: .LBB9_2:
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: v_readfirstlane_b32 s2, v0 ; GFX1064-NEXT: v_readfirstlane_b32 s2, v0
; GFX1064-NEXT: v_mul_u32_u24_e32 v0, 5, v2 ; GFX1064-NEXT: v_mul_u32_u24_e32 v0, 5, v2
; GFX1064-NEXT: v_readfirstlane_b32 s3, v1 ; GFX1064-NEXT: v_readfirstlane_b32 s3, v1
; GFX1064-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v2 ; GFX1064-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v2
; GFX1064-NEXT: v_sub_co_u32 v0, vcc, s2, v0 ; GFX1064-NEXT: v_sub_co_u32 v0, vcc, s2, v0
; GFX1064-NEXT: v_sub_co_ci_u32_e32 v1, vcc, s3, v1, vcc ; GFX1064-NEXT: v_sub_co_ci_u32_e32 v1, vcc, s3, v1, vcc
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064-NEXT: s_mov_b32 s2, -1 ; GFX1064-NEXT: s_mov_b32 s2, -1
; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: s_endpgm
; ;
; GFX1032-LABEL: sub_i64_constant: ; GFX1032-LABEL: sub_i64_constant:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX1032-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX1032-NEXT: s_mov_b32 s5, exec_lo ; GFX1032-NEXT: s_mov_b32 s5, exec_lo
; GFX1032-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX1032-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v2, s5, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v2, s5, 0
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX1032-NEXT: s_and_saveexec_b32 s4, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s4, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB9_2 ; GFX1032-NEXT: s_cbranch_execz .LBB9_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: s_bcnt1_i32_b32 s5, s5 ; GFX1032-NEXT: s_bcnt1_i32_b32 s5, s5
; GFX1032-NEXT: v_mov_b32_e32 v1, 0 ; GFX1032-NEXT: v_mov_b32_e32 v1, 0
; GFX1032-NEXT: s_mul_i32 s5, s5, 5 ; GFX1032-NEXT: s_mul_i32 s5, s5, 5
; GFX1032-NEXT: s_mov_b32 s11, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s11, 0x31016000
; GFX1032-NEXT: v_mov_b32_e32 v0, s5 ; GFX1032-NEXT: v_mov_b32_e32 v0, s5
; GFX1032-NEXT: s_mov_b32 s10, -1 ; GFX1032-NEXT: s_mov_b32 s10, -1
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: s_mov_b32 s8, s2 ; GFX1032-NEXT: s_mov_b32 s8, s2
; GFX1032-NEXT: s_mov_b32 s9, s3 ; GFX1032-NEXT: s_mov_b32 s9, s3
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: buffer_atomic_sub_x2 v[0:1], off, s[8:11], 0 glc ; GFX1032-NEXT: buffer_atomic_sub_x2 v[0:1], off, s[8:11], 0 glc
; GFX1032-NEXT: s_waitcnt vmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: buffer_gl1_inv ; GFX1032-NEXT: buffer_gl1_inv
; GFX1032-NEXT: BB9_2: ; GFX1032-NEXT: .LBB9_2:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: v_readfirstlane_b32 s2, v0 ; GFX1032-NEXT: v_readfirstlane_b32 s2, v0
; GFX1032-NEXT: v_mul_u32_u24_e32 v0, 5, v2 ; GFX1032-NEXT: v_mul_u32_u24_e32 v0, 5, v2
; GFX1032-NEXT: v_readfirstlane_b32 s3, v1 ; GFX1032-NEXT: v_readfirstlane_b32 s3, v1
; GFX1032-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v2 ; GFX1032-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v2
; GFX1032-NEXT: v_sub_co_u32 v0, vcc_lo, s2, v0 ; GFX1032-NEXT: v_sub_co_u32 v0, vcc_lo, s2, v0
Show All 14 Lines
; GFX7LESS-NEXT: s_mov_b64 s[8:9], exec ; GFX7LESS-NEXT: s_mov_b64 s[8:9], exec
; GFX7LESS-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GFX7LESS-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd ; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s8, 0 ; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s8, 0
; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v2, s9, v0 ; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v2, s9, v0
; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX7LESS-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX7LESS-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX7LESS-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX7LESS-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX7LESS-NEXT: s_cbranch_execz BB10_2 ; GFX7LESS-NEXT: s_cbranch_execz .LBB10_2
; GFX7LESS-NEXT: ; %bb.1: ; GFX7LESS-NEXT: ; %bb.1:
; GFX7LESS-NEXT: s_mov_b32 s15, 0xf000 ; GFX7LESS-NEXT: s_mov_b32 s15, 0xf000
; GFX7LESS-NEXT: s_mov_b32 s14, -1 ; GFX7LESS-NEXT: s_mov_b32 s14, -1
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: s_mov_b32 s12, s6 ; GFX7LESS-NEXT: s_mov_b32 s12, s6
; GFX7LESS-NEXT: s_mov_b32 s13, s7 ; GFX7LESS-NEXT: s_mov_b32 s13, s7
; GFX7LESS-NEXT: s_bcnt1_i32_b64 s6, s[8:9] ; GFX7LESS-NEXT: s_bcnt1_i32_b64 s6, s[8:9]
; GFX7LESS-NEXT: s_mul_i32 s7, s1, s6 ; GFX7LESS-NEXT: s_mul_i32 s7, s1, s6
; GFX7LESS-NEXT: v_mov_b32_e32 v0, s6 ; GFX7LESS-NEXT: v_mov_b32_e32 v0, s6
; GFX7LESS-NEXT: v_mul_hi_u32 v0, s0, v0 ; GFX7LESS-NEXT: v_mul_hi_u32 v0, s0, v0
; GFX7LESS-NEXT: s_mul_i32 s6, s0, s6 ; GFX7LESS-NEXT: s_mul_i32 s6, s0, s6
; GFX7LESS-NEXT: v_add_i32_e32 v1, vcc, s7, v0 ; GFX7LESS-NEXT: v_add_i32_e32 v1, vcc, s7, v0
; GFX7LESS-NEXT: v_mov_b32_e32 v0, s6 ; GFX7LESS-NEXT: v_mov_b32_e32 v0, s6
; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX7LESS-NEXT: buffer_atomic_sub_x2 v[0:1], off, s[12:15], 0 glc ; GFX7LESS-NEXT: buffer_atomic_sub_x2 v[0:1], off, s[12:15], 0 glc
; GFX7LESS-NEXT: s_waitcnt vmcnt(0) ; GFX7LESS-NEXT: s_waitcnt vmcnt(0)
; GFX7LESS-NEXT: buffer_wbinvl1 ; GFX7LESS-NEXT: buffer_wbinvl1
; GFX7LESS-NEXT: BB10_2: ; GFX7LESS-NEXT: .LBB10_2:
; GFX7LESS-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX7LESS-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: s_mov_b32 s7, 0xf000 ; GFX7LESS-NEXT: s_mov_b32 s7, 0xf000
; GFX7LESS-NEXT: s_mov_b32 s6, -1 ; GFX7LESS-NEXT: s_mov_b32 s6, -1
; GFX7LESS-NEXT: v_readfirstlane_b32 s2, v0 ; GFX7LESS-NEXT: v_readfirstlane_b32 s2, v0
; GFX7LESS-NEXT: v_readfirstlane_b32 s3, v1 ; GFX7LESS-NEXT: v_readfirstlane_b32 s3, v1
; GFX7LESS-NEXT: s_waitcnt expcnt(0) ; GFX7LESS-NEXT: s_waitcnt expcnt(0)
; GFX7LESS-NEXT: v_mul_lo_u32 v0, s1, v2 ; GFX7LESS-NEXT: v_mul_lo_u32 v0, s1, v2
Show All 11 Lines
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX8-NEXT: s_mov_b64 s[8:9], exec ; GFX8-NEXT: s_mov_b64 s[8:9], exec
; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s8, 0 ; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s8, 0
; GFX8-NEXT: v_mbcnt_hi_u32_b32 v2, s9, v0 ; GFX8-NEXT: v_mbcnt_hi_u32_b32 v2, s9, v0
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX8-NEXT: s_cbranch_execz BB10_2 ; GFX8-NEXT: s_cbranch_execz .LBB10_2
; GFX8-NEXT: ; %bb.1: ; GFX8-NEXT: ; %bb.1:
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_mov_b32 s12, s6 ; GFX8-NEXT: s_mov_b32 s12, s6
; GFX8-NEXT: s_bcnt1_i32_b64 s6, s[8:9] ; GFX8-NEXT: s_bcnt1_i32_b64 s6, s[8:9]
; GFX8-NEXT: v_mov_b32_e32 v0, s6 ; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0 ; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0
; GFX8-NEXT: s_mov_b32 s13, s7 ; GFX8-NEXT: s_mov_b32 s13, s7
; GFX8-NEXT: s_mul_i32 s7, s1, s6 ; GFX8-NEXT: s_mul_i32 s7, s1, s6
; GFX8-NEXT: s_mul_i32 s6, s0, s6 ; GFX8-NEXT: s_mul_i32 s6, s0, s6
; GFX8-NEXT: s_mov_b32 s15, 0xf000 ; GFX8-NEXT: s_mov_b32 s15, 0xf000
; GFX8-NEXT: s_mov_b32 s14, -1 ; GFX8-NEXT: s_mov_b32 s14, -1
; GFX8-NEXT: v_add_u32_e32 v1, vcc, s7, v0 ; GFX8-NEXT: v_add_u32_e32 v1, vcc, s7, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s6 ; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_atomic_sub_x2 v[0:1], off, s[12:15], 0 glc ; GFX8-NEXT: buffer_atomic_sub_x2 v[0:1], off, s[12:15], 0 glc
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1_vol ; GFX8-NEXT: buffer_wbinvl1_vol
; GFX8-NEXT: BB10_2: ; GFX8-NEXT: .LBB10_2:
; GFX8-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX8-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX8-NEXT: v_readfirstlane_b32 s2, v0 ; GFX8-NEXT: v_readfirstlane_b32 s2, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mul_lo_u32 v0, s1, v2 ; GFX8-NEXT: v_mul_lo_u32 v0, s1, v2
; GFX8-NEXT: v_mul_hi_u32 v3, s0, v2 ; GFX8-NEXT: v_mul_hi_u32 v3, s0, v2
; GFX8-NEXT: v_readfirstlane_b32 s1, v1 ; GFX8-NEXT: v_readfirstlane_b32 s1, v1
; GFX8-NEXT: v_mul_lo_u32 v1, s0, v2 ; GFX8-NEXT: v_mul_lo_u32 v1, s0, v2
; GFX8-NEXT: s_mov_b32 s7, 0xf000 ; GFX8-NEXT: s_mov_b32 s7, 0xf000
Show All 10 Lines
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX9-NEXT: s_mov_b64 s[8:9], exec ; GFX9-NEXT: s_mov_b64 s[8:9], exec
; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s8, 0 ; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s8, 0
; GFX9-NEXT: v_mbcnt_hi_u32_b32 v2, s9, v0 ; GFX9-NEXT: v_mbcnt_hi_u32_b32 v2, s9, v0
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX9-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX9-NEXT: s_cbranch_execz BB10_2 ; GFX9-NEXT: s_cbranch_execz .LBB10_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s12, s6 ; GFX9-NEXT: s_mov_b32 s12, s6
; GFX9-NEXT: s_bcnt1_i32_b64 s6, s[8:9] ; GFX9-NEXT: s_bcnt1_i32_b64 s6, s[8:9]
; GFX9-NEXT: s_mov_b32 s13, s7 ; GFX9-NEXT: s_mov_b32 s13, s7
; GFX9-NEXT: s_mul_i32 s7, s3, s6 ; GFX9-NEXT: s_mul_i32 s7, s3, s6
; GFX9-NEXT: s_mul_hi_u32 s8, s2, s6 ; GFX9-NEXT: s_mul_hi_u32 s8, s2, s6
; GFX9-NEXT: s_add_i32 s8, s8, s7 ; GFX9-NEXT: s_add_i32 s8, s8, s7
; GFX9-NEXT: s_mul_i32 s6, s2, s6 ; GFX9-NEXT: s_mul_i32 s6, s2, s6
; GFX9-NEXT: s_mov_b32 s15, 0xf000 ; GFX9-NEXT: s_mov_b32 s15, 0xf000
; GFX9-NEXT: s_mov_b32 s14, -1 ; GFX9-NEXT: s_mov_b32 s14, -1
; GFX9-NEXT: v_mov_b32_e32 v0, s6 ; GFX9-NEXT: v_mov_b32_e32 v0, s6
; GFX9-NEXT: v_mov_b32_e32 v1, s8 ; GFX9-NEXT: v_mov_b32_e32 v1, s8
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_atomic_sub_x2 v[0:1], off, s[12:15], 0 glc ; GFX9-NEXT: buffer_atomic_sub_x2 v[0:1], off, s[12:15], 0 glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: buffer_wbinvl1_vol ; GFX9-NEXT: buffer_wbinvl1_vol
; GFX9-NEXT: BB10_2: ; GFX9-NEXT: .LBB10_2:
; GFX9-NEXT: s_or_b64 exec, exec, s[0:1] ; GFX9-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mul_lo_u32 v3, s3, v2 ; GFX9-NEXT: v_mul_lo_u32 v3, s3, v2
; GFX9-NEXT: v_mul_hi_u32 v4, s2, v2 ; GFX9-NEXT: v_mul_hi_u32 v4, s2, v2
; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: v_mul_lo_u32 v0, s2, v2 ; GFX9-NEXT: v_mul_lo_u32 v0, s2, v2
; GFX9-NEXT: v_readfirstlane_b32 s1, v1 ; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: v_add_u32_e32 v1, v4, v3 ; GFX9-NEXT: v_add_u32_e32 v1, v4, v3
Show All 11 Lines
; GFX1064-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX1064-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX1064-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX1064-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX1064-NEXT: s_mov_b64 s[8:9], exec ; GFX1064-NEXT: s_mov_b64 s[8:9], exec
; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s8, 0 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s8, 0
; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v2, s9, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v2, s9, v0
; GFX1064-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX1064-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX1064-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064-NEXT: s_cbranch_execz BB10_2 ; GFX1064-NEXT: s_cbranch_execz .LBB10_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: s_bcnt1_i32_b64 s8, s[8:9] ; GFX1064-NEXT: s_bcnt1_i32_b64 s8, s[8:9]
; GFX1064-NEXT: s_mov_b32 s11, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s11, 0x31016000
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: s_mul_i32 s9, s3, s8 ; GFX1064-NEXT: s_mul_i32 s9, s3, s8
; GFX1064-NEXT: s_mul_hi_u32 s10, s2, s8 ; GFX1064-NEXT: s_mul_hi_u32 s10, s2, s8
; GFX1064-NEXT: s_mul_i32 s8, s2, s8 ; GFX1064-NEXT: s_mul_i32 s8, s2, s8
; GFX1064-NEXT: s_add_i32 s10, s10, s9 ; GFX1064-NEXT: s_add_i32 s10, s10, s9
; GFX1064-NEXT: v_mov_b32_e32 v0, s8 ; GFX1064-NEXT: v_mov_b32_e32 v0, s8
; GFX1064-NEXT: v_mov_b32_e32 v1, s10 ; GFX1064-NEXT: v_mov_b32_e32 v1, s10
; GFX1064-NEXT: s_mov_b32 s10, -1 ; GFX1064-NEXT: s_mov_b32 s10, -1
; GFX1064-NEXT: s_mov_b32 s8, s6 ; GFX1064-NEXT: s_mov_b32 s8, s6
; GFX1064-NEXT: s_mov_b32 s9, s7 ; GFX1064-NEXT: s_mov_b32 s9, s7
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: buffer_atomic_sub_x2 v[0:1], off, s[8:11], 0 glc ; GFX1064-NEXT: buffer_atomic_sub_x2 v[0:1], off, s[8:11], 0 glc
; GFX1064-NEXT: s_waitcnt vmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: buffer_gl1_inv ; GFX1064-NEXT: buffer_gl1_inv
; GFX1064-NEXT: BB10_2: ; GFX1064-NEXT: .LBB10_2:
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[0:1] ; GFX1064-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: v_mul_lo_u32 v3, s3, v2 ; GFX1064-NEXT: v_mul_lo_u32 v3, s3, v2
; GFX1064-NEXT: v_mul_hi_u32 v4, s2, v2 ; GFX1064-NEXT: v_mul_hi_u32 v4, s2, v2
; GFX1064-NEXT: v_mul_lo_u32 v2, s2, v2 ; GFX1064-NEXT: v_mul_lo_u32 v2, s2, v2
; GFX1064-NEXT: v_readfirstlane_b32 s0, v0 ; GFX1064-NEXT: v_readfirstlane_b32 s0, v0
; GFX1064-NEXT: v_readfirstlane_b32 s1, v1 ; GFX1064-NEXT: v_readfirstlane_b32 s1, v1
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; GFX1032-NEXT: s_clause 0x1 ; GFX1032-NEXT: s_clause 0x1
; GFX1032-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX1032-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX1032-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX1032-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX1032-NEXT: s_mov_b32 s8, exec_lo ; GFX1032-NEXT: s_mov_b32 s8, exec_lo
; GFX1032-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX1032-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v2, s8, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v2, s8, 0
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX1032-NEXT: s_and_saveexec_b32 s0, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB10_2 ; GFX1032-NEXT: s_cbranch_execz .LBB10_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: s_bcnt1_i32_b32 s1, s8 ; GFX1032-NEXT: s_bcnt1_i32_b32 s1, s8
; GFX1032-NEXT: s_mov_b32 s11, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s11, 0x31016000
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: s_mul_i32 s8, s3, s1 ; GFX1032-NEXT: s_mul_i32 s8, s3, s1
; GFX1032-NEXT: s_mul_hi_u32 s9, s2, s1 ; GFX1032-NEXT: s_mul_hi_u32 s9, s2, s1
; GFX1032-NEXT: s_mul_i32 s1, s2, s1 ; GFX1032-NEXT: s_mul_i32 s1, s2, s1
; GFX1032-NEXT: s_add_i32 s9, s9, s8 ; GFX1032-NEXT: s_add_i32 s9, s9, s8
; GFX1032-NEXT: v_mov_b32_e32 v0, s1 ; GFX1032-NEXT: v_mov_b32_e32 v0, s1
; GFX1032-NEXT: v_mov_b32_e32 v1, s9 ; GFX1032-NEXT: v_mov_b32_e32 v1, s9
; GFX1032-NEXT: s_mov_b32 s10, -1 ; GFX1032-NEXT: s_mov_b32 s10, -1
; GFX1032-NEXT: s_mov_b32 s8, s6 ; GFX1032-NEXT: s_mov_b32 s8, s6
; GFX1032-NEXT: s_mov_b32 s9, s7 ; GFX1032-NEXT: s_mov_b32 s9, s7
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: buffer_atomic_sub_x2 v[0:1], off, s[8:11], 0 glc ; GFX1032-NEXT: buffer_atomic_sub_x2 v[0:1], off, s[8:11], 0 glc
; GFX1032-NEXT: s_waitcnt vmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: buffer_gl1_inv ; GFX1032-NEXT: buffer_gl1_inv
; GFX1032-NEXT: BB10_2: ; GFX1032-NEXT: .LBB10_2:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s0 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: v_mul_lo_u32 v3, s3, v2 ; GFX1032-NEXT: v_mul_lo_u32 v3, s3, v2
; GFX1032-NEXT: v_mul_hi_u32 v4, s2, v2 ; GFX1032-NEXT: v_mul_hi_u32 v4, s2, v2
; GFX1032-NEXT: v_mul_lo_u32 v2, s2, v2 ; GFX1032-NEXT: v_mul_lo_u32 v2, s2, v2
; GFX1032-NEXT: v_readfirstlane_b32 s0, v0 ; GFX1032-NEXT: v_readfirstlane_b32 s0, v0
; GFX1032-NEXT: v_readfirstlane_b32 s1, v1 ; GFX1032-NEXT: v_readfirstlane_b32 s1, v1
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llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll

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; GFX7LESS: ; %bb.0: ; %entry ; GFX7LESS: ; %bb.0: ; %entry
; GFX7LESS-NEXT: s_mov_b64 s[2:3], exec ; GFX7LESS-NEXT: s_mov_b64 s[2:3], exec
; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 ; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0
; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s3, v0 ; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s3, v0
; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX7LESS-NEXT: ; implicit-def: $vgpr1 ; GFX7LESS-NEXT: ; implicit-def: $vgpr1
; GFX7LESS-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX7LESS-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX7LESS-NEXT: s_cbranch_execz BB0_2 ; GFX7LESS-NEXT: s_cbranch_execz .LBB0_2
; GFX7LESS-NEXT: ; %bb.1: ; GFX7LESS-NEXT: ; %bb.1:
; GFX7LESS-NEXT: s_bcnt1_i32_b64 s2, s[2:3] ; GFX7LESS-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX7LESS-NEXT: s_mul_i32 s2, s2, 5 ; GFX7LESS-NEXT: s_mul_i32 s2, s2, 5
; GFX7LESS-NEXT: v_mov_b32_e32 v1, 0 ; GFX7LESS-NEXT: v_mov_b32_e32 v1, 0
; GFX7LESS-NEXT: v_mov_b32_e32 v2, s2 ; GFX7LESS-NEXT: v_mov_b32_e32 v2, s2
; GFX7LESS-NEXT: s_mov_b32 m0, -1 ; GFX7LESS-NEXT: s_mov_b32 m0, -1
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: ds_add_rtn_u32 v1, v1, v2 ; GFX7LESS-NEXT: ds_add_rtn_u32 v1, v1, v2
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: BB0_2: ; GFX7LESS-NEXT: .LBB0_2:
; GFX7LESS-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX7LESS-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: v_readfirstlane_b32 s2, v1 ; GFX7LESS-NEXT: v_readfirstlane_b32 s2, v1
; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000 ; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000
; GFX7LESS-NEXT: v_mad_u32_u24 v0, v0, 5, s2 ; GFX7LESS-NEXT: v_mad_u32_u24 v0, v0, 5, s2
; GFX7LESS-NEXT: s_mov_b32 s2, -1 ; GFX7LESS-NEXT: s_mov_b32 s2, -1
; GFX7LESS-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX7LESS-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7LESS-NEXT: s_endpgm ; GFX7LESS-NEXT: s_endpgm
; ;
; GFX8-LABEL: add_i32_constant: ; GFX8-LABEL: add_i32_constant:
; GFX8: ; %bb.0: ; %entry ; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX8-NEXT: s_mov_b64 s[2:3], exec ; GFX8-NEXT: s_mov_b64 s[2:3], exec
; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 ; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 ; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX8-NEXT: ; implicit-def: $vgpr1 ; GFX8-NEXT: ; implicit-def: $vgpr1
; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX8-NEXT: s_cbranch_execz BB0_2 ; GFX8-NEXT: s_cbranch_execz .LBB0_2
; GFX8-NEXT: ; %bb.1: ; GFX8-NEXT: ; %bb.1:
; GFX8-NEXT: s_bcnt1_i32_b64 s2, s[2:3] ; GFX8-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX8-NEXT: s_mul_i32 s2, s2, 5 ; GFX8-NEXT: s_mul_i32 s2, s2, 5
; GFX8-NEXT: v_mov_b32_e32 v1, 0 ; GFX8-NEXT: v_mov_b32_e32 v1, 0
; GFX8-NEXT: v_mov_b32_e32 v2, s2 ; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: s_mov_b32 m0, -1 ; GFX8-NEXT: s_mov_b32 m0, -1
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: ds_add_rtn_u32 v1, v1, v2 ; GFX8-NEXT: ds_add_rtn_u32 v1, v1, v2
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: BB0_2: ; GFX8-NEXT: .LBB0_2:
; GFX8-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_readfirstlane_b32 s2, v1 ; GFX8-NEXT: v_readfirstlane_b32 s2, v1
; GFX8-NEXT: v_mad_u32_u24 v0, v0, 5, s2 ; GFX8-NEXT: v_mad_u32_u24 v0, v0, 5, s2
; GFX8-NEXT: s_mov_b32 s3, 0xf000 ; GFX8-NEXT: s_mov_b32 s3, 0xf000
; GFX8-NEXT: s_mov_b32 s2, -1 ; GFX8-NEXT: s_mov_b32 s2, -1
; GFX8-NEXT: s_nop 1 ; GFX8-NEXT: s_nop 1
; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-LABEL: add_i32_constant: ; GFX9-LABEL: add_i32_constant:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: s_mov_b64 s[2:3], exec ; GFX9-NEXT: s_mov_b64 s[2:3], exec
; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 ; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 ; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-NEXT: ; implicit-def: $vgpr1 ; GFX9-NEXT: ; implicit-def: $vgpr1
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_cbranch_execz BB0_2 ; GFX9-NEXT: s_cbranch_execz .LBB0_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: s_bcnt1_i32_b64 s2, s[2:3] ; GFX9-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX9-NEXT: s_mul_i32 s2, s2, 5 ; GFX9-NEXT: s_mul_i32 s2, s2, 5
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: v_mov_b32_e32 v2, s2 ; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: ds_add_rtn_u32 v1, v1, v2 ; GFX9-NEXT: ds_add_rtn_u32 v1, v1, v2
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: BB0_2: ; GFX9-NEXT: .LBB0_2:
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s2, v1 ; GFX9-NEXT: v_readfirstlane_b32 s2, v1
; GFX9-NEXT: v_mad_u32_u24 v0, v0, 5, s2 ; GFX9-NEXT: v_mad_u32_u24 v0, v0, 5, s2
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_nop 1 ; GFX9-NEXT: s_nop 1
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX1064-LABEL: add_i32_constant: ; GFX1064-LABEL: add_i32_constant:
; GFX1064: ; %bb.0: ; %entry ; GFX1064: ; %bb.0: ; %entry
; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX1064-NEXT: s_mov_b64 s[2:3], exec ; GFX1064-NEXT: s_mov_b64 s[2:3], exec
; GFX1064-NEXT: ; implicit-def: $vgpr1 ; GFX1064-NEXT: ; implicit-def: $vgpr1
; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX1064-NEXT: s_cbranch_execz BB0_2 ; GFX1064-NEXT: s_cbranch_execz .LBB0_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: s_bcnt1_i32_b64 s2, s[2:3] ; GFX1064-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX1064-NEXT: v_mov_b32_e32 v1, 0 ; GFX1064-NEXT: v_mov_b32_e32 v1, 0
; GFX1064-NEXT: s_mul_i32 s2, s2, 5 ; GFX1064-NEXT: s_mul_i32 s2, s2, 5
; GFX1064-NEXT: v_mov_b32_e32 v2, s2 ; GFX1064-NEXT: v_mov_b32_e32 v2, s2
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: ds_add_rtn_u32 v1, v1, v2 ; GFX1064-NEXT: ds_add_rtn_u32 v1, v1, v2
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: BB0_2: ; GFX1064-NEXT: .LBB0_2:
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX1064-NEXT: v_readfirstlane_b32 s2, v1 ; GFX1064-NEXT: v_readfirstlane_b32 s2, v1
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064-NEXT: v_mad_u32_u24 v0, v0, 5, s2 ; GFX1064-NEXT: v_mad_u32_u24 v0, v0, 5, s2
; GFX1064-NEXT: s_mov_b32 s2, -1 ; GFX1064-NEXT: s_mov_b32 s2, -1
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: s_endpgm
; ;
; GFX1032-LABEL: add_i32_constant: ; GFX1032-LABEL: add_i32_constant:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX1032-NEXT: s_mov_b32 s3, exec_lo ; GFX1032-NEXT: s_mov_b32 s3, exec_lo
; GFX1032-NEXT: ; implicit-def: $vgpr1 ; GFX1032-NEXT: ; implicit-def: $vgpr1
; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, s3, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, s3, 0
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: s_and_saveexec_b32 s2, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s2, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB0_2 ; GFX1032-NEXT: s_cbranch_execz .LBB0_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: s_bcnt1_i32_b32 s3, s3 ; GFX1032-NEXT: s_bcnt1_i32_b32 s3, s3
; GFX1032-NEXT: v_mov_b32_e32 v1, 0 ; GFX1032-NEXT: v_mov_b32_e32 v1, 0
; GFX1032-NEXT: s_mul_i32 s3, s3, 5 ; GFX1032-NEXT: s_mul_i32 s3, s3, 5
; GFX1032-NEXT: v_mov_b32_e32 v2, s3 ; GFX1032-NEXT: v_mov_b32_e32 v2, s3
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: ds_add_rtn_u32 v1, v1, v2 ; GFX1032-NEXT: ds_add_rtn_u32 v1, v1, v2
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: BB0_2: ; GFX1032-NEXT: .LBB0_2:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX1032-NEXT: v_readfirstlane_b32 s2, v1 ; GFX1032-NEXT: v_readfirstlane_b32 s2, v1
; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s3, 0x31016000
; GFX1032-NEXT: v_mad_u32_u24 v0, v0, 5, s2 ; GFX1032-NEXT: v_mad_u32_u24 v0, v0, 5, s2
; GFX1032-NEXT: s_mov_b32 s2, -1 ; GFX1032-NEXT: s_mov_b32 s2, -1
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX7LESS-NEXT: s_mov_b64 s[2:3], exec ; GFX7LESS-NEXT: s_mov_b64 s[2:3], exec
; GFX7LESS-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; GFX7LESS-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GFX7LESS-NEXT: s_load_dword s6, s[0:1], 0xb ; GFX7LESS-NEXT: s_load_dword s6, s[0:1], 0xb
; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 ; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0
; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s3, v0 ; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s3, v0
; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX7LESS-NEXT: ; implicit-def: $vgpr1 ; GFX7LESS-NEXT: ; implicit-def: $vgpr1
; GFX7LESS-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX7LESS-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX7LESS-NEXT: s_cbranch_execz BB1_2 ; GFX7LESS-NEXT: s_cbranch_execz .LBB1_2
; GFX7LESS-NEXT: ; %bb.1: ; GFX7LESS-NEXT: ; %bb.1:
; GFX7LESS-NEXT: s_bcnt1_i32_b64 s2, s[2:3] ; GFX7LESS-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: s_mul_i32 s2, s6, s2 ; GFX7LESS-NEXT: s_mul_i32 s2, s6, s2
; GFX7LESS-NEXT: v_mov_b32_e32 v1, 0 ; GFX7LESS-NEXT: v_mov_b32_e32 v1, 0
; GFX7LESS-NEXT: v_mov_b32_e32 v2, s2 ; GFX7LESS-NEXT: v_mov_b32_e32 v2, s2
; GFX7LESS-NEXT: s_mov_b32 m0, -1 ; GFX7LESS-NEXT: s_mov_b32 m0, -1
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: ds_add_rtn_u32 v1, v1, v2 ; GFX7LESS-NEXT: ds_add_rtn_u32 v1, v1, v2
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: BB1_2: ; GFX7LESS-NEXT: .LBB1_2:
; GFX7LESS-NEXT: s_or_b64 exec, exec, s[0:1] ; GFX7LESS-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: v_readfirstlane_b32 s0, v1 ; GFX7LESS-NEXT: v_readfirstlane_b32 s0, v1
; GFX7LESS-NEXT: v_mul_lo_u32 v0, s6, v0 ; GFX7LESS-NEXT: v_mul_lo_u32 v0, s6, v0
; GFX7LESS-NEXT: s_mov_b32 s7, 0xf000 ; GFX7LESS-NEXT: s_mov_b32 s7, 0xf000
; GFX7LESS-NEXT: v_add_i32_e32 v0, vcc, s0, v0 ; GFX7LESS-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; GFX7LESS-NEXT: s_mov_b32 s6, -1 ; GFX7LESS-NEXT: s_mov_b32 s6, -1
; GFX7LESS-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GFX7LESS-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX7LESS-NEXT: s_endpgm ; GFX7LESS-NEXT: s_endpgm
; ;
; GFX8-LABEL: add_i32_uniform: ; GFX8-LABEL: add_i32_uniform:
; GFX8: ; %bb.0: ; %entry ; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; GFX8-NEXT: s_load_dword s6, s[0:1], 0x2c ; GFX8-NEXT: s_load_dword s6, s[0:1], 0x2c
; GFX8-NEXT: s_mov_b64 s[2:3], exec ; GFX8-NEXT: s_mov_b64 s[2:3], exec
; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 ; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 ; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX8-NEXT: ; implicit-def: $vgpr1 ; GFX8-NEXT: ; implicit-def: $vgpr1
; GFX8-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX8-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX8-NEXT: s_cbranch_execz BB1_2 ; GFX8-NEXT: s_cbranch_execz .LBB1_2
; GFX8-NEXT: ; %bb.1: ; GFX8-NEXT: ; %bb.1:
; GFX8-NEXT: s_bcnt1_i32_b64 s2, s[2:3] ; GFX8-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_mul_i32 s2, s6, s2 ; GFX8-NEXT: s_mul_i32 s2, s6, s2
; GFX8-NEXT: v_mov_b32_e32 v1, 0 ; GFX8-NEXT: v_mov_b32_e32 v1, 0
; GFX8-NEXT: v_mov_b32_e32 v2, s2 ; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: s_mov_b32 m0, -1 ; GFX8-NEXT: s_mov_b32 m0, -1
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: ds_add_rtn_u32 v1, v1, v2 ; GFX8-NEXT: ds_add_rtn_u32 v1, v1, v2
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: BB1_2: ; GFX8-NEXT: .LBB1_2:
; GFX8-NEXT: s_or_b64 exec, exec, s[0:1] ; GFX8-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mul_lo_u32 v0, s6, v0 ; GFX8-NEXT: v_mul_lo_u32 v0, s6, v0
; GFX8-NEXT: v_readfirstlane_b32 s0, v1 ; GFX8-NEXT: v_readfirstlane_b32 s0, v1
; GFX8-NEXT: s_mov_b32 s7, 0xf000 ; GFX8-NEXT: s_mov_b32 s7, 0xf000
; GFX8-NEXT: s_mov_b32 s6, -1 ; GFX8-NEXT: s_mov_b32 s6, -1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0
; GFX8-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GFX8-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-LABEL: add_i32_uniform: ; GFX9-LABEL: add_i32_uniform:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; GFX9-NEXT: s_load_dword s6, s[0:1], 0x2c ; GFX9-NEXT: s_load_dword s6, s[0:1], 0x2c
; GFX9-NEXT: s_mov_b64 s[2:3], exec ; GFX9-NEXT: s_mov_b64 s[2:3], exec
; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 ; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 ; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-NEXT: ; implicit-def: $vgpr1 ; GFX9-NEXT: ; implicit-def: $vgpr1
; GFX9-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX9-NEXT: s_cbranch_execz BB1_2 ; GFX9-NEXT: s_cbranch_execz .LBB1_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: s_bcnt1_i32_b64 s2, s[2:3] ; GFX9-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mul_i32 s2, s6, s2 ; GFX9-NEXT: s_mul_i32 s2, s6, s2
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: v_mov_b32_e32 v2, s2 ; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: ds_add_rtn_u32 v1, v1, v2 ; GFX9-NEXT: ds_add_rtn_u32 v1, v1, v2
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: BB1_2: ; GFX9-NEXT: .LBB1_2:
; GFX9-NEXT: s_or_b64 exec, exec, s[0:1] ; GFX9-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mul_lo_u32 v0, s6, v0 ; GFX9-NEXT: v_mul_lo_u32 v0, s6, v0
; GFX9-NEXT: v_readfirstlane_b32 s0, v1 ; GFX9-NEXT: v_readfirstlane_b32 s0, v1
; GFX9-NEXT: s_mov_b32 s7, 0xf000 ; GFX9-NEXT: s_mov_b32 s7, 0xf000
; GFX9-NEXT: s_mov_b32 s6, -1 ; GFX9-NEXT: s_mov_b32 s6, -1
; GFX9-NEXT: v_add_u32_e32 v0, s0, v0 ; GFX9-NEXT: v_add_u32_e32 v0, s0, v0
; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX1064-LABEL: add_i32_uniform: ; GFX1064-LABEL: add_i32_uniform:
; GFX1064: ; %bb.0: ; %entry ; GFX1064: ; %bb.0: ; %entry
; GFX1064-NEXT: s_clause 0x1 ; GFX1064-NEXT: s_clause 0x1
; GFX1064-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX1064-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; GFX1064-NEXT: s_load_dword s6, s[0:1], 0x2c ; GFX1064-NEXT: s_load_dword s6, s[0:1], 0x2c
; GFX1064-NEXT: s_mov_b64 s[2:3], exec ; GFX1064-NEXT: s_mov_b64 s[2:3], exec
; GFX1064-NEXT: ; implicit-def: $vgpr1 ; GFX1064-NEXT: ; implicit-def: $vgpr1
; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064-NEXT: s_cbranch_execz BB1_2 ; GFX1064-NEXT: s_cbranch_execz .LBB1_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: s_bcnt1_i32_b64 s2, s[2:3] ; GFX1064-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX1064-NEXT: v_mov_b32_e32 v1, 0 ; GFX1064-NEXT: v_mov_b32_e32 v1, 0
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: s_mul_i32 s2, s6, s2 ; GFX1064-NEXT: s_mul_i32 s2, s6, s2
; GFX1064-NEXT: v_mov_b32_e32 v2, s2 ; GFX1064-NEXT: v_mov_b32_e32 v2, s2
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: ds_add_rtn_u32 v1, v1, v2 ; GFX1064-NEXT: ds_add_rtn_u32 v1, v1, v2
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: BB1_2: ; GFX1064-NEXT: .LBB1_2:
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[0:1] ; GFX1064-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: v_mul_lo_u32 v0, s6, v0 ; GFX1064-NEXT: v_mul_lo_u32 v0, s6, v0
; GFX1064-NEXT: v_readfirstlane_b32 s0, v1 ; GFX1064-NEXT: v_readfirstlane_b32 s0, v1
; GFX1064-NEXT: s_mov_b32 s7, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s7, 0x31016000
; GFX1064-NEXT: s_mov_b32 s6, -1 ; GFX1064-NEXT: s_mov_b32 s6, -1
; GFX1064-NEXT: v_add_nc_u32_e32 v0, s0, v0 ; GFX1064-NEXT: v_add_nc_u32_e32 v0, s0, v0
; GFX1064-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GFX1064-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: s_endpgm
; ;
; GFX1032-LABEL: add_i32_uniform: ; GFX1032-LABEL: add_i32_uniform:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_clause 0x1 ; GFX1032-NEXT: s_clause 0x1
; GFX1032-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX1032-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; GFX1032-NEXT: s_load_dword s2, s[0:1], 0x2c ; GFX1032-NEXT: s_load_dword s2, s[0:1], 0x2c
; GFX1032-NEXT: s_mov_b32 s3, exec_lo ; GFX1032-NEXT: s_mov_b32 s3, exec_lo
; GFX1032-NEXT: ; implicit-def: $vgpr1 ; GFX1032-NEXT: ; implicit-def: $vgpr1
; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, s3, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, s3, 0
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: s_and_saveexec_b32 s0, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB1_2 ; GFX1032-NEXT: s_cbranch_execz .LBB1_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: s_bcnt1_i32_b32 s1, s3 ; GFX1032-NEXT: s_bcnt1_i32_b32 s1, s3
; GFX1032-NEXT: v_mov_b32_e32 v1, 0 ; GFX1032-NEXT: v_mov_b32_e32 v1, 0
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: s_mul_i32 s1, s2, s1 ; GFX1032-NEXT: s_mul_i32 s1, s2, s1
; GFX1032-NEXT: v_mov_b32_e32 v2, s1 ; GFX1032-NEXT: v_mov_b32_e32 v2, s1
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: ds_add_rtn_u32 v1, v1, v2 ; GFX1032-NEXT: ds_add_rtn_u32 v1, v1, v2
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: BB1_2: ; GFX1032-NEXT: .LBB1_2:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s0 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: v_mul_lo_u32 v0, s2, v0 ; GFX1032-NEXT: v_mul_lo_u32 v0, s2, v0
; GFX1032-NEXT: v_readfirstlane_b32 s0, v1 ; GFX1032-NEXT: v_readfirstlane_b32 s0, v1
; GFX1032-NEXT: s_mov_b32 s7, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s7, 0x31016000
; GFX1032-NEXT: s_mov_b32 s6, -1 ; GFX1032-NEXT: s_mov_b32 s6, -1
; GFX1032-NEXT: v_add_nc_u32_e32 v0, s0, v0 ; GFX1032-NEXT: v_add_nc_u32_e32 v0, s0, v0
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX8-NEXT: v_readlane_b32 s4, v2, 63 ; GFX8-NEXT: v_readlane_b32 s4, v2, 63
; GFX8-NEXT: s_nop 0 ; GFX8-NEXT: s_nop 0
; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf ; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX8-NEXT: s_mov_b64 exec, s[2:3] ; GFX8-NEXT: s_mov_b64 exec, s[2:3]
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX8-NEXT: ; implicit-def: $vgpr0 ; GFX8-NEXT: ; implicit-def: $vgpr0
; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX8-NEXT: s_cbranch_execz BB2_2 ; GFX8-NEXT: s_cbranch_execz .LBB2_2
; GFX8-NEXT: ; %bb.1: ; GFX8-NEXT: ; %bb.1:
; GFX8-NEXT: v_mov_b32_e32 v0, 0 ; GFX8-NEXT: v_mov_b32_e32 v0, 0
; GFX8-NEXT: v_mov_b32_e32 v3, s4 ; GFX8-NEXT: v_mov_b32_e32 v3, s4
; GFX8-NEXT: s_mov_b32 m0, -1 ; GFX8-NEXT: s_mov_b32 m0, -1
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: ds_add_rtn_u32 v0, v0, v3 ; GFX8-NEXT: ds_add_rtn_u32 v0, v0, v3
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: BB2_2: ; GFX8-NEXT: .LBB2_2:
; GFX8-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX8-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_readfirstlane_b32 s2, v0 ; GFX8-NEXT: v_readfirstlane_b32 s2, v0
; GFX8-NEXT: v_mov_b32_e32 v0, v1 ; GFX8-NEXT: v_mov_b32_e32 v0, v1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v0 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v0
; GFX8-NEXT: s_mov_b32 s3, 0xf000 ; GFX8-NEXT: s_mov_b32 s3, 0xf000
; GFX8-NEXT: s_mov_b32 s2, -1 ; GFX8-NEXT: s_mov_b32 s2, -1
; GFX8-NEXT: s_nop 0 ; GFX8-NEXT: s_nop 0
Show All 26 Lines
; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9-NEXT: v_readlane_b32 s4, v2, 63 ; GFX9-NEXT: v_readlane_b32 s4, v2, 63
; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: s_nop 0
; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf ; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX9-NEXT: s_mov_b64 exec, s[2:3] ; GFX9-NEXT: s_mov_b64 exec, s[2:3]
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-NEXT: ; implicit-def: $vgpr0 ; GFX9-NEXT: ; implicit-def: $vgpr0
; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-NEXT: s_cbranch_execz BB2_2 ; GFX9-NEXT: s_cbranch_execz .LBB2_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v3, s4 ; GFX9-NEXT: v_mov_b32_e32 v3, s4
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: ds_add_rtn_u32 v0, v0, v3 ; GFX9-NEXT: ds_add_rtn_u32 v0, v0, v3
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: BB2_2: ; GFX9-NEXT: .LBB2_2:
; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX9-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s2, v0 ; GFX9-NEXT: v_readfirstlane_b32 s2, v0
; GFX9-NEXT: v_mov_b32_e32 v0, v1 ; GFX9-NEXT: v_mov_b32_e32 v0, v1
; GFX9-NEXT: v_add_u32_e32 v0, s2, v0 ; GFX9-NEXT: v_add_u32_e32 v0, s2, v0
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: s_nop 0
Show All 35 Lines
; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1064-NEXT: s_or_saveexec_b64 s[4:5], -1 ; GFX1064-NEXT: s_or_saveexec_b64 s[4:5], -1
; GFX1064-NEXT: v_writelane_b32 v3, s6, 48 ; GFX1064-NEXT: v_writelane_b32 v3, s6, 48
; GFX1064-NEXT: s_mov_b64 exec, s[4:5] ; GFX1064-NEXT: s_mov_b64 exec, s[4:5]
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: s_mov_b32 s2, -1 ; GFX1064-NEXT: s_mov_b32 s2, -1
; GFX1064-NEXT: ; implicit-def: $vgpr0 ; GFX1064-NEXT: ; implicit-def: $vgpr0
; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX1064-NEXT: s_cbranch_execz BB2_2 ; GFX1064-NEXT: s_cbranch_execz .LBB2_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: v_mov_b32_e32 v0, 0 ; GFX1064-NEXT: v_mov_b32_e32 v0, 0
; GFX1064-NEXT: v_mov_b32_e32 v4, s7 ; GFX1064-NEXT: v_mov_b32_e32 v4, s7
; GFX1064-NEXT: s_mov_b32 s3, s7 ; GFX1064-NEXT: s_mov_b32 s3, s7
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: ds_add_rtn_u32 v0, v0, v4 ; GFX1064-NEXT: ds_add_rtn_u32 v0, v0, v4
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: BB2_2: ; GFX1064-NEXT: .LBB2_2:
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX1064-NEXT: v_readfirstlane_b32 s3, v0 ; GFX1064-NEXT: v_readfirstlane_b32 s3, v0
; GFX1064-NEXT: v_mov_b32_e32 v0, v3 ; GFX1064-NEXT: v_mov_b32_e32 v0, v3
; GFX1064-NEXT: v_add_nc_u32_e32 v0, s3, v0 ; GFX1064-NEXT: v_add_nc_u32_e32 v0, s3, v0
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0
Show All 24 Lines
; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1032-NEXT: s_or_saveexec_b32 s2, -1 ; GFX1032-NEXT: s_or_saveexec_b32 s2, -1
; GFX1032-NEXT: v_writelane_b32 v3, s3, 16 ; GFX1032-NEXT: v_writelane_b32 v3, s3, 16
; GFX1032-NEXT: s_mov_b32 exec_lo, s2 ; GFX1032-NEXT: s_mov_b32 exec_lo, s2
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: s_mov_b32 s2, -1 ; GFX1032-NEXT: s_mov_b32 s2, -1
; GFX1032-NEXT: ; implicit-def: $vgpr0 ; GFX1032-NEXT: ; implicit-def: $vgpr0
; GFX1032-NEXT: s_and_saveexec_b32 s3, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s3, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB2_2 ; GFX1032-NEXT: s_cbranch_execz .LBB2_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: v_mov_b32_e32 v0, 0 ; GFX1032-NEXT: v_mov_b32_e32 v0, 0
; GFX1032-NEXT: v_mov_b32_e32 v4, s4 ; GFX1032-NEXT: v_mov_b32_e32 v4, s4
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: ds_add_rtn_u32 v0, v0, v4 ; GFX1032-NEXT: ds_add_rtn_u32 v0, v0, v4
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: BB2_2: ; GFX1032-NEXT: .LBB2_2:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s3 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s3
; GFX1032-NEXT: v_readfirstlane_b32 s3, v0 ; GFX1032-NEXT: v_readfirstlane_b32 s3, v0
; GFX1032-NEXT: v_mov_b32_e32 v0, v3 ; GFX1032-NEXT: v_mov_b32_e32 v0, v3
; GFX1032-NEXT: v_add_nc_u32_e32 v0, s3, v0 ; GFX1032-NEXT: v_add_nc_u32_e32 v0, s3, v0
; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s3, 0x31016000
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0
Show All 35 Lines
; GFX8-NEXT: v_add_u32_dpp v1, vcc, v1, v1 row_bcast:15 row_mask:0xa bank_mask:0xf ; GFX8-NEXT: v_add_u32_dpp v1, vcc, v1, v1 row_bcast:15 row_mask:0xa bank_mask:0xf
; GFX8-NEXT: s_nop 1 ; GFX8-NEXT: s_nop 1
; GFX8-NEXT: v_add_u32_dpp v1, vcc, v1, v1 row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX8-NEXT: v_add_u32_dpp v1, vcc, v1, v1 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX8-NEXT: v_readlane_b32 s2, v1, 63 ; GFX8-NEXT: v_readlane_b32 s2, v1, 63
; GFX8-NEXT: s_mov_b64 exec, s[0:1] ; GFX8-NEXT: s_mov_b64 exec, s[0:1]
; GFX8-NEXT: s_mov_b32 s0, s2 ; GFX8-NEXT: s_mov_b32 s0, s2
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX8-NEXT: s_cbranch_execz BB3_2 ; GFX8-NEXT: s_cbranch_execz .LBB3_2
; GFX8-NEXT: ; %bb.1: ; GFX8-NEXT: ; %bb.1:
; GFX8-NEXT: v_mov_b32_e32 v0, 0 ; GFX8-NEXT: v_mov_b32_e32 v0, 0
; GFX8-NEXT: v_mov_b32_e32 v2, s0 ; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: s_mov_b32 m0, -1 ; GFX8-NEXT: s_mov_b32 m0, -1
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: ds_add_u32 v0, v2 ; GFX8-NEXT: ds_add_u32 v0, v2
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: BB3_2: ; GFX8-NEXT: .LBB3_2:
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-LABEL: add_i32_varying_nouse: ; GFX9-LABEL: add_i32_varying_nouse:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: v_mov_b32_e32 v1, v0 ; GFX9-NEXT: v_mov_b32_e32 v1, v0
; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX9-NEXT: s_not_b64 exec, exec ; GFX9-NEXT: s_not_b64 exec, exec
Show All 11 Lines
; GFX9-NEXT: v_add_u32_dpp v1, v1, v1 row_bcast:15 row_mask:0xa bank_mask:0xf ; GFX9-NEXT: v_add_u32_dpp v1, v1, v1 row_bcast:15 row_mask:0xa bank_mask:0xf
; GFX9-NEXT: s_nop 1 ; GFX9-NEXT: s_nop 1
; GFX9-NEXT: v_add_u32_dpp v1, v1, v1 row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX9-NEXT: v_add_u32_dpp v1, v1, v1 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9-NEXT: v_readlane_b32 s2, v1, 63 ; GFX9-NEXT: v_readlane_b32 s2, v1, 63
; GFX9-NEXT: s_mov_b64 exec, s[0:1] ; GFX9-NEXT: s_mov_b64 exec, s[0:1]
; GFX9-NEXT: s_mov_b32 s0, s2 ; GFX9-NEXT: s_mov_b32 s0, s2
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-NEXT: s_cbranch_execz BB3_2 ; GFX9-NEXT: s_cbranch_execz .LBB3_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v2, s0 ; GFX9-NEXT: v_mov_b32_e32 v2, s0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: ds_add_u32 v0, v2 ; GFX9-NEXT: ds_add_u32 v0, v2
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: BB3_2: ; GFX9-NEXT: .LBB3_2:
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX1064-LABEL: add_i32_varying_nouse: ; GFX1064-LABEL: add_i32_varying_nouse:
; GFX1064: ; %bb.0: ; %entry ; GFX1064: ; %bb.0: ; %entry
; GFX1064-NEXT: v_mov_b32_e32 v1, v0 ; GFX1064-NEXT: v_mov_b32_e32 v1, v0
; GFX1064-NEXT: s_not_b64 exec, exec ; GFX1064-NEXT: s_not_b64 exec, exec
; GFX1064-NEXT: v_mov_b32_e32 v1, 0 ; GFX1064-NEXT: v_mov_b32_e32 v1, 0
; GFX1064-NEXT: s_not_b64 exec, exec ; GFX1064-NEXT: s_not_b64 exec, exec
Show All 10 Lines
; GFX1064-NEXT: s_or_saveexec_b64 s[0:1], -1 ; GFX1064-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX1064-NEXT: v_readlane_b32 s2, v1, 0 ; GFX1064-NEXT: v_readlane_b32 s2, v1, 0
; GFX1064-NEXT: v_readlane_b32 s3, v1, 32 ; GFX1064-NEXT: v_readlane_b32 s3, v1, 32
; GFX1064-NEXT: s_mov_b64 exec, s[0:1] ; GFX1064-NEXT: s_mov_b64 exec, s[0:1]
; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1064-NEXT: s_add_i32 s0, s2, s3 ; GFX1064-NEXT: s_add_i32 s0, s2, s3
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX1064-NEXT: s_cbranch_execz BB3_2 ; GFX1064-NEXT: s_cbranch_execz .LBB3_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: v_mov_b32_e32 v0, 0 ; GFX1064-NEXT: v_mov_b32_e32 v0, 0
; GFX1064-NEXT: v_mov_b32_e32 v3, s0 ; GFX1064-NEXT: v_mov_b32_e32 v3, s0
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: ds_add_u32 v0, v3 ; GFX1064-NEXT: ds_add_u32 v0, v3
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: BB3_2: ; GFX1064-NEXT: .LBB3_2:
; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: s_endpgm
; ;
; GFX1032-LABEL: add_i32_varying_nouse: ; GFX1032-LABEL: add_i32_varying_nouse:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: v_mov_b32_e32 v1, v0 ; GFX1032-NEXT: v_mov_b32_e32 v1, v0
; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo ; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo
; GFX1032-NEXT: v_mov_b32_e32 v1, 0 ; GFX1032-NEXT: v_mov_b32_e32 v1, 0
; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo ; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo
; GFX1032-NEXT: s_or_saveexec_b32 s0, -1 ; GFX1032-NEXT: s_or_saveexec_b32 s0, -1
; GFX1032-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_xmask:1 row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX1032-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_xmask:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1032-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_xmask:2 row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX1032-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_xmask:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1032-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_xmask:4 row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX1032-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_xmask:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1032-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_xmask:8 row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX1032-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_xmask:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1032-NEXT: v_mov_b32_e32 v2, v1 ; GFX1032-NEXT: v_mov_b32_e32 v2, v1
; GFX1032-NEXT: v_permlanex16_b32 v2, v2, -1, -1 ; GFX1032-NEXT: v_permlanex16_b32 v2, v2, -1, -1
; GFX1032-NEXT: v_add_nc_u32_e32 v1, v1, v2 ; GFX1032-NEXT: v_add_nc_u32_e32 v1, v1, v2
; GFX1032-NEXT: s_mov_b32 exec_lo, s0 ; GFX1032-NEXT: s_mov_b32 exec_lo, s0
; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v3, exec_lo, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v3, exec_lo, 0
; GFX1032-NEXT: v_mov_b32_e32 v0, v1 ; GFX1032-NEXT: v_mov_b32_e32 v0, v1
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v3 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v3
; GFX1032-NEXT: s_and_saveexec_b32 s0, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB3_2 ; GFX1032-NEXT: s_cbranch_execz .LBB3_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: v_mov_b32_e32 v3, 0 ; GFX1032-NEXT: v_mov_b32_e32 v3, 0
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: ds_add_u32 v3, v0 ; GFX1032-NEXT: ds_add_u32 v3, v0
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: BB3_2: ; GFX1032-NEXT: .LBB3_2:
; GFX1032-NEXT: s_endpgm ; GFX1032-NEXT: s_endpgm
entry: entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x() %lane = call i32 @llvm.amdgcn.workitem.id.x()
%old = atomicrmw add i32 addrspace(3)* @local_var32, i32 %lane acq_rel %old = atomicrmw add i32 addrspace(3)* @local_var32, i32 %lane acq_rel
ret void ret void
} }
define amdgpu_kernel void @add_i64_constant(i64 addrspace(1)* %out) { define amdgpu_kernel void @add_i64_constant(i64 addrspace(1)* %out) {
; ;
; ;
; GFX7LESS-LABEL: add_i64_constant: ; GFX7LESS-LABEL: add_i64_constant:
; GFX7LESS: ; %bb.0: ; %entry ; GFX7LESS: ; %bb.0: ; %entry
; GFX7LESS-NEXT: s_mov_b64 s[4:5], exec ; GFX7LESS-NEXT: s_mov_b64 s[4:5], exec
; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s4, 0 ; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s4, 0
; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v2, s5, v0 ; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v2, s5, v0
; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX7LESS-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX7LESS-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX7LESS-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX7LESS-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX7LESS-NEXT: s_cbranch_execz BB4_2 ; GFX7LESS-NEXT: s_cbranch_execz .LBB4_2
; GFX7LESS-NEXT: ; %bb.1: ; GFX7LESS-NEXT: ; %bb.1:
; GFX7LESS-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX7LESS-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
; GFX7LESS-NEXT: s_mul_i32 s4, s4, 5 ; GFX7LESS-NEXT: s_mul_i32 s4, s4, 5
; GFX7LESS-NEXT: v_mov_b32_e32 v1, 0 ; GFX7LESS-NEXT: v_mov_b32_e32 v1, 0
; GFX7LESS-NEXT: v_mov_b32_e32 v0, s4 ; GFX7LESS-NEXT: v_mov_b32_e32 v0, s4
; GFX7LESS-NEXT: s_mov_b32 m0, -1 ; GFX7LESS-NEXT: s_mov_b32 m0, -1
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: ds_add_rtn_u64 v[0:1], v1, v[0:1] ; GFX7LESS-NEXT: ds_add_rtn_u64 v[0:1], v1, v[0:1]
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: BB4_2: ; GFX7LESS-NEXT: .LBB4_2:
; GFX7LESS-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX7LESS-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: v_readfirstlane_b32 s2, v0 ; GFX7LESS-NEXT: v_readfirstlane_b32 s2, v0
; GFX7LESS-NEXT: v_readfirstlane_b32 s4, v1 ; GFX7LESS-NEXT: v_readfirstlane_b32 s4, v1
; GFX7LESS-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v2 ; GFX7LESS-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v2
; GFX7LESS-NEXT: v_mul_u32_u24_e32 v0, 5, v2 ; GFX7LESS-NEXT: v_mul_u32_u24_e32 v0, 5, v2
; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000 ; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000
; GFX7LESS-NEXT: v_mov_b32_e32 v2, s4 ; GFX7LESS-NEXT: v_mov_b32_e32 v2, s4
; GFX7LESS-NEXT: v_add_i32_e32 v0, vcc, s2, v0 ; GFX7LESS-NEXT: v_add_i32_e32 v0, vcc, s2, v0
; GFX7LESS-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc ; GFX7LESS-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc
; GFX7LESS-NEXT: s_mov_b32 s2, -1 ; GFX7LESS-NEXT: s_mov_b32 s2, -1
; GFX7LESS-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX7LESS-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX7LESS-NEXT: s_endpgm ; GFX7LESS-NEXT: s_endpgm
; ;
; GFX8-LABEL: add_i64_constant: ; GFX8-LABEL: add_i64_constant:
; GFX8: ; %bb.0: ; %entry ; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX8-NEXT: s_mov_b64 s[4:5], exec ; GFX8-NEXT: s_mov_b64 s[4:5], exec
; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 ; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0
; GFX8-NEXT: v_mbcnt_hi_u32_b32 v2, s5, v0 ; GFX8-NEXT: v_mbcnt_hi_u32_b32 v2, s5, v0
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX8-NEXT: s_cbranch_execz BB4_2 ; GFX8-NEXT: s_cbranch_execz .LBB4_2
; GFX8-NEXT: ; %bb.1: ; GFX8-NEXT: ; %bb.1:
; GFX8-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX8-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
; GFX8-NEXT: s_mul_i32 s4, s4, 5 ; GFX8-NEXT: s_mul_i32 s4, s4, 5
; GFX8-NEXT: v_mov_b32_e32 v0, s4 ; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, 0 ; GFX8-NEXT: v_mov_b32_e32 v1, 0
; GFX8-NEXT: s_mov_b32 m0, -1 ; GFX8-NEXT: s_mov_b32 m0, -1
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: ds_add_rtn_u64 v[0:1], v1, v[0:1] ; GFX8-NEXT: ds_add_rtn_u64 v[0:1], v1, v[0:1]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: BB4_2: ; GFX8-NEXT: .LBB4_2:
; GFX8-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX8-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_readfirstlane_b32 s2, v0 ; GFX8-NEXT: v_readfirstlane_b32 s2, v0
; GFX8-NEXT: v_readfirstlane_b32 s3, v1 ; GFX8-NEXT: v_readfirstlane_b32 s3, v1
; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: v_mad_u64_u32 v[0:1], s[2:3], v2, 5, v[0:1] ; GFX8-NEXT: v_mad_u64_u32 v[0:1], s[2:3], v2, 5, v[0:1]
; GFX8-NEXT: s_mov_b32 s3, 0xf000 ; GFX8-NEXT: s_mov_b32 s3, 0xf000
; GFX8-NEXT: s_mov_b32 s2, -1 ; GFX8-NEXT: s_mov_b32 s2, -1
; GFX8-NEXT: s_nop 2 ; GFX8-NEXT: s_nop 2
; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-LABEL: add_i64_constant: ; GFX9-LABEL: add_i64_constant:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: s_mov_b64 s[4:5], exec ; GFX9-NEXT: s_mov_b64 s[4:5], exec
; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 ; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0
; GFX9-NEXT: v_mbcnt_hi_u32_b32 v2, s5, v0 ; GFX9-NEXT: v_mbcnt_hi_u32_b32 v2, s5, v0
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-NEXT: s_cbranch_execz BB4_2 ; GFX9-NEXT: s_cbranch_execz .LBB4_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX9-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
; GFX9-NEXT: s_mul_i32 s4, s4, 5 ; GFX9-NEXT: s_mul_i32 s4, s4, 5
; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: ds_add_rtn_u64 v[0:1], v1, v[0:1] ; GFX9-NEXT: ds_add_rtn_u64 v[0:1], v1, v[0:1]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: BB4_2: ; GFX9-NEXT: .LBB4_2:
; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX9-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s2, v0 ; GFX9-NEXT: v_readfirstlane_b32 s2, v0
; GFX9-NEXT: v_readfirstlane_b32 s3, v1 ; GFX9-NEXT: v_readfirstlane_b32 s3, v1
; GFX9-NEXT: v_mov_b32_e32 v0, s2 ; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[2:3], v2, 5, v[0:1] ; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[2:3], v2, 5, v[0:1]
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_nop 2 ; GFX9-NEXT: s_nop 2
; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX1064-LABEL: add_i64_constant: ; GFX1064-LABEL: add_i64_constant:
; GFX1064: ; %bb.0: ; %entry ; GFX1064: ; %bb.0: ; %entry
; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX1064-NEXT: s_mov_b64 s[4:5], exec ; GFX1064-NEXT: s_mov_b64 s[4:5], exec
; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0
; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v2, s5, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v2, s5, v0
; GFX1064-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX1064-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX1064-NEXT: s_cbranch_execz BB4_2 ; GFX1064-NEXT: s_cbranch_execz .LBB4_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX1064-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
; GFX1064-NEXT: v_mov_b32_e32 v1, 0 ; GFX1064-NEXT: v_mov_b32_e32 v1, 0
; GFX1064-NEXT: s_mul_i32 s4, s4, 5 ; GFX1064-NEXT: s_mul_i32 s4, s4, 5
; GFX1064-NEXT: v_mov_b32_e32 v0, s4 ; GFX1064-NEXT: v_mov_b32_e32 v0, s4
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: ds_add_rtn_u64 v[0:1], v1, v[0:1] ; GFX1064-NEXT: ds_add_rtn_u64 v[0:1], v1, v[0:1]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: BB4_2: ; GFX1064-NEXT: .LBB4_2:
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX1064-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX1064-NEXT: v_readfirstlane_b32 s2, v0 ; GFX1064-NEXT: v_readfirstlane_b32 s2, v0
; GFX1064-NEXT: v_readfirstlane_b32 s3, v1 ; GFX1064-NEXT: v_readfirstlane_b32 s3, v1
; GFX1064-NEXT: v_mad_u64_u32 v[0:1], s[2:3], v2, 5, s[2:3] ; GFX1064-NEXT: v_mad_u64_u32 v[0:1], s[2:3], v2, 5, s[2:3]
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064-NEXT: s_mov_b32 s2, -1 ; GFX1064-NEXT: s_mov_b32 s2, -1
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: s_endpgm
; ;
; GFX1032-LABEL: add_i64_constant: ; GFX1032-LABEL: add_i64_constant:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX1032-NEXT: s_mov_b32 s3, exec_lo ; GFX1032-NEXT: s_mov_b32 s3, exec_lo
; GFX1032-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX1032-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v2, s3, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v2, s3, 0
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX1032-NEXT: s_and_saveexec_b32 s2, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s2, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB4_2 ; GFX1032-NEXT: s_cbranch_execz .LBB4_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: s_bcnt1_i32_b32 s3, s3 ; GFX1032-NEXT: s_bcnt1_i32_b32 s3, s3
; GFX1032-NEXT: v_mov_b32_e32 v1, 0 ; GFX1032-NEXT: v_mov_b32_e32 v1, 0
; GFX1032-NEXT: s_mul_i32 s3, s3, 5 ; GFX1032-NEXT: s_mul_i32 s3, s3, 5
; GFX1032-NEXT: v_mov_b32_e32 v0, s3 ; GFX1032-NEXT: v_mov_b32_e32 v0, s3
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: ds_add_rtn_u64 v[0:1], v1, v[0:1] ; GFX1032-NEXT: ds_add_rtn_u64 v[0:1], v1, v[0:1]
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: BB4_2: ; GFX1032-NEXT: .LBB4_2:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX1032-NEXT: v_readfirstlane_b32 s2, v0 ; GFX1032-NEXT: v_readfirstlane_b32 s2, v0
; GFX1032-NEXT: v_readfirstlane_b32 s3, v1 ; GFX1032-NEXT: v_readfirstlane_b32 s3, v1
; GFX1032-NEXT: v_mad_u64_u32 v[0:1], s2, v2, 5, s[2:3] ; GFX1032-NEXT: v_mad_u64_u32 v[0:1], s2, v2, 5, s[2:3]
; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s3, 0x31016000
; GFX1032-NEXT: s_mov_b32 s2, -1 ; GFX1032-NEXT: s_mov_b32 s2, -1
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
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; GFX7LESS: ; %bb.0: ; %entry ; GFX7LESS: ; %bb.0: ; %entry
; GFX7LESS-NEXT: s_mov_b64 s[6:7], exec ; GFX7LESS-NEXT: s_mov_b64 s[6:7], exec
; GFX7LESS-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GFX7LESS-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0 ; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0
; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v2, s7, v0 ; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v2, s7, v0
; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX7LESS-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX7LESS-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX7LESS-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX7LESS-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX7LESS-NEXT: s_cbranch_execz BB5_2 ; GFX7LESS-NEXT: s_cbranch_execz .LBB5_2
; GFX7LESS-NEXT: ; %bb.1: ; GFX7LESS-NEXT: ; %bb.1:
; GFX7LESS-NEXT: s_bcnt1_i32_b64 s6, s[6:7] ; GFX7LESS-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
; GFX7LESS-NEXT: v_mov_b32_e32 v3, 0 ; GFX7LESS-NEXT: v_mov_b32_e32 v3, 0
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: s_mul_i32 s7, s3, s6 ; GFX7LESS-NEXT: s_mul_i32 s7, s3, s6
; GFX7LESS-NEXT: v_mov_b32_e32 v0, s6 ; GFX7LESS-NEXT: v_mov_b32_e32 v0, s6
; GFX7LESS-NEXT: v_mul_hi_u32 v0, s2, v0 ; GFX7LESS-NEXT: v_mul_hi_u32 v0, s2, v0
; GFX7LESS-NEXT: s_mul_i32 s6, s2, s6 ; GFX7LESS-NEXT: s_mul_i32 s6, s2, s6
; GFX7LESS-NEXT: v_add_i32_e32 v1, vcc, s7, v0 ; GFX7LESS-NEXT: v_add_i32_e32 v1, vcc, s7, v0
; GFX7LESS-NEXT: v_mov_b32_e32 v0, s6 ; GFX7LESS-NEXT: v_mov_b32_e32 v0, s6
; GFX7LESS-NEXT: s_mov_b32 m0, -1 ; GFX7LESS-NEXT: s_mov_b32 m0, -1
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: ds_add_rtn_u64 v[0:1], v3, v[0:1] ; GFX7LESS-NEXT: ds_add_rtn_u64 v[0:1], v3, v[0:1]
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: BB5_2: ; GFX7LESS-NEXT: .LBB5_2:
; GFX7LESS-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX7LESS-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX7LESS-NEXT: s_mov_b32 s7, 0xf000 ; GFX7LESS-NEXT: s_mov_b32 s7, 0xf000
; GFX7LESS-NEXT: s_mov_b32 s6, -1 ; GFX7LESS-NEXT: s_mov_b32 s6, -1
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: s_mov_b32 s4, s0 ; GFX7LESS-NEXT: s_mov_b32 s4, s0
; GFX7LESS-NEXT: s_mov_b32 s5, s1 ; GFX7LESS-NEXT: s_mov_b32 s5, s1
; GFX7LESS-NEXT: v_readfirstlane_b32 s0, v0 ; GFX7LESS-NEXT: v_readfirstlane_b32 s0, v0
; GFX7LESS-NEXT: v_readfirstlane_b32 s1, v1 ; GFX7LESS-NEXT: v_readfirstlane_b32 s1, v1
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; GFX8: ; %bb.0: ; %entry ; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX8-NEXT: s_mov_b64 s[6:7], exec ; GFX8-NEXT: s_mov_b64 s[6:7], exec
; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0 ; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
; GFX8-NEXT: v_mbcnt_hi_u32_b32 v2, s7, v0 ; GFX8-NEXT: v_mbcnt_hi_u32_b32 v2, s7, v0
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX8-NEXT: s_cbranch_execz BB5_2 ; GFX8-NEXT: s_cbranch_execz .LBB5_2
; GFX8-NEXT: ; %bb.1: ; GFX8-NEXT: ; %bb.1:
; GFX8-NEXT: s_bcnt1_i32_b64 s6, s[6:7] ; GFX8-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
; GFX8-NEXT: v_mov_b32_e32 v0, s6 ; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mul_hi_u32 v0, s2, v0 ; GFX8-NEXT: v_mul_hi_u32 v0, s2, v0
; GFX8-NEXT: s_mul_i32 s7, s3, s6 ; GFX8-NEXT: s_mul_i32 s7, s3, s6
; GFX8-NEXT: s_mul_i32 s6, s2, s6 ; GFX8-NEXT: s_mul_i32 s6, s2, s6
; GFX8-NEXT: v_mov_b32_e32 v3, 0 ; GFX8-NEXT: v_mov_b32_e32 v3, 0
; GFX8-NEXT: v_add_u32_e32 v1, vcc, s7, v0 ; GFX8-NEXT: v_add_u32_e32 v1, vcc, s7, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s6 ; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: s_mov_b32 m0, -1 ; GFX8-NEXT: s_mov_b32 m0, -1
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: ds_add_rtn_u64 v[0:1], v3, v[0:1] ; GFX8-NEXT: ds_add_rtn_u64 v[0:1], v3, v[0:1]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: BB5_2: ; GFX8-NEXT: .LBB5_2:
; GFX8-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_mov_b32 s4, s0 ; GFX8-NEXT: s_mov_b32 s4, s0
; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: v_mul_lo_u32 v0, s3, v2 ; GFX8-NEXT: v_mul_lo_u32 v0, s3, v2
; GFX8-NEXT: v_mul_hi_u32 v3, s2, v2 ; GFX8-NEXT: v_mul_hi_u32 v3, s2, v2
; GFX8-NEXT: s_mov_b32 s5, s1 ; GFX8-NEXT: s_mov_b32 s5, s1
; GFX8-NEXT: v_readfirstlane_b32 s1, v1 ; GFX8-NEXT: v_readfirstlane_b32 s1, v1
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; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: s_mov_b64 s[6:7], exec ; GFX9-NEXT: s_mov_b64 s[6:7], exec
; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0 ; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
; GFX9-NEXT: v_mbcnt_hi_u32_b32 v2, s7, v0 ; GFX9-NEXT: v_mbcnt_hi_u32_b32 v2, s7, v0
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_cbranch_execz BB5_2 ; GFX9-NEXT: s_cbranch_execz .LBB5_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: s_bcnt1_i32_b64 s6, s[6:7] ; GFX9-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mul_i32 s7, s3, s6 ; GFX9-NEXT: s_mul_i32 s7, s3, s6
; GFX9-NEXT: s_mul_hi_u32 s8, s2, s6 ; GFX9-NEXT: s_mul_hi_u32 s8, s2, s6
; GFX9-NEXT: s_add_i32 s8, s8, s7 ; GFX9-NEXT: s_add_i32 s8, s8, s7
; GFX9-NEXT: s_mul_i32 s6, s2, s6 ; GFX9-NEXT: s_mul_i32 s6, s2, s6
; GFX9-NEXT: v_mov_b32_e32 v0, s6 ; GFX9-NEXT: v_mov_b32_e32 v0, s6
; GFX9-NEXT: v_mov_b32_e32 v1, s8 ; GFX9-NEXT: v_mov_b32_e32 v1, s8
; GFX9-NEXT: v_mov_b32_e32 v3, 0 ; GFX9-NEXT: v_mov_b32_e32 v3, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: ds_add_rtn_u64 v[0:1], v3, v[0:1] ; GFX9-NEXT: ds_add_rtn_u64 v[0:1], v3, v[0:1]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: BB5_2: ; GFX9-NEXT: .LBB5_2:
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, s0 ; GFX9-NEXT: s_mov_b32 s4, s0
; GFX9-NEXT: v_mul_lo_u32 v3, s3, v2 ; GFX9-NEXT: v_mul_lo_u32 v3, s3, v2
; GFX9-NEXT: v_mul_hi_u32 v4, s2, v2 ; GFX9-NEXT: v_mul_hi_u32 v4, s2, v2
; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: v_mul_lo_u32 v0, s2, v2 ; GFX9-NEXT: v_mul_lo_u32 v0, s2, v2
; GFX9-NEXT: s_mov_b32 s5, s1 ; GFX9-NEXT: s_mov_b32 s5, s1
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; GFX1064: ; %bb.0: ; %entry ; GFX1064: ; %bb.0: ; %entry
; GFX1064-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX1064-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX1064-NEXT: s_mov_b64 s[6:7], exec ; GFX1064-NEXT: s_mov_b64 s[6:7], exec
; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v2, s7, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v2, s7, v0
; GFX1064-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX1064-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX1064-NEXT: s_cbranch_execz BB5_2 ; GFX1064-NEXT: s_cbranch_execz .LBB5_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: s_bcnt1_i32_b64 s6, s[6:7] ; GFX1064-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
; GFX1064-NEXT: v_mov_b32_e32 v3, 0 ; GFX1064-NEXT: v_mov_b32_e32 v3, 0
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: s_mul_i32 s7, s3, s6 ; GFX1064-NEXT: s_mul_i32 s7, s3, s6
; GFX1064-NEXT: s_mul_hi_u32 s8, s2, s6 ; GFX1064-NEXT: s_mul_hi_u32 s8, s2, s6
; GFX1064-NEXT: s_mul_i32 s6, s2, s6 ; GFX1064-NEXT: s_mul_i32 s6, s2, s6
; GFX1064-NEXT: s_add_i32 s8, s8, s7 ; GFX1064-NEXT: s_add_i32 s8, s8, s7
; GFX1064-NEXT: v_mov_b32_e32 v0, s6 ; GFX1064-NEXT: v_mov_b32_e32 v0, s6
; GFX1064-NEXT: v_mov_b32_e32 v1, s8 ; GFX1064-NEXT: v_mov_b32_e32 v1, s8
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: ds_add_rtn_u64 v[0:1], v3, v[0:1] ; GFX1064-NEXT: ds_add_rtn_u64 v[0:1], v3, v[0:1]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: BB5_2: ; GFX1064-NEXT: .LBB5_2:
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: v_mul_lo_u32 v3, s3, v2 ; GFX1064-NEXT: v_mul_lo_u32 v3, s3, v2
; GFX1064-NEXT: v_mul_hi_u32 v4, s2, v2 ; GFX1064-NEXT: v_mul_hi_u32 v4, s2, v2
; GFX1064-NEXT: v_mul_lo_u32 v2, s2, v2 ; GFX1064-NEXT: v_mul_lo_u32 v2, s2, v2
; GFX1064-NEXT: v_readfirstlane_b32 s2, v0 ; GFX1064-NEXT: v_readfirstlane_b32 s2, v0
; GFX1064-NEXT: v_readfirstlane_b32 s4, v1 ; GFX1064-NEXT: v_readfirstlane_b32 s4, v1
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064-NEXT: v_add_nc_u32_e32 v1, v4, v3 ; GFX1064-NEXT: v_add_nc_u32_e32 v1, v4, v3
; GFX1064-NEXT: v_add_co_u32 v0, vcc, s2, v2 ; GFX1064-NEXT: v_add_co_u32 v0, vcc, s2, v2
; GFX1064-NEXT: s_mov_b32 s2, -1 ; GFX1064-NEXT: s_mov_b32 s2, -1
; GFX1064-NEXT: v_add_co_ci_u32_e32 v1, vcc, s4, v1, vcc ; GFX1064-NEXT: v_add_co_ci_u32_e32 v1, vcc, s4, v1, vcc
; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: s_endpgm
; ;
; GFX1032-LABEL: add_i64_uniform: ; GFX1032-LABEL: add_i64_uniform:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX1032-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX1032-NEXT: s_mov_b32 s5, exec_lo ; GFX1032-NEXT: s_mov_b32 s5, exec_lo
; GFX1032-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX1032-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v2, s5, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v2, s5, 0
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX1032-NEXT: s_and_saveexec_b32 s4, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s4, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB5_2 ; GFX1032-NEXT: s_cbranch_execz .LBB5_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: s_bcnt1_i32_b32 s5, s5 ; GFX1032-NEXT: s_bcnt1_i32_b32 s5, s5
; GFX1032-NEXT: v_mov_b32_e32 v3, 0 ; GFX1032-NEXT: v_mov_b32_e32 v3, 0
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: s_mul_i32 s6, s3, s5 ; GFX1032-NEXT: s_mul_i32 s6, s3, s5
; GFX1032-NEXT: s_mul_hi_u32 s7, s2, s5 ; GFX1032-NEXT: s_mul_hi_u32 s7, s2, s5
; GFX1032-NEXT: s_mul_i32 s5, s2, s5 ; GFX1032-NEXT: s_mul_i32 s5, s2, s5
; GFX1032-NEXT: s_add_i32 s7, s7, s6 ; GFX1032-NEXT: s_add_i32 s7, s7, s6
; GFX1032-NEXT: v_mov_b32_e32 v0, s5 ; GFX1032-NEXT: v_mov_b32_e32 v0, s5
; GFX1032-NEXT: v_mov_b32_e32 v1, s7 ; GFX1032-NEXT: v_mov_b32_e32 v1, s7
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: ds_add_rtn_u64 v[0:1], v3, v[0:1] ; GFX1032-NEXT: ds_add_rtn_u64 v[0:1], v3, v[0:1]
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: BB5_2: ; GFX1032-NEXT: .LBB5_2:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: v_mul_lo_u32 v3, s3, v2 ; GFX1032-NEXT: v_mul_lo_u32 v3, s3, v2
; GFX1032-NEXT: v_mul_hi_u32 v4, s2, v2 ; GFX1032-NEXT: v_mul_hi_u32 v4, s2, v2
; GFX1032-NEXT: v_mul_lo_u32 v2, s2, v2 ; GFX1032-NEXT: v_mul_lo_u32 v2, s2, v2
; GFX1032-NEXT: v_readfirstlane_b32 s2, v0 ; GFX1032-NEXT: v_readfirstlane_b32 s2, v0
; GFX1032-NEXT: v_readfirstlane_b32 s4, v1 ; GFX1032-NEXT: v_readfirstlane_b32 s4, v1
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; GFX7LESS: ; %bb.0: ; %entry ; GFX7LESS: ; %bb.0: ; %entry
; GFX7LESS-NEXT: s_mov_b64 s[2:3], exec ; GFX7LESS-NEXT: s_mov_b64 s[2:3], exec
; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 ; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0
; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s3, v0 ; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s3, v0
; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX7LESS-NEXT: ; implicit-def: $vgpr1 ; GFX7LESS-NEXT: ; implicit-def: $vgpr1
; GFX7LESS-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX7LESS-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX7LESS-NEXT: s_cbranch_execz BB7_2 ; GFX7LESS-NEXT: s_cbranch_execz .LBB7_2
; GFX7LESS-NEXT: ; %bb.1: ; GFX7LESS-NEXT: ; %bb.1:
; GFX7LESS-NEXT: s_bcnt1_i32_b64 s2, s[2:3] ; GFX7LESS-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX7LESS-NEXT: s_mul_i32 s2, s2, 5 ; GFX7LESS-NEXT: s_mul_i32 s2, s2, 5
; GFX7LESS-NEXT: v_mov_b32_e32 v1, 0 ; GFX7LESS-NEXT: v_mov_b32_e32 v1, 0
; GFX7LESS-NEXT: v_mov_b32_e32 v2, s2 ; GFX7LESS-NEXT: v_mov_b32_e32 v2, s2
; GFX7LESS-NEXT: s_mov_b32 m0, -1 ; GFX7LESS-NEXT: s_mov_b32 m0, -1
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: ds_sub_rtn_u32 v1, v1, v2 ; GFX7LESS-NEXT: ds_sub_rtn_u32 v1, v1, v2
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: BB7_2: ; GFX7LESS-NEXT: .LBB7_2:
; GFX7LESS-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX7LESS-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: v_readfirstlane_b32 s2, v1 ; GFX7LESS-NEXT: v_readfirstlane_b32 s2, v1
; GFX7LESS-NEXT: v_mul_u32_u24_e32 v0, 5, v0 ; GFX7LESS-NEXT: v_mul_u32_u24_e32 v0, 5, v0
; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000 ; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000
; GFX7LESS-NEXT: v_sub_i32_e32 v0, vcc, s2, v0 ; GFX7LESS-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
; GFX7LESS-NEXT: s_mov_b32 s2, -1 ; GFX7LESS-NEXT: s_mov_b32 s2, -1
; GFX7LESS-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX7LESS-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7LESS-NEXT: s_endpgm ; GFX7LESS-NEXT: s_endpgm
; ;
; GFX8-LABEL: sub_i32_constant: ; GFX8-LABEL: sub_i32_constant:
; GFX8: ; %bb.0: ; %entry ; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX8-NEXT: s_mov_b64 s[2:3], exec ; GFX8-NEXT: s_mov_b64 s[2:3], exec
; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 ; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 ; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX8-NEXT: ; implicit-def: $vgpr1 ; GFX8-NEXT: ; implicit-def: $vgpr1
; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX8-NEXT: s_cbranch_execz BB7_2 ; GFX8-NEXT: s_cbranch_execz .LBB7_2
; GFX8-NEXT: ; %bb.1: ; GFX8-NEXT: ; %bb.1:
; GFX8-NEXT: s_bcnt1_i32_b64 s2, s[2:3] ; GFX8-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX8-NEXT: s_mul_i32 s2, s2, 5 ; GFX8-NEXT: s_mul_i32 s2, s2, 5
; GFX8-NEXT: v_mov_b32_e32 v1, 0 ; GFX8-NEXT: v_mov_b32_e32 v1, 0
; GFX8-NEXT: v_mov_b32_e32 v2, s2 ; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: s_mov_b32 m0, -1 ; GFX8-NEXT: s_mov_b32 m0, -1
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: ds_sub_rtn_u32 v1, v1, v2 ; GFX8-NEXT: ds_sub_rtn_u32 v1, v1, v2
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: BB7_2: ; GFX8-NEXT: .LBB7_2:
; GFX8-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_readfirstlane_b32 s2, v1 ; GFX8-NEXT: v_readfirstlane_b32 s2, v1
; GFX8-NEXT: v_mul_u32_u24_e32 v0, 5, v0 ; GFX8-NEXT: v_mul_u32_u24_e32 v0, 5, v0
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s2, v0 ; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s2, v0
; GFX8-NEXT: s_mov_b32 s3, 0xf000 ; GFX8-NEXT: s_mov_b32 s3, 0xf000
; GFX8-NEXT: s_mov_b32 s2, -1 ; GFX8-NEXT: s_mov_b32 s2, -1
; GFX8-NEXT: s_nop 0 ; GFX8-NEXT: s_nop 0
; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-LABEL: sub_i32_constant: ; GFX9-LABEL: sub_i32_constant:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: s_mov_b64 s[2:3], exec ; GFX9-NEXT: s_mov_b64 s[2:3], exec
; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 ; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 ; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-NEXT: ; implicit-def: $vgpr1 ; GFX9-NEXT: ; implicit-def: $vgpr1
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_cbranch_execz BB7_2 ; GFX9-NEXT: s_cbranch_execz .LBB7_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: s_bcnt1_i32_b64 s2, s[2:3] ; GFX9-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX9-NEXT: s_mul_i32 s2, s2, 5 ; GFX9-NEXT: s_mul_i32 s2, s2, 5
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: v_mov_b32_e32 v2, s2 ; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: ds_sub_rtn_u32 v1, v1, v2 ; GFX9-NEXT: ds_sub_rtn_u32 v1, v1, v2
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: BB7_2: ; GFX9-NEXT: .LBB7_2:
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s2, v1 ; GFX9-NEXT: v_readfirstlane_b32 s2, v1
; GFX9-NEXT: v_mul_u32_u24_e32 v0, 5, v0 ; GFX9-NEXT: v_mul_u32_u24_e32 v0, 5, v0
; GFX9-NEXT: v_sub_u32_e32 v0, s2, v0 ; GFX9-NEXT: v_sub_u32_e32 v0, s2, v0
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX1064-LABEL: sub_i32_constant: ; GFX1064-LABEL: sub_i32_constant:
; GFX1064: ; %bb.0: ; %entry ; GFX1064: ; %bb.0: ; %entry
; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX1064-NEXT: s_mov_b64 s[2:3], exec ; GFX1064-NEXT: s_mov_b64 s[2:3], exec
; GFX1064-NEXT: ; implicit-def: $vgpr1 ; GFX1064-NEXT: ; implicit-def: $vgpr1
; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX1064-NEXT: s_cbranch_execz BB7_2 ; GFX1064-NEXT: s_cbranch_execz .LBB7_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: s_bcnt1_i32_b64 s2, s[2:3] ; GFX1064-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX1064-NEXT: v_mov_b32_e32 v1, 0 ; GFX1064-NEXT: v_mov_b32_e32 v1, 0
; GFX1064-NEXT: s_mul_i32 s2, s2, 5 ; GFX1064-NEXT: s_mul_i32 s2, s2, 5
; GFX1064-NEXT: v_mov_b32_e32 v2, s2 ; GFX1064-NEXT: v_mov_b32_e32 v2, s2
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: ds_sub_rtn_u32 v1, v1, v2 ; GFX1064-NEXT: ds_sub_rtn_u32 v1, v1, v2
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: BB7_2: ; GFX1064-NEXT: .LBB7_2:
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX1064-NEXT: v_readfirstlane_b32 s2, v1 ; GFX1064-NEXT: v_readfirstlane_b32 s2, v1
; GFX1064-NEXT: v_mul_u32_u24_e32 v0, 5, v0 ; GFX1064-NEXT: v_mul_u32_u24_e32 v0, 5, v0
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064-NEXT: v_sub_nc_u32_e32 v0, s2, v0 ; GFX1064-NEXT: v_sub_nc_u32_e32 v0, s2, v0
; GFX1064-NEXT: s_mov_b32 s2, -1 ; GFX1064-NEXT: s_mov_b32 s2, -1
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: s_endpgm
; ;
; GFX1032-LABEL: sub_i32_constant: ; GFX1032-LABEL: sub_i32_constant:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX1032-NEXT: s_mov_b32 s3, exec_lo ; GFX1032-NEXT: s_mov_b32 s3, exec_lo
; GFX1032-NEXT: ; implicit-def: $vgpr1 ; GFX1032-NEXT: ; implicit-def: $vgpr1
; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, s3, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, s3, 0
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: s_and_saveexec_b32 s2, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s2, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB7_2 ; GFX1032-NEXT: s_cbranch_execz .LBB7_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: s_bcnt1_i32_b32 s3, s3 ; GFX1032-NEXT: s_bcnt1_i32_b32 s3, s3
; GFX1032-NEXT: v_mov_b32_e32 v1, 0 ; GFX1032-NEXT: v_mov_b32_e32 v1, 0
; GFX1032-NEXT: s_mul_i32 s3, s3, 5 ; GFX1032-NEXT: s_mul_i32 s3, s3, 5
; GFX1032-NEXT: v_mov_b32_e32 v2, s3 ; GFX1032-NEXT: v_mov_b32_e32 v2, s3
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: ds_sub_rtn_u32 v1, v1, v2 ; GFX1032-NEXT: ds_sub_rtn_u32 v1, v1, v2
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: BB7_2: ; GFX1032-NEXT: .LBB7_2:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX1032-NEXT: v_readfirstlane_b32 s2, v1 ; GFX1032-NEXT: v_readfirstlane_b32 s2, v1
; GFX1032-NEXT: v_mul_u32_u24_e32 v0, 5, v0 ; GFX1032-NEXT: v_mul_u32_u24_e32 v0, 5, v0
; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s3, 0x31016000
; GFX1032-NEXT: v_sub_nc_u32_e32 v0, s2, v0 ; GFX1032-NEXT: v_sub_nc_u32_e32 v0, s2, v0
; GFX1032-NEXT: s_mov_b32 s2, -1 ; GFX1032-NEXT: s_mov_b32 s2, -1
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
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; GFX7LESS-NEXT: s_mov_b64 s[2:3], exec ; GFX7LESS-NEXT: s_mov_b64 s[2:3], exec
; GFX7LESS-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; GFX7LESS-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GFX7LESS-NEXT: s_load_dword s6, s[0:1], 0xb ; GFX7LESS-NEXT: s_load_dword s6, s[0:1], 0xb
; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 ; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0
; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s3, v0 ; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s3, v0
; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX7LESS-NEXT: ; implicit-def: $vgpr1 ; GFX7LESS-NEXT: ; implicit-def: $vgpr1
; GFX7LESS-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX7LESS-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX7LESS-NEXT: s_cbranch_execz BB8_2 ; GFX7LESS-NEXT: s_cbranch_execz .LBB8_2
; GFX7LESS-NEXT: ; %bb.1: ; GFX7LESS-NEXT: ; %bb.1:
; GFX7LESS-NEXT: s_bcnt1_i32_b64 s2, s[2:3] ; GFX7LESS-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: s_mul_i32 s2, s6, s2 ; GFX7LESS-NEXT: s_mul_i32 s2, s6, s2
; GFX7LESS-NEXT: v_mov_b32_e32 v1, 0 ; GFX7LESS-NEXT: v_mov_b32_e32 v1, 0
; GFX7LESS-NEXT: v_mov_b32_e32 v2, s2 ; GFX7LESS-NEXT: v_mov_b32_e32 v2, s2
; GFX7LESS-NEXT: s_mov_b32 m0, -1 ; GFX7LESS-NEXT: s_mov_b32 m0, -1
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: ds_sub_rtn_u32 v1, v1, v2 ; GFX7LESS-NEXT: ds_sub_rtn_u32 v1, v1, v2
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: BB8_2: ; GFX7LESS-NEXT: .LBB8_2:
; GFX7LESS-NEXT: s_or_b64 exec, exec, s[0:1] ; GFX7LESS-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: v_readfirstlane_b32 s0, v1 ; GFX7LESS-NEXT: v_readfirstlane_b32 s0, v1
; GFX7LESS-NEXT: v_mul_lo_u32 v0, s6, v0 ; GFX7LESS-NEXT: v_mul_lo_u32 v0, s6, v0
; GFX7LESS-NEXT: s_mov_b32 s7, 0xf000 ; GFX7LESS-NEXT: s_mov_b32 s7, 0xf000
; GFX7LESS-NEXT: v_sub_i32_e32 v0, vcc, s0, v0 ; GFX7LESS-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
; GFX7LESS-NEXT: s_mov_b32 s6, -1 ; GFX7LESS-NEXT: s_mov_b32 s6, -1
; GFX7LESS-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GFX7LESS-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX7LESS-NEXT: s_endpgm ; GFX7LESS-NEXT: s_endpgm
; ;
; GFX8-LABEL: sub_i32_uniform: ; GFX8-LABEL: sub_i32_uniform:
; GFX8: ; %bb.0: ; %entry ; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; GFX8-NEXT: s_load_dword s6, s[0:1], 0x2c ; GFX8-NEXT: s_load_dword s6, s[0:1], 0x2c
; GFX8-NEXT: s_mov_b64 s[2:3], exec ; GFX8-NEXT: s_mov_b64 s[2:3], exec
; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 ; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 ; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX8-NEXT: ; implicit-def: $vgpr1 ; GFX8-NEXT: ; implicit-def: $vgpr1
; GFX8-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX8-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX8-NEXT: s_cbranch_execz BB8_2 ; GFX8-NEXT: s_cbranch_execz .LBB8_2
; GFX8-NEXT: ; %bb.1: ; GFX8-NEXT: ; %bb.1:
; GFX8-NEXT: s_bcnt1_i32_b64 s2, s[2:3] ; GFX8-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_mul_i32 s2, s6, s2 ; GFX8-NEXT: s_mul_i32 s2, s6, s2
; GFX8-NEXT: v_mov_b32_e32 v1, 0 ; GFX8-NEXT: v_mov_b32_e32 v1, 0
; GFX8-NEXT: v_mov_b32_e32 v2, s2 ; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: s_mov_b32 m0, -1 ; GFX8-NEXT: s_mov_b32 m0, -1
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: ds_sub_rtn_u32 v1, v1, v2 ; GFX8-NEXT: ds_sub_rtn_u32 v1, v1, v2
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: BB8_2: ; GFX8-NEXT: .LBB8_2:
; GFX8-NEXT: s_or_b64 exec, exec, s[0:1] ; GFX8-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mul_lo_u32 v0, s6, v0 ; GFX8-NEXT: v_mul_lo_u32 v0, s6, v0
; GFX8-NEXT: v_readfirstlane_b32 s0, v1 ; GFX8-NEXT: v_readfirstlane_b32 s0, v1
; GFX8-NEXT: s_mov_b32 s7, 0xf000 ; GFX8-NEXT: s_mov_b32 s7, 0xf000
; GFX8-NEXT: s_mov_b32 s6, -1 ; GFX8-NEXT: s_mov_b32 s6, -1
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s0, v0 ; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s0, v0
; GFX8-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GFX8-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-LABEL: sub_i32_uniform: ; GFX9-LABEL: sub_i32_uniform:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; GFX9-NEXT: s_load_dword s6, s[0:1], 0x2c ; GFX9-NEXT: s_load_dword s6, s[0:1], 0x2c
; GFX9-NEXT: s_mov_b64 s[2:3], exec ; GFX9-NEXT: s_mov_b64 s[2:3], exec
; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 ; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 ; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-NEXT: ; implicit-def: $vgpr1 ; GFX9-NEXT: ; implicit-def: $vgpr1
; GFX9-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX9-NEXT: s_cbranch_execz BB8_2 ; GFX9-NEXT: s_cbranch_execz .LBB8_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: s_bcnt1_i32_b64 s2, s[2:3] ; GFX9-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mul_i32 s2, s6, s2 ; GFX9-NEXT: s_mul_i32 s2, s6, s2
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: v_mov_b32_e32 v2, s2 ; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: ds_sub_rtn_u32 v1, v1, v2 ; GFX9-NEXT: ds_sub_rtn_u32 v1, v1, v2
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: BB8_2: ; GFX9-NEXT: .LBB8_2:
; GFX9-NEXT: s_or_b64 exec, exec, s[0:1] ; GFX9-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mul_lo_u32 v0, s6, v0 ; GFX9-NEXT: v_mul_lo_u32 v0, s6, v0
; GFX9-NEXT: v_readfirstlane_b32 s0, v1 ; GFX9-NEXT: v_readfirstlane_b32 s0, v1
; GFX9-NEXT: s_mov_b32 s7, 0xf000 ; GFX9-NEXT: s_mov_b32 s7, 0xf000
; GFX9-NEXT: s_mov_b32 s6, -1 ; GFX9-NEXT: s_mov_b32 s6, -1
; GFX9-NEXT: v_sub_u32_e32 v0, s0, v0 ; GFX9-NEXT: v_sub_u32_e32 v0, s0, v0
; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX1064-LABEL: sub_i32_uniform: ; GFX1064-LABEL: sub_i32_uniform:
; GFX1064: ; %bb.0: ; %entry ; GFX1064: ; %bb.0: ; %entry
; GFX1064-NEXT: s_clause 0x1 ; GFX1064-NEXT: s_clause 0x1
; GFX1064-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX1064-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; GFX1064-NEXT: s_load_dword s6, s[0:1], 0x2c ; GFX1064-NEXT: s_load_dword s6, s[0:1], 0x2c
; GFX1064-NEXT: s_mov_b64 s[2:3], exec ; GFX1064-NEXT: s_mov_b64 s[2:3], exec
; GFX1064-NEXT: ; implicit-def: $vgpr1 ; GFX1064-NEXT: ; implicit-def: $vgpr1
; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064-NEXT: s_cbranch_execz BB8_2 ; GFX1064-NEXT: s_cbranch_execz .LBB8_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: s_bcnt1_i32_b64 s2, s[2:3] ; GFX1064-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX1064-NEXT: v_mov_b32_e32 v1, 0 ; GFX1064-NEXT: v_mov_b32_e32 v1, 0
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: s_mul_i32 s2, s6, s2 ; GFX1064-NEXT: s_mul_i32 s2, s6, s2
; GFX1064-NEXT: v_mov_b32_e32 v2, s2 ; GFX1064-NEXT: v_mov_b32_e32 v2, s2
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: ds_sub_rtn_u32 v1, v1, v2 ; GFX1064-NEXT: ds_sub_rtn_u32 v1, v1, v2
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: BB8_2: ; GFX1064-NEXT: .LBB8_2:
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[0:1] ; GFX1064-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: v_mul_lo_u32 v0, s6, v0 ; GFX1064-NEXT: v_mul_lo_u32 v0, s6, v0
; GFX1064-NEXT: v_readfirstlane_b32 s0, v1 ; GFX1064-NEXT: v_readfirstlane_b32 s0, v1
; GFX1064-NEXT: s_mov_b32 s7, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s7, 0x31016000
; GFX1064-NEXT: s_mov_b32 s6, -1 ; GFX1064-NEXT: s_mov_b32 s6, -1
; GFX1064-NEXT: v_sub_nc_u32_e32 v0, s0, v0 ; GFX1064-NEXT: v_sub_nc_u32_e32 v0, s0, v0
; GFX1064-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GFX1064-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: s_endpgm
; ;
; GFX1032-LABEL: sub_i32_uniform: ; GFX1032-LABEL: sub_i32_uniform:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_clause 0x1 ; GFX1032-NEXT: s_clause 0x1
; GFX1032-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX1032-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; GFX1032-NEXT: s_load_dword s2, s[0:1], 0x2c ; GFX1032-NEXT: s_load_dword s2, s[0:1], 0x2c
; GFX1032-NEXT: s_mov_b32 s3, exec_lo ; GFX1032-NEXT: s_mov_b32 s3, exec_lo
; GFX1032-NEXT: ; implicit-def: $vgpr1 ; GFX1032-NEXT: ; implicit-def: $vgpr1
; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, s3, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, s3, 0
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: s_and_saveexec_b32 s0, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB8_2 ; GFX1032-NEXT: s_cbranch_execz .LBB8_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: s_bcnt1_i32_b32 s1, s3 ; GFX1032-NEXT: s_bcnt1_i32_b32 s1, s3
; GFX1032-NEXT: v_mov_b32_e32 v1, 0 ; GFX1032-NEXT: v_mov_b32_e32 v1, 0
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: s_mul_i32 s1, s2, s1 ; GFX1032-NEXT: s_mul_i32 s1, s2, s1
; GFX1032-NEXT: v_mov_b32_e32 v2, s1 ; GFX1032-NEXT: v_mov_b32_e32 v2, s1
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: ds_sub_rtn_u32 v1, v1, v2 ; GFX1032-NEXT: ds_sub_rtn_u32 v1, v1, v2
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: BB8_2: ; GFX1032-NEXT: .LBB8_2:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s0 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: v_mul_lo_u32 v0, s2, v0 ; GFX1032-NEXT: v_mul_lo_u32 v0, s2, v0
; GFX1032-NEXT: v_readfirstlane_b32 s0, v1 ; GFX1032-NEXT: v_readfirstlane_b32 s0, v1
; GFX1032-NEXT: s_mov_b32 s7, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s7, 0x31016000
; GFX1032-NEXT: s_mov_b32 s6, -1 ; GFX1032-NEXT: s_mov_b32 s6, -1
; GFX1032-NEXT: v_sub_nc_u32_e32 v0, s0, v0 ; GFX1032-NEXT: v_sub_nc_u32_e32 v0, s0, v0
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; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX8-NEXT: v_readlane_b32 s4, v2, 63 ; GFX8-NEXT: v_readlane_b32 s4, v2, 63
; GFX8-NEXT: s_nop 0 ; GFX8-NEXT: s_nop 0
; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf ; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX8-NEXT: s_mov_b64 exec, s[2:3] ; GFX8-NEXT: s_mov_b64 exec, s[2:3]
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX8-NEXT: ; implicit-def: $vgpr0 ; GFX8-NEXT: ; implicit-def: $vgpr0
; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX8-NEXT: s_cbranch_execz BB9_2 ; GFX8-NEXT: s_cbranch_execz .LBB9_2
; GFX8-NEXT: ; %bb.1: ; GFX8-NEXT: ; %bb.1:
; GFX8-NEXT: v_mov_b32_e32 v0, 0 ; GFX8-NEXT: v_mov_b32_e32 v0, 0
; GFX8-NEXT: v_mov_b32_e32 v3, s4 ; GFX8-NEXT: v_mov_b32_e32 v3, s4
; GFX8-NEXT: s_mov_b32 m0, -1 ; GFX8-NEXT: s_mov_b32 m0, -1
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: ds_sub_rtn_u32 v0, v0, v3 ; GFX8-NEXT: ds_sub_rtn_u32 v0, v0, v3
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: BB9_2: ; GFX8-NEXT: .LBB9_2:
; GFX8-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX8-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_readfirstlane_b32 s2, v0 ; GFX8-NEXT: v_readfirstlane_b32 s2, v0
; GFX8-NEXT: v_mov_b32_e32 v0, v1 ; GFX8-NEXT: v_mov_b32_e32 v0, v1
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s2, v0 ; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s2, v0
; GFX8-NEXT: s_mov_b32 s3, 0xf000 ; GFX8-NEXT: s_mov_b32 s3, 0xf000
; GFX8-NEXT: s_mov_b32 s2, -1 ; GFX8-NEXT: s_mov_b32 s2, -1
; GFX8-NEXT: s_nop 0 ; GFX8-NEXT: s_nop 0
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; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9-NEXT: v_readlane_b32 s4, v2, 63 ; GFX9-NEXT: v_readlane_b32 s4, v2, 63
; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: s_nop 0
; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf ; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX9-NEXT: s_mov_b64 exec, s[2:3] ; GFX9-NEXT: s_mov_b64 exec, s[2:3]
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-NEXT: ; implicit-def: $vgpr0 ; GFX9-NEXT: ; implicit-def: $vgpr0
; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-NEXT: s_cbranch_execz BB9_2 ; GFX9-NEXT: s_cbranch_execz .LBB9_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v3, s4 ; GFX9-NEXT: v_mov_b32_e32 v3, s4
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: ds_sub_rtn_u32 v0, v0, v3 ; GFX9-NEXT: ds_sub_rtn_u32 v0, v0, v3
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: BB9_2: ; GFX9-NEXT: .LBB9_2:
; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX9-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s2, v0 ; GFX9-NEXT: v_readfirstlane_b32 s2, v0
; GFX9-NEXT: v_mov_b32_e32 v0, v1 ; GFX9-NEXT: v_mov_b32_e32 v0, v1
; GFX9-NEXT: v_sub_u32_e32 v0, s2, v0 ; GFX9-NEXT: v_sub_u32_e32 v0, s2, v0
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: s_nop 0
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; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1064-NEXT: s_or_saveexec_b64 s[4:5], -1 ; GFX1064-NEXT: s_or_saveexec_b64 s[4:5], -1
; GFX1064-NEXT: v_writelane_b32 v3, s6, 48 ; GFX1064-NEXT: v_writelane_b32 v3, s6, 48
; GFX1064-NEXT: s_mov_b64 exec, s[4:5] ; GFX1064-NEXT: s_mov_b64 exec, s[4:5]
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: s_mov_b32 s2, -1 ; GFX1064-NEXT: s_mov_b32 s2, -1
; GFX1064-NEXT: ; implicit-def: $vgpr0 ; GFX1064-NEXT: ; implicit-def: $vgpr0
; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX1064-NEXT: s_cbranch_execz BB9_2 ; GFX1064-NEXT: s_cbranch_execz .LBB9_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: v_mov_b32_e32 v0, 0 ; GFX1064-NEXT: v_mov_b32_e32 v0, 0
; GFX1064-NEXT: v_mov_b32_e32 v4, s7 ; GFX1064-NEXT: v_mov_b32_e32 v4, s7
; GFX1064-NEXT: s_mov_b32 s3, s7 ; GFX1064-NEXT: s_mov_b32 s3, s7
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: ds_sub_rtn_u32 v0, v0, v4 ; GFX1064-NEXT: ds_sub_rtn_u32 v0, v0, v4
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: BB9_2: ; GFX1064-NEXT: .LBB9_2:
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX1064-NEXT: v_readfirstlane_b32 s3, v0 ; GFX1064-NEXT: v_readfirstlane_b32 s3, v0
; GFX1064-NEXT: v_mov_b32_e32 v0, v3 ; GFX1064-NEXT: v_mov_b32_e32 v0, v3
; GFX1064-NEXT: v_sub_nc_u32_e32 v0, s3, v0 ; GFX1064-NEXT: v_sub_nc_u32_e32 v0, s3, v0
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0
Show All 24 Lines
; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1032-NEXT: s_or_saveexec_b32 s2, -1 ; GFX1032-NEXT: s_or_saveexec_b32 s2, -1
; GFX1032-NEXT: v_writelane_b32 v3, s3, 16 ; GFX1032-NEXT: v_writelane_b32 v3, s3, 16
; GFX1032-NEXT: s_mov_b32 exec_lo, s2 ; GFX1032-NEXT: s_mov_b32 exec_lo, s2
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: s_mov_b32 s2, -1 ; GFX1032-NEXT: s_mov_b32 s2, -1
; GFX1032-NEXT: ; implicit-def: $vgpr0 ; GFX1032-NEXT: ; implicit-def: $vgpr0
; GFX1032-NEXT: s_and_saveexec_b32 s3, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s3, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB9_2 ; GFX1032-NEXT: s_cbranch_execz .LBB9_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: v_mov_b32_e32 v0, 0 ; GFX1032-NEXT: v_mov_b32_e32 v0, 0
; GFX1032-NEXT: v_mov_b32_e32 v4, s4 ; GFX1032-NEXT: v_mov_b32_e32 v4, s4
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: ds_sub_rtn_u32 v0, v0, v4 ; GFX1032-NEXT: ds_sub_rtn_u32 v0, v0, v4
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: BB9_2: ; GFX1032-NEXT: .LBB9_2:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s3 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s3
; GFX1032-NEXT: v_readfirstlane_b32 s3, v0 ; GFX1032-NEXT: v_readfirstlane_b32 s3, v0
; GFX1032-NEXT: v_mov_b32_e32 v0, v3 ; GFX1032-NEXT: v_mov_b32_e32 v0, v3
; GFX1032-NEXT: v_sub_nc_u32_e32 v0, s3, v0 ; GFX1032-NEXT: v_sub_nc_u32_e32 v0, s3, v0
; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s3, 0x31016000
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0
Show All 35 Lines
; GFX8-NEXT: v_add_u32_dpp v1, vcc, v1, v1 row_bcast:15 row_mask:0xa bank_mask:0xf ; GFX8-NEXT: v_add_u32_dpp v1, vcc, v1, v1 row_bcast:15 row_mask:0xa bank_mask:0xf
; GFX8-NEXT: s_nop 1 ; GFX8-NEXT: s_nop 1
; GFX8-NEXT: v_add_u32_dpp v1, vcc, v1, v1 row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX8-NEXT: v_add_u32_dpp v1, vcc, v1, v1 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX8-NEXT: v_readlane_b32 s2, v1, 63 ; GFX8-NEXT: v_readlane_b32 s2, v1, 63
; GFX8-NEXT: s_mov_b64 exec, s[0:1] ; GFX8-NEXT: s_mov_b64 exec, s[0:1]
; GFX8-NEXT: s_mov_b32 s0, s2 ; GFX8-NEXT: s_mov_b32 s0, s2
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX8-NEXT: s_cbranch_execz BB10_2 ; GFX8-NEXT: s_cbranch_execz .LBB10_2
; GFX8-NEXT: ; %bb.1: ; GFX8-NEXT: ; %bb.1:
; GFX8-NEXT: v_mov_b32_e32 v0, 0 ; GFX8-NEXT: v_mov_b32_e32 v0, 0
; GFX8-NEXT: v_mov_b32_e32 v2, s0 ; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: s_mov_b32 m0, -1 ; GFX8-NEXT: s_mov_b32 m0, -1
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: ds_sub_u32 v0, v2 ; GFX8-NEXT: ds_sub_u32 v0, v2
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: BB10_2: ; GFX8-NEXT: .LBB10_2:
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-LABEL: sub_i32_varying_nouse: ; GFX9-LABEL: sub_i32_varying_nouse:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: v_mov_b32_e32 v1, v0 ; GFX9-NEXT: v_mov_b32_e32 v1, v0
; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX9-NEXT: s_not_b64 exec, exec ; GFX9-NEXT: s_not_b64 exec, exec
Show All 11 Lines
; GFX9-NEXT: v_add_u32_dpp v1, v1, v1 row_bcast:15 row_mask:0xa bank_mask:0xf ; GFX9-NEXT: v_add_u32_dpp v1, v1, v1 row_bcast:15 row_mask:0xa bank_mask:0xf
; GFX9-NEXT: s_nop 1 ; GFX9-NEXT: s_nop 1
; GFX9-NEXT: v_add_u32_dpp v1, v1, v1 row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX9-NEXT: v_add_u32_dpp v1, v1, v1 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9-NEXT: v_readlane_b32 s2, v1, 63 ; GFX9-NEXT: v_readlane_b32 s2, v1, 63
; GFX9-NEXT: s_mov_b64 exec, s[0:1] ; GFX9-NEXT: s_mov_b64 exec, s[0:1]
; GFX9-NEXT: s_mov_b32 s0, s2 ; GFX9-NEXT: s_mov_b32 s0, s2
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-NEXT: s_cbranch_execz BB10_2 ; GFX9-NEXT: s_cbranch_execz .LBB10_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v2, s0 ; GFX9-NEXT: v_mov_b32_e32 v2, s0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: ds_sub_u32 v0, v2 ; GFX9-NEXT: ds_sub_u32 v0, v2
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: BB10_2: ; GFX9-NEXT: .LBB10_2:
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX1064-LABEL: sub_i32_varying_nouse: ; GFX1064-LABEL: sub_i32_varying_nouse:
; GFX1064: ; %bb.0: ; %entry ; GFX1064: ; %bb.0: ; %entry
; GFX1064-NEXT: v_mov_b32_e32 v1, v0 ; GFX1064-NEXT: v_mov_b32_e32 v1, v0
; GFX1064-NEXT: s_not_b64 exec, exec ; GFX1064-NEXT: s_not_b64 exec, exec
; GFX1064-NEXT: v_mov_b32_e32 v1, 0 ; GFX1064-NEXT: v_mov_b32_e32 v1, 0
; GFX1064-NEXT: s_not_b64 exec, exec ; GFX1064-NEXT: s_not_b64 exec, exec
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; GFX1064-NEXT: s_or_saveexec_b64 s[0:1], -1 ; GFX1064-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX1064-NEXT: v_readlane_b32 s2, v1, 0 ; GFX1064-NEXT: v_readlane_b32 s2, v1, 0
; GFX1064-NEXT: v_readlane_b32 s3, v1, 32 ; GFX1064-NEXT: v_readlane_b32 s3, v1, 32
; GFX1064-NEXT: s_mov_b64 exec, s[0:1] ; GFX1064-NEXT: s_mov_b64 exec, s[0:1]
; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1064-NEXT: s_add_i32 s0, s2, s3 ; GFX1064-NEXT: s_add_i32 s0, s2, s3
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX1064-NEXT: s_cbranch_execz BB10_2 ; GFX1064-NEXT: s_cbranch_execz .LBB10_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: v_mov_b32_e32 v0, 0 ; GFX1064-NEXT: v_mov_b32_e32 v0, 0
; GFX1064-NEXT: v_mov_b32_e32 v3, s0 ; GFX1064-NEXT: v_mov_b32_e32 v3, s0
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: ds_sub_u32 v0, v3 ; GFX1064-NEXT: ds_sub_u32 v0, v3
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: BB10_2: ; GFX1064-NEXT: .LBB10_2:
; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: s_endpgm
; ;
; GFX1032-LABEL: sub_i32_varying_nouse: ; GFX1032-LABEL: sub_i32_varying_nouse:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: v_mov_b32_e32 v1, v0 ; GFX1032-NEXT: v_mov_b32_e32 v1, v0
; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo ; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo
; GFX1032-NEXT: v_mov_b32_e32 v1, 0 ; GFX1032-NEXT: v_mov_b32_e32 v1, 0
; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo ; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo
; GFX1032-NEXT: s_or_saveexec_b32 s0, -1 ; GFX1032-NEXT: s_or_saveexec_b32 s0, -1
; GFX1032-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_xmask:1 row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX1032-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_xmask:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1032-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_xmask:2 row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX1032-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_xmask:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1032-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_xmask:4 row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX1032-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_xmask:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1032-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_xmask:8 row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX1032-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_xmask:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1032-NEXT: v_mov_b32_e32 v2, v1 ; GFX1032-NEXT: v_mov_b32_e32 v2, v1
; GFX1032-NEXT: v_permlanex16_b32 v2, v2, -1, -1 ; GFX1032-NEXT: v_permlanex16_b32 v2, v2, -1, -1
; GFX1032-NEXT: v_add_nc_u32_e32 v1, v1, v2 ; GFX1032-NEXT: v_add_nc_u32_e32 v1, v1, v2
; GFX1032-NEXT: s_mov_b32 exec_lo, s0 ; GFX1032-NEXT: s_mov_b32 exec_lo, s0
; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v3, exec_lo, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v3, exec_lo, 0
; GFX1032-NEXT: v_mov_b32_e32 v0, v1 ; GFX1032-NEXT: v_mov_b32_e32 v0, v1
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v3 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v3
; GFX1032-NEXT: s_and_saveexec_b32 s0, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB10_2 ; GFX1032-NEXT: s_cbranch_execz .LBB10_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: v_mov_b32_e32 v3, 0 ; GFX1032-NEXT: v_mov_b32_e32 v3, 0
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: ds_sub_u32 v3, v0 ; GFX1032-NEXT: ds_sub_u32 v3, v0
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: BB10_2: ; GFX1032-NEXT: .LBB10_2:
; GFX1032-NEXT: s_endpgm ; GFX1032-NEXT: s_endpgm
entry: entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x() %lane = call i32 @llvm.amdgcn.workitem.id.x()
%old = atomicrmw sub i32 addrspace(3)* @local_var32, i32 %lane acq_rel %old = atomicrmw sub i32 addrspace(3)* @local_var32, i32 %lane acq_rel
ret void ret void
} }
define amdgpu_kernel void @sub_i64_constant(i64 addrspace(1)* %out) { define amdgpu_kernel void @sub_i64_constant(i64 addrspace(1)* %out) {
; ;
; ;
; GFX7LESS-LABEL: sub_i64_constant: ; GFX7LESS-LABEL: sub_i64_constant:
; GFX7LESS: ; %bb.0: ; %entry ; GFX7LESS: ; %bb.0: ; %entry
; GFX7LESS-NEXT: s_mov_b64 s[4:5], exec ; GFX7LESS-NEXT: s_mov_b64 s[4:5], exec
; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s4, 0 ; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s4, 0
; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v2, s5, v0 ; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v2, s5, v0
; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX7LESS-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX7LESS-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX7LESS-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX7LESS-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX7LESS-NEXT: s_cbranch_execz BB11_2 ; GFX7LESS-NEXT: s_cbranch_execz .LBB11_2
; GFX7LESS-NEXT: ; %bb.1: ; GFX7LESS-NEXT: ; %bb.1:
; GFX7LESS-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX7LESS-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
; GFX7LESS-NEXT: s_mul_i32 s4, s4, 5 ; GFX7LESS-NEXT: s_mul_i32 s4, s4, 5
; GFX7LESS-NEXT: v_mov_b32_e32 v1, 0 ; GFX7LESS-NEXT: v_mov_b32_e32 v1, 0
; GFX7LESS-NEXT: v_mov_b32_e32 v0, s4 ; GFX7LESS-NEXT: v_mov_b32_e32 v0, s4
; GFX7LESS-NEXT: s_mov_b32 m0, -1 ; GFX7LESS-NEXT: s_mov_b32 m0, -1
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: ds_sub_rtn_u64 v[0:1], v1, v[0:1] ; GFX7LESS-NEXT: ds_sub_rtn_u64 v[0:1], v1, v[0:1]
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: BB11_2: ; GFX7LESS-NEXT: .LBB11_2:
; GFX7LESS-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX7LESS-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: v_readfirstlane_b32 s2, v0 ; GFX7LESS-NEXT: v_readfirstlane_b32 s2, v0
; GFX7LESS-NEXT: v_readfirstlane_b32 s4, v1 ; GFX7LESS-NEXT: v_readfirstlane_b32 s4, v1
; GFX7LESS-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v2 ; GFX7LESS-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v2
; GFX7LESS-NEXT: v_mul_u32_u24_e32 v0, 5, v2 ; GFX7LESS-NEXT: v_mul_u32_u24_e32 v0, 5, v2
; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000 ; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000
; GFX7LESS-NEXT: v_mov_b32_e32 v2, s4 ; GFX7LESS-NEXT: v_mov_b32_e32 v2, s4
; GFX7LESS-NEXT: v_sub_i32_e32 v0, vcc, s2, v0 ; GFX7LESS-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
; GFX7LESS-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc ; GFX7LESS-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc
; GFX7LESS-NEXT: s_mov_b32 s2, -1 ; GFX7LESS-NEXT: s_mov_b32 s2, -1
; GFX7LESS-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX7LESS-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX7LESS-NEXT: s_endpgm ; GFX7LESS-NEXT: s_endpgm
; ;
; GFX8-LABEL: sub_i64_constant: ; GFX8-LABEL: sub_i64_constant:
; GFX8: ; %bb.0: ; %entry ; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX8-NEXT: s_mov_b64 s[4:5], exec ; GFX8-NEXT: s_mov_b64 s[4:5], exec
; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 ; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0
; GFX8-NEXT: v_mbcnt_hi_u32_b32 v2, s5, v0 ; GFX8-NEXT: v_mbcnt_hi_u32_b32 v2, s5, v0
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX8-NEXT: s_cbranch_execz BB11_2 ; GFX8-NEXT: s_cbranch_execz .LBB11_2
; GFX8-NEXT: ; %bb.1: ; GFX8-NEXT: ; %bb.1:
; GFX8-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX8-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
; GFX8-NEXT: s_mul_i32 s4, s4, 5 ; GFX8-NEXT: s_mul_i32 s4, s4, 5
; GFX8-NEXT: v_mov_b32_e32 v0, s4 ; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, 0 ; GFX8-NEXT: v_mov_b32_e32 v1, 0
; GFX8-NEXT: s_mov_b32 m0, -1 ; GFX8-NEXT: s_mov_b32 m0, -1
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: ds_sub_rtn_u64 v[0:1], v1, v[0:1] ; GFX8-NEXT: ds_sub_rtn_u64 v[0:1], v1, v[0:1]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: BB11_2: ; GFX8-NEXT: .LBB11_2:
; GFX8-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX8-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_readfirstlane_b32 s2, v0 ; GFX8-NEXT: v_readfirstlane_b32 s2, v0
; GFX8-NEXT: v_readfirstlane_b32 s3, v1 ; GFX8-NEXT: v_readfirstlane_b32 s3, v1
; GFX8-NEXT: v_mul_u32_u24_e32 v0, 5, v2 ; GFX8-NEXT: v_mul_u32_u24_e32 v0, 5, v2
; GFX8-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v2 ; GFX8-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v2
; GFX8-NEXT: v_mov_b32_e32 v2, s3 ; GFX8-NEXT: v_mov_b32_e32 v2, s3
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s2, v0 ; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s2, v0
; GFX8-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc ; GFX8-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc
; GFX8-NEXT: s_mov_b32 s3, 0xf000 ; GFX8-NEXT: s_mov_b32 s3, 0xf000
; GFX8-NEXT: s_mov_b32 s2, -1 ; GFX8-NEXT: s_mov_b32 s2, -1
; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-LABEL: sub_i64_constant: ; GFX9-LABEL: sub_i64_constant:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: s_mov_b64 s[4:5], exec ; GFX9-NEXT: s_mov_b64 s[4:5], exec
; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 ; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0
; GFX9-NEXT: v_mbcnt_hi_u32_b32 v2, s5, v0 ; GFX9-NEXT: v_mbcnt_hi_u32_b32 v2, s5, v0
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-NEXT: s_cbranch_execz BB11_2 ; GFX9-NEXT: s_cbranch_execz .LBB11_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX9-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
; GFX9-NEXT: s_mul_i32 s4, s4, 5 ; GFX9-NEXT: s_mul_i32 s4, s4, 5
; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: ds_sub_rtn_u64 v[0:1], v1, v[0:1] ; GFX9-NEXT: ds_sub_rtn_u64 v[0:1], v1, v[0:1]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: BB11_2: ; GFX9-NEXT: .LBB11_2:
; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX9-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s2, v0 ; GFX9-NEXT: v_readfirstlane_b32 s2, v0
; GFX9-NEXT: v_readfirstlane_b32 s3, v1 ; GFX9-NEXT: v_readfirstlane_b32 s3, v1
; GFX9-NEXT: v_mul_u32_u24_e32 v0, 5, v2 ; GFX9-NEXT: v_mul_u32_u24_e32 v0, 5, v2
; GFX9-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v2 ; GFX9-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v2
; GFX9-NEXT: v_mov_b32_e32 v2, s3 ; GFX9-NEXT: v_mov_b32_e32 v2, s3
; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s2, v0 ; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s2, v0
; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v2, v1, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v2, v1, vcc
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX1064-LABEL: sub_i64_constant: ; GFX1064-LABEL: sub_i64_constant:
; GFX1064: ; %bb.0: ; %entry ; GFX1064: ; %bb.0: ; %entry
; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX1064-NEXT: s_mov_b64 s[4:5], exec ; GFX1064-NEXT: s_mov_b64 s[4:5], exec
; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0
; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v2, s5, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v2, s5, v0
; GFX1064-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX1064-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX1064-NEXT: s_cbranch_execz BB11_2 ; GFX1064-NEXT: s_cbranch_execz .LBB11_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX1064-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
; GFX1064-NEXT: v_mov_b32_e32 v1, 0 ; GFX1064-NEXT: v_mov_b32_e32 v1, 0
; GFX1064-NEXT: s_mul_i32 s4, s4, 5 ; GFX1064-NEXT: s_mul_i32 s4, s4, 5
; GFX1064-NEXT: v_mov_b32_e32 v0, s4 ; GFX1064-NEXT: v_mov_b32_e32 v0, s4
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: ds_sub_rtn_u64 v[0:1], v1, v[0:1] ; GFX1064-NEXT: ds_sub_rtn_u64 v[0:1], v1, v[0:1]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: BB11_2: ; GFX1064-NEXT: .LBB11_2:
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX1064-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX1064-NEXT: v_readfirstlane_b32 s2, v0 ; GFX1064-NEXT: v_readfirstlane_b32 s2, v0
; GFX1064-NEXT: v_mul_u32_u24_e32 v0, 5, v2 ; GFX1064-NEXT: v_mul_u32_u24_e32 v0, 5, v2
; GFX1064-NEXT: v_readfirstlane_b32 s3, v1 ; GFX1064-NEXT: v_readfirstlane_b32 s3, v1
; GFX1064-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v2 ; GFX1064-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v2
; GFX1064-NEXT: v_sub_co_u32 v0, vcc, s2, v0 ; GFX1064-NEXT: v_sub_co_u32 v0, vcc, s2, v0
; GFX1064-NEXT: v_sub_co_ci_u32_e32 v1, vcc, s3, v1, vcc ; GFX1064-NEXT: v_sub_co_ci_u32_e32 v1, vcc, s3, v1, vcc
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064-NEXT: s_mov_b32 s2, -1 ; GFX1064-NEXT: s_mov_b32 s2, -1
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: s_endpgm
; ;
; GFX1032-LABEL: sub_i64_constant: ; GFX1032-LABEL: sub_i64_constant:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX1032-NEXT: s_mov_b32 s3, exec_lo ; GFX1032-NEXT: s_mov_b32 s3, exec_lo
; GFX1032-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX1032-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v2, s3, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v2, s3, 0
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX1032-NEXT: s_and_saveexec_b32 s2, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s2, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB11_2 ; GFX1032-NEXT: s_cbranch_execz .LBB11_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: s_bcnt1_i32_b32 s3, s3 ; GFX1032-NEXT: s_bcnt1_i32_b32 s3, s3
; GFX1032-NEXT: v_mov_b32_e32 v1, 0 ; GFX1032-NEXT: v_mov_b32_e32 v1, 0
; GFX1032-NEXT: s_mul_i32 s3, s3, 5 ; GFX1032-NEXT: s_mul_i32 s3, s3, 5
; GFX1032-NEXT: v_mov_b32_e32 v0, s3 ; GFX1032-NEXT: v_mov_b32_e32 v0, s3
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: ds_sub_rtn_u64 v[0:1], v1, v[0:1] ; GFX1032-NEXT: ds_sub_rtn_u64 v[0:1], v1, v[0:1]
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: BB11_2: ; GFX1032-NEXT: .LBB11_2:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX1032-NEXT: v_readfirstlane_b32 s2, v0 ; GFX1032-NEXT: v_readfirstlane_b32 s2, v0
; GFX1032-NEXT: v_mul_u32_u24_e32 v0, 5, v2 ; GFX1032-NEXT: v_mul_u32_u24_e32 v0, 5, v2
; GFX1032-NEXT: v_readfirstlane_b32 s3, v1 ; GFX1032-NEXT: v_readfirstlane_b32 s3, v1
; GFX1032-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v2 ; GFX1032-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v2
; GFX1032-NEXT: v_sub_co_u32 v0, vcc_lo, s2, v0 ; GFX1032-NEXT: v_sub_co_u32 v0, vcc_lo, s2, v0
; GFX1032-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo ; GFX1032-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
Show All 15 Lines
; GFX7LESS: ; %bb.0: ; %entry ; GFX7LESS: ; %bb.0: ; %entry
; GFX7LESS-NEXT: s_mov_b64 s[6:7], exec ; GFX7LESS-NEXT: s_mov_b64 s[6:7], exec
; GFX7LESS-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GFX7LESS-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0 ; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0
; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v2, s7, v0 ; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v2, s7, v0
; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX7LESS-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX7LESS-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX7LESS-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX7LESS-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX7LESS-NEXT: s_cbranch_execz BB12_2 ; GFX7LESS-NEXT: s_cbranch_execz .LBB12_2
; GFX7LESS-NEXT: ; %bb.1: ; GFX7LESS-NEXT: ; %bb.1:
; GFX7LESS-NEXT: s_bcnt1_i32_b64 s6, s[6:7] ; GFX7LESS-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
; GFX7LESS-NEXT: v_mov_b32_e32 v3, 0 ; GFX7LESS-NEXT: v_mov_b32_e32 v3, 0
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: s_mul_i32 s7, s3, s6 ; GFX7LESS-NEXT: s_mul_i32 s7, s3, s6
; GFX7LESS-NEXT: v_mov_b32_e32 v0, s6 ; GFX7LESS-NEXT: v_mov_b32_e32 v0, s6
; GFX7LESS-NEXT: v_mul_hi_u32 v0, s2, v0 ; GFX7LESS-NEXT: v_mul_hi_u32 v0, s2, v0
; GFX7LESS-NEXT: s_mul_i32 s6, s2, s6 ; GFX7LESS-NEXT: s_mul_i32 s6, s2, s6
; GFX7LESS-NEXT: v_add_i32_e32 v1, vcc, s7, v0 ; GFX7LESS-NEXT: v_add_i32_e32 v1, vcc, s7, v0
; GFX7LESS-NEXT: v_mov_b32_e32 v0, s6 ; GFX7LESS-NEXT: v_mov_b32_e32 v0, s6
; GFX7LESS-NEXT: s_mov_b32 m0, -1 ; GFX7LESS-NEXT: s_mov_b32 m0, -1
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: ds_sub_rtn_u64 v[0:1], v3, v[0:1] ; GFX7LESS-NEXT: ds_sub_rtn_u64 v[0:1], v3, v[0:1]
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: BB12_2: ; GFX7LESS-NEXT: .LBB12_2:
; GFX7LESS-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX7LESS-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX7LESS-NEXT: s_mov_b32 s7, 0xf000 ; GFX7LESS-NEXT: s_mov_b32 s7, 0xf000
; GFX7LESS-NEXT: s_mov_b32 s6, -1 ; GFX7LESS-NEXT: s_mov_b32 s6, -1
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: s_mov_b32 s4, s0 ; GFX7LESS-NEXT: s_mov_b32 s4, s0
; GFX7LESS-NEXT: s_mov_b32 s5, s1 ; GFX7LESS-NEXT: s_mov_b32 s5, s1
; GFX7LESS-NEXT: v_readfirstlane_b32 s0, v0 ; GFX7LESS-NEXT: v_readfirstlane_b32 s0, v0
; GFX7LESS-NEXT: v_readfirstlane_b32 s1, v1 ; GFX7LESS-NEXT: v_readfirstlane_b32 s1, v1
Show All 11 Lines
; GFX8: ; %bb.0: ; %entry ; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX8-NEXT: s_mov_b64 s[6:7], exec ; GFX8-NEXT: s_mov_b64 s[6:7], exec
; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0 ; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
; GFX8-NEXT: v_mbcnt_hi_u32_b32 v2, s7, v0 ; GFX8-NEXT: v_mbcnt_hi_u32_b32 v2, s7, v0
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX8-NEXT: s_cbranch_execz BB12_2 ; GFX8-NEXT: s_cbranch_execz .LBB12_2
; GFX8-NEXT: ; %bb.1: ; GFX8-NEXT: ; %bb.1:
; GFX8-NEXT: s_bcnt1_i32_b64 s6, s[6:7] ; GFX8-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
; GFX8-NEXT: v_mov_b32_e32 v0, s6 ; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mul_hi_u32 v0, s2, v0 ; GFX8-NEXT: v_mul_hi_u32 v0, s2, v0
; GFX8-NEXT: s_mul_i32 s7, s3, s6 ; GFX8-NEXT: s_mul_i32 s7, s3, s6
; GFX8-NEXT: s_mul_i32 s6, s2, s6 ; GFX8-NEXT: s_mul_i32 s6, s2, s6
; GFX8-NEXT: v_mov_b32_e32 v3, 0 ; GFX8-NEXT: v_mov_b32_e32 v3, 0
; GFX8-NEXT: v_add_u32_e32 v1, vcc, s7, v0 ; GFX8-NEXT: v_add_u32_e32 v1, vcc, s7, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s6 ; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: s_mov_b32 m0, -1 ; GFX8-NEXT: s_mov_b32 m0, -1
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: ds_sub_rtn_u64 v[0:1], v3, v[0:1] ; GFX8-NEXT: ds_sub_rtn_u64 v[0:1], v3, v[0:1]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: BB12_2: ; GFX8-NEXT: .LBB12_2:
; GFX8-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_mov_b32 s4, s0 ; GFX8-NEXT: s_mov_b32 s4, s0
; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: v_mul_lo_u32 v0, s3, v2 ; GFX8-NEXT: v_mul_lo_u32 v0, s3, v2
; GFX8-NEXT: v_mul_hi_u32 v3, s2, v2 ; GFX8-NEXT: v_mul_hi_u32 v3, s2, v2
; GFX8-NEXT: s_mov_b32 s5, s1 ; GFX8-NEXT: s_mov_b32 s5, s1
; GFX8-NEXT: v_readfirstlane_b32 s1, v1 ; GFX8-NEXT: v_readfirstlane_b32 s1, v1
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; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: s_mov_b64 s[6:7], exec ; GFX9-NEXT: s_mov_b64 s[6:7], exec
; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0 ; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
; GFX9-NEXT: v_mbcnt_hi_u32_b32 v2, s7, v0 ; GFX9-NEXT: v_mbcnt_hi_u32_b32 v2, s7, v0
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_cbranch_execz BB12_2 ; GFX9-NEXT: s_cbranch_execz .LBB12_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: s_bcnt1_i32_b64 s6, s[6:7] ; GFX9-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mul_i32 s7, s3, s6 ; GFX9-NEXT: s_mul_i32 s7, s3, s6
; GFX9-NEXT: s_mul_hi_u32 s8, s2, s6 ; GFX9-NEXT: s_mul_hi_u32 s8, s2, s6
; GFX9-NEXT: s_add_i32 s8, s8, s7 ; GFX9-NEXT: s_add_i32 s8, s8, s7
; GFX9-NEXT: s_mul_i32 s6, s2, s6 ; GFX9-NEXT: s_mul_i32 s6, s2, s6
; GFX9-NEXT: v_mov_b32_e32 v0, s6 ; GFX9-NEXT: v_mov_b32_e32 v0, s6
; GFX9-NEXT: v_mov_b32_e32 v1, s8 ; GFX9-NEXT: v_mov_b32_e32 v1, s8
; GFX9-NEXT: v_mov_b32_e32 v3, 0 ; GFX9-NEXT: v_mov_b32_e32 v3, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: ds_sub_rtn_u64 v[0:1], v3, v[0:1] ; GFX9-NEXT: ds_sub_rtn_u64 v[0:1], v3, v[0:1]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: BB12_2: ; GFX9-NEXT: .LBB12_2:
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, s0 ; GFX9-NEXT: s_mov_b32 s4, s0
; GFX9-NEXT: v_mul_lo_u32 v3, s3, v2 ; GFX9-NEXT: v_mul_lo_u32 v3, s3, v2
; GFX9-NEXT: v_mul_hi_u32 v4, s2, v2 ; GFX9-NEXT: v_mul_hi_u32 v4, s2, v2
; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: v_mul_lo_u32 v0, s2, v2 ; GFX9-NEXT: v_mul_lo_u32 v0, s2, v2
; GFX9-NEXT: s_mov_b32 s5, s1 ; GFX9-NEXT: s_mov_b32 s5, s1
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; GFX1064: ; %bb.0: ; %entry ; GFX1064: ; %bb.0: ; %entry
; GFX1064-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX1064-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX1064-NEXT: s_mov_b64 s[6:7], exec ; GFX1064-NEXT: s_mov_b64 s[6:7], exec
; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v2, s7, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v2, s7, v0
; GFX1064-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX1064-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX1064-NEXT: s_cbranch_execz BB12_2 ; GFX1064-NEXT: s_cbranch_execz .LBB12_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: s_bcnt1_i32_b64 s6, s[6:7] ; GFX1064-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
; GFX1064-NEXT: v_mov_b32_e32 v3, 0 ; GFX1064-NEXT: v_mov_b32_e32 v3, 0
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: s_mul_i32 s7, s3, s6 ; GFX1064-NEXT: s_mul_i32 s7, s3, s6
; GFX1064-NEXT: s_mul_hi_u32 s8, s2, s6 ; GFX1064-NEXT: s_mul_hi_u32 s8, s2, s6
; GFX1064-NEXT: s_mul_i32 s6, s2, s6 ; GFX1064-NEXT: s_mul_i32 s6, s2, s6
; GFX1064-NEXT: s_add_i32 s8, s8, s7 ; GFX1064-NEXT: s_add_i32 s8, s8, s7
; GFX1064-NEXT: v_mov_b32_e32 v0, s6 ; GFX1064-NEXT: v_mov_b32_e32 v0, s6
; GFX1064-NEXT: v_mov_b32_e32 v1, s8 ; GFX1064-NEXT: v_mov_b32_e32 v1, s8
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: ds_sub_rtn_u64 v[0:1], v3, v[0:1] ; GFX1064-NEXT: ds_sub_rtn_u64 v[0:1], v3, v[0:1]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: BB12_2: ; GFX1064-NEXT: .LBB12_2:
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: v_mul_lo_u32 v3, s3, v2 ; GFX1064-NEXT: v_mul_lo_u32 v3, s3, v2
; GFX1064-NEXT: v_mul_hi_u32 v4, s2, v2 ; GFX1064-NEXT: v_mul_hi_u32 v4, s2, v2
; GFX1064-NEXT: v_mul_lo_u32 v2, s2, v2 ; GFX1064-NEXT: v_mul_lo_u32 v2, s2, v2
; GFX1064-NEXT: v_readfirstlane_b32 s2, v0 ; GFX1064-NEXT: v_readfirstlane_b32 s2, v0
; GFX1064-NEXT: v_readfirstlane_b32 s4, v1 ; GFX1064-NEXT: v_readfirstlane_b32 s4, v1
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064-NEXT: v_add_nc_u32_e32 v1, v4, v3 ; GFX1064-NEXT: v_add_nc_u32_e32 v1, v4, v3
; GFX1064-NEXT: v_sub_co_u32 v0, vcc, s2, v2 ; GFX1064-NEXT: v_sub_co_u32 v0, vcc, s2, v2
; GFX1064-NEXT: s_mov_b32 s2, -1 ; GFX1064-NEXT: s_mov_b32 s2, -1
; GFX1064-NEXT: v_sub_co_ci_u32_e32 v1, vcc, s4, v1, vcc ; GFX1064-NEXT: v_sub_co_ci_u32_e32 v1, vcc, s4, v1, vcc
; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: s_endpgm
; ;
; GFX1032-LABEL: sub_i64_uniform: ; GFX1032-LABEL: sub_i64_uniform:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX1032-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX1032-NEXT: s_mov_b32 s5, exec_lo ; GFX1032-NEXT: s_mov_b32 s5, exec_lo
; GFX1032-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX1032-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v2, s5, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v2, s5, 0
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX1032-NEXT: s_and_saveexec_b32 s4, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s4, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB12_2 ; GFX1032-NEXT: s_cbranch_execz .LBB12_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: s_bcnt1_i32_b32 s5, s5 ; GFX1032-NEXT: s_bcnt1_i32_b32 s5, s5
; GFX1032-NEXT: v_mov_b32_e32 v3, 0 ; GFX1032-NEXT: v_mov_b32_e32 v3, 0
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: s_mul_i32 s6, s3, s5 ; GFX1032-NEXT: s_mul_i32 s6, s3, s5
; GFX1032-NEXT: s_mul_hi_u32 s7, s2, s5 ; GFX1032-NEXT: s_mul_hi_u32 s7, s2, s5
; GFX1032-NEXT: s_mul_i32 s5, s2, s5 ; GFX1032-NEXT: s_mul_i32 s5, s2, s5
; GFX1032-NEXT: s_add_i32 s7, s7, s6 ; GFX1032-NEXT: s_add_i32 s7, s7, s6
; GFX1032-NEXT: v_mov_b32_e32 v0, s5 ; GFX1032-NEXT: v_mov_b32_e32 v0, s5
; GFX1032-NEXT: v_mov_b32_e32 v1, s7 ; GFX1032-NEXT: v_mov_b32_e32 v1, s7
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: ds_sub_rtn_u64 v[0:1], v3, v[0:1] ; GFX1032-NEXT: ds_sub_rtn_u64 v[0:1], v3, v[0:1]
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: BB12_2: ; GFX1032-NEXT: .LBB12_2:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: v_mul_lo_u32 v3, s3, v2 ; GFX1032-NEXT: v_mul_lo_u32 v3, s3, v2
; GFX1032-NEXT: v_mul_hi_u32 v4, s2, v2 ; GFX1032-NEXT: v_mul_hi_u32 v4, s2, v2
; GFX1032-NEXT: v_mul_lo_u32 v2, s2, v2 ; GFX1032-NEXT: v_mul_lo_u32 v2, s2, v2
; GFX1032-NEXT: v_readfirstlane_b32 s2, v0 ; GFX1032-NEXT: v_readfirstlane_b32 s2, v0
; GFX1032-NEXT: v_readfirstlane_b32 s4, v1 ; GFX1032-NEXT: v_readfirstlane_b32 s4, v1
▲ Show 20 Lines • Show All 114 Lines • ▼ Show 20 Lines
; GFX8-NEXT: v_and_b32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX8-NEXT: v_and_b32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX8-NEXT: v_readlane_b32 s4, v2, 63 ; GFX8-NEXT: v_readlane_b32 s4, v2, 63
; GFX8-NEXT: s_nop 0 ; GFX8-NEXT: s_nop 0
; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf ; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX8-NEXT: s_mov_b64 exec, s[2:3] ; GFX8-NEXT: s_mov_b64 exec, s[2:3]
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX8-NEXT: ; implicit-def: $vgpr0 ; GFX8-NEXT: ; implicit-def: $vgpr0
; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX8-NEXT: s_cbranch_execz BB14_2 ; GFX8-NEXT: s_cbranch_execz .LBB14_2
; GFX8-NEXT: ; %bb.1: ; GFX8-NEXT: ; %bb.1:
; GFX8-NEXT: v_mov_b32_e32 v0, 0 ; GFX8-NEXT: v_mov_b32_e32 v0, 0
; GFX8-NEXT: v_mov_b32_e32 v3, s4 ; GFX8-NEXT: v_mov_b32_e32 v3, s4
; GFX8-NEXT: s_mov_b32 m0, -1 ; GFX8-NEXT: s_mov_b32 m0, -1
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: ds_and_rtn_b32 v0, v0, v3 ; GFX8-NEXT: ds_and_rtn_b32 v0, v0, v3
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: BB14_2: ; GFX8-NEXT: .LBB14_2:
; GFX8-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX8-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_readfirstlane_b32 s2, v0 ; GFX8-NEXT: v_readfirstlane_b32 s2, v0
; GFX8-NEXT: v_mov_b32_e32 v0, v1 ; GFX8-NEXT: v_mov_b32_e32 v0, v1
; GFX8-NEXT: v_and_b32_e32 v0, s2, v0 ; GFX8-NEXT: v_and_b32_e32 v0, s2, v0
; GFX8-NEXT: s_mov_b32 s3, 0xf000 ; GFX8-NEXT: s_mov_b32 s3, 0xf000
; GFX8-NEXT: s_mov_b32 s2, -1 ; GFX8-NEXT: s_mov_b32 s2, -1
; GFX8-NEXT: s_nop 0 ; GFX8-NEXT: s_nop 0
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; GFX9-NEXT: v_and_b32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX9-NEXT: v_and_b32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9-NEXT: v_readlane_b32 s4, v2, 63 ; GFX9-NEXT: v_readlane_b32 s4, v2, 63
; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: s_nop 0
; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf ; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX9-NEXT: s_mov_b64 exec, s[2:3] ; GFX9-NEXT: s_mov_b64 exec, s[2:3]
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-NEXT: ; implicit-def: $vgpr0 ; GFX9-NEXT: ; implicit-def: $vgpr0
; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-NEXT: s_cbranch_execz BB14_2 ; GFX9-NEXT: s_cbranch_execz .LBB14_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v3, s4 ; GFX9-NEXT: v_mov_b32_e32 v3, s4
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: ds_and_rtn_b32 v0, v0, v3 ; GFX9-NEXT: ds_and_rtn_b32 v0, v0, v3
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: BB14_2: ; GFX9-NEXT: .LBB14_2:
; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX9-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s2, v0 ; GFX9-NEXT: v_readfirstlane_b32 s2, v0
; GFX9-NEXT: v_mov_b32_e32 v0, v1 ; GFX9-NEXT: v_mov_b32_e32 v0, v1
; GFX9-NEXT: v_and_b32_e32 v0, s2, v0 ; GFX9-NEXT: v_and_b32_e32 v0, s2, v0
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: s_nop 0
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; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1064-NEXT: s_or_saveexec_b64 s[4:5], -1 ; GFX1064-NEXT: s_or_saveexec_b64 s[4:5], -1
; GFX1064-NEXT: v_writelane_b32 v3, s6, 48 ; GFX1064-NEXT: v_writelane_b32 v3, s6, 48
; GFX1064-NEXT: s_mov_b64 exec, s[4:5] ; GFX1064-NEXT: s_mov_b64 exec, s[4:5]
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: s_mov_b32 s2, -1 ; GFX1064-NEXT: s_mov_b32 s2, -1
; GFX1064-NEXT: ; implicit-def: $vgpr0 ; GFX1064-NEXT: ; implicit-def: $vgpr0
; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX1064-NEXT: s_cbranch_execz BB14_2 ; GFX1064-NEXT: s_cbranch_execz .LBB14_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: v_mov_b32_e32 v0, 0 ; GFX1064-NEXT: v_mov_b32_e32 v0, 0
; GFX1064-NEXT: v_mov_b32_e32 v4, s7 ; GFX1064-NEXT: v_mov_b32_e32 v4, s7
; GFX1064-NEXT: s_mov_b32 s3, s7 ; GFX1064-NEXT: s_mov_b32 s3, s7
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: ds_and_rtn_b32 v0, v0, v4 ; GFX1064-NEXT: ds_and_rtn_b32 v0, v0, v4
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: BB14_2: ; GFX1064-NEXT: .LBB14_2:
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX1064-NEXT: v_readfirstlane_b32 s3, v0 ; GFX1064-NEXT: v_readfirstlane_b32 s3, v0
; GFX1064-NEXT: v_mov_b32_e32 v0, v3 ; GFX1064-NEXT: v_mov_b32_e32 v0, v3
; GFX1064-NEXT: v_and_b32_e32 v0, s3, v0 ; GFX1064-NEXT: v_and_b32_e32 v0, s3, v0
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0
Show All 24 Lines
; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1032-NEXT: s_or_saveexec_b32 s2, -1 ; GFX1032-NEXT: s_or_saveexec_b32 s2, -1
; GFX1032-NEXT: v_writelane_b32 v3, s3, 16 ; GFX1032-NEXT: v_writelane_b32 v3, s3, 16
; GFX1032-NEXT: s_mov_b32 exec_lo, s2 ; GFX1032-NEXT: s_mov_b32 exec_lo, s2
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: s_mov_b32 s2, -1 ; GFX1032-NEXT: s_mov_b32 s2, -1
; GFX1032-NEXT: ; implicit-def: $vgpr0 ; GFX1032-NEXT: ; implicit-def: $vgpr0
; GFX1032-NEXT: s_and_saveexec_b32 s3, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s3, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB14_2 ; GFX1032-NEXT: s_cbranch_execz .LBB14_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: v_mov_b32_e32 v0, 0 ; GFX1032-NEXT: v_mov_b32_e32 v0, 0
; GFX1032-NEXT: v_mov_b32_e32 v4, s4 ; GFX1032-NEXT: v_mov_b32_e32 v4, s4
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: ds_and_rtn_b32 v0, v0, v4 ; GFX1032-NEXT: ds_and_rtn_b32 v0, v0, v4
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: BB14_2: ; GFX1032-NEXT: .LBB14_2:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s3 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s3
; GFX1032-NEXT: v_readfirstlane_b32 s3, v0 ; GFX1032-NEXT: v_readfirstlane_b32 s3, v0
; GFX1032-NEXT: v_mov_b32_e32 v0, v3 ; GFX1032-NEXT: v_mov_b32_e32 v0, v3
; GFX1032-NEXT: v_and_b32_e32 v0, s3, v0 ; GFX1032-NEXT: v_and_b32_e32 v0, s3, v0
; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s3, 0x31016000
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; GFX8-NEXT: v_or_b32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX8-NEXT: v_or_b32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX8-NEXT: v_readlane_b32 s4, v2, 63 ; GFX8-NEXT: v_readlane_b32 s4, v2, 63
; GFX8-NEXT: s_nop 0 ; GFX8-NEXT: s_nop 0
; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf ; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX8-NEXT: s_mov_b64 exec, s[2:3] ; GFX8-NEXT: s_mov_b64 exec, s[2:3]
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX8-NEXT: ; implicit-def: $vgpr0 ; GFX8-NEXT: ; implicit-def: $vgpr0
; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX8-NEXT: s_cbranch_execz BB15_2 ; GFX8-NEXT: s_cbranch_execz .LBB15_2
; GFX8-NEXT: ; %bb.1: ; GFX8-NEXT: ; %bb.1:
; GFX8-NEXT: v_mov_b32_e32 v0, 0 ; GFX8-NEXT: v_mov_b32_e32 v0, 0
; GFX8-NEXT: v_mov_b32_e32 v3, s4 ; GFX8-NEXT: v_mov_b32_e32 v3, s4
; GFX8-NEXT: s_mov_b32 m0, -1 ; GFX8-NEXT: s_mov_b32 m0, -1
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: ds_or_rtn_b32 v0, v0, v3 ; GFX8-NEXT: ds_or_rtn_b32 v0, v0, v3
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: BB15_2: ; GFX8-NEXT: .LBB15_2:
; GFX8-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX8-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_readfirstlane_b32 s2, v0 ; GFX8-NEXT: v_readfirstlane_b32 s2, v0
; GFX8-NEXT: v_mov_b32_e32 v0, v1 ; GFX8-NEXT: v_mov_b32_e32 v0, v1
; GFX8-NEXT: v_or_b32_e32 v0, s2, v0 ; GFX8-NEXT: v_or_b32_e32 v0, s2, v0
; GFX8-NEXT: s_mov_b32 s3, 0xf000 ; GFX8-NEXT: s_mov_b32 s3, 0xf000
; GFX8-NEXT: s_mov_b32 s2, -1 ; GFX8-NEXT: s_mov_b32 s2, -1
; GFX8-NEXT: s_nop 0 ; GFX8-NEXT: s_nop 0
Show All 26 Lines
; GFX9-NEXT: v_or_b32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX9-NEXT: v_or_b32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9-NEXT: v_readlane_b32 s4, v2, 63 ; GFX9-NEXT: v_readlane_b32 s4, v2, 63
; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: s_nop 0
; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf ; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX9-NEXT: s_mov_b64 exec, s[2:3] ; GFX9-NEXT: s_mov_b64 exec, s[2:3]
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-NEXT: ; implicit-def: $vgpr0 ; GFX9-NEXT: ; implicit-def: $vgpr0
; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-NEXT: s_cbranch_execz BB15_2 ; GFX9-NEXT: s_cbranch_execz .LBB15_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v3, s4 ; GFX9-NEXT: v_mov_b32_e32 v3, s4
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: ds_or_rtn_b32 v0, v0, v3 ; GFX9-NEXT: ds_or_rtn_b32 v0, v0, v3
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: BB15_2: ; GFX9-NEXT: .LBB15_2:
; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX9-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s2, v0 ; GFX9-NEXT: v_readfirstlane_b32 s2, v0
; GFX9-NEXT: v_mov_b32_e32 v0, v1 ; GFX9-NEXT: v_mov_b32_e32 v0, v1
; GFX9-NEXT: v_or_b32_e32 v0, s2, v0 ; GFX9-NEXT: v_or_b32_e32 v0, s2, v0
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: s_nop 0
Show All 35 Lines
; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1064-NEXT: s_or_saveexec_b64 s[4:5], -1 ; GFX1064-NEXT: s_or_saveexec_b64 s[4:5], -1
; GFX1064-NEXT: v_writelane_b32 v3, s6, 48 ; GFX1064-NEXT: v_writelane_b32 v3, s6, 48
; GFX1064-NEXT: s_mov_b64 exec, s[4:5] ; GFX1064-NEXT: s_mov_b64 exec, s[4:5]
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: s_mov_b32 s2, -1 ; GFX1064-NEXT: s_mov_b32 s2, -1
; GFX1064-NEXT: ; implicit-def: $vgpr0 ; GFX1064-NEXT: ; implicit-def: $vgpr0
; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX1064-NEXT: s_cbranch_execz BB15_2 ; GFX1064-NEXT: s_cbranch_execz .LBB15_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: v_mov_b32_e32 v0, 0 ; GFX1064-NEXT: v_mov_b32_e32 v0, 0
; GFX1064-NEXT: v_mov_b32_e32 v4, s7 ; GFX1064-NEXT: v_mov_b32_e32 v4, s7
; GFX1064-NEXT: s_mov_b32 s3, s7 ; GFX1064-NEXT: s_mov_b32 s3, s7
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: ds_or_rtn_b32 v0, v0, v4 ; GFX1064-NEXT: ds_or_rtn_b32 v0, v0, v4
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: BB15_2: ; GFX1064-NEXT: .LBB15_2:
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX1064-NEXT: v_readfirstlane_b32 s3, v0 ; GFX1064-NEXT: v_readfirstlane_b32 s3, v0
; GFX1064-NEXT: v_mov_b32_e32 v0, v3 ; GFX1064-NEXT: v_mov_b32_e32 v0, v3
; GFX1064-NEXT: v_or_b32_e32 v0, s3, v0 ; GFX1064-NEXT: v_or_b32_e32 v0, s3, v0
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0
Show All 24 Lines
; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1032-NEXT: s_or_saveexec_b32 s2, -1 ; GFX1032-NEXT: s_or_saveexec_b32 s2, -1
; GFX1032-NEXT: v_writelane_b32 v3, s3, 16 ; GFX1032-NEXT: v_writelane_b32 v3, s3, 16
; GFX1032-NEXT: s_mov_b32 exec_lo, s2 ; GFX1032-NEXT: s_mov_b32 exec_lo, s2
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: s_mov_b32 s2, -1 ; GFX1032-NEXT: s_mov_b32 s2, -1
; GFX1032-NEXT: ; implicit-def: $vgpr0 ; GFX1032-NEXT: ; implicit-def: $vgpr0
; GFX1032-NEXT: s_and_saveexec_b32 s3, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s3, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB15_2 ; GFX1032-NEXT: s_cbranch_execz .LBB15_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: v_mov_b32_e32 v0, 0 ; GFX1032-NEXT: v_mov_b32_e32 v0, 0
; GFX1032-NEXT: v_mov_b32_e32 v4, s4 ; GFX1032-NEXT: v_mov_b32_e32 v4, s4
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: ds_or_rtn_b32 v0, v0, v4 ; GFX1032-NEXT: ds_or_rtn_b32 v0, v0, v4
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: BB15_2: ; GFX1032-NEXT: .LBB15_2:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s3 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s3
; GFX1032-NEXT: v_readfirstlane_b32 s3, v0 ; GFX1032-NEXT: v_readfirstlane_b32 s3, v0
; GFX1032-NEXT: v_mov_b32_e32 v0, v3 ; GFX1032-NEXT: v_mov_b32_e32 v0, v3
; GFX1032-NEXT: v_or_b32_e32 v0, s3, v0 ; GFX1032-NEXT: v_or_b32_e32 v0, s3, v0
; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s3, 0x31016000
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; GFX8-NEXT: v_xor_b32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX8-NEXT: v_xor_b32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX8-NEXT: v_readlane_b32 s4, v2, 63 ; GFX8-NEXT: v_readlane_b32 s4, v2, 63
; GFX8-NEXT: s_nop 0 ; GFX8-NEXT: s_nop 0
; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf ; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX8-NEXT: s_mov_b64 exec, s[2:3] ; GFX8-NEXT: s_mov_b64 exec, s[2:3]
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX8-NEXT: ; implicit-def: $vgpr0 ; GFX8-NEXT: ; implicit-def: $vgpr0
; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX8-NEXT: s_cbranch_execz BB16_2 ; GFX8-NEXT: s_cbranch_execz .LBB16_2
; GFX8-NEXT: ; %bb.1: ; GFX8-NEXT: ; %bb.1:
; GFX8-NEXT: v_mov_b32_e32 v0, 0 ; GFX8-NEXT: v_mov_b32_e32 v0, 0
; GFX8-NEXT: v_mov_b32_e32 v3, s4 ; GFX8-NEXT: v_mov_b32_e32 v3, s4
; GFX8-NEXT: s_mov_b32 m0, -1 ; GFX8-NEXT: s_mov_b32 m0, -1
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: ds_xor_rtn_b32 v0, v0, v3 ; GFX8-NEXT: ds_xor_rtn_b32 v0, v0, v3
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: BB16_2: ; GFX8-NEXT: .LBB16_2:
; GFX8-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX8-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_readfirstlane_b32 s2, v0 ; GFX8-NEXT: v_readfirstlane_b32 s2, v0
; GFX8-NEXT: v_mov_b32_e32 v0, v1 ; GFX8-NEXT: v_mov_b32_e32 v0, v1
; GFX8-NEXT: v_xor_b32_e32 v0, s2, v0 ; GFX8-NEXT: v_xor_b32_e32 v0, s2, v0
; GFX8-NEXT: s_mov_b32 s3, 0xf000 ; GFX8-NEXT: s_mov_b32 s3, 0xf000
; GFX8-NEXT: s_mov_b32 s2, -1 ; GFX8-NEXT: s_mov_b32 s2, -1
; GFX8-NEXT: s_nop 0 ; GFX8-NEXT: s_nop 0
Show All 26 Lines
; GFX9-NEXT: v_xor_b32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX9-NEXT: v_xor_b32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9-NEXT: v_readlane_b32 s4, v2, 63 ; GFX9-NEXT: v_readlane_b32 s4, v2, 63
; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: s_nop 0
; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf ; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX9-NEXT: s_mov_b64 exec, s[2:3] ; GFX9-NEXT: s_mov_b64 exec, s[2:3]
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-NEXT: ; implicit-def: $vgpr0 ; GFX9-NEXT: ; implicit-def: $vgpr0
; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-NEXT: s_cbranch_execz BB16_2 ; GFX9-NEXT: s_cbranch_execz .LBB16_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v3, s4 ; GFX9-NEXT: v_mov_b32_e32 v3, s4
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: ds_xor_rtn_b32 v0, v0, v3 ; GFX9-NEXT: ds_xor_rtn_b32 v0, v0, v3
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: BB16_2: ; GFX9-NEXT: .LBB16_2:
; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX9-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s2, v0 ; GFX9-NEXT: v_readfirstlane_b32 s2, v0
; GFX9-NEXT: v_mov_b32_e32 v0, v1 ; GFX9-NEXT: v_mov_b32_e32 v0, v1
; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0 ; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: s_nop 0
Show All 35 Lines
; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1064-NEXT: s_or_saveexec_b64 s[4:5], -1 ; GFX1064-NEXT: s_or_saveexec_b64 s[4:5], -1
; GFX1064-NEXT: v_writelane_b32 v3, s6, 48 ; GFX1064-NEXT: v_writelane_b32 v3, s6, 48
; GFX1064-NEXT: s_mov_b64 exec, s[4:5] ; GFX1064-NEXT: s_mov_b64 exec, s[4:5]
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: s_mov_b32 s2, -1 ; GFX1064-NEXT: s_mov_b32 s2, -1
; GFX1064-NEXT: ; implicit-def: $vgpr0 ; GFX1064-NEXT: ; implicit-def: $vgpr0
; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX1064-NEXT: s_cbranch_execz BB16_2 ; GFX1064-NEXT: s_cbranch_execz .LBB16_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: v_mov_b32_e32 v0, 0 ; GFX1064-NEXT: v_mov_b32_e32 v0, 0
; GFX1064-NEXT: v_mov_b32_e32 v4, s7 ; GFX1064-NEXT: v_mov_b32_e32 v4, s7
; GFX1064-NEXT: s_mov_b32 s3, s7 ; GFX1064-NEXT: s_mov_b32 s3, s7
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: ds_xor_rtn_b32 v0, v0, v4 ; GFX1064-NEXT: ds_xor_rtn_b32 v0, v0, v4
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: BB16_2: ; GFX1064-NEXT: .LBB16_2:
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX1064-NEXT: v_readfirstlane_b32 s3, v0 ; GFX1064-NEXT: v_readfirstlane_b32 s3, v0
; GFX1064-NEXT: v_mov_b32_e32 v0, v3 ; GFX1064-NEXT: v_mov_b32_e32 v0, v3
; GFX1064-NEXT: v_xor_b32_e32 v0, s3, v0 ; GFX1064-NEXT: v_xor_b32_e32 v0, s3, v0
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0
Show All 24 Lines
; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1032-NEXT: s_or_saveexec_b32 s2, -1 ; GFX1032-NEXT: s_or_saveexec_b32 s2, -1
; GFX1032-NEXT: v_writelane_b32 v3, s3, 16 ; GFX1032-NEXT: v_writelane_b32 v3, s3, 16
; GFX1032-NEXT: s_mov_b32 exec_lo, s2 ; GFX1032-NEXT: s_mov_b32 exec_lo, s2
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: s_mov_b32 s2, -1 ; GFX1032-NEXT: s_mov_b32 s2, -1
; GFX1032-NEXT: ; implicit-def: $vgpr0 ; GFX1032-NEXT: ; implicit-def: $vgpr0
; GFX1032-NEXT: s_and_saveexec_b32 s3, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s3, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB16_2 ; GFX1032-NEXT: s_cbranch_execz .LBB16_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: v_mov_b32_e32 v0, 0 ; GFX1032-NEXT: v_mov_b32_e32 v0, 0
; GFX1032-NEXT: v_mov_b32_e32 v4, s4 ; GFX1032-NEXT: v_mov_b32_e32 v4, s4
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: ds_xor_rtn_b32 v0, v0, v4 ; GFX1032-NEXT: ds_xor_rtn_b32 v0, v0, v4
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: BB16_2: ; GFX1032-NEXT: .LBB16_2:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s3 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s3
; GFX1032-NEXT: v_readfirstlane_b32 s3, v0 ; GFX1032-NEXT: v_readfirstlane_b32 s3, v0
; GFX1032-NEXT: v_mov_b32_e32 v0, v3 ; GFX1032-NEXT: v_mov_b32_e32 v0, v3
; GFX1032-NEXT: v_xor_b32_e32 v0, s3, v0 ; GFX1032-NEXT: v_xor_b32_e32 v0, s3, v0
; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s3, 0x31016000
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; GFX8-NEXT: v_max_i32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX8-NEXT: v_max_i32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX8-NEXT: v_readlane_b32 s4, v2, 63 ; GFX8-NEXT: v_readlane_b32 s4, v2, 63
; GFX8-NEXT: s_nop 0 ; GFX8-NEXT: s_nop 0
; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf ; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX8-NEXT: s_mov_b64 exec, s[2:3] ; GFX8-NEXT: s_mov_b64 exec, s[2:3]
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX8-NEXT: ; implicit-def: $vgpr0 ; GFX8-NEXT: ; implicit-def: $vgpr0
; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX8-NEXT: s_cbranch_execz BB17_2 ; GFX8-NEXT: s_cbranch_execz .LBB17_2
; GFX8-NEXT: ; %bb.1: ; GFX8-NEXT: ; %bb.1:
; GFX8-NEXT: v_mov_b32_e32 v0, 0 ; GFX8-NEXT: v_mov_b32_e32 v0, 0
; GFX8-NEXT: v_mov_b32_e32 v3, s4 ; GFX8-NEXT: v_mov_b32_e32 v3, s4
; GFX8-NEXT: s_mov_b32 m0, -1 ; GFX8-NEXT: s_mov_b32 m0, -1
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: ds_max_rtn_i32 v0, v0, v3 ; GFX8-NEXT: ds_max_rtn_i32 v0, v0, v3
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: BB17_2: ; GFX8-NEXT: .LBB17_2:
; GFX8-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX8-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_readfirstlane_b32 s2, v0 ; GFX8-NEXT: v_readfirstlane_b32 s2, v0
; GFX8-NEXT: v_mov_b32_e32 v0, v1 ; GFX8-NEXT: v_mov_b32_e32 v0, v1
; GFX8-NEXT: v_max_i32_e32 v0, s2, v0 ; GFX8-NEXT: v_max_i32_e32 v0, s2, v0
; GFX8-NEXT: s_mov_b32 s3, 0xf000 ; GFX8-NEXT: s_mov_b32 s3, 0xf000
; GFX8-NEXT: s_mov_b32 s2, -1 ; GFX8-NEXT: s_mov_b32 s2, -1
; GFX8-NEXT: s_nop 0 ; GFX8-NEXT: s_nop 0
Show All 26 Lines
; GFX9-NEXT: v_max_i32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX9-NEXT: v_max_i32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9-NEXT: v_readlane_b32 s4, v2, 63 ; GFX9-NEXT: v_readlane_b32 s4, v2, 63
; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: s_nop 0
; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf ; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX9-NEXT: s_mov_b64 exec, s[2:3] ; GFX9-NEXT: s_mov_b64 exec, s[2:3]
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-NEXT: ; implicit-def: $vgpr0 ; GFX9-NEXT: ; implicit-def: $vgpr0
; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-NEXT: s_cbranch_execz BB17_2 ; GFX9-NEXT: s_cbranch_execz .LBB17_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v3, s4 ; GFX9-NEXT: v_mov_b32_e32 v3, s4
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: ds_max_rtn_i32 v0, v0, v3 ; GFX9-NEXT: ds_max_rtn_i32 v0, v0, v3
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: BB17_2: ; GFX9-NEXT: .LBB17_2:
; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX9-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s2, v0 ; GFX9-NEXT: v_readfirstlane_b32 s2, v0
; GFX9-NEXT: v_mov_b32_e32 v0, v1 ; GFX9-NEXT: v_mov_b32_e32 v0, v1
; GFX9-NEXT: v_max_i32_e32 v0, s2, v0 ; GFX9-NEXT: v_max_i32_e32 v0, s2, v0
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: s_nop 0
Show All 37 Lines
; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1064-NEXT: s_or_saveexec_b64 s[4:5], -1 ; GFX1064-NEXT: s_or_saveexec_b64 s[4:5], -1
; GFX1064-NEXT: v_writelane_b32 v1, s6, 48 ; GFX1064-NEXT: v_writelane_b32 v1, s6, 48
; GFX1064-NEXT: s_mov_b64 exec, s[4:5] ; GFX1064-NEXT: s_mov_b64 exec, s[4:5]
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: s_mov_b32 s2, -1 ; GFX1064-NEXT: s_mov_b32 s2, -1
; GFX1064-NEXT: ; implicit-def: $vgpr0 ; GFX1064-NEXT: ; implicit-def: $vgpr0
; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX1064-NEXT: s_cbranch_execz BB17_2 ; GFX1064-NEXT: s_cbranch_execz .LBB17_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: v_mov_b32_e32 v0, 0 ; GFX1064-NEXT: v_mov_b32_e32 v0, 0
; GFX1064-NEXT: v_mov_b32_e32 v4, s7 ; GFX1064-NEXT: v_mov_b32_e32 v4, s7
; GFX1064-NEXT: s_mov_b32 s3, s7 ; GFX1064-NEXT: s_mov_b32 s3, s7
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: ds_max_rtn_i32 v0, v0, v4 ; GFX1064-NEXT: ds_max_rtn_i32 v0, v0, v4
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: BB17_2: ; GFX1064-NEXT: .LBB17_2:
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX1064-NEXT: v_readfirstlane_b32 s3, v0 ; GFX1064-NEXT: v_readfirstlane_b32 s3, v0
; GFX1064-NEXT: v_mov_b32_e32 v0, v1 ; GFX1064-NEXT: v_mov_b32_e32 v0, v1
; GFX1064-NEXT: v_max_i32_e32 v0, s3, v0 ; GFX1064-NEXT: v_max_i32_e32 v0, s3, v0
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0
Show All 26 Lines
; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1032-NEXT: s_or_saveexec_b32 s2, -1 ; GFX1032-NEXT: s_or_saveexec_b32 s2, -1
; GFX1032-NEXT: v_writelane_b32 v1, s3, 16 ; GFX1032-NEXT: v_writelane_b32 v1, s3, 16
; GFX1032-NEXT: s_mov_b32 exec_lo, s2 ; GFX1032-NEXT: s_mov_b32 exec_lo, s2
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: s_mov_b32 s2, -1 ; GFX1032-NEXT: s_mov_b32 s2, -1
; GFX1032-NEXT: ; implicit-def: $vgpr0 ; GFX1032-NEXT: ; implicit-def: $vgpr0
; GFX1032-NEXT: s_and_saveexec_b32 s3, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s3, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB17_2 ; GFX1032-NEXT: s_cbranch_execz .LBB17_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: v_mov_b32_e32 v0, 0 ; GFX1032-NEXT: v_mov_b32_e32 v0, 0
; GFX1032-NEXT: v_mov_b32_e32 v4, s4 ; GFX1032-NEXT: v_mov_b32_e32 v4, s4
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: ds_max_rtn_i32 v0, v0, v4 ; GFX1032-NEXT: ds_max_rtn_i32 v0, v0, v4
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: BB17_2: ; GFX1032-NEXT: .LBB17_2:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s3 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s3
; GFX1032-NEXT: v_readfirstlane_b32 s3, v0 ; GFX1032-NEXT: v_readfirstlane_b32 s3, v0
; GFX1032-NEXT: v_mov_b32_e32 v0, v1 ; GFX1032-NEXT: v_mov_b32_e32 v0, v1
; GFX1032-NEXT: v_max_i32_e32 v0, s3, v0 ; GFX1032-NEXT: v_max_i32_e32 v0, s3, v0
; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s3, 0x31016000
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0
Show All 11 Lines
; GFX7LESS-LABEL: max_i64_constant: ; GFX7LESS-LABEL: max_i64_constant:
; GFX7LESS: ; %bb.0: ; %entry ; GFX7LESS: ; %bb.0: ; %entry
; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0 ; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, exec_hi, v0 ; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, exec_hi, v0
; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX7LESS-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX7LESS-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX7LESS-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX7LESS-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX7LESS-NEXT: s_cbranch_execz BB18_2 ; GFX7LESS-NEXT: s_cbranch_execz .LBB18_2
; GFX7LESS-NEXT: ; %bb.1: ; GFX7LESS-NEXT: ; %bb.1:
; GFX7LESS-NEXT: v_mov_b32_e32 v2, 0 ; GFX7LESS-NEXT: v_mov_b32_e32 v2, 0
; GFX7LESS-NEXT: v_mov_b32_e32 v0, 5 ; GFX7LESS-NEXT: v_mov_b32_e32 v0, 5
; GFX7LESS-NEXT: v_mov_b32_e32 v1, 0 ; GFX7LESS-NEXT: v_mov_b32_e32 v1, 0
; GFX7LESS-NEXT: s_mov_b32 m0, -1 ; GFX7LESS-NEXT: s_mov_b32 m0, -1
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: ds_max_rtn_i64 v[0:1], v2, v[0:1] ; GFX7LESS-NEXT: ds_max_rtn_i64 v[0:1], v2, v[0:1]
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: BB18_2: ; GFX7LESS-NEXT: .LBB18_2:
; GFX7LESS-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX7LESS-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: v_readfirstlane_b32 s4, v0 ; GFX7LESS-NEXT: v_readfirstlane_b32 s4, v0
; GFX7LESS-NEXT: v_readfirstlane_b32 s5, v1 ; GFX7LESS-NEXT: v_readfirstlane_b32 s5, v1
; GFX7LESS-NEXT: v_bfrev_b32_e32 v1, 1 ; GFX7LESS-NEXT: v_bfrev_b32_e32 v1, 1
; GFX7LESS-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc ; GFX7LESS-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc
; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000 ; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000
; GFX7LESS-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc ; GFX7LESS-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
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; GFX8-LABEL: max_i64_constant: ; GFX8-LABEL: max_i64_constant:
; GFX8: ; %bb.0: ; %entry ; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX8-NEXT: s_cbranch_execz BB18_2 ; GFX8-NEXT: s_cbranch_execz .LBB18_2
; GFX8-NEXT: ; %bb.1: ; GFX8-NEXT: ; %bb.1:
; GFX8-NEXT: v_mov_b32_e32 v0, 5 ; GFX8-NEXT: v_mov_b32_e32 v0, 5
; GFX8-NEXT: v_mov_b32_e32 v2, 0 ; GFX8-NEXT: v_mov_b32_e32 v2, 0
; GFX8-NEXT: v_mov_b32_e32 v1, 0 ; GFX8-NEXT: v_mov_b32_e32 v1, 0
; GFX8-NEXT: s_mov_b32 m0, -1 ; GFX8-NEXT: s_mov_b32 m0, -1
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: ds_max_rtn_i64 v[0:1], v2, v[0:1] ; GFX8-NEXT: ds_max_rtn_i64 v[0:1], v2, v[0:1]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: BB18_2: ; GFX8-NEXT: .LBB18_2:
; GFX8-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX8-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_readfirstlane_b32 s2, v0 ; GFX8-NEXT: v_readfirstlane_b32 s2, v0
; GFX8-NEXT: v_bfrev_b32_e32 v0, 1 ; GFX8-NEXT: v_bfrev_b32_e32 v0, 1
; GFX8-NEXT: v_readfirstlane_b32 s3, v1 ; GFX8-NEXT: v_readfirstlane_b32 s3, v1
; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v0, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc
; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1] ; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1]
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; GFX9-LABEL: max_i64_constant: ; GFX9-LABEL: max_i64_constant:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-NEXT: s_cbranch_execz BB18_2 ; GFX9-NEXT: s_cbranch_execz .LBB18_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: v_mov_b32_e32 v0, 5 ; GFX9-NEXT: v_mov_b32_e32 v0, 5
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: ds_max_rtn_i64 v[0:1], v2, v[0:1] ; GFX9-NEXT: ds_max_rtn_i64 v[0:1], v2, v[0:1]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: BB18_2: ; GFX9-NEXT: .LBB18_2:
; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX9-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s2, v0 ; GFX9-NEXT: v_readfirstlane_b32 s2, v0
; GFX9-NEXT: v_bfrev_b32_e32 v0, 1 ; GFX9-NEXT: v_bfrev_b32_e32 v0, 1
; GFX9-NEXT: v_readfirstlane_b32 s3, v1 ; GFX9-NEXT: v_readfirstlane_b32 s3, v1
; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v0, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v0, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc
; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1] ; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1]
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; GFX1064-LABEL: max_i64_constant: ; GFX1064-LABEL: max_i64_constant:
; GFX1064: ; %bb.0: ; %entry ; GFX1064: ; %bb.0: ; %entry
; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX1064-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX1064-NEXT: s_cbranch_execz BB18_2 ; GFX1064-NEXT: s_cbranch_execz .LBB18_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: v_mov_b32_e32 v0, 5 ; GFX1064-NEXT: v_mov_b32_e32 v0, 5
; GFX1064-NEXT: v_mov_b32_e32 v1, 0 ; GFX1064-NEXT: v_mov_b32_e32 v1, 0
; GFX1064-NEXT: v_mov_b32_e32 v2, 0 ; GFX1064-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: ds_max_rtn_i64 v[0:1], v2, v[0:1] ; GFX1064-NEXT: ds_max_rtn_i64 v[0:1], v2, v[0:1]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: BB18_2: ; GFX1064-NEXT: .LBB18_2:
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX1064-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX1064-NEXT: v_readfirstlane_b32 s2, v0 ; GFX1064-NEXT: v_readfirstlane_b32 s2, v0
; GFX1064-NEXT: v_readfirstlane_b32 s3, v1 ; GFX1064-NEXT: v_readfirstlane_b32 s3, v1
; GFX1064-NEXT: v_cndmask_b32_e64 v1, 0, 0x80000000, vcc ; GFX1064-NEXT: v_cndmask_b32_e64 v1, 0, 0x80000000, vcc
; GFX1064-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc ; GFX1064-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc
; GFX1064-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1] ; GFX1064-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1]
; GFX1064-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc ; GFX1064-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc
; GFX1064-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc ; GFX1064-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064-NEXT: s_mov_b32 s2, -1 ; GFX1064-NEXT: s_mov_b32 s2, -1
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: s_endpgm
; ;
; GFX1032-LABEL: max_i64_constant: ; GFX1032-LABEL: max_i64_constant:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX1032-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1032-NEXT: s_and_saveexec_b32 s2, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s2, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB18_2 ; GFX1032-NEXT: s_cbranch_execz .LBB18_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: v_mov_b32_e32 v0, 5 ; GFX1032-NEXT: v_mov_b32_e32 v0, 5
; GFX1032-NEXT: v_mov_b32_e32 v1, 0 ; GFX1032-NEXT: v_mov_b32_e32 v1, 0
; GFX1032-NEXT: v_mov_b32_e32 v2, 0 ; GFX1032-NEXT: v_mov_b32_e32 v2, 0
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: ds_max_rtn_i64 v[0:1], v2, v[0:1] ; GFX1032-NEXT: ds_max_rtn_i64 v[0:1], v2, v[0:1]
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: BB18_2: ; GFX1032-NEXT: .LBB18_2:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX1032-NEXT: v_readfirstlane_b32 s2, v0 ; GFX1032-NEXT: v_readfirstlane_b32 s2, v0
; GFX1032-NEXT: v_readfirstlane_b32 s3, v1 ; GFX1032-NEXT: v_readfirstlane_b32 s3, v1
; GFX1032-NEXT: v_cndmask_b32_e64 v1, 0, 0x80000000, vcc_lo ; GFX1032-NEXT: v_cndmask_b32_e64 v1, 0, 0x80000000, vcc_lo
; GFX1032-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc_lo ; GFX1032-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc_lo
; GFX1032-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[0:1] ; GFX1032-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[0:1]
; GFX1032-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc_lo ; GFX1032-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc_lo
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; GFX8-NEXT: v_min_i32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX8-NEXT: v_min_i32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX8-NEXT: v_readlane_b32 s4, v2, 63 ; GFX8-NEXT: v_readlane_b32 s4, v2, 63
; GFX8-NEXT: s_nop 0 ; GFX8-NEXT: s_nop 0
; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf ; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX8-NEXT: s_mov_b64 exec, s[2:3] ; GFX8-NEXT: s_mov_b64 exec, s[2:3]
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX8-NEXT: ; implicit-def: $vgpr0 ; GFX8-NEXT: ; implicit-def: $vgpr0
; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX8-NEXT: s_cbranch_execz BB19_2 ; GFX8-NEXT: s_cbranch_execz .LBB19_2
; GFX8-NEXT: ; %bb.1: ; GFX8-NEXT: ; %bb.1:
; GFX8-NEXT: v_mov_b32_e32 v0, 0 ; GFX8-NEXT: v_mov_b32_e32 v0, 0
; GFX8-NEXT: v_mov_b32_e32 v3, s4 ; GFX8-NEXT: v_mov_b32_e32 v3, s4
; GFX8-NEXT: s_mov_b32 m0, -1 ; GFX8-NEXT: s_mov_b32 m0, -1
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: ds_min_rtn_i32 v0, v0, v3 ; GFX8-NEXT: ds_min_rtn_i32 v0, v0, v3
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: BB19_2: ; GFX8-NEXT: .LBB19_2:
; GFX8-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX8-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_readfirstlane_b32 s2, v0 ; GFX8-NEXT: v_readfirstlane_b32 s2, v0
; GFX8-NEXT: v_mov_b32_e32 v0, v1 ; GFX8-NEXT: v_mov_b32_e32 v0, v1
; GFX8-NEXT: v_min_i32_e32 v0, s2, v0 ; GFX8-NEXT: v_min_i32_e32 v0, s2, v0
; GFX8-NEXT: s_mov_b32 s3, 0xf000 ; GFX8-NEXT: s_mov_b32 s3, 0xf000
; GFX8-NEXT: s_mov_b32 s2, -1 ; GFX8-NEXT: s_mov_b32 s2, -1
; GFX8-NEXT: s_nop 0 ; GFX8-NEXT: s_nop 0
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; GFX9-NEXT: v_min_i32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX9-NEXT: v_min_i32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9-NEXT: v_readlane_b32 s4, v2, 63 ; GFX9-NEXT: v_readlane_b32 s4, v2, 63
; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: s_nop 0
; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf ; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX9-NEXT: s_mov_b64 exec, s[2:3] ; GFX9-NEXT: s_mov_b64 exec, s[2:3]
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-NEXT: ; implicit-def: $vgpr0 ; GFX9-NEXT: ; implicit-def: $vgpr0
; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-NEXT: s_cbranch_execz BB19_2 ; GFX9-NEXT: s_cbranch_execz .LBB19_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v3, s4 ; GFX9-NEXT: v_mov_b32_e32 v3, s4
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: ds_min_rtn_i32 v0, v0, v3 ; GFX9-NEXT: ds_min_rtn_i32 v0, v0, v3
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: BB19_2: ; GFX9-NEXT: .LBB19_2:
; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX9-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s2, v0 ; GFX9-NEXT: v_readfirstlane_b32 s2, v0
; GFX9-NEXT: v_mov_b32_e32 v0, v1 ; GFX9-NEXT: v_mov_b32_e32 v0, v1
; GFX9-NEXT: v_min_i32_e32 v0, s2, v0 ; GFX9-NEXT: v_min_i32_e32 v0, s2, v0
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: s_nop 0
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; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1064-NEXT: s_or_saveexec_b64 s[4:5], -1 ; GFX1064-NEXT: s_or_saveexec_b64 s[4:5], -1
; GFX1064-NEXT: v_writelane_b32 v1, s6, 48 ; GFX1064-NEXT: v_writelane_b32 v1, s6, 48
; GFX1064-NEXT: s_mov_b64 exec, s[4:5] ; GFX1064-NEXT: s_mov_b64 exec, s[4:5]
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: s_mov_b32 s2, -1 ; GFX1064-NEXT: s_mov_b32 s2, -1
; GFX1064-NEXT: ; implicit-def: $vgpr0 ; GFX1064-NEXT: ; implicit-def: $vgpr0
; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX1064-NEXT: s_cbranch_execz BB19_2 ; GFX1064-NEXT: s_cbranch_execz .LBB19_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: v_mov_b32_e32 v0, 0 ; GFX1064-NEXT: v_mov_b32_e32 v0, 0
; GFX1064-NEXT: v_mov_b32_e32 v4, s7 ; GFX1064-NEXT: v_mov_b32_e32 v4, s7
; GFX1064-NEXT: s_mov_b32 s3, s7 ; GFX1064-NEXT: s_mov_b32 s3, s7
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: ds_min_rtn_i32 v0, v0, v4 ; GFX1064-NEXT: ds_min_rtn_i32 v0, v0, v4
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: BB19_2: ; GFX1064-NEXT: .LBB19_2:
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX1064-NEXT: v_readfirstlane_b32 s3, v0 ; GFX1064-NEXT: v_readfirstlane_b32 s3, v0
; GFX1064-NEXT: v_mov_b32_e32 v0, v1 ; GFX1064-NEXT: v_mov_b32_e32 v0, v1
; GFX1064-NEXT: v_min_i32_e32 v0, s3, v0 ; GFX1064-NEXT: v_min_i32_e32 v0, s3, v0
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1032-NEXT: s_or_saveexec_b32 s2, -1 ; GFX1032-NEXT: s_or_saveexec_b32 s2, -1
; GFX1032-NEXT: v_writelane_b32 v1, s3, 16 ; GFX1032-NEXT: v_writelane_b32 v1, s3, 16
; GFX1032-NEXT: s_mov_b32 exec_lo, s2 ; GFX1032-NEXT: s_mov_b32 exec_lo, s2
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: s_mov_b32 s2, -1 ; GFX1032-NEXT: s_mov_b32 s2, -1
; GFX1032-NEXT: ; implicit-def: $vgpr0 ; GFX1032-NEXT: ; implicit-def: $vgpr0
; GFX1032-NEXT: s_and_saveexec_b32 s3, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s3, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB19_2 ; GFX1032-NEXT: s_cbranch_execz .LBB19_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: v_mov_b32_e32 v0, 0 ; GFX1032-NEXT: v_mov_b32_e32 v0, 0
; GFX1032-NEXT: v_mov_b32_e32 v4, s4 ; GFX1032-NEXT: v_mov_b32_e32 v4, s4
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: ds_min_rtn_i32 v0, v0, v4 ; GFX1032-NEXT: ds_min_rtn_i32 v0, v0, v4
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: BB19_2: ; GFX1032-NEXT: .LBB19_2:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s3 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s3
; GFX1032-NEXT: v_readfirstlane_b32 s3, v0 ; GFX1032-NEXT: v_readfirstlane_b32 s3, v0
; GFX1032-NEXT: v_mov_b32_e32 v0, v1 ; GFX1032-NEXT: v_mov_b32_e32 v0, v1
; GFX1032-NEXT: v_min_i32_e32 v0, s3, v0 ; GFX1032-NEXT: v_min_i32_e32 v0, s3, v0
; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s3, 0x31016000
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX7LESS-LABEL: min_i64_constant: ; GFX7LESS-LABEL: min_i64_constant:
; GFX7LESS: ; %bb.0: ; %entry ; GFX7LESS: ; %bb.0: ; %entry
; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0 ; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, exec_hi, v0 ; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, exec_hi, v0
; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX7LESS-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX7LESS-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX7LESS-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX7LESS-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX7LESS-NEXT: s_cbranch_execz BB20_2 ; GFX7LESS-NEXT: s_cbranch_execz .LBB20_2
; GFX7LESS-NEXT: ; %bb.1: ; GFX7LESS-NEXT: ; %bb.1:
; GFX7LESS-NEXT: v_mov_b32_e32 v2, 0 ; GFX7LESS-NEXT: v_mov_b32_e32 v2, 0
; GFX7LESS-NEXT: v_mov_b32_e32 v0, 5 ; GFX7LESS-NEXT: v_mov_b32_e32 v0, 5
; GFX7LESS-NEXT: v_mov_b32_e32 v1, 0 ; GFX7LESS-NEXT: v_mov_b32_e32 v1, 0
; GFX7LESS-NEXT: s_mov_b32 m0, -1 ; GFX7LESS-NEXT: s_mov_b32 m0, -1
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: ds_min_rtn_i64 v[0:1], v2, v[0:1] ; GFX7LESS-NEXT: ds_min_rtn_i64 v[0:1], v2, v[0:1]
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: BB20_2: ; GFX7LESS-NEXT: .LBB20_2:
; GFX7LESS-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX7LESS-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: v_readfirstlane_b32 s4, v0 ; GFX7LESS-NEXT: v_readfirstlane_b32 s4, v0
; GFX7LESS-NEXT: v_readfirstlane_b32 s5, v1 ; GFX7LESS-NEXT: v_readfirstlane_b32 s5, v1
; GFX7LESS-NEXT: v_bfrev_b32_e32 v1, -2 ; GFX7LESS-NEXT: v_bfrev_b32_e32 v1, -2
; GFX7LESS-NEXT: s_mov_b32 s2, -1 ; GFX7LESS-NEXT: s_mov_b32 s2, -1
; GFX7LESS-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc ; GFX7LESS-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc
; GFX7LESS-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc ; GFX7LESS-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
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; GFX8-LABEL: min_i64_constant: ; GFX8-LABEL: min_i64_constant:
; GFX8: ; %bb.0: ; %entry ; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX8-NEXT: s_cbranch_execz BB20_2 ; GFX8-NEXT: s_cbranch_execz .LBB20_2
; GFX8-NEXT: ; %bb.1: ; GFX8-NEXT: ; %bb.1:
; GFX8-NEXT: v_mov_b32_e32 v0, 5 ; GFX8-NEXT: v_mov_b32_e32 v0, 5
; GFX8-NEXT: v_mov_b32_e32 v2, 0 ; GFX8-NEXT: v_mov_b32_e32 v2, 0
; GFX8-NEXT: v_mov_b32_e32 v1, 0 ; GFX8-NEXT: v_mov_b32_e32 v1, 0
; GFX8-NEXT: s_mov_b32 m0, -1 ; GFX8-NEXT: s_mov_b32 m0, -1
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: ds_min_rtn_i64 v[0:1], v2, v[0:1] ; GFX8-NEXT: ds_min_rtn_i64 v[0:1], v2, v[0:1]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: BB20_2: ; GFX8-NEXT: .LBB20_2:
; GFX8-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX8-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_readfirstlane_b32 s4, v0 ; GFX8-NEXT: v_readfirstlane_b32 s4, v0
; GFX8-NEXT: v_bfrev_b32_e32 v0, -2 ; GFX8-NEXT: v_bfrev_b32_e32 v0, -2
; GFX8-NEXT: v_readfirstlane_b32 s5, v1 ; GFX8-NEXT: v_readfirstlane_b32 s5, v1
; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v0, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1] ; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]
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; GFX9-LABEL: min_i64_constant: ; GFX9-LABEL: min_i64_constant:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-NEXT: s_cbranch_execz BB20_2 ; GFX9-NEXT: s_cbranch_execz .LBB20_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: v_mov_b32_e32 v0, 5 ; GFX9-NEXT: v_mov_b32_e32 v0, 5
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: ds_min_rtn_i64 v[0:1], v2, v[0:1] ; GFX9-NEXT: ds_min_rtn_i64 v[0:1], v2, v[0:1]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: BB20_2: ; GFX9-NEXT: .LBB20_2:
; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX9-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s4, v0 ; GFX9-NEXT: v_readfirstlane_b32 s4, v0
; GFX9-NEXT: v_bfrev_b32_e32 v0, -2 ; GFX9-NEXT: v_bfrev_b32_e32 v0, -2
; GFX9-NEXT: v_readfirstlane_b32 s5, v1 ; GFX9-NEXT: v_readfirstlane_b32 s5, v1
; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v0, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v0, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1] ; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]
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; GFX1064-LABEL: min_i64_constant: ; GFX1064-LABEL: min_i64_constant:
; GFX1064: ; %bb.0: ; %entry ; GFX1064: ; %bb.0: ; %entry
; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX1064-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX1064-NEXT: s_cbranch_execz BB20_2 ; GFX1064-NEXT: s_cbranch_execz .LBB20_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: v_mov_b32_e32 v0, 5 ; GFX1064-NEXT: v_mov_b32_e32 v0, 5
; GFX1064-NEXT: v_mov_b32_e32 v1, 0 ; GFX1064-NEXT: v_mov_b32_e32 v1, 0
; GFX1064-NEXT: v_mov_b32_e32 v2, 0 ; GFX1064-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: ds_min_rtn_i64 v[0:1], v2, v[0:1] ; GFX1064-NEXT: ds_min_rtn_i64 v[0:1], v2, v[0:1]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: BB20_2: ; GFX1064-NEXT: .LBB20_2:
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX1064-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX1064-NEXT: v_readfirstlane_b32 s2, v0 ; GFX1064-NEXT: v_readfirstlane_b32 s2, v0
; GFX1064-NEXT: v_readfirstlane_b32 s3, v1 ; GFX1064-NEXT: v_readfirstlane_b32 s3, v1
; GFX1064-NEXT: v_cndmask_b32_e64 v1, 0, 0x7fffffff, vcc ; GFX1064-NEXT: v_cndmask_b32_e64 v1, 0, 0x7fffffff, vcc
; GFX1064-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc ; GFX1064-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc
; GFX1064-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1] ; GFX1064-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
; GFX1064-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc ; GFX1064-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc
; GFX1064-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc ; GFX1064-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc
; GFX1064-NEXT: s_mov_b32 s2, -1 ; GFX1064-NEXT: s_mov_b32 s2, -1
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: s_endpgm
; ;
; GFX1032-LABEL: min_i64_constant: ; GFX1032-LABEL: min_i64_constant:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX1032-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1032-NEXT: s_and_saveexec_b32 s2, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s2, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB20_2 ; GFX1032-NEXT: s_cbranch_execz .LBB20_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: v_mov_b32_e32 v0, 5 ; GFX1032-NEXT: v_mov_b32_e32 v0, 5
; GFX1032-NEXT: v_mov_b32_e32 v1, 0 ; GFX1032-NEXT: v_mov_b32_e32 v1, 0
; GFX1032-NEXT: v_mov_b32_e32 v2, 0 ; GFX1032-NEXT: v_mov_b32_e32 v2, 0
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: ds_min_rtn_i64 v[0:1], v2, v[0:1] ; GFX1032-NEXT: ds_min_rtn_i64 v[0:1], v2, v[0:1]
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: BB20_2: ; GFX1032-NEXT: .LBB20_2:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX1032-NEXT: v_readfirstlane_b32 s2, v0 ; GFX1032-NEXT: v_readfirstlane_b32 s2, v0
; GFX1032-NEXT: v_readfirstlane_b32 s3, v1 ; GFX1032-NEXT: v_readfirstlane_b32 s3, v1
; GFX1032-NEXT: v_cndmask_b32_e64 v1, 0, 0x7fffffff, vcc_lo ; GFX1032-NEXT: v_cndmask_b32_e64 v1, 0, 0x7fffffff, vcc_lo
; GFX1032-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc_lo ; GFX1032-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc_lo
; GFX1032-NEXT: v_cmp_lt_i64_e32 vcc_lo, s[2:3], v[0:1] ; GFX1032-NEXT: v_cmp_lt_i64_e32 vcc_lo, s[2:3], v[0:1]
; GFX1032-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc_lo ; GFX1032-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc_lo
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; GFX8-NEXT: v_max_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX8-NEXT: v_max_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX8-NEXT: v_readlane_b32 s4, v2, 63 ; GFX8-NEXT: v_readlane_b32 s4, v2, 63
; GFX8-NEXT: s_nop 0 ; GFX8-NEXT: s_nop 0
; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf ; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX8-NEXT: s_mov_b64 exec, s[2:3] ; GFX8-NEXT: s_mov_b64 exec, s[2:3]
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX8-NEXT: ; implicit-def: $vgpr0 ; GFX8-NEXT: ; implicit-def: $vgpr0
; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX8-NEXT: s_cbranch_execz BB21_2 ; GFX8-NEXT: s_cbranch_execz .LBB21_2
; GFX8-NEXT: ; %bb.1: ; GFX8-NEXT: ; %bb.1:
; GFX8-NEXT: v_mov_b32_e32 v0, 0 ; GFX8-NEXT: v_mov_b32_e32 v0, 0
; GFX8-NEXT: v_mov_b32_e32 v3, s4 ; GFX8-NEXT: v_mov_b32_e32 v3, s4
; GFX8-NEXT: s_mov_b32 m0, -1 ; GFX8-NEXT: s_mov_b32 m0, -1
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: ds_max_rtn_u32 v0, v0, v3 ; GFX8-NEXT: ds_max_rtn_u32 v0, v0, v3
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: BB21_2: ; GFX8-NEXT: .LBB21_2:
; GFX8-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX8-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_readfirstlane_b32 s2, v0 ; GFX8-NEXT: v_readfirstlane_b32 s2, v0
; GFX8-NEXT: v_mov_b32_e32 v0, v1 ; GFX8-NEXT: v_mov_b32_e32 v0, v1
; GFX8-NEXT: v_max_u32_e32 v0, s2, v0 ; GFX8-NEXT: v_max_u32_e32 v0, s2, v0
; GFX8-NEXT: s_mov_b32 s3, 0xf000 ; GFX8-NEXT: s_mov_b32 s3, 0xf000
; GFX8-NEXT: s_mov_b32 s2, -1 ; GFX8-NEXT: s_mov_b32 s2, -1
; GFX8-NEXT: s_nop 0 ; GFX8-NEXT: s_nop 0
Show All 26 Lines
; GFX9-NEXT: v_max_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX9-NEXT: v_max_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9-NEXT: v_readlane_b32 s4, v2, 63 ; GFX9-NEXT: v_readlane_b32 s4, v2, 63
; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: s_nop 0
; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf ; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX9-NEXT: s_mov_b64 exec, s[2:3] ; GFX9-NEXT: s_mov_b64 exec, s[2:3]
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-NEXT: ; implicit-def: $vgpr0 ; GFX9-NEXT: ; implicit-def: $vgpr0
; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-NEXT: s_cbranch_execz BB21_2 ; GFX9-NEXT: s_cbranch_execz .LBB21_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v3, s4 ; GFX9-NEXT: v_mov_b32_e32 v3, s4
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: ds_max_rtn_u32 v0, v0, v3 ; GFX9-NEXT: ds_max_rtn_u32 v0, v0, v3
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: BB21_2: ; GFX9-NEXT: .LBB21_2:
; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX9-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s2, v0 ; GFX9-NEXT: v_readfirstlane_b32 s2, v0
; GFX9-NEXT: v_mov_b32_e32 v0, v1 ; GFX9-NEXT: v_mov_b32_e32 v0, v1
; GFX9-NEXT: v_max_u32_e32 v0, s2, v0 ; GFX9-NEXT: v_max_u32_e32 v0, s2, v0
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: s_nop 0
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; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1064-NEXT: s_or_saveexec_b64 s[4:5], -1 ; GFX1064-NEXT: s_or_saveexec_b64 s[4:5], -1
; GFX1064-NEXT: v_writelane_b32 v3, s6, 48 ; GFX1064-NEXT: v_writelane_b32 v3, s6, 48
; GFX1064-NEXT: s_mov_b64 exec, s[4:5] ; GFX1064-NEXT: s_mov_b64 exec, s[4:5]
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: s_mov_b32 s2, -1 ; GFX1064-NEXT: s_mov_b32 s2, -1
; GFX1064-NEXT: ; implicit-def: $vgpr0 ; GFX1064-NEXT: ; implicit-def: $vgpr0
; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX1064-NEXT: s_cbranch_execz BB21_2 ; GFX1064-NEXT: s_cbranch_execz .LBB21_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: v_mov_b32_e32 v0, 0 ; GFX1064-NEXT: v_mov_b32_e32 v0, 0
; GFX1064-NEXT: v_mov_b32_e32 v4, s7 ; GFX1064-NEXT: v_mov_b32_e32 v4, s7
; GFX1064-NEXT: s_mov_b32 s3, s7 ; GFX1064-NEXT: s_mov_b32 s3, s7
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: ds_max_rtn_u32 v0, v0, v4 ; GFX1064-NEXT: ds_max_rtn_u32 v0, v0, v4
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: BB21_2: ; GFX1064-NEXT: .LBB21_2:
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX1064-NEXT: v_readfirstlane_b32 s3, v0 ; GFX1064-NEXT: v_readfirstlane_b32 s3, v0
; GFX1064-NEXT: v_mov_b32_e32 v0, v3 ; GFX1064-NEXT: v_mov_b32_e32 v0, v3
; GFX1064-NEXT: v_max_u32_e32 v0, s3, v0 ; GFX1064-NEXT: v_max_u32_e32 v0, s3, v0
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1032-NEXT: s_or_saveexec_b32 s2, -1 ; GFX1032-NEXT: s_or_saveexec_b32 s2, -1
; GFX1032-NEXT: v_writelane_b32 v3, s3, 16 ; GFX1032-NEXT: v_writelane_b32 v3, s3, 16
; GFX1032-NEXT: s_mov_b32 exec_lo, s2 ; GFX1032-NEXT: s_mov_b32 exec_lo, s2
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: s_mov_b32 s2, -1 ; GFX1032-NEXT: s_mov_b32 s2, -1
; GFX1032-NEXT: ; implicit-def: $vgpr0 ; GFX1032-NEXT: ; implicit-def: $vgpr0
; GFX1032-NEXT: s_and_saveexec_b32 s3, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s3, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB21_2 ; GFX1032-NEXT: s_cbranch_execz .LBB21_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: v_mov_b32_e32 v0, 0 ; GFX1032-NEXT: v_mov_b32_e32 v0, 0
; GFX1032-NEXT: v_mov_b32_e32 v4, s4 ; GFX1032-NEXT: v_mov_b32_e32 v4, s4
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: ds_max_rtn_u32 v0, v0, v4 ; GFX1032-NEXT: ds_max_rtn_u32 v0, v0, v4
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: BB21_2: ; GFX1032-NEXT: .LBB21_2:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s3 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s3
; GFX1032-NEXT: v_readfirstlane_b32 s3, v0 ; GFX1032-NEXT: v_readfirstlane_b32 s3, v0
; GFX1032-NEXT: v_mov_b32_e32 v0, v3 ; GFX1032-NEXT: v_mov_b32_e32 v0, v3
; GFX1032-NEXT: v_max_u32_e32 v0, s3, v0 ; GFX1032-NEXT: v_max_u32_e32 v0, s3, v0
; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s3, 0x31016000
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX7LESS-LABEL: umax_i64_constant: ; GFX7LESS-LABEL: umax_i64_constant:
; GFX7LESS: ; %bb.0: ; %entry ; GFX7LESS: ; %bb.0: ; %entry
; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0 ; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, exec_hi, v0 ; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, exec_hi, v0
; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX7LESS-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX7LESS-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX7LESS-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX7LESS-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX7LESS-NEXT: s_cbranch_execz BB22_2 ; GFX7LESS-NEXT: s_cbranch_execz .LBB22_2
; GFX7LESS-NEXT: ; %bb.1: ; GFX7LESS-NEXT: ; %bb.1:
; GFX7LESS-NEXT: v_mov_b32_e32 v2, 0 ; GFX7LESS-NEXT: v_mov_b32_e32 v2, 0
; GFX7LESS-NEXT: v_mov_b32_e32 v0, 5 ; GFX7LESS-NEXT: v_mov_b32_e32 v0, 5
; GFX7LESS-NEXT: v_mov_b32_e32 v1, 0 ; GFX7LESS-NEXT: v_mov_b32_e32 v1, 0
; GFX7LESS-NEXT: s_mov_b32 m0, -1 ; GFX7LESS-NEXT: s_mov_b32 m0, -1
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: ds_max_rtn_u64 v[0:1], v2, v[0:1] ; GFX7LESS-NEXT: ds_max_rtn_u64 v[0:1], v2, v[0:1]
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: BB22_2: ; GFX7LESS-NEXT: .LBB22_2:
; GFX7LESS-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX7LESS-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: v_readfirstlane_b32 s4, v0 ; GFX7LESS-NEXT: v_readfirstlane_b32 s4, v0
; GFX7LESS-NEXT: v_readfirstlane_b32 s5, v1 ; GFX7LESS-NEXT: v_readfirstlane_b32 s5, v1
; GFX7LESS-NEXT: v_mov_b32_e32 v1, 0 ; GFX7LESS-NEXT: v_mov_b32_e32 v1, 0
; GFX7LESS-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc ; GFX7LESS-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc
; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000 ; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000
; GFX7LESS-NEXT: v_mov_b32_e32 v2, s4 ; GFX7LESS-NEXT: v_mov_b32_e32 v2, s4
; GFX7LESS-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[0:1] ; GFX7LESS-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[0:1]
; GFX7LESS-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX7LESS-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX7LESS-NEXT: v_mov_b32_e32 v1, s5 ; GFX7LESS-NEXT: v_mov_b32_e32 v1, s5
; GFX7LESS-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc ; GFX7LESS-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX7LESS-NEXT: s_mov_b32 s2, -1 ; GFX7LESS-NEXT: s_mov_b32 s2, -1
; GFX7LESS-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX7LESS-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX7LESS-NEXT: s_endpgm ; GFX7LESS-NEXT: s_endpgm
; ;
; GFX8-LABEL: umax_i64_constant: ; GFX8-LABEL: umax_i64_constant:
; GFX8: ; %bb.0: ; %entry ; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX8-NEXT: s_cbranch_execz BB22_2 ; GFX8-NEXT: s_cbranch_execz .LBB22_2
; GFX8-NEXT: ; %bb.1: ; GFX8-NEXT: ; %bb.1:
; GFX8-NEXT: v_mov_b32_e32 v0, 5 ; GFX8-NEXT: v_mov_b32_e32 v0, 5
; GFX8-NEXT: v_mov_b32_e32 v2, 0 ; GFX8-NEXT: v_mov_b32_e32 v2, 0
; GFX8-NEXT: v_mov_b32_e32 v1, 0 ; GFX8-NEXT: v_mov_b32_e32 v1, 0
; GFX8-NEXT: s_mov_b32 m0, -1 ; GFX8-NEXT: s_mov_b32 m0, -1
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: ds_max_rtn_u64 v[0:1], v2, v[0:1] ; GFX8-NEXT: ds_max_rtn_u64 v[0:1], v2, v[0:1]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: BB22_2: ; GFX8-NEXT: .LBB22_2:
; GFX8-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX8-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_readfirstlane_b32 s2, v0 ; GFX8-NEXT: v_readfirstlane_b32 s2, v0
; GFX8-NEXT: v_readfirstlane_b32 s3, v1 ; GFX8-NEXT: v_readfirstlane_b32 s3, v1
; GFX8-NEXT: v_mov_b32_e32 v1, 0 ; GFX8-NEXT: v_mov_b32_e32 v1, 0
; GFX8-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc
; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[0:1] ; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[0:1]
; GFX8-NEXT: v_mov_b32_e32 v2, s2 ; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX8-NEXT: s_mov_b32 s3, 0xf000 ; GFX8-NEXT: s_mov_b32 s3, 0xf000
; GFX8-NEXT: s_mov_b32 s2, -1 ; GFX8-NEXT: s_mov_b32 s2, -1
; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-LABEL: umax_i64_constant: ; GFX9-LABEL: umax_i64_constant:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-NEXT: s_cbranch_execz BB22_2 ; GFX9-NEXT: s_cbranch_execz .LBB22_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: v_mov_b32_e32 v0, 5 ; GFX9-NEXT: v_mov_b32_e32 v0, 5
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: ds_max_rtn_u64 v[0:1], v2, v[0:1] ; GFX9-NEXT: ds_max_rtn_u64 v[0:1], v2, v[0:1]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: BB22_2: ; GFX9-NEXT: .LBB22_2:
; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX9-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s2, v0 ; GFX9-NEXT: v_readfirstlane_b32 s2, v0
; GFX9-NEXT: v_readfirstlane_b32 s3, v1 ; GFX9-NEXT: v_readfirstlane_b32 s3, v1
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc
; GFX9-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[0:1] ; GFX9-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[0:1]
; GFX9-NEXT: v_mov_b32_e32 v2, s2 ; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX1064-LABEL: umax_i64_constant: ; GFX1064-LABEL: umax_i64_constant:
; GFX1064: ; %bb.0: ; %entry ; GFX1064: ; %bb.0: ; %entry
; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX1064-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX1064-NEXT: s_cbranch_execz BB22_2 ; GFX1064-NEXT: s_cbranch_execz .LBB22_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: v_mov_b32_e32 v0, 5 ; GFX1064-NEXT: v_mov_b32_e32 v0, 5
; GFX1064-NEXT: v_mov_b32_e32 v1, 0 ; GFX1064-NEXT: v_mov_b32_e32 v1, 0
; GFX1064-NEXT: v_mov_b32_e32 v2, 0 ; GFX1064-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: ds_max_rtn_u64 v[0:1], v2, v[0:1] ; GFX1064-NEXT: ds_max_rtn_u64 v[0:1], v2, v[0:1]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: BB22_2: ; GFX1064-NEXT: .LBB22_2:
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX1064-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX1064-NEXT: v_readfirstlane_b32 s2, v0 ; GFX1064-NEXT: v_readfirstlane_b32 s2, v0
; GFX1064-NEXT: v_readfirstlane_b32 s3, v1 ; GFX1064-NEXT: v_readfirstlane_b32 s3, v1
; GFX1064-NEXT: v_mov_b32_e32 v1, 0 ; GFX1064-NEXT: v_mov_b32_e32 v1, 0
; GFX1064-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc ; GFX1064-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc
; GFX1064-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[0:1] ; GFX1064-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[0:1]
; GFX1064-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc ; GFX1064-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc
; GFX1064-NEXT: v_cndmask_b32_e64 v1, 0, s3, vcc ; GFX1064-NEXT: v_cndmask_b32_e64 v1, 0, s3, vcc
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064-NEXT: s_mov_b32 s2, -1 ; GFX1064-NEXT: s_mov_b32 s2, -1
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: s_endpgm
; ;
; GFX1032-LABEL: umax_i64_constant: ; GFX1032-LABEL: umax_i64_constant:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX1032-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1032-NEXT: s_and_saveexec_b32 s2, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s2, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB22_2 ; GFX1032-NEXT: s_cbranch_execz .LBB22_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: v_mov_b32_e32 v0, 5 ; GFX1032-NEXT: v_mov_b32_e32 v0, 5
; GFX1032-NEXT: v_mov_b32_e32 v1, 0 ; GFX1032-NEXT: v_mov_b32_e32 v1, 0
; GFX1032-NEXT: v_mov_b32_e32 v2, 0 ; GFX1032-NEXT: v_mov_b32_e32 v2, 0
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: ds_max_rtn_u64 v[0:1], v2, v[0:1] ; GFX1032-NEXT: ds_max_rtn_u64 v[0:1], v2, v[0:1]
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: BB22_2: ; GFX1032-NEXT: .LBB22_2:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX1032-NEXT: v_readfirstlane_b32 s2, v0 ; GFX1032-NEXT: v_readfirstlane_b32 s2, v0
; GFX1032-NEXT: v_readfirstlane_b32 s3, v1 ; GFX1032-NEXT: v_readfirstlane_b32 s3, v1
; GFX1032-NEXT: v_mov_b32_e32 v1, 0 ; GFX1032-NEXT: v_mov_b32_e32 v1, 0
; GFX1032-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc_lo ; GFX1032-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc_lo
; GFX1032-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[0:1] ; GFX1032-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[0:1]
; GFX1032-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo ; GFX1032-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
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; GFX8-NEXT: v_min_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX8-NEXT: v_min_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX8-NEXT: v_readlane_b32 s4, v2, 63 ; GFX8-NEXT: v_readlane_b32 s4, v2, 63
; GFX8-NEXT: s_nop 0 ; GFX8-NEXT: s_nop 0
; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf ; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX8-NEXT: s_mov_b64 exec, s[2:3] ; GFX8-NEXT: s_mov_b64 exec, s[2:3]
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX8-NEXT: ; implicit-def: $vgpr0 ; GFX8-NEXT: ; implicit-def: $vgpr0
; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX8-NEXT: s_cbranch_execz BB23_2 ; GFX8-NEXT: s_cbranch_execz .LBB23_2
; GFX8-NEXT: ; %bb.1: ; GFX8-NEXT: ; %bb.1:
; GFX8-NEXT: v_mov_b32_e32 v0, 0 ; GFX8-NEXT: v_mov_b32_e32 v0, 0
; GFX8-NEXT: v_mov_b32_e32 v3, s4 ; GFX8-NEXT: v_mov_b32_e32 v3, s4
; GFX8-NEXT: s_mov_b32 m0, -1 ; GFX8-NEXT: s_mov_b32 m0, -1
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: ds_min_rtn_u32 v0, v0, v3 ; GFX8-NEXT: ds_min_rtn_u32 v0, v0, v3
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: BB23_2: ; GFX8-NEXT: .LBB23_2:
; GFX8-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX8-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_readfirstlane_b32 s2, v0 ; GFX8-NEXT: v_readfirstlane_b32 s2, v0
; GFX8-NEXT: v_mov_b32_e32 v0, v1 ; GFX8-NEXT: v_mov_b32_e32 v0, v1
; GFX8-NEXT: v_min_u32_e32 v0, s2, v0 ; GFX8-NEXT: v_min_u32_e32 v0, s2, v0
; GFX8-NEXT: s_mov_b32 s3, 0xf000 ; GFX8-NEXT: s_mov_b32 s3, 0xf000
; GFX8-NEXT: s_mov_b32 s2, -1 ; GFX8-NEXT: s_mov_b32 s2, -1
; GFX8-NEXT: s_nop 0 ; GFX8-NEXT: s_nop 0
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; GFX9-NEXT: v_min_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX9-NEXT: v_min_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9-NEXT: v_readlane_b32 s4, v2, 63 ; GFX9-NEXT: v_readlane_b32 s4, v2, 63
; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: s_nop 0
; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf ; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX9-NEXT: s_mov_b64 exec, s[2:3] ; GFX9-NEXT: s_mov_b64 exec, s[2:3]
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-NEXT: ; implicit-def: $vgpr0 ; GFX9-NEXT: ; implicit-def: $vgpr0
; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-NEXT: s_cbranch_execz BB23_2 ; GFX9-NEXT: s_cbranch_execz .LBB23_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v3, s4 ; GFX9-NEXT: v_mov_b32_e32 v3, s4
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: ds_min_rtn_u32 v0, v0, v3 ; GFX9-NEXT: ds_min_rtn_u32 v0, v0, v3
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: BB23_2: ; GFX9-NEXT: .LBB23_2:
; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX9-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s2, v0 ; GFX9-NEXT: v_readfirstlane_b32 s2, v0
; GFX9-NEXT: v_mov_b32_e32 v0, v1 ; GFX9-NEXT: v_mov_b32_e32 v0, v1
; GFX9-NEXT: v_min_u32_e32 v0, s2, v0 ; GFX9-NEXT: v_min_u32_e32 v0, s2, v0
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: s_nop 0
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; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1064-NEXT: s_or_saveexec_b64 s[4:5], -1 ; GFX1064-NEXT: s_or_saveexec_b64 s[4:5], -1
; GFX1064-NEXT: v_writelane_b32 v3, s6, 48 ; GFX1064-NEXT: v_writelane_b32 v3, s6, 48
; GFX1064-NEXT: s_mov_b64 exec, s[4:5] ; GFX1064-NEXT: s_mov_b64 exec, s[4:5]
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: s_mov_b32 s2, -1 ; GFX1064-NEXT: s_mov_b32 s2, -1
; GFX1064-NEXT: ; implicit-def: $vgpr0 ; GFX1064-NEXT: ; implicit-def: $vgpr0
; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX1064-NEXT: s_cbranch_execz BB23_2 ; GFX1064-NEXT: s_cbranch_execz .LBB23_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: v_mov_b32_e32 v0, 0 ; GFX1064-NEXT: v_mov_b32_e32 v0, 0
; GFX1064-NEXT: v_mov_b32_e32 v4, s7 ; GFX1064-NEXT: v_mov_b32_e32 v4, s7
; GFX1064-NEXT: s_mov_b32 s3, s7 ; GFX1064-NEXT: s_mov_b32 s3, s7
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: ds_min_rtn_u32 v0, v0, v4 ; GFX1064-NEXT: ds_min_rtn_u32 v0, v0, v4
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: BB23_2: ; GFX1064-NEXT: .LBB23_2:
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX1064-NEXT: v_readfirstlane_b32 s3, v0 ; GFX1064-NEXT: v_readfirstlane_b32 s3, v0
; GFX1064-NEXT: v_mov_b32_e32 v0, v3 ; GFX1064-NEXT: v_mov_b32_e32 v0, v3
; GFX1064-NEXT: v_min_u32_e32 v0, s3, v0 ; GFX1064-NEXT: v_min_u32_e32 v0, s3, v0
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1032-NEXT: s_or_saveexec_b32 s2, -1 ; GFX1032-NEXT: s_or_saveexec_b32 s2, -1
; GFX1032-NEXT: v_writelane_b32 v3, s3, 16 ; GFX1032-NEXT: v_writelane_b32 v3, s3, 16
; GFX1032-NEXT: s_mov_b32 exec_lo, s2 ; GFX1032-NEXT: s_mov_b32 exec_lo, s2
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: s_mov_b32 s2, -1 ; GFX1032-NEXT: s_mov_b32 s2, -1
; GFX1032-NEXT: ; implicit-def: $vgpr0 ; GFX1032-NEXT: ; implicit-def: $vgpr0
; GFX1032-NEXT: s_and_saveexec_b32 s3, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s3, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB23_2 ; GFX1032-NEXT: s_cbranch_execz .LBB23_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: v_mov_b32_e32 v0, 0 ; GFX1032-NEXT: v_mov_b32_e32 v0, 0
; GFX1032-NEXT: v_mov_b32_e32 v4, s4 ; GFX1032-NEXT: v_mov_b32_e32 v4, s4
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: ds_min_rtn_u32 v0, v0, v4 ; GFX1032-NEXT: ds_min_rtn_u32 v0, v0, v4
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: BB23_2: ; GFX1032-NEXT: .LBB23_2:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s3 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s3
; GFX1032-NEXT: v_readfirstlane_b32 s3, v0 ; GFX1032-NEXT: v_readfirstlane_b32 s3, v0
; GFX1032-NEXT: v_mov_b32_e32 v0, v3 ; GFX1032-NEXT: v_mov_b32_e32 v0, v3
; GFX1032-NEXT: v_min_u32_e32 v0, s3, v0 ; GFX1032-NEXT: v_min_u32_e32 v0, s3, v0
; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s3, 0x31016000
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX7LESS-LABEL: umin_i64_constant: ; GFX7LESS-LABEL: umin_i64_constant:
; GFX7LESS: ; %bb.0: ; %entry ; GFX7LESS: ; %bb.0: ; %entry
; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0 ; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, exec_hi, v0 ; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, exec_hi, v0
; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX7LESS-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX7LESS-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX7LESS-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX7LESS-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX7LESS-NEXT: s_cbranch_execz BB24_2 ; GFX7LESS-NEXT: s_cbranch_execz .LBB24_2
; GFX7LESS-NEXT: ; %bb.1: ; GFX7LESS-NEXT: ; %bb.1:
; GFX7LESS-NEXT: v_mov_b32_e32 v2, 0 ; GFX7LESS-NEXT: v_mov_b32_e32 v2, 0
; GFX7LESS-NEXT: v_mov_b32_e32 v0, 5 ; GFX7LESS-NEXT: v_mov_b32_e32 v0, 5
; GFX7LESS-NEXT: v_mov_b32_e32 v1, 0 ; GFX7LESS-NEXT: v_mov_b32_e32 v1, 0
; GFX7LESS-NEXT: s_mov_b32 m0, -1 ; GFX7LESS-NEXT: s_mov_b32 m0, -1
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: ds_min_rtn_u64 v[0:1], v2, v[0:1] ; GFX7LESS-NEXT: ds_min_rtn_u64 v[0:1], v2, v[0:1]
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: BB24_2: ; GFX7LESS-NEXT: .LBB24_2:
; GFX7LESS-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX7LESS-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) ; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: v_readfirstlane_b32 s4, v0 ; GFX7LESS-NEXT: v_readfirstlane_b32 s4, v0
; GFX7LESS-NEXT: v_readfirstlane_b32 s5, v1 ; GFX7LESS-NEXT: v_readfirstlane_b32 s5, v1
; GFX7LESS-NEXT: s_mov_b32 s2, -1 ; GFX7LESS-NEXT: s_mov_b32 s2, -1
; GFX7LESS-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc ; GFX7LESS-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc
; GFX7LESS-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc ; GFX7LESS-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc
; GFX7LESS-NEXT: v_mov_b32_e32 v2, s5 ; GFX7LESS-NEXT: v_mov_b32_e32 v2, s5
; GFX7LESS-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[0:1] ; GFX7LESS-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[0:1]
; GFX7LESS-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; GFX7LESS-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX7LESS-NEXT: v_mov_b32_e32 v2, s4 ; GFX7LESS-NEXT: v_mov_b32_e32 v2, s4
; GFX7LESS-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX7LESS-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000 ; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000
; GFX7LESS-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX7LESS-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX7LESS-NEXT: s_endpgm ; GFX7LESS-NEXT: s_endpgm
; ;
; GFX8-LABEL: umin_i64_constant: ; GFX8-LABEL: umin_i64_constant:
; GFX8: ; %bb.0: ; %entry ; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX8-NEXT: s_cbranch_execz BB24_2 ; GFX8-NEXT: s_cbranch_execz .LBB24_2
; GFX8-NEXT: ; %bb.1: ; GFX8-NEXT: ; %bb.1:
; GFX8-NEXT: v_mov_b32_e32 v0, 5 ; GFX8-NEXT: v_mov_b32_e32 v0, 5
; GFX8-NEXT: v_mov_b32_e32 v2, 0 ; GFX8-NEXT: v_mov_b32_e32 v2, 0
; GFX8-NEXT: v_mov_b32_e32 v1, 0 ; GFX8-NEXT: v_mov_b32_e32 v1, 0
; GFX8-NEXT: s_mov_b32 m0, -1 ; GFX8-NEXT: s_mov_b32 m0, -1
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: ds_min_rtn_u64 v[0:1], v2, v[0:1] ; GFX8-NEXT: ds_min_rtn_u64 v[0:1], v2, v[0:1]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: BB24_2: ; GFX8-NEXT: .LBB24_2:
; GFX8-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX8-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_readfirstlane_b32 s4, v0 ; GFX8-NEXT: v_readfirstlane_b32 s4, v0
; GFX8-NEXT: v_readfirstlane_b32 s5, v1 ; GFX8-NEXT: v_readfirstlane_b32 s5, v1
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc
; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[0:1] ; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[0:1]
; GFX8-NEXT: v_mov_b32_e32 v2, s5 ; GFX8-NEXT: v_mov_b32_e32 v2, s5
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX8-NEXT: v_mov_b32_e32 v2, s4 ; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: s_mov_b32 s2, -1 ; GFX8-NEXT: s_mov_b32 s2, -1
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX8-NEXT: s_mov_b32 s3, 0xf000 ; GFX8-NEXT: s_mov_b32 s3, 0xf000
; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-LABEL: umin_i64_constant: ; GFX9-LABEL: umin_i64_constant:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-NEXT: s_cbranch_execz BB24_2 ; GFX9-NEXT: s_cbranch_execz .LBB24_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: v_mov_b32_e32 v0, 5 ; GFX9-NEXT: v_mov_b32_e32 v0, 5
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: ds_min_rtn_u64 v[0:1], v2, v[0:1] ; GFX9-NEXT: ds_min_rtn_u64 v[0:1], v2, v[0:1]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: BB24_2: ; GFX9-NEXT: .LBB24_2:
; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX9-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s4, v0 ; GFX9-NEXT: v_readfirstlane_b32 s4, v0
; GFX9-NEXT: v_readfirstlane_b32 s5, v1 ; GFX9-NEXT: v_readfirstlane_b32 s5, v1
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[0:1] ; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[0:1]
; GFX9-NEXT: v_mov_b32_e32 v2, s5 ; GFX9-NEXT: v_mov_b32_e32 v2, s5
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX9-NEXT: v_mov_b32_e32 v2, s4 ; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX1064-LABEL: umin_i64_constant: ; GFX1064-LABEL: umin_i64_constant:
; GFX1064: ; %bb.0: ; %entry ; GFX1064: ; %bb.0: ; %entry
; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX1064-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX1064-NEXT: s_cbranch_execz BB24_2 ; GFX1064-NEXT: s_cbranch_execz .LBB24_2
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: v_mov_b32_e32 v0, 5 ; GFX1064-NEXT: v_mov_b32_e32 v0, 5
; GFX1064-NEXT: v_mov_b32_e32 v1, 0 ; GFX1064-NEXT: v_mov_b32_e32 v1, 0
; GFX1064-NEXT: v_mov_b32_e32 v2, 0 ; GFX1064-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1064-NEXT: ds_min_rtn_u64 v[0:1], v2, v[0:1] ; GFX1064-NEXT: ds_min_rtn_u64 v[0:1], v2, v[0:1]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv ; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: BB24_2: ; GFX1064-NEXT: .LBB24_2:
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX1064-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX1064-NEXT: v_readfirstlane_b32 s2, v0 ; GFX1064-NEXT: v_readfirstlane_b32 s2, v0
; GFX1064-NEXT: v_readfirstlane_b32 s3, v1 ; GFX1064-NEXT: v_readfirstlane_b32 s3, v1
; GFX1064-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc ; GFX1064-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc
; GFX1064-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc ; GFX1064-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc
; GFX1064-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1] ; GFX1064-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1]
; GFX1064-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc ; GFX1064-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc
; GFX1064-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc ; GFX1064-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc
; GFX1064-NEXT: s_mov_b32 s2, -1 ; GFX1064-NEXT: s_mov_b32 s2, -1
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: s_endpgm
; ;
; GFX1032-LABEL: umin_i64_constant: ; GFX1032-LABEL: umin_i64_constant:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX1032-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1032-NEXT: s_and_saveexec_b32 s2, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s2, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB24_2 ; GFX1032-NEXT: s_cbranch_execz .LBB24_2
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: v_mov_b32_e32 v0, 5 ; GFX1032-NEXT: v_mov_b32_e32 v0, 5
; GFX1032-NEXT: v_mov_b32_e32 v1, 0 ; GFX1032-NEXT: v_mov_b32_e32 v1, 0
; GFX1032-NEXT: v_mov_b32_e32 v2, 0 ; GFX1032-NEXT: v_mov_b32_e32 v2, 0
; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1032-NEXT: ds_min_rtn_u64 v[0:1], v2, v[0:1] ; GFX1032-NEXT: ds_min_rtn_u64 v[0:1], v2, v[0:1]
; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv ; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: BB24_2: ; GFX1032-NEXT: .LBB24_2:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX1032-NEXT: v_readfirstlane_b32 s2, v0 ; GFX1032-NEXT: v_readfirstlane_b32 s2, v0
; GFX1032-NEXT: v_readfirstlane_b32 s3, v1 ; GFX1032-NEXT: v_readfirstlane_b32 s3, v1
; GFX1032-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo ; GFX1032-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX1032-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc_lo ; GFX1032-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc_lo
; GFX1032-NEXT: v_cmp_lt_u64_e32 vcc_lo, s[2:3], v[0:1] ; GFX1032-NEXT: v_cmp_lt_u64_e32 vcc_lo, s[2:3], v[0:1]
; GFX1032-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc_lo ; GFX1032-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc_lo
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llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll

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; Show what the atomic optimization pass will do for raw buffers. ; Show what the atomic optimization pass will do for raw buffers.
define amdgpu_ps void @add_i32_constant(<4 x i32> inreg %out, <4 x i32> inreg %inout) { define amdgpu_ps void @add_i32_constant(<4 x i32> inreg %out, <4 x i32> inreg %inout) {
; GFX7-LABEL: add_i32_constant: ; GFX7-LABEL: add_i32_constant:
; GFX7: ; %bb.0: ; %entry ; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_mov_b64 s[10:11], exec ; GFX7-NEXT: s_mov_b64 s[10:11], exec
; GFX7-NEXT: ; implicit-def: $vgpr0 ; GFX7-NEXT: ; implicit-def: $vgpr0
; GFX7-NEXT: s_and_saveexec_b64 s[8:9], s[10:11] ; GFX7-NEXT: s_and_saveexec_b64 s[8:9], s[10:11]
; GFX7-NEXT: s_cbranch_execz BB0_4 ; GFX7-NEXT: s_cbranch_execz .LBB0_4
; GFX7-NEXT: ; %bb.1: ; GFX7-NEXT: ; %bb.1:
; GFX7-NEXT: s_mov_b64 s[12:13], exec ; GFX7-NEXT: s_mov_b64 s[12:13], exec
; GFX7-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s12, 0 ; GFX7-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s12, 0
; GFX7-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s13, v0 ; GFX7-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s13, v0
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX7-NEXT: ; implicit-def: $vgpr1 ; GFX7-NEXT: ; implicit-def: $vgpr1
; GFX7-NEXT: s_and_saveexec_b64 s[10:11], vcc ; GFX7-NEXT: s_and_saveexec_b64 s[10:11], vcc
; GFX7-NEXT: s_cbranch_execz BB0_3 ; GFX7-NEXT: s_cbranch_execz .LBB0_3
; GFX7-NEXT: ; %bb.2: ; GFX7-NEXT: ; %bb.2:
; GFX7-NEXT: s_bcnt1_i32_b64 s12, s[12:13] ; GFX7-NEXT: s_bcnt1_i32_b64 s12, s[12:13]
; GFX7-NEXT: s_mul_i32 s12, s12, 5 ; GFX7-NEXT: s_mul_i32 s12, s12, 5
; GFX7-NEXT: v_mov_b32_e32 v1, s12 ; GFX7-NEXT: v_mov_b32_e32 v1, s12
; GFX7-NEXT: buffer_atomic_add v1, off, s[4:7], 0 glc ; GFX7-NEXT: buffer_atomic_add v1, off, s[4:7], 0 glc
; GFX7-NEXT: BB0_3: ; GFX7-NEXT: .LBB0_3:
; GFX7-NEXT: s_or_b64 exec, exec, s[10:11] ; GFX7-NEXT: s_or_b64 exec, exec, s[10:11]
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_readfirstlane_b32 s4, v1 ; GFX7-NEXT: v_readfirstlane_b32 s4, v1
; GFX7-NEXT: v_mad_u32_u24 v0, v0, 5, s4 ; GFX7-NEXT: v_mad_u32_u24 v0, v0, 5, s4
; GFX7-NEXT: BB0_4: ; %Flow ; GFX7-NEXT: .LBB0_4: ; %Flow
; GFX7-NEXT: s_or_b64 exec, exec, s[8:9] ; GFX7-NEXT: s_or_b64 exec, exec, s[8:9]
; GFX7-NEXT: s_wqm_b64 s[4:5], -1 ; GFX7-NEXT: s_wqm_b64 s[4:5], -1
; GFX7-NEXT: s_andn2_b64 vcc, exec, s[4:5] ; GFX7-NEXT: s_andn2_b64 vcc, exec, s[4:5]
; GFX7-NEXT: s_cbranch_vccnz BB0_6 ; GFX7-NEXT: s_cbranch_vccnz .LBB0_6
; GFX7-NEXT: ; %bb.5: ; %if ; GFX7-NEXT: ; %bb.5: ; %if
; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7-NEXT: BB0_6: ; %UnifiedReturnBlock ; GFX7-NEXT: .LBB0_6: ; %UnifiedReturnBlock
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX89-LABEL: add_i32_constant: ; GFX89-LABEL: add_i32_constant:
; GFX89: ; %bb.0: ; %entry ; GFX89: ; %bb.0: ; %entry
; GFX89-NEXT: s_mov_b64 s[10:11], exec ; GFX89-NEXT: s_mov_b64 s[10:11], exec
; GFX89-NEXT: ; implicit-def: $vgpr0 ; GFX89-NEXT: ; implicit-def: $vgpr0
; GFX89-NEXT: s_and_saveexec_b64 s[8:9], s[10:11] ; GFX89-NEXT: s_and_saveexec_b64 s[8:9], s[10:11]
; GFX89-NEXT: s_cbranch_execz BB0_4 ; GFX89-NEXT: s_cbranch_execz .LBB0_4
; GFX89-NEXT: ; %bb.1: ; GFX89-NEXT: ; %bb.1:
; GFX89-NEXT: s_mov_b64 s[12:13], exec ; GFX89-NEXT: s_mov_b64 s[12:13], exec
; GFX89-NEXT: v_mbcnt_lo_u32_b32 v0, s12, 0 ; GFX89-NEXT: v_mbcnt_lo_u32_b32 v0, s12, 0
; GFX89-NEXT: v_mbcnt_hi_u32_b32 v0, s13, v0 ; GFX89-NEXT: v_mbcnt_hi_u32_b32 v0, s13, v0
; GFX89-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX89-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX89-NEXT: ; implicit-def: $vgpr1 ; GFX89-NEXT: ; implicit-def: $vgpr1
; GFX89-NEXT: s_and_saveexec_b64 s[10:11], vcc ; GFX89-NEXT: s_and_saveexec_b64 s[10:11], vcc
; GFX89-NEXT: s_cbranch_execz BB0_3 ; GFX89-NEXT: s_cbranch_execz .LBB0_3
; GFX89-NEXT: ; %bb.2: ; GFX89-NEXT: ; %bb.2:
; GFX89-NEXT: s_bcnt1_i32_b64 s12, s[12:13] ; GFX89-NEXT: s_bcnt1_i32_b64 s12, s[12:13]
; GFX89-NEXT: s_mul_i32 s12, s12, 5 ; GFX89-NEXT: s_mul_i32 s12, s12, 5
; GFX89-NEXT: v_mov_b32_e32 v1, s12 ; GFX89-NEXT: v_mov_b32_e32 v1, s12
; GFX89-NEXT: buffer_atomic_add v1, off, s[4:7], 0 glc ; GFX89-NEXT: buffer_atomic_add v1, off, s[4:7], 0 glc
; GFX89-NEXT: BB0_3: ; GFX89-NEXT: .LBB0_3:
; GFX89-NEXT: s_or_b64 exec, exec, s[10:11] ; GFX89-NEXT: s_or_b64 exec, exec, s[10:11]
; GFX89-NEXT: s_waitcnt vmcnt(0) ; GFX89-NEXT: s_waitcnt vmcnt(0)
; GFX89-NEXT: v_readfirstlane_b32 s4, v1 ; GFX89-NEXT: v_readfirstlane_b32 s4, v1
; GFX89-NEXT: v_mad_u32_u24 v0, v0, 5, s4 ; GFX89-NEXT: v_mad_u32_u24 v0, v0, 5, s4
; GFX89-NEXT: BB0_4: ; %Flow ; GFX89-NEXT: .LBB0_4: ; %Flow
; GFX89-NEXT: s_or_b64 exec, exec, s[8:9] ; GFX89-NEXT: s_or_b64 exec, exec, s[8:9]
; GFX89-NEXT: s_wqm_b64 s[4:5], -1 ; GFX89-NEXT: s_wqm_b64 s[4:5], -1
; GFX89-NEXT: s_andn2_b64 vcc, exec, s[4:5] ; GFX89-NEXT: s_andn2_b64 vcc, exec, s[4:5]
; GFX89-NEXT: s_cbranch_vccnz BB0_6 ; GFX89-NEXT: s_cbranch_vccnz .LBB0_6
; GFX89-NEXT: ; %bb.5: ; %if ; GFX89-NEXT: ; %bb.5: ; %if
; GFX89-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX89-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX89-NEXT: BB0_6: ; %UnifiedReturnBlock ; GFX89-NEXT: .LBB0_6: ; %UnifiedReturnBlock
; GFX89-NEXT: s_endpgm ; GFX89-NEXT: s_endpgm
; ;
; GFX1064-LABEL: add_i32_constant: ; GFX1064-LABEL: add_i32_constant:
; GFX1064: ; %bb.0: ; %entry ; GFX1064: ; %bb.0: ; %entry
; GFX1064-NEXT: s_mov_b64 s[10:11], exec ; GFX1064-NEXT: s_mov_b64 s[10:11], exec
; GFX1064-NEXT: ; implicit-def: $vgpr0 ; GFX1064-NEXT: ; implicit-def: $vgpr0
; GFX1064-NEXT: s_and_saveexec_b64 s[8:9], s[10:11] ; GFX1064-NEXT: s_and_saveexec_b64 s[8:9], s[10:11]
; GFX1064-NEXT: s_cbranch_execz BB0_4 ; GFX1064-NEXT: s_cbranch_execz .LBB0_4
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: s_mov_b64 s[12:13], exec ; GFX1064-NEXT: s_mov_b64 s[12:13], exec
; GFX1064-NEXT: ; implicit-def: $vgpr1 ; GFX1064-NEXT: ; implicit-def: $vgpr1
; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s12, 0 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, s12, 0
; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, s13, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, s13, v0
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: s_and_saveexec_b64 s[10:11], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[10:11], vcc
; GFX1064-NEXT: s_cbranch_execz BB0_3 ; GFX1064-NEXT: s_cbranch_execz .LBB0_3
; GFX1064-NEXT: ; %bb.2: ; GFX1064-NEXT: ; %bb.2:
; GFX1064-NEXT: s_bcnt1_i32_b64 s12, s[12:13] ; GFX1064-NEXT: s_bcnt1_i32_b64 s12, s[12:13]
; GFX1064-NEXT: s_mul_i32 s12, s12, 5 ; GFX1064-NEXT: s_mul_i32 s12, s12, 5
; GFX1064-NEXT: v_mov_b32_e32 v1, s12 ; GFX1064-NEXT: v_mov_b32_e32 v1, s12
; GFX1064-NEXT: buffer_atomic_add v1, off, s[4:7], 0 glc ; GFX1064-NEXT: buffer_atomic_add v1, off, s[4:7], 0 glc
; GFX1064-NEXT: BB0_3: ; GFX1064-NEXT: .LBB0_3:
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[10:11] ; GFX1064-NEXT: s_or_b64 exec, exec, s[10:11]
; GFX1064-NEXT: s_waitcnt vmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0)
; GFX1064-NEXT: v_readfirstlane_b32 s4, v1 ; GFX1064-NEXT: v_readfirstlane_b32 s4, v1
; GFX1064-NEXT: v_mad_u32_u24 v0, v0, 5, s4 ; GFX1064-NEXT: v_mad_u32_u24 v0, v0, 5, s4
; GFX1064-NEXT: BB0_4: ; %Flow ; GFX1064-NEXT: .LBB0_4: ; %Flow
; GFX1064-NEXT: s_or_b64 exec, exec, s[8:9] ; GFX1064-NEXT: s_or_b64 exec, exec, s[8:9]
; GFX1064-NEXT: s_wqm_b64 s[4:5], -1 ; GFX1064-NEXT: s_wqm_b64 s[4:5], -1
; GFX1064-NEXT: s_andn2_b64 vcc, exec, s[4:5] ; GFX1064-NEXT: s_andn2_b64 vcc, exec, s[4:5]
; GFX1064-NEXT: s_cbranch_vccnz BB0_6 ; GFX1064-NEXT: s_cbranch_vccnz .LBB0_6
; GFX1064-NEXT: ; %bb.5: ; %if ; GFX1064-NEXT: ; %bb.5: ; %if
; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX1064-NEXT: BB0_6: ; %UnifiedReturnBlock ; GFX1064-NEXT: .LBB0_6: ; %UnifiedReturnBlock
; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: s_endpgm
; ;
; GFX1032-LABEL: add_i32_constant: ; GFX1032-LABEL: add_i32_constant:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_mov_b32 s9, exec_lo ; GFX1032-NEXT: s_mov_b32 s9, exec_lo
; GFX1032-NEXT: ; implicit-def: $vgpr0 ; GFX1032-NEXT: ; implicit-def: $vgpr0
; GFX1032-NEXT: s_and_saveexec_b32 s8, s9 ; GFX1032-NEXT: s_and_saveexec_b32 s8, s9
; GFX1032-NEXT: s_cbranch_execz BB0_4 ; GFX1032-NEXT: s_cbranch_execz .LBB0_4
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: s_mov_b32 s10, exec_lo ; GFX1032-NEXT: s_mov_b32 s10, exec_lo
; GFX1032-NEXT: ; implicit-def: $vgpr1 ; GFX1032-NEXT: ; implicit-def: $vgpr1
; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, s10, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, s10, 0
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: s_and_saveexec_b32 s9, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s9, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB0_3 ; GFX1032-NEXT: s_cbranch_execz .LBB0_3
; GFX1032-NEXT: ; %bb.2: ; GFX1032-NEXT: ; %bb.2:
; GFX1032-NEXT: s_bcnt1_i32_b32 s10, s10 ; GFX1032-NEXT: s_bcnt1_i32_b32 s10, s10
; GFX1032-NEXT: s_mul_i32 s10, s10, 5 ; GFX1032-NEXT: s_mul_i32 s10, s10, 5
; GFX1032-NEXT: v_mov_b32_e32 v1, s10 ; GFX1032-NEXT: v_mov_b32_e32 v1, s10
; GFX1032-NEXT: buffer_atomic_add v1, off, s[4:7], 0 glc ; GFX1032-NEXT: buffer_atomic_add v1, off, s[4:7], 0 glc
; GFX1032-NEXT: BB0_3: ; GFX1032-NEXT: .LBB0_3:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s9 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s9
; GFX1032-NEXT: s_waitcnt vmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0)
; GFX1032-NEXT: v_readfirstlane_b32 s4, v1 ; GFX1032-NEXT: v_readfirstlane_b32 s4, v1
; GFX1032-NEXT: v_mad_u32_u24 v0, v0, 5, s4 ; GFX1032-NEXT: v_mad_u32_u24 v0, v0, 5, s4
; GFX1032-NEXT: BB0_4: ; %Flow ; GFX1032-NEXT: .LBB0_4: ; %Flow
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s8 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s8
; GFX1032-NEXT: s_wqm_b32 s4, -1 ; GFX1032-NEXT: s_wqm_b32 s4, -1
; GFX1032-NEXT: s_andn2_b32 vcc_lo, exec_lo, s4 ; GFX1032-NEXT: s_andn2_b32 vcc_lo, exec_lo, s4
; GFX1032-NEXT: s_cbranch_vccnz BB0_6 ; GFX1032-NEXT: s_cbranch_vccnz .LBB0_6
; GFX1032-NEXT: ; %bb.5: ; %if ; GFX1032-NEXT: ; %bb.5: ; %if
; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX1032-NEXT: BB0_6: ; %UnifiedReturnBlock ; GFX1032-NEXT: .LBB0_6: ; %UnifiedReturnBlock
; GFX1032-NEXT: s_endpgm ; GFX1032-NEXT: s_endpgm
entry: entry:
%cond1 = call i1 @llvm.amdgcn.wqm.vote(i1 true) %cond1 = call i1 @llvm.amdgcn.wqm.vote(i1 true)
%old = call i32 @llvm.amdgcn.raw.buffer.atomic.add(i32 5, <4 x i32> %inout, i32 0, i32 0, i32 0) %old = call i32 @llvm.amdgcn.raw.buffer.atomic.add(i32 5, <4 x i32> %inout, i32 0, i32 0, i32 0)
%cond2 = call i1 @llvm.amdgcn.wqm.vote(i1 true) %cond2 = call i1 @llvm.amdgcn.wqm.vote(i1 true)
%cond = and i1 %cond1, %cond2 %cond = and i1 %cond1, %cond2
br i1 %cond, label %if, label %else br i1 %cond, label %if, label %else
if: if:
%bitcast = bitcast i32 %old to float %bitcast = bitcast i32 %old to float
call void @llvm.amdgcn.raw.buffer.store.f32(float %bitcast, <4 x i32> %out, i32 0, i32 0, i32 0) call void @llvm.amdgcn.raw.buffer.store.f32(float %bitcast, <4 x i32> %out, i32 0, i32 0, i32 0)
ret void ret void
else: else:
ret void ret void
} }
define amdgpu_ps void @add_i32_varying(<4 x i32> inreg %out, <4 x i32> inreg %inout, i32 %val) { define amdgpu_ps void @add_i32_varying(<4 x i32> inreg %out, <4 x i32> inreg %inout, i32 %val) {
; GFX7-LABEL: add_i32_varying: ; GFX7-LABEL: add_i32_varying:
; GFX7: ; %bb.0: ; %entry ; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_wqm_b64 s[8:9], -1 ; GFX7-NEXT: s_wqm_b64 s[8:9], -1
; GFX7-NEXT: buffer_atomic_add v0, off, s[4:7], 0 glc ; GFX7-NEXT: buffer_atomic_add v0, off, s[4:7], 0 glc
; GFX7-NEXT: s_andn2_b64 vcc, exec, s[8:9] ; GFX7-NEXT: s_andn2_b64 vcc, exec, s[8:9]
; GFX7-NEXT: s_cbranch_vccnz BB1_2 ; GFX7-NEXT: s_cbranch_vccnz .LBB1_2
; GFX7-NEXT: ; %bb.1: ; %if ; GFX7-NEXT: ; %bb.1: ; %if
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7-NEXT: BB1_2: ; %else ; GFX7-NEXT: .LBB1_2: ; %else
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX8-LABEL: add_i32_varying: ; GFX8-LABEL: add_i32_varying:
; GFX8: ; %bb.0: ; %entry ; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_mov_b64 s[8:9], exec ; GFX8-NEXT: s_mov_b64 s[8:9], exec
; GFX8-NEXT: s_mov_b64 s[10:11], s[8:9] ; GFX8-NEXT: s_mov_b64 s[10:11], s[8:9]
; GFX8-NEXT: v_mov_b32_e32 v2, v0 ; GFX8-NEXT: v_mov_b32_e32 v2, v0
; GFX8-NEXT: ; implicit-def: $vgpr0 ; GFX8-NEXT: ; implicit-def: $vgpr0
; GFX8-NEXT: s_and_saveexec_b64 s[8:9], s[10:11] ; GFX8-NEXT: s_and_saveexec_b64 s[8:9], s[10:11]
; GFX8-NEXT: s_cbranch_execz BB1_4 ; GFX8-NEXT: s_cbranch_execz .LBB1_4
; GFX8-NEXT: ; %bb.1: ; GFX8-NEXT: ; %bb.1:
; GFX8-NEXT: s_or_saveexec_b64 s[10:11], -1 ; GFX8-NEXT: s_or_saveexec_b64 s[10:11], -1
; GFX8-NEXT: v_mov_b32_e32 v1, 0 ; GFX8-NEXT: v_mov_b32_e32 v1, 0
; GFX8-NEXT: s_mov_b64 exec, s[10:11] ; GFX8-NEXT: s_mov_b64 exec, s[10:11]
; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX8-NEXT: s_not_b64 exec, exec ; GFX8-NEXT: s_not_b64 exec, exec
; GFX8-NEXT: v_mov_b32_e32 v2, 0 ; GFX8-NEXT: v_mov_b32_e32 v2, 0
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; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX8-NEXT: v_readlane_b32 s12, v2, 63 ; GFX8-NEXT: v_readlane_b32 s12, v2, 63
; GFX8-NEXT: s_nop 0 ; GFX8-NEXT: s_nop 0
; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf ; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX8-NEXT: s_mov_b64 exec, s[10:11] ; GFX8-NEXT: s_mov_b64 exec, s[10:11]
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX8-NEXT: ; implicit-def: $vgpr0 ; GFX8-NEXT: ; implicit-def: $vgpr0
; GFX8-NEXT: s_and_saveexec_b64 s[10:11], vcc ; GFX8-NEXT: s_and_saveexec_b64 s[10:11], vcc
; GFX8-NEXT: s_cbranch_execz BB1_3 ; GFX8-NEXT: s_cbranch_execz .LBB1_3
; GFX8-NEXT: ; %bb.2: ; GFX8-NEXT: ; %bb.2:
; GFX8-NEXT: v_mov_b32_e32 v0, s12 ; GFX8-NEXT: v_mov_b32_e32 v0, s12
; GFX8-NEXT: buffer_atomic_add v0, off, s[4:7], 0 glc ; GFX8-NEXT: buffer_atomic_add v0, off, s[4:7], 0 glc
; GFX8-NEXT: BB1_3: ; GFX8-NEXT: .LBB1_3:
; GFX8-NEXT: s_or_b64 exec, exec, s[10:11] ; GFX8-NEXT: s_or_b64 exec, exec, s[10:11]
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_readfirstlane_b32 s4, v0 ; GFX8-NEXT: v_readfirstlane_b32 s4, v0
; GFX8-NEXT: v_mov_b32_e32 v0, v1 ; GFX8-NEXT: v_mov_b32_e32 v0, v1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v0 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v0
; GFX8-NEXT: BB1_4: ; %Flow ; GFX8-NEXT: .LBB1_4: ; %Flow
; GFX8-NEXT: s_or_b64 exec, exec, s[8:9] ; GFX8-NEXT: s_or_b64 exec, exec, s[8:9]
; GFX8-NEXT: s_wqm_b64 s[4:5], -1 ; GFX8-NEXT: s_wqm_b64 s[4:5], -1
; GFX8-NEXT: s_andn2_b64 vcc, exec, s[4:5] ; GFX8-NEXT: s_andn2_b64 vcc, exec, s[4:5]
; GFX8-NEXT: s_cbranch_vccnz BB1_6 ; GFX8-NEXT: s_cbranch_vccnz .LBB1_6
; GFX8-NEXT: ; %bb.5: ; %if ; GFX8-NEXT: ; %bb.5: ; %if
; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX8-NEXT: BB1_6: ; %UnifiedReturnBlock ; GFX8-NEXT: .LBB1_6: ; %UnifiedReturnBlock
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-LABEL: add_i32_varying: ; GFX9-LABEL: add_i32_varying:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_mov_b64 s[8:9], exec ; GFX9-NEXT: s_mov_b64 s[8:9], exec
; GFX9-NEXT: s_mov_b64 s[10:11], s[8:9] ; GFX9-NEXT: s_mov_b64 s[10:11], s[8:9]
; GFX9-NEXT: v_mov_b32_e32 v2, v0 ; GFX9-NEXT: v_mov_b32_e32 v2, v0
; GFX9-NEXT: ; implicit-def: $vgpr0 ; GFX9-NEXT: ; implicit-def: $vgpr0
; GFX9-NEXT: s_and_saveexec_b64 s[8:9], s[10:11] ; GFX9-NEXT: s_and_saveexec_b64 s[8:9], s[10:11]
; GFX9-NEXT: s_cbranch_execz BB1_4 ; GFX9-NEXT: s_cbranch_execz .LBB1_4
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: s_or_saveexec_b64 s[10:11], -1 ; GFX9-NEXT: s_or_saveexec_b64 s[10:11], -1
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: s_mov_b64 exec, s[10:11] ; GFX9-NEXT: s_mov_b64 exec, s[10:11]
; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX9-NEXT: s_not_b64 exec, exec ; GFX9-NEXT: s_not_b64 exec, exec
; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
Show All 12 Lines
; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9-NEXT: v_readlane_b32 s12, v2, 63 ; GFX9-NEXT: v_readlane_b32 s12, v2, 63
; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: s_nop 0
; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf ; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX9-NEXT: s_mov_b64 exec, s[10:11] ; GFX9-NEXT: s_mov_b64 exec, s[10:11]
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-NEXT: ; implicit-def: $vgpr0 ; GFX9-NEXT: ; implicit-def: $vgpr0
; GFX9-NEXT: s_and_saveexec_b64 s[10:11], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[10:11], vcc
; GFX9-NEXT: s_cbranch_execz BB1_3 ; GFX9-NEXT: s_cbranch_execz .LBB1_3
; GFX9-NEXT: ; %bb.2: ; GFX9-NEXT: ; %bb.2:
; GFX9-NEXT: v_mov_b32_e32 v0, s12 ; GFX9-NEXT: v_mov_b32_e32 v0, s12
; GFX9-NEXT: buffer_atomic_add v0, off, s[4:7], 0 glc ; GFX9-NEXT: buffer_atomic_add v0, off, s[4:7], 0 glc
; GFX9-NEXT: BB1_3: ; GFX9-NEXT: .LBB1_3:
; GFX9-NEXT: s_or_b64 exec, exec, s[10:11] ; GFX9-NEXT: s_or_b64 exec, exec, s[10:11]
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s4, v0 ; GFX9-NEXT: v_readfirstlane_b32 s4, v0
; GFX9-NEXT: v_mov_b32_e32 v0, v1 ; GFX9-NEXT: v_mov_b32_e32 v0, v1
; GFX9-NEXT: v_add_u32_e32 v0, s4, v0 ; GFX9-NEXT: v_add_u32_e32 v0, s4, v0
; GFX9-NEXT: BB1_4: ; %Flow ; GFX9-NEXT: .LBB1_4: ; %Flow
; GFX9-NEXT: s_or_b64 exec, exec, s[8:9] ; GFX9-NEXT: s_or_b64 exec, exec, s[8:9]
; GFX9-NEXT: s_wqm_b64 s[4:5], -1 ; GFX9-NEXT: s_wqm_b64 s[4:5], -1
; GFX9-NEXT: s_andn2_b64 vcc, exec, s[4:5] ; GFX9-NEXT: s_andn2_b64 vcc, exec, s[4:5]
; GFX9-NEXT: s_cbranch_vccnz BB1_6 ; GFX9-NEXT: s_cbranch_vccnz .LBB1_6
; GFX9-NEXT: ; %bb.5: ; %if ; GFX9-NEXT: ; %bb.5: ; %if
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-NEXT: BB1_6: ; %UnifiedReturnBlock ; GFX9-NEXT: .LBB1_6: ; %UnifiedReturnBlock
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX1064-LABEL: add_i32_varying: ; GFX1064-LABEL: add_i32_varying:
; GFX1064: ; %bb.0: ; %entry ; GFX1064: ; %bb.0: ; %entry
; GFX1064-NEXT: s_mov_b64 s[8:9], exec ; GFX1064-NEXT: s_mov_b64 s[8:9], exec
; GFX1064-NEXT: v_mov_b32_e32 v1, v0 ; GFX1064-NEXT: v_mov_b32_e32 v1, v0
; GFX1064-NEXT: s_mov_b64 s[10:11], s[8:9] ; GFX1064-NEXT: s_mov_b64 s[10:11], s[8:9]
; GFX1064-NEXT: ; implicit-def: $vgpr0 ; GFX1064-NEXT: ; implicit-def: $vgpr0
; GFX1064-NEXT: s_and_saveexec_b64 s[8:9], s[10:11] ; GFX1064-NEXT: s_and_saveexec_b64 s[8:9], s[10:11]
; GFX1064-NEXT: s_cbranch_execz BB1_4 ; GFX1064-NEXT: s_cbranch_execz .LBB1_4
; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: s_not_b64 exec, exec ; GFX1064-NEXT: s_not_b64 exec, exec
; GFX1064-NEXT: v_mov_b32_e32 v1, 0 ; GFX1064-NEXT: v_mov_b32_e32 v1, 0
; GFX1064-NEXT: s_not_b64 exec, exec ; GFX1064-NEXT: s_not_b64 exec, exec
; GFX1064-NEXT: s_or_saveexec_b64 s[10:11], -1 ; GFX1064-NEXT: s_or_saveexec_b64 s[10:11], -1
; GFX1064-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX1064-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1064-NEXT: v_mov_b32_e32 v3, 0 ; GFX1064-NEXT: v_mov_b32_e32 v3, 0
; GFX1064-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX1064-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
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; GFX1064-NEXT: s_mov_b64 exec, s[10:11] ; GFX1064-NEXT: s_mov_b64 exec, s[10:11]
; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1064-NEXT: s_or_saveexec_b64 s[10:11], -1 ; GFX1064-NEXT: s_or_saveexec_b64 s[10:11], -1
; GFX1064-NEXT: v_writelane_b32 v3, s14, 48 ; GFX1064-NEXT: v_writelane_b32 v3, s14, 48
; GFX1064-NEXT: s_mov_b64 exec, s[10:11] ; GFX1064-NEXT: s_mov_b64 exec, s[10:11]
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064-NEXT: ; implicit-def: $vgpr0 ; GFX1064-NEXT: ; implicit-def: $vgpr0
; GFX1064-NEXT: s_and_saveexec_b64 s[10:11], vcc ; GFX1064-NEXT: s_and_saveexec_b64 s[10:11], vcc
; GFX1064-NEXT: s_cbranch_execz BB1_3 ; GFX1064-NEXT: s_cbranch_execz .LBB1_3
; GFX1064-NEXT: ; %bb.2: ; GFX1064-NEXT: ; %bb.2:
; GFX1064-NEXT: v_mov_b32_e32 v0, s12 ; GFX1064-NEXT: v_mov_b32_e32 v0, s12
; GFX1064-NEXT: buffer_atomic_add v0, off, s[4:7], 0 glc ; GFX1064-NEXT: buffer_atomic_add v0, off, s[4:7], 0 glc
; GFX1064-NEXT: BB1_3: ; GFX1064-NEXT: .LBB1_3:
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[10:11] ; GFX1064-NEXT: s_or_b64 exec, exec, s[10:11]
; GFX1064-NEXT: s_waitcnt vmcnt(0) ; GFX1064-NEXT: s_waitcnt vmcnt(0)
; GFX1064-NEXT: v_readfirstlane_b32 s4, v0 ; GFX1064-NEXT: v_readfirstlane_b32 s4, v0
; GFX1064-NEXT: v_mov_b32_e32 v0, v3 ; GFX1064-NEXT: v_mov_b32_e32 v0, v3
; GFX1064-NEXT: v_add_nc_u32_e32 v0, s4, v0 ; GFX1064-NEXT: v_add_nc_u32_e32 v0, s4, v0
; GFX1064-NEXT: BB1_4: ; %Flow ; GFX1064-NEXT: .LBB1_4: ; %Flow
; GFX1064-NEXT: s_or_b64 exec, exec, s[8:9] ; GFX1064-NEXT: s_or_b64 exec, exec, s[8:9]
; GFX1064-NEXT: s_wqm_b64 s[4:5], -1 ; GFX1064-NEXT: s_wqm_b64 s[4:5], -1
; GFX1064-NEXT: s_andn2_b64 vcc, exec, s[4:5] ; GFX1064-NEXT: s_andn2_b64 vcc, exec, s[4:5]
; GFX1064-NEXT: s_cbranch_vccnz BB1_6 ; GFX1064-NEXT: s_cbranch_vccnz .LBB1_6
; GFX1064-NEXT: ; %bb.5: ; %if ; GFX1064-NEXT: ; %bb.5: ; %if
; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX1064-NEXT: BB1_6: ; %UnifiedReturnBlock ; GFX1064-NEXT: .LBB1_6: ; %UnifiedReturnBlock
; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: s_endpgm
; ;
; GFX1032-LABEL: add_i32_varying: ; GFX1032-LABEL: add_i32_varying:
; GFX1032: ; %bb.0: ; %entry ; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_mov_b32 s8, exec_lo ; GFX1032-NEXT: s_mov_b32 s8, exec_lo
; GFX1032-NEXT: v_mov_b32_e32 v1, v0 ; GFX1032-NEXT: v_mov_b32_e32 v1, v0
; GFX1032-NEXT: s_mov_b32 s9, s8 ; GFX1032-NEXT: s_mov_b32 s9, s8
; GFX1032-NEXT: ; implicit-def: $vgpr0 ; GFX1032-NEXT: ; implicit-def: $vgpr0
; GFX1032-NEXT: s_and_saveexec_b32 s8, s9 ; GFX1032-NEXT: s_and_saveexec_b32 s8, s9
; GFX1032-NEXT: s_cbranch_execz BB1_4 ; GFX1032-NEXT: s_cbranch_execz .LBB1_4
; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo ; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo
; GFX1032-NEXT: v_mov_b32_e32 v1, 0 ; GFX1032-NEXT: v_mov_b32_e32 v1, 0
; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo ; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo
; GFX1032-NEXT: s_or_saveexec_b32 s9, -1 ; GFX1032-NEXT: s_or_saveexec_b32 s9, -1
; GFX1032-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX1032-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1032-NEXT: v_mov_b32_e32 v3, 0 ; GFX1032-NEXT: v_mov_b32_e32 v3, 0
; GFX1032-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX1032-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1032-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX1032-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1032-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX1032-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1032-NEXT: v_mov_b32_e32 v2, v1 ; GFX1032-NEXT: v_mov_b32_e32 v2, v1
; GFX1032-NEXT: v_permlanex16_b32 v2, v2, -1, -1 ; GFX1032-NEXT: v_permlanex16_b32 v2, v2, -1, -1
; GFX1032-NEXT: v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf ; GFX1032-NEXT: v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
; GFX1032-NEXT: v_readlane_b32 s11, v1, 31 ; GFX1032-NEXT: v_readlane_b32 s11, v1, 31
; GFX1032-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; GFX1032-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1032-NEXT: v_readlane_b32 s10, v1, 15 ; GFX1032-NEXT: v_readlane_b32 s10, v1, 15
; GFX1032-NEXT: s_mov_b32 exec_lo, s9 ; GFX1032-NEXT: s_mov_b32 exec_lo, s9
; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1032-NEXT: s_or_saveexec_b32 s9, -1 ; GFX1032-NEXT: s_or_saveexec_b32 s9, -1
; GFX1032-NEXT: v_writelane_b32 v3, s10, 16 ; GFX1032-NEXT: v_writelane_b32 v3, s10, 16
; GFX1032-NEXT: s_mov_b32 exec_lo, s9 ; GFX1032-NEXT: s_mov_b32 exec_lo, s9
; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: ; implicit-def: $vgpr0 ; GFX1032-NEXT: ; implicit-def: $vgpr0
; GFX1032-NEXT: s_and_saveexec_b32 s9, vcc_lo ; GFX1032-NEXT: s_and_saveexec_b32 s9, vcc_lo
; GFX1032-NEXT: s_cbranch_execz BB1_3 ; GFX1032-NEXT: s_cbranch_execz .LBB1_3
; GFX1032-NEXT: ; %bb.2: ; GFX1032-NEXT: ; %bb.2:
; GFX1032-NEXT: v_mov_b32_e32 v0, s11 ; GFX1032-NEXT: v_mov_b32_e32 v0, s11
; GFX1032-NEXT: s_mov_b32 s10, s11 ; GFX1032-NEXT: s_mov_b32 s10, s11
; GFX1032-NEXT: buffer_atomic_add v0, off, s[4:7], 0 glc ; GFX1032-NEXT: buffer_atomic_add v0, off, s[4:7], 0 glc
; GFX1032-NEXT: BB1_3: ; GFX1032-NEXT: .LBB1_3:
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s9 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s9
; GFX1032-NEXT: s_waitcnt vmcnt(0) ; GFX1032-NEXT: s_waitcnt vmcnt(0)
; GFX1032-NEXT: v_readfirstlane_b32 s4, v0 ; GFX1032-NEXT: v_readfirstlane_b32 s4, v0
; GFX1032-NEXT: v_mov_b32_e32 v0, v3 ; GFX1032-NEXT: v_mov_b32_e32 v0, v3
; GFX1032-NEXT: v_add_nc_u32_e32 v0, s4, v0 ; GFX1032-NEXT: v_add_nc_u32_e32 v0, s4, v0
; GFX1032-NEXT: BB1_4: ; %Flow ; GFX1032-NEXT: .LBB1_4: ; %Flow
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s8 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s8
; GFX1032-NEXT: s_wqm_b32 s4, -1 ; GFX1032-NEXT: s_wqm_b32 s4, -1
; GFX1032-NEXT: s_andn2_b32 vcc_lo, exec_lo, s4 ; GFX1032-NEXT: s_andn2_b32 vcc_lo, exec_lo, s4
; GFX1032-NEXT: s_cbranch_vccnz BB1_6 ; GFX1032-NEXT: s_cbranch_vccnz .LBB1_6
; GFX1032-NEXT: ; %bb.5: ; %if ; GFX1032-NEXT: ; %bb.5: ; %if
; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX1032-NEXT: BB1_6: ; %UnifiedReturnBlock ; GFX1032-NEXT: .LBB1_6: ; %UnifiedReturnBlock
; GFX1032-NEXT: s_endpgm ; GFX1032-NEXT: s_endpgm
entry: entry:
%cond1 = call i1 @llvm.amdgcn.wqm.vote(i1 true) %cond1 = call i1 @llvm.amdgcn.wqm.vote(i1 true)
%old = call i32 @llvm.amdgcn.raw.buffer.atomic.add(i32 %val, <4 x i32> %inout, i32 0, i32 0, i32 0) %old = call i32 @llvm.amdgcn.raw.buffer.atomic.add(i32 %val, <4 x i32> %inout, i32 0, i32 0, i32 0)
%cond2 = call i1 @llvm.amdgcn.wqm.vote(i1 true) %cond2 = call i1 @llvm.amdgcn.wqm.vote(i1 true)
%cond = and i1 %cond1, %cond2 %cond = and i1 %cond1, %cond2
br i1 %cond, label %if, label %else br i1 %cond, label %if, label %else
if: if:
%bitcast = bitcast i32 %old to float %bitcast = bitcast i32 %old to float
call void @llvm.amdgcn.raw.buffer.store.f32(float %bitcast, <4 x i32> %out, i32 0, i32 0, i32 0) call void @llvm.amdgcn.raw.buffer.store.f32(float %bitcast, <4 x i32> %out, i32 0, i32 0, i32 0)
ret void ret void
else: else:
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/atomicrmw-nand.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
define i32 @atomic_nand_i32_lds(i32 addrspace(3)* %ptr) nounwind { define i32 @atomic_nand_i32_lds(i32 addrspace(3)* %ptr) nounwind {
; GCN-LABEL: atomic_nand_i32_lds: ; GCN-LABEL: atomic_nand_i32_lds:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: ds_read_b32 v1, v0 ; GCN-NEXT: ds_read_b32 v1, v0
; GCN-NEXT: s_mov_b64 s[4:5], 0 ; GCN-NEXT: s_mov_b64 s[4:5], 0
; GCN-NEXT: BB0_1: ; %atomicrmw.start ; GCN-NEXT: .LBB0_1: ; %atomicrmw.start
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v2, v1 ; GCN-NEXT: v_mov_b32_e32 v2, v1
; GCN-NEXT: v_not_b32_e32 v1, v2 ; GCN-NEXT: v_not_b32_e32 v1, v2
; GCN-NEXT: v_or_b32_e32 v1, -5, v1 ; GCN-NEXT: v_or_b32_e32 v1, -5, v1
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: ds_cmpst_rtn_b32 v1, v0, v2, v1 ; GCN-NEXT: ds_cmpst_rtn_b32 v1, v0, v2, v1
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
; GCN-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GCN-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GCN-NEXT: s_andn2_b64 exec, exec, s[4:5] ; GCN-NEXT: s_andn2_b64 exec, exec, s[4:5]
; GCN-NEXT: s_cbranch_execnz BB0_1 ; GCN-NEXT: s_cbranch_execnz .LBB0_1
; GCN-NEXT: ; %bb.2: ; %atomicrmw.end ; GCN-NEXT: ; %bb.2: ; %atomicrmw.end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5] ; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v0, v1 ; GCN-NEXT: v_mov_b32_e32 v0, v1
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
%result = atomicrmw nand i32 addrspace(3)* %ptr, i32 4 seq_cst %result = atomicrmw nand i32 addrspace(3)* %ptr, i32 4 seq_cst
ret i32 %result ret i32 %result
} }
define i32 @atomic_nand_i32_global(i32 addrspace(1)* %ptr) nounwind { define i32 @atomic_nand_i32_global(i32 addrspace(1)* %ptr) nounwind {
; GCN-LABEL: atomic_nand_i32_global: ; GCN-LABEL: atomic_nand_i32_global:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: global_load_dword v2, v[0:1], off ; GCN-NEXT: global_load_dword v2, v[0:1], off
; GCN-NEXT: s_mov_b64 s[4:5], 0 ; GCN-NEXT: s_mov_b64 s[4:5], 0
; GCN-NEXT: BB1_1: ; %atomicrmw.start ; GCN-NEXT: .LBB1_1: ; %atomicrmw.start
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v3, v2 ; GCN-NEXT: v_mov_b32_e32 v3, v2
; GCN-NEXT: v_not_b32_e32 v2, v3 ; GCN-NEXT: v_not_b32_e32 v2, v3
; GCN-NEXT: v_or_b32_e32 v2, -5, v2 ; GCN-NEXT: v_or_b32_e32 v2, -5, v2
; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc ; GCN-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_wbinvl1_vol ; GCN-NEXT: buffer_wbinvl1_vol
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3
; GCN-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GCN-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GCN-NEXT: s_andn2_b64 exec, exec, s[4:5] ; GCN-NEXT: s_andn2_b64 exec, exec, s[4:5]
; GCN-NEXT: s_cbranch_execnz BB1_1 ; GCN-NEXT: s_cbranch_execnz .LBB1_1
; GCN-NEXT: ; %bb.2: ; %atomicrmw.end ; GCN-NEXT: ; %bb.2: ; %atomicrmw.end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5] ; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v0, v2 ; GCN-NEXT: v_mov_b32_e32 v0, v2
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
%result = atomicrmw nand i32 addrspace(1)* %ptr, i32 4 seq_cst %result = atomicrmw nand i32 addrspace(1)* %ptr, i32 4 seq_cst
ret i32 %result ret i32 %result
} }
define i32 @atomic_nand_i32_flat(i32* %ptr) nounwind { define i32 @atomic_nand_i32_flat(i32* %ptr) nounwind {
; GCN-LABEL: atomic_nand_i32_flat: ; GCN-LABEL: atomic_nand_i32_flat:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: flat_load_dword v2, v[0:1] ; GCN-NEXT: flat_load_dword v2, v[0:1]
; GCN-NEXT: s_mov_b64 s[4:5], 0 ; GCN-NEXT: s_mov_b64 s[4:5], 0
; GCN-NEXT: BB2_1: ; %atomicrmw.start ; GCN-NEXT: .LBB2_1: ; %atomicrmw.start
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v3, v2 ; GCN-NEXT: v_mov_b32_e32 v3, v2
; GCN-NEXT: v_not_b32_e32 v2, v3 ; GCN-NEXT: v_not_b32_e32 v2, v3
; GCN-NEXT: v_or_b32_e32 v2, -5, v2 ; GCN-NEXT: v_or_b32_e32 v2, -5, v2
; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc ; GCN-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN-NEXT: buffer_wbinvl1_vol ; GCN-NEXT: buffer_wbinvl1_vol
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3
; GCN-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GCN-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GCN-NEXT: s_andn2_b64 exec, exec, s[4:5] ; GCN-NEXT: s_andn2_b64 exec, exec, s[4:5]
; GCN-NEXT: s_cbranch_execnz BB2_1 ; GCN-NEXT: s_cbranch_execnz .LBB2_1
; GCN-NEXT: ; %bb.2: ; %atomicrmw.end ; GCN-NEXT: ; %bb.2: ; %atomicrmw.end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5] ; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v0, v2 ; GCN-NEXT: v_mov_b32_e32 v0, v2
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
%result = atomicrmw nand i32* %ptr, i32 4 seq_cst %result = atomicrmw nand i32* %ptr, i32 4 seq_cst
ret i32 %result ret i32 %result
} }

llvm/test/CodeGen/AMDGPU/basic-branch.ll

; RUN: llc -O0 -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCNNOOPT -check-prefix=GCN %s ; RUN: llc -O0 -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCNNOOPT -check-prefix=GCN %s
; RUN: llc -O0 -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCNNOOPT -check-prefix=GCN %s ; RUN: llc -O0 -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCNNOOPT -check-prefix=GCN %s
; RUN: llc -O0 -march=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global,-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCNNOOPT -check-prefix=GCN %s ; RUN: llc -O0 -march=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global,-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCNNOOPT -check-prefix=GCN %s
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCNOPT -check-prefix=GCN %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCNOPT -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCNOPT -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCNOPT -check-prefix=GCN %s
; GCN-LABEL: {{^}}test_branch: ; GCN-LABEL: {{^}}test_branch:
; GCNNOOPT: v_writelane_b32 ; GCNNOOPT: v_writelane_b32
; GCNNOOPT: v_writelane_b32 ; GCNNOOPT: v_writelane_b32
; GCN: s_cbranch_scc1 [[END:BB[0-9]+_[0-9]+]] ; GCN: s_cbranch_scc1 [[END:.LBB[0-9]+_[0-9]+]]
; GCNNOOPT: v_readlane_b32 ; GCNNOOPT: v_readlane_b32
; GCNNOOPT: v_readlane_b32 ; GCNNOOPT: v_readlane_b32
; GCN: buffer_store_dword ; GCN: buffer_store_dword
; GCNNOOPT: s_endpgm ; GCNNOOPT: s_endpgm
; GCN: {{^}}[[END]]: ; GCN: {{^}}[[END]]:
; GCN: s_endpgm ; GCN: s_endpgm
Show All 10 Lines
} }
; GCN-LABEL: {{^}}test_brcc_i1: ; GCN-LABEL: {{^}}test_brcc_i1:
; GCN: s_load_dword [[VAL:s[0-9]+]] ; GCN: s_load_dword [[VAL:s[0-9]+]]
; GCNNOOPT: s_mov_b32 [[ONE:s[0-9]+]], 1{{$}} ; GCNNOOPT: s_mov_b32 [[ONE:s[0-9]+]], 1{{$}}
; GCNNOOPT: s_and_b32 s{{[0-9]+}}, [[VAL]], [[ONE]] ; GCNNOOPT: s_and_b32 s{{[0-9]+}}, [[VAL]], [[ONE]]
; GCNOPT: s_bitcmp0_b32 [[VAL]], 0 ; GCNOPT: s_bitcmp0_b32 [[VAL]], 0
; GCNNOOPT: s_cmp_eq_u32 ; GCNNOOPT: s_cmp_eq_u32
; GCN: s_cbranch_scc1 [[END:BB[0-9]+_[0-9]+]] ; GCN: s_cbranch_scc1 [[END:.LBB[0-9]+_[0-9]+]]
; GCN: buffer_store_dword ; GCN: buffer_store_dword
; GCN: {{^}}[[END]]: ; GCN: {{^}}[[END]]:
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @test_brcc_i1(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in, i1 %val) #0 { define amdgpu_kernel void @test_brcc_i1(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in, i1 %val) #0 {
%cmp0 = icmp ne i1 %val, 0 %cmp0 = icmp ne i1 %val, 0
br i1 %cmp0, label %store, label %end br i1 %cmp0, label %store, label %end
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llvm/test/CodeGen/AMDGPU/branch-condition-and.ll

; RUN: llc -march=amdgcn -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s
; This used to crash because during intermediate control flow lowering, there ; This used to crash because during intermediate control flow lowering, there
; was a sequence ; was a sequence
; s_mov_b64 s[0:1], exec ; s_mov_b64 s[0:1], exec
; s_and_b64 s[2:3], s[0:1], s[2:3] ; def & use of the same register pair ; s_and_b64 s[2:3], s[0:1], s[2:3] ; def & use of the same register pair
; ... ; ...
; s_mov_b64_term exec, s[2:3] ; s_mov_b64_term exec, s[2:3]
; that was not treated correctly. ; that was not treated correctly.
; ;
; GCN-LABEL: {{^}}ham: ; GCN-LABEL: {{^}}ham:
; GCN-DAG: v_cmp_lt_f32_e64 [[OTHERCC:s\[[0-9]+:[0-9]+\]]], ; GCN-DAG: v_cmp_lt_f32_e64 [[OTHERCC:s\[[0-9]+:[0-9]+\]]],
; GCN-DAG: v_cmp_lt_f32_e32 vcc, ; GCN-DAG: v_cmp_lt_f32_e32 vcc,
; GCN: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[OTHERCC]] ; GCN: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[OTHERCC]]
; GCN: s_and_saveexec_b64 [[SAVED:s\[[0-9]+:[0-9]+\]]], [[AND]] ; GCN: s_and_saveexec_b64 [[SAVED:s\[[0-9]+:[0-9]+\]]], [[AND]]
; GCN-NEXT: s_cbranch_execz BB0_{{[0-9]+}} ; GCN-NEXT: s_cbranch_execz .LBB0_{{[0-9]+}}
; GCN-NEXT: ; %bb.{{[0-9]+}}: ; %bb4 ; GCN-NEXT: ; %bb.{{[0-9]+}}: ; %bb4
; GCN: ds_write_b32 ; GCN: ds_write_b32
; GCN: BB0_{{[0-9]+}}: ; %UnifiedReturnBlock ; GCN: .LBB0_{{[0-9]+}}: ; %UnifiedReturnBlock
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; GCN-NEXT: .Lfunc_end ; GCN-NEXT: .Lfunc_end
define amdgpu_ps void @ham(float %arg, float %arg1) #0 { define amdgpu_ps void @ham(float %arg, float %arg1) #0 {
bb: bb:
%tmp = fcmp ogt float %arg, 0.000000e+00 %tmp = fcmp ogt float %arg, 0.000000e+00
%tmp2 = fcmp ogt float %arg1, 0.000000e+00 %tmp2 = fcmp ogt float %arg1, 0.000000e+00
%tmp3 = and i1 %tmp, %tmp2 %tmp3 = and i1 %tmp, %tmp2
br i1 %tmp3, label %bb4, label %bb5 br i1 %tmp3, label %bb4, label %bb5
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llvm/test/CodeGen/AMDGPU/branch-relax-bundle.ll

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; plus additional overhead ; plus additional overhead
; s_setpc_b64 ; s_setpc_b64
; and some register copies ; and some register copies
declare void @func() #0 declare void @func() #0
; GCN-LABEL: {{^}}bundle_size: ; GCN-LABEL: {{^}}bundle_size:
; GCN: s_cbranch_scc0 [[BB_EXPANSION:BB[0-9]+_[0-9]+]] ; GCN: s_cbranch_scc0 [[BB_EXPANSION:.LBB[0-9]+_[0-9]+]]
; GCN: s_getpc_b64 ; GCN: s_getpc_b64
; GCN-NEXT: .Lpost_getpc{{[0-9]+}}:{{$}} ; GCN-NEXT: .Lpost_getpc{{[0-9]+}}:{{$}}
; GCN-NEXT: s_add_u32 ; GCN-NEXT: s_add_u32
; GCN-NEXT: s_addc_u32 ; GCN-NEXT: s_addc_u32
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
; GCN: {{^}}[[BB_EXPANSION]]: ; GCN: {{^}}[[BB_EXPANSION]]:
; GCN: s_getpc_b64 ; GCN: s_getpc_b64
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llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll

Show First 20 Lines • Show All 317 Lines • ▼ Show 20 Lines
; CHECK-NEXT: s_mov_b32 s101, 0 ; CHECK-NEXT: s_mov_b32 s101, 0
; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: ;;#ASMEND
; CHECK-NEXT: ;;#ASMSTART ; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: s_mov_b32 vcc_lo, 0 ; CHECK-NEXT: s_mov_b32 vcc_lo, 0
; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: ;;#ASMEND
; CHECK-NEXT: ;;#ASMSTART ; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: s_mov_b32 vcc_hi, 0 ; CHECK-NEXT: s_mov_b32 vcc_hi, 0
; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: ;;#ASMEND
; CHECK-NEXT: s_cbranch_scc0 BB0_1 ; CHECK-NEXT: s_cbranch_scc0 .LBB0_1
; CHECK-NEXT: BB0_3: ; %entry ; CHECK-NEXT: .LBB0_3: ; %entry
; CHECK-NEXT: s_not_b64 exec, exec ; CHECK-NEXT: s_not_b64 exec, exec
; CHECK-NEXT: buffer_store_dword v0, off, s[96:99], 0 ; CHECK-NEXT: buffer_store_dword v0, off, s[96:99], 0
; CHECK-NEXT: v_writelane_b32 v0, s0, 0 ; CHECK-NEXT: v_writelane_b32 v0, s0, 0
; CHECK-NEXT: v_writelane_b32 v0, s1, 1 ; CHECK-NEXT: v_writelane_b32 v0, s1, 1
; CHECK-NEXT: s_getpc_b64 s[0:1] ; CHECK-NEXT: s_getpc_b64 s[0:1]
; CHECK-NEXT: .Lpost_getpc0: ; CHECK-NEXT: .Lpost_getpc0:
; CHECK-NEXT: s_add_u32 s0, s0, (BB0_4-.Lpost_getpc0)&4294967295 ; CHECK-NEXT: s_add_u32 s0, s0, (.LBB0_4-.Lpost_getpc0)&4294967295
; CHECK-NEXT: s_addc_u32 s1, s1, (BB0_4-.Lpost_getpc0)>>32 ; CHECK-NEXT: s_addc_u32 s1, s1, (.LBB0_4-.Lpost_getpc0)>>32
; CHECK-NEXT: s_setpc_b64 s[0:1] ; CHECK-NEXT: s_setpc_b64 s[0:1]
; CHECK-NEXT: BB0_1: ; %bb2 ; CHECK-NEXT: .LBB0_1: ; %bb2
; CHECK-NEXT: ;;#ASMSTART ; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: v_nop_e64 ; CHECK-NEXT: v_nop_e64
; CHECK-NEXT: v_nop_e64 ; CHECK-NEXT: v_nop_e64
; CHECK-NEXT: v_nop_e64 ; CHECK-NEXT: v_nop_e64
; CHECK-NEXT: v_nop_e64 ; CHECK-NEXT: v_nop_e64
; CHECK-NEXT: v_nop_e64 ; CHECK-NEXT: v_nop_e64
; CHECK-NEXT: v_nop_e64 ; CHECK-NEXT: v_nop_e64
; CHECK-NEXT: v_nop_e64 ; CHECK-NEXT: v_nop_e64
; CHECK-NEXT: v_nop_e64 ; CHECK-NEXT: v_nop_e64
; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: ;;#ASMEND
; CHECK-NEXT: s_branch BB0_2 ; CHECK-NEXT: s_branch .LBB0_2
; CHECK-NEXT: BB0_4: ; %bb3 ; CHECK-NEXT: .LBB0_4: ; %bb3
; CHECK-NEXT: v_readlane_b32 s0, v0, 0 ; CHECK-NEXT: v_readlane_b32 s0, v0, 0
; CHECK-NEXT: v_readlane_b32 s1, v0, 1 ; CHECK-NEXT: v_readlane_b32 s1, v0, 1
; CHECK-NEXT: buffer_load_dword v0, off, s[96:99], 0 ; CHECK-NEXT: buffer_load_dword v0, off, s[96:99], 0
; CHECK-NEXT: s_not_b64 exec, exec ; CHECK-NEXT: s_not_b64 exec, exec
; CHECK-NEXT: BB0_2: ; %bb3 ; CHECK-NEXT: .LBB0_2: ; %bb3
; CHECK-NEXT: ;;#ASMSTART ; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: ; reg use s0 ; CHECK-NEXT: ; reg use s0
; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: ;;#ASMEND
; CHECK-NEXT: ;;#ASMSTART ; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: ; reg use s1 ; CHECK-NEXT: ; reg use s1
; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: ;;#ASMEND
; CHECK-NEXT: ;;#ASMSTART ; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: ; reg use s2 ; CHECK-NEXT: ; reg use s2
▲ Show 20 Lines • Show All 921 Lines • ▼ Show 20 Lines
; CHECK-NEXT: s_mov_b32 s101, 0 ; CHECK-NEXT: s_mov_b32 s101, 0
; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: ;;#ASMEND
; CHECK-NEXT: ;;#ASMSTART ; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: s_mov_b32 vcc_lo, 0 ; CHECK-NEXT: s_mov_b32 vcc_lo, 0
; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: ;;#ASMEND
; CHECK-NEXT: ;;#ASMSTART ; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: s_mov_b32 vcc_hi, 0 ; CHECK-NEXT: s_mov_b32 vcc_hi, 0
; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: ;;#ASMEND
; CHECK-NEXT: s_cbranch_scc0 BB1_1 ; CHECK-NEXT: s_cbranch_scc0 .LBB1_1
; CHECK-NEXT: BB1_3: ; %entry ; CHECK-NEXT: .LBB1_3: ; %entry
; CHECK-NEXT: s_not_b64 exec, exec ; CHECK-NEXT: s_not_b64 exec, exec
; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:8 ; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:8
; CHECK-NEXT: v_writelane_b32 v2, s0, 0 ; CHECK-NEXT: v_writelane_b32 v2, s0, 0
; CHECK-NEXT: v_writelane_b32 v2, s1, 1 ; CHECK-NEXT: v_writelane_b32 v2, s1, 1
; CHECK-NEXT: s_getpc_b64 s[0:1] ; CHECK-NEXT: s_getpc_b64 s[0:1]
; CHECK-NEXT: .Lpost_getpc1: ; CHECK-NEXT: .Lpost_getpc1:
; CHECK-NEXT: s_add_u32 s0, s0, (BB1_4-.Lpost_getpc1)&4294967295 ; CHECK-NEXT: s_add_u32 s0, s0, (.LBB1_4-.Lpost_getpc1)&4294967295
; CHECK-NEXT: s_addc_u32 s1, s1, (BB1_4-.Lpost_getpc1)>>32 ; CHECK-NEXT: s_addc_u32 s1, s1, (.LBB1_4-.Lpost_getpc1)>>32
; CHECK-NEXT: s_setpc_b64 s[0:1] ; CHECK-NEXT: s_setpc_b64 s[0:1]
; CHECK-NEXT: BB1_1: ; %bb2 ; CHECK-NEXT: .LBB1_1: ; %bb2
; CHECK-NEXT: ;;#ASMSTART ; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: v_nop_e64 ; CHECK-NEXT: v_nop_e64
; CHECK-NEXT: v_nop_e64 ; CHECK-NEXT: v_nop_e64
; CHECK-NEXT: v_nop_e64 ; CHECK-NEXT: v_nop_e64
; CHECK-NEXT: v_nop_e64 ; CHECK-NEXT: v_nop_e64
; CHECK-NEXT: v_nop_e64 ; CHECK-NEXT: v_nop_e64
; CHECK-NEXT: v_nop_e64 ; CHECK-NEXT: v_nop_e64
; CHECK-NEXT: v_nop_e64 ; CHECK-NEXT: v_nop_e64
; CHECK-NEXT: v_nop_e64 ; CHECK-NEXT: v_nop_e64
; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: ;;#ASMEND
; CHECK-NEXT: s_branch BB1_2 ; CHECK-NEXT: s_branch .LBB1_2
; CHECK-NEXT: BB1_4: ; %bb3 ; CHECK-NEXT: .LBB1_4: ; %bb3
; CHECK-NEXT: v_readlane_b32 s0, v2, 0 ; CHECK-NEXT: v_readlane_b32 s0, v2, 0
; CHECK-NEXT: v_readlane_b32 s1, v2, 1 ; CHECK-NEXT: v_readlane_b32 s1, v2, 1
; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:8 ; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:8
; CHECK-NEXT: s_not_b64 exec, exec ; CHECK-NEXT: s_not_b64 exec, exec
; CHECK-NEXT: BB1_2: ; %bb3 ; CHECK-NEXT: .LBB1_2: ; %bb3
; CHECK-NEXT: ;;#ASMSTART ; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: ; reg use s0 ; CHECK-NEXT: ; reg use s0
; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: ;;#ASMEND
; CHECK-NEXT: ;;#ASMSTART ; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: ; reg use s1 ; CHECK-NEXT: ; reg use s1
; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: ;;#ASMEND
; CHECK-NEXT: ;;#ASMSTART ; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: ; reg use s2 ; CHECK-NEXT: ; reg use s2
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llvm/test/CodeGen/AMDGPU/branch-relaxation-debug-info.mir

# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -start-before=branch-relaxation -amdgpu-s-branch-bits=4 -o - %s | FileCheck -check-prefix=GCN %s # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -start-before=branch-relaxation -amdgpu-s-branch-bits=4 -o - %s | FileCheck -check-prefix=GCN %s
# Make sure there's no assert if the DBG_VALUE ends up in the same # Make sure there's no assert if the DBG_VALUE ends up in the same
# block as the branch expansion. # block as the branch expansion.
# GCN-LABEL: long_branch_dbg_value: # GCN-LABEL: long_branch_dbg_value:
# GCN: BB0_5: ; %bb # GCN: .LBB0_5: ; %bb
# GCN-NEXT: ;DEBUG_VALUE: test_debug_value:globalptr_arg <- [DW_OP_plus_uconst 12, DW_OP_stack_value] # GCN-NEXT: ;DEBUG_VALUE: test_debug_value:globalptr_arg <- [DW_OP_plus_uconst 12, DW_OP_stack_value]
# GCN-NEXT: .loc 1 0 42 is_stmt 0 ; /tmp/test_debug_value.cl:0:42 # GCN-NEXT: .loc 1 0 42 is_stmt 0 ; /tmp/test_debug_value.cl:0:42
# GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} # GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
# GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}} # GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}
# GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], (BB0_4-[[POST_GETPC]])&4294967295 # GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], (.LBB0_4-[[POST_GETPC]])&4294967295
# GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], (BB0_4-[[POST_GETPC]])>>32 # GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], (.LBB0_4-[[POST_GETPC]])>>32
# GCN-NEXT: s_setpc_b64 # GCN-NEXT: s_setpc_b64
--- | --- |
define amdgpu_kernel void @long_branch_dbg_value(float addrspace(1)* nocapture %arg, float %arg1) #1 !dbg !5 { define amdgpu_kernel void @long_branch_dbg_value(float addrspace(1)* nocapture %arg, float %arg1) #1 !dbg !5 {
bb: bb:
%long_branch_dbg_value.kernarg.segment = call nonnull align 16 dereferenceable(12) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() %long_branch_dbg_value.kernarg.segment = call nonnull align 16 dereferenceable(12) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
%arg.kernarg.offset = getelementptr inbounds i8, i8 addrspace(4)* %long_branch_dbg_value.kernarg.segment, i64 0 %arg.kernarg.offset = getelementptr inbounds i8, i8 addrspace(4)* %long_branch_dbg_value.kernarg.segment, i64 0
▲ Show 20 Lines • Show All 103 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx10-branch-offset-bug.ll

; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs -amdgpu-s-branch-bits=7 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1030 %s ; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs -amdgpu-s-branch-bits=7 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1030 %s
; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -amdgpu-s-branch-bits=7 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1010 %s ; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -amdgpu-s-branch-bits=7 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1010 %s
; For gfx1010, overestimate the branch size in case we need to insert ; For gfx1010, overestimate the branch size in case we need to insert
; a nop for the buggy offset. ; a nop for the buggy offset.
; GCN-LABEL: long_forward_scc_branch_3f_offset_bug: ; GCN-LABEL: long_forward_scc_branch_3f_offset_bug:
; GFX1030: s_cmp_lg_u32 ; GFX1030: s_cmp_lg_u32
; GFX1030-NEXT: s_cbranch_scc1 [[ENDBB:BB[0-9]+_[0-9]+]] ; GFX1030-NEXT: s_cbranch_scc1 [[ENDBB:.LBB[0-9]+_[0-9]+]]
; GFX1010: s_cmp_lg_u32 ; GFX1010: s_cmp_lg_u32
; GFX1010-NEXT: s_cbranch_scc0 [[RELAX_BB:BB[0-9]+_[0-9]+]] ; GFX1010-NEXT: s_cbranch_scc0 [[RELAX_BB:.LBB[0-9]+_[0-9]+]]
; GFX1010: s_getpc_b64 ; GFX1010: s_getpc_b64
; GFX1010-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}} ; GFX1010-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}
; GFX1010-NEXT: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, ([[ENDBB:BB[0-9]+_[0-9]+]]-[[POST_GETPC]])&4294967295 ; GFX1010-NEXT: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, ([[ENDBB:.LBB[0-9]+_[0-9]+]]-[[POST_GETPC]])&4294967295
; GFX1010-NEXT: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, ([[ENDBB:BB[0-9]+_[0-9]+]]-[[POST_GETPC]])>>32 ; GFX1010-NEXT: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, ([[ENDBB:.LBB[0-9]+_[0-9]+]]-[[POST_GETPC]])>>32
; GFX1010: [[RELAX_BB]]: ; GFX1010: [[RELAX_BB]]:
; GCN: v_nop ; GCN: v_nop
; GCN: s_sleep ; GCN: s_sleep
; GCN: s_cbranch_scc1 ; GCN: s_cbranch_scc1
; GCN: [[ENDBB]]: ; GCN: [[ENDBB]]:
; GCN: global_store_dword ; GCN: global_store_dword
Show All 23 Lines
bb3: bb3:
store volatile i32 %cnd0, i32 addrspace(1)* %arg store volatile i32 %cnd0, i32 addrspace(1)* %arg
ret void ret void
} }
; GCN-LABEL: {{^}}long_forward_exec_branch_3f_offset_bug: ; GCN-LABEL: {{^}}long_forward_exec_branch_3f_offset_bug:
; GFX1030: v_cmp_eq_u32 ; GFX1030: v_cmp_eq_u32
; GFX1030: s_and_saveexec_b32 ; GFX1030: s_and_saveexec_b32
; GFX1030-NEXT: s_cbranch_execnz [[RELAX_BB:BB[0-9]+_[0-9]+]] ; GFX1030-NEXT: s_cbranch_execnz [[RELAX_BB:.LBB[0-9]+_[0-9]+]]
; GFX1010: v_cmp_eq_u32 ; GFX1010: v_cmp_eq_u32
; GFX1010: s_and_saveexec_b32 ; GFX1010: s_and_saveexec_b32
; GFX1010-NEXT: s_cbranch_execnz [[RELAX_BB:BB[0-9]+_[0-9]+]] ; GFX1010-NEXT: s_cbranch_execnz [[RELAX_BB:.LBB[0-9]+_[0-9]+]]
; GCN: s_getpc_b64 ; GCN: s_getpc_b64
; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}} ; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}
; GCN-NEXT: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, ([[ENDBB:BB[0-9]+_[0-9]+]]-[[POST_GETPC]])&4294967295 ; GCN-NEXT: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, ([[ENDBB:.LBB[0-9]+_[0-9]+]]-[[POST_GETPC]])&4294967295
; GCN-NEXT: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, ([[ENDBB:BB[0-9]+_[0-9]+]]-[[POST_GETPC]])>>32 ; GCN-NEXT: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, ([[ENDBB:.LBB[0-9]+_[0-9]+]]-[[POST_GETPC]])>>32
; GCN: [[RELAX_BB]]: ; GCN: [[RELAX_BB]]:
; GCN: v_nop ; GCN: v_nop
; GCN: s_sleep ; GCN: s_sleep
; GCN: s_cbranch_execz ; GCN: s_cbranch_execz
; GCN: [[ENDBB]]: ; GCN: [[ENDBB]]:
; GCN: global_store_dword ; GCN: global_store_dword
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llvm/test/CodeGen/AMDGPU/branch-relaxation.ll

Show All 15 Lines
declare void @llvm.amdgcn.s.sleep(i32) #0 declare void @llvm.amdgcn.s.sleep(i32) #0
declare i32 @llvm.amdgcn.workitem.id.x() #1 declare i32 @llvm.amdgcn.workitem.id.x() #1
; GCN-LABEL: {{^}}uniform_conditional_max_short_forward_branch: ; GCN-LABEL: {{^}}uniform_conditional_max_short_forward_branch:
; GCN: s_load_dword [[CND:s[0-9]+]] ; GCN: s_load_dword [[CND:s[0-9]+]]
; GCN: s_cmp_eq_u32 [[CND]], 0 ; GCN: s_cmp_eq_u32 [[CND]], 0
; GCN-NEXT: s_cbranch_scc1 [[BB3:BB[0-9]+_[0-9]+]] ; GCN-NEXT: s_cbranch_scc1 [[BB3:.LBB[0-9]+_[0-9]+]]
; GCN-NEXT: ; %bb.1: ; %bb2 ; GCN-NEXT: ; %bb.1: ; %bb2
; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: ;;#ASMSTART
; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64
; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64
; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64
; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: ;;#ASMEND
Show All 20 Lines
bb3: bb3:
store volatile i32 %cnd, i32 addrspace(1)* %arg store volatile i32 %cnd, i32 addrspace(1)* %arg
ret void ret void
} }
; GCN-LABEL: {{^}}uniform_conditional_min_long_forward_branch: ; GCN-LABEL: {{^}}uniform_conditional_min_long_forward_branch:
; GCN: s_load_dword [[CND:s[0-9]+]] ; GCN: s_load_dword [[CND:s[0-9]+]]
; GCN: s_cmp_eq_u32 [[CND]], 0 ; GCN: s_cmp_eq_u32 [[CND]], 0
; GCN-NEXT: s_cbranch_scc0 [[LONGBB:BB[0-9]+_[0-9]+]] ; GCN-NEXT: s_cbranch_scc0 [[LONGBB:.LBB[0-9]+_[0-9]+]]
; GCN-NEXT: {{BB[0-9]+_[0-9]+}}: ; %bb0 ; GCN-NEXT: {{.LBB[0-9]+_[0-9]+}}: ; %bb0
; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}} ; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}
; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], ([[ENDBB:BB[0-9]+_[0-9]+]]-[[POST_GETPC]])&4294967295 ; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], ([[ENDBB:.LBB[0-9]+_[0-9]+]]-[[POST_GETPC]])&4294967295
; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], ([[ENDBB]]-[[POST_GETPC]])>>32 ; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], ([[ENDBB]]-[[POST_GETPC]])>>32
; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}} ; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
; GCN-NEXT: [[LONGBB]]: ; GCN-NEXT: [[LONGBB]]:
; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: ;;#ASMSTART
; GCN: v_nop_e64 ; GCN: v_nop_e64
; GCN: v_nop_e64 ; GCN: v_nop_e64
; GCN: v_nop_e64 ; GCN: v_nop_e64
Show All 23 Linesbb3:
ret void ret void
} }
; GCN-LABEL: {{^}}uniform_conditional_min_long_forward_vcnd_branch: ; GCN-LABEL: {{^}}uniform_conditional_min_long_forward_vcnd_branch:
; GCN: s_load_dword [[CND:s[0-9]+]] ; GCN: s_load_dword [[CND:s[0-9]+]]
; GCN-DAG: v_cmp_eq_f32_e64 [[UNMASKED:s\[[0-9]+:[0-9]+\]]], [[CND]], 0 ; GCN-DAG: v_cmp_eq_f32_e64 [[UNMASKED:s\[[0-9]+:[0-9]+\]]], [[CND]], 0
; GCN-DAG: s_and_b64 vcc, exec, [[UNMASKED]] ; GCN-DAG: s_and_b64 vcc, exec, [[UNMASKED]]
; GCN: s_cbranch_vccz [[LONGBB:BB[0-9]+_[0-9]+]] ; GCN: s_cbranch_vccz [[LONGBB:.LBB[0-9]+_[0-9]+]]
; GCN-NEXT: {{BB[0-9]+_[0-9]+}}: ; %bb0 ; GCN-NEXT: {{.LBB[0-9]+_[0-9]+}}: ; %bb0
; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}} ; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}
; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], ([[ENDBB:BB[0-9]+_[0-9]+]]-[[POST_GETPC]])&4294967295 ; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], ([[ENDBB:.LBB[0-9]+_[0-9]+]]-[[POST_GETPC]])&4294967295
; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], ([[ENDBB]]-[[POST_GETPC]])>>32 ; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], ([[ENDBB]]-[[POST_GETPC]])>>32
; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}} ; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
; GCN-NEXT: [[LONGBB]]: ; GCN-NEXT: [[LONGBB]]:
; GCN: v_nop_e64 ; GCN: v_nop_e64
; GCN: v_nop_e64 ; GCN: v_nop_e64
; GCN: v_nop_e64 ; GCN: v_nop_e64
; GCN: v_nop_e64 ; GCN: v_nop_e64
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
bb3: bb3:
store volatile i32 %load, i32 addrspace(1)* %gep store volatile i32 %load, i32 addrspace(1)* %gep
ret void ret void
} }
; GCN-LABEL: {{^}}long_backward_sbranch: ; GCN-LABEL: {{^}}long_backward_sbranch:
; GCN: s_mov_b32 [[LOOPIDX:s[0-9]+]], 0{{$}} ; GCN: s_mov_b32 [[LOOPIDX:s[0-9]+]], 0{{$}}
; GCN: [[LOOPBB:BB[0-9]+_[0-9]+]]: ; %bb2 ; GCN: .L[[LOOPBB:BB[0-9]+_[0-9]+]]: ; %bb2
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: s_add_i32 [[INC:s[0-9]+]], [[LOOPIDX]], 1 ; GCN-NEXT: s_add_i32 [[INC:s[0-9]+]], [[LOOPIDX]], 1
; GCN-NEXT: s_cmp_lt_i32 [[INC]], 10 ; GCN-NEXT: s_cmp_lt_i32 [[INC]], 10
; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: ;;#ASMSTART
; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64
; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64
; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64
; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: ;;#ASMEND
; GCN-NEXT: s_cbranch_scc0 [[ENDBB:BB[0-9]+_[0-9]+]] ; GCN-NEXT: s_cbranch_scc0 [[ENDBB:.LBB[0-9]+_[0-9]+]]
; GCN-NEXT: {{BB[0-9]+_[0-9]+}}: ; %bb2 ; GCN-NEXT: {{.LBB[0-9]+_[0-9]+}}: ; %bb2
; GCN-NEXT: ; in Loop: Header=[[LOOPBB]] Depth=1 ; GCN-NEXT: ; in Loop: Header=[[LOOPBB]] Depth=1
; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}} ; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}
; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], ([[LOOPBB]]-[[POST_GETPC]])&4294967295 ; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], (.L[[LOOPBB]]-[[POST_GETPC]])&4294967295
; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], ([[LOOPBB]]-[[POST_GETPC]])>>32 ; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], (.L[[LOOPBB]]-[[POST_GETPC]])>>32
; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}} ; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
; GCN-NEXT: [[ENDBB]]: ; GCN-NEXT: [[ENDBB]]:
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @long_backward_sbranch(i32 addrspace(1)* %arg) #0 { define amdgpu_kernel void @long_backward_sbranch(i32 addrspace(1)* %arg) #0 {
bb: bb:
br label %bb2 br label %bb2
Show All 12 Linesbb3:
ret void ret void
} }
; Requires expansion of unconditional branch from %bb2 to %bb4 (and ; Requires expansion of unconditional branch from %bb2 to %bb4 (and
; expansion of conditional branch from %bb to %bb3. ; expansion of conditional branch from %bb to %bb3.
; GCN-LABEL: {{^}}uniform_unconditional_min_long_forward_branch: ; GCN-LABEL: {{^}}uniform_unconditional_min_long_forward_branch:
; GCN: s_cmp_eq_u32 ; GCN: s_cmp_eq_u32
; GCN: s_cbranch_scc{{[0-1]}} [[BB2:BB[0-9]+_[0-9]+]] ; GCN: s_cbranch_scc{{[0-1]}} [[BB2:.LBB[0-9]+_[0-9]+]]
; GCN-NEXT: {{BB[0-9]+_[0-9]+}}: ; %bb0 ; GCN-NEXT: {{.LBB[0-9]+_[0-9]+}}: ; %bb0
; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]{{\]}} ; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]{{\]}}
; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}} ; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}
; GCN-NEXT: s_add_u32 s[[PC0_LO]], s[[PC0_LO]], ([[BB3:BB[0-9]_[0-9]+]]-[[POST_GETPC]])&4294967295 ; GCN-NEXT: s_add_u32 s[[PC0_LO]], s[[PC0_LO]], ([[BB3:.LBB[0-9]_[0-9]+]]-[[POST_GETPC]])&4294967295
; GCN-NEXT: s_addc_u32 s[[PC0_HI]], s[[PC0_HI]], ([[BB3:BB[0-9]_[0-9]+]]-[[POST_GETPC]])>>32 ; GCN-NEXT: s_addc_u32 s[[PC0_HI]], s[[PC0_HI]], ([[BB3:.LBB[0-9]_[0-9]+]]-[[POST_GETPC]])>>32
; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC0_LO]]:[[PC0_HI]]{{\]}} ; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC0_LO]]:[[PC0_HI]]{{\]}}
; GCN: [[BB2]]: ; %bb3 ; GCN: [[BB2]]: ; %bb3
; GCN: v_nop_e64 ; GCN: v_nop_e64
; GCN: v_nop_e64 ; GCN: v_nop_e64
; GCN: v_nop_e64 ; GCN: v_nop_e64
; GCN: v_nop_e64 ; GCN: v_nop_e64
; GCN: ;;#ASMEND ; GCN: ;;#ASMEND
Show All 27 Lines
bb4: bb4:
store volatile i32 63, i32 addrspace(1)* %arg store volatile i32 63, i32 addrspace(1)* %arg
ret void ret void
} }
; GCN-LABEL: {{^}}uniform_unconditional_min_long_backward_branch: ; GCN-LABEL: {{^}}uniform_unconditional_min_long_backward_branch:
; GCN-NEXT: ; %bb.0: ; %entry ; GCN-NEXT: ; %bb.0: ; %entry
; GCN-NEXT: [[LOOP:BB[0-9]_[0-9]+]]: ; %loop ; GCN-NEXT: .L[[LOOP:BB[0-9]_[0-9]+]]: ; %loop
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: ;;#ASMSTART
; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64
; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64
; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64
; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64
; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: ;;#ASMEND
; GCN-NEXT: {{BB[0-9]+_[0-9]+}}: ; %loop ; GCN-NEXT: {{.LBB[0-9]+_[0-9]+}}: ; %loop
; GCN-NEXT: ; in Loop: Header=[[LOOP]] Depth=1 ; GCN-NEXT: ; in Loop: Header=[[LOOP]] Depth=1
; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}} ; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}
; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], ([[LOOP]]-[[POST_GETPC]])&4294967295 ; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], (.L[[LOOP]]-[[POST_GETPC]])&4294967295
; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], ([[LOOP]]-[[POST_GETPC]])>>32 ; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], (.L[[LOOP]]-[[POST_GETPC]])>>32
; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}} ; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
; GCN-NEXT: .Lfunc_end{{[0-9]+}}: ; GCN-NEXT: .Lfunc_end{{[0-9]+}}:
define amdgpu_kernel void @uniform_unconditional_min_long_backward_branch(i32 addrspace(1)* %arg, i32 %arg1) { define amdgpu_kernel void @uniform_unconditional_min_long_backward_branch(i32 addrspace(1)* %arg, i32 %arg1) {
entry: entry:
br label %loop br label %loop
loop: loop:
; 32 byte asm ; 32 byte asm
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; GCN: s_load_dword ; GCN: s_load_dword
; GCN: {{s|v}}_cmp_lt_i32 ; GCN: {{s|v}}_cmp_lt_i32
; GCN: s_cbranch ; GCN: s_cbranch
; GCN: s_load_dword ; GCN: s_load_dword
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_cmp_lg_u32 ; GCN-NEXT: s_cmp_lg_u32
; GCN-NEXT: s_cselect_b64 ; GCN-NEXT: s_cselect_b64
; GCN: s_cbranch_vccz [[BB2:BB[0-9]_[0-9]+]] ; GCN: s_cbranch_vccz [[BB2:.LBB[0-9]_[0-9]+]]
; GCN-NEXT: {{BB[0-9]+_[0-9]+}}: ; GCN-NEXT: {{.LBB[0-9]+_[0-9]+}}:
; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC1_LO:[0-9]+]]:[[PC1_HI:[0-9]+]]{{\]}} ; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC1_LO:[0-9]+]]:[[PC1_HI:[0-9]+]]{{\]}}
; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}} ; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}
; GCN-NEXT: s_add_u32 s[[PC1_LO]], s[[PC1_LO]], ([[BB3:BB[0-9]+_[0-9]+]]-[[POST_GETPC]])&4294967295 ; GCN-NEXT: s_add_u32 s[[PC1_LO]], s[[PC1_LO]], ([[BB3:.LBB[0-9]+_[0-9]+]]-[[POST_GETPC]])&4294967295
; GCN-NEXT: s_addc_u32 s[[PC1_HI]], s[[PC1_HI]], ([[BB3:BB[0-9]+_[0-9]+]]-[[POST_GETPC]])>>32 ; GCN-NEXT: s_addc_u32 s[[PC1_HI]], s[[PC1_HI]], ([[BB3:.LBB[0-9]+_[0-9]+]]-[[POST_GETPC]])>>32
; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC1_LO]]:[[PC1_HI]]{{\]}} ; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC1_LO]]:[[PC1_HI]]{{\]}}
; GCN-NEXT: [[BB2]]: ; %bb2 ; GCN-NEXT: [[BB2]]: ; %bb2
; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: ;;#ASMSTART
; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64
; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64
; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64
; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64
Show All 36 Lines; from firing, which defeats the need to expand the branches and this test.
ret void ret void
} }
; Requires expanding of required skip branch. ; Requires expanding of required skip branch.
; GCN-LABEL: {{^}}uniform_inside_divergent: ; GCN-LABEL: {{^}}uniform_inside_divergent:
; GCN: v_cmp_gt_u32_e32 vcc, 16, v{{[0-9]+}} ; GCN: v_cmp_gt_u32_e32 vcc, 16, v{{[0-9]+}}
; GCN-NEXT: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc ; GCN-NEXT: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc
; GCN-NEXT: s_cbranch_execnz [[IF:BB[0-9]+_[0-9]+]] ; GCN-NEXT: s_cbranch_execnz [[IF:.LBB[0-9]+_[0-9]+]]
; GCN-NEXT: {{BB[0-9]+_[0-9]+}}: ; %entry ; GCN-NEXT: {{.LBB[0-9]+_[0-9]+}}: ; %entry
; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}} ; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}
; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], ([[BB2:BB[0-9]_[0-9]+]]-[[POST_GETPC]])&4294967295 ; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], ([[BB2:.LBB[0-9]_[0-9]+]]-[[POST_GETPC]])&4294967295
; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], ([[BB2:BB[0-9]_[0-9]+]]-[[POST_GETPC]])>>32 ; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], ([[BB2:.LBB[0-9]_[0-9]+]]-[[POST_GETPC]])>>32
; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}} ; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
; GCN-NEXT: [[IF]]: ; %if ; GCN-NEXT: [[IF]]: ; %if
; GCN: buffer_store_dword ; GCN: buffer_store_dword
; GCN: s_cmp_lg_u32 ; GCN: s_cmp_lg_u32
; GCN: s_cbranch_scc1 [[ENDIF:BB[0-9]+_[0-9]+]] ; GCN: s_cbranch_scc1 [[ENDIF:.LBB[0-9]+_[0-9]+]]
; GCN-NEXT: ; %bb.2: ; %if_uniform ; GCN-NEXT: ; %bb.2: ; %if_uniform
; GCN: buffer_store_dword ; GCN: buffer_store_dword
; GCN-NEXT: [[ENDIF]]: ; %endif ; GCN-NEXT: [[ENDIF]]: ; %endif
; GCN-NEXT: s_or_b64 exec, exec, [[MASK]] ; GCN-NEXT: s_or_b64 exec, exec, [[MASK]]
; GCN-NEXT: s_sleep 5 ; GCN-NEXT: s_sleep 5
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
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; GCN: v_cmp_nlt_f32_e32 vcc ; GCN: v_cmp_nlt_f32_e32 vcc
; GCN-NEXT: s_and_saveexec_b64 [[TEMP_MASK:s\[[0-9]+:[0-9]+\]]], vcc ; GCN-NEXT: s_and_saveexec_b64 [[TEMP_MASK:s\[[0-9]+:[0-9]+\]]], vcc
; GCN-NEXT: s_xor_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], exec, [[TEMP_MASK]] ; GCN-NEXT: s_xor_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], exec, [[TEMP_MASK]]
; GCN: BB{{[0-9]+_[0-9]+}}: ; %Flow ; GCN: BB{{[0-9]+_[0-9]+}}: ; %Flow
; GCN-NEXT: s_or_saveexec_b64 [[TEMP_MASK1:s\[[0-9]+:[0-9]+\]]], [[MASK]] ; GCN-NEXT: s_or_saveexec_b64 [[TEMP_MASK1:s\[[0-9]+:[0-9]+\]]], [[MASK]]
; GCN-NEXT: s_xor_b64 exec, exec, [[TEMP_MASK1]] ; GCN-NEXT: s_xor_b64 exec, exec, [[TEMP_MASK1]]
; GCN: [[LOOP_BODY:BB[0-9]+_[0-9]+]]: ; %loop{{$}} ; GCN: .L[[LOOP_BODY:BB[0-9]+_[0-9]+]]: ; %loop{{$}}
; GCN: ;;#ASMSTART ; GCN: ;;#ASMSTART
; GCN: v_nop_e64 ; GCN: v_nop_e64
; GCN: v_nop_e64 ; GCN: v_nop_e64
; GCN: v_nop_e64 ; GCN: v_nop_e64
; GCN: v_nop_e64 ; GCN: v_nop_e64
; GCN: v_nop_e64 ; GCN: v_nop_e64
; GCN: v_nop_e64 ; GCN: v_nop_e64
; GCN: ;;#ASMEND ; GCN: ;;#ASMEND
; GCN: s_cbranch_{{vccz|vccnz}} [[RET:BB[0-9]+_[0-9]+]] ; GCN: s_cbranch_{{vccz|vccnz}} [[RET:.LBB[0-9]+_[0-9]+]]
; GCN-NEXT: {{BB[0-9]+_[0-9]+}}: ; %loop ; GCN-NEXT: {{.LBB[0-9]+_[0-9]+}}: ; %loop
; GCN-NEXT: ; in Loop: Header=[[LOOP_BODY]] Depth=1 ; GCN-NEXT: ; in Loop: Header=[[LOOP_BODY]] Depth=1
; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}} ; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}
; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], ([[LOOP_BODY]]-[[POST_GETPC]])&4294967295 ; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], (.L[[LOOP_BODY]]-[[POST_GETPC]])&4294967295
; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], ([[LOOP_BODY]]-[[POST_GETPC]])>>32 ; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], (.L[[LOOP_BODY]]-[[POST_GETPC]])>>32
; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}} ; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
; GCN-NEXT: [[RET]]: ; %UnifiedReturnBlock ; GCN-NEXT: [[RET]]: ; %UnifiedReturnBlock
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @analyze_mask_branch() #0 { define amdgpu_kernel void @analyze_mask_branch() #0 {
entry: entry:
%reg = call float asm sideeffect "v_mov_b32_e64 $0, 0", "=v"() %reg = call float asm sideeffect "v_mov_b32_e64 $0, 0", "=v"()
%cmp0 = fcmp ogt float %reg, 0.000000e+00 %cmp0 = fcmp ogt float %reg, 0.000000e+00
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ret: ret:
store volatile i32 7, i32 addrspace(1)* undef store volatile i32 7, i32 addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}long_branch_hang: ; GCN-LABEL: {{^}}long_branch_hang:
; GCN: s_cmp_lt_i32 s{{[0-9]+}}, 6 ; GCN: s_cmp_lt_i32 s{{[0-9]+}}, 6
; GCN: s_cbranch_scc{{[0-1]}} [[LONG_BR_0:BB[0-9]+_[0-9]+]] ; GCN: s_cbranch_scc{{[0-1]}} [[LONG_BR_0:.LBB[0-9]+_[0-9]+]]
; GCN-NEXT: BB{{[0-9]+_[0-9]+}}: ; GCN-NEXT: BB{{[0-9]+_[0-9]+}}:
; GCN: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; GCN: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}} ; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}
; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], ([[LONG_BR_DEST0:BB[0-9]+_[0-9]+]]-[[POST_GETPC]])&4294967295 ; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], ([[LONG_BR_DEST0:.LBB[0-9]+_[0-9]+]]-[[POST_GETPC]])&4294967295
; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], ([[LONG_BR_DEST0]]-[[POST_GETPC]])>>32 ; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], ([[LONG_BR_DEST0]]-[[POST_GETPC]])>>32
; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}} ; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
; GCN-NEXT: [[LONG_BR_0]]: ; GCN-NEXT: [[LONG_BR_0]]:
; GCN: [[LONG_BR_DEST0]]: ; GCN: [[LONG_BR_DEST0]]:
; GCN-DAG: s_cmp_lt_i32 ; GCN-DAG: s_cmp_lt_i32
; GCN-DAG: s_cmp_ge_i32 ; GCN-DAG: s_cmp_ge_i32
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llvm/test/CodeGen/AMDGPU/bypass-div.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
; 64-bit divides and rems should be split into a fast and slow path ; 64-bit divides and rems should be split into a fast and slow path
; where the fast path uses a 32-bit operation. ; where the fast path uses a 32-bit operation.
define i64 @sdiv64(i64 %a, i64 %b) { define i64 @sdiv64(i64 %a, i64 %b) {
; GFX9-LABEL: sdiv64: ; GFX9-LABEL: sdiv64:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_or_b32_e32 v5, v1, v3 ; GFX9-NEXT: v_or_b32_e32 v5, v1, v3
; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5] ; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
; GFX9-NEXT: ; implicit-def: $vgpr4_vgpr5 ; GFX9-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[6:7], exec, s[4:5] ; GFX9-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz BB0_2 ; GFX9-NEXT: s_cbranch_execz .LBB0_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: v_ashrrev_i32_e32 v4, 31, v3 ; GFX9-NEXT: v_ashrrev_i32_e32 v4, 31, v3
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v4, vcc
; GFX9-NEXT: v_xor_b32_e32 v3, v3, v4 ; GFX9-NEXT: v_xor_b32_e32 v3, v3, v4
; GFX9-NEXT: v_xor_b32_e32 v2, v2, v4 ; GFX9-NEXT: v_xor_b32_e32 v2, v2, v4
; GFX9-NEXT: v_cvt_f32_u32_e32 v5, v2 ; GFX9-NEXT: v_cvt_f32_u32_e32 v5, v2
; GFX9-NEXT: v_cvt_f32_u32_e32 v6, v3 ; GFX9-NEXT: v_cvt_f32_u32_e32 v6, v3
▲ Show 20 Lines • Show All 104 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_xor_b32_e32 v2, v7, v4 ; GFX9-NEXT: v_xor_b32_e32 v2, v7, v4
; GFX9-NEXT: v_cndmask_b32_e32 v0, v6, v9, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v6, v9, vcc
; GFX9-NEXT: v_xor_b32_e32 v1, v1, v2 ; GFX9-NEXT: v_xor_b32_e32 v1, v1, v2
; GFX9-NEXT: v_xor_b32_e32 v0, v0, v2 ; GFX9-NEXT: v_xor_b32_e32 v0, v0, v2
; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v1, v2 ; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v1, v2
; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v0, v2, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v0, v2, vcc
; GFX9-NEXT: ; implicit-def: $vgpr2_vgpr3 ; GFX9-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX9-NEXT: BB0_2: ; %Flow ; GFX9-NEXT: .LBB0_2: ; %Flow
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], s[6:7] ; GFX9-NEXT: s_or_saveexec_b64 s[4:5], s[6:7]
; GFX9-NEXT: s_xor_b64 exec, exec, s[4:5] ; GFX9-NEXT: s_xor_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz BB0_4 ; GFX9-NEXT: s_cbranch_execz .LBB0_4
; GFX9-NEXT: ; %bb.3: ; GFX9-NEXT: ; %bb.3:
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v2 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v2
; GFX9-NEXT: v_sub_u32_e32 v3, 0, v2 ; GFX9-NEXT: v_sub_u32_e32 v3, 0, v2
; GFX9-NEXT: v_mov_b32_e32 v5, 0 ; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_mul_lo_u32 v3, v3, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, v3, v1
; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX9-NEXT: v_mul_lo_u32 v3, v1, v2 ; GFX9-NEXT: v_mul_lo_u32 v3, v1, v2
; GFX9-NEXT: v_add_u32_e32 v4, 1, v1 ; GFX9-NEXT: v_add_u32_e32 v4, 1, v1
; GFX9-NEXT: v_sub_u32_e32 v0, v0, v3 ; GFX9-NEXT: v_sub_u32_e32 v0, v0, v3
; GFX9-NEXT: v_sub_u32_e32 v3, v0, v2 ; GFX9-NEXT: v_sub_u32_e32 v3, v0, v2
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 ; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX9-NEXT: v_add_u32_e32 v3, 1, v1 ; GFX9-NEXT: v_add_u32_e32 v3, 1, v1
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 ; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
; GFX9-NEXT: v_cndmask_b32_e32 v4, v1, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, v1, v3, vcc
; GFX9-NEXT: BB0_4: ; GFX9-NEXT: .LBB0_4:
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: v_mov_b32_e32 v0, v4 ; GFX9-NEXT: v_mov_b32_e32 v0, v4
; GFX9-NEXT: v_mov_b32_e32 v1, v5 ; GFX9-NEXT: v_mov_b32_e32 v1, v5
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
%d = sdiv i64 %a, %b %d = sdiv i64 %a, %b
ret i64 %d ret i64 %d
} }
define i64 @udiv64(i64 %a, i64 %b) { define i64 @udiv64(i64 %a, i64 %b) {
; GFX9-LABEL: udiv64: ; GFX9-LABEL: udiv64:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_or_b32_e32 v5, v1, v3 ; GFX9-NEXT: v_or_b32_e32 v5, v1, v3
; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5] ; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
; GFX9-NEXT: ; implicit-def: $vgpr4_vgpr5 ; GFX9-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[6:7], exec, s[4:5] ; GFX9-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz BB1_2 ; GFX9-NEXT: s_cbranch_execz .LBB1_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: v_cvt_f32_u32_e32 v4, v2 ; GFX9-NEXT: v_cvt_f32_u32_e32 v4, v2
; GFX9-NEXT: v_cvt_f32_u32_e32 v5, v3 ; GFX9-NEXT: v_cvt_f32_u32_e32 v5, v3
; GFX9-NEXT: v_sub_co_u32_e32 v6, vcc, 0, v2 ; GFX9-NEXT: v_sub_co_u32_e32 v6, vcc, 0, v2
; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, 0, v3, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, 0, v3, vcc
; GFX9-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; GFX9-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
; GFX9-NEXT: v_rcp_f32_e32 v4, v4 ; GFX9-NEXT: v_rcp_f32_e32 v4, v4
; GFX9-NEXT: v_mov_b32_e32 v12, 0 ; GFX9-NEXT: v_mov_b32_e32 v12, 0
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; GFX9-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v7, v11, v9, s[4:5] ; GFX9-NEXT: v_cndmask_b32_e64 v7, v11, v9, s[4:5]
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT: v_cndmask_b32_e64 v0, v10, v8, s[4:5] ; GFX9-NEXT: v_cndmask_b32_e64 v0, v10, v8, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc
; GFX9-NEXT: ; implicit-def: $vgpr2_vgpr3 ; GFX9-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX9-NEXT: BB1_2: ; %Flow ; GFX9-NEXT: .LBB1_2: ; %Flow
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], s[6:7] ; GFX9-NEXT: s_or_saveexec_b64 s[4:5], s[6:7]
; GFX9-NEXT: s_xor_b64 exec, exec, s[4:5] ; GFX9-NEXT: s_xor_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz BB1_4 ; GFX9-NEXT: s_cbranch_execz .LBB1_4
; GFX9-NEXT: ; %bb.3: ; GFX9-NEXT: ; %bb.3:
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v2 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v2
; GFX9-NEXT: v_sub_u32_e32 v3, 0, v2 ; GFX9-NEXT: v_sub_u32_e32 v3, 0, v2
; GFX9-NEXT: v_mov_b32_e32 v5, 0 ; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_mul_lo_u32 v3, v3, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, v3, v1
; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX9-NEXT: v_mul_lo_u32 v3, v1, v2 ; GFX9-NEXT: v_mul_lo_u32 v3, v1, v2
; GFX9-NEXT: v_add_u32_e32 v4, 1, v1 ; GFX9-NEXT: v_add_u32_e32 v4, 1, v1
; GFX9-NEXT: v_sub_u32_e32 v0, v0, v3 ; GFX9-NEXT: v_sub_u32_e32 v0, v0, v3
; GFX9-NEXT: v_sub_u32_e32 v3, v0, v2 ; GFX9-NEXT: v_sub_u32_e32 v3, v0, v2
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 ; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX9-NEXT: v_add_u32_e32 v3, 1, v1 ; GFX9-NEXT: v_add_u32_e32 v3, 1, v1
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 ; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
; GFX9-NEXT: v_cndmask_b32_e32 v4, v1, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, v1, v3, vcc
; GFX9-NEXT: BB1_4: ; GFX9-NEXT: .LBB1_4:
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: v_mov_b32_e32 v0, v4 ; GFX9-NEXT: v_mov_b32_e32 v0, v4
; GFX9-NEXT: v_mov_b32_e32 v1, v5 ; GFX9-NEXT: v_mov_b32_e32 v1, v5
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
%d = udiv i64 %a, %b %d = udiv i64 %a, %b
ret i64 %d ret i64 %d
} }
define i64 @srem64(i64 %a, i64 %b) { define i64 @srem64(i64 %a, i64 %b) {
; GFX9-LABEL: srem64: ; GFX9-LABEL: srem64:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_or_b32_e32 v5, v1, v3 ; GFX9-NEXT: v_or_b32_e32 v5, v1, v3
; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5] ; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
; GFX9-NEXT: ; implicit-def: $vgpr4_vgpr5 ; GFX9-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GFX9-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz BB2_2 ; GFX9-NEXT: s_cbranch_execz .LBB2_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: v_ashrrev_i32_e32 v4, 31, v3 ; GFX9-NEXT: v_ashrrev_i32_e32 v4, 31, v3
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v4, vcc
; GFX9-NEXT: v_xor_b32_e32 v3, v3, v4 ; GFX9-NEXT: v_xor_b32_e32 v3, v3, v4
; GFX9-NEXT: v_xor_b32_e32 v2, v2, v4 ; GFX9-NEXT: v_xor_b32_e32 v2, v2, v4
; GFX9-NEXT: v_cvt_f32_u32_e32 v4, v2 ; GFX9-NEXT: v_cvt_f32_u32_e32 v4, v2
; GFX9-NEXT: v_cvt_f32_u32_e32 v5, v3 ; GFX9-NEXT: v_cvt_f32_u32_e32 v5, v3
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; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX9-NEXT: v_xor_b32_e32 v0, v0, v6 ; GFX9-NEXT: v_xor_b32_e32 v0, v0, v6
; GFX9-NEXT: v_xor_b32_e32 v1, v1, v6 ; GFX9-NEXT: v_xor_b32_e32 v1, v1, v6
; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v0, v6 ; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v0, v6
; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v1, v6, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v1, v6, vcc
; GFX9-NEXT: ; implicit-def: $vgpr2_vgpr3 ; GFX9-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX9-NEXT: BB2_2: ; %Flow ; GFX9-NEXT: .LBB2_2: ; %Flow
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], s[8:9] ; GFX9-NEXT: s_or_saveexec_b64 s[4:5], s[8:9]
; GFX9-NEXT: s_xor_b64 exec, exec, s[4:5] ; GFX9-NEXT: s_xor_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz BB2_4 ; GFX9-NEXT: s_cbranch_execz .LBB2_4
; GFX9-NEXT: ; %bb.3: ; GFX9-NEXT: ; %bb.3:
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v2 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v2
; GFX9-NEXT: v_sub_u32_e32 v3, 0, v2 ; GFX9-NEXT: v_sub_u32_e32 v3, 0, v2
; GFX9-NEXT: v_mov_b32_e32 v5, 0 ; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_mul_lo_u32 v3, v3, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, v3, v1
; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX9-NEXT: v_mul_lo_u32 v1, v1, v2 ; GFX9-NEXT: v_mul_lo_u32 v1, v1, v2
; GFX9-NEXT: v_sub_u32_e32 v0, v0, v1 ; GFX9-NEXT: v_sub_u32_e32 v0, v0, v1
; GFX9-NEXT: v_sub_u32_e32 v1, v0, v2 ; GFX9-NEXT: v_sub_u32_e32 v1, v0, v2
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 ; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX9-NEXT: v_sub_u32_e32 v1, v0, v2 ; GFX9-NEXT: v_sub_u32_e32 v1, v0, v2
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 ; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
; GFX9-NEXT: v_cndmask_b32_e32 v4, v0, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, v0, v1, vcc
; GFX9-NEXT: BB2_4: ; GFX9-NEXT: .LBB2_4:
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: v_mov_b32_e32 v0, v4 ; GFX9-NEXT: v_mov_b32_e32 v0, v4
; GFX9-NEXT: v_mov_b32_e32 v1, v5 ; GFX9-NEXT: v_mov_b32_e32 v1, v5
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
%d = srem i64 %a, %b %d = srem i64 %a, %b
ret i64 %d ret i64 %d
} }
define i64 @urem64(i64 %a, i64 %b) { define i64 @urem64(i64 %a, i64 %b) {
; GFX9-LABEL: urem64: ; GFX9-LABEL: urem64:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_or_b32_e32 v5, v1, v3 ; GFX9-NEXT: v_or_b32_e32 v5, v1, v3
; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5] ; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
; GFX9-NEXT: ; implicit-def: $vgpr4_vgpr5 ; GFX9-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GFX9-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz BB3_2 ; GFX9-NEXT: s_cbranch_execz .LBB3_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: v_cvt_f32_u32_e32 v4, v2 ; GFX9-NEXT: v_cvt_f32_u32_e32 v4, v2
; GFX9-NEXT: v_cvt_f32_u32_e32 v5, v3 ; GFX9-NEXT: v_cvt_f32_u32_e32 v5, v3
; GFX9-NEXT: v_sub_co_u32_e32 v6, vcc, 0, v2 ; GFX9-NEXT: v_sub_co_u32_e32 v6, vcc, 0, v2
; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, 0, v3, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, 0, v3, vcc
; GFX9-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; GFX9-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
; GFX9-NEXT: v_rcp_f32_e32 v4, v4 ; GFX9-NEXT: v_rcp_f32_e32 v4, v4
; GFX9-NEXT: v_mov_b32_e32 v12, 0 ; GFX9-NEXT: v_mov_b32_e32 v12, 0
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; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v4, v7, v4, s[4:5] ; GFX9-NEXT: v_cndmask_b32_e64 v4, v7, v4, s[4:5]
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GFX9-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v1, v6, v9, s[4:5] ; GFX9-NEXT: v_cndmask_b32_e64 v1, v6, v9, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v4, v0, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, v0, v1, vcc
; GFX9-NEXT: ; implicit-def: $vgpr2_vgpr3 ; GFX9-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX9-NEXT: BB3_2: ; %Flow ; GFX9-NEXT: .LBB3_2: ; %Flow
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], s[8:9] ; GFX9-NEXT: s_or_saveexec_b64 s[4:5], s[8:9]
; GFX9-NEXT: s_xor_b64 exec, exec, s[4:5] ; GFX9-NEXT: s_xor_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz BB3_4 ; GFX9-NEXT: s_cbranch_execz .LBB3_4
; GFX9-NEXT: ; %bb.3: ; GFX9-NEXT: ; %bb.3:
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v2 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v2
; GFX9-NEXT: v_sub_u32_e32 v3, 0, v2 ; GFX9-NEXT: v_sub_u32_e32 v3, 0, v2
; GFX9-NEXT: v_mov_b32_e32 v5, 0 ; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_mul_lo_u32 v3, v3, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, v3, v1
; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX9-NEXT: v_mul_lo_u32 v1, v1, v2 ; GFX9-NEXT: v_mul_lo_u32 v1, v1, v2
; GFX9-NEXT: v_sub_u32_e32 v0, v0, v1 ; GFX9-NEXT: v_sub_u32_e32 v0, v0, v1
; GFX9-NEXT: v_sub_u32_e32 v1, v0, v2 ; GFX9-NEXT: v_sub_u32_e32 v1, v0, v2
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 ; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX9-NEXT: v_sub_u32_e32 v1, v0, v2 ; GFX9-NEXT: v_sub_u32_e32 v1, v0, v2
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 ; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
; GFX9-NEXT: v_cndmask_b32_e32 v4, v0, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, v0, v1, vcc
; GFX9-NEXT: BB3_4: ; GFX9-NEXT: .LBB3_4:
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: v_mov_b32_e32 v0, v4 ; GFX9-NEXT: v_mov_b32_e32 v0, v4
; GFX9-NEXT: v_mov_b32_e32 v1, v5 ; GFX9-NEXT: v_mov_b32_e32 v1, v5
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
%d = urem i64 %a, %b %d = urem i64 %a, %b
ret i64 %d ret i64 %d
} }
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_or_b32_e32 v5, v1, v3 ; GFX9-NEXT: v_or_b32_e32 v5, v1, v3
; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5] ; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
; GFX9-NEXT: ; implicit-def: $vgpr6_vgpr7 ; GFX9-NEXT: ; implicit-def: $vgpr6_vgpr7
; GFX9-NEXT: ; implicit-def: $vgpr4_vgpr5 ; GFX9-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[10:11], exec, s[4:5] ; GFX9-NEXT: s_xor_b64 s[10:11], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz BB8_2 ; GFX9-NEXT: s_cbranch_execz .LBB8_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: v_ashrrev_i32_e32 v4, 31, v3 ; GFX9-NEXT: v_ashrrev_i32_e32 v4, 31, v3
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v4, vcc
; GFX9-NEXT: v_xor_b32_e32 v3, v3, v4 ; GFX9-NEXT: v_xor_b32_e32 v3, v3, v4
; GFX9-NEXT: v_xor_b32_e32 v2, v2, v4 ; GFX9-NEXT: v_xor_b32_e32 v2, v2, v4
; GFX9-NEXT: v_cvt_f32_u32_e32 v5, v2 ; GFX9-NEXT: v_cvt_f32_u32_e32 v5, v2
; GFX9-NEXT: v_cvt_f32_u32_e32 v6, v3 ; GFX9-NEXT: v_cvt_f32_u32_e32 v6, v3
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; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX9-NEXT: v_xor_b32_e32 v0, v0, v7 ; GFX9-NEXT: v_xor_b32_e32 v0, v0, v7
; GFX9-NEXT: v_subb_co_u32_e64 v5, s[8:9], v6, v8, s[8:9] ; GFX9-NEXT: v_subb_co_u32_e64 v5, s[8:9], v6, v8, s[8:9]
; GFX9-NEXT: v_xor_b32_e32 v1, v1, v7 ; GFX9-NEXT: v_xor_b32_e32 v1, v1, v7
; GFX9-NEXT: v_sub_co_u32_e32 v6, vcc, v0, v7 ; GFX9-NEXT: v_sub_co_u32_e32 v6, vcc, v0, v7
; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, v1, v7, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, v1, v7, vcc
; GFX9-NEXT: ; implicit-def: $vgpr2_vgpr3 ; GFX9-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX9-NEXT: BB8_2: ; %Flow ; GFX9-NEXT: .LBB8_2: ; %Flow
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], s[10:11] ; GFX9-NEXT: s_or_saveexec_b64 s[4:5], s[10:11]
; GFX9-NEXT: s_xor_b64 exec, exec, s[4:5] ; GFX9-NEXT: s_xor_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz BB8_4 ; GFX9-NEXT: s_cbranch_execz .LBB8_4
; GFX9-NEXT: ; %bb.3: ; GFX9-NEXT: ; %bb.3:
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v2 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v2
; GFX9-NEXT: v_sub_u32_e32 v3, 0, v2 ; GFX9-NEXT: v_sub_u32_e32 v3, 0, v2
; GFX9-NEXT: v_mov_b32_e32 v5, 0 ; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: v_mov_b32_e32 v7, v5 ; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_mul_lo_u32 v3, v3, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, v3, v1
; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX9-NEXT: v_mul_lo_u32 v3, v1, v2 ; GFX9-NEXT: v_mul_lo_u32 v3, v1, v2
; GFX9-NEXT: v_add_u32_e32 v4, 1, v1 ; GFX9-NEXT: v_add_u32_e32 v4, 1, v1
; GFX9-NEXT: v_sub_u32_e32 v0, v0, v3 ; GFX9-NEXT: v_sub_u32_e32 v0, v0, v3
; GFX9-NEXT: v_sub_u32_e32 v3, v0, v2 ; GFX9-NEXT: v_sub_u32_e32 v3, v0, v2
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 ; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX9-NEXT: v_sub_u32_e32 v3, v0, v2 ; GFX9-NEXT: v_sub_u32_e32 v3, v0, v2
; GFX9-NEXT: v_add_u32_e32 v4, 1, v1 ; GFX9-NEXT: v_add_u32_e32 v4, 1, v1
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 ; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
; GFX9-NEXT: v_cndmask_b32_e32 v6, v0, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v6, v0, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v4, v1, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, v1, v4, vcc
; GFX9-NEXT: BB8_4: ; GFX9-NEXT: .LBB8_4:
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: v_mov_b32_e32 v0, v4 ; GFX9-NEXT: v_mov_b32_e32 v0, v4
; GFX9-NEXT: v_mov_b32_e32 v1, v5 ; GFX9-NEXT: v_mov_b32_e32 v1, v5
; GFX9-NEXT: v_mov_b32_e32 v2, v6 ; GFX9-NEXT: v_mov_b32_e32 v2, v6
; GFX9-NEXT: v_mov_b32_e32 v3, v7 ; GFX9-NEXT: v_mov_b32_e32 v3, v7
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
%d = sdiv i64 %a, %b %d = sdiv i64 %a, %b
%r = srem i64 %a, %b %r = srem i64 %a, %b
%ins.0 = insertelement <2 x i64> undef, i64 %d, i32 0 %ins.0 = insertelement <2 x i64> undef, i64 %d, i32 0
%ins.1 = insertelement <2 x i64> %ins.0, i64 %r, i32 1 %ins.1 = insertelement <2 x i64> %ins.0, i64 %r, i32 1
ret <2 x i64> %ins.1 ret <2 x i64> %ins.1
} }
define <2 x i64> @udivrem64(i64 %a, i64 %b) { define <2 x i64> @udivrem64(i64 %a, i64 %b) {
; GFX9-LABEL: udivrem64: ; GFX9-LABEL: udivrem64:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_or_b32_e32 v5, v1, v3 ; GFX9-NEXT: v_or_b32_e32 v5, v1, v3
; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5] ; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
; GFX9-NEXT: ; implicit-def: $vgpr6_vgpr7 ; GFX9-NEXT: ; implicit-def: $vgpr6_vgpr7
; GFX9-NEXT: ; implicit-def: $vgpr4_vgpr5 ; GFX9-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GFX9-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz BB9_2 ; GFX9-NEXT: s_cbranch_execz .LBB9_2
; GFX9-NEXT: ; %bb.1: ; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: v_cvt_f32_u32_e32 v4, v2 ; GFX9-NEXT: v_cvt_f32_u32_e32 v4, v2
; GFX9-NEXT: v_cvt_f32_u32_e32 v5, v3 ; GFX9-NEXT: v_cvt_f32_u32_e32 v5, v3
; GFX9-NEXT: v_sub_co_u32_e32 v6, vcc, 0, v2 ; GFX9-NEXT: v_sub_co_u32_e32 v6, vcc, 0, v2
; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, 0, v3, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, 0, v3, vcc
; GFX9-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; GFX9-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
; GFX9-NEXT: v_rcp_f32_e32 v4, v4 ; GFX9-NEXT: v_rcp_f32_e32 v4, v4
; GFX9-NEXT: v_mov_b32_e32 v12, 0 ; GFX9-NEXT: v_mov_b32_e32 v12, 0
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; GFX9-NEXT: v_cndmask_b32_e64 v6, v13, v11, s[6:7] ; GFX9-NEXT: v_cndmask_b32_e64 v6, v13, v11, s[6:7]
; GFX9-NEXT: v_cndmask_b32_e32 v7, v1, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v7, v1, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v1, v8, v2, s[6:7] ; GFX9-NEXT: v_cndmask_b32_e64 v1, v8, v2, s[6:7]
; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v10, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v10, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v6, v0, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v6, v0, v1, vcc
; GFX9-NEXT: ; implicit-def: $vgpr2_vgpr3 ; GFX9-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX9-NEXT: BB9_2: ; %Flow ; GFX9-NEXT: .LBB9_2: ; %Flow
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], s[8:9] ; GFX9-NEXT: s_or_saveexec_b64 s[4:5], s[8:9]
; GFX9-NEXT: s_xor_b64 exec, exec, s[4:5] ; GFX9-NEXT: s_xor_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz BB9_4 ; GFX9-NEXT: s_cbranch_execz .LBB9_4
; GFX9-NEXT: ; %bb.3: ; GFX9-NEXT: ; %bb.3:
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v2 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v2
; GFX9-NEXT: v_sub_u32_e32 v3, 0, v2 ; GFX9-NEXT: v_sub_u32_e32 v3, 0, v2
; GFX9-NEXT: v_mov_b32_e32 v5, 0 ; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: v_mov_b32_e32 v7, v5 ; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_mul_lo_u32 v3, v3, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, v3, v1
; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX9-NEXT: v_mul_lo_u32 v3, v1, v2 ; GFX9-NEXT: v_mul_lo_u32 v3, v1, v2
; GFX9-NEXT: v_add_u32_e32 v4, 1, v1 ; GFX9-NEXT: v_add_u32_e32 v4, 1, v1
; GFX9-NEXT: v_sub_u32_e32 v0, v0, v3 ; GFX9-NEXT: v_sub_u32_e32 v0, v0, v3
; GFX9-NEXT: v_sub_u32_e32 v3, v0, v2 ; GFX9-NEXT: v_sub_u32_e32 v3, v0, v2
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 ; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX9-NEXT: v_sub_u32_e32 v3, v0, v2 ; GFX9-NEXT: v_sub_u32_e32 v3, v0, v2
; GFX9-NEXT: v_add_u32_e32 v4, 1, v1 ; GFX9-NEXT: v_add_u32_e32 v4, 1, v1
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 ; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
; GFX9-NEXT: v_cndmask_b32_e32 v6, v0, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v6, v0, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v4, v1, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, v1, v4, vcc
; GFX9-NEXT: BB9_4: ; GFX9-NEXT: .LBB9_4:
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: v_mov_b32_e32 v0, v4 ; GFX9-NEXT: v_mov_b32_e32 v0, v4
; GFX9-NEXT: v_mov_b32_e32 v1, v5 ; GFX9-NEXT: v_mov_b32_e32 v1, v5
; GFX9-NEXT: v_mov_b32_e32 v2, v6 ; GFX9-NEXT: v_mov_b32_e32 v2, v6
; GFX9-NEXT: v_mov_b32_e32 v3, v7 ; GFX9-NEXT: v_mov_b32_e32 v3, v7
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
%d = udiv i64 %a, %b %d = udiv i64 %a, %b
%r = urem i64 %a, %b %r = urem i64 %a, %b
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llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GCN %s
%struct.ByValStruct = type { [4 x i32] } %struct.ByValStruct = type { [4 x i32] }
; Make sure the offset is folded and function's frame register is used ; Make sure the offset is folded and function's frame register is used
; rather than the global scratch wave offset. ; rather than the global scratch wave offset.
; GCN-LABEL: {{^}}void_func_byval_struct_use_outside_entry_block: ; GCN-LABEL: {{^}}void_func_byval_struct_use_outside_entry_block:
; GCN-NOT: v_lshrrev_b32 ; GCN-NOT: v_lshrrev_b32
; GCN-NOT: s_sub_u32 ; GCN-NOT: s_sub_u32
; GCN: s_and_saveexec_b64 ; GCN: s_and_saveexec_b64
; GCN: s_cbranch_execz [[BB1:BB[0-9]+_[0-9]+]] ; GCN: s_cbranch_execz [[BB1:.LBB[0-9]+_[0-9]+]]
; GCN: buffer_load_dword [[LOAD0:v[0-9]+]], off, s[0:3], s32 glc{{$}} ; GCN: buffer_load_dword [[LOAD0:v[0-9]+]], off, s[0:3], s32 glc{{$}}
; GCN-NOT: s32 ; GCN-NOT: s32
; GCN: buffer_store_dword [[LOAD0]], off, s[0:3], s32{{$}} ; GCN: buffer_store_dword [[LOAD0]], off, s[0:3], s32{{$}}
; GCN-NOT: s32 ; GCN-NOT: s32
; GCN: buffer_load_dword [[LOAD1:v[0-9]+]], off, s[0:3], s32 offset:16 glc{{$}} ; GCN: buffer_load_dword [[LOAD1:v[0-9]+]], off, s[0:3], s32 offset:16 glc{{$}}
; GCN-NOT: s32 ; GCN-NOT: s32
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llvm/test/CodeGen/AMDGPU/call-skip.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii < %s | FileCheck -enable-var-scope -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
; A call should be skipped if all lanes are zero, since we don't know ; A call should be skipped if all lanes are zero, since we don't know
; what side effects should be avoided inside the call. ; what side effects should be avoided inside the call.
define hidden void @func() #1 { define hidden void @func() #1 {
ret void ret void
} }
; GCN-LABEL: {{^}}if_call: ; GCN-LABEL: {{^}}if_call:
; GCN: s_and_saveexec_b64 ; GCN: s_and_saveexec_b64
; GCN-NEXT: s_cbranch_execz [[END:BB[0-9]+_[0-9]+]] ; GCN-NEXT: s_cbranch_execz [[END:.LBB[0-9]+_[0-9]+]]
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
; GCN: [[END]]: ; GCN: [[END]]:
define void @if_call(i32 %flag) #0 { define void @if_call(i32 %flag) #0 {
%cc = icmp eq i32 %flag, 0 %cc = icmp eq i32 %flag, 0
br i1 %cc, label %call, label %end br i1 %cc, label %call, label %end
call: call:
call void @func() call void @func()
br label %end br label %end
end: end:
ret void ret void
} }
; GCN-LABEL: {{^}}if_asm: ; GCN-LABEL: {{^}}if_asm:
; GCN: s_and_saveexec_b64 ; GCN: s_and_saveexec_b64
; GCN-NEXT: s_cbranch_execz [[END:BB[0-9]+_[0-9]+]] ; GCN-NEXT: s_cbranch_execz [[END:.LBB[0-9]+_[0-9]+]]
; GCN: ; sample asm ; GCN: ; sample asm
; GCN: [[END]]: ; GCN: [[END]]:
define void @if_asm(i32 %flag) #0 { define void @if_asm(i32 %flag) #0 {
%cc = icmp eq i32 %flag, 0 %cc = icmp eq i32 %flag, 0
br i1 %cc, label %call, label %end br i1 %cc, label %call, label %end
call: call:
call void asm sideeffect "; sample asm", ""() call void asm sideeffect "; sample asm", ""()
br label %end br label %end
end: end:
ret void ret void
} }
; GCN-LABEL: {{^}}if_call_kernel: ; GCN-LABEL: {{^}}if_call_kernel:
; GCN: s_and_saveexec_b64 ; GCN: s_and_saveexec_b64
; GCN-NEXT: s_cbranch_execz BB3_2 ; GCN-NEXT: s_cbranch_execz .LBB3_2
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
define amdgpu_kernel void @if_call_kernel() #0 { define amdgpu_kernel void @if_call_kernel() #0 {
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%cc = icmp eq i32 %id, 0 %cc = icmp eq i32 %id, 0
br i1 %cc, label %call, label %end br i1 %cc, label %call, label %end
call: call:
call void @func() call void @func()
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llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -verify-machineinstrs -O0 < %s ; RUN: llc -march=amdgcn -verify-machineinstrs -O0 < %s
; GCN-LABEL: {{^}}test_loop: ; GCN-LABEL: {{^}}test_loop:
; GCN: s_and_b64 s[0:1], exec, -1 ; GCN: s_and_b64 s[0:1], exec, -1
; GCN: [[LABEL:BB[0-9]+_[0-9]+]]: ; %for.body{{$}} ; GCN: [[LABEL:.LBB[0-9]+_[0-9]+]]: ; %for.body{{$}}
; GCN: ds_read_b32 ; GCN: ds_read_b32
; GCN: ds_write_b32 ; GCN: ds_write_b32
; GCN: s_cbranch_vccnz [[LABEL]] ; GCN: s_cbranch_vccnz [[LABEL]]
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @test_loop(float addrspace(3)* %ptr, i32 %n) nounwind { define amdgpu_kernel void @test_loop(float addrspace(3)* %ptr, i32 %n) nounwind {
entry: entry:
%cmp = icmp eq i32 %n, -1 %cmp = icmp eq i32 %n, -1
br i1 %cmp, label %for.exit, label %for.body br i1 %cmp, label %for.exit, label %for.body
for.exit: for.exit:
ret void ret void
for.body: for.body:
%indvar = phi i32 [ %inc, %for.body ], [ 0, %entry ] %indvar = phi i32 [ %inc, %for.body ], [ 0, %entry ]
%tmp = add i32 %indvar, 32 %tmp = add i32 %indvar, 32
%arrayidx = getelementptr float, float addrspace(3)* %ptr, i32 %tmp %arrayidx = getelementptr float, float addrspace(3)* %ptr, i32 %tmp
%vecload = load float, float addrspace(3)* %arrayidx, align 4 %vecload = load float, float addrspace(3)* %arrayidx, align 4
%add = fadd float %vecload, 1.0 %add = fadd float %vecload, 1.0
store float %add, float addrspace(3)* %arrayidx, align 8 store float %add, float addrspace(3)* %arrayidx, align 8
%inc = add i32 %indvar, 1 %inc = add i32 %indvar, 1
br label %for.body br label %for.body
} }
; GCN-LABEL: @loop_const_true ; GCN-LABEL: @loop_const_true
; GCN: [[LABEL:BB[0-9]+_[0-9]+]]: ; GCN: [[LABEL:.LBB[0-9]+_[0-9]+]]:
; GCN: ds_read_b32 ; GCN: ds_read_b32
; GCN: ds_write_b32 ; GCN: ds_write_b32
; GCN: s_branch [[LABEL]] ; GCN: s_branch [[LABEL]]
define amdgpu_kernel void @loop_const_true(float addrspace(3)* %ptr, i32 %n) nounwind { define amdgpu_kernel void @loop_const_true(float addrspace(3)* %ptr, i32 %n) nounwind {
entry: entry:
br label %for.body br label %for.body
for.exit: for.exit:
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Linesfor.body:
br i1 undef, label %for.body, label %for.exit br i1 undef, label %for.body, label %for.exit
} }
; GCN-LABEL: {{^}}loop_arg_0: ; GCN-LABEL: {{^}}loop_arg_0:
; GCN: v_and_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}} ; GCN: v_and_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
; GCN: v_cmp_eq_u32{{[^,]*}}, 1, ; GCN: v_cmp_eq_u32{{[^,]*}}, 1,
; GCN: s_add_i32 s2, s0, 0x80 ; GCN: s_add_i32 s2, s0, 0x80
; GCN: [[LOOPBB:BB[0-9]+_[0-9]+]] ; GCN: [[LOOPBB:.LBB[0-9]+_[0-9]+]]
; GCN: _add_i32_e32 v0, vcc, 4, v0 ; GCN: _add_i32_e32 v0, vcc, 4, v0
; GCN: s_cbranch_{{vccz|vccnz}} [[LOOPBB]] ; GCN: s_cbranch_{{vccz|vccnz}} [[LOOPBB]]
; GCN-NEXT: ; %bb.2 ; GCN-NEXT: ; %bb.2
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @loop_arg_0(float addrspace(3)* %ptr, i32 %n) nounwind { define amdgpu_kernel void @loop_arg_0(float addrspace(3)* %ptr, i32 %n) nounwind {
entry: entry:
%cond = load volatile i1, i1 addrspace(3)* null %cond = load volatile i1, i1 addrspace(3)* null
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llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll

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; OPT-GFX9: br ; OPT-GFX9: br
; OPT-GFX9: %sunkaddr = getelementptr i8, i8* %0, i64 28 ; OPT-GFX9: %sunkaddr = getelementptr i8, i8* %0, i64 28
; OPT-GFX9: %1 = bitcast i8* %sunkaddr to i32* ; OPT-GFX9: %1 = bitcast i8* %sunkaddr to i32*
; OPT-GFX9: load i32, i32* %1 ; OPT-GFX9: load i32, i32* %1
; GCN-LABEL: {{^}}test_no_sink_flat_small_offset_i32: ; GCN-LABEL: {{^}}test_no_sink_flat_small_offset_i32:
; GCN: flat_load_dword ; GCN: flat_load_dword
; GCN: {{^}}BB0_2: ; GCN: {{^}}.LBB0_2:
define amdgpu_kernel void @test_no_sink_flat_small_offset_i32(i32* %out, i32* %in, i32 %cond) { define amdgpu_kernel void @test_no_sink_flat_small_offset_i32(i32* %out, i32* %in, i32 %cond) {
entry: entry:
%out.gep = getelementptr i32, i32* %out, i64 999999 %out.gep = getelementptr i32, i32* %out, i64 999999
%in.gep = getelementptr i32, i32* %in, i64 7 %in.gep = getelementptr i32, i32* %in, i64 7
%tmp0 = icmp eq i32 %cond, 0 %tmp0 = icmp eq i32 %cond, 0
br i1 %tmp0, label %endif, label %if br i1 %tmp0, label %endif, label %if
if: if:
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llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll

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; ;
; GCN-LABEL: test_sink_small_offset_global_atomic_csub_i32: ; GCN-LABEL: test_sink_small_offset_global_atomic_csub_i32:
; GCN: ; %bb.0: ; %entry ; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GCN-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0 ; GCN-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
; GCN-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 ; GCN-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: s_and_saveexec_b32 s4, vcc_lo ; GCN-NEXT: s_and_saveexec_b32 s4, vcc_lo
; GCN-NEXT: s_cbranch_execz BB0_2 ; GCN-NEXT: s_cbranch_execz .LBB0_2
; GCN-NEXT: ; %bb.1: ; %if ; GCN-NEXT: ; %bb.1: ; %if
; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: v_mov_b32_e32 v1, 2 ; GCN-NEXT: v_mov_b32_e32 v1, 2
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: global_atomic_csub v0, v0, v1, s[2:3] offset:28 glc ; GCN-NEXT: global_atomic_csub v0, v0, v1, s[2:3] offset:28 glc
; GCN-NEXT: BB0_2: ; %endif ; GCN-NEXT: .LBB0_2: ; %endif
; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s4 ; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GCN-NEXT: v_mov_b32_e32 v1, 0x3d0800 ; GCN-NEXT: v_mov_b32_e32 v1, 0x3d0800
; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN-NEXT: global_store_dword v1, v0, s[0:1] offset:252 ; GCN-NEXT: global_store_dword v1, v0, s[0:1] offset:252
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
entry: entry:
%out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 999999 %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 999999
%in.gep = getelementptr i32, i32 addrspace(1)* %in, i32 7 %in.gep = getelementptr i32, i32 addrspace(1)* %in, i32 7
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llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx908.ll

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; ;
; GCN-LABEL: test_sink_small_offset_global_atomic_fadd_f32: ; GCN-LABEL: test_sink_small_offset_global_atomic_fadd_f32:
; GCN: ; %bb.0: ; %entry ; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GCN-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0 ; GCN-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_cbranch_execz BB0_2 ; GCN-NEXT: s_cbranch_execz .LBB0_2
; GCN-NEXT: ; %bb.1: ; %if ; GCN-NEXT: ; %bb.1: ; %if
; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: v_mov_b32_e32 v1, 2.0 ; GCN-NEXT: v_mov_b32_e32 v1, 2.0
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: global_atomic_add_f32 v0, v1, s[2:3] offset:28 ; GCN-NEXT: global_atomic_add_f32 v0, v1, s[2:3] offset:28
; GCN-NEXT: global_load_dword v0, v[0:1], off glc ; GCN-NEXT: global_load_dword v0, v[0:1], off glc
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: BB0_2: ; %endif ; GCN-NEXT: .LBB0_2: ; %endif
; GCN-NEXT: s_or_b64 exec, exec, s[4:5] ; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v1, 0x3d0000 ; GCN-NEXT: v_mov_b32_e32 v1, 0x3d0000
; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN-NEXT: global_store_dword v1, v0, s[0:1] offset:2300 ; GCN-NEXT: global_store_dword v1, v0, s[0:1] offset:2300
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
entry: entry:
%out.gep = getelementptr float, float addrspace(1)* %out, i32 999999 %out.gep = getelementptr float, float addrspace(1)* %out, i32 999999
%in.gep = getelementptr float, float addrspace(1)* %in, i32 7 %in.gep = getelementptr float, float addrspace(1)* %in, i32 7
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llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll

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; OPT: br i1 ; OPT: br i1
; GCN-LABEL: {{^}}test_sink_global_small_max_i32_ds_offset: ; GCN-LABEL: {{^}}test_sink_global_small_max_i32_ds_offset:
; GCN: s_and_saveexec_b64 ; GCN: s_and_saveexec_b64
; SICIVI: buffer_load_sbyte {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, s{{[0-9]+$}} ; SICIVI: buffer_load_sbyte {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, s{{[0-9]+$}}
; GFX9: v_mov_b32_e32 [[VOFFSET:v[0-9]+]], 0xf000{{$}} ; GFX9: v_mov_b32_e32 [[VOFFSET:v[0-9]+]], 0xf000{{$}}
; GFX9: global_load_sbyte {{v[0-9]+}}, [[VOFFSET]], {{s\[[0-9]+:[0-9]+\]}} offset:4095{{$}} ; GFX9: global_load_sbyte {{v[0-9]+}}, [[VOFFSET]], {{s\[[0-9]+:[0-9]+\]}} offset:4095{{$}}
; GCN: {{^}}BB1_2: ; GCN: {{^}}.LBB1_2:
; GCN: s_or_b64 exec ; GCN: s_or_b64 exec
define amdgpu_kernel void @test_sink_global_small_max_i32_ds_offset(i32 addrspace(1)* %out, i8 addrspace(1)* %in) { define amdgpu_kernel void @test_sink_global_small_max_i32_ds_offset(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
entry: entry:
%out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 99999 %out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 99999
%in.gep = getelementptr i8, i8 addrspace(1)* %in, i64 65535 %in.gep = getelementptr i8, i8 addrspace(1)* %in, i64 65535
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
%tmp0 = icmp eq i32 %tid, 0 %tmp0 = icmp eq i32 %tid, 0
br i1 %tmp0, label %endif, label %if br i1 %tmp0, label %endif, label %if
Show All 12 Linesdone:
ret void ret void
} }
; GCN-LABEL: {{^}}test_sink_global_small_max_mubuf_offset: ; GCN-LABEL: {{^}}test_sink_global_small_max_mubuf_offset:
; GCN: s_and_saveexec_b64 ; GCN: s_and_saveexec_b64
; SICIVI: buffer_load_sbyte {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:4095{{$}} ; SICIVI: buffer_load_sbyte {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:4095{{$}}
; GFX9: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}} ; GFX9: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}}
; GFX9: global_load_sbyte {{v[0-9]+}}, [[ZERO]], {{s\[[0-9]+:[0-9]+\]}} offset:4095{{$}} ; GFX9: global_load_sbyte {{v[0-9]+}}, [[ZERO]], {{s\[[0-9]+:[0-9]+\]}} offset:4095{{$}}
; GCN: {{^}}BB2_2: ; GCN: {{^}}.LBB2_2:
; GCN: s_or_b64 exec ; GCN: s_or_b64 exec
define amdgpu_kernel void @test_sink_global_small_max_mubuf_offset(i32 addrspace(1)* %out, i8 addrspace(1)* %in) { define amdgpu_kernel void @test_sink_global_small_max_mubuf_offset(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
entry: entry:
%out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 1024 %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 1024
%in.gep = getelementptr i8, i8 addrspace(1)* %in, i64 4095 %in.gep = getelementptr i8, i8 addrspace(1)* %in, i64 4095
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
%tmp0 = icmp eq i32 %tid, 0 %tmp0 = icmp eq i32 %tid, 0
br i1 %tmp0, label %endif, label %if br i1 %tmp0, label %endif, label %if
Show All 12 Linesdone:
ret void ret void
} }
; GCN-LABEL: {{^}}test_sink_global_small_max_plus_1_mubuf_offset: ; GCN-LABEL: {{^}}test_sink_global_small_max_plus_1_mubuf_offset:
; GCN: s_and_saveexec_b64 ; GCN: s_and_saveexec_b64
; SICIVI: buffer_load_sbyte {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, s{{[0-9]+$}} ; SICIVI: buffer_load_sbyte {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, s{{[0-9]+$}}
; GFX9: v_mov_b32_e32 [[VOFFSET:v[0-9]+]], 0x1000{{$}} ; GFX9: v_mov_b32_e32 [[VOFFSET:v[0-9]+]], 0x1000{{$}}
; GFX9: global_load_sbyte {{v[0-9]+}}, [[VOFFSET]], {{s\[[0-9]+:[0-9]+\]$}} ; GFX9: global_load_sbyte {{v[0-9]+}}, [[VOFFSET]], {{s\[[0-9]+:[0-9]+\]$}}
; GCN: {{^}}BB3_2: ; GCN: {{^}}.LBB3_2:
; GCN: s_or_b64 exec ; GCN: s_or_b64 exec
define amdgpu_kernel void @test_sink_global_small_max_plus_1_mubuf_offset(i32 addrspace(1)* %out, i8 addrspace(1)* %in) { define amdgpu_kernel void @test_sink_global_small_max_plus_1_mubuf_offset(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
entry: entry:
%out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 99999 %out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 99999
%in.gep = getelementptr i8, i8 addrspace(1)* %in, i64 4096 %in.gep = getelementptr i8, i8 addrspace(1)* %in, i64 4096
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
%tmp0 = icmp eq i32 %tid, 0 %tmp0 = icmp eq i32 %tid, 0
br i1 %tmp0, label %endif, label %if br i1 %tmp0, label %endif, label %if
Show All 16 Lines
; OPT-NOT: getelementptr [512 x i32] ; OPT-NOT: getelementptr [512 x i32]
; OPT: br i1 ; OPT: br i1
; OPT: getelementptr i8, ; OPT: getelementptr i8,
; GCN-LABEL: {{^}}test_sink_scratch_small_offset_i32: ; GCN-LABEL: {{^}}test_sink_scratch_small_offset_i32:
; GCN: s_and_saveexec_b64 ; GCN: s_and_saveexec_b64
; GCN: buffer_store_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:4092{{$}} ; GCN: buffer_store_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:4092{{$}}
; GCN: buffer_load_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:4092 glc{{$}} ; GCN: buffer_load_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:4092 glc{{$}}
; GCN: {{^}}BB4_2: ; GCN: {{^}}.LBB4_2:
define amdgpu_kernel void @test_sink_scratch_small_offset_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %arg) { define amdgpu_kernel void @test_sink_scratch_small_offset_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %arg) {
entry: entry:
%alloca = alloca [512 x i32], align 4, addrspace(5) %alloca = alloca [512 x i32], align 4, addrspace(5)
%out.gep.0 = getelementptr i32, i32 addrspace(1)* %out, i64 999998 %out.gep.0 = getelementptr i32, i32 addrspace(1)* %out, i64 999998
%out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i64 999999 %out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i64 999999
%add.arg = add i32 %arg, 8 %add.arg = add i32 %arg, 8
%alloca.gep = getelementptr [512 x i32], [512 x i32] addrspace(5)* %alloca, i32 0, i32 1022 %alloca.gep = getelementptr [512 x i32], [512 x i32] addrspace(5)* %alloca, i32 0, i32 1022
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
Show All 23 Lines
; OPT: getelementptr i8, ; OPT: getelementptr i8,
; GCN-LABEL: {{^}}test_sink_scratch_small_offset_i32_reserved: ; GCN-LABEL: {{^}}test_sink_scratch_small_offset_i32_reserved:
; GCN: s_and_saveexec_b64 ; GCN: s_and_saveexec_b64
; GCN: v_mov_b32_e32 [[BASE_FI0:v[0-9]+]], 4 ; GCN: v_mov_b32_e32 [[BASE_FI0:v[0-9]+]], 4
; GCN: buffer_store_dword {{v[0-9]+}}, [[BASE_FI0]], {{s\[[0-9]+:[0-9]+\]}}, 0 offen offset:4092{{$}} ; GCN: buffer_store_dword {{v[0-9]+}}, [[BASE_FI0]], {{s\[[0-9]+:[0-9]+\]}}, 0 offen offset:4092{{$}}
; GCN: v_mov_b32_e32 [[BASE_FI1:v[0-9]+]], 4 ; GCN: v_mov_b32_e32 [[BASE_FI1:v[0-9]+]], 4
; GCN: buffer_load_dword {{v[0-9]+}}, [[BASE_FI1]], {{s\[[0-9]+:[0-9]+\]}}, 0 offen offset:4092 glc{{$}} ; GCN: buffer_load_dword {{v[0-9]+}}, [[BASE_FI1]], {{s\[[0-9]+:[0-9]+\]}}, 0 offen offset:4092 glc{{$}}
; GCN: {{^BB[0-9]+}}_2: ; GCN: {{^.LBB[0-9]+}}_2:
define amdgpu_kernel void @test_sink_scratch_small_offset_i32_reserved(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %arg) { define amdgpu_kernel void @test_sink_scratch_small_offset_i32_reserved(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %arg) {
entry: entry:
%alloca = alloca [512 x i32], align 4, addrspace(5) %alloca = alloca [512 x i32], align 4, addrspace(5)
%out.gep.0 = getelementptr i32, i32 addrspace(1)* %out, i64 999998 %out.gep.0 = getelementptr i32, i32 addrspace(1)* %out, i64 999998
%out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i64 999999 %out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i64 999999
%add.arg = add i32 %arg, 8 %add.arg = add i32 %arg, 8
%alloca.gep = getelementptr [512 x i32], [512 x i32] addrspace(5)* %alloca, i32 0, i32 1023 %alloca.gep = getelementptr [512 x i32], [512 x i32] addrspace(5)* %alloca, i32 0, i32 1023
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; OPT: %alloca.gep = getelementptr [512 x i32], [512 x i32] addrspace(5)* %alloca, i32 0, i32 1024 ; OPT: %alloca.gep = getelementptr [512 x i32], [512 x i32] addrspace(5)* %alloca, i32 0, i32 1024
; OPT: br i1 ; OPT: br i1
; OPT-NOT: ptrtoint ; OPT-NOT: ptrtoint
; GCN-LABEL: {{^}}test_no_sink_scratch_large_offset_i32: ; GCN-LABEL: {{^}}test_no_sink_scratch_large_offset_i32:
; GCN: s_and_saveexec_b64 ; GCN: s_and_saveexec_b64
; GCN: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offen{{$}} ; GCN: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offen{{$}}
; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offen glc{{$}} ; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offen glc{{$}}
; GCN: {{^BB[0-9]+}}_2: ; GCN: {{^.LBB[0-9]+}}_2:
define amdgpu_kernel void @test_no_sink_scratch_large_offset_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %arg) { define amdgpu_kernel void @test_no_sink_scratch_large_offset_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %arg) {
entry: entry:
%alloca = alloca [512 x i32], align 4, addrspace(5) %alloca = alloca [512 x i32], align 4, addrspace(5)
%out.gep.0 = getelementptr i32, i32 addrspace(1)* %out, i64 999998 %out.gep.0 = getelementptr i32, i32 addrspace(1)* %out, i64 999998
%out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i64 999999 %out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i64 999999
%add.arg = add i32 %arg, 8 %add.arg = add i32 %arg, 8
%alloca.gep = getelementptr [512 x i32], [512 x i32] addrspace(5)* %alloca, i32 0, i32 1024 %alloca.gep = getelementptr [512 x i32], [512 x i32] addrspace(5)* %alloca, i32 0, i32 1024
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
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done: done:
ret void ret void
} }
; GCN-LABEL: {{^}}test_sink_global_vreg_sreg_i32: ; GCN-LABEL: {{^}}test_sink_global_vreg_sreg_i32:
; GCN: s_and_saveexec_b64 ; GCN: s_and_saveexec_b64
; CI: buffer_load_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; CI: buffer_load_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
; VI: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}] ; VI: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}]
; GCN: {{^BB[0-9]+}}_2: ; GCN: {{^.LBB[0-9]+}}_2:
define amdgpu_kernel void @test_sink_global_vreg_sreg_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %offset) { define amdgpu_kernel void @test_sink_global_vreg_sreg_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %offset) {
entry: entry:
%offset.ext = zext i32 %offset to i64 %offset.ext = zext i32 %offset to i64
%out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 999999 %out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 999999
%in.gep = getelementptr i32, i32 addrspace(1)* %in, i64 %offset.ext %in.gep = getelementptr i32, i32 addrspace(1)* %in, i64 %offset.ext
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
%tmp0 = icmp eq i32 %tid, 0 %tmp0 = icmp eq i32 %tid, 0
br i1 %tmp0, label %endif, label %if br i1 %tmp0, label %endif, label %if
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llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll

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; OPT: ret ; OPT: ret
; GCN-LABEL: {{^}}sink_ubfe_i32: ; GCN-LABEL: {{^}}sink_ubfe_i32:
; GCN-NOT: lshr ; GCN-NOT: lshr
; GCN: s_cbranch_scc{{[0-1]}} ; GCN: s_cbranch_scc{{[0-1]}}
; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x70008 ; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x70008
; GCN: BB0_3: ; GCN: .LBB0_3:
; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80008 ; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80008
; GCN: buffer_store_dword ; GCN: buffer_store_dword
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @sink_ubfe_i32(i32 addrspace(1)* %out, i32 %arg1) #0 { define amdgpu_kernel void @sink_ubfe_i32(i32 addrspace(1)* %out, i32 %arg1) #0 {
entry: entry:
%shr = lshr i32 %arg1, 8 %shr = lshr i32 %arg1, 8
br i1 undef, label %bb0, label %bb1 br i1 undef, label %bb0, label %bb1
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; OPT: %1 = lshr i16 %arg1, 4 ; OPT: %1 = lshr i16 %arg1, 4
; OPT-NEXT: %val1 = and i16 %1, 127 ; OPT-NEXT: %val1 = and i16 %1, 127
; OPT: br label ; OPT: br label
; OPT: ret: ; OPT: ret:
; OPT: store ; OPT: store
; OPT: ret ; OPT: ret
; For GFX8: since i16 is legal type, we cannot sink lshr into BBs. ; For GFX8: since i16 is legal type, we cannot sink lshr into .LBBs.
; GCN-LABEL: {{^}}sink_ubfe_i16: ; GCN-LABEL: {{^}}sink_ubfe_i16:
; GCN-NOT: lshr ; GCN-NOT: lshr
; VI: s_load_dword [[ARG:s[0-9]+]], s[0:1], 0x2c ; VI: s_load_dword [[ARG:s[0-9]+]], s[0:1], 0x2c
; VI: s_bfe_u32 [[BFE:s[0-9]+]], [[ARG]], 0xc0004 ; VI: s_bfe_u32 [[BFE:s[0-9]+]], [[ARG]], 0xc0004
; GCN: s_cbranch_scc{{[0-1]}} ; GCN: s_cbranch_scc{{[0-1]}}
; SI: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x70004 ; SI: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x70004
; VI: v_mov_b32_e32 v{{[0-9]+}}, 0x7f ; VI: v_mov_b32_e32 v{{[0-9]+}}, 0x7f
; GCN: BB2_3: ; GCN: .LBB2_3:
; SI: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80004 ; SI: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80004
; VI: v_mov_b32_e32 v{{[0-9]+}}, 0xff ; VI: v_mov_b32_e32 v{{[0-9]+}}, 0xff
; GCN: buffer_store_short ; GCN: buffer_store_short
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @sink_ubfe_i16(i16 addrspace(1)* %out, i16 %arg1) #0 { define amdgpu_kernel void @sink_ubfe_i16(i16 addrspace(1)* %out, i16 %arg1) #0 {
entry: entry:
%shr = lshr i16 %arg1, 4 %shr = lshr i16 %arg1, 4
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; OPT-NEXT: %val1 = and i64 %1, 127 ; OPT-NEXT: %val1 = and i64 %1, 127
; OPT: ret: ; OPT: ret:
; OPT: store ; OPT: store
; OPT: ret ; OPT: ret
; GCN-LABEL: {{^}}sink_ubfe_i64_span_midpoint: ; GCN-LABEL: {{^}}sink_ubfe_i64_span_midpoint:
; GCN: s_cbranch_scc{{[0-1]}} BB3_2 ; GCN: s_cbranch_scc{{[0-1]}} .LBB3_2
; GCN: v_alignbit_b32 v[[LO:[0-9]+]], s{{[0-9]+}}, v{{[0-9]+}}, 30 ; GCN: v_alignbit_b32 v[[LO:[0-9]+]], s{{[0-9]+}}, v{{[0-9]+}}, 30
; GCN: v_and_b32_e32 v{{[0-9]+}}, 0x7f, v[[LO]] ; GCN: v_and_b32_e32 v{{[0-9]+}}, 0x7f, v[[LO]]
; GCN: BB3_3: ; GCN: .LBB3_3:
; GCN: v_and_b32_e32 v{{[0-9]+}}, 0xff, v[[LO]] ; GCN: v_and_b32_e32 v{{[0-9]+}}, 0xff, v[[LO]]
; GCN: buffer_store_dwordx2 ; GCN: buffer_store_dwordx2
define amdgpu_kernel void @sink_ubfe_i64_span_midpoint(i64 addrspace(1)* %out, i64 %arg1) #0 { define amdgpu_kernel void @sink_ubfe_i64_span_midpoint(i64 addrspace(1)* %out, i64 %arg1) #0 {
entry: entry:
%shr = lshr i64 %arg1, 30 %shr = lshr i64 %arg1, 30
br i1 undef, label %bb0, label %bb1 br i1 undef, label %bb0, label %bb1
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; OPT-NEXT: %val1 = and i64 %1, 127 ; OPT-NEXT: %val1 = and i64 %1, 127
; OPT: ret: ; OPT: ret:
; OPT: store ; OPT: store
; OPT: ret ; OPT: ret
; GCN-LABEL: {{^}}sink_ubfe_i64_low32: ; GCN-LABEL: {{^}}sink_ubfe_i64_low32:
; GCN: s_cbranch_scc{{[0-1]}} BB4_2 ; GCN: s_cbranch_scc{{[0-1]}} .LBB4_2
; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x7000f ; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x7000f
; GCN: BB4_3: ; GCN: .LBB4_3:
; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x8000f ; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x8000f
; GCN: buffer_store_dwordx2 ; GCN: buffer_store_dwordx2
define amdgpu_kernel void @sink_ubfe_i64_low32(i64 addrspace(1)* %out, i64 %arg1) #0 { define amdgpu_kernel void @sink_ubfe_i64_low32(i64 addrspace(1)* %out, i64 %arg1) #0 {
entry: entry:
%shr = lshr i64 %arg1, 15 %shr = lshr i64 %arg1, 15
br i1 undef, label %bb0, label %bb1 br i1 undef, label %bb0, label %bb1
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; OPT: %1 = lshr i64 %arg1, 35 ; OPT: %1 = lshr i64 %arg1, 35
; OPT-NEXT: %val1 = and i64 %1, 127 ; OPT-NEXT: %val1 = and i64 %1, 127
; OPT: ret: ; OPT: ret:
; OPT: store ; OPT: store
; OPT: ret ; OPT: ret
; GCN-LABEL: {{^}}sink_ubfe_i64_high32: ; GCN-LABEL: {{^}}sink_ubfe_i64_high32:
; GCN: s_cbranch_scc{{[0-1]}} BB5_2 ; GCN: s_cbranch_scc{{[0-1]}} .LBB5_2
; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x70003 ; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x70003
; GCN: BB5_3: ; GCN: .LBB5_3:
; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80003 ; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80003
; GCN: buffer_store_dwordx2 ; GCN: buffer_store_dwordx2
define amdgpu_kernel void @sink_ubfe_i64_high32(i64 addrspace(1)* %out, i64 %arg1) #0 { define amdgpu_kernel void @sink_ubfe_i64_high32(i64 addrspace(1)* %out, i64 %arg1) #0 {
entry: entry:
%shr = lshr i64 %arg1, 35 %shr = lshr i64 %arg1, 35
br i1 undef, label %bb0, label %bb1 br i1 undef, label %bb0, label %bb1
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llvm/test/CodeGen/AMDGPU/collapse-endcf.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-remove-redundant-endcf < %s | FileCheck -enable-var-scope -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-remove-redundant-endcf < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
; GCN-LABEL: {{^}}simple_nested_if: ; GCN-LABEL: {{^}}simple_nested_if:
; GCN: s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9:]+\]]] ; GCN: s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9:]+\]]]
; GCN-NEXT: s_cbranch_execz [[ENDIF:BB[0-9_]+]] ; GCN-NEXT: s_cbranch_execz [[ENDIF:.LBB[0-9_]+]]
; GCN: s_and_b64 exec, exec, vcc ; GCN: s_and_b64 exec, exec, vcc
; GCN-NEXT: s_cbranch_execz [[ENDIF]] ; GCN-NEXT: s_cbranch_execz [[ENDIF]]
; GCN-NEXT: ; %bb.{{[0-9]+}}: ; GCN-NEXT: ; %bb.{{[0-9]+}}:
; GCN: store_dword ; GCN: store_dword
; GCN-NEXT: {{^}}[[ENDIF]]: ; GCN-NEXT: {{^}}[[ENDIF]]:
; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC]] ; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC]]
; GCN: ds_write_b32 ; GCN: ds_write_b32
; GCN: s_endpgm ; GCN: s_endpgm
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bb.outer.end: ; preds = %bb.outer.then, %bb.inner.then, %bb bb.outer.end: ; preds = %bb.outer.then, %bb.inner.then, %bb
store i32 3, i32 addrspace(3)* null store i32 3, i32 addrspace(3)* null
ret void ret void
} }
; GCN-LABEL: {{^}}uncollapsable_nested_if: ; GCN-LABEL: {{^}}uncollapsable_nested_if:
; GCN: s_and_saveexec_b64 [[SAVEEXEC_OUTER:s\[[0-9:]+\]]] ; GCN: s_and_saveexec_b64 [[SAVEEXEC_OUTER:s\[[0-9:]+\]]]
; GCN-NEXT: s_cbranch_execz [[ENDIF_OUTER:BB[0-9_]+]] ; GCN-NEXT: s_cbranch_execz [[ENDIF_OUTER:.LBB[0-9_]+]]
; GCN: s_and_saveexec_b64 [[SAVEEXEC_INNER:s\[[0-9:]+\]]] ; GCN: s_and_saveexec_b64 [[SAVEEXEC_INNER:s\[[0-9:]+\]]]
; GCN-NEXT: s_cbranch_execz [[ENDIF_INNER:BB[0-9_]+]] ; GCN-NEXT: s_cbranch_execz [[ENDIF_INNER:.LBB[0-9_]+]]
; GCN-NEXT: ; %bb.{{[0-9]+}}: ; GCN-NEXT: ; %bb.{{[0-9]+}}:
; GCN: store_dword ; GCN: store_dword
; GCN-NEXT: {{^}}[[ENDIF_INNER]]: ; GCN-NEXT: {{^}}[[ENDIF_INNER]]:
; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_INNER]] ; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_INNER]]
; GCN: store_dword ; GCN: store_dword
; GCN-NEXT: {{^}}[[ENDIF_OUTER]]: ; GCN-NEXT: {{^}}[[ENDIF_OUTER]]:
; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_OUTER]] ; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_OUTER]]
; GCN: ds_write_b32 ; GCN: ds_write_b32
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bb.outer.end: ; preds = %bb.inner.then, %bb bb.outer.end: ; preds = %bb.inner.then, %bb
store i32 3, i32 addrspace(3)* null store i32 3, i32 addrspace(3)* null
ret void ret void
} }
; GCN-LABEL: {{^}}nested_if_if_else: ; GCN-LABEL: {{^}}nested_if_if_else:
; GCN: s_and_saveexec_b64 [[SAVEEXEC_OUTER:s\[[0-9:]+\]]] ; GCN: s_and_saveexec_b64 [[SAVEEXEC_OUTER:s\[[0-9:]+\]]]
; GCN-NEXT: s_cbranch_execz [[ENDIF_OUTER:BB[0-9_]+]] ; GCN-NEXT: s_cbranch_execz [[ENDIF_OUTER:.LBB[0-9_]+]]
; GCN: s_and_saveexec_b64 [[SAVEEXEC_INNER:s\[[0-9:]+\]]] ; GCN: s_and_saveexec_b64 [[SAVEEXEC_INNER:s\[[0-9:]+\]]]
; GCN-NEXT: s_xor_b64 [[SAVEEXEC_INNER2:s\[[0-9:]+\]]], exec, [[SAVEEXEC_INNER]] ; GCN-NEXT: s_xor_b64 [[SAVEEXEC_INNER2:s\[[0-9:]+\]]], exec, [[SAVEEXEC_INNER]]
; GCN-NEXT: s_cbranch_execz [[THEN_INNER:BB[0-9_]+]] ; GCN-NEXT: s_cbranch_execz [[THEN_INNER:.LBB[0-9_]+]]
; GCN-NEXT: ; %bb.{{[0-9]+}}: ; GCN-NEXT: ; %bb.{{[0-9]+}}:
; GCN: store_dword ; GCN: store_dword
; GCN: {{^}}[[THEN_INNER]]: ; GCN: {{^}}[[THEN_INNER]]:
; GCN-NEXT: s_or_saveexec_b64 [[SAVEEXEC_INNER3:s\[[0-9:]+\]]], [[SAVEEXEC_INNER2]] ; GCN-NEXT: s_or_saveexec_b64 [[SAVEEXEC_INNER3:s\[[0-9:]+\]]], [[SAVEEXEC_INNER2]]
; GCN-NEXT: s_xor_b64 exec, exec, [[SAVEEXEC_INNER3]] ; GCN-NEXT: s_xor_b64 exec, exec, [[SAVEEXEC_INNER3]]
; GCN-NEXT: s_cbranch_execz [[ENDIF_OUTER]] ; GCN-NEXT: s_cbranch_execz [[ENDIF_OUTER]]
; GCN: store_dword ; GCN: store_dword
; GCN-NEXT: {{^}}[[ENDIF_OUTER]]: ; GCN-NEXT: {{^}}[[ENDIF_OUTER]]:
Show All 27 Lines
bb.outer.end: ; preds = %bb, %bb.then, %bb.else bb.outer.end: ; preds = %bb, %bb.then, %bb.else
store i32 3, i32 addrspace(3)* null store i32 3, i32 addrspace(3)* null
ret void ret void
} }
; GCN-LABEL: {{^}}nested_if_else_if: ; GCN-LABEL: {{^}}nested_if_else_if:
; GCN: s_and_saveexec_b64 [[SAVEEXEC_OUTER:s\[[0-9:]+\]]] ; GCN: s_and_saveexec_b64 [[SAVEEXEC_OUTER:s\[[0-9:]+\]]]
; GCN-NEXT: s_xor_b64 [[SAVEEXEC_OUTER2:s\[[0-9:]+\]]], exec, [[SAVEEXEC_OUTER]] ; GCN-NEXT: s_xor_b64 [[SAVEEXEC_OUTER2:s\[[0-9:]+\]]], exec, [[SAVEEXEC_OUTER]]
; GCN-NEXT: s_cbranch_execz [[THEN_OUTER:BB[0-9_]+]] ; GCN-NEXT: s_cbranch_execz [[THEN_OUTER:.LBB[0-9_]+]]
; GCN-NEXT: ; %bb.{{[0-9]+}}: ; GCN-NEXT: ; %bb.{{[0-9]+}}:
; GCN: store_dword ; GCN: store_dword
; GCN-NEXT: s_and_saveexec_b64 [[SAVEEXEC_INNER_IF_OUTER_ELSE:s\[[0-9:]+\]]] ; GCN-NEXT: s_and_saveexec_b64 [[SAVEEXEC_INNER_IF_OUTER_ELSE:s\[[0-9:]+\]]]
; GCN-NEXT: s_cbranch_execz [[THEN_OUTER_FLOW:BB[0-9_]+]] ; GCN-NEXT: s_cbranch_execz [[THEN_OUTER_FLOW:.LBB[0-9_]+]]
; GCN-NEXT: ; %bb.{{[0-9]+}}: ; GCN-NEXT: ; %bb.{{[0-9]+}}:
; GCN: store_dword ; GCN: store_dword
; GCN-NEXT: {{^}}[[THEN_OUTER_FLOW]]: ; GCN-NEXT: {{^}}[[THEN_OUTER_FLOW]]:
; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_INNER_IF_OUTER_ELSE]] ; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_INNER_IF_OUTER_ELSE]]
; GCN: {{^}}[[THEN_OUTER]]: ; GCN: {{^}}[[THEN_OUTER]]:
; GCN-NEXT: s_or_saveexec_b64 [[SAVEEXEC_OUTER3:s\[[0-9:]+\]]], [[SAVEEXEC_OUTER2]] ; GCN-NEXT: s_or_saveexec_b64 [[SAVEEXEC_OUTER3:s\[[0-9:]+\]]], [[SAVEEXEC_OUTER2]]
; GCN-NEXT: s_xor_b64 exec, exec, [[SAVEEXEC_OUTER3]] ; GCN-NEXT: s_xor_b64 exec, exec, [[SAVEEXEC_OUTER3]]
; GCN-NEXT: s_cbranch_execz [[ENDIF_OUTER:BB[0-9_]+]] ; GCN-NEXT: s_cbranch_execz [[ENDIF_OUTER:.LBB[0-9_]+]]
; GCN-NEXT: ; %bb.{{[0-9]+}}: ; GCN-NEXT: ; %bb.{{[0-9]+}}:
; GCN: store_dword ; GCN: store_dword
; GCN-NEXT: s_and_saveexec_b64 [[SAVEEXEC_ELSE:s\[[0-9:]+\]]], ; GCN-NEXT: s_and_saveexec_b64 [[SAVEEXEC_ELSE:s\[[0-9:]+\]]],
; GCN-NEXT: s_cbranch_execz [[FLOW1:BB[0-9_]+]] ; GCN-NEXT: s_cbranch_execz [[FLOW1:.LBB[0-9_]+]]
; GCN-NEXT: ; %bb.{{[0-9]+}}: ; GCN-NEXT: ; %bb.{{[0-9]+}}:
; GCN: store_dword ; GCN: store_dword
; GCN-NEXT: [[FLOW1]]: ; GCN-NEXT: [[FLOW1]]:
; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_ELSE]] ; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_ELSE]]
; GCN: s_or_b64 exec, exec, [[SAVEEXEC_OUTER3]] ; GCN: s_or_b64 exec, exec, [[SAVEEXEC_OUTER3]]
; GCN: ds_write_b32 ; GCN: ds_write_b32
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @nested_if_else_if(i32 addrspace(1)* nocapture %arg) { define amdgpu_kernel void @nested_if_else_if(i32 addrspace(1)* nocapture %arg) {
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bb.outer.end: bb.outer.end:
store i32 3, i32 addrspace(3)* null store i32 3, i32 addrspace(3)* null
ret void ret void
} }
; GCN-LABEL: {{^}}s_endpgm_unsafe_barrier: ; GCN-LABEL: {{^}}s_endpgm_unsafe_barrier:
; GCN: s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9:]+\]]] ; GCN: s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9:]+\]]]
; GCN-NEXT: s_cbranch_execz [[ENDIF:BB[0-9_]+]] ; GCN-NEXT: s_cbranch_execz [[ENDIF:.LBB[0-9_]+]]
; GCN-NEXT: ; %bb.{{[0-9]+}}: ; GCN-NEXT: ; %bb.{{[0-9]+}}:
; GCN: store_dword ; GCN: store_dword
; GCN-NEXT: {{^}}[[ENDIF]]: ; GCN-NEXT: {{^}}[[ENDIF]]:
; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC]] ; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC]]
; GCN: s_barrier ; GCN: s_barrier
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @s_endpgm_unsafe_barrier(i32 addrspace(1)* nocapture %arg) { define amdgpu_kernel void @s_endpgm_unsafe_barrier(i32 addrspace(1)* nocapture %arg) {
bb: bb:
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x() %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = icmp ugt i32 %tmp, 1 %tmp1 = icmp ugt i32 %tmp, 1
br i1 %tmp1, label %bb.then, label %bb.end br i1 %tmp1, label %bb.then, label %bb.end
bb.then: ; preds = %bb bb.then: ; preds = %bb
%tmp4 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp %tmp4 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp
store i32 0, i32 addrspace(1)* %tmp4, align 4 store i32 0, i32 addrspace(1)* %tmp4, align 4
br label %bb.end br label %bb.end
bb.end: ; preds = %bb.then, %bb bb.end: ; preds = %bb.then, %bb
call void @llvm.amdgcn.s.barrier() call void @llvm.amdgcn.s.barrier()
ret void ret void
} }
; GCN-LABEL: {{^}}scc_liveness: ; GCN-LABEL: {{^}}scc_liveness:
; GCN: [[BB1_OUTER_LOOP:BB[0-9]+_[0-9]+]]: ; GCN: [[BB1_OUTER_LOOP:.LBB[0-9]+_[0-9]+]]:
; GCN: s_or_b64 exec, exec, [[SAVEEXEC_OUTER:s\[[0-9:]+\]]] ; GCN: s_or_b64 exec, exec, [[SAVEEXEC_OUTER:s\[[0-9:]+\]]]
; ;
; GCN: [[BB1_INNER_LOOP:BB[0-9]+_[0-9]+]]: ; GCN: [[BB1_INNER_LOOP:.LBB[0-9]+_[0-9]+]]:
; GCN: s_or_b64 exec, exec, s{{\[[0-9]+:[0-9]+\]}} ; GCN: s_or_b64 exec, exec, s{{\[[0-9]+:[0-9]+\]}}
; GCN: s_andn2_b64 ; GCN: s_andn2_b64
; GCN-NEXT: s_cbranch_execz ; GCN-NEXT: s_cbranch_execz
; GCN: [[BB1_LOOP:BB[0-9]+_[0-9]+]]: ; GCN: [[BB1_LOOP:.LBB[0-9]+_[0-9]+]]:
; GCN: s_andn2_b64 exec, exec, ; GCN: s_andn2_b64 exec, exec,
; GCN-NEXT: s_cbranch_execnz [[BB1_LOOP]] ; GCN-NEXT: s_cbranch_execnz [[BB1_LOOP]]
; GCN: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0 offen ; GCN: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0 offen
; GCN: s_and_saveexec_b64 [[SAVEEXEC_OUTER]], {{vcc|s\[[0-9:]+\]}} ; GCN: s_and_saveexec_b64 [[SAVEEXEC_OUTER]], {{vcc|s\[[0-9:]+\]}}
; GCN-NEXT: s_cbranch_execz [[BB1_OUTER_LOOP]] ; GCN-NEXT: s_cbranch_execz [[BB1_OUTER_LOOP]]
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llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll

Show All 27 Lines
; VMEM: v_writelane_b32 v[[V_SAVEEXEC:[0-9]+]], s[[SAVEEXEC_LO]], 0 ; VMEM: v_writelane_b32 v[[V_SAVEEXEC:[0-9]+]], s[[SAVEEXEC_LO]], 0
; VMEM: v_writelane_b32 v[[V_SAVEEXEC]], s[[SAVEEXEC_HI]], 1 ; VMEM: v_writelane_b32 v[[V_SAVEEXEC]], s[[SAVEEXEC_HI]], 1
; VMEM: buffer_store_dword v[[V_SAVEEXEC]], off, s[0:3], 0 offset:[[V_EXEC_SPILL_OFFSET:[0-9]+]] ; 4-byte Folded Spill ; VMEM: buffer_store_dword v[[V_SAVEEXEC]], off, s[0:3], 0 offset:[[V_EXEC_SPILL_OFFSET:[0-9]+]] ; 4-byte Folded Spill
; GCN: s_and_b64 s{{\[}}[[ANDEXEC_LO:[0-9]+]]:[[ANDEXEC_HI:[0-9]+]]{{\]}}, s{{\[}}[[SAVEEXEC_LO]]:[[SAVEEXEC_HI]]{{\]}}, [[CMP0]] ; GCN: s_and_b64 s{{\[}}[[ANDEXEC_LO:[0-9]+]]:[[ANDEXEC_HI:[0-9]+]]{{\]}}, s{{\[}}[[SAVEEXEC_LO]]:[[SAVEEXEC_HI]]{{\]}}, [[CMP0]]
; GCN: s_mov_b64 exec, s{{\[}}[[ANDEXEC_LO]]:[[ANDEXEC_HI]]{{\]}} ; GCN: s_mov_b64 exec, s{{\[}}[[ANDEXEC_LO]]:[[ANDEXEC_HI]]{{\]}}
; GCN: s_cbranch_execz [[ENDIF:BB[0-9]+_[0-9]+]] ; GCN: s_cbranch_execz [[ENDIF:.LBB[0-9]+_[0-9]+]]
; GCN: ; %bb.{{[0-9]+}}: ; %if ; GCN: ; %bb.{{[0-9]+}}: ; %if
; GCN: buffer_load_dword [[RELOAD_LOAD0:v[0-9]+]], off, s[0:3], 0 offset:[[LOAD0_OFFSET]] ; 4-byte Folded Reload ; GCN: buffer_load_dword [[RELOAD_LOAD0:v[0-9]+]], off, s[0:3], 0 offset:[[LOAD0_OFFSET]] ; 4-byte Folded Reload
; GCN: s_mov_b32 m0, -1 ; GCN: s_mov_b32 m0, -1
; GCN: ds_read_b32 [[LOAD1:v[0-9]+]] ; GCN: ds_read_b32 [[LOAD1:v[0-9]+]]
; GCN: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN: s_waitcnt vmcnt(0) lgkmcnt(0)
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; VMEM: v_writelane_b32 v[[V_SAVEEXEC:[0-9]+]], s[[SAVEEXEC_LO]], 0 ; VMEM: v_writelane_b32 v[[V_SAVEEXEC:[0-9]+]], s[[SAVEEXEC_LO]], 0
; VMEM: v_writelane_b32 v[[V_SAVEEXEC]], s[[SAVEEXEC_HI]], 1 ; VMEM: v_writelane_b32 v[[V_SAVEEXEC]], s[[SAVEEXEC_HI]], 1
; VMEM: buffer_store_dword v[[V_SAVEEXEC]], off, s[0:3], 0 offset:[[V_EXEC_SPILL_OFFSET:[0-9]+]] ; 4-byte Folded Spill ; VMEM: buffer_store_dword v[[V_SAVEEXEC]], off, s[0:3], 0 offset:[[V_EXEC_SPILL_OFFSET:[0-9]+]] ; 4-byte Folded Spill
; GCN: s_and_b64 s{{\[}}[[ANDEXEC_LO:[0-9]+]]:[[ANDEXEC_HI:[0-9]+]]{{\]}}, s{{\[}}[[SAVEEXEC_LO:[0-9]+]]:[[SAVEEXEC_HI:[0-9]+]]{{\]}}, [[CMP0]] ; GCN: s_and_b64 s{{\[}}[[ANDEXEC_LO:[0-9]+]]:[[ANDEXEC_HI:[0-9]+]]{{\]}}, s{{\[}}[[SAVEEXEC_LO:[0-9]+]]:[[SAVEEXEC_HI:[0-9]+]]{{\]}}, [[CMP0]]
; GCN: s_mov_b64 exec, s{{\[}}[[ANDEXEC_LO]]:[[ANDEXEC_HI]]{{\]}} ; GCN: s_mov_b64 exec, s{{\[}}[[ANDEXEC_LO]]:[[ANDEXEC_HI]]{{\]}}
; GCN-NEXT: s_cbranch_execz [[END:BB[0-9]+_[0-9]+]] ; GCN-NEXT: s_cbranch_execz [[END:.LBB[0-9]+_[0-9]+]]
; GCN: [[LOOP:BB[0-9]+_[0-9]+]]: ; GCN: [[LOOP:.LBB[0-9]+_[0-9]+]]:
; GCN: buffer_load_dword v[[VAL_LOOP_RELOAD:[0-9]+]], off, s[0:3], 0 offset:[[LOAD0_OFFSET]] ; 4-byte Folded Reload ; GCN: buffer_load_dword v[[VAL_LOOP_RELOAD:[0-9]+]], off, s[0:3], 0 offset:[[LOAD0_OFFSET]] ; 4-byte Folded Reload
; GCN: v_subrev_i32_e32 [[VAL_LOOP:v[0-9]+]], vcc, v{{[0-9]+}}, v[[VAL_LOOP_RELOAD]] ; GCN: v_subrev_i32_e32 [[VAL_LOOP:v[0-9]+]], vcc, v{{[0-9]+}}, v[[VAL_LOOP_RELOAD]]
; GCN: s_cmp_lg_u32 ; GCN: s_cmp_lg_u32
; VMEM: buffer_store_dword ; VMEM: buffer_store_dword
; VMEM: buffer_store_dword ; VMEM: buffer_store_dword
; VMEM: buffer_store_dword ; VMEM: buffer_store_dword
; GCN: buffer_store_dword [[VAL_LOOP]], off, s[0:3], 0 offset:{{[0-9]+}} ; 4-byte Folded Spill ; GCN: buffer_store_dword [[VAL_LOOP]], off, s[0:3], 0 offset:{{[0-9]+}} ; 4-byte Folded Spill
; GCN-NEXT: s_cbranch_scc1 [[LOOP]] ; GCN-NEXT: s_cbranch_scc1 [[LOOP]]
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; VMEM: v_writelane_b32 v[[V_SAVEEXEC:[0-9]+]], s[[SAVEEXEC_LO]], 0 ; VMEM: v_writelane_b32 v[[V_SAVEEXEC:[0-9]+]], s[[SAVEEXEC_LO]], 0
; VMEM: v_writelane_b32 v[[V_SAVEEXEC]], s[[SAVEEXEC_HI]], 1 ; VMEM: v_writelane_b32 v[[V_SAVEEXEC]], s[[SAVEEXEC_HI]], 1
; VMEM: buffer_store_dword v[[V_SAVEEXEC]], off, s[0:3], 0 offset:[[SAVEEXEC_OFFSET:[0-9]+]] ; 4-byte Folded Spill ; VMEM: buffer_store_dword v[[V_SAVEEXEC]], off, s[0:3], 0 offset:[[SAVEEXEC_OFFSET:[0-9]+]] ; 4-byte Folded Spill
; GCN: s_mov_b64 exec, [[CMP0]] ; GCN: s_mov_b64 exec, [[CMP0]]
; FIXME: It makes no sense to put this skip here ; FIXME: It makes no sense to put this skip here
; GCN: s_cbranch_execz [[FLOW:BB[0-9]+_[0-9]+]] ; GCN: s_cbranch_execz [[FLOW:.LBB[0-9]+_[0-9]+]]
; GCN-NEXT: s_branch [[ELSE:BB[0-9]+_[0-9]+]] ; GCN-NEXT: s_branch [[ELSE:.LBB[0-9]+_[0-9]+]]
; GCN: [[FLOW]]: ; %Flow ; GCN: [[FLOW]]: ; %Flow
; VGPR: v_readlane_b32 s[[FLOW_S_RELOAD_SAVEEXEC_LO:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_LO_LANE]] ; VGPR: v_readlane_b32 s[[FLOW_S_RELOAD_SAVEEXEC_LO:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_LO_LANE]]
; VGPR: v_readlane_b32 s[[FLOW_S_RELOAD_SAVEEXEC_HI:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_HI_LANE]] ; VGPR: v_readlane_b32 s[[FLOW_S_RELOAD_SAVEEXEC_HI:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_HI_LANE]]
; VMEM: buffer_load_dword v[[FLOW_V_RELOAD_SAVEEXEC:[0-9]+]], off, s[0:3], 0 offset:[[SAVEEXEC_OFFSET]] ; VMEM: buffer_load_dword v[[FLOW_V_RELOAD_SAVEEXEC:[0-9]+]], off, s[0:3], 0 offset:[[SAVEEXEC_OFFSET]]
; VMEM: s_waitcnt vmcnt(0) ; VMEM: s_waitcnt vmcnt(0)
; VMEM: v_readlane_b32 s[[FLOW_S_RELOAD_SAVEEXEC_LO:[0-9]+]], v[[FLOW_V_RELOAD_SAVEEXEC]], 0 ; VMEM: v_readlane_b32 s[[FLOW_S_RELOAD_SAVEEXEC_LO:[0-9]+]], v[[FLOW_V_RELOAD_SAVEEXEC]], 0
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; VGPR: v_writelane_b32 [[SPILL_VGPR]], s[[FLOW_AND_EXEC_LO]], [[FLOW_SAVEEXEC_LO_LANE:[0-9]+]] ; VGPR: v_writelane_b32 [[SPILL_VGPR]], s[[FLOW_AND_EXEC_LO]], [[FLOW_SAVEEXEC_LO_LANE:[0-9]+]]
; VGPR: v_writelane_b32 [[SPILL_VGPR]], s[[FLOW_AND_EXEC_HI]], [[FLOW_SAVEEXEC_HI_LANE:[0-9]+]] ; VGPR: v_writelane_b32 [[SPILL_VGPR]], s[[FLOW_AND_EXEC_HI]], [[FLOW_SAVEEXEC_HI_LANE:[0-9]+]]
; VMEM: v_writelane_b32 v[[FLOW_V_SAVEEXEC:[0-9]+]], s[[FLOW_AND_EXEC_LO]], 0 ; VMEM: v_writelane_b32 v[[FLOW_V_SAVEEXEC:[0-9]+]], s[[FLOW_AND_EXEC_LO]], 0
; VMEM: v_writelane_b32 v[[FLOW_V_SAVEEXEC]], s[[FLOW_AND_EXEC_HI]], 1 ; VMEM: v_writelane_b32 v[[FLOW_V_SAVEEXEC]], s[[FLOW_AND_EXEC_HI]], 1
; VMEM: buffer_store_dword v[[FLOW_V_SAVEEXEC]], off, s[0:3], 0 offset:[[FLOW_SAVEEXEC_OFFSET:[0-9]+]] ; 4-byte Folded Spill ; VMEM: buffer_store_dword v[[FLOW_V_SAVEEXEC]], off, s[0:3], 0 offset:[[FLOW_SAVEEXEC_OFFSET:[0-9]+]] ; 4-byte Folded Spill
; GCN: s_xor_b64 exec, exec, s{{\[}}[[FLOW_AND_EXEC_LO]]:[[FLOW_AND_EXEC_HI]]{{\]}} ; GCN: s_xor_b64 exec, exec, s{{\[}}[[FLOW_AND_EXEC_LO]]:[[FLOW_AND_EXEC_HI]]{{\]}}
; GCN-NEXT: s_cbranch_execz [[ENDIF:BB[0-9]+_[0-9]+]] ; GCN-NEXT: s_cbranch_execz [[ENDIF:.LBB[0-9]+_[0-9]+]]
; GCN: ; %bb.{{[0-9]+}}: ; %if ; GCN: ; %bb.{{[0-9]+}}: ; %if
; GCN: buffer_load_dword v[[LOAD0_RELOAD:[0-9]+]], off, s[0:3], 0 offset:[[LOAD0_OFFSET]] ; 4-byte Folded Reload ; GCN: buffer_load_dword v[[LOAD0_RELOAD:[0-9]+]], off, s[0:3], 0 offset:[[LOAD0_OFFSET]] ; 4-byte Folded Reload
; GCN: ds_read_b32 ; GCN: ds_read_b32
; GCN: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, v{{[0-9]+}}, v[[LOAD0_RELOAD]] ; GCN: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, v{{[0-9]+}}, v[[LOAD0_RELOAD]]
; GCN: buffer_store_dword [[ADD]], off, s[0:3], 0 offset:[[RESULT_OFFSET]] ; 4-byte Folded Spill ; GCN: buffer_store_dword [[ADD]], off, s[0:3], 0 offset:[[RESULT_OFFSET]] ; 4-byte Folded Spill
; GCN-NEXT: s_branch [[ENDIF:BB[0-9]+_[0-9]+]] ; GCN-NEXT: s_branch [[ENDIF:.LBB[0-9]+_[0-9]+]]
; GCN: [[ELSE]]: ; %else ; GCN: [[ELSE]]: ; %else
; GCN: buffer_load_dword v[[LOAD0_RELOAD:[0-9]+]], off, s[0:3], 0 offset:[[LOAD0_OFFSET]] ; 4-byte Folded Reload ; GCN: buffer_load_dword v[[LOAD0_RELOAD:[0-9]+]], off, s[0:3], 0 offset:[[LOAD0_OFFSET]] ; 4-byte Folded Reload
; GCN: v_subrev_i32_e32 [[SUB:v[0-9]+]], vcc, v{{[0-9]+}}, v[[LOAD0_RELOAD]] ; GCN: v_subrev_i32_e32 [[SUB:v[0-9]+]], vcc, v{{[0-9]+}}, v[[LOAD0_RELOAD]]
; GCN: buffer_store_dword [[ADD]], off, s[0:3], 0 offset:[[FLOW_RESULT_OFFSET:[0-9]+]] ; 4-byte Folded Spill ; GCN: buffer_store_dword [[ADD]], off, s[0:3], 0 offset:[[FLOW_RESULT_OFFSET:[0-9]+]] ; 4-byte Folded Spill
; GCN-NEXT: s_branch [[FLOW]] ; GCN-NEXT: s_branch [[FLOW]]
; GCN: [[ENDIF]]: ; GCN: [[ENDIF]]:
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llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll

Show First 20 Lines • Show All 172 Lines • ▼ Show 20 Lines
; GCN-NEXT: s_addc_u32 flat_scratch_hi, s13, 0 ; GCN-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
; GCN-NEXT: s_add_u32 s0, s0, s17 ; GCN-NEXT: s_add_u32 s0, s0, s17
; GCN-NEXT: s_addc_u32 s1, s1, 0 ; GCN-NEXT: s_addc_u32 s1, s1, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_bitcmp1_b32 s4, 0 ; GCN-NEXT: s_bitcmp1_b32 s4, 0
; GCN-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GCN-NEXT: s_cselect_b64 s[4:5], -1, 0
; GCN-NEXT: s_and_b64 vcc, exec, s[4:5] ; GCN-NEXT: s_and_b64 vcc, exec, s[4:5]
; GCN-NEXT: s_mov_b32 s32, 0 ; GCN-NEXT: s_mov_b32 s32, 0
; GCN-NEXT: s_cbranch_vccnz BB4_2 ; GCN-NEXT: s_cbranch_vccnz .LBB4_2
; GCN-NEXT: ; %bb.1: ; %if.else ; GCN-NEXT: ; %bb.1: ; %if.else
; GCN-NEXT: s_getpc_b64 s[4:5] ; GCN-NEXT: s_getpc_b64 s[4:5]
; GCN-NEXT: s_add_u32 s4, s4, func_v3i16@rel32@lo+4 ; GCN-NEXT: s_add_u32 s4, s4, func_v3i16@rel32@lo+4
; GCN-NEXT: s_addc_u32 s5, s5, func_v3i16@rel32@hi+12 ; GCN-NEXT: s_addc_u32 s5, s5, func_v3i16@rel32@hi+12
; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GCN-NEXT: s_branch BB4_3 ; GCN-NEXT: s_branch .LBB4_3
; GCN-NEXT: BB4_2: ; GCN-NEXT: .LBB4_2:
; GCN-NEXT: s_mov_b32 s4, 0 ; GCN-NEXT: s_mov_b32 s4, 0
; GCN-NEXT: s_mov_b32 s5, s4 ; GCN-NEXT: s_mov_b32 s5, s4
; GCN-NEXT: v_mov_b32_e32 v0, s4 ; GCN-NEXT: v_mov_b32_e32 v0, s4
; GCN-NEXT: v_mov_b32_e32 v1, s5 ; GCN-NEXT: v_mov_b32_e32 v1, s5
; GCN-NEXT: BB4_3: ; %if.end ; GCN-NEXT: .LBB4_3: ; %if.end
; GCN-NEXT: global_store_short v[0:1], v1, off ; GCN-NEXT: global_store_short v[0:1], v1, off
; GCN-NEXT: global_store_dword v[0:1], v0, off ; GCN-NEXT: global_store_dword v[0:1], v0, off
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
entry: entry:
br i1 %cond, label %if.then, label %if.else br i1 %cond, label %if.then, label %if.else
if.then: ; preds = %entry if.then: ; preds = %entry
br label %if.end br label %if.end
Show All 16 Lines
; GCN-NEXT: s_addc_u32 flat_scratch_hi, s13, 0 ; GCN-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
; GCN-NEXT: s_add_u32 s0, s0, s17 ; GCN-NEXT: s_add_u32 s0, s0, s17
; GCN-NEXT: s_addc_u32 s1, s1, 0 ; GCN-NEXT: s_addc_u32 s1, s1, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_bitcmp1_b32 s4, 0 ; GCN-NEXT: s_bitcmp1_b32 s4, 0
; GCN-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GCN-NEXT: s_cselect_b64 s[4:5], -1, 0
; GCN-NEXT: s_and_b64 vcc, exec, s[4:5] ; GCN-NEXT: s_and_b64 vcc, exec, s[4:5]
; GCN-NEXT: s_mov_b32 s32, 0 ; GCN-NEXT: s_mov_b32 s32, 0
; GCN-NEXT: s_cbranch_vccnz BB5_2 ; GCN-NEXT: s_cbranch_vccnz .LBB5_2
; GCN-NEXT: ; %bb.1: ; %if.else ; GCN-NEXT: ; %bb.1: ; %if.else
; GCN-NEXT: s_getpc_b64 s[4:5] ; GCN-NEXT: s_getpc_b64 s[4:5]
; GCN-NEXT: s_add_u32 s4, s4, func_v3f16@rel32@lo+4 ; GCN-NEXT: s_add_u32 s4, s4, func_v3f16@rel32@lo+4
; GCN-NEXT: s_addc_u32 s5, s5, func_v3f16@rel32@hi+12 ; GCN-NEXT: s_addc_u32 s5, s5, func_v3f16@rel32@hi+12
; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GCN-NEXT: s_branch BB5_3 ; GCN-NEXT: s_branch .LBB5_3
; GCN-NEXT: BB5_2: ; GCN-NEXT: .LBB5_2:
; GCN-NEXT: s_mov_b32 s4, 0 ; GCN-NEXT: s_mov_b32 s4, 0
; GCN-NEXT: s_mov_b32 s5, s4 ; GCN-NEXT: s_mov_b32 s5, s4
; GCN-NEXT: v_mov_b32_e32 v0, s4 ; GCN-NEXT: v_mov_b32_e32 v0, s4
; GCN-NEXT: v_mov_b32_e32 v1, s5 ; GCN-NEXT: v_mov_b32_e32 v1, s5
; GCN-NEXT: BB5_3: ; %if.end ; GCN-NEXT: .LBB5_3: ; %if.end
; GCN-NEXT: global_store_short v[0:1], v1, off ; GCN-NEXT: global_store_short v[0:1], v1, off
; GCN-NEXT: global_store_dword v[0:1], v0, off ; GCN-NEXT: global_store_dword v[0:1], v0, off
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
entry: entry:
br i1 %cond, label %if.then, label %if.else br i1 %cond, label %if.then, label %if.else
if.then: ; preds = %entry if.then: ; preds = %entry
br label %if.end br label %if.end
Show All 21 Lines

llvm/test/CodeGen/AMDGPU/ctpop16.ll

Show First 20 Lines • Show All 1,484 Lines • ▼ Show 20 Lines
define amdgpu_kernel void @ctpop_i16_in_br(i16 addrspace(1)* %out, i16 addrspace(1)* %in, i16 %ctpop_arg, i16 %cond) { define amdgpu_kernel void @ctpop_i16_in_br(i16 addrspace(1)* %out, i16 addrspace(1)* %in, i16 %ctpop_arg, i16 %cond) {
; SI-LABEL: ctpop_i16_in_br: ; SI-LABEL: ctpop_i16_in_br:
; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dword s4, s[0:1], 0xd ; SI-NEXT: s_load_dword s4, s[0:1], 0xd
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_lshr_b32 s2, s4, 16 ; SI-NEXT: s_lshr_b32 s2, s4, 16
; SI-NEXT: s_cmp_lg_u32 s2, 0 ; SI-NEXT: s_cmp_lg_u32 s2, 0
; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; SI-NEXT: s_cbranch_scc0 BB14_2 ; SI-NEXT: s_cbranch_scc0 .LBB14_2
; SI-NEXT: ; %bb.1: ; %else ; SI-NEXT: ; %bb.1: ; %else
; SI-NEXT: s_mov_b32 s11, 0xf000 ; SI-NEXT: s_mov_b32 s11, 0xf000
; SI-NEXT: s_mov_b32 s10, -1 ; SI-NEXT: s_mov_b32 s10, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s8, s2 ; SI-NEXT: s_mov_b32 s8, s2
; SI-NEXT: s_mov_b32 s9, s3 ; SI-NEXT: s_mov_b32 s9, s3
; SI-NEXT: buffer_load_ushort v0, off, s[8:11], 0 offset:2 ; SI-NEXT: buffer_load_ushort v0, off, s[8:11], 0 offset:2
; SI-NEXT: s_mov_b64 s[2:3], 0 ; SI-NEXT: s_mov_b64 s[2:3], 0
; SI-NEXT: s_cbranch_execz BB14_3 ; SI-NEXT: s_cbranch_execz .LBB14_3
; SI-NEXT: s_branch BB14_4 ; SI-NEXT: s_branch .LBB14_4
; SI-NEXT: BB14_2: ; SI-NEXT: .LBB14_2:
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b64 s[2:3], -1 ; SI-NEXT: s_mov_b64 s[2:3], -1
; SI-NEXT: v_mov_b32_e32 v0, 0 ; SI-NEXT: v_mov_b32_e32 v0, 0
; SI-NEXT: BB14_3: ; %if ; SI-NEXT: .LBB14_3: ; %if
; SI-NEXT: s_and_b32 s2, s4, 0xffff ; SI-NEXT: s_and_b32 s2, s4, 0xffff
; SI-NEXT: s_bcnt1_i32_b32 s2, s2 ; SI-NEXT: s_bcnt1_i32_b32 s2, s2
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s2 ; SI-NEXT: v_mov_b32_e32 v0, s2
; SI-NEXT: BB14_4: ; %endif ; SI-NEXT: .LBB14_4: ; %endif
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: ctpop_i16_in_br: ; VI-LABEL: ctpop_i16_in_br:
; VI: ; %bb.0: ; %entry ; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_load_dword s2, s[0:1], 0x34 ; VI-NEXT: s_load_dword s2, s[0:1], 0x34
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_lshr_b32 s0, s2, 16 ; VI-NEXT: s_lshr_b32 s0, s2, 16
; VI-NEXT: v_cmp_ne_u16_e64 s[0:1], s0, 0 ; VI-NEXT: v_cmp_ne_u16_e64 s[0:1], s0, 0
; VI-NEXT: s_and_b64 vcc, exec, s[0:1] ; VI-NEXT: s_and_b64 vcc, exec, s[0:1]
; VI-NEXT: s_cbranch_vccz BB14_2 ; VI-NEXT: s_cbranch_vccz .LBB14_2
; VI-NEXT: ; %bb.1: ; %else ; VI-NEXT: ; %bb.1: ; %else
; VI-NEXT: s_mov_b32 s11, 0xf000 ; VI-NEXT: s_mov_b32 s11, 0xf000
; VI-NEXT: s_mov_b32 s10, -1 ; VI-NEXT: s_mov_b32 s10, -1
; VI-NEXT: s_mov_b32 s8, s6 ; VI-NEXT: s_mov_b32 s8, s6
; VI-NEXT: s_mov_b32 s9, s7 ; VI-NEXT: s_mov_b32 s9, s7
; VI-NEXT: buffer_load_ushort v0, off, s[8:11], 0 offset:2 ; VI-NEXT: buffer_load_ushort v0, off, s[8:11], 0 offset:2
; VI-NEXT: s_cbranch_execz BB14_3 ; VI-NEXT: s_cbranch_execz .LBB14_3
; VI-NEXT: s_branch BB14_4 ; VI-NEXT: s_branch .LBB14_4
; VI-NEXT: BB14_2: ; VI-NEXT: .LBB14_2:
; VI-NEXT: ; implicit-def: $vgpr0 ; VI-NEXT: ; implicit-def: $vgpr0
; VI-NEXT: BB14_3: ; %if ; VI-NEXT: .LBB14_3: ; %if
; VI-NEXT: s_and_b32 s0, s2, 0xffff ; VI-NEXT: s_and_b32 s0, s2, 0xffff
; VI-NEXT: s_bcnt1_i32_b32 s0, s0 ; VI-NEXT: s_bcnt1_i32_b32 s0, s0
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s0 ; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: BB14_4: ; %endif ; VI-NEXT: .LBB14_4: ; %endif
; VI-NEXT: s_mov_b32 s7, 0xf000 ; VI-NEXT: s_mov_b32 s7, 0xf000
; VI-NEXT: s_mov_b32 s6, -1 ; VI-NEXT: s_mov_b32 s6, -1
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_store_short v0, off, s[4:7], 0 ; VI-NEXT: buffer_store_short v0, off, s[4:7], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; EG-LABEL: ctpop_i16_in_br: ; EG-LABEL: ctpop_i16_in_br:
; EG: ; %bb.0: ; %entry ; EG: ; %bb.0: ; %entry
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llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll

Show First 20 Lines • Show All 119 Lines • ▼ Show 20 Lines
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; CHECK-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; CHECK-NEXT: s_mov_b64 s[4:5], 0 ; CHECK-NEXT: s_mov_b64 s[4:5], 0
; CHECK-NEXT: v_mov_b32_e32 v0, 0 ; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: s_waitcnt lgkmcnt(0) ; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: s_load_dword s6, s[0:1], 0x0 ; CHECK-NEXT: s_load_dword s6, s[0:1], 0x0
; CHECK-NEXT: s_waitcnt lgkmcnt(0) ; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_mov_b32_e32 v1, s6 ; CHECK-NEXT: v_mov_b32_e32 v1, s6
; CHECK-NEXT: BB5_1: ; %atomicrmw.start ; CHECK-NEXT: .LBB5_1: ; %atomicrmw.start
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: v_mov_b32_e32 v3, v1 ; CHECK-NEXT: v_mov_b32_e32 v3, v1
; CHECK-NEXT: v_not_b32_e32 v1, v3 ; CHECK-NEXT: v_not_b32_e32 v1, v3
; CHECK-NEXT: v_or_b32_e32 v2, -2, v1 ; CHECK-NEXT: v_or_b32_e32 v2, -2, v1
; CHECK-NEXT: global_atomic_cmpswap v1, v0, v[2:3], s[0:1] glc ; CHECK-NEXT: global_atomic_cmpswap v1, v0, v[2:3], s[0:1] glc
; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3 ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
; CHECK-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; CHECK-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; CHECK-NEXT: s_andn2_b64 exec, exec, s[4:5] ; CHECK-NEXT: s_andn2_b64 exec, exec, s[4:5]
; CHECK-NEXT: s_cbranch_execnz BB5_1 ; CHECK-NEXT: s_cbranch_execnz .LBB5_1
; CHECK-NEXT: ; %bb.2: ; %atomicrmw.end ; CHECK-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NEXT: s_or_b64 exec, exec, s[4:5] ; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v1, 12, s[2:3] ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v1, 12, s[2:3]
; CHECK-NEXT: v_mov_b32_e32 v2, 1.0 ; CHECK-NEXT: v_mov_b32_e32 v2, 1.0
; CHECK-NEXT: global_store_dword v[0:1], v2, off ; CHECK-NEXT: global_store_dword v[0:1], v2, off
; CHECK-NEXT: s_endpgm ; CHECK-NEXT: s_endpgm
%n32 = atomicrmw nand i32 addrspace(1)* %p, i32 1 monotonic %n32 = atomicrmw nand i32 addrspace(1)* %p, i32 1 monotonic
%n64 = zext i32 %n32 to i64 %n64 = zext i32 %n32 to i64
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; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; CHECK-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; CHECK-NEXT: s_mov_b64 s[4:5], 0 ; CHECK-NEXT: s_mov_b64 s[4:5], 0
; CHECK-NEXT: v_mov_b32_e32 v0, 0 ; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: s_waitcnt lgkmcnt(0) ; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: s_load_dword s6, s[0:1], 0x0 ; CHECK-NEXT: s_load_dword s6, s[0:1], 0x0
; CHECK-NEXT: s_waitcnt lgkmcnt(0) ; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_mov_b32_e32 v1, s6 ; CHECK-NEXT: v_mov_b32_e32 v1, s6
; CHECK-NEXT: BB14_1: ; %atomicrmw.start ; CHECK-NEXT: .LBB14_1: ; %atomicrmw.start
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: v_mov_b32_e32 v3, v1 ; CHECK-NEXT: v_mov_b32_e32 v3, v1
; CHECK-NEXT: v_add_f32_e32 v2, 1.0, v3 ; CHECK-NEXT: v_add_f32_e32 v2, 1.0, v3
; CHECK-NEXT: global_atomic_cmpswap v1, v0, v[2:3], s[0:1] glc ; CHECK-NEXT: global_atomic_cmpswap v1, v0, v[2:3], s[0:1] glc
; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3 ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
; CHECK-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; CHECK-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; CHECK-NEXT: s_andn2_b64 exec, exec, s[4:5] ; CHECK-NEXT: s_andn2_b64 exec, exec, s[4:5]
; CHECK-NEXT: s_cbranch_execnz BB14_1 ; CHECK-NEXT: s_cbranch_execnz .LBB14_1
; CHECK-NEXT: ; %bb.2: ; %atomicrmw.end ; CHECK-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NEXT: s_or_b64 exec, exec, s[4:5] ; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v1 ; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v1
; CHECK-NEXT: v_mov_b32_e32 v2, 1.0 ; CHECK-NEXT: v_mov_b32_e32 v2, 1.0
; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v0, 12, s[2:3] ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v0, 12, s[2:3]
; CHECK-NEXT: global_store_dword v[0:1], v2, off ; CHECK-NEXT: global_store_dword v[0:1], v2, off
; CHECK-NEXT: s_endpgm ; CHECK-NEXT: s_endpgm
%f32 = atomicrmw fadd float addrspace(1)* %p, float 1.0 monotonic %f32 = atomicrmw fadd float addrspace(1)* %p, float 1.0 monotonic
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; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; CHECK-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; CHECK-NEXT: s_mov_b64 s[4:5], 0 ; CHECK-NEXT: s_mov_b64 s[4:5], 0
; CHECK-NEXT: v_mov_b32_e32 v0, 0 ; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: s_waitcnt lgkmcnt(0) ; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: s_load_dword s6, s[0:1], 0x0 ; CHECK-NEXT: s_load_dword s6, s[0:1], 0x0
; CHECK-NEXT: s_waitcnt lgkmcnt(0) ; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_mov_b32_e32 v1, s6 ; CHECK-NEXT: v_mov_b32_e32 v1, s6
; CHECK-NEXT: BB15_1: ; %atomicrmw.start ; CHECK-NEXT: .LBB15_1: ; %atomicrmw.start
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: v_mov_b32_e32 v3, v1 ; CHECK-NEXT: v_mov_b32_e32 v3, v1
; CHECK-NEXT: v_add_f32_e32 v2, -1.0, v3 ; CHECK-NEXT: v_add_f32_e32 v2, -1.0, v3
; CHECK-NEXT: global_atomic_cmpswap v1, v0, v[2:3], s[0:1] glc ; CHECK-NEXT: global_atomic_cmpswap v1, v0, v[2:3], s[0:1] glc
; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3 ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
; CHECK-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; CHECK-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; CHECK-NEXT: s_andn2_b64 exec, exec, s[4:5] ; CHECK-NEXT: s_andn2_b64 exec, exec, s[4:5]
; CHECK-NEXT: s_cbranch_execnz BB15_1 ; CHECK-NEXT: s_cbranch_execnz .LBB15_1
; CHECK-NEXT: ; %bb.2: ; %atomicrmw.end ; CHECK-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NEXT: s_or_b64 exec, exec, s[4:5] ; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v1 ; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v1
; CHECK-NEXT: v_mov_b32_e32 v2, 1.0 ; CHECK-NEXT: v_mov_b32_e32 v2, 1.0
; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v0, 12, s[2:3] ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v0, 12, s[2:3]
; CHECK-NEXT: global_store_dword v[0:1], v2, off ; CHECK-NEXT: global_store_dword v[0:1], v2, off
; CHECK-NEXT: s_endpgm ; CHECK-NEXT: s_endpgm
%f32 = atomicrmw fsub float addrspace(1)* %p, float 1.0 monotonic %f32 = atomicrmw fsub float addrspace(1)* %p, float 1.0 monotonic
▲ Show 20 Lines • Show All 438 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll

Show All 20 Lines
; ISA-NEXT: v_readfirstlane_b32 s0, v0 ; ISA-NEXT: v_readfirstlane_b32 s0, v0
; ISA-NEXT: s_mov_b32 m0, s0 ; ISA-NEXT: s_mov_b32 m0, s0
; ISA-NEXT: s_mov_b32 s8, 0 ; ISA-NEXT: s_mov_b32 s8, 0
; ISA-NEXT: v_interp_p1_f32_e32 v0, v1, attr0.x ; ISA-NEXT: v_interp_p1_f32_e32 v0, v1, attr0.x
; ISA-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v0 ; ISA-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v0
; ISA-NEXT: s_mov_b64 s[0:1], 0 ; ISA-NEXT: s_mov_b64 s[0:1], 0
; ISA-NEXT: ; implicit-def: $sgpr4_sgpr5 ; ISA-NEXT: ; implicit-def: $sgpr4_sgpr5
; ISA-NEXT: ; implicit-def: $sgpr2_sgpr3 ; ISA-NEXT: ; implicit-def: $sgpr2_sgpr3
; ISA-NEXT: s_branch BB0_3 ; ISA-NEXT: s_branch .LBB0_3
; ISA-NEXT: BB0_1: ; %Flow1 ; ISA-NEXT: .LBB0_1: ; %Flow1
; ISA-NEXT: ; in Loop: Header=BB0_3 Depth=1 ; ISA-NEXT: ; in Loop: Header=BB0_3 Depth=1
; ISA-NEXT: s_or_b64 exec, exec, s[6:7] ; ISA-NEXT: s_or_b64 exec, exec, s[6:7]
; ISA-NEXT: s_add_i32 s8, s8, 1 ; ISA-NEXT: s_add_i32 s8, s8, 1
; ISA-NEXT: s_mov_b64 s[6:7], 0 ; ISA-NEXT: s_mov_b64 s[6:7], 0
; ISA-NEXT: BB0_2: ; %Flow ; ISA-NEXT: .LBB0_2: ; %Flow
; ISA-NEXT: ; in Loop: Header=BB0_3 Depth=1 ; ISA-NEXT: ; in Loop: Header=BB0_3 Depth=1
; ISA-NEXT: s_and_b64 s[10:11], exec, s[4:5] ; ISA-NEXT: s_and_b64 s[10:11], exec, s[4:5]
; ISA-NEXT: s_or_b64 s[0:1], s[10:11], s[0:1] ; ISA-NEXT: s_or_b64 s[0:1], s[10:11], s[0:1]
; ISA-NEXT: s_andn2_b64 s[2:3], s[2:3], exec ; ISA-NEXT: s_andn2_b64 s[2:3], s[2:3], exec
; ISA-NEXT: s_and_b64 s[6:7], s[6:7], exec ; ISA-NEXT: s_and_b64 s[6:7], s[6:7], exec
; ISA-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7] ; ISA-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7]
; ISA-NEXT: s_andn2_b64 exec, exec, s[0:1] ; ISA-NEXT: s_andn2_b64 exec, exec, s[0:1]
; ISA-NEXT: s_cbranch_execz BB0_6 ; ISA-NEXT: s_cbranch_execz .LBB0_6
; ISA-NEXT: BB0_3: ; %loop ; ISA-NEXT: .LBB0_3: ; %loop
; ISA-NEXT: ; =>This Inner Loop Header: Depth=1 ; ISA-NEXT: ; =>This Inner Loop Header: Depth=1
; ISA-NEXT: s_or_b64 s[4:5], s[4:5], exec ; ISA-NEXT: s_or_b64 s[4:5], s[4:5], exec
; ISA-NEXT: s_cmp_lt_u32 s8, 32 ; ISA-NEXT: s_cmp_lt_u32 s8, 32
; ISA-NEXT: s_mov_b64 s[6:7], -1 ; ISA-NEXT: s_mov_b64 s[6:7], -1
; ISA-NEXT: s_cbranch_scc0 BB0_2 ; ISA-NEXT: s_cbranch_scc0 .LBB0_2
; ISA-NEXT: ; %bb.4: ; %endif1 ; ISA-NEXT: ; %bb.4: ; %endif1
; ISA-NEXT: ; in Loop: Header=BB0_3 Depth=1 ; ISA-NEXT: ; in Loop: Header=BB0_3 Depth=1
; ISA-NEXT: s_mov_b64 s[4:5], -1 ; ISA-NEXT: s_mov_b64 s[4:5], -1
; ISA-NEXT: s_and_saveexec_b64 s[6:7], vcc ; ISA-NEXT: s_and_saveexec_b64 s[6:7], vcc
; ISA-NEXT: s_cbranch_execz BB0_1 ; ISA-NEXT: s_cbranch_execz .LBB0_1
; ISA-NEXT: ; %bb.5: ; %endif2 ; ISA-NEXT: ; %bb.5: ; %endif2
; ISA-NEXT: ; in Loop: Header=BB0_3 Depth=1 ; ISA-NEXT: ; in Loop: Header=BB0_3 Depth=1
; ISA-NEXT: s_xor_b64 s[4:5], exec, -1 ; ISA-NEXT: s_xor_b64 s[4:5], exec, -1
; ISA-NEXT: s_branch BB0_1 ; ISA-NEXT: s_branch .LBB0_1
; ISA-NEXT: BB0_6: ; %Flow2 ; ISA-NEXT: .LBB0_6: ; %Flow2
; ISA-NEXT: s_or_b64 exec, exec, s[0:1] ; ISA-NEXT: s_or_b64 exec, exec, s[0:1]
; ISA-NEXT: v_mov_b32_e32 v1, 0 ; ISA-NEXT: v_mov_b32_e32 v1, 0
; ISA-NEXT: s_and_saveexec_b64 s[0:1], s[2:3] ; ISA-NEXT: s_and_saveexec_b64 s[0:1], s[2:3]
; ISA-NEXT: ; %bb.7: ; %if1 ; ISA-NEXT: ; %bb.7: ; %if1
; ISA-NEXT: v_sqrt_f32_e32 v1, v0 ; ISA-NEXT: v_sqrt_f32_e32 v1, v0
; ISA-NEXT: ; %bb.8: ; %endloop ; ISA-NEXT: ; %bb.8: ; %endloop
; ISA-NEXT: s_or_b64 exec, exec, s[0:1] ; ISA-NEXT: s_or_b64 exec, exec, s[0:1]
; ISA-NEXT: exp mrt0 v1, v1, v1, v1 done vm ; ISA-NEXT: exp mrt0 v1, v1, v1, v1 done vm
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llvm/test/CodeGen/AMDGPU/early-if-convert.ll

Show First 20 Lines • Show All 106 Lines • ▼ Show 20 Lines
endif: endif:
%r = phi float [ %v, %entry ], [ %u.8, %if ] %r = phi float [ %v, %entry ], [ %u.8, %if ]
store float %r, float addrspace(1)* %out store float %r, float addrspace(1)* %out
ret void ret void
} }
; Short chain of cheap instructions to not convert ; Short chain of cheap instructions to not convert
; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle_min_expensive: ; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle_min_expensive:
; GCN: s_cbranch_vccnz [[ENDIF:BB[0-9]+_[0-9]+]] ; GCN: s_cbranch_vccnz [[ENDIF:.LBB[0-9]+_[0-9]+]]
; GCN: v_mul_f32 ; GCN: v_mul_f32
; GCN: v_mul_f32 ; GCN: v_mul_f32
; GCN: v_mul_f32 ; GCN: v_mul_f32
; GCN: v_mul_f32 ; GCN: v_mul_f32
; GCN: v_mul_f32 ; GCN: v_mul_f32
; GCN: v_mul_f32 ; GCN: v_mul_f32
; GCN: v_mul_f32 ; GCN: v_mul_f32
Show All 26 Linesendif:
%r = phi float [ %v, %entry ], [ %u.9, %if ] %r = phi float [ %v, %entry ], [ %u.9, %if ]
store float %r, float addrspace(1)* %out store float %r, float addrspace(1)* %out
ret void ret void
} }
; Should still branch over fdiv expansion ; Should still branch over fdiv expansion
; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle_expensive: ; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle_expensive:
; GCN: v_cmp_neq_f32_e32 ; GCN: v_cmp_neq_f32_e32
; GCN: s_cbranch_vccnz [[ENDIF:BB[0-9]+_[0-9]+]] ; GCN: s_cbranch_vccnz [[ENDIF:.LBB[0-9]+_[0-9]+]]
; GCN: v_div_scale_f32 ; GCN: v_div_scale_f32
; GCN: [[ENDIF]]: ; GCN: [[ENDIF]]:
; GCN: buffer_store_dword ; GCN: buffer_store_dword
define amdgpu_kernel void @test_vccnz_ifcvt_triangle_expensive(float addrspace(1)* %out, float addrspace(1)* %in) #0 { define amdgpu_kernel void @test_vccnz_ifcvt_triangle_expensive(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
entry: entry:
%v = load float, float addrspace(1)* %in %v = load float, float addrspace(1)* %in
%cc = fcmp oeq float %v, 1.000000e+00 %cc = fcmp oeq float %v, 1.000000e+00
br i1 %cc, label %if, label %endif br i1 %cc, label %if, label %endif
if: if:
%u = fdiv float %v, %v %u = fdiv float %v, %v
br label %endif br label %endif
endif: endif:
%r = phi float [ %v, %entry ], [ %u, %if ] %r = phi float [ %v, %entry ], [ %u, %if ]
store float %r, float addrspace(1)* %out store float %r, float addrspace(1)* %out
ret void ret void
} }
; vcc branch with SGPR inputs ; vcc branch with SGPR inputs
; GCN-LABEL: {{^}}test_vccnz_sgpr_ifcvt_triangle: ; GCN-LABEL: {{^}}test_vccnz_sgpr_ifcvt_triangle:
; GCN: v_cmp_neq_f32_e64 ; GCN: v_cmp_neq_f32_e64
; GCN: s_cbranch_vccnz [[ENDIF:BB[0-9]+_[0-9]+]] ; GCN: s_cbranch_vccnz [[ENDIF:.LBB[0-9]+_[0-9]+]]
; GCN: s_add_i32 ; GCN: s_add_i32
; GCN: [[ENDIF]]: ; GCN: [[ENDIF]]:
; GCN: buffer_store_dword ; GCN: buffer_store_dword
define amdgpu_kernel void @test_vccnz_sgpr_ifcvt_triangle(i32 addrspace(1)* %out, i32 addrspace(4)* %in, float %cnd) #0 { define amdgpu_kernel void @test_vccnz_sgpr_ifcvt_triangle(i32 addrspace(1)* %out, i32 addrspace(4)* %in, float %cnd) #0 {
entry: entry:
%v = load i32, i32 addrspace(4)* %in %v = load i32, i32 addrspace(4)* %in
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Linesendif:
call void asm sideeffect "; reg use $0", "s"(i32 %r) #0 call void asm sideeffect "; reg use $0", "s"(i32 %r) #0
ret void ret void
} }
; FIXME: Should be able to use VALU compare and select ; FIXME: Should be able to use VALU compare and select
; Scalar branch but VGPR select operands ; Scalar branch but VGPR select operands
; GCN-LABEL: {{^}}test_scc1_vgpr_ifcvt_triangle: ; GCN-LABEL: {{^}}test_scc1_vgpr_ifcvt_triangle:
; GCN: s_cmp_lg_u32 ; GCN: s_cmp_lg_u32
; GCN: s_cbranch_scc1 [[ENDIF:BB[0-9]+_[0-9]+]] ; GCN: s_cbranch_scc1 [[ENDIF:.LBB[0-9]+_[0-9]+]]
; GCN: v_add_f32_e32 ; GCN: v_add_f32_e32
; GCN: [[ENDIF]]: ; GCN: [[ENDIF]]:
; GCN: buffer_store_dword ; GCN: buffer_store_dword
define amdgpu_kernel void @test_scc1_vgpr_ifcvt_triangle(float addrspace(1)* %out, float addrspace(1)* %in, i32 %cond) #0 { define amdgpu_kernel void @test_scc1_vgpr_ifcvt_triangle(float addrspace(1)* %out, float addrspace(1)* %in, i32 %cond) #0 {
entry: entry:
%v = load float, float addrspace(1)* %in %v = load float, float addrspace(1)* %in
▲ Show 20 Lines • Show All 118 Lines • ▼ Show 20 Lines
done: done:
%value = phi i32 [0, %if], [1, %else] %value = phi i32 [0, %if], [1, %else]
store i32 %value, i32 addrspace(1)* %out store i32 %value, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle256: ; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle256:
; GCN: v_cmp_neq_f32 ; GCN: v_cmp_neq_f32
; GCN: s_cbranch_vccnz [[ENDIF:BB[0-9]+_[0-9]+]] ; GCN: s_cbranch_vccnz [[ENDIF:.LBB[0-9]+_[0-9]+]]
; GCN: v_add_i32 ; GCN: v_add_i32
; GCN: v_add_i32 ; GCN: v_add_i32
; GCN: [[ENDIF]]: ; GCN: [[ENDIF]]:
; GCN: buffer_store_dword ; GCN: buffer_store_dword
define amdgpu_kernel void @test_vccnz_ifcvt_triangle256(<8 x i32> addrspace(1)* %out, <8 x i32> addrspace(1)* %in, float %cnd) #0 { define amdgpu_kernel void @test_vccnz_ifcvt_triangle256(<8 x i32> addrspace(1)* %out, <8 x i32> addrspace(1)* %in, float %cnd) #0 {
entry: entry:
%v = load <8 x i32>, <8 x i32> addrspace(1)* %in %v = load <8 x i32>, <8 x i32> addrspace(1)* %in
%cc = fcmp oeq float %cnd, 1.000000e+00 %cc = fcmp oeq float %cnd, 1.000000e+00
br i1 %cc, label %if, label %endif br i1 %cc, label %if, label %endif
if: if:
%u = add <8 x i32> %v, %v %u = add <8 x i32> %v, %v
br label %endif br label %endif
endif: endif:
%r = phi <8 x i32> [ %v, %entry ], [ %u, %if ] %r = phi <8 x i32> [ %v, %entry ], [ %u, %if ]
store <8 x i32> %r, <8 x i32> addrspace(1)* %out store <8 x i32> %r, <8 x i32> addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle512: ; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle512:
; GCN: v_cmp_neq_f32 ; GCN: v_cmp_neq_f32
; GCN: s_cbranch_vccnz [[ENDIF:BB[0-9]+_[0-9]+]] ; GCN: s_cbranch_vccnz [[ENDIF:.LBB[0-9]+_[0-9]+]]
; GCN: v_add_i32 ; GCN: v_add_i32
; GCN: v_add_i32 ; GCN: v_add_i32
; GCN: [[ENDIF]]: ; GCN: [[ENDIF]]:
; GCN: buffer_store_dword ; GCN: buffer_store_dword
define amdgpu_kernel void @test_vccnz_ifcvt_triangle512(<16 x i32> addrspace(1)* %out, <16 x i32> addrspace(1)* %in, float %cnd) #0 { define amdgpu_kernel void @test_vccnz_ifcvt_triangle512(<16 x i32> addrspace(1)* %out, <16 x i32> addrspace(1)* %in, float %cnd) #0 {
entry: entry:
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llvm/test/CodeGen/AMDGPU/endcf-loop-header.ll

; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s
; This tests that the llvm.SI.end.cf intrinsic is not inserted into the ; This tests that the llvm.SI.end.cf intrinsic is not inserted into the
; loop block. This intrinsic will be lowered to s_or_b64 by the code ; loop block. This intrinsic will be lowered to s_or_b64 by the code
; generator. ; generator.
; CHECK-LABEL: {{^}}test: ; CHECK-LABEL: {{^}}test:
; This is was lowered from the llvm.SI.end.cf intrinsic: ; This is was lowered from the llvm.SI.end.cf intrinsic:
; CHECK: s_or_b64 exec, exec ; CHECK: s_or_b64 exec, exec
; CHECK: [[LOOP_LABEL:[0-9A-Za-z_]+]]: ; %loop{{$}} ; CHECK: [[LOOP_LABEL:.L[0-9A-Za-z_]+]]: ; %loop{{$}}
; CHECK-NOT: s_or_b64 exec, exec ; CHECK-NOT: s_or_b64 exec, exec
; CHECK: s_cbranch_execnz [[LOOP_LABEL]] ; CHECK: s_cbranch_execnz [[LOOP_LABEL]]
define amdgpu_kernel void @test(i32 addrspace(1)* %out) { define amdgpu_kernel void @test(i32 addrspace(1)* %out) {
entry: entry:
%cond = call i32 @llvm.amdgcn.workitem.id.x() #0 %cond = call i32 @llvm.amdgcn.workitem.id.x() #0
%tmp0 = icmp eq i32 %cond, 0 %tmp0 = icmp eq i32 %cond, 0
br i1 %tmp0, label %if, label %loop br i1 %tmp0, label %if, label %loop
Show All 19 Lines

llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll

Show First 20 Lines • Show All 77 Lines • ▼ Show 20 Lines
; GFX7-NEXT: s_cmp_lt_u32 s0, s2 ; GFX7-NEXT: s_cmp_lt_u32 s0, s2
; GFX7-NEXT: s_cselect_b64 s[0:1], -1, 0 ; GFX7-NEXT: s_cselect_b64 s[0:1], -1, 0
; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] ; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; GFX7-NEXT: s_or_b32 s0, s0, s1 ; GFX7-NEXT: s_or_b32 s0, s0, s1
; GFX7-NEXT: s_cmp_lg_u32 s0, 0 ; GFX7-NEXT: s_cmp_lg_u32 s0, 0
; GFX7-NEXT: s_addc_u32 s0, s2, 0 ; GFX7-NEXT: s_addc_u32 s0, s2, 0
; GFX7-NEXT: v_cmp_ge_u32_e32 vcc, s0, v0 ; GFX7-NEXT: v_cmp_ge_u32_e32 vcc, s0, v0
; GFX7-NEXT: s_and_b64 vcc, exec, vcc ; GFX7-NEXT: s_and_b64 vcc, exec, vcc
; GFX7-NEXT: s_cbranch_vccnz BB1_2 ; GFX7-NEXT: s_cbranch_vccnz .LBB1_2
; GFX7-NEXT: ; %bb.1: ; %bb0 ; GFX7-NEXT: ; %bb.1: ; %bb0
; GFX7-NEXT: v_mov_b32_e32 v0, 0 ; GFX7-NEXT: v_mov_b32_e32 v0, 0
; GFX7-NEXT: v_mov_b32_e32 v1, 0 ; GFX7-NEXT: v_mov_b32_e32 v1, 0
; GFX7-NEXT: v_mov_b32_e32 v2, 9 ; GFX7-NEXT: v_mov_b32_e32 v2, 9
; GFX7-NEXT: flat_store_dword v[0:1], v2 ; GFX7-NEXT: flat_store_dword v[0:1], v2
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: BB1_2: ; %bb1 ; GFX7-NEXT: .LBB1_2: ; %bb1
; GFX7-NEXT: v_mov_b32_e32 v0, 0 ; GFX7-NEXT: v_mov_b32_e32 v0, 0
; GFX7-NEXT: v_mov_b32_e32 v1, 0 ; GFX7-NEXT: v_mov_b32_e32 v1, 0
; GFX7-NEXT: v_mov_b32_e32 v2, 10 ; GFX7-NEXT: v_mov_b32_e32 v2, 10
; GFX7-NEXT: flat_store_dword v[0:1], v2 ; GFX7-NEXT: flat_store_dword v[0:1], v2
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX9-LABEL: s_add_co_br_user: ; GFX9-LABEL: s_add_co_br_user:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_load_dword s2, s[4:5], 0x0 ; GFX9-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_add_i32 s0, s2, s2 ; GFX9-NEXT: s_add_i32 s0, s2, s2
; GFX9-NEXT: s_cmp_lt_u32 s0, s2 ; GFX9-NEXT: s_cmp_lt_u32 s0, s2
; GFX9-NEXT: s_cselect_b64 s[0:1], -1, 0 ; GFX9-NEXT: s_cselect_b64 s[0:1], -1, 0
; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0 ; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; GFX9-NEXT: s_addc_u32 s0, s2, 0 ; GFX9-NEXT: s_addc_u32 s0, s2, 0
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, s0, v0 ; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, s0, v0
; GFX9-NEXT: s_and_b64 vcc, exec, vcc ; GFX9-NEXT: s_and_b64 vcc, exec, vcc
; GFX9-NEXT: s_cbranch_vccnz BB1_2 ; GFX9-NEXT: s_cbranch_vccnz .LBB1_2
; GFX9-NEXT: ; %bb.1: ; %bb0 ; GFX9-NEXT: ; %bb.1: ; %bb0
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: v_mov_b32_e32 v2, 9 ; GFX9-NEXT: v_mov_b32_e32 v2, 9
; GFX9-NEXT: global_store_dword v[0:1], v2, off ; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: BB1_2: ; %bb1 ; GFX9-NEXT: .LBB1_2: ; %bb1
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: v_mov_b32_e32 v2, 10 ; GFX9-NEXT: v_mov_b32_e32 v2, 10
; GFX9-NEXT: global_store_dword v[0:1], v2, off ; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: s_add_co_br_user: ; GFX10-LABEL: s_add_co_br_user:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_load_dword s0, s[4:5], 0x0 ; GFX10-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_add_i32 s1, s0, s0 ; GFX10-NEXT: s_add_i32 s1, s0, s0
; GFX10-NEXT: s_cmp_lt_u32 s1, s0 ; GFX10-NEXT: s_cmp_lt_u32 s1, s0
; GFX10-NEXT: s_cselect_b32 s1, -1, 0 ; GFX10-NEXT: s_cselect_b32 s1, -1, 0
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s1
; GFX10-NEXT: s_cmpk_lg_u32 s1, 0x0 ; GFX10-NEXT: s_cmpk_lg_u32 s1, 0x0
; GFX10-NEXT: s_addc_u32 s0, s0, 0 ; GFX10-NEXT: s_addc_u32 s0, s0, 0
; GFX10-NEXT: v_cmp_ge_u32_e32 vcc_lo, s0, v0 ; GFX10-NEXT: v_cmp_ge_u32_e32 vcc_lo, s0, v0
; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, vcc_lo ; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, vcc_lo
; GFX10-NEXT: s_cbranch_vccnz BB1_2 ; GFX10-NEXT: s_cbranch_vccnz .LBB1_2
; GFX10-NEXT: ; %bb.1: ; %bb0 ; GFX10-NEXT: ; %bb.1: ; %bb0
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: v_mov_b32_e32 v2, 9 ; GFX10-NEXT: v_mov_b32_e32 v2, 9
; GFX10-NEXT: global_store_dword v[0:1], v2, off ; GFX10-NEXT: global_store_dword v[0:1], v2, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: BB1_2: ; %bb1 ; GFX10-NEXT: .LBB1_2: ; %bb1
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: v_mov_b32_e32 v2, 10 ; GFX10-NEXT: v_mov_b32_e32 v2, 10
; GFX10-NEXT: global_store_dword v[0:1], v2, off ; GFX10-NEXT: global_store_dword v[0:1], v2, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
bb: bb:
%i1 = add i32 %i, %i %i1 = add i32 %i, %i
Show All 16 Lines

llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll

Show First 20 Lines • Show All 415 Lines • ▼ Show 20 Lines
; GFX90A: ; %bb.0: ; %main_body ; GFX90A: ; %bb.0: ; %main_body
; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX90A-NEXT: s_mov_b64 s[2:3], 0 ; GFX90A-NEXT: s_mov_b64 s[2:3], 0
; GFX90A-NEXT: v_mov_b32_e32 v4, 0 ; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0 ; GFX90A-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: v_pk_mov_b32 v[2:3], s[4:5], s[4:5] op_sel:[0,1] ; GFX90A-NEXT: v_pk_mov_b32 v[2:3], s[4:5], s[4:5] op_sel:[0,1]
; GFX90A-NEXT: BB24_1: ; %atomicrmw.start ; GFX90A-NEXT: .LBB24_1: ; %atomicrmw.start
; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX90A-NEXT: v_add_f64 v[0:1], v[2:3], 4.0 ; GFX90A-NEXT: v_add_f64 v[0:1], v[2:3], 4.0
; GFX90A-NEXT: buffer_wbl2 ; GFX90A-NEXT: buffer_wbl2
; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-NEXT: global_atomic_cmpswap_x2 v[0:1], v4, v[0:3], s[0:1] glc ; GFX90A-NEXT: global_atomic_cmpswap_x2 v[0:1], v4, v[0:3], s[0:1] glc
; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: buffer_invl2 ; GFX90A-NEXT: buffer_invl2
; GFX90A-NEXT: buffer_wbinvl1_vol ; GFX90A-NEXT: buffer_wbinvl1_vol
; GFX90A-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[2:3] ; GFX90A-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[2:3]
; GFX90A-NEXT: s_or_b64 s[2:3], vcc, s[2:3] ; GFX90A-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX90A-NEXT: v_pk_mov_b32 v[2:3], v[0:1], v[0:1] op_sel:[0,1] ; GFX90A-NEXT: v_pk_mov_b32 v[2:3], v[0:1], v[0:1] op_sel:[0,1]
; GFX90A-NEXT: s_andn2_b64 exec, exec, s[2:3] ; GFX90A-NEXT: s_andn2_b64 exec, exec, s[2:3]
; GFX90A-NEXT: s_cbranch_execnz BB24_1 ; GFX90A-NEXT: s_cbranch_execnz .LBB24_1
; GFX90A-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX90A-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX90A-NEXT: s_endpgm ; GFX90A-NEXT: s_endpgm
main_body: main_body:
%ret = atomicrmw fadd double addrspace(1)* %ptr, double 4.0 seq_cst %ret = atomicrmw fadd double addrspace(1)* %ptr, double 4.0 seq_cst
ret void ret void
} }
define amdgpu_kernel void @global_atomic_fadd_f64_noret_pat_agent(double addrspace(1)* %ptr) #1 { define amdgpu_kernel void @global_atomic_fadd_f64_noret_pat_agent(double addrspace(1)* %ptr) #1 {
Show All 18 Lines
; GFX90A: ; %bb.0: ; %main_body ; GFX90A: ; %bb.0: ; %main_body
; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX90A-NEXT: s_mov_b64 s[2:3], 0 ; GFX90A-NEXT: s_mov_b64 s[2:3], 0
; GFX90A-NEXT: v_mov_b32_e32 v4, 0 ; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0 ; GFX90A-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: v_pk_mov_b32 v[2:3], s[4:5], s[4:5] op_sel:[0,1] ; GFX90A-NEXT: v_pk_mov_b32 v[2:3], s[4:5], s[4:5] op_sel:[0,1]
; GFX90A-NEXT: BB26_1: ; %atomicrmw.start ; GFX90A-NEXT: .LBB26_1: ; %atomicrmw.start
; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX90A-NEXT: v_add_f64 v[0:1], v[2:3], 4.0 ; GFX90A-NEXT: v_add_f64 v[0:1], v[2:3], 4.0
; GFX90A-NEXT: buffer_wbl2 ; GFX90A-NEXT: buffer_wbl2
; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: global_atomic_cmpswap_x2 v[0:1], v4, v[0:3], s[0:1] glc ; GFX90A-NEXT: global_atomic_cmpswap_x2 v[0:1], v4, v[0:3], s[0:1] glc
; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: buffer_invl2 ; GFX90A-NEXT: buffer_invl2
; GFX90A-NEXT: buffer_wbinvl1_vol ; GFX90A-NEXT: buffer_wbinvl1_vol
; GFX90A-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[2:3] ; GFX90A-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[2:3]
; GFX90A-NEXT: s_or_b64 s[2:3], vcc, s[2:3] ; GFX90A-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX90A-NEXT: v_pk_mov_b32 v[2:3], v[0:1], v[0:1] op_sel:[0,1] ; GFX90A-NEXT: v_pk_mov_b32 v[2:3], v[0:1], v[0:1] op_sel:[0,1]
; GFX90A-NEXT: s_andn2_b64 exec, exec, s[2:3] ; GFX90A-NEXT: s_andn2_b64 exec, exec, s[2:3]
; GFX90A-NEXT: s_cbranch_execnz BB26_1 ; GFX90A-NEXT: s_cbranch_execnz .LBB26_1
; GFX90A-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX90A-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX90A-NEXT: s_endpgm ; GFX90A-NEXT: s_endpgm
main_body: main_body:
%ret = atomicrmw fadd double addrspace(1)* %ptr, double 4.0 syncscope("one-as") seq_cst %ret = atomicrmw fadd double addrspace(1)* %ptr, double 4.0 syncscope("one-as") seq_cst
ret void ret void
} }
define amdgpu_kernel void @global_atomic_fadd_f64_noret_pat_flush(double addrspace(1)* %ptr) #0 { define amdgpu_kernel void @global_atomic_fadd_f64_noret_pat_flush(double addrspace(1)* %ptr) #0 {
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} }
define double @global_atomic_fadd_f64_rtn_pat(double addrspace(1)* %ptr, double %data) #1 { define double @global_atomic_fadd_f64_rtn_pat(double addrspace(1)* %ptr, double %data) #1 {
; GFX90A-LABEL: global_atomic_fadd_f64_rtn_pat: ; GFX90A-LABEL: global_atomic_fadd_f64_rtn_pat:
; GFX90A: ; %bb.0: ; %main_body ; GFX90A: ; %bb.0: ; %main_body
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: global_load_dwordx2 v[2:3], v[0:1], off ; GFX90A-NEXT: global_load_dwordx2 v[2:3], v[0:1], off
; GFX90A-NEXT: s_mov_b64 s[4:5], 0 ; GFX90A-NEXT: s_mov_b64 s[4:5], 0
; GFX90A-NEXT: BB29_1: ; %atomicrmw.start ; GFX90A-NEXT: .LBB29_1: ; %atomicrmw.start
; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: v_pk_mov_b32 v[4:5], v[2:3], v[2:3] op_sel:[0,1] ; GFX90A-NEXT: v_pk_mov_b32 v[4:5], v[2:3], v[2:3] op_sel:[0,1]
; GFX90A-NEXT: v_add_f64 v[2:3], v[4:5], 4.0 ; GFX90A-NEXT: v_add_f64 v[2:3], v[4:5], 4.0
; GFX90A-NEXT: buffer_wbl2 ; GFX90A-NEXT: buffer_wbl2
; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-NEXT: global_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5], off glc ; GFX90A-NEXT: global_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5], off glc
; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: buffer_invl2 ; GFX90A-NEXT: buffer_invl2
; GFX90A-NEXT: buffer_wbinvl1_vol ; GFX90A-NEXT: buffer_wbinvl1_vol
; GFX90A-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[4:5] ; GFX90A-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[4:5]
; GFX90A-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GFX90A-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX90A-NEXT: s_andn2_b64 exec, exec, s[4:5] ; GFX90A-NEXT: s_andn2_b64 exec, exec, s[4:5]
; GFX90A-NEXT: s_cbranch_execnz BB29_1 ; GFX90A-NEXT: s_cbranch_execnz .LBB29_1
; GFX90A-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX90A-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX90A-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX90A-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX90A-NEXT: v_mov_b32_e32 v0, v2 ; GFX90A-NEXT: v_mov_b32_e32 v0, v2
; GFX90A-NEXT: v_mov_b32_e32 v1, v3 ; GFX90A-NEXT: v_mov_b32_e32 v1, v3
; GFX90A-NEXT: s_setpc_b64 s[30:31] ; GFX90A-NEXT: s_setpc_b64 s[30:31]
main_body: main_body:
%ret = atomicrmw fadd double addrspace(1)* %ptr, double 4.0 seq_cst %ret = atomicrmw fadd double addrspace(1)* %ptr, double 4.0 seq_cst
ret double %ret ret double %ret
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} }
define double @global_atomic_fadd_f64_rtn_pat_system(double addrspace(1)* %ptr, double %data) #1 { define double @global_atomic_fadd_f64_rtn_pat_system(double addrspace(1)* %ptr, double %data) #1 {
; GFX90A-LABEL: global_atomic_fadd_f64_rtn_pat_system: ; GFX90A-LABEL: global_atomic_fadd_f64_rtn_pat_system:
; GFX90A: ; %bb.0: ; %main_body ; GFX90A: ; %bb.0: ; %main_body
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: global_load_dwordx2 v[2:3], v[0:1], off ; GFX90A-NEXT: global_load_dwordx2 v[2:3], v[0:1], off
; GFX90A-NEXT: s_mov_b64 s[4:5], 0 ; GFX90A-NEXT: s_mov_b64 s[4:5], 0
; GFX90A-NEXT: BB31_1: ; %atomicrmw.start ; GFX90A-NEXT: .LBB31_1: ; %atomicrmw.start
; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: v_pk_mov_b32 v[4:5], v[2:3], v[2:3] op_sel:[0,1] ; GFX90A-NEXT: v_pk_mov_b32 v[4:5], v[2:3], v[2:3] op_sel:[0,1]
; GFX90A-NEXT: v_add_f64 v[2:3], v[4:5], 4.0 ; GFX90A-NEXT: v_add_f64 v[2:3], v[4:5], 4.0
; GFX90A-NEXT: buffer_wbl2 ; GFX90A-NEXT: buffer_wbl2
; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: global_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5], off glc ; GFX90A-NEXT: global_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5], off glc
; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: buffer_invl2 ; GFX90A-NEXT: buffer_invl2
; GFX90A-NEXT: buffer_wbinvl1_vol ; GFX90A-NEXT: buffer_wbinvl1_vol
; GFX90A-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[4:5] ; GFX90A-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[4:5]
; GFX90A-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GFX90A-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX90A-NEXT: s_andn2_b64 exec, exec, s[4:5] ; GFX90A-NEXT: s_andn2_b64 exec, exec, s[4:5]
; GFX90A-NEXT: s_cbranch_execnz BB31_1 ; GFX90A-NEXT: s_cbranch_execnz .LBB31_1
; GFX90A-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX90A-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX90A-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX90A-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX90A-NEXT: v_mov_b32_e32 v0, v2 ; GFX90A-NEXT: v_mov_b32_e32 v0, v2
; GFX90A-NEXT: v_mov_b32_e32 v1, v3 ; GFX90A-NEXT: v_mov_b32_e32 v1, v3
; GFX90A-NEXT: s_setpc_b64 s[30:31] ; GFX90A-NEXT: s_setpc_b64 s[30:31]
main_body: main_body:
%ret = atomicrmw fadd double addrspace(1)* %ptr, double 4.0 syncscope("one-as") seq_cst %ret = atomicrmw fadd double addrspace(1)* %ptr, double 4.0 syncscope("one-as") seq_cst
ret double %ret ret double %ret
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; GFX90A: ; %bb.0: ; %main_body ; GFX90A: ; %bb.0: ; %main_body
; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX90A-NEXT: s_mov_b64 s[2:3], 0 ; GFX90A-NEXT: s_mov_b64 s[2:3], 0
; GFX90A-NEXT: v_mov_b32_e32 v4, 0 ; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0 ; GFX90A-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: v_pk_mov_b32 v[2:3], s[4:5], s[4:5] op_sel:[0,1] ; GFX90A-NEXT: v_pk_mov_b32 v[2:3], s[4:5], s[4:5] op_sel:[0,1]
; GFX90A-NEXT: BB34_1: ; %atomicrmw.start ; GFX90A-NEXT: .LBB34_1: ; %atomicrmw.start
; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX90A-NEXT: v_add_f64 v[0:1], v[2:3], 4.0 ; GFX90A-NEXT: v_add_f64 v[0:1], v[2:3], 4.0
; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-NEXT: global_atomic_cmpswap_x2 v[0:1], v4, v[0:3], s[0:1] glc ; GFX90A-NEXT: global_atomic_cmpswap_x2 v[0:1], v4, v[0:3], s[0:1] glc
; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: buffer_wbinvl1_vol ; GFX90A-NEXT: buffer_wbinvl1_vol
; GFX90A-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[2:3] ; GFX90A-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[2:3]
; GFX90A-NEXT: s_or_b64 s[2:3], vcc, s[2:3] ; GFX90A-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX90A-NEXT: v_pk_mov_b32 v[2:3], v[0:1], v[0:1] op_sel:[0,1] ; GFX90A-NEXT: v_pk_mov_b32 v[2:3], v[0:1], v[0:1] op_sel:[0,1]
; GFX90A-NEXT: s_andn2_b64 exec, exec, s[2:3] ; GFX90A-NEXT: s_andn2_b64 exec, exec, s[2:3]
; GFX90A-NEXT: s_cbranch_execnz BB34_1 ; GFX90A-NEXT: s_cbranch_execnz .LBB34_1
; GFX90A-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX90A-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX90A-NEXT: s_endpgm ; GFX90A-NEXT: s_endpgm
main_body: main_body:
%ret = atomicrmw fadd double addrspace(1)* %ptr, double 4.0 syncscope("agent") seq_cst %ret = atomicrmw fadd double addrspace(1)* %ptr, double 4.0 syncscope("agent") seq_cst
ret void ret void
} }
define amdgpu_kernel void @flat_atomic_fadd_f64_noret_pat(double* %ptr) #1 { define amdgpu_kernel void @flat_atomic_fadd_f64_noret_pat(double* %ptr) #1 {
; GFX90A-LABEL: flat_atomic_fadd_f64_noret_pat: ; GFX90A-LABEL: flat_atomic_fadd_f64_noret_pat:
; GFX90A: ; %bb.0: ; %main_body ; GFX90A: ; %bb.0: ; %main_body
; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX90A-NEXT: s_mov_b64 s[2:3], 0 ; GFX90A-NEXT: s_mov_b64 s[2:3], 0
; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1] ; GFX90A-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
; GFX90A-NEXT: flat_load_dwordx2 v[2:3], v[0:1] ; GFX90A-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
; GFX90A-NEXT: BB35_1: ; %atomicrmw.start ; GFX90A-NEXT: .LBB35_1: ; %atomicrmw.start
; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-NEXT: v_add_f64 v[0:1], v[2:3], 4.0 ; GFX90A-NEXT: v_add_f64 v[0:1], v[2:3], 4.0
; GFX90A-NEXT: v_pk_mov_b32 v[4:5], s[0:1], s[0:1] op_sel:[0,1] ; GFX90A-NEXT: v_pk_mov_b32 v[4:5], s[0:1], s[0:1] op_sel:[0,1]
; GFX90A-NEXT: buffer_wbl2 ; GFX90A-NEXT: buffer_wbl2
; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc ; GFX90A-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-NEXT: buffer_invl2 ; GFX90A-NEXT: buffer_invl2
; GFX90A-NEXT: buffer_wbinvl1_vol ; GFX90A-NEXT: buffer_wbinvl1_vol
; GFX90A-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[2:3] ; GFX90A-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[2:3]
; GFX90A-NEXT: s_or_b64 s[2:3], vcc, s[2:3] ; GFX90A-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX90A-NEXT: v_pk_mov_b32 v[2:3], v[0:1], v[0:1] op_sel:[0,1] ; GFX90A-NEXT: v_pk_mov_b32 v[2:3], v[0:1], v[0:1] op_sel:[0,1]
; GFX90A-NEXT: s_andn2_b64 exec, exec, s[2:3] ; GFX90A-NEXT: s_andn2_b64 exec, exec, s[2:3]
; GFX90A-NEXT: s_cbranch_execnz BB35_1 ; GFX90A-NEXT: s_cbranch_execnz .LBB35_1
; GFX90A-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX90A-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX90A-NEXT: s_endpgm ; GFX90A-NEXT: s_endpgm
main_body: main_body:
%ret = atomicrmw fadd double* %ptr, double 4.0 seq_cst %ret = atomicrmw fadd double* %ptr, double 4.0 seq_cst
ret void ret void
} }
define amdgpu_kernel void @flat_atomic_fadd_f64_noret_pat_agent(double* %ptr) #1 { define amdgpu_kernel void @flat_atomic_fadd_f64_noret_pat_agent(double* %ptr) #1 {
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define amdgpu_kernel void @flat_atomic_fadd_f64_noret_pat_system(double* %ptr) #1 { define amdgpu_kernel void @flat_atomic_fadd_f64_noret_pat_system(double* %ptr) #1 {
; GFX90A-LABEL: flat_atomic_fadd_f64_noret_pat_system: ; GFX90A-LABEL: flat_atomic_fadd_f64_noret_pat_system:
; GFX90A: ; %bb.0: ; %main_body ; GFX90A: ; %bb.0: ; %main_body
; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX90A-NEXT: s_mov_b64 s[2:3], 0 ; GFX90A-NEXT: s_mov_b64 s[2:3], 0
; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1] ; GFX90A-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
; GFX90A-NEXT: flat_load_dwordx2 v[2:3], v[0:1] ; GFX90A-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
; GFX90A-NEXT: BB37_1: ; %atomicrmw.start ; GFX90A-NEXT: .LBB37_1: ; %atomicrmw.start
; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-NEXT: v_add_f64 v[0:1], v[2:3], 4.0 ; GFX90A-NEXT: v_add_f64 v[0:1], v[2:3], 4.0
; GFX90A-NEXT: v_pk_mov_b32 v[4:5], s[0:1], s[0:1] op_sel:[0,1] ; GFX90A-NEXT: v_pk_mov_b32 v[4:5], s[0:1], s[0:1] op_sel:[0,1]
; GFX90A-NEXT: buffer_wbl2 ; GFX90A-NEXT: buffer_wbl2
; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc ; GFX90A-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: buffer_invl2 ; GFX90A-NEXT: buffer_invl2
; GFX90A-NEXT: buffer_wbinvl1_vol ; GFX90A-NEXT: buffer_wbinvl1_vol
; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[2:3] ; GFX90A-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[2:3]
; GFX90A-NEXT: s_or_b64 s[2:3], vcc, s[2:3] ; GFX90A-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX90A-NEXT: v_pk_mov_b32 v[2:3], v[0:1], v[0:1] op_sel:[0,1] ; GFX90A-NEXT: v_pk_mov_b32 v[2:3], v[0:1], v[0:1] op_sel:[0,1]
; GFX90A-NEXT: s_andn2_b64 exec, exec, s[2:3] ; GFX90A-NEXT: s_andn2_b64 exec, exec, s[2:3]
; GFX90A-NEXT: s_cbranch_execnz BB37_1 ; GFX90A-NEXT: s_cbranch_execnz .LBB37_1
; GFX90A-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX90A-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX90A-NEXT: s_endpgm ; GFX90A-NEXT: s_endpgm
main_body: main_body:
%ret = atomicrmw fadd double* %ptr, double 4.0 syncscope("one-as") seq_cst %ret = atomicrmw fadd double* %ptr, double 4.0 syncscope("one-as") seq_cst
ret void ret void
} }
define double @flat_atomic_fadd_f64_rtn_pat(double* %ptr) #1 { define double @flat_atomic_fadd_f64_rtn_pat(double* %ptr) #1 {
; GFX90A-LABEL: flat_atomic_fadd_f64_rtn_pat: ; GFX90A-LABEL: flat_atomic_fadd_f64_rtn_pat:
; GFX90A: ; %bb.0: ; %main_body ; GFX90A: ; %bb.0: ; %main_body
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: flat_load_dwordx2 v[2:3], v[0:1] ; GFX90A-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
; GFX90A-NEXT: s_mov_b64 s[4:5], 0 ; GFX90A-NEXT: s_mov_b64 s[4:5], 0
; GFX90A-NEXT: BB38_1: ; %atomicrmw.start ; GFX90A-NEXT: .LBB38_1: ; %atomicrmw.start
; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-NEXT: v_pk_mov_b32 v[4:5], v[2:3], v[2:3] op_sel:[0,1] ; GFX90A-NEXT: v_pk_mov_b32 v[4:5], v[2:3], v[2:3] op_sel:[0,1]
; GFX90A-NEXT: v_add_f64 v[2:3], v[4:5], 4.0 ; GFX90A-NEXT: v_add_f64 v[2:3], v[4:5], 4.0
; GFX90A-NEXT: buffer_wbl2 ; GFX90A-NEXT: buffer_wbl2
; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] glc ; GFX90A-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] glc
; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-NEXT: buffer_invl2 ; GFX90A-NEXT: buffer_invl2
; GFX90A-NEXT: buffer_wbinvl1_vol ; GFX90A-NEXT: buffer_wbinvl1_vol
; GFX90A-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[4:5] ; GFX90A-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[4:5]
; GFX90A-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GFX90A-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX90A-NEXT: s_andn2_b64 exec, exec, s[4:5] ; GFX90A-NEXT: s_andn2_b64 exec, exec, s[4:5]
; GFX90A-NEXT: s_cbranch_execnz BB38_1 ; GFX90A-NEXT: s_cbranch_execnz .LBB38_1
; GFX90A-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX90A-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX90A-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX90A-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX90A-NEXT: v_mov_b32_e32 v0, v2 ; GFX90A-NEXT: v_mov_b32_e32 v0, v2
; GFX90A-NEXT: v_mov_b32_e32 v1, v3 ; GFX90A-NEXT: v_mov_b32_e32 v1, v3
; GFX90A-NEXT: s_setpc_b64 s[30:31] ; GFX90A-NEXT: s_setpc_b64 s[30:31]
main_body: main_body:
%ret = atomicrmw fadd double* %ptr, double 4.0 seq_cst %ret = atomicrmw fadd double* %ptr, double 4.0 seq_cst
ret double %ret ret double %ret
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} }
define double @flat_atomic_fadd_f64_rtn_pat_system(double* %ptr) #1 { define double @flat_atomic_fadd_f64_rtn_pat_system(double* %ptr) #1 {
; GFX90A-LABEL: flat_atomic_fadd_f64_rtn_pat_system: ; GFX90A-LABEL: flat_atomic_fadd_f64_rtn_pat_system:
; GFX90A: ; %bb.0: ; %main_body ; GFX90A: ; %bb.0: ; %main_body
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: flat_load_dwordx2 v[2:3], v[0:1] ; GFX90A-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
; GFX90A-NEXT: s_mov_b64 s[4:5], 0 ; GFX90A-NEXT: s_mov_b64 s[4:5], 0
; GFX90A-NEXT: BB40_1: ; %atomicrmw.start ; GFX90A-NEXT: .LBB40_1: ; %atomicrmw.start
; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-NEXT: v_pk_mov_b32 v[4:5], v[2:3], v[2:3] op_sel:[0,1] ; GFX90A-NEXT: v_pk_mov_b32 v[4:5], v[2:3], v[2:3] op_sel:[0,1]
; GFX90A-NEXT: v_add_f64 v[2:3], v[4:5], 4.0 ; GFX90A-NEXT: v_add_f64 v[2:3], v[4:5], 4.0
; GFX90A-NEXT: buffer_wbl2 ; GFX90A-NEXT: buffer_wbl2
; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] glc ; GFX90A-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] glc
; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: buffer_invl2 ; GFX90A-NEXT: buffer_invl2
; GFX90A-NEXT: buffer_wbinvl1_vol ; GFX90A-NEXT: buffer_wbinvl1_vol
; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[4:5] ; GFX90A-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[4:5]
; GFX90A-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GFX90A-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX90A-NEXT: s_andn2_b64 exec, exec, s[4:5] ; GFX90A-NEXT: s_andn2_b64 exec, exec, s[4:5]
; GFX90A-NEXT: s_cbranch_execnz BB40_1 ; GFX90A-NEXT: s_cbranch_execnz .LBB40_1
; GFX90A-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX90A-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX90A-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX90A-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX90A-NEXT: v_mov_b32_e32 v0, v2 ; GFX90A-NEXT: v_mov_b32_e32 v0, v2
; GFX90A-NEXT: v_mov_b32_e32 v1, v3 ; GFX90A-NEXT: v_mov_b32_e32 v1, v3
; GFX90A-NEXT: s_setpc_b64 s[30:31] ; GFX90A-NEXT: s_setpc_b64 s[30:31]
main_body: main_body:
%ret = atomicrmw fadd double* %ptr, double 4.0 syncscope("one-as") seq_cst %ret = atomicrmw fadd double* %ptr, double 4.0 syncscope("one-as") seq_cst
ret double %ret ret double %ret
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define amdgpu_kernel void @flat_atomic_fadd_f64_noret_pat_agent_safe(double* %ptr) { define amdgpu_kernel void @flat_atomic_fadd_f64_noret_pat_agent_safe(double* %ptr) {
; GFX90A-LABEL: flat_atomic_fadd_f64_noret_pat_agent_safe: ; GFX90A-LABEL: flat_atomic_fadd_f64_noret_pat_agent_safe:
; GFX90A: ; %bb.0: ; %main_body ; GFX90A: ; %bb.0: ; %main_body
; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX90A-NEXT: s_mov_b64 s[2:3], 0 ; GFX90A-NEXT: s_mov_b64 s[2:3], 0
; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1] ; GFX90A-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
; GFX90A-NEXT: flat_load_dwordx2 v[2:3], v[0:1] ; GFX90A-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
; GFX90A-NEXT: BB43_1: ; %atomicrmw.start ; GFX90A-NEXT: .LBB43_1: ; %atomicrmw.start
; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-NEXT: v_add_f64 v[0:1], v[2:3], 4.0 ; GFX90A-NEXT: v_add_f64 v[0:1], v[2:3], 4.0
; GFX90A-NEXT: v_pk_mov_b32 v[4:5], s[0:1], s[0:1] op_sel:[0,1] ; GFX90A-NEXT: v_pk_mov_b32 v[4:5], s[0:1], s[0:1] op_sel:[0,1]
; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc ; GFX90A-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-NEXT: buffer_wbinvl1_vol ; GFX90A-NEXT: buffer_wbinvl1_vol
; GFX90A-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[2:3] ; GFX90A-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[2:3]
; GFX90A-NEXT: s_or_b64 s[2:3], vcc, s[2:3] ; GFX90A-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX90A-NEXT: v_pk_mov_b32 v[2:3], v[0:1], v[0:1] op_sel:[0,1] ; GFX90A-NEXT: v_pk_mov_b32 v[2:3], v[0:1], v[0:1] op_sel:[0,1]
; GFX90A-NEXT: s_andn2_b64 exec, exec, s[2:3] ; GFX90A-NEXT: s_andn2_b64 exec, exec, s[2:3]
; GFX90A-NEXT: s_cbranch_execnz BB43_1 ; GFX90A-NEXT: s_cbranch_execnz .LBB43_1
; GFX90A-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX90A-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX90A-NEXT: s_endpgm ; GFX90A-NEXT: s_endpgm
main_body: main_body:
%ret = atomicrmw fadd double* %ptr, double 4.0 syncscope("agent") seq_cst %ret = atomicrmw fadd double* %ptr, double 4.0 syncscope("agent") seq_cst
ret void ret void
} }
define amdgpu_kernel void @flat_atomic_fmin_f64_noret(double* %ptr, double %data) { define amdgpu_kernel void @flat_atomic_fmin_f64_noret(double* %ptr, double %data) {
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define amdgpu_kernel void @local_atomic_fadd_f64_noret_pat_flush_safe(double addrspace(3)* %ptr) #4 { define amdgpu_kernel void @local_atomic_fadd_f64_noret_pat_flush_safe(double addrspace(3)* %ptr) #4 {
; GFX90A-LABEL: local_atomic_fadd_f64_noret_pat_flush_safe: ; GFX90A-LABEL: local_atomic_fadd_f64_noret_pat_flush_safe:
; GFX90A: ; %bb.0: ; %main_body ; GFX90A: ; %bb.0: ; %main_body
; GFX90A-NEXT: s_load_dword s2, s[0:1], 0x24 ; GFX90A-NEXT: s_load_dword s2, s[0:1], 0x24
; GFX90A-NEXT: s_mov_b64 s[0:1], 0 ; GFX90A-NEXT: s_mov_b64 s[0:1], 0
; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: v_mov_b32_e32 v0, s2 ; GFX90A-NEXT: v_mov_b32_e32 v0, s2
; GFX90A-NEXT: ds_read_b64 v[0:1], v0 ; GFX90A-NEXT: ds_read_b64 v[0:1], v0
; GFX90A-NEXT: BB52_1: ; %atomicrmw.start ; GFX90A-NEXT: .LBB52_1: ; %atomicrmw.start
; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: v_add_f64 v[2:3], v[0:1], 4.0 ; GFX90A-NEXT: v_add_f64 v[2:3], v[0:1], 4.0
; GFX90A-NEXT: v_mov_b32_e32 v4, s2 ; GFX90A-NEXT: v_mov_b32_e32 v4, s2
; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: ds_cmpst_rtn_b64 v[2:3], v4, v[0:1], v[2:3] ; GFX90A-NEXT: ds_cmpst_rtn_b64 v[2:3], v4, v[0:1], v[2:3]
; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[0:1] ; GFX90A-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[0:1]
; GFX90A-NEXT: s_or_b64 s[0:1], vcc, s[0:1] ; GFX90A-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[2:3] op_sel:[0,1] ; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[2:3] op_sel:[0,1]
; GFX90A-NEXT: s_andn2_b64 exec, exec, s[0:1] ; GFX90A-NEXT: s_andn2_b64 exec, exec, s[0:1]
; GFX90A-NEXT: s_cbranch_execnz BB52_1 ; GFX90A-NEXT: s_cbranch_execnz .LBB52_1
; GFX90A-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX90A-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX90A-NEXT: s_endpgm ; GFX90A-NEXT: s_endpgm
main_body: main_body:
%ret = atomicrmw fadd double addrspace(3)* %ptr, double 4.0 seq_cst %ret = atomicrmw fadd double addrspace(3)* %ptr, double 4.0 seq_cst
ret void ret void
} }
define double @local_atomic_fadd_f64_rtn_pat(double addrspace(3)* %ptr, double %data) #1 { define double @local_atomic_fadd_f64_rtn_pat(double addrspace(3)* %ptr, double %data) #1 {
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llvm/test/CodeGen/AMDGPU/global-atomics-fp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX900 %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX900 %s
; RUN: llc -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX908 %s ; RUN: llc -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX908 %s
; RUN: llc -march=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX90A %s ; RUN: llc -march=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX90A %s
; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10 %s ; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10 %s
define amdgpu_kernel void @global_atomic_fadd_ret_f32(float addrspace(1)* %ptr) #0 { define amdgpu_kernel void @global_atomic_fadd_ret_f32(float addrspace(1)* %ptr) #0 {
; GFX900-LABEL: global_atomic_fadd_ret_f32: ; GFX900-LABEL: global_atomic_fadd_ret_f32:
; GFX900: ; %bb.0: ; GFX900: ; %bb.0:
; GFX900-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX900-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX900-NEXT: s_mov_b64 s[2:3], 0 ; GFX900-NEXT: s_mov_b64 s[2:3], 0
; GFX900-NEXT: v_mov_b32_e32 v0, 0 ; GFX900-NEXT: v_mov_b32_e32 v0, 0
; GFX900-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX900-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX900-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-NEXT: v_mov_b32_e32 v1, s4 ; GFX900-NEXT: v_mov_b32_e32 v1, s4
; GFX900-NEXT: BB0_1: ; %atomicrmw.start ; GFX900-NEXT: .LBB0_1: ; %atomicrmw.start
; GFX900-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX900-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX900-NEXT: v_mov_b32_e32 v2, v1 ; GFX900-NEXT: v_mov_b32_e32 v2, v1
; GFX900-NEXT: v_add_f32_e32 v1, 4.0, v2 ; GFX900-NEXT: v_add_f32_e32 v1, 4.0, v2
; GFX900-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX900-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[0:1] glc ; GFX900-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[0:1] glc
; GFX900-NEXT: s_waitcnt vmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: buffer_wbinvl1_vol ; GFX900-NEXT: buffer_wbinvl1_vol
; GFX900-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 ; GFX900-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
; GFX900-NEXT: s_or_b64 s[2:3], vcc, s[2:3] ; GFX900-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX900-NEXT: s_andn2_b64 exec, exec, s[2:3] ; GFX900-NEXT: s_andn2_b64 exec, exec, s[2:3]
; GFX900-NEXT: s_cbranch_execnz BB0_1 ; GFX900-NEXT: s_cbranch_execnz .LBB0_1
; GFX900-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX900-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX900-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX900-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX900-NEXT: global_store_dword v[0:1], v1, off ; GFX900-NEXT: global_store_dword v[0:1], v1, off
; GFX900-NEXT: s_endpgm ; GFX900-NEXT: s_endpgm
; ;
; GFX908-LABEL: global_atomic_fadd_ret_f32: ; GFX908-LABEL: global_atomic_fadd_ret_f32:
; GFX908: ; %bb.0: ; GFX908: ; %bb.0:
; GFX908-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX908-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX908-NEXT: s_mov_b64 s[2:3], 0 ; GFX908-NEXT: s_mov_b64 s[2:3], 0
; GFX908-NEXT: v_mov_b32_e32 v0, 0 ; GFX908-NEXT: v_mov_b32_e32 v0, 0
; GFX908-NEXT: s_waitcnt lgkmcnt(0) ; GFX908-NEXT: s_waitcnt lgkmcnt(0)
; GFX908-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX908-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX908-NEXT: s_waitcnt lgkmcnt(0) ; GFX908-NEXT: s_waitcnt lgkmcnt(0)
; GFX908-NEXT: v_mov_b32_e32 v1, s4 ; GFX908-NEXT: v_mov_b32_e32 v1, s4
; GFX908-NEXT: BB0_1: ; %atomicrmw.start ; GFX908-NEXT: .LBB0_1: ; %atomicrmw.start
; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX908-NEXT: v_mov_b32_e32 v2, v1 ; GFX908-NEXT: v_mov_b32_e32 v2, v1
; GFX908-NEXT: v_add_f32_e32 v1, 4.0, v2 ; GFX908-NEXT: v_add_f32_e32 v1, 4.0, v2
; GFX908-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX908-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX908-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[0:1] glc ; GFX908-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[0:1] glc
; GFX908-NEXT: s_waitcnt vmcnt(0) ; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: buffer_wbinvl1_vol ; GFX908-NEXT: buffer_wbinvl1_vol
; GFX908-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 ; GFX908-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
; GFX908-NEXT: s_or_b64 s[2:3], vcc, s[2:3] ; GFX908-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX908-NEXT: s_andn2_b64 exec, exec, s[2:3] ; GFX908-NEXT: s_andn2_b64 exec, exec, s[2:3]
; GFX908-NEXT: s_cbranch_execnz BB0_1 ; GFX908-NEXT: s_cbranch_execnz .LBB0_1
; GFX908-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX908-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX908-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX908-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX908-NEXT: global_store_dword v[0:1], v1, off ; GFX908-NEXT: global_store_dword v[0:1], v1, off
; GFX908-NEXT: s_endpgm ; GFX908-NEXT: s_endpgm
; ;
; GFX90A-LABEL: global_atomic_fadd_ret_f32: ; GFX90A-LABEL: global_atomic_fadd_ret_f32:
; GFX90A: ; %bb.0: ; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX90A-NEXT: s_mov_b64 s[2:3], 0 ; GFX90A-NEXT: s_mov_b64 s[2:3], 0
; GFX90A-NEXT: v_mov_b32_e32 v0, 0 ; GFX90A-NEXT: v_mov_b32_e32 v0, 0
; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX90A-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: v_mov_b32_e32 v1, s4 ; GFX90A-NEXT: v_mov_b32_e32 v1, s4
; GFX90A-NEXT: BB0_1: ; %atomicrmw.start ; GFX90A-NEXT: .LBB0_1: ; %atomicrmw.start
; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX90A-NEXT: v_mov_b32_e32 v3, v1 ; GFX90A-NEXT: v_mov_b32_e32 v3, v1
; GFX90A-NEXT: v_add_f32_e32 v2, 4.0, v3 ; GFX90A-NEXT: v_add_f32_e32 v2, 4.0, v3
; GFX90A-NEXT: buffer_wbl2 ; GFX90A-NEXT: buffer_wbl2
; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-NEXT: global_atomic_cmpswap v1, v0, v[2:3], s[0:1] glc ; GFX90A-NEXT: global_atomic_cmpswap v1, v0, v[2:3], s[0:1] glc
; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: buffer_invl2 ; GFX90A-NEXT: buffer_invl2
; GFX90A-NEXT: buffer_wbinvl1_vol ; GFX90A-NEXT: buffer_wbinvl1_vol
; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3 ; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
; GFX90A-NEXT: s_or_b64 s[2:3], vcc, s[2:3] ; GFX90A-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX90A-NEXT: s_andn2_b64 exec, exec, s[2:3] ; GFX90A-NEXT: s_andn2_b64 exec, exec, s[2:3]
; GFX90A-NEXT: s_cbranch_execnz BB0_1 ; GFX90A-NEXT: s_cbranch_execnz .LBB0_1
; GFX90A-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX90A-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX90A-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX90A-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX90A-NEXT: global_store_dword v[0:1], v1, off ; GFX90A-NEXT: global_store_dword v[0:1], v1, off
; GFX90A-NEXT: s_endpgm ; GFX90A-NEXT: s_endpgm
; ;
; GFX10-LABEL: global_atomic_fadd_ret_f32: ; GFX10-LABEL: global_atomic_fadd_ret_f32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v1, s2 ; GFX10-NEXT: v_mov_b32_e32 v1, s2
; GFX10-NEXT: s_mov_b32 s2, 0 ; GFX10-NEXT: s_mov_b32 s2, 0
; GFX10-NEXT: BB0_1: ; %atomicrmw.start ; GFX10-NEXT: .LBB0_1: ; %atomicrmw.start
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v2, v1 ; GFX10-NEXT: v_mov_b32_e32 v2, v1
; GFX10-NEXT: v_add_f32_e32 v1, 4.0, v2 ; GFX10-NEXT: v_add_f32_e32 v1, 4.0, v2
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[0:1] glc ; GFX10-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[0:1] glc
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_gl0_inv ; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv ; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
; GFX10-NEXT: s_or_b32 s2, vcc_lo, s2 ; GFX10-NEXT: s_or_b32 s2, vcc_lo, s2
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s2 ; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s2
; GFX10-NEXT: s_cbranch_execnz BB0_1 ; GFX10-NEXT: s_cbranch_execnz .LBB0_1
; GFX10-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX10-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s2 ; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX10-NEXT: global_store_dword v[0:1], v1, off ; GFX10-NEXT: global_store_dword v[0:1], v1, off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%result = atomicrmw fadd float addrspace(1)* %ptr, float 4.0 seq_cst %result = atomicrmw fadd float addrspace(1)* %ptr, float 4.0 seq_cst
store float %result, float addrspace(1)* undef store float %result, float addrspace(1)* undef
ret void ret void
} }
define amdgpu_kernel void @global_atomic_fadd_ret_f32_ieee(float addrspace(1)* %ptr) #2 { define amdgpu_kernel void @global_atomic_fadd_ret_f32_ieee(float addrspace(1)* %ptr) #2 {
; GFX900-LABEL: global_atomic_fadd_ret_f32_ieee: ; GFX900-LABEL: global_atomic_fadd_ret_f32_ieee:
; GFX900: ; %bb.0: ; GFX900: ; %bb.0:
; GFX900-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX900-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX900-NEXT: s_mov_b64 s[2:3], 0 ; GFX900-NEXT: s_mov_b64 s[2:3], 0
; GFX900-NEXT: v_mov_b32_e32 v0, 0 ; GFX900-NEXT: v_mov_b32_e32 v0, 0
; GFX900-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX900-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX900-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-NEXT: v_mov_b32_e32 v1, s4 ; GFX900-NEXT: v_mov_b32_e32 v1, s4
; GFX900-NEXT: BB1_1: ; %atomicrmw.start ; GFX900-NEXT: .LBB1_1: ; %atomicrmw.start
; GFX900-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX900-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX900-NEXT: v_mov_b32_e32 v2, v1 ; GFX900-NEXT: v_mov_b32_e32 v2, v1
; GFX900-NEXT: v_add_f32_e32 v1, 4.0, v2 ; GFX900-NEXT: v_add_f32_e32 v1, 4.0, v2
; GFX900-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX900-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[0:1] glc ; GFX900-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[0:1] glc
; GFX900-NEXT: s_waitcnt vmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: buffer_wbinvl1_vol ; GFX900-NEXT: buffer_wbinvl1_vol
; GFX900-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 ; GFX900-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
; GFX900-NEXT: s_or_b64 s[2:3], vcc, s[2:3] ; GFX900-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX900-NEXT: s_andn2_b64 exec, exec, s[2:3] ; GFX900-NEXT: s_andn2_b64 exec, exec, s[2:3]
; GFX900-NEXT: s_cbranch_execnz BB1_1 ; GFX900-NEXT: s_cbranch_execnz .LBB1_1
; GFX900-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX900-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX900-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX900-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX900-NEXT: global_store_dword v[0:1], v1, off ; GFX900-NEXT: global_store_dword v[0:1], v1, off
; GFX900-NEXT: s_endpgm ; GFX900-NEXT: s_endpgm
; ;
; GFX908-LABEL: global_atomic_fadd_ret_f32_ieee: ; GFX908-LABEL: global_atomic_fadd_ret_f32_ieee:
; GFX908: ; %bb.0: ; GFX908: ; %bb.0:
; GFX908-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX908-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX908-NEXT: s_mov_b64 s[2:3], 0 ; GFX908-NEXT: s_mov_b64 s[2:3], 0
; GFX908-NEXT: v_mov_b32_e32 v0, 0 ; GFX908-NEXT: v_mov_b32_e32 v0, 0
; GFX908-NEXT: s_waitcnt lgkmcnt(0) ; GFX908-NEXT: s_waitcnt lgkmcnt(0)
; GFX908-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX908-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX908-NEXT: s_waitcnt lgkmcnt(0) ; GFX908-NEXT: s_waitcnt lgkmcnt(0)
; GFX908-NEXT: v_mov_b32_e32 v1, s4 ; GFX908-NEXT: v_mov_b32_e32 v1, s4
; GFX908-NEXT: BB1_1: ; %atomicrmw.start ; GFX908-NEXT: .LBB1_1: ; %atomicrmw.start
; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX908-NEXT: v_mov_b32_e32 v2, v1 ; GFX908-NEXT: v_mov_b32_e32 v2, v1
; GFX908-NEXT: v_add_f32_e32 v1, 4.0, v2 ; GFX908-NEXT: v_add_f32_e32 v1, 4.0, v2
; GFX908-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX908-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX908-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[0:1] glc ; GFX908-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[0:1] glc
; GFX908-NEXT: s_waitcnt vmcnt(0) ; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: buffer_wbinvl1_vol ; GFX908-NEXT: buffer_wbinvl1_vol
; GFX908-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 ; GFX908-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
; GFX908-NEXT: s_or_b64 s[2:3], vcc, s[2:3] ; GFX908-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX908-NEXT: s_andn2_b64 exec, exec, s[2:3] ; GFX908-NEXT: s_andn2_b64 exec, exec, s[2:3]
; GFX908-NEXT: s_cbranch_execnz BB1_1 ; GFX908-NEXT: s_cbranch_execnz .LBB1_1
; GFX908-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX908-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX908-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX908-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX908-NEXT: global_store_dword v[0:1], v1, off ; GFX908-NEXT: global_store_dword v[0:1], v1, off
; GFX908-NEXT: s_endpgm ; GFX908-NEXT: s_endpgm
; ;
; GFX90A-LABEL: global_atomic_fadd_ret_f32_ieee: ; GFX90A-LABEL: global_atomic_fadd_ret_f32_ieee:
; GFX90A: ; %bb.0: ; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v1, s2 ; GFX10-NEXT: v_mov_b32_e32 v1, s2
; GFX10-NEXT: s_mov_b32 s2, 0 ; GFX10-NEXT: s_mov_b32 s2, 0
; GFX10-NEXT: BB1_1: ; %atomicrmw.start ; GFX10-NEXT: .LBB1_1: ; %atomicrmw.start
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v2, v1 ; GFX10-NEXT: v_mov_b32_e32 v2, v1
; GFX10-NEXT: v_add_f32_e32 v1, 4.0, v2 ; GFX10-NEXT: v_add_f32_e32 v1, 4.0, v2
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[0:1] glc ; GFX10-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[0:1] glc
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_gl0_inv ; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv ; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
; GFX10-NEXT: s_or_b32 s2, vcc_lo, s2 ; GFX10-NEXT: s_or_b32 s2, vcc_lo, s2
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s2 ; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s2
; GFX10-NEXT: s_cbranch_execnz BB1_1 ; GFX10-NEXT: s_cbranch_execnz .LBB1_1
; GFX10-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX10-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s2 ; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX10-NEXT: global_store_dword v[0:1], v1, off ; GFX10-NEXT: global_store_dword v[0:1], v1, off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%result = atomicrmw fadd float addrspace(1)* %ptr, float 4.0 syncscope("agent") seq_cst %result = atomicrmw fadd float addrspace(1)* %ptr, float 4.0 syncscope("agent") seq_cst
store float %result, float addrspace(1)* undef store float %result, float addrspace(1)* undef
ret void ret void
} }
define amdgpu_kernel void @global_atomic_fadd_noret_f32(float addrspace(1)* %ptr) #0 { define amdgpu_kernel void @global_atomic_fadd_noret_f32(float addrspace(1)* %ptr) #0 {
; GFX900-LABEL: global_atomic_fadd_noret_f32: ; GFX900-LABEL: global_atomic_fadd_noret_f32:
; GFX900: ; %bb.0: ; GFX900: ; %bb.0:
; GFX900-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX900-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX900-NEXT: s_mov_b64 s[2:3], 0 ; GFX900-NEXT: s_mov_b64 s[2:3], 0
; GFX900-NEXT: v_mov_b32_e32 v2, 0 ; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX900-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX900-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-NEXT: v_mov_b32_e32 v1, s4 ; GFX900-NEXT: v_mov_b32_e32 v1, s4
; GFX900-NEXT: BB2_1: ; %atomicrmw.start ; GFX900-NEXT: .LBB2_1: ; %atomicrmw.start
; GFX900-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX900-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX900-NEXT: v_add_f32_e32 v0, 4.0, v1 ; GFX900-NEXT: v_add_f32_e32 v0, 4.0, v1
; GFX900-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX900-NEXT: global_atomic_cmpswap v0, v2, v[0:1], s[0:1] glc ; GFX900-NEXT: global_atomic_cmpswap v0, v2, v[0:1], s[0:1] glc
; GFX900-NEXT: s_waitcnt vmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: buffer_wbinvl1_vol ; GFX900-NEXT: buffer_wbinvl1_vol
; GFX900-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1 ; GFX900-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
; GFX900-NEXT: s_or_b64 s[2:3], vcc, s[2:3] ; GFX900-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX900-NEXT: v_mov_b32_e32 v1, v0 ; GFX900-NEXT: v_mov_b32_e32 v1, v0
; GFX900-NEXT: s_andn2_b64 exec, exec, s[2:3] ; GFX900-NEXT: s_andn2_b64 exec, exec, s[2:3]
; GFX900-NEXT: s_cbranch_execnz BB2_1 ; GFX900-NEXT: s_cbranch_execnz .LBB2_1
; GFX900-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX900-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX900-NEXT: s_endpgm ; GFX900-NEXT: s_endpgm
; ;
; GFX908-LABEL: global_atomic_fadd_noret_f32: ; GFX908-LABEL: global_atomic_fadd_noret_f32:
; GFX908: ; %bb.0: ; GFX908: ; %bb.0:
; GFX908-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX908-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX908-NEXT: v_mov_b32_e32 v0, 0 ; GFX908-NEXT: v_mov_b32_e32 v0, 0
; GFX908-NEXT: v_mov_b32_e32 v1, 4.0 ; GFX908-NEXT: v_mov_b32_e32 v1, 4.0
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; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v1, s2 ; GFX10-NEXT: v_mov_b32_e32 v1, s2
; GFX10-NEXT: s_mov_b32 s2, 0 ; GFX10-NEXT: s_mov_b32 s2, 0
; GFX10-NEXT: BB2_1: ; %atomicrmw.start ; GFX10-NEXT: .LBB2_1: ; %atomicrmw.start
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_add_f32_e32 v0, 4.0, v1 ; GFX10-NEXT: v_add_f32_e32 v0, 4.0, v1
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v0, v2, v[0:1], s[0:1] glc ; GFX10-NEXT: global_atomic_cmpswap v0, v2, v[0:1], s[0:1] glc
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_gl0_inv ; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv ; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v1 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v1
; GFX10-NEXT: v_mov_b32_e32 v1, v0 ; GFX10-NEXT: v_mov_b32_e32 v1, v0
; GFX10-NEXT: s_or_b32 s2, vcc_lo, s2 ; GFX10-NEXT: s_or_b32 s2, vcc_lo, s2
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s2 ; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s2
; GFX10-NEXT: s_cbranch_execnz BB2_1 ; GFX10-NEXT: s_cbranch_execnz .LBB2_1
; GFX10-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX10-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%result = atomicrmw fadd float addrspace(1)* %ptr, float 4.0 syncscope("agent") seq_cst %result = atomicrmw fadd float addrspace(1)* %ptr, float 4.0 syncscope("agent") seq_cst
ret void ret void
} }
define amdgpu_kernel void @global_atomic_fadd_noret_f32_ieee(float addrspace(1)* %ptr) #2 { define amdgpu_kernel void @global_atomic_fadd_noret_f32_ieee(float addrspace(1)* %ptr) #2 {
; GFX900-LABEL: global_atomic_fadd_noret_f32_ieee: ; GFX900-LABEL: global_atomic_fadd_noret_f32_ieee:
; GFX900: ; %bb.0: ; GFX900: ; %bb.0:
; GFX900-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX900-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX900-NEXT: s_mov_b64 s[2:3], 0 ; GFX900-NEXT: s_mov_b64 s[2:3], 0
; GFX900-NEXT: v_mov_b32_e32 v2, 0 ; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX900-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX900-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-NEXT: v_mov_b32_e32 v1, s4 ; GFX900-NEXT: v_mov_b32_e32 v1, s4
; GFX900-NEXT: BB3_1: ; %atomicrmw.start ; GFX900-NEXT: .LBB3_1: ; %atomicrmw.start
; GFX900-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX900-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX900-NEXT: v_add_f32_e32 v0, 4.0, v1 ; GFX900-NEXT: v_add_f32_e32 v0, 4.0, v1
; GFX900-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX900-NEXT: global_atomic_cmpswap v0, v2, v[0:1], s[0:1] glc ; GFX900-NEXT: global_atomic_cmpswap v0, v2, v[0:1], s[0:1] glc
; GFX900-NEXT: s_waitcnt vmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: buffer_wbinvl1_vol ; GFX900-NEXT: buffer_wbinvl1_vol
; GFX900-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1 ; GFX900-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
; GFX900-NEXT: s_or_b64 s[2:3], vcc, s[2:3] ; GFX900-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX900-NEXT: v_mov_b32_e32 v1, v0 ; GFX900-NEXT: v_mov_b32_e32 v1, v0
; GFX900-NEXT: s_andn2_b64 exec, exec, s[2:3] ; GFX900-NEXT: s_andn2_b64 exec, exec, s[2:3]
; GFX900-NEXT: s_cbranch_execnz BB3_1 ; GFX900-NEXT: s_cbranch_execnz .LBB3_1
; GFX900-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX900-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX900-NEXT: s_endpgm ; GFX900-NEXT: s_endpgm
; ;
; GFX908-LABEL: global_atomic_fadd_noret_f32_ieee: ; GFX908-LABEL: global_atomic_fadd_noret_f32_ieee:
; GFX908: ; %bb.0: ; GFX908: ; %bb.0:
; GFX908-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX908-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX908-NEXT: v_mov_b32_e32 v0, 0 ; GFX908-NEXT: v_mov_b32_e32 v0, 0
; GFX908-NEXT: v_mov_b32_e32 v1, 4.0 ; GFX908-NEXT: v_mov_b32_e32 v1, 4.0
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; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v1, s2 ; GFX10-NEXT: v_mov_b32_e32 v1, s2
; GFX10-NEXT: s_mov_b32 s2, 0 ; GFX10-NEXT: s_mov_b32 s2, 0
; GFX10-NEXT: BB3_1: ; %atomicrmw.start ; GFX10-NEXT: .LBB3_1: ; %atomicrmw.start
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_add_f32_e32 v0, 4.0, v1 ; GFX10-NEXT: v_add_f32_e32 v0, 4.0, v1
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v0, v2, v[0:1], s[0:1] glc ; GFX10-NEXT: global_atomic_cmpswap v0, v2, v[0:1], s[0:1] glc
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_gl0_inv ; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv ; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v1 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v1
; GFX10-NEXT: v_mov_b32_e32 v1, v0 ; GFX10-NEXT: v_mov_b32_e32 v1, v0
; GFX10-NEXT: s_or_b32 s2, vcc_lo, s2 ; GFX10-NEXT: s_or_b32 s2, vcc_lo, s2
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s2 ; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s2
; GFX10-NEXT: s_cbranch_execnz BB3_1 ; GFX10-NEXT: s_cbranch_execnz .LBB3_1
; GFX10-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX10-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%result = atomicrmw fadd float addrspace(1)* %ptr, float 4.0 syncscope("agent") seq_cst %result = atomicrmw fadd float addrspace(1)* %ptr, float 4.0 syncscope("agent") seq_cst
ret void ret void
} }
define amdgpu_kernel void @global_atomic_fadd_ret_f32_agent(float addrspace(1)* %ptr) #0 { define amdgpu_kernel void @global_atomic_fadd_ret_f32_agent(float addrspace(1)* %ptr) #0 {
; GFX900-LABEL: global_atomic_fadd_ret_f32_agent: ; GFX900-LABEL: global_atomic_fadd_ret_f32_agent:
; GFX900: ; %bb.0: ; GFX900: ; %bb.0:
; GFX900-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX900-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX900-NEXT: s_mov_b64 s[2:3], 0 ; GFX900-NEXT: s_mov_b64 s[2:3], 0
; GFX900-NEXT: v_mov_b32_e32 v0, 0 ; GFX900-NEXT: v_mov_b32_e32 v0, 0
; GFX900-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX900-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX900-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-NEXT: v_mov_b32_e32 v1, s4 ; GFX900-NEXT: v_mov_b32_e32 v1, s4
; GFX900-NEXT: BB4_1: ; %atomicrmw.start ; GFX900-NEXT: .LBB4_1: ; %atomicrmw.start
; GFX900-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX900-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX900-NEXT: v_mov_b32_e32 v2, v1 ; GFX900-NEXT: v_mov_b32_e32 v2, v1
; GFX900-NEXT: v_add_f32_e32 v1, 4.0, v2 ; GFX900-NEXT: v_add_f32_e32 v1, 4.0, v2
; GFX900-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX900-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[0:1] glc ; GFX900-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[0:1] glc
; GFX900-NEXT: s_waitcnt vmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: buffer_wbinvl1_vol ; GFX900-NEXT: buffer_wbinvl1_vol
; GFX900-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 ; GFX900-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
; GFX900-NEXT: s_or_b64 s[2:3], vcc, s[2:3] ; GFX900-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX900-NEXT: s_andn2_b64 exec, exec, s[2:3] ; GFX900-NEXT: s_andn2_b64 exec, exec, s[2:3]
; GFX900-NEXT: s_cbranch_execnz BB4_1 ; GFX900-NEXT: s_cbranch_execnz .LBB4_1
; GFX900-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX900-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX900-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX900-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX900-NEXT: global_store_dword v[0:1], v1, off ; GFX900-NEXT: global_store_dword v[0:1], v1, off
; GFX900-NEXT: s_endpgm ; GFX900-NEXT: s_endpgm
; ;
; GFX908-LABEL: global_atomic_fadd_ret_f32_agent: ; GFX908-LABEL: global_atomic_fadd_ret_f32_agent:
; GFX908: ; %bb.0: ; GFX908: ; %bb.0:
; GFX908-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX908-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX908-NEXT: s_mov_b64 s[2:3], 0 ; GFX908-NEXT: s_mov_b64 s[2:3], 0
; GFX908-NEXT: v_mov_b32_e32 v0, 0 ; GFX908-NEXT: v_mov_b32_e32 v0, 0
; GFX908-NEXT: s_waitcnt lgkmcnt(0) ; GFX908-NEXT: s_waitcnt lgkmcnt(0)
; GFX908-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX908-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX908-NEXT: s_waitcnt lgkmcnt(0) ; GFX908-NEXT: s_waitcnt lgkmcnt(0)
; GFX908-NEXT: v_mov_b32_e32 v1, s4 ; GFX908-NEXT: v_mov_b32_e32 v1, s4
; GFX908-NEXT: BB4_1: ; %atomicrmw.start ; GFX908-NEXT: .LBB4_1: ; %atomicrmw.start
; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX908-NEXT: v_mov_b32_e32 v2, v1 ; GFX908-NEXT: v_mov_b32_e32 v2, v1
; GFX908-NEXT: v_add_f32_e32 v1, 4.0, v2 ; GFX908-NEXT: v_add_f32_e32 v1, 4.0, v2
; GFX908-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX908-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX908-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[0:1] glc ; GFX908-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[0:1] glc
; GFX908-NEXT: s_waitcnt vmcnt(0) ; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: buffer_wbinvl1_vol ; GFX908-NEXT: buffer_wbinvl1_vol
; GFX908-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 ; GFX908-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
; GFX908-NEXT: s_or_b64 s[2:3], vcc, s[2:3] ; GFX908-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX908-NEXT: s_andn2_b64 exec, exec, s[2:3] ; GFX908-NEXT: s_andn2_b64 exec, exec, s[2:3]
; GFX908-NEXT: s_cbranch_execnz BB4_1 ; GFX908-NEXT: s_cbranch_execnz .LBB4_1
; GFX908-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX908-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX908-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX908-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX908-NEXT: global_store_dword v[0:1], v1, off ; GFX908-NEXT: global_store_dword v[0:1], v1, off
; GFX908-NEXT: s_endpgm ; GFX908-NEXT: s_endpgm
; ;
; GFX90A-LABEL: global_atomic_fadd_ret_f32_agent: ; GFX90A-LABEL: global_atomic_fadd_ret_f32_agent:
; GFX90A: ; %bb.0: ; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v1, s2 ; GFX10-NEXT: v_mov_b32_e32 v1, s2
; GFX10-NEXT: s_mov_b32 s2, 0 ; GFX10-NEXT: s_mov_b32 s2, 0
; GFX10-NEXT: BB4_1: ; %atomicrmw.start ; GFX10-NEXT: .LBB4_1: ; %atomicrmw.start
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v2, v1 ; GFX10-NEXT: v_mov_b32_e32 v2, v1
; GFX10-NEXT: v_add_f32_e32 v1, 4.0, v2 ; GFX10-NEXT: v_add_f32_e32 v1, 4.0, v2
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[0:1] glc ; GFX10-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[0:1] glc
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_gl0_inv ; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv ; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
; GFX10-NEXT: s_or_b32 s2, vcc_lo, s2 ; GFX10-NEXT: s_or_b32 s2, vcc_lo, s2
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s2 ; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s2
; GFX10-NEXT: s_cbranch_execnz BB4_1 ; GFX10-NEXT: s_cbranch_execnz .LBB4_1
; GFX10-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX10-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s2 ; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX10-NEXT: global_store_dword v[0:1], v1, off ; GFX10-NEXT: global_store_dword v[0:1], v1, off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%result = atomicrmw fadd float addrspace(1)* %ptr, float 4.0 syncscope("agent") seq_cst %result = atomicrmw fadd float addrspace(1)* %ptr, float 4.0 syncscope("agent") seq_cst
store float %result, float addrspace(1)* undef store float %result, float addrspace(1)* undef
ret void ret void
} }
define amdgpu_kernel void @global_atomic_fadd_ret_f32_system(float addrspace(1)* %ptr) #0 { define amdgpu_kernel void @global_atomic_fadd_ret_f32_system(float addrspace(1)* %ptr) #0 {
; GFX900-LABEL: global_atomic_fadd_ret_f32_system: ; GFX900-LABEL: global_atomic_fadd_ret_f32_system:
; GFX900: ; %bb.0: ; GFX900: ; %bb.0:
; GFX900-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX900-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX900-NEXT: s_mov_b64 s[2:3], 0 ; GFX900-NEXT: s_mov_b64 s[2:3], 0
; GFX900-NEXT: v_mov_b32_e32 v0, 0 ; GFX900-NEXT: v_mov_b32_e32 v0, 0
; GFX900-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX900-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX900-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-NEXT: v_mov_b32_e32 v1, s4 ; GFX900-NEXT: v_mov_b32_e32 v1, s4
; GFX900-NEXT: BB5_1: ; %atomicrmw.start ; GFX900-NEXT: .LBB5_1: ; %atomicrmw.start
; GFX900-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX900-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX900-NEXT: v_mov_b32_e32 v2, v1 ; GFX900-NEXT: v_mov_b32_e32 v2, v1
; GFX900-NEXT: v_add_f32_e32 v1, 4.0, v2 ; GFX900-NEXT: v_add_f32_e32 v1, 4.0, v2
; GFX900-NEXT: s_waitcnt vmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[0:1] glc ; GFX900-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[0:1] glc
; GFX900-NEXT: s_waitcnt vmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: buffer_wbinvl1_vol ; GFX900-NEXT: buffer_wbinvl1_vol
; GFX900-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 ; GFX900-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
; GFX900-NEXT: s_or_b64 s[2:3], vcc, s[2:3] ; GFX900-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX900-NEXT: s_andn2_b64 exec, exec, s[2:3] ; GFX900-NEXT: s_andn2_b64 exec, exec, s[2:3]
; GFX900-NEXT: s_cbranch_execnz BB5_1 ; GFX900-NEXT: s_cbranch_execnz .LBB5_1
; GFX900-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX900-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX900-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX900-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX900-NEXT: global_store_dword v[0:1], v1, off ; GFX900-NEXT: global_store_dword v[0:1], v1, off
; GFX900-NEXT: s_endpgm ; GFX900-NEXT: s_endpgm
; ;
; GFX908-LABEL: global_atomic_fadd_ret_f32_system: ; GFX908-LABEL: global_atomic_fadd_ret_f32_system:
; GFX908: ; %bb.0: ; GFX908: ; %bb.0:
; GFX908-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX908-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX908-NEXT: s_mov_b64 s[2:3], 0 ; GFX908-NEXT: s_mov_b64 s[2:3], 0
; GFX908-NEXT: v_mov_b32_e32 v0, 0 ; GFX908-NEXT: v_mov_b32_e32 v0, 0
; GFX908-NEXT: s_waitcnt lgkmcnt(0) ; GFX908-NEXT: s_waitcnt lgkmcnt(0)
; GFX908-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX908-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX908-NEXT: s_waitcnt lgkmcnt(0) ; GFX908-NEXT: s_waitcnt lgkmcnt(0)
; GFX908-NEXT: v_mov_b32_e32 v1, s4 ; GFX908-NEXT: v_mov_b32_e32 v1, s4
; GFX908-NEXT: BB5_1: ; %atomicrmw.start ; GFX908-NEXT: .LBB5_1: ; %atomicrmw.start
; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX908-NEXT: v_mov_b32_e32 v2, v1 ; GFX908-NEXT: v_mov_b32_e32 v2, v1
; GFX908-NEXT: v_add_f32_e32 v1, 4.0, v2 ; GFX908-NEXT: v_add_f32_e32 v1, 4.0, v2
; GFX908-NEXT: s_waitcnt vmcnt(0) ; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[0:1] glc ; GFX908-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[0:1] glc
; GFX908-NEXT: s_waitcnt vmcnt(0) ; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: buffer_wbinvl1_vol ; GFX908-NEXT: buffer_wbinvl1_vol
; GFX908-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 ; GFX908-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
; GFX908-NEXT: s_or_b64 s[2:3], vcc, s[2:3] ; GFX908-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX908-NEXT: s_andn2_b64 exec, exec, s[2:3] ; GFX908-NEXT: s_andn2_b64 exec, exec, s[2:3]
; GFX908-NEXT: s_cbranch_execnz BB5_1 ; GFX908-NEXT: s_cbranch_execnz .LBB5_1
; GFX908-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX908-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX908-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX908-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX908-NEXT: global_store_dword v[0:1], v1, off ; GFX908-NEXT: global_store_dword v[0:1], v1, off
; GFX908-NEXT: s_endpgm ; GFX908-NEXT: s_endpgm
; ;
; GFX90A-LABEL: global_atomic_fadd_ret_f32_system: ; GFX90A-LABEL: global_atomic_fadd_ret_f32_system:
; GFX90A: ; %bb.0: ; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX90A-NEXT: s_mov_b64 s[2:3], 0 ; GFX90A-NEXT: s_mov_b64 s[2:3], 0
; GFX90A-NEXT: v_mov_b32_e32 v0, 0 ; GFX90A-NEXT: v_mov_b32_e32 v0, 0
; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX90A-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: v_mov_b32_e32 v1, s4 ; GFX90A-NEXT: v_mov_b32_e32 v1, s4
; GFX90A-NEXT: BB5_1: ; %atomicrmw.start ; GFX90A-NEXT: .LBB5_1: ; %atomicrmw.start
; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX90A-NEXT: v_mov_b32_e32 v3, v1 ; GFX90A-NEXT: v_mov_b32_e32 v3, v1
; GFX90A-NEXT: v_add_f32_e32 v2, 4.0, v3 ; GFX90A-NEXT: v_add_f32_e32 v2, 4.0, v3
; GFX90A-NEXT: buffer_wbl2 ; GFX90A-NEXT: buffer_wbl2
; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: global_atomic_cmpswap v1, v0, v[2:3], s[0:1] glc ; GFX90A-NEXT: global_atomic_cmpswap v1, v0, v[2:3], s[0:1] glc
; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: buffer_invl2 ; GFX90A-NEXT: buffer_invl2
; GFX90A-NEXT: buffer_wbinvl1_vol ; GFX90A-NEXT: buffer_wbinvl1_vol
; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3 ; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
; GFX90A-NEXT: s_or_b64 s[2:3], vcc, s[2:3] ; GFX90A-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX90A-NEXT: s_andn2_b64 exec, exec, s[2:3] ; GFX90A-NEXT: s_andn2_b64 exec, exec, s[2:3]
; GFX90A-NEXT: s_cbranch_execnz BB5_1 ; GFX90A-NEXT: s_cbranch_execnz .LBB5_1
; GFX90A-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX90A-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX90A-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX90A-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX90A-NEXT: global_store_dword v[0:1], v1, off ; GFX90A-NEXT: global_store_dword v[0:1], v1, off
; GFX90A-NEXT: s_endpgm ; GFX90A-NEXT: s_endpgm
; ;
; GFX10-LABEL: global_atomic_fadd_ret_f32_system: ; GFX10-LABEL: global_atomic_fadd_ret_f32_system:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v1, s2 ; GFX10-NEXT: v_mov_b32_e32 v1, s2
; GFX10-NEXT: s_mov_b32 s2, 0 ; GFX10-NEXT: s_mov_b32 s2, 0
; GFX10-NEXT: BB5_1: ; %atomicrmw.start ; GFX10-NEXT: .LBB5_1: ; %atomicrmw.start
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v2, v1 ; GFX10-NEXT: v_mov_b32_e32 v2, v1
; GFX10-NEXT: v_add_f32_e32 v1, 4.0, v2 ; GFX10-NEXT: v_add_f32_e32 v1, 4.0, v2
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[0:1] glc ; GFX10-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[0:1] glc
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_gl0_inv ; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv ; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
; GFX10-NEXT: s_or_b32 s2, vcc_lo, s2 ; GFX10-NEXT: s_or_b32 s2, vcc_lo, s2
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s2 ; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s2
; GFX10-NEXT: s_cbranch_execnz BB5_1 ; GFX10-NEXT: s_cbranch_execnz .LBB5_1
; GFX10-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX10-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s2 ; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX10-NEXT: global_store_dword v[0:1], v1, off ; GFX10-NEXT: global_store_dword v[0:1], v1, off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%result = atomicrmw fadd float addrspace(1)* %ptr, float 4.0 syncscope("one-as") seq_cst %result = atomicrmw fadd float addrspace(1)* %ptr, float 4.0 syncscope("one-as") seq_cst
store float %result, float addrspace(1)* undef store float %result, float addrspace(1)* undef
ret void ret void
} }
define amdgpu_kernel void @global_atomic_fadd_ret_f32_wrong_subtarget(float addrspace(1)* %ptr) #1 { define amdgpu_kernel void @global_atomic_fadd_ret_f32_wrong_subtarget(float addrspace(1)* %ptr) #1 {
; GCN-LABEL: global_atomic_fadd_ret_f32_wrong_subtarget: ; GCN-LABEL: global_atomic_fadd_ret_f32_wrong_subtarget:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GCN-NEXT: s_mov_b64 s[2:3], 0 ; GCN-NEXT: s_mov_b64 s[2:3], 0
; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_load_dword s4, s[0:1], 0x0 ; GCN-NEXT: s_load_dword s4, s[0:1], 0x0
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v1, s4 ; GCN-NEXT: v_mov_b32_e32 v1, s4
; GCN-NEXT: BB6_1: ; %atomicrmw.start ; GCN-NEXT: .LBB6_1: ; %atomicrmw.start
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: v_mov_b32_e32 v2, v1 ; GCN-NEXT: v_mov_b32_e32 v2, v1
; GCN-NEXT: v_add_f32_e32 v1, 4.0, v2 ; GCN-NEXT: v_add_f32_e32 v1, 4.0, v2
; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[0:1] glc ; GCN-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[0:1] glc
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_wbinvl1_vol ; GCN-NEXT: buffer_wbinvl1_vol
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
; GCN-NEXT: s_or_b64 s[2:3], vcc, s[2:3] ; GCN-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GCN-NEXT: s_andn2_b64 exec, exec, s[2:3] ; GCN-NEXT: s_andn2_b64 exec, exec, s[2:3]
; GCN-NEXT: s_cbranch_execnz BB6_1 ; GCN-NEXT: s_cbranch_execnz .LBB6_1
; GCN-NEXT: ; %bb.2: ; %atomicrmw.end ; GCN-NEXT: ; %bb.2: ; %atomicrmw.end
; GCN-NEXT: s_or_b64 exec, exec, s[2:3] ; GCN-NEXT: s_or_b64 exec, exec, s[2:3]
; GCN-NEXT: global_store_dword v[0:1], v1, off ; GCN-NEXT: global_store_dword v[0:1], v1, off
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
%result = atomicrmw fadd float addrspace(1)* %ptr, float 4.0 syncscope("agent") seq_cst %result = atomicrmw fadd float addrspace(1)* %ptr, float 4.0 syncscope("agent") seq_cst
store float %result, float addrspace(1)* undef store float %result, float addrspace(1)* undef
ret void ret void
} }
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; GFX900: ; %bb.0: ; GFX900: ; %bb.0:
; GFX900-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX900-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX900-NEXT: s_mov_b64 s[2:3], 0 ; GFX900-NEXT: s_mov_b64 s[2:3], 0
; GFX900-NEXT: v_mov_b32_e32 v2, 0 ; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX900-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX900-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-NEXT: v_mov_b32_e32 v1, s4 ; GFX900-NEXT: v_mov_b32_e32 v1, s4
; GFX900-NEXT: BB8_1: ; %atomicrmw.start ; GFX900-NEXT: .LBB8_1: ; %atomicrmw.start
; GFX900-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX900-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX900-NEXT: v_add_f32_e32 v0, 4.0, v1 ; GFX900-NEXT: v_add_f32_e32 v0, 4.0, v1
; GFX900-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX900-NEXT: global_atomic_cmpswap v0, v2, v[0:1], s[0:1] glc ; GFX900-NEXT: global_atomic_cmpswap v0, v2, v[0:1], s[0:1] glc
; GFX900-NEXT: s_waitcnt vmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: buffer_wbinvl1_vol ; GFX900-NEXT: buffer_wbinvl1_vol
; GFX900-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1 ; GFX900-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
; GFX900-NEXT: s_or_b64 s[2:3], vcc, s[2:3] ; GFX900-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX900-NEXT: v_mov_b32_e32 v1, v0 ; GFX900-NEXT: v_mov_b32_e32 v1, v0
; GFX900-NEXT: s_andn2_b64 exec, exec, s[2:3] ; GFX900-NEXT: s_andn2_b64 exec, exec, s[2:3]
; GFX900-NEXT: s_cbranch_execnz BB8_1 ; GFX900-NEXT: s_cbranch_execnz .LBB8_1
; GFX900-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX900-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX900-NEXT: s_endpgm ; GFX900-NEXT: s_endpgm
; ;
; GFX908-LABEL: global_atomic_fadd_noret_f32_safe: ; GFX908-LABEL: global_atomic_fadd_noret_f32_safe:
; GFX908: ; %bb.0: ; GFX908: ; %bb.0:
; GFX908-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX908-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX908-NEXT: s_mov_b64 s[2:3], 0 ; GFX908-NEXT: s_mov_b64 s[2:3], 0
; GFX908-NEXT: v_mov_b32_e32 v2, 0 ; GFX908-NEXT: v_mov_b32_e32 v2, 0
; GFX908-NEXT: s_waitcnt lgkmcnt(0) ; GFX908-NEXT: s_waitcnt lgkmcnt(0)
; GFX908-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX908-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX908-NEXT: s_waitcnt lgkmcnt(0) ; GFX908-NEXT: s_waitcnt lgkmcnt(0)
; GFX908-NEXT: v_mov_b32_e32 v1, s4 ; GFX908-NEXT: v_mov_b32_e32 v1, s4
; GFX908-NEXT: BB8_1: ; %atomicrmw.start ; GFX908-NEXT: .LBB8_1: ; %atomicrmw.start
; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX908-NEXT: v_add_f32_e32 v0, 4.0, v1 ; GFX908-NEXT: v_add_f32_e32 v0, 4.0, v1
; GFX908-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX908-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX908-NEXT: global_atomic_cmpswap v0, v2, v[0:1], s[0:1] glc ; GFX908-NEXT: global_atomic_cmpswap v0, v2, v[0:1], s[0:1] glc
; GFX908-NEXT: s_waitcnt vmcnt(0) ; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: buffer_wbinvl1_vol ; GFX908-NEXT: buffer_wbinvl1_vol
; GFX908-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1 ; GFX908-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
; GFX908-NEXT: s_or_b64 s[2:3], vcc, s[2:3] ; GFX908-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX908-NEXT: v_mov_b32_e32 v1, v0 ; GFX908-NEXT: v_mov_b32_e32 v1, v0
; GFX908-NEXT: s_andn2_b64 exec, exec, s[2:3] ; GFX908-NEXT: s_andn2_b64 exec, exec, s[2:3]
; GFX908-NEXT: s_cbranch_execnz BB8_1 ; GFX908-NEXT: s_cbranch_execnz .LBB8_1
; GFX908-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX908-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX908-NEXT: s_endpgm ; GFX908-NEXT: s_endpgm
; ;
; GFX90A-LABEL: global_atomic_fadd_noret_f32_safe: ; GFX90A-LABEL: global_atomic_fadd_noret_f32_safe:
; GFX90A: ; %bb.0: ; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX90A-NEXT: s_mov_b64 s[2:3], 0 ; GFX90A-NEXT: s_mov_b64 s[2:3], 0
; GFX90A-NEXT: v_mov_b32_e32 v2, 0 ; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX90A-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: v_mov_b32_e32 v1, s4 ; GFX90A-NEXT: v_mov_b32_e32 v1, s4
; GFX90A-NEXT: BB8_1: ; %atomicrmw.start ; GFX90A-NEXT: .LBB8_1: ; %atomicrmw.start
; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX90A-NEXT: v_add_f32_e32 v0, 4.0, v1 ; GFX90A-NEXT: v_add_f32_e32 v0, 4.0, v1
; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-NEXT: global_atomic_cmpswap v0, v2, v[0:1], s[0:1] glc ; GFX90A-NEXT: global_atomic_cmpswap v0, v2, v[0:1], s[0:1] glc
; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: buffer_wbinvl1_vol ; GFX90A-NEXT: buffer_wbinvl1_vol
; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1 ; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
; GFX90A-NEXT: s_or_b64 s[2:3], vcc, s[2:3] ; GFX90A-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX90A-NEXT: v_mov_b32_e32 v1, v0 ; GFX90A-NEXT: v_mov_b32_e32 v1, v0
; GFX90A-NEXT: s_andn2_b64 exec, exec, s[2:3] ; GFX90A-NEXT: s_andn2_b64 exec, exec, s[2:3]
; GFX90A-NEXT: s_cbranch_execnz BB8_1 ; GFX90A-NEXT: s_cbranch_execnz .LBB8_1
; GFX90A-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX90A-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX90A-NEXT: s_endpgm ; GFX90A-NEXT: s_endpgm
; ;
; GFX10-LABEL: global_atomic_fadd_noret_f32_safe: ; GFX10-LABEL: global_atomic_fadd_noret_f32_safe:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v1, s2 ; GFX10-NEXT: v_mov_b32_e32 v1, s2
; GFX10-NEXT: s_mov_b32 s2, 0 ; GFX10-NEXT: s_mov_b32 s2, 0
; GFX10-NEXT: BB8_1: ; %atomicrmw.start ; GFX10-NEXT: .LBB8_1: ; %atomicrmw.start
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_add_f32_e32 v0, 4.0, v1 ; GFX10-NEXT: v_add_f32_e32 v0, 4.0, v1
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_cmpswap v0, v2, v[0:1], s[0:1] glc ; GFX10-NEXT: global_atomic_cmpswap v0, v2, v[0:1], s[0:1] glc
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_gl0_inv ; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv ; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v1 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v1
; GFX10-NEXT: v_mov_b32_e32 v1, v0 ; GFX10-NEXT: v_mov_b32_e32 v1, v0
; GFX10-NEXT: s_or_b32 s2, vcc_lo, s2 ; GFX10-NEXT: s_or_b32 s2, vcc_lo, s2
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s2 ; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s2
; GFX10-NEXT: s_cbranch_execnz BB8_1 ; GFX10-NEXT: s_cbranch_execnz .LBB8_1
; GFX10-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX10-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%result = atomicrmw fadd float addrspace(1)* %ptr, float 4.0 syncscope("agent") seq_cst %result = atomicrmw fadd float addrspace(1)* %ptr, float 4.0 syncscope("agent") seq_cst
ret void ret void
} }
define amdgpu_kernel void @infer_as_before_atomic(float* addrspace(4)* %arg) #0 { define amdgpu_kernel void @infer_as_before_atomic(float* addrspace(4)* %arg) #0 {
; GFX900-LABEL: infer_as_before_atomic: ; GFX900-LABEL: infer_as_before_atomic:
; GFX900: ; %bb.0: ; GFX900: ; %bb.0:
; GFX900-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX900-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX900-NEXT: s_mov_b64 s[2:3], 0 ; GFX900-NEXT: s_mov_b64 s[2:3], 0
; GFX900-NEXT: v_mov_b32_e32 v2, 0 ; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; GFX900-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX900-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX900-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX900-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-NEXT: v_mov_b32_e32 v1, s4 ; GFX900-NEXT: v_mov_b32_e32 v1, s4
; GFX900-NEXT: BB9_1: ; %atomicrmw.start ; GFX900-NEXT: .LBB9_1: ; %atomicrmw.start
; GFX900-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX900-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX900-NEXT: v_add_f32_e32 v0, 1.0, v1 ; GFX900-NEXT: v_add_f32_e32 v0, 1.0, v1
; GFX900-NEXT: global_atomic_cmpswap v0, v2, v[0:1], s[0:1] glc ; GFX900-NEXT: global_atomic_cmpswap v0, v2, v[0:1], s[0:1] glc
; GFX900-NEXT: s_waitcnt vmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1 ; GFX900-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
; GFX900-NEXT: s_or_b64 s[2:3], vcc, s[2:3] ; GFX900-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX900-NEXT: v_mov_b32_e32 v1, v0 ; GFX900-NEXT: v_mov_b32_e32 v1, v0
; GFX900-NEXT: s_andn2_b64 exec, exec, s[2:3] ; GFX900-NEXT: s_andn2_b64 exec, exec, s[2:3]
; GFX900-NEXT: s_cbranch_execnz BB9_1 ; GFX900-NEXT: s_cbranch_execnz .LBB9_1
; GFX900-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX900-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX900-NEXT: s_endpgm ; GFX900-NEXT: s_endpgm
; ;
; GFX908-LABEL: infer_as_before_atomic: ; GFX908-LABEL: infer_as_before_atomic:
; GFX908: ; %bb.0: ; GFX908: ; %bb.0:
; GFX908-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX908-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX908-NEXT: v_mov_b32_e32 v0, 0 ; GFX908-NEXT: v_mov_b32_e32 v0, 0
; GFX908-NEXT: v_mov_b32_e32 v1, 1.0 ; GFX908-NEXT: v_mov_b32_e32 v1, 1.0
Show All 20 Lines
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v1, s2 ; GFX10-NEXT: v_mov_b32_e32 v1, s2
; GFX10-NEXT: s_mov_b32 s2, 0 ; GFX10-NEXT: s_mov_b32 s2, 0
; GFX10-NEXT: BB9_1: ; %atomicrmw.start ; GFX10-NEXT: .LBB9_1: ; %atomicrmw.start
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_add_f32_e32 v0, 1.0, v1 ; GFX10-NEXT: v_add_f32_e32 v0, 1.0, v1
; GFX10-NEXT: global_atomic_cmpswap v0, v2, v[0:1], s[0:1] glc ; GFX10-NEXT: global_atomic_cmpswap v0, v2, v[0:1], s[0:1] glc
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v1 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v1
; GFX10-NEXT: v_mov_b32_e32 v1, v0 ; GFX10-NEXT: v_mov_b32_e32 v1, v0
; GFX10-NEXT: s_or_b32 s2, vcc_lo, s2 ; GFX10-NEXT: s_or_b32 s2, vcc_lo, s2
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s2 ; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s2
; GFX10-NEXT: s_cbranch_execnz BB9_1 ; GFX10-NEXT: s_cbranch_execnz .LBB9_1
; GFX10-NEXT: ; %bb.2: ; %atomicrmw.end ; GFX10-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%load = load float*, float* addrspace(4)* %arg %load = load float*, float* addrspace(4)* %arg
%v = atomicrmw fadd float* %load, float 1.0 syncscope("agent-one-as") monotonic, align 4 %v = atomicrmw fadd float* %load, float 1.0 syncscope("agent-one-as") monotonic, align 4
ret void ret void
} }
attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" "amdgpu-unsafe-fp-atomics"="true" } attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" "amdgpu-unsafe-fp-atomics"="true" }
attributes #1 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" "target-cpu"="gfx803" "target-features"="+atomic-fadd-insts" "amdgpu-unsafe-fp-atomics"="true" } attributes #1 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" "target-cpu"="gfx803" "target-features"="+atomic-fadd-insts" "amdgpu-unsafe-fp-atomics"="true" }
attributes #2 = { "amdgpu-unsafe-fp-atomics"="true" } attributes #2 = { "amdgpu-unsafe-fp-atomics"="true" }

llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll

Show All 17 Lines
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: global_load_dword v0, v1, s[0:1] glc ; GCN-NEXT: global_load_dword v0, v1, s[0:1] glc
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v3, s1 ; GCN-NEXT: v_mov_b32_e32 v3, s1
; GCN-NEXT: v_add_u32_e32 v2, 0xffffff00, v0 ; GCN-NEXT: v_add_u32_e32 v2, 0xffffff00, v0
; GCN-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1] ; GCN-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
; GCN-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0 ; GCN-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0
; GCN-NEXT: v_addc_co_u32_e32 v1, vcc, v3, v1, vcc ; GCN-NEXT: v_addc_co_u32_e32 v1, vcc, v3, v1, vcc
; GCN-NEXT: BB0_1: ; %bb3 ; GCN-NEXT: .LBB0_1: ; %bb3
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: global_load_dword v3, v[0:1], off glc ; GCN-NEXT: global_load_dword v3, v[0:1], off glc
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_add_co_u32_e32 v2, vcc, 1, v2 ; GCN-NEXT: v_add_co_u32_e32 v2, vcc, 1, v2
; GCN-NEXT: v_add_co_u32_e64 v0, s[0:1], 4, v0 ; GCN-NEXT: v_add_co_u32_e64 v0, s[0:1], 4, v0
; GCN-NEXT: v_addc_co_u32_e64 v1, s[0:1], 0, v1, s[0:1] ; GCN-NEXT: v_addc_co_u32_e64 v1, s[0:1], 0, v1, s[0:1]
; GCN-NEXT: s_and_b64 vcc, exec, vcc ; GCN-NEXT: s_and_b64 vcc, exec, vcc
; GCN-NEXT: s_cbranch_vccz BB0_1 ; GCN-NEXT: s_cbranch_vccz .LBB0_1
; GCN-NEXT: ; %bb.2: ; %bb2 ; GCN-NEXT: ; %bb.2: ; %bb2
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
bb: bb:
%i1 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 0 %i1 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 0
%i2 = load volatile i32, i32 addrspace(1)* %i1, align 4 %i2 = load volatile i32, i32 addrspace(1)* %i1, align 4
br label %bb3 br label %bb3
bb2: ; preds = %bb3 bb2: ; preds = %bb3
Show All 13 Lines
; GCN-LABEL: test_move_load_address_to_vgpr_d16_hi: ; GCN-LABEL: test_move_load_address_to_vgpr_d16_hi:
; GCN: ; %bb.0: ; %bb ; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_movk_i32 s2, 0x100 ; GCN-NEXT: s_movk_i32 s2, 0x100
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: global_load_ushort v0, v1, s[0:1] glc ; GCN-NEXT: global_load_ushort v0, v1, s[0:1] glc
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: BB1_1: ; %bb3 ; GCN-NEXT: .LBB1_1: ; %bb3
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_lshlrev_b64 v[2:3], 1, v[0:1] ; GCN-NEXT: v_lshlrev_b64 v[2:3], 1, v[0:1]
; GCN-NEXT: v_mov_b32_e32 v0, s1 ; GCN-NEXT: v_mov_b32_e32 v0, s1
; GCN-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2 ; GCN-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2
; GCN-NEXT: v_addc_co_u32_e32 v3, vcc, v0, v3, vcc ; GCN-NEXT: v_addc_co_u32_e32 v3, vcc, v0, v3, vcc
; GCN-NEXT: global_load_short_d16_hi v0, v[2:3], off glc ; GCN-NEXT: global_load_short_d16_hi v0, v[2:3], off glc
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s2, v0 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s2, v0
; GCN-NEXT: s_and_b64 vcc, exec, vcc ; GCN-NEXT: s_and_b64 vcc, exec, vcc
; GCN-NEXT: s_cbranch_vccz BB1_1 ; GCN-NEXT: s_cbranch_vccz .LBB1_1
; GCN-NEXT: ; %bb.2: ; %bb2 ; GCN-NEXT: ; %bb.2: ; %bb2
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
bb: bb:
%i1 = getelementptr inbounds i16, i16 addrspace(1)* %arg, i64 0 %i1 = getelementptr inbounds i16, i16 addrspace(1)* %arg, i64 0
%load.pre = load volatile i16, i16 addrspace(1)* %i1, align 4 %load.pre = load volatile i16, i16 addrspace(1)* %i1, align 4
%i2 = zext i16 %load.pre to i32 %i2 = zext i16 %load.pre to i32
br label %bb3 br label %bb3
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llvm/test/CodeGen/AMDGPU/global-saddr-load.ll

Show First 20 Lines • Show All 2,383 Lines • ▼ Show 20 Lines
; Full 64-bit scalar add. ; Full 64-bit scalar add.
; -------------------------------------------------------------------------------- ; --------------------------------------------------------------------------------
define amdgpu_ps void @global_addr_64bit_lsr_iv(float addrspace(1)* inreg %arg) { define amdgpu_ps void @global_addr_64bit_lsr_iv(float addrspace(1)* inreg %arg) {
; GFX9-LABEL: global_addr_64bit_lsr_iv: ; GFX9-LABEL: global_addr_64bit_lsr_iv:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_mov_b64 s[0:1], 0 ; GFX9-NEXT: s_mov_b64 s[0:1], 0
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: BB128_1: ; %bb3 ; GFX9-NEXT: .LBB128_1: ; %bb3
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_add_u32 s4, s2, s0 ; GFX9-NEXT: s_add_u32 s4, s2, s0
; GFX9-NEXT: s_addc_u32 s5, s3, s1 ; GFX9-NEXT: s_addc_u32 s5, s3, s1
; GFX9-NEXT: global_load_dword v1, v0, s[4:5] glc ; GFX9-NEXT: global_load_dword v1, v0, s[4:5] glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_add_u32 s0, s0, 4 ; GFX9-NEXT: s_add_u32 s0, s0, 4
; GFX9-NEXT: s_addc_u32 s1, s1, 0 ; GFX9-NEXT: s_addc_u32 s1, s1, 0
; GFX9-NEXT: s_cmpk_eq_i32 s0, 0x400 ; GFX9-NEXT: s_cmpk_eq_i32 s0, 0x400
; GFX9-NEXT: s_cbranch_scc0 BB128_1 ; GFX9-NEXT: s_cbranch_scc0 .LBB128_1
; GFX9-NEXT: ; %bb.2: ; %bb2 ; GFX9-NEXT: ; %bb.2: ; %bb2
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: global_addr_64bit_lsr_iv: ; GFX10-LABEL: global_addr_64bit_lsr_iv:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_mov_b64 s[0:1], 0 ; GFX10-NEXT: s_mov_b64 s[0:1], 0
; GFX10-NEXT: BB128_1: ; %bb3 ; GFX10-NEXT: .LBB128_1: ; %bb3
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_add_u32 s4, s2, s0 ; GFX10-NEXT: s_add_u32 s4, s2, s0
; GFX10-NEXT: s_addc_u32 s5, s3, s1 ; GFX10-NEXT: s_addc_u32 s5, s3, s1
; GFX10-NEXT: s_add_u32 s0, s0, 4 ; GFX10-NEXT: s_add_u32 s0, s0, 4
; GFX10-NEXT: global_load_dword v1, v0, s[4:5] glc dlc ; GFX10-NEXT: global_load_dword v1, v0, s[4:5] glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_addc_u32 s1, s1, 0 ; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_cmpk_eq_i32 s0, 0x400 ; GFX10-NEXT: s_cmpk_eq_i32 s0, 0x400
; GFX10-NEXT: s_cbranch_scc0 BB128_1 ; GFX10-NEXT: s_cbranch_scc0 .LBB128_1
; GFX10-NEXT: ; %bb.2: ; %bb2 ; GFX10-NEXT: ; %bb.2: ; %bb2
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
bb: bb:
br label %bb3 br label %bb3
bb2: ; preds = %bb3 bb2: ; preds = %bb3
ret void ret void
Show All 9 Lines
; Make sure we only have a single zero vaddr initialization. ; Make sure we only have a single zero vaddr initialization.
define amdgpu_ps void @global_addr_64bit_lsr_iv_multiload(float addrspace(1)* inreg %arg, float addrspace(1)* inreg %arg.1) { define amdgpu_ps void @global_addr_64bit_lsr_iv_multiload(float addrspace(1)* inreg %arg, float addrspace(1)* inreg %arg.1) {
; GFX9-LABEL: global_addr_64bit_lsr_iv_multiload: ; GFX9-LABEL: global_addr_64bit_lsr_iv_multiload:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_mov_b64 s[0:1], 0 ; GFX9-NEXT: s_mov_b64 s[0:1], 0
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: BB129_1: ; %bb3 ; GFX9-NEXT: .LBB129_1: ; %bb3
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_add_u32 s4, s2, s0 ; GFX9-NEXT: s_add_u32 s4, s2, s0
; GFX9-NEXT: s_addc_u32 s5, s3, s1 ; GFX9-NEXT: s_addc_u32 s5, s3, s1
; GFX9-NEXT: global_load_dword v1, v0, s[4:5] glc ; GFX9-NEXT: global_load_dword v1, v0, s[4:5] glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_load_dword v1, v0, s[4:5] glc ; GFX9-NEXT: global_load_dword v1, v0, s[4:5] glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_add_u32 s0, s0, 4 ; GFX9-NEXT: s_add_u32 s0, s0, 4
; GFX9-NEXT: s_addc_u32 s1, s1, 0 ; GFX9-NEXT: s_addc_u32 s1, s1, 0
; GFX9-NEXT: s_cmpk_eq_i32 s0, 0x400 ; GFX9-NEXT: s_cmpk_eq_i32 s0, 0x400
; GFX9-NEXT: ; kill: killed $sgpr4 killed $sgpr5 ; GFX9-NEXT: ; kill: killed $sgpr4 killed $sgpr5
; GFX9-NEXT: s_cbranch_scc0 BB129_1 ; GFX9-NEXT: s_cbranch_scc0 .LBB129_1
; GFX9-NEXT: ; %bb.2: ; %bb2 ; GFX9-NEXT: ; %bb.2: ; %bb2
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: global_addr_64bit_lsr_iv_multiload: ; GFX10-LABEL: global_addr_64bit_lsr_iv_multiload:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_mov_b64 s[0:1], 0 ; GFX10-NEXT: s_mov_b64 s[0:1], 0
; GFX10-NEXT: BB129_1: ; %bb3 ; GFX10-NEXT: .LBB129_1: ; %bb3
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_add_u32 s4, s2, s0 ; GFX10-NEXT: s_add_u32 s4, s2, s0
; GFX10-NEXT: s_addc_u32 s5, s3, s1 ; GFX10-NEXT: s_addc_u32 s5, s3, s1
; GFX10-NEXT: s_add_u32 s0, s0, 4 ; GFX10-NEXT: s_add_u32 s0, s0, 4
; GFX10-NEXT: global_load_dword v1, v0, s[4:5] glc dlc ; GFX10-NEXT: global_load_dword v1, v0, s[4:5] glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_load_dword v1, v0, s[4:5] glc dlc ; GFX10-NEXT: global_load_dword v1, v0, s[4:5] glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_addc_u32 s1, s1, 0 ; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_cmpk_eq_i32 s0, 0x400 ; GFX10-NEXT: s_cmpk_eq_i32 s0, 0x400
; GFX10-NEXT: ; kill: killed $sgpr4 killed $sgpr5 ; GFX10-NEXT: ; kill: killed $sgpr4 killed $sgpr5
; GFX10-NEXT: s_cbranch_scc0 BB129_1 ; GFX10-NEXT: s_cbranch_scc0 .LBB129_1
; GFX10-NEXT: ; %bb.2: ; %bb2 ; GFX10-NEXT: ; %bb.2: ; %bb2
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
bb: bb:
br label %bb3 br label %bb3
bb2: ; preds = %bb3 bb2: ; preds = %bb3
ret void ret void
Show All 14 Lines

llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
define amdgpu_ps void @i1_copy_from_loop(<4 x i32> inreg %rsrc, i32 %tid) { define amdgpu_ps void @i1_copy_from_loop(<4 x i32> inreg %rsrc, i32 %tid) {
; SI-LABEL: i1_copy_from_loop: ; SI-LABEL: i1_copy_from_loop:
; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: s_mov_b32 s14, 0 ; SI-NEXT: s_mov_b32 s14, 0
; SI-NEXT: s_mov_b64 s[4:5], 0 ; SI-NEXT: s_mov_b64 s[4:5], 0
; SI-NEXT: ; implicit-def: $sgpr6_sgpr7 ; SI-NEXT: ; implicit-def: $sgpr6_sgpr7
; SI-NEXT: ; implicit-def: $sgpr8_sgpr9 ; SI-NEXT: ; implicit-def: $sgpr8_sgpr9
; SI-NEXT: s_branch BB0_3 ; SI-NEXT: s_branch .LBB0_3
; SI-NEXT: BB0_1: ; in Loop: Header=BB0_3 Depth=1 ; SI-NEXT: .LBB0_1: ; in Loop: Header=BB0_3 Depth=1
; SI-NEXT: ; implicit-def: $sgpr14 ; SI-NEXT: ; implicit-def: $sgpr14
; SI-NEXT: BB0_2: ; %Flow ; SI-NEXT: .LBB0_2: ; %Flow
; SI-NEXT: ; in Loop: Header=BB0_3 Depth=1 ; SI-NEXT: ; in Loop: Header=BB0_3 Depth=1
; SI-NEXT: s_and_b64 s[12:13], exec, s[8:9] ; SI-NEXT: s_and_b64 s[12:13], exec, s[8:9]
; SI-NEXT: s_or_b64 s[4:5], s[12:13], s[4:5] ; SI-NEXT: s_or_b64 s[4:5], s[12:13], s[4:5]
; SI-NEXT: s_andn2_b64 s[6:7], s[6:7], exec ; SI-NEXT: s_andn2_b64 s[6:7], s[6:7], exec
; SI-NEXT: s_and_b64 s[10:11], s[10:11], exec ; SI-NEXT: s_and_b64 s[10:11], s[10:11], exec
; SI-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11] ; SI-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
; SI-NEXT: s_andn2_b64 exec, exec, s[4:5] ; SI-NEXT: s_andn2_b64 exec, exec, s[4:5]
; SI-NEXT: s_cbranch_execz BB0_7 ; SI-NEXT: s_cbranch_execz .LBB0_7
; SI-NEXT: BB0_3: ; %for.body ; SI-NEXT: .LBB0_3: ; %for.body
; SI-NEXT: ; =>This Inner Loop Header: Depth=1 ; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_cmp_lt_u32 s14, 4 ; SI-NEXT: s_cmp_lt_u32 s14, 4
; SI-NEXT: s_cselect_b64 s[10:11], -1, 0 ; SI-NEXT: s_cselect_b64 s[10:11], -1, 0
; SI-NEXT: s_or_b64 s[8:9], s[8:9], exec ; SI-NEXT: s_or_b64 s[8:9], s[8:9], exec
; SI-NEXT: s_cmp_gt_u32 s14, 3 ; SI-NEXT: s_cmp_gt_u32 s14, 3
; SI-NEXT: s_cbranch_scc1 BB0_1 ; SI-NEXT: s_cbranch_scc1 .LBB0_1
; SI-NEXT: ; %bb.4: ; %mid.loop ; SI-NEXT: ; %bb.4: ; %mid.loop
; SI-NEXT: ; in Loop: Header=BB0_3 Depth=1 ; SI-NEXT: ; in Loop: Header=BB0_3 Depth=1
; SI-NEXT: v_mov_b32_e32 v1, s14 ; SI-NEXT: v_mov_b32_e32 v1, s14
; SI-NEXT: buffer_load_dword v1, v[0:1], s[0:3], 0 idxen offen ; SI-NEXT: buffer_load_dword v1, v[0:1], s[0:3], 0 idxen offen
; SI-NEXT: s_mov_b64 s[10:11], -1 ; SI-NEXT: s_mov_b64 s[10:11], -1
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cmp_le_f32_e32 vcc, 0, v1 ; SI-NEXT: v_cmp_le_f32_e32 vcc, 0, v1
; SI-NEXT: s_mov_b64 s[8:9], -1 ; SI-NEXT: s_mov_b64 s[8:9], -1
; SI-NEXT: s_and_saveexec_b64 s[12:13], vcc ; SI-NEXT: s_and_saveexec_b64 s[12:13], vcc
; SI-NEXT: ; %bb.5: ; %end.loop ; SI-NEXT: ; %bb.5: ; %end.loop
; SI-NEXT: ; in Loop: Header=BB0_3 Depth=1 ; SI-NEXT: ; in Loop: Header=BB0_3 Depth=1
; SI-NEXT: s_add_i32 s14, s14, 1 ; SI-NEXT: s_add_i32 s14, s14, 1
; SI-NEXT: s_xor_b64 s[8:9], exec, -1 ; SI-NEXT: s_xor_b64 s[8:9], exec, -1
; SI-NEXT: ; %bb.6: ; %Flow1 ; SI-NEXT: ; %bb.6: ; %Flow1
; SI-NEXT: ; in Loop: Header=BB0_3 Depth=1 ; SI-NEXT: ; in Loop: Header=BB0_3 Depth=1
; SI-NEXT: s_or_b64 exec, exec, s[12:13] ; SI-NEXT: s_or_b64 exec, exec, s[12:13]
; SI-NEXT: s_branch BB0_2 ; SI-NEXT: s_branch .LBB0_2
; SI-NEXT: BB0_7: ; %for.end ; SI-NEXT: .LBB0_7: ; %for.end
; SI-NEXT: s_or_b64 exec, exec, s[4:5] ; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_and_saveexec_b64 s[0:1], s[6:7] ; SI-NEXT: s_and_saveexec_b64 s[0:1], s[6:7]
; SI-NEXT: s_cbranch_execz BB0_9 ; SI-NEXT: s_cbranch_execz .LBB0_9
; SI-NEXT: ; %bb.8: ; %if ; SI-NEXT: ; %bb.8: ; %if
; SI-NEXT: exp mrt0 v0, v0, v0, v0 done vm ; SI-NEXT: exp mrt0 v0, v0, v0, v0 done vm
; SI-NEXT: BB0_9: ; %end ; SI-NEXT: .LBB0_9: ; %end
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
entry: entry:
br label %for.body br label %for.body
for.body: for.body:
%i = phi i32 [0, %entry], [%i.inc, %end.loop] %i = phi i32 [0, %entry], [%i.inc, %end.loop]
%cc = icmp ult i32 %i, 4 %cc = icmp ult i32 %i, 4
br i1 %cc, label %mid.loop, label %for.end br i1 %cc, label %mid.loop, label %for.end
Show All 26 Lines

llvm/test/CodeGen/AMDGPU/i1-copy-phi-uniform-branch.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}test_dont_clobber_scc: ; GCN-LABEL: {{^}}test_dont_clobber_scc:
; GCN: ; %entry ; GCN: ; %entry
; GCN: s_cmp_eq_u32 s0, 0 ; GCN: s_cmp_eq_u32 s0, 0
; GCN: s_cbranch_scc1 [[EXIT:BB[0-9_]+]] ; GCN: s_cbranch_scc1 [[EXIT:.LBB[0-9_]+]]
; GCN: ; %blocka ; GCN: ; %blocka
; GCN: s_cmp_eq_u32 s1, 0 ; GCN: s_cmp_eq_u32 s1, 0
; GCN: s_cbranch_scc1 [[PREEXIT:BB[0-9_]+]] ; GCN: s_cbranch_scc1 [[PREEXIT:.LBB[0-9_]+]]
; GCN: [[PREEXIT]]: ; GCN: [[PREEXIT]]:
; GCN: [[EXIT]]: ; GCN: [[EXIT]]:
define amdgpu_vs float @test_dont_clobber_scc(i32 inreg %uni, i32 inreg %uni2) #0 { define amdgpu_vs float @test_dont_clobber_scc(i32 inreg %uni, i32 inreg %uni2) #0 {
entry: entry:
%cc.uni = icmp eq i32 %uni, 0 %cc.uni = icmp eq i32 %uni, 0
br i1 %cc.uni, label %exit, label %blocka br i1 %cc.uni, label %exit, label %blocka
Show All 18 Lines

llvm/test/CodeGen/AMDGPU/idiv-licm.ll

Show All 12 Lines
; GFX9-NEXT: s_sub_i32 s5, 0, s4 ; GFX9-NEXT: s_sub_i32 s5, 0, s4
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_mul_lo_u32 v1, s5, v0 ; GFX9-NEXT: v_mul_lo_u32 v1, s5, v0
; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX9-NEXT: v_add_u32_e32 v0, v0, v1 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: BB0_1: ; %bb3 ; GFX9-NEXT: .LBB0_1: ; %bb3
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mul_lo_u32 v2, s3, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, s3, v0
; GFX9-NEXT: v_mul_hi_u32 v3, s2, v0 ; GFX9-NEXT: v_mul_hi_u32 v3, s2, v0
; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
; GFX9-NEXT: v_mul_lo_u32 v3, s5, v2 ; GFX9-NEXT: v_mul_lo_u32 v3, s5, v2
; GFX9-NEXT: v_not_b32_e32 v5, v2 ; GFX9-NEXT: v_not_b32_e32 v5, v2
; GFX9-NEXT: v_mul_lo_u32 v5, s4, v5 ; GFX9-NEXT: v_mul_lo_u32 v5, s4, v5
; GFX9-NEXT: v_add_u32_e32 v4, 1, v2 ; GFX9-NEXT: v_add_u32_e32 v4, 1, v2
; GFX9-NEXT: v_add_u32_e32 v3, s2, v3 ; GFX9-NEXT: v_add_u32_e32 v3, s2, v3
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v3
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX9-NEXT: v_add_u32_e32 v4, s2, v5 ; GFX9-NEXT: v_add_u32_e32 v4, s2, v5
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX9-NEXT: s_add_u32 s2, s2, 1 ; GFX9-NEXT: s_add_u32 s2, s2, 1
; GFX9-NEXT: v_add_u32_e32 v4, 1, v2 ; GFX9-NEXT: v_add_u32_e32 v4, 1, v2
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v3
; GFX9-NEXT: s_addc_u32 s3, s3, 0 ; GFX9-NEXT: s_addc_u32 s3, s3, 0
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX9-NEXT: global_store_dword v1, v2, s[0:1] ; GFX9-NEXT: global_store_dword v1, v2, s[0:1]
; GFX9-NEXT: s_add_u32 s0, s0, 4 ; GFX9-NEXT: s_add_u32 s0, s0, 4
; GFX9-NEXT: s_addc_u32 s1, s1, 0 ; GFX9-NEXT: s_addc_u32 s1, s1, 0
; GFX9-NEXT: s_cmpk_eq_i32 s2, 0x400 ; GFX9-NEXT: s_cmpk_eq_i32 s2, 0x400
; GFX9-NEXT: s_cbranch_scc0 BB0_1 ; GFX9-NEXT: s_cbranch_scc0 .LBB0_1
; GFX9-NEXT: ; %bb.2: ; %bb2 ; GFX9-NEXT: ; %bb.2: ; %bb2
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: udiv32_invariant_denom: ; GFX10-LABEL: udiv32_invariant_denom:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c ; GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
; GFX10-NEXT: s_mov_b64 s[2:3], 0 ; GFX10-NEXT: s_mov_b64 s[2:3], 0
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s4 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s4
; GFX10-NEXT: s_sub_i32 s5, 0, s4 ; GFX10-NEXT: s_sub_i32 s5, 0, s4
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: v_mul_lo_u32 v1, s5, v0 ; GFX10-NEXT: v_mul_lo_u32 v1, s5, v0
; GFX10-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX10-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: BB0_1: ; %bb3 ; GFX10-NEXT: .LBB0_1: ; %bb3
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mul_lo_u32 v2, s3, v0 ; GFX10-NEXT: v_mul_lo_u32 v2, s3, v0
; GFX10-NEXT: v_mul_hi_u32 v3, s2, v0 ; GFX10-NEXT: v_mul_hi_u32 v3, s2, v0
; GFX10-NEXT: v_add_nc_u32_e32 v2, v3, v2 ; GFX10-NEXT: v_add_nc_u32_e32 v2, v3, v2
; GFX10-NEXT: v_not_b32_e32 v3, v2 ; GFX10-NEXT: v_not_b32_e32 v3, v2
; GFX10-NEXT: v_mul_lo_u32 v4, s5, v2 ; GFX10-NEXT: v_mul_lo_u32 v4, s5, v2
; GFX10-NEXT: v_add_nc_u32_e32 v5, 1, v2 ; GFX10-NEXT: v_add_nc_u32_e32 v5, 1, v2
; GFX10-NEXT: v_mul_lo_u32 v3, s4, v3 ; GFX10-NEXT: v_mul_lo_u32 v3, s4, v3
; GFX10-NEXT: v_add_nc_u32_e32 v4, s2, v4 ; GFX10-NEXT: v_add_nc_u32_e32 v4, s2, v4
; GFX10-NEXT: v_add_nc_u32_e32 v3, s2, v3 ; GFX10-NEXT: v_add_nc_u32_e32 v3, s2, v3
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s4, v4 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s4, v4
; GFX10-NEXT: s_add_u32 s2, s2, 1 ; GFX10-NEXT: s_add_u32 s2, s2, 1
; GFX10-NEXT: s_addc_u32 s3, s3, 0 ; GFX10-NEXT: s_addc_u32 s3, s3, 0
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v2 ; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v2
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s4, v3 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s4, v3
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX10-NEXT: global_store_dword v1, v2, s[0:1] ; GFX10-NEXT: global_store_dword v1, v2, s[0:1]
; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_add_u32 s0, s0, 4 ; GFX10-NEXT: s_add_u32 s0, s0, 4
; GFX10-NEXT: s_addc_u32 s1, s1, 0 ; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_cmpk_eq_i32 s2, 0x400 ; GFX10-NEXT: s_cmpk_eq_i32 s2, 0x400
; GFX10-NEXT: s_cbranch_scc0 BB0_1 ; GFX10-NEXT: s_cbranch_scc0 .LBB0_1
; GFX10-NEXT: ; %bb.2: ; %bb2 ; GFX10-NEXT: ; %bb.2: ; %bb2
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
bb: bb:
br label %bb3 br label %bb3
bb2: ; preds = %bb3 bb2: ; preds = %bb3
ret void ret void
Show All 19 Lines
; GFX9-NEXT: s_sub_i32 s5, 0, s4 ; GFX9-NEXT: s_sub_i32 s5, 0, s4
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_mul_lo_u32 v1, s5, v0 ; GFX9-NEXT: v_mul_lo_u32 v1, s5, v0
; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX9-NEXT: v_add_u32_e32 v0, v0, v1 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: BB1_1: ; %bb3 ; GFX9-NEXT: .LBB1_1: ; %bb3
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mul_lo_u32 v2, s3, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, s3, v0
; GFX9-NEXT: v_mul_hi_u32 v3, s2, v0 ; GFX9-NEXT: v_mul_hi_u32 v3, s2, v0
; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
; GFX9-NEXT: v_mul_lo_u32 v3, s5, v2 ; GFX9-NEXT: v_mul_lo_u32 v3, s5, v2
; GFX9-NEXT: v_not_b32_e32 v2, v2 ; GFX9-NEXT: v_not_b32_e32 v2, v2
; GFX9-NEXT: v_mul_lo_u32 v2, s4, v2 ; GFX9-NEXT: v_mul_lo_u32 v2, s4, v2
; GFX9-NEXT: v_add_u32_e32 v3, s2, v3 ; GFX9-NEXT: v_add_u32_e32 v3, s2, v3
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v3
; GFX9-NEXT: v_add_u32_e32 v2, s2, v2 ; GFX9-NEXT: v_add_u32_e32 v2, s2, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX9-NEXT: s_add_u32 s2, s2, 1 ; GFX9-NEXT: s_add_u32 s2, s2, 1
; GFX9-NEXT: v_subrev_u32_e32 v3, s4, v2 ; GFX9-NEXT: v_subrev_u32_e32 v3, s4, v2
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v2 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v2
; GFX9-NEXT: s_addc_u32 s3, s3, 0 ; GFX9-NEXT: s_addc_u32 s3, s3, 0
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX9-NEXT: global_store_dword v1, v2, s[0:1] ; GFX9-NEXT: global_store_dword v1, v2, s[0:1]
; GFX9-NEXT: s_add_u32 s0, s0, 4 ; GFX9-NEXT: s_add_u32 s0, s0, 4
; GFX9-NEXT: s_addc_u32 s1, s1, 0 ; GFX9-NEXT: s_addc_u32 s1, s1, 0
; GFX9-NEXT: s_cmpk_eq_i32 s2, 0x400 ; GFX9-NEXT: s_cmpk_eq_i32 s2, 0x400
; GFX9-NEXT: s_cbranch_scc0 BB1_1 ; GFX9-NEXT: s_cbranch_scc0 .LBB1_1
; GFX9-NEXT: ; %bb.2: ; %bb2 ; GFX9-NEXT: ; %bb.2: ; %bb2
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: urem32_invariant_denom: ; GFX10-LABEL: urem32_invariant_denom:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c ; GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
; GFX10-NEXT: s_mov_b64 s[2:3], 0 ; GFX10-NEXT: s_mov_b64 s[2:3], 0
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s4 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s4
; GFX10-NEXT: s_sub_i32 s5, 0, s4 ; GFX10-NEXT: s_sub_i32 s5, 0, s4
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: v_mul_lo_u32 v1, s5, v0 ; GFX10-NEXT: v_mul_lo_u32 v1, s5, v0
; GFX10-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX10-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: BB1_1: ; %bb3 ; GFX10-NEXT: .LBB1_1: ; %bb3
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mul_lo_u32 v2, s3, v0 ; GFX10-NEXT: v_mul_lo_u32 v2, s3, v0
; GFX10-NEXT: v_mul_hi_u32 v3, s2, v0 ; GFX10-NEXT: v_mul_hi_u32 v3, s2, v0
; GFX10-NEXT: v_add_nc_u32_e32 v2, v3, v2 ; GFX10-NEXT: v_add_nc_u32_e32 v2, v3, v2
; GFX10-NEXT: v_not_b32_e32 v3, v2 ; GFX10-NEXT: v_not_b32_e32 v3, v2
; GFX10-NEXT: v_mul_lo_u32 v2, s5, v2 ; GFX10-NEXT: v_mul_lo_u32 v2, s5, v2
; GFX10-NEXT: v_mul_lo_u32 v3, s4, v3 ; GFX10-NEXT: v_mul_lo_u32 v3, s4, v3
; GFX10-NEXT: v_add_nc_u32_e32 v2, s2, v2 ; GFX10-NEXT: v_add_nc_u32_e32 v2, s2, v2
; GFX10-NEXT: v_add_nc_u32_e32 v3, s2, v3 ; GFX10-NEXT: v_add_nc_u32_e32 v3, s2, v3
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s4, v2 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s4, v2
; GFX10-NEXT: s_add_u32 s2, s2, 1 ; GFX10-NEXT: s_add_u32 s2, s2, 1
; GFX10-NEXT: s_addc_u32 s3, s3, 0 ; GFX10-NEXT: s_addc_u32 s3, s3, 0
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX10-NEXT: v_subrev_nc_u32_e32 v3, s4, v2 ; GFX10-NEXT: v_subrev_nc_u32_e32 v3, s4, v2
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s4, v2 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s4, v2
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX10-NEXT: global_store_dword v1, v2, s[0:1] ; GFX10-NEXT: global_store_dword v1, v2, s[0:1]
; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_add_u32 s0, s0, 4 ; GFX10-NEXT: s_add_u32 s0, s0, 4
; GFX10-NEXT: s_addc_u32 s1, s1, 0 ; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_cmpk_eq_i32 s2, 0x400 ; GFX10-NEXT: s_cmpk_eq_i32 s2, 0x400
; GFX10-NEXT: s_cbranch_scc0 BB1_1 ; GFX10-NEXT: s_cbranch_scc0 .LBB1_1
; GFX10-NEXT: ; %bb.2: ; %bb2 ; GFX10-NEXT: ; %bb.2: ; %bb2
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
bb: bb:
br label %bb3 br label %bb3
bb2: ; preds = %bb3 bb2: ; preds = %bb3
ret void ret void
Show All 22 Lines
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_mul_lo_u32 v1, s4, v0 ; GFX9-NEXT: v_mul_lo_u32 v1, s4, v0
; GFX9-NEXT: s_mov_b32 s4, 0 ; GFX9-NEXT: s_mov_b32 s4, 0
; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX9-NEXT: v_add_u32_e32 v0, v0, v1 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: BB2_1: ; %bb3 ; GFX9-NEXT: .LBB2_1: ; %bb3
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mul_hi_u32 v2, s4, v0 ; GFX9-NEXT: v_mul_hi_u32 v2, s4, v0
; GFX9-NEXT: v_mul_lo_u32 v3, v2, s3 ; GFX9-NEXT: v_mul_lo_u32 v3, v2, s3
; GFX9-NEXT: v_add_u32_e32 v4, 1, v2 ; GFX9-NEXT: v_add_u32_e32 v4, 1, v2
; GFX9-NEXT: v_sub_u32_e32 v3, s4, v3 ; GFX9-NEXT: v_sub_u32_e32 v3, s4, v3
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v3
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX9-NEXT: v_subrev_u32_e32 v4, s3, v3 ; GFX9-NEXT: v_subrev_u32_e32 v4, s3, v3
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX9-NEXT: v_add_u32_e32 v4, 1, v2 ; GFX9-NEXT: v_add_u32_e32 v4, 1, v2
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v3
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX9-NEXT: v_xor_b32_e32 v2, s2, v2 ; GFX9-NEXT: v_xor_b32_e32 v2, s2, v2
; GFX9-NEXT: s_add_i32 s4, s4, 1 ; GFX9-NEXT: s_add_i32 s4, s4, 1
; GFX9-NEXT: v_subrev_u32_e32 v2, s2, v2 ; GFX9-NEXT: v_subrev_u32_e32 v2, s2, v2
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dword v1, v2, s[0:1] ; GFX9-NEXT: global_store_dword v1, v2, s[0:1]
; GFX9-NEXT: s_add_u32 s0, s0, 4 ; GFX9-NEXT: s_add_u32 s0, s0, 4
; GFX9-NEXT: s_addc_u32 s1, s1, 0 ; GFX9-NEXT: s_addc_u32 s1, s1, 0
; GFX9-NEXT: s_cmpk_eq_i32 s4, 0x400 ; GFX9-NEXT: s_cmpk_eq_i32 s4, 0x400
; GFX9-NEXT: s_cbranch_scc0 BB2_1 ; GFX9-NEXT: s_cbranch_scc0 .LBB2_1
; GFX9-NEXT: ; %bb.2: ; %bb2 ; GFX9-NEXT: ; %bb.2: ; %bb2
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: sdiv32_invariant_denom: ; GFX10-LABEL: sdiv32_invariant_denom:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_load_dword s3, s[0:1], 0x2c ; GFX10-NEXT: s_load_dword s3, s[0:1], 0x2c
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_ashr_i32 s2, s3, 31 ; GFX10-NEXT: s_ashr_i32 s2, s3, 31
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX10-NEXT: s_add_i32 s3, s3, s2 ; GFX10-NEXT: s_add_i32 s3, s3, s2
; GFX10-NEXT: s_xor_b32 s3, s3, s2 ; GFX10-NEXT: s_xor_b32 s3, s3, s2
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s3 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s3
; GFX10-NEXT: s_sub_i32 s4, 0, s3 ; GFX10-NEXT: s_sub_i32 s4, 0, s3
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: v_mul_lo_u32 v1, s4, v0 ; GFX10-NEXT: v_mul_lo_u32 v1, s4, v0
; GFX10-NEXT: s_mov_b32 s4, 0 ; GFX10-NEXT: s_mov_b32 s4, 0
; GFX10-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX10-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: BB2_1: ; %bb3 ; GFX10-NEXT: .LBB2_1: ; %bb3
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mul_hi_u32 v2, s4, v0 ; GFX10-NEXT: v_mul_hi_u32 v2, s4, v0
; GFX10-NEXT: v_mul_lo_u32 v3, v2, s3 ; GFX10-NEXT: v_mul_lo_u32 v3, v2, s3
; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v2 ; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v2
; GFX10-NEXT: v_sub_nc_u32_e32 v3, s4, v3 ; GFX10-NEXT: v_sub_nc_u32_e32 v3, s4, v3
; GFX10-NEXT: s_add_i32 s4, s4, 1 ; GFX10-NEXT: s_add_i32 s4, s4, 1
; GFX10-NEXT: v_subrev_nc_u32_e32 v5, s3, v3 ; GFX10-NEXT: v_subrev_nc_u32_e32 v5, s3, v3
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s3, v3 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s3, v3
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v2 ; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v2
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s3, v3 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s3, v3
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX10-NEXT: v_xor_b32_e32 v2, s2, v2 ; GFX10-NEXT: v_xor_b32_e32 v2, s2, v2
; GFX10-NEXT: v_subrev_nc_u32_e32 v2, s2, v2 ; GFX10-NEXT: v_subrev_nc_u32_e32 v2, s2, v2
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_store_dword v1, v2, s[0:1] ; GFX10-NEXT: global_store_dword v1, v2, s[0:1]
; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_add_u32 s0, s0, 4 ; GFX10-NEXT: s_add_u32 s0, s0, 4
; GFX10-NEXT: s_addc_u32 s1, s1, 0 ; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_cmpk_eq_i32 s4, 0x400 ; GFX10-NEXT: s_cmpk_eq_i32 s4, 0x400
; GFX10-NEXT: s_cbranch_scc0 BB2_1 ; GFX10-NEXT: s_cbranch_scc0 .LBB2_1
; GFX10-NEXT: ; %bb.2: ; %bb2 ; GFX10-NEXT: ; %bb.2: ; %bb2
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
bb: bb:
br label %bb3 br label %bb3
bb2: ; preds = %bb3 bb2: ; preds = %bb3
ret void ret void
Show All 22 Lines
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_mul_lo_u32 v1, s3, v0 ; GFX9-NEXT: v_mul_lo_u32 v1, s3, v0
; GFX9-NEXT: s_mov_b32 s3, 0 ; GFX9-NEXT: s_mov_b32 s3, 0
; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX9-NEXT: v_add_u32_e32 v0, v0, v1 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: BB3_1: ; %bb3 ; GFX9-NEXT: .LBB3_1: ; %bb3
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mul_hi_u32 v2, s3, v0 ; GFX9-NEXT: v_mul_hi_u32 v2, s3, v0
; GFX9-NEXT: v_mul_lo_u32 v2, v2, s2 ; GFX9-NEXT: v_mul_lo_u32 v2, v2, s2
; GFX9-NEXT: v_sub_u32_e32 v2, s3, v2 ; GFX9-NEXT: v_sub_u32_e32 v2, s3, v2
; GFX9-NEXT: v_subrev_u32_e32 v3, s2, v2 ; GFX9-NEXT: v_subrev_u32_e32 v3, s2, v2
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v2 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX9-NEXT: v_subrev_u32_e32 v3, s2, v2 ; GFX9-NEXT: v_subrev_u32_e32 v3, s2, v2
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v2 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v2
; GFX9-NEXT: s_add_i32 s3, s3, 1 ; GFX9-NEXT: s_add_i32 s3, s3, 1
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dword v1, v2, s[0:1] ; GFX9-NEXT: global_store_dword v1, v2, s[0:1]
; GFX9-NEXT: s_add_u32 s0, s0, 4 ; GFX9-NEXT: s_add_u32 s0, s0, 4
; GFX9-NEXT: s_addc_u32 s1, s1, 0 ; GFX9-NEXT: s_addc_u32 s1, s1, 0
; GFX9-NEXT: s_cmpk_eq_i32 s3, 0x400 ; GFX9-NEXT: s_cmpk_eq_i32 s3, 0x400
; GFX9-NEXT: s_cbranch_scc0 BB3_1 ; GFX9-NEXT: s_cbranch_scc0 .LBB3_1
; GFX9-NEXT: ; %bb.2: ; %bb2 ; GFX9-NEXT: ; %bb.2: ; %bb2
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: srem32_invariant_denom: ; GFX10-LABEL: srem32_invariant_denom:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_load_dword s2, s[0:1], 0x2c ; GFX10-NEXT: s_load_dword s2, s[0:1], 0x2c
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_ashr_i32 s3, s2, 31 ; GFX10-NEXT: s_ashr_i32 s3, s2, 31
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX10-NEXT: s_add_i32 s2, s2, s3 ; GFX10-NEXT: s_add_i32 s2, s2, s3
; GFX10-NEXT: s_xor_b32 s2, s2, s3 ; GFX10-NEXT: s_xor_b32 s2, s2, s3
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s2 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX10-NEXT: s_sub_i32 s3, 0, s2 ; GFX10-NEXT: s_sub_i32 s3, 0, s2
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: v_mul_lo_u32 v1, s3, v0 ; GFX10-NEXT: v_mul_lo_u32 v1, s3, v0
; GFX10-NEXT: s_mov_b32 s3, 0 ; GFX10-NEXT: s_mov_b32 s3, 0
; GFX10-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX10-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: BB3_1: ; %bb3 ; GFX10-NEXT: .LBB3_1: ; %bb3
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mul_hi_u32 v2, s3, v0 ; GFX10-NEXT: v_mul_hi_u32 v2, s3, v0
; GFX10-NEXT: v_mul_lo_u32 v2, v2, s2 ; GFX10-NEXT: v_mul_lo_u32 v2, v2, s2
; GFX10-NEXT: v_sub_nc_u32_e32 v2, s3, v2 ; GFX10-NEXT: v_sub_nc_u32_e32 v2, s3, v2
; GFX10-NEXT: s_add_i32 s3, s3, 1 ; GFX10-NEXT: s_add_i32 s3, s3, 1
; GFX10-NEXT: v_subrev_nc_u32_e32 v3, s2, v2 ; GFX10-NEXT: v_subrev_nc_u32_e32 v3, s2, v2
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v2 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v2
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX10-NEXT: v_subrev_nc_u32_e32 v3, s2, v2 ; GFX10-NEXT: v_subrev_nc_u32_e32 v3, s2, v2
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v2 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v2
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_store_dword v1, v2, s[0:1] ; GFX10-NEXT: global_store_dword v1, v2, s[0:1]
; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_add_u32 s0, s0, 4 ; GFX10-NEXT: s_add_u32 s0, s0, 4
; GFX10-NEXT: s_addc_u32 s1, s1, 0 ; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_cmpk_eq_i32 s3, 0x400 ; GFX10-NEXT: s_cmpk_eq_i32 s3, 0x400
; GFX10-NEXT: s_cbranch_scc0 BB3_1 ; GFX10-NEXT: s_cbranch_scc0 .LBB3_1
; GFX10-NEXT: ; %bb.2: ; %bb2 ; GFX10-NEXT: ; %bb.2: ; %bb2
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
bb: bb:
br label %bb3 br label %bb3
bb2: ; preds = %bb3 bb2: ; preds = %bb3
ret void ret void
Show All 16 Lines
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: s_movk_i32 s5, 0x400 ; GFX9-NEXT: s_movk_i32 s5, 0x400
; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_and_b32 s2, s4, s2 ; GFX9-NEXT: s_and_b32 s2, s4, s2
; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s2 ; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s2
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v2 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v2
; GFX9-NEXT: BB4_1: ; %bb3 ; GFX9-NEXT: .LBB4_1: ; %bb3
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_and_b32_e32 v0, s4, v4 ; GFX9-NEXT: v_and_b32_e32 v0, s4, v4
; GFX9-NEXT: v_cvt_f32_u32_e32 v8, v0 ; GFX9-NEXT: v_cvt_f32_u32_e32 v8, v0
; GFX9-NEXT: v_lshlrev_b64 v[5:6], 1, v[0:1] ; GFX9-NEXT: v_lshlrev_b64 v[5:6], 1, v[0:1]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v7, s3 ; GFX9-NEXT: v_mov_b32_e32 v7, s3
; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], s2, v5 ; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], s2, v5
; GFX9-NEXT: v_mul_f32_e32 v0, v8, v3 ; GFX9-NEXT: v_mul_f32_e32 v0, v8, v3
; GFX9-NEXT: v_trunc_f32_e32 v0, v0 ; GFX9-NEXT: v_trunc_f32_e32 v0, v0
; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1]
; GFX9-NEXT: v_cvt_u32_f32_e32 v7, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v7, v0
; GFX9-NEXT: v_add_u16_e32 v4, 1, v4 ; GFX9-NEXT: v_add_u16_e32 v4, 1, v4
; GFX9-NEXT: v_mad_f32 v0, -v0, v2, v8 ; GFX9-NEXT: v_mad_f32 v0, -v0, v2, v8
; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, s5, v4 ; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, s5, v4
; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v0|, v2 ; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v0|, v2
; GFX9-NEXT: s_and_b64 vcc, exec, vcc ; GFX9-NEXT: s_and_b64 vcc, exec, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v0, s[0:1], 0, v7, s[0:1] ; GFX9-NEXT: v_addc_co_u32_e64 v0, s[0:1], 0, v7, s[0:1]
; GFX9-NEXT: global_store_short v[5:6], v0, off ; GFX9-NEXT: global_store_short v[5:6], v0, off
; GFX9-NEXT: s_cbranch_vccz BB4_1 ; GFX9-NEXT: s_cbranch_vccz .LBB4_1
; GFX9-NEXT: ; %bb.2: ; %bb2 ; GFX9-NEXT: ; %bb.2: ; %bb2
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: udiv16_invariant_denom: ; GFX10-LABEL: udiv16_invariant_denom:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c ; GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX10-NEXT: s_mov_b32 s1, 0xffff ; GFX10-NEXT: s_mov_b32 s1, 0xffff
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_and_b32 s0, s1, s4 ; GFX10-NEXT: s_and_b32 s0, s1, s4
; GFX10-NEXT: v_cvt_f32_u32_e32 v2, s0 ; GFX10-NEXT: v_cvt_f32_u32_e32 v2, s0
; GFX10-NEXT: v_rcp_iflag_f32_e32 v3, v2 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v3, v2
; GFX10-NEXT: BB4_1: ; %bb3 ; GFX10-NEXT: .LBB4_1: ; %bb3
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_and_b32_e32 v0, s1, v4 ; GFX10-NEXT: v_and_b32_e32 v0, s1, v4
; GFX10-NEXT: v_add_nc_u16 v4, v4, 1 ; GFX10-NEXT: v_add_nc_u16 v4, v4, 1
; GFX10-NEXT: v_cvt_f32_u32_e32 v7, v0 ; GFX10-NEXT: v_cvt_f32_u32_e32 v7, v0
; GFX10-NEXT: v_lshlrev_b64 v[5:6], 1, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[5:6], 1, v[0:1]
; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x400, v4 ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x400, v4
; GFX10-NEXT: v_mul_f32_e32 v0, v7, v3 ; GFX10-NEXT: v_mul_f32_e32 v0, v7, v3
; GFX10-NEXT: v_add_co_u32 v5, s0, s2, v5 ; GFX10-NEXT: v_add_co_u32 v5, s0, s2, v5
; GFX10-NEXT: v_add_co_ci_u32_e64 v6, s0, s3, v6, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
; GFX10-NEXT: v_trunc_f32_e32 v0, v0 ; GFX10-NEXT: v_trunc_f32_e32 v0, v0
; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, vcc_lo ; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, vcc_lo
; GFX10-NEXT: v_mad_f32 v7, -v0, v2, v7 ; GFX10-NEXT: v_mad_f32 v7, -v0, v2, v7
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: v_cmp_ge_f32_e64 s0, |v7|, v2 ; GFX10-NEXT: v_cmp_ge_f32_e64 s0, |v7|, v2
; GFX10-NEXT: v_add_co_ci_u32_e64 v0, s0, 0, v0, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v0, s0, 0, v0, s0
; GFX10-NEXT: global_store_short v[5:6], v0, off ; GFX10-NEXT: global_store_short v[5:6], v0, off
; GFX10-NEXT: s_cbranch_vccz BB4_1 ; GFX10-NEXT: s_cbranch_vccz .LBB4_1
; GFX10-NEXT: ; %bb.2: ; %bb2 ; GFX10-NEXT: ; %bb.2: ; %bb2
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
bb: bb:
br label %bb3 br label %bb3
bb2: ; preds = %bb3 bb2: ; preds = %bb3
ret void ret void
Show All 16 Lines
; GFX9-NEXT: s_mov_b32 s6, 0xffff ; GFX9-NEXT: s_mov_b32 s6, 0xffff
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: s_movk_i32 s8, 0x400 ; GFX9-NEXT: s_movk_i32 s8, 0x400
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_and_b32 s7, s6, s2 ; GFX9-NEXT: s_and_b32 s7, s6, s2
; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s7 ; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s7
; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v2 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v2
; GFX9-NEXT: BB5_1: ; %bb3 ; GFX9-NEXT: .LBB5_1: ; %bb3
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_and_b32_e32 v0, s6, v4 ; GFX9-NEXT: v_and_b32_e32 v0, s6, v4
; GFX9-NEXT: v_cvt_f32_u32_e32 v8, v0 ; GFX9-NEXT: v_cvt_f32_u32_e32 v8, v0
; GFX9-NEXT: v_lshlrev_b64 v[5:6], 1, v[0:1] ; GFX9-NEXT: v_lshlrev_b64 v[5:6], 1, v[0:1]
; GFX9-NEXT: v_add_u16_e32 v4, 1, v4 ; GFX9-NEXT: v_add_u16_e32 v4, 1, v4
; GFX9-NEXT: v_mov_b32_e32 v7, s5 ; GFX9-NEXT: v_mov_b32_e32 v7, s5
; GFX9-NEXT: v_mul_f32_e32 v9, v8, v3 ; GFX9-NEXT: v_mul_f32_e32 v9, v8, v3
; GFX9-NEXT: v_trunc_f32_e32 v9, v9 ; GFX9-NEXT: v_trunc_f32_e32 v9, v9
; GFX9-NEXT: v_cvt_u32_f32_e32 v10, v9 ; GFX9-NEXT: v_cvt_u32_f32_e32 v10, v9
; GFX9-NEXT: v_mad_f32 v8, -v9, v2, v8 ; GFX9-NEXT: v_mad_f32 v8, -v9, v2, v8
; GFX9-NEXT: v_cmp_ge_f32_e64 s[2:3], |v8|, v2 ; GFX9-NEXT: v_cmp_ge_f32_e64 s[2:3], |v8|, v2
; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, s8, v4 ; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, s8, v4
; GFX9-NEXT: v_addc_co_u32_e64 v8, s[2:3], 0, v10, s[2:3] ; GFX9-NEXT: v_addc_co_u32_e64 v8, s[2:3], 0, v10, s[2:3]
; GFX9-NEXT: v_mul_lo_u32 v8, v8, s7 ; GFX9-NEXT: v_mul_lo_u32 v8, v8, s7
; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], s4, v5 ; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], s4, v5
; GFX9-NEXT: s_and_b64 vcc, exec, vcc ; GFX9-NEXT: s_and_b64 vcc, exec, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1]
; GFX9-NEXT: v_sub_u32_e32 v0, v0, v8 ; GFX9-NEXT: v_sub_u32_e32 v0, v0, v8
; GFX9-NEXT: global_store_short v[5:6], v0, off ; GFX9-NEXT: global_store_short v[5:6], v0, off
; GFX9-NEXT: s_cbranch_vccz BB5_1 ; GFX9-NEXT: s_cbranch_vccz .LBB5_1
; GFX9-NEXT: ; %bb.2: ; %bb2 ; GFX9-NEXT: ; %bb.2: ; %bb2
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: urem16_invariant_denom: ; GFX10-LABEL: urem16_invariant_denom:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c ; GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX10-NEXT: s_mov_b32 s1, 0xffff ; GFX10-NEXT: s_mov_b32 s1, 0xffff
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_and_b32 s4, s1, s4 ; GFX10-NEXT: s_and_b32 s4, s1, s4
; GFX10-NEXT: v_cvt_f32_u32_e32 v2, s4 ; GFX10-NEXT: v_cvt_f32_u32_e32 v2, s4
; GFX10-NEXT: v_rcp_iflag_f32_e32 v3, v2 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v3, v2
; GFX10-NEXT: BB5_1: ; %bb3 ; GFX10-NEXT: .LBB5_1: ; %bb3
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_and_b32_e32 v0, s1, v4 ; GFX10-NEXT: v_and_b32_e32 v0, s1, v4
; GFX10-NEXT: v_add_nc_u16 v4, v4, 1 ; GFX10-NEXT: v_add_nc_u16 v4, v4, 1
; GFX10-NEXT: v_cvt_f32_u32_e32 v7, v0 ; GFX10-NEXT: v_cvt_f32_u32_e32 v7, v0
; GFX10-NEXT: v_lshlrev_b64 v[5:6], 1, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[5:6], 1, v[0:1]
; GFX10-NEXT: v_mul_f32_e32 v8, v7, v3 ; GFX10-NEXT: v_mul_f32_e32 v8, v7, v3
; GFX10-NEXT: v_add_co_u32 v5, s0, s2, v5 ; GFX10-NEXT: v_add_co_u32 v5, s0, s2, v5
; GFX10-NEXT: v_add_co_ci_u32_e64 v6, s0, s3, v6, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
; GFX10-NEXT: v_trunc_f32_e32 v8, v8 ; GFX10-NEXT: v_trunc_f32_e32 v8, v8
; GFX10-NEXT: v_mad_f32 v7, -v8, v2, v7 ; GFX10-NEXT: v_mad_f32 v7, -v8, v2, v7
; GFX10-NEXT: v_cvt_u32_f32_e32 v8, v8 ; GFX10-NEXT: v_cvt_u32_f32_e32 v8, v8
; GFX10-NEXT: v_cmp_ge_f32_e64 vcc_lo, |v7|, v2 ; GFX10-NEXT: v_cmp_ge_f32_e64 vcc_lo, |v7|, v2
; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x400, v4 ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x400, v4
; GFX10-NEXT: v_mul_lo_u32 v7, v7, s4 ; GFX10-NEXT: v_mul_lo_u32 v7, v7, s4
; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, vcc_lo ; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, vcc_lo
; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v7 ; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v7
; GFX10-NEXT: global_store_short v[5:6], v0, off ; GFX10-NEXT: global_store_short v[5:6], v0, off
; GFX10-NEXT: s_cbranch_vccz BB5_1 ; GFX10-NEXT: s_cbranch_vccz .LBB5_1
; GFX10-NEXT: ; %bb.2: ; %bb2 ; GFX10-NEXT: ; %bb.2: ; %bb2
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
bb: bb:
br label %bb3 br label %bb3
bb2: ; preds = %bb3 bb2: ; preds = %bb3
ret void ret void
Show All 15 Lines
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: s_movk_i32 s5, 0x400 ; GFX9-NEXT: s_movk_i32 s5, 0x400
; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_sext_i32_i16 s4, s2 ; GFX9-NEXT: s_sext_i32_i16 s4, s2
; GFX9-NEXT: v_cvt_f32_i32_e32 v2, s4 ; GFX9-NEXT: v_cvt_f32_i32_e32 v2, s4
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v2 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v2
; GFX9-NEXT: BB6_1: ; %bb3 ; GFX9-NEXT: .LBB6_1: ; %bb3
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_bfe_i32 v5, v4, 0, 16 ; GFX9-NEXT: v_bfe_i32 v5, v4, 0, 16
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v4 ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v4
; GFX9-NEXT: v_cvt_f32_i32_e32 v9, v5 ; GFX9-NEXT: v_cvt_f32_i32_e32 v9, v5
; GFX9-NEXT: v_xor_b32_e32 v8, s4, v5 ; GFX9-NEXT: v_xor_b32_e32 v8, s4, v5
; GFX9-NEXT: v_lshlrev_b64 v[5:6], 1, v[0:1] ; GFX9-NEXT: v_lshlrev_b64 v[5:6], 1, v[0:1]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v7, s3 ; GFX9-NEXT: v_mov_b32_e32 v7, s3
; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], s2, v5 ; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], s2, v5
; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1]
; GFX9-NEXT: v_mul_f32_e32 v7, v9, v3 ; GFX9-NEXT: v_mul_f32_e32 v7, v9, v3
; GFX9-NEXT: v_trunc_f32_e32 v7, v7 ; GFX9-NEXT: v_trunc_f32_e32 v7, v7
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 30, v8 ; GFX9-NEXT: v_ashrrev_i32_e32 v0, 30, v8
; GFX9-NEXT: v_cvt_i32_f32_e32 v8, v7 ; GFX9-NEXT: v_cvt_i32_f32_e32 v8, v7
; GFX9-NEXT: v_mad_f32 v7, -v7, v2, v9 ; GFX9-NEXT: v_mad_f32 v7, -v7, v2, v9
; GFX9-NEXT: v_add_u16_e32 v4, 1, v4 ; GFX9-NEXT: v_add_u16_e32 v4, 1, v4
; GFX9-NEXT: v_or_b32_e32 v0, 1, v0 ; GFX9-NEXT: v_or_b32_e32 v0, 1, v0
; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v7|, |v2| ; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v7|, |v2|
; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, s5, v4 ; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, s5, v4
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[0:1]
; GFX9-NEXT: s_and_b64 vcc, exec, vcc ; GFX9-NEXT: s_and_b64 vcc, exec, vcc
; GFX9-NEXT: v_add_u32_e32 v0, v8, v0 ; GFX9-NEXT: v_add_u32_e32 v0, v8, v0
; GFX9-NEXT: global_store_short v[5:6], v0, off ; GFX9-NEXT: global_store_short v[5:6], v0, off
; GFX9-NEXT: s_cbranch_vccz BB6_1 ; GFX9-NEXT: s_cbranch_vccz .LBB6_1
; GFX9-NEXT: ; %bb.2: ; %bb2 ; GFX9-NEXT: ; %bb.2: ; %bb2
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: sdiv16_invariant_denom: ; GFX10-LABEL: sdiv16_invariant_denom:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c ; GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_sext_i32_i16 s4, s4 ; GFX10-NEXT: s_sext_i32_i16 s4, s4
; GFX10-NEXT: v_cvt_f32_i32_e32 v2, s4 ; GFX10-NEXT: v_cvt_f32_i32_e32 v2, s4
; GFX10-NEXT: v_rcp_iflag_f32_e32 v3, v2 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v3, v2
; GFX10-NEXT: BB6_1: ; %bb3 ; GFX10-NEXT: .LBB6_1: ; %bb3
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_bfe_i32 v5, v4, 0, 16 ; GFX10-NEXT: v_bfe_i32 v5, v4, 0, 16
; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v4 ; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v4
; GFX10-NEXT: v_add_nc_u16 v4, v4, 1 ; GFX10-NEXT: v_add_nc_u16 v4, v4, 1
; GFX10-NEXT: v_cvt_f32_i32_e32 v7, v5 ; GFX10-NEXT: v_cvt_f32_i32_e32 v7, v5
; GFX10-NEXT: v_xor_b32_e32 v8, s4, v5 ; GFX10-NEXT: v_xor_b32_e32 v8, s4, v5
; GFX10-NEXT: v_lshlrev_b64 v[5:6], 1, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[5:6], 1, v[0:1]
; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x400, v4 ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x400, v4
; GFX10-NEXT: v_mul_f32_e32 v0, v7, v3 ; GFX10-NEXT: v_mul_f32_e32 v0, v7, v3
; GFX10-NEXT: v_ashrrev_i32_e32 v8, 30, v8 ; GFX10-NEXT: v_ashrrev_i32_e32 v8, 30, v8
; GFX10-NEXT: v_add_co_u32 v5, s0, s2, v5 ; GFX10-NEXT: v_add_co_u32 v5, s0, s2, v5
; GFX10-NEXT: v_trunc_f32_e32 v0, v0 ; GFX10-NEXT: v_trunc_f32_e32 v0, v0
; GFX10-NEXT: v_or_b32_e32 v8, 1, v8 ; GFX10-NEXT: v_or_b32_e32 v8, 1, v8
; GFX10-NEXT: v_add_co_ci_u32_e64 v6, s0, s3, v6, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, vcc_lo ; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, vcc_lo
; GFX10-NEXT: v_mad_f32 v7, -v0, v2, v7 ; GFX10-NEXT: v_mad_f32 v7, -v0, v2, v7
; GFX10-NEXT: v_cvt_i32_f32_e32 v0, v0 ; GFX10-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX10-NEXT: v_cmp_ge_f32_e64 s1, |v7|, |v2| ; GFX10-NEXT: v_cmp_ge_f32_e64 s1, |v7|, |v2|
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, v8, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, v8, s1
; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v7 ; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v7
; GFX10-NEXT: global_store_short v[5:6], v0, off ; GFX10-NEXT: global_store_short v[5:6], v0, off
; GFX10-NEXT: s_cbranch_vccz BB6_1 ; GFX10-NEXT: s_cbranch_vccz .LBB6_1
; GFX10-NEXT: ; %bb.2: ; %bb2 ; GFX10-NEXT: ; %bb.2: ; %bb2
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
bb: bb:
br label %bb3 br label %bb3
bb2: ; preds = %bb3 bb2: ; preds = %bb3
ret void ret void
Show All 15 Lines
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: s_movk_i32 s7, 0x400 ; GFX9-NEXT: s_movk_i32 s7, 0x400
; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_sext_i32_i16 s6, s2 ; GFX9-NEXT: s_sext_i32_i16 s6, s2
; GFX9-NEXT: v_cvt_f32_i32_e32 v2, s6 ; GFX9-NEXT: v_cvt_f32_i32_e32 v2, s6
; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v2 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v2
; GFX9-NEXT: BB7_1: ; %bb3 ; GFX9-NEXT: .LBB7_1: ; %bb3
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_bfe_i32 v7, v4, 0, 16 ; GFX9-NEXT: v_bfe_i32 v7, v4, 0, 16
; GFX9-NEXT: v_cvt_f32_i32_e32 v10, v7 ; GFX9-NEXT: v_cvt_f32_i32_e32 v10, v7
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v4 ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v4
; GFX9-NEXT: v_xor_b32_e32 v9, s6, v7 ; GFX9-NEXT: v_xor_b32_e32 v9, s6, v7
; GFX9-NEXT: v_lshlrev_b64 v[5:6], 1, v[0:1] ; GFX9-NEXT: v_lshlrev_b64 v[5:6], 1, v[0:1]
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 30, v9 ; GFX9-NEXT: v_ashrrev_i32_e32 v0, 30, v9
; GFX9-NEXT: v_mul_f32_e32 v9, v10, v3 ; GFX9-NEXT: v_mul_f32_e32 v9, v10, v3
; GFX9-NEXT: v_trunc_f32_e32 v9, v9 ; GFX9-NEXT: v_trunc_f32_e32 v9, v9
; GFX9-NEXT: v_cvt_i32_f32_e32 v11, v9 ; GFX9-NEXT: v_cvt_i32_f32_e32 v11, v9
; GFX9-NEXT: v_mad_f32 v9, -v9, v2, v10 ; GFX9-NEXT: v_mad_f32 v9, -v9, v2, v10
; GFX9-NEXT: v_or_b32_e32 v0, 1, v0 ; GFX9-NEXT: v_or_b32_e32 v0, 1, v0
; GFX9-NEXT: v_cmp_ge_f32_e64 s[2:3], |v9|, |v2| ; GFX9-NEXT: v_cmp_ge_f32_e64 s[2:3], |v9|, |v2|
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[2:3] ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[2:3]
; GFX9-NEXT: v_add_u32_e32 v0, v11, v0 ; GFX9-NEXT: v_add_u32_e32 v0, v11, v0
; GFX9-NEXT: v_mul_lo_u32 v0, v0, s6 ; GFX9-NEXT: v_mul_lo_u32 v0, v0, s6
; GFX9-NEXT: v_add_u16_e32 v4, 1, v4 ; GFX9-NEXT: v_add_u16_e32 v4, 1, v4
; GFX9-NEXT: v_mov_b32_e32 v8, s5 ; GFX9-NEXT: v_mov_b32_e32 v8, s5
; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, s7, v4 ; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, s7, v4
; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], s4, v5 ; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], s4, v5
; GFX9-NEXT: s_and_b64 vcc, exec, vcc ; GFX9-NEXT: s_and_b64 vcc, exec, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v8, v6, s[0:1] ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v8, v6, s[0:1]
; GFX9-NEXT: v_sub_u32_e32 v0, v7, v0 ; GFX9-NEXT: v_sub_u32_e32 v0, v7, v0
; GFX9-NEXT: global_store_short v[5:6], v0, off ; GFX9-NEXT: global_store_short v[5:6], v0, off
; GFX9-NEXT: s_cbranch_vccz BB7_1 ; GFX9-NEXT: s_cbranch_vccz .LBB7_1
; GFX9-NEXT: ; %bb.2: ; %bb2 ; GFX9-NEXT: ; %bb.2: ; %bb2
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: srem16_invariant_denom: ; GFX10-LABEL: srem16_invariant_denom:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c ; GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_sext_i32_i16 s1, s4 ; GFX10-NEXT: s_sext_i32_i16 s1, s4
; GFX10-NEXT: v_cvt_f32_i32_e32 v2, s1 ; GFX10-NEXT: v_cvt_f32_i32_e32 v2, s1
; GFX10-NEXT: v_rcp_iflag_f32_e32 v3, v2 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v3, v2
; GFX10-NEXT: BB7_1: ; %bb3 ; GFX10-NEXT: .LBB7_1: ; %bb3
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_bfe_i32 v7, v4, 0, 16 ; GFX10-NEXT: v_bfe_i32 v7, v4, 0, 16
; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v4 ; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v4
; GFX10-NEXT: v_add_nc_u16 v4, v4, 1 ; GFX10-NEXT: v_add_nc_u16 v4, v4, 1
; GFX10-NEXT: v_cvt_f32_i32_e32 v5, v7 ; GFX10-NEXT: v_cvt_f32_i32_e32 v5, v7
; GFX10-NEXT: v_xor_b32_e32 v6, s1, v7 ; GFX10-NEXT: v_xor_b32_e32 v6, s1, v7
; GFX10-NEXT: v_mul_f32_e32 v8, v5, v3 ; GFX10-NEXT: v_mul_f32_e32 v8, v5, v3
; GFX10-NEXT: v_ashrrev_i32_e32 v6, 30, v6 ; GFX10-NEXT: v_ashrrev_i32_e32 v6, 30, v6
; GFX10-NEXT: v_trunc_f32_e32 v8, v8 ; GFX10-NEXT: v_trunc_f32_e32 v8, v8
; GFX10-NEXT: v_or_b32_e32 v6, 1, v6 ; GFX10-NEXT: v_or_b32_e32 v6, 1, v6
; GFX10-NEXT: v_mad_f32 v5, -v8, v2, v5 ; GFX10-NEXT: v_mad_f32 v5, -v8, v2, v5
; GFX10-NEXT: v_cvt_i32_f32_e32 v8, v8 ; GFX10-NEXT: v_cvt_i32_f32_e32 v8, v8
; GFX10-NEXT: v_cmp_ge_f32_e64 vcc_lo, |v5|, |v2| ; GFX10-NEXT: v_cmp_ge_f32_e64 vcc_lo, |v5|, |v2|
; GFX10-NEXT: v_cndmask_b32_e32 v9, 0, v6, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v9, 0, v6, vcc_lo
; GFX10-NEXT: v_lshlrev_b64 v[5:6], 1, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[5:6], 1, v[0:1]
; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x400, v4 ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x400, v4
; GFX10-NEXT: v_add_nc_u32_e32 v0, v8, v9 ; GFX10-NEXT: v_add_nc_u32_e32 v0, v8, v9
; GFX10-NEXT: v_add_co_u32 v5, s0, s2, v5 ; GFX10-NEXT: v_add_co_u32 v5, s0, s2, v5
; GFX10-NEXT: v_add_co_ci_u32_e64 v6, s0, s3, v6, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
; GFX10-NEXT: v_mul_lo_u32 v0, v0, s1 ; GFX10-NEXT: v_mul_lo_u32 v0, v0, s1
; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, vcc_lo ; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, vcc_lo
; GFX10-NEXT: v_sub_nc_u32_e32 v0, v7, v0 ; GFX10-NEXT: v_sub_nc_u32_e32 v0, v7, v0
; GFX10-NEXT: global_store_short v[5:6], v0, off ; GFX10-NEXT: global_store_short v[5:6], v0, off
; GFX10-NEXT: s_cbranch_vccz BB7_1 ; GFX10-NEXT: s_cbranch_vccz .LBB7_1
; GFX10-NEXT: ; %bb.2: ; %bb2 ; GFX10-NEXT: ; %bb.2: ; %bb2
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
bb: bb:
br label %bb3 br label %bb3
bb2: ; preds = %bb3 bb2: ; preds = %bb3
ret void ret void
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llvm/test/CodeGen/AMDGPU/image-sample-waterfall.ll

; RUN: llc -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s ; RUN: llc -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s
declare <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) declare <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32)
; GCN-LABEL: {{^}}water_loop_rsrc: ; GCN-LABEL: {{^}}water_loop_rsrc:
; GCN: [[RSRC_LOOP:[a-zA-Z0-9_]+]]: ; =>This Inner Loop Header: Depth=1 ; GCN: [[RSRC_LOOP:.L[a-zA-Z0-9_]+]]: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: v_readfirstlane_b32 s[[SREG0:[0-9]+]], v[[VREG0:[0-9]+]] ; GCN-NEXT: v_readfirstlane_b32 s[[SREG0:[0-9]+]], v[[VREG0:[0-9]+]]
; GCN-NEXT: v_readfirstlane_b32 s[[SREG1:[0-9]+]], v[[VREG1:[0-9]+]] ; GCN-NEXT: v_readfirstlane_b32 s[[SREG1:[0-9]+]], v[[VREG1:[0-9]+]]
; GCN-NEXT: v_readfirstlane_b32 s[[SREG2:[0-9]+]], v[[VREG2:[0-9]+]] ; GCN-NEXT: v_readfirstlane_b32 s[[SREG2:[0-9]+]], v[[VREG2:[0-9]+]]
; GCN-NEXT: v_readfirstlane_b32 s[[SREG3:[0-9]+]], v[[VREG3:[0-9]+]] ; GCN-NEXT: v_readfirstlane_b32 s[[SREG3:[0-9]+]], v[[VREG3:[0-9]+]]
; GCN-NEXT: v_cmp_eq_u64_e32 [[CMP0:vcc]], s{{\[}}[[SREG0]]:[[SREG1]]{{\]}}, v{{\[}}[[VREG0]]:[[VREG1]]{{\]}} ; GCN-NEXT: v_cmp_eq_u64_e32 [[CMP0:vcc]], s{{\[}}[[SREG0]]:[[SREG1]]{{\]}}, v{{\[}}[[VREG0]]:[[VREG1]]{{\]}}
; GCN-NEXT: v_cmp_eq_u64_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[SREG2]]:[[SREG3]]{{\]}}, v{{\[}}[[VREG2]]:[[VREG3]]{{\]}} ; GCN-NEXT: v_cmp_eq_u64_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[SREG2]]:[[SREG3]]{{\]}}, v{{\[}}[[VREG2]]:[[VREG3]]{{\]}}
; GCN-NEXT: v_readfirstlane_b32 s[[SREG4:[0-9]+]], v[[VREG4:[0-9]+]] ; GCN-NEXT: v_readfirstlane_b32 s[[SREG4:[0-9]+]], v[[VREG4:[0-9]+]]
; GCN-NEXT: v_readfirstlane_b32 s[[SREG5:[0-9]+]], v[[VREG5:[0-9]+]] ; GCN-NEXT: v_readfirstlane_b32 s[[SREG5:[0-9]+]], v[[VREG5:[0-9]+]]
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main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f32(i32 1, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f32(i32 1, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
; GCN-LABEL: {{^}}water_loop_samp: ; GCN-LABEL: {{^}}water_loop_samp:
; GCN: [[SAMP_LOOP:[a-zA-Z0-9_]+]]: ; =>This Inner Loop Header: Depth=1 ; GCN: [[SAMP_LOOP:.L[a-zA-Z0-9_]+]]: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: v_readfirstlane_b32 s[[SREG0:[0-9]+]], v[[VREG0:[0-9]+]] ; GCN-NEXT: v_readfirstlane_b32 s[[SREG0:[0-9]+]], v[[VREG0:[0-9]+]]
; GCN-NEXT: v_readfirstlane_b32 s[[SREG1:[0-9]+]], v[[VREG1:[0-9]+]] ; GCN-NEXT: v_readfirstlane_b32 s[[SREG1:[0-9]+]], v[[VREG1:[0-9]+]]
; GCN-NEXT: v_readfirstlane_b32 s[[SREG2:[0-9]+]], v[[VREG2:[0-9]+]] ; GCN-NEXT: v_readfirstlane_b32 s[[SREG2:[0-9]+]], v[[VREG2:[0-9]+]]
; GCN-NEXT: v_readfirstlane_b32 s[[SREG3:[0-9]+]], v[[VREG3:[0-9]+]] ; GCN-NEXT: v_readfirstlane_b32 s[[SREG3:[0-9]+]], v[[VREG3:[0-9]+]]
; GCN-NEXT: v_cmp_eq_u64_e32 [[CMP0:vcc]], s{{\[}}[[SREG0]]:[[SREG1]]{{\]}}, v{{\[}}[[VREG0]]:[[VREG1]]{{\]}} ; GCN-NEXT: v_cmp_eq_u64_e32 [[CMP0:vcc]], s{{\[}}[[SREG0]]:[[SREG1]]{{\]}}, v{{\[}}[[VREG0]]:[[VREG1]]{{\]}}
; GCN-NEXT: v_cmp_eq_u64_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[SREG2]]:[[SREG3]]{{\]}}, v{{\[}}[[VREG2]]:[[VREG3]]{{\]}} ; GCN-NEXT: v_cmp_eq_u64_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[SREG2]]:[[SREG3]]{{\]}}, v{{\[}}[[VREG2]]:[[VREG3]]{{\]}}
; GCN-NEXT: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], [[CMP0]], [[CMP1]] ; GCN-NEXT: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], [[CMP0]], [[CMP1]]
Show All 13 Lines

llvm/test/CodeGen/AMDGPU/indirect-addressing-si-noopt.ll

Show All 20 Lines
} }
; Make sure we don't hit use of undefined register errors when expanding an ; Make sure we don't hit use of undefined register errors when expanding an
; extract with undef index. ; extract with undef index.
; CHECK-LABEL: {{^}}extract_adjacent_blocks: ; CHECK-LABEL: {{^}}extract_adjacent_blocks:
; CHECK: s_load_dword [[ARG:s[0-9]+]] ; CHECK: s_load_dword [[ARG:s[0-9]+]]
; CHECK: s_cmp_lg_u32 ; CHECK: s_cmp_lg_u32
; CHECK: s_cbranch_scc1 [[BB4:BB[0-9]+_[0-9]+]] ; CHECK: s_cbranch_scc1 [[BB4:.LBB[0-9]+_[0-9]+]]
; CHECK: buffer_load_dwordx4 ; CHECK: buffer_load_dwordx4
; CHECK: s_branch [[ENDBB:BB[0-9]+_[0-9]+]] ; CHECK: s_branch [[ENDBB:.LBB[0-9]+_[0-9]+]]
; CHECK: [[BB4]]: ; CHECK: [[BB4]]:
; CHECK: buffer_load_dwordx4 ; CHECK: buffer_load_dwordx4
; CHECK: [[ENDBB]]: ; CHECK: [[ENDBB]]:
; CHECK: buffer_store_dword ; CHECK: buffer_store_dword
; CHECK: s_endpgm ; CHECK: s_endpgm
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llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll

Show First 20 Lines • Show All 502 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @insertelement_v16f32_or_index(<16 x float> addrspace(1)* %out, <16 x float> %a, i32 %idx.in) nounwind {
%vecins = insertelement <16 x float> %a, float 5.000000e+00, i32 %idx %vecins = insertelement <16 x float> %a, float 5.000000e+00, i32 %idx
store <16 x float> %vecins, <16 x float> addrspace(1)* %out, align 64 store <16 x float> %vecins, <16 x float> addrspace(1)* %out, align 64
ret void ret void
} }
; GCN-LABEL: {{^}}broken_phi_bb: ; GCN-LABEL: {{^}}broken_phi_bb:
; GCN: v_mov_b32_e32 [[PHIREG:v[0-9]+]], 8 ; GCN: v_mov_b32_e32 [[PHIREG:v[0-9]+]], 8
; GCN: {{BB[0-9]+_[0-9]+}}: ; GCN: {{.LBB[0-9]+_[0-9]+}}:
; GCN: [[BB2:BB[0-9]+_[0-9]+]]: ; GCN: [[BB2:.LBB[0-9]+_[0-9]+]]:
; GCN: v_cmp_le_i32_e32 vcc, s{{[0-9]+}}, [[PHIREG]] ; GCN: v_cmp_le_i32_e32 vcc, s{{[0-9]+}}, [[PHIREG]]
; GCN: buffer_load_dword ; GCN: buffer_load_dword
; GCN: [[REGLOOP:BB[0-9]+_[0-9]+]]: ; GCN: [[REGLOOP:.LBB[0-9]+_[0-9]+]]:
; MOVREL: v_movreld_b32_e32 ; MOVREL: v_movreld_b32_e32
; IDXMODE: s_set_gpr_idx_on ; IDXMODE: s_set_gpr_idx_on
; IDXMODE: v_mov_b32_e32 ; IDXMODE: v_mov_b32_e32
; IDXMODE: s_set_gpr_idx_off ; IDXMODE: s_set_gpr_idx_off
; GCN: s_cbranch_execnz [[REGLOOP]] ; GCN: s_cbranch_execnz [[REGLOOP]]
Show All 30 Lines

llvm/test/CodeGen/AMDGPU/indirect-call.ll

Show First 20 Lines • Show All 418 Lines • ▼ Show 20 Lines
; GCN-NEXT: s_mov_b32 s42, s14 ; GCN-NEXT: s_mov_b32 s42, s14
; GCN-NEXT: s_mov_b32 s43, s13 ; GCN-NEXT: s_mov_b32 s43, s13
; GCN-NEXT: s_mov_b32 s44, s12 ; GCN-NEXT: s_mov_b32 s44, s12
; GCN-NEXT: s_mov_b64 s[34:35], s[10:11] ; GCN-NEXT: s_mov_b64 s[34:35], s[10:11]
; GCN-NEXT: s_mov_b64 s[36:37], s[8:9] ; GCN-NEXT: s_mov_b64 s[36:37], s[8:9]
; GCN-NEXT: s_mov_b64 s[38:39], s[6:7] ; GCN-NEXT: s_mov_b64 s[38:39], s[6:7]
; GCN-NEXT: s_mov_b64 s[40:41], s[4:5] ; GCN-NEXT: s_mov_b64 s[40:41], s[4:5]
; GCN-NEXT: s_mov_b64 s[46:47], exec ; GCN-NEXT: s_mov_b64 s[46:47], exec
; GCN-NEXT: BB2_1: ; =>This Inner Loop Header: Depth=1 ; GCN-NEXT: .LBB2_1: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: v_readfirstlane_b32 s16, v0 ; GCN-NEXT: v_readfirstlane_b32 s16, v0
; GCN-NEXT: v_readfirstlane_b32 s17, v1 ; GCN-NEXT: v_readfirstlane_b32 s17, v1
; GCN-NEXT: v_cmp_eq_u64_e32 vcc, s[16:17], v[0:1] ; GCN-NEXT: v_cmp_eq_u64_e32 vcc, s[16:17], v[0:1]
; GCN-NEXT: s_and_saveexec_b64 s[48:49], vcc ; GCN-NEXT: s_and_saveexec_b64 s[48:49], vcc
; GCN-NEXT: s_mov_b64 s[4:5], s[40:41] ; GCN-NEXT: s_mov_b64 s[4:5], s[40:41]
; GCN-NEXT: s_mov_b64 s[6:7], s[38:39] ; GCN-NEXT: s_mov_b64 s[6:7], s[38:39]
; GCN-NEXT: s_mov_b64 s[8:9], s[36:37] ; GCN-NEXT: s_mov_b64 s[8:9], s[36:37]
; GCN-NEXT: s_mov_b64 s[10:11], s[34:35] ; GCN-NEXT: s_mov_b64 s[10:11], s[34:35]
; GCN-NEXT: s_mov_b32 s12, s44 ; GCN-NEXT: s_mov_b32 s12, s44
; GCN-NEXT: s_mov_b32 s13, s43 ; GCN-NEXT: s_mov_b32 s13, s43
; GCN-NEXT: s_mov_b32 s14, s42 ; GCN-NEXT: s_mov_b32 s14, s42
; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17] ; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1
; GCN-NEXT: ; implicit-def: $vgpr31 ; GCN-NEXT: ; implicit-def: $vgpr31
; GCN-NEXT: s_xor_b64 exec, exec, s[48:49] ; GCN-NEXT: s_xor_b64 exec, exec, s[48:49]
; GCN-NEXT: s_cbranch_execnz BB2_1 ; GCN-NEXT: s_cbranch_execnz .LBB2_1
; GCN-NEXT: ; %bb.2: ; GCN-NEXT: ; %bb.2:
; GCN-NEXT: s_mov_b64 exec, s[46:47] ; GCN-NEXT: s_mov_b64 exec, s[46:47]
; GCN-NEXT: v_readlane_b32 s4, v40, 15 ; GCN-NEXT: v_readlane_b32 s4, v40, 15
; GCN-NEXT: v_readlane_b32 s5, v40, 16 ; GCN-NEXT: v_readlane_b32 s5, v40, 16
; GCN-NEXT: v_readlane_b32 s49, v40, 14 ; GCN-NEXT: v_readlane_b32 s49, v40, 14
; GCN-NEXT: v_readlane_b32 s48, v40, 13 ; GCN-NEXT: v_readlane_b32 s48, v40, 13
; GCN-NEXT: v_readlane_b32 s47, v40, 12 ; GCN-NEXT: v_readlane_b32 s47, v40, 12
; GCN-NEXT: v_readlane_b32 s46, v40, 11 ; GCN-NEXT: v_readlane_b32 s46, v40, 11
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; GISEL-NEXT: s_mov_b32 s44, s12 ; GISEL-NEXT: s_mov_b32 s44, s12
; GISEL-NEXT: s_mov_b64 s[34:35], s[10:11] ; GISEL-NEXT: s_mov_b64 s[34:35], s[10:11]
; GISEL-NEXT: s_mov_b64 s[36:37], s[8:9] ; GISEL-NEXT: s_mov_b64 s[36:37], s[8:9]
; GISEL-NEXT: s_mov_b64 s[38:39], s[6:7] ; GISEL-NEXT: s_mov_b64 s[38:39], s[6:7]
; GISEL-NEXT: s_mov_b64 s[40:41], s[4:5] ; GISEL-NEXT: s_mov_b64 s[40:41], s[4:5]
; GISEL-NEXT: v_writelane_b32 v40, s30, 15 ; GISEL-NEXT: v_writelane_b32 v40, s30, 15
; GISEL-NEXT: v_writelane_b32 v40, s31, 16 ; GISEL-NEXT: v_writelane_b32 v40, s31, 16
; GISEL-NEXT: s_mov_b64 s[46:47], exec ; GISEL-NEXT: s_mov_b64 s[46:47], exec
; GISEL-NEXT: BB2_1: ; =>This Inner Loop Header: Depth=1 ; GISEL-NEXT: .LBB2_1: ; =>This Inner Loop Header: Depth=1
; GISEL-NEXT: v_readfirstlane_b32 s16, v0 ; GISEL-NEXT: v_readfirstlane_b32 s16, v0
; GISEL-NEXT: v_readfirstlane_b32 s17, v1 ; GISEL-NEXT: v_readfirstlane_b32 s17, v1
; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, s[16:17], v[0:1] ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, s[16:17], v[0:1]
; GISEL-NEXT: s_and_saveexec_b64 s[48:49], vcc ; GISEL-NEXT: s_and_saveexec_b64 s[48:49], vcc
; GISEL-NEXT: s_mov_b64 s[4:5], s[40:41] ; GISEL-NEXT: s_mov_b64 s[4:5], s[40:41]
; GISEL-NEXT: s_mov_b64 s[6:7], s[38:39] ; GISEL-NEXT: s_mov_b64 s[6:7], s[38:39]
; GISEL-NEXT: s_mov_b64 s[8:9], s[36:37] ; GISEL-NEXT: s_mov_b64 s[8:9], s[36:37]
; GISEL-NEXT: s_mov_b64 s[10:11], s[34:35] ; GISEL-NEXT: s_mov_b64 s[10:11], s[34:35]
; GISEL-NEXT: s_mov_b32 s12, s44 ; GISEL-NEXT: s_mov_b32 s12, s44
; GISEL-NEXT: s_mov_b32 s13, s43 ; GISEL-NEXT: s_mov_b32 s13, s43
; GISEL-NEXT: s_mov_b32 s14, s42 ; GISEL-NEXT: s_mov_b32 s14, s42
; GISEL-NEXT: s_swappc_b64 s[30:31], s[16:17] ; GISEL-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1
; GISEL-NEXT: ; implicit-def: $vgpr31 ; GISEL-NEXT: ; implicit-def: $vgpr31
; GISEL-NEXT: s_xor_b64 exec, exec, s[48:49] ; GISEL-NEXT: s_xor_b64 exec, exec, s[48:49]
; GISEL-NEXT: s_cbranch_execnz BB2_1 ; GISEL-NEXT: s_cbranch_execnz .LBB2_1
; GISEL-NEXT: ; %bb.2: ; GISEL-NEXT: ; %bb.2:
; GISEL-NEXT: s_mov_b64 exec, s[46:47] ; GISEL-NEXT: s_mov_b64 exec, s[46:47]
; GISEL-NEXT: v_readlane_b32 s4, v40, 15 ; GISEL-NEXT: v_readlane_b32 s4, v40, 15
; GISEL-NEXT: v_readlane_b32 s5, v40, 16 ; GISEL-NEXT: v_readlane_b32 s5, v40, 16
; GISEL-NEXT: v_readlane_b32 s49, v40, 14 ; GISEL-NEXT: v_readlane_b32 s49, v40, 14
; GISEL-NEXT: v_readlane_b32 s48, v40, 13 ; GISEL-NEXT: v_readlane_b32 s48, v40, 13
; GISEL-NEXT: v_readlane_b32 s47, v40, 12 ; GISEL-NEXT: v_readlane_b32 s47, v40, 12
; GISEL-NEXT: v_readlane_b32 s46, v40, 11 ; GISEL-NEXT: v_readlane_b32 s46, v40, 11
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; GCN-NEXT: s_mov_b32 s43, s13 ; GCN-NEXT: s_mov_b32 s43, s13
; GCN-NEXT: s_mov_b32 s44, s12 ; GCN-NEXT: s_mov_b32 s44, s12
; GCN-NEXT: s_mov_b64 s[34:35], s[10:11] ; GCN-NEXT: s_mov_b64 s[34:35], s[10:11]
; GCN-NEXT: s_mov_b64 s[36:37], s[8:9] ; GCN-NEXT: s_mov_b64 s[36:37], s[8:9]
; GCN-NEXT: s_mov_b64 s[38:39], s[6:7] ; GCN-NEXT: s_mov_b64 s[38:39], s[6:7]
; GCN-NEXT: s_mov_b64 s[40:41], s[4:5] ; GCN-NEXT: s_mov_b64 s[40:41], s[4:5]
; GCN-NEXT: s_mov_b64 s[46:47], exec ; GCN-NEXT: s_mov_b64 s[46:47], exec
; GCN-NEXT: v_mov_b32_e32 v2, 0x7b ; GCN-NEXT: v_mov_b32_e32 v2, 0x7b
; GCN-NEXT: BB3_1: ; =>This Inner Loop Header: Depth=1 ; GCN-NEXT: .LBB3_1: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: v_readfirstlane_b32 s16, v0 ; GCN-NEXT: v_readfirstlane_b32 s16, v0
; GCN-NEXT: v_readfirstlane_b32 s17, v1 ; GCN-NEXT: v_readfirstlane_b32 s17, v1
; GCN-NEXT: v_cmp_eq_u64_e32 vcc, s[16:17], v[0:1] ; GCN-NEXT: v_cmp_eq_u64_e32 vcc, s[16:17], v[0:1]
; GCN-NEXT: s_and_saveexec_b64 s[48:49], vcc ; GCN-NEXT: s_and_saveexec_b64 s[48:49], vcc
; GCN-NEXT: s_mov_b64 s[4:5], s[40:41] ; GCN-NEXT: s_mov_b64 s[4:5], s[40:41]
; GCN-NEXT: s_mov_b64 s[6:7], s[38:39] ; GCN-NEXT: s_mov_b64 s[6:7], s[38:39]
; GCN-NEXT: s_mov_b64 s[8:9], s[36:37] ; GCN-NEXT: s_mov_b64 s[8:9], s[36:37]
; GCN-NEXT: s_mov_b64 s[10:11], s[34:35] ; GCN-NEXT: s_mov_b64 s[10:11], s[34:35]
; GCN-NEXT: s_mov_b32 s12, s44 ; GCN-NEXT: s_mov_b32 s12, s44
; GCN-NEXT: s_mov_b32 s13, s43 ; GCN-NEXT: s_mov_b32 s13, s43
; GCN-NEXT: s_mov_b32 s14, s42 ; GCN-NEXT: s_mov_b32 s14, s42
; GCN-NEXT: v_mov_b32_e32 v0, v2 ; GCN-NEXT: v_mov_b32_e32 v0, v2
; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17] ; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1
; GCN-NEXT: ; implicit-def: $vgpr31 ; GCN-NEXT: ; implicit-def: $vgpr31
; GCN-NEXT: ; implicit-def: $vgpr2 ; GCN-NEXT: ; implicit-def: $vgpr2
; GCN-NEXT: s_xor_b64 exec, exec, s[48:49] ; GCN-NEXT: s_xor_b64 exec, exec, s[48:49]
; GCN-NEXT: s_cbranch_execnz BB3_1 ; GCN-NEXT: s_cbranch_execnz .LBB3_1
; GCN-NEXT: ; %bb.2: ; GCN-NEXT: ; %bb.2:
; GCN-NEXT: s_mov_b64 exec, s[46:47] ; GCN-NEXT: s_mov_b64 exec, s[46:47]
; GCN-NEXT: v_readlane_b32 s4, v40, 15 ; GCN-NEXT: v_readlane_b32 s4, v40, 15
; GCN-NEXT: v_readlane_b32 s5, v40, 16 ; GCN-NEXT: v_readlane_b32 s5, v40, 16
; GCN-NEXT: v_readlane_b32 s49, v40, 14 ; GCN-NEXT: v_readlane_b32 s49, v40, 14
; GCN-NEXT: v_readlane_b32 s48, v40, 13 ; GCN-NEXT: v_readlane_b32 s48, v40, 13
; GCN-NEXT: v_readlane_b32 s47, v40, 12 ; GCN-NEXT: v_readlane_b32 s47, v40, 12
; GCN-NEXT: v_readlane_b32 s46, v40, 11 ; GCN-NEXT: v_readlane_b32 s46, v40, 11
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; GISEL-NEXT: s_mov_b32 s44, s12 ; GISEL-NEXT: s_mov_b32 s44, s12
; GISEL-NEXT: s_mov_b64 s[34:35], s[10:11] ; GISEL-NEXT: s_mov_b64 s[34:35], s[10:11]
; GISEL-NEXT: s_mov_b64 s[36:37], s[8:9] ; GISEL-NEXT: s_mov_b64 s[36:37], s[8:9]
; GISEL-NEXT: s_mov_b64 s[38:39], s[6:7] ; GISEL-NEXT: s_mov_b64 s[38:39], s[6:7]
; GISEL-NEXT: s_mov_b64 s[40:41], s[4:5] ; GISEL-NEXT: s_mov_b64 s[40:41], s[4:5]
; GISEL-NEXT: v_writelane_b32 v40, s30, 15 ; GISEL-NEXT: v_writelane_b32 v40, s30, 15
; GISEL-NEXT: v_writelane_b32 v40, s31, 16 ; GISEL-NEXT: v_writelane_b32 v40, s31, 16
; GISEL-NEXT: s_mov_b64 s[46:47], exec ; GISEL-NEXT: s_mov_b64 s[46:47], exec
; GISEL-NEXT: BB3_1: ; =>This Inner Loop Header: Depth=1 ; GISEL-NEXT: .LBB3_1: ; =>This Inner Loop Header: Depth=1
; GISEL-NEXT: v_readfirstlane_b32 s16, v0 ; GISEL-NEXT: v_readfirstlane_b32 s16, v0
; GISEL-NEXT: v_readfirstlane_b32 s17, v1 ; GISEL-NEXT: v_readfirstlane_b32 s17, v1
; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, s[16:17], v[0:1] ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, s[16:17], v[0:1]
; GISEL-NEXT: s_and_saveexec_b64 s[48:49], vcc ; GISEL-NEXT: s_and_saveexec_b64 s[48:49], vcc
; GISEL-NEXT: v_mov_b32_e32 v0, 0x7b ; GISEL-NEXT: v_mov_b32_e32 v0, 0x7b
; GISEL-NEXT: s_mov_b64 s[4:5], s[40:41] ; GISEL-NEXT: s_mov_b64 s[4:5], s[40:41]
; GISEL-NEXT: s_mov_b64 s[6:7], s[38:39] ; GISEL-NEXT: s_mov_b64 s[6:7], s[38:39]
; GISEL-NEXT: s_mov_b64 s[8:9], s[36:37] ; GISEL-NEXT: s_mov_b64 s[8:9], s[36:37]
; GISEL-NEXT: s_mov_b64 s[10:11], s[34:35] ; GISEL-NEXT: s_mov_b64 s[10:11], s[34:35]
; GISEL-NEXT: s_mov_b32 s12, s44 ; GISEL-NEXT: s_mov_b32 s12, s44
; GISEL-NEXT: s_mov_b32 s13, s43 ; GISEL-NEXT: s_mov_b32 s13, s43
; GISEL-NEXT: s_mov_b32 s14, s42 ; GISEL-NEXT: s_mov_b32 s14, s42
; GISEL-NEXT: s_swappc_b64 s[30:31], s[16:17] ; GISEL-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1
; GISEL-NEXT: ; implicit-def: $vgpr31 ; GISEL-NEXT: ; implicit-def: $vgpr31
; GISEL-NEXT: s_xor_b64 exec, exec, s[48:49] ; GISEL-NEXT: s_xor_b64 exec, exec, s[48:49]
; GISEL-NEXT: s_cbranch_execnz BB3_1 ; GISEL-NEXT: s_cbranch_execnz .LBB3_1
; GISEL-NEXT: ; %bb.2: ; GISEL-NEXT: ; %bb.2:
; GISEL-NEXT: s_mov_b64 exec, s[46:47] ; GISEL-NEXT: s_mov_b64 exec, s[46:47]
; GISEL-NEXT: v_readlane_b32 s4, v40, 15 ; GISEL-NEXT: v_readlane_b32 s4, v40, 15
; GISEL-NEXT: v_readlane_b32 s5, v40, 16 ; GISEL-NEXT: v_readlane_b32 s5, v40, 16
; GISEL-NEXT: v_readlane_b32 s49, v40, 14 ; GISEL-NEXT: v_readlane_b32 s49, v40, 14
; GISEL-NEXT: v_readlane_b32 s48, v40, 13 ; GISEL-NEXT: v_readlane_b32 s48, v40, 13
; GISEL-NEXT: v_readlane_b32 s47, v40, 12 ; GISEL-NEXT: v_readlane_b32 s47, v40, 12
; GISEL-NEXT: v_readlane_b32 s46, v40, 11 ; GISEL-NEXT: v_readlane_b32 s46, v40, 11
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
; GCN-NEXT: s_mov_b32 s42, s14 ; GCN-NEXT: s_mov_b32 s42, s14
; GCN-NEXT: s_mov_b32 s43, s13 ; GCN-NEXT: s_mov_b32 s43, s13
; GCN-NEXT: s_mov_b32 s44, s12 ; GCN-NEXT: s_mov_b32 s44, s12
; GCN-NEXT: s_mov_b64 s[34:35], s[10:11] ; GCN-NEXT: s_mov_b64 s[34:35], s[10:11]
; GCN-NEXT: s_mov_b64 s[36:37], s[8:9] ; GCN-NEXT: s_mov_b64 s[36:37], s[8:9]
; GCN-NEXT: s_mov_b64 s[38:39], s[6:7] ; GCN-NEXT: s_mov_b64 s[38:39], s[6:7]
; GCN-NEXT: s_mov_b64 s[40:41], s[4:5] ; GCN-NEXT: s_mov_b64 s[40:41], s[4:5]
; GCN-NEXT: s_mov_b64 s[46:47], exec ; GCN-NEXT: s_mov_b64 s[46:47], exec
; GCN-NEXT: BB4_1: ; =>This Inner Loop Header: Depth=1 ; GCN-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: v_readfirstlane_b32 s16, v0 ; GCN-NEXT: v_readfirstlane_b32 s16, v0
; GCN-NEXT: v_readfirstlane_b32 s17, v1 ; GCN-NEXT: v_readfirstlane_b32 s17, v1
; GCN-NEXT: v_cmp_eq_u64_e32 vcc, s[16:17], v[0:1] ; GCN-NEXT: v_cmp_eq_u64_e32 vcc, s[16:17], v[0:1]
; GCN-NEXT: s_and_saveexec_b64 s[48:49], vcc ; GCN-NEXT: s_and_saveexec_b64 s[48:49], vcc
; GCN-NEXT: s_mov_b64 s[4:5], s[40:41] ; GCN-NEXT: s_mov_b64 s[4:5], s[40:41]
; GCN-NEXT: s_mov_b64 s[6:7], s[38:39] ; GCN-NEXT: s_mov_b64 s[6:7], s[38:39]
; GCN-NEXT: s_mov_b64 s[8:9], s[36:37] ; GCN-NEXT: s_mov_b64 s[8:9], s[36:37]
; GCN-NEXT: s_mov_b64 s[10:11], s[34:35] ; GCN-NEXT: s_mov_b64 s[10:11], s[34:35]
; GCN-NEXT: s_mov_b32 s12, s44 ; GCN-NEXT: s_mov_b32 s12, s44
; GCN-NEXT: s_mov_b32 s13, s43 ; GCN-NEXT: s_mov_b32 s13, s43
; GCN-NEXT: s_mov_b32 s14, s42 ; GCN-NEXT: s_mov_b32 s14, s42
; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17] ; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GCN-NEXT: v_mov_b32_e32 v2, v0 ; GCN-NEXT: v_mov_b32_e32 v2, v0
; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1
; GCN-NEXT: ; implicit-def: $vgpr31 ; GCN-NEXT: ; implicit-def: $vgpr31
; GCN-NEXT: s_xor_b64 exec, exec, s[48:49] ; GCN-NEXT: s_xor_b64 exec, exec, s[48:49]
; GCN-NEXT: s_cbranch_execnz BB4_1 ; GCN-NEXT: s_cbranch_execnz .LBB4_1
; GCN-NEXT: ; %bb.2: ; GCN-NEXT: ; %bb.2:
; GCN-NEXT: s_mov_b64 exec, s[46:47] ; GCN-NEXT: s_mov_b64 exec, s[46:47]
; GCN-NEXT: v_add_i32_e32 v0, vcc, 1, v2 ; GCN-NEXT: v_add_i32_e32 v0, vcc, 1, v2
; GCN-NEXT: v_readlane_b32 s4, v40, 15 ; GCN-NEXT: v_readlane_b32 s4, v40, 15
; GCN-NEXT: v_readlane_b32 s5, v40, 16 ; GCN-NEXT: v_readlane_b32 s5, v40, 16
; GCN-NEXT: v_readlane_b32 s49, v40, 14 ; GCN-NEXT: v_readlane_b32 s49, v40, 14
; GCN-NEXT: v_readlane_b32 s48, v40, 13 ; GCN-NEXT: v_readlane_b32 s48, v40, 13
; GCN-NEXT: v_readlane_b32 s47, v40, 12 ; GCN-NEXT: v_readlane_b32 s47, v40, 12
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; GISEL-NEXT: s_mov_b32 s44, s12 ; GISEL-NEXT: s_mov_b32 s44, s12
; GISEL-NEXT: s_mov_b64 s[34:35], s[10:11] ; GISEL-NEXT: s_mov_b64 s[34:35], s[10:11]
; GISEL-NEXT: s_mov_b64 s[36:37], s[8:9] ; GISEL-NEXT: s_mov_b64 s[36:37], s[8:9]
; GISEL-NEXT: s_mov_b64 s[38:39], s[6:7] ; GISEL-NEXT: s_mov_b64 s[38:39], s[6:7]
; GISEL-NEXT: s_mov_b64 s[40:41], s[4:5] ; GISEL-NEXT: s_mov_b64 s[40:41], s[4:5]
; GISEL-NEXT: v_writelane_b32 v40, s30, 15 ; GISEL-NEXT: v_writelane_b32 v40, s30, 15
; GISEL-NEXT: v_writelane_b32 v40, s31, 16 ; GISEL-NEXT: v_writelane_b32 v40, s31, 16
; GISEL-NEXT: s_mov_b64 s[46:47], exec ; GISEL-NEXT: s_mov_b64 s[46:47], exec
; GISEL-NEXT: BB4_1: ; =>This Inner Loop Header: Depth=1 ; GISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
; GISEL-NEXT: v_readfirstlane_b32 s16, v0 ; GISEL-NEXT: v_readfirstlane_b32 s16, v0
; GISEL-NEXT: v_readfirstlane_b32 s17, v1 ; GISEL-NEXT: v_readfirstlane_b32 s17, v1
; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, s[16:17], v[0:1] ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, s[16:17], v[0:1]
; GISEL-NEXT: s_and_saveexec_b64 s[48:49], vcc ; GISEL-NEXT: s_and_saveexec_b64 s[48:49], vcc
; GISEL-NEXT: s_mov_b64 s[4:5], s[40:41] ; GISEL-NEXT: s_mov_b64 s[4:5], s[40:41]
; GISEL-NEXT: s_mov_b64 s[6:7], s[38:39] ; GISEL-NEXT: s_mov_b64 s[6:7], s[38:39]
; GISEL-NEXT: s_mov_b64 s[8:9], s[36:37] ; GISEL-NEXT: s_mov_b64 s[8:9], s[36:37]
; GISEL-NEXT: s_mov_b64 s[10:11], s[34:35] ; GISEL-NEXT: s_mov_b64 s[10:11], s[34:35]
; GISEL-NEXT: s_mov_b32 s12, s44 ; GISEL-NEXT: s_mov_b32 s12, s44
; GISEL-NEXT: s_mov_b32 s13, s43 ; GISEL-NEXT: s_mov_b32 s13, s43
; GISEL-NEXT: s_mov_b32 s14, s42 ; GISEL-NEXT: s_mov_b32 s14, s42
; GISEL-NEXT: s_swappc_b64 s[30:31], s[16:17] ; GISEL-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GISEL-NEXT: v_mov_b32_e32 v2, v0 ; GISEL-NEXT: v_mov_b32_e32 v2, v0
; GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1
; GISEL-NEXT: ; implicit-def: $vgpr31 ; GISEL-NEXT: ; implicit-def: $vgpr31
; GISEL-NEXT: s_xor_b64 exec, exec, s[48:49] ; GISEL-NEXT: s_xor_b64 exec, exec, s[48:49]
; GISEL-NEXT: s_cbranch_execnz BB4_1 ; GISEL-NEXT: s_cbranch_execnz .LBB4_1
; GISEL-NEXT: ; %bb.2: ; GISEL-NEXT: ; %bb.2:
; GISEL-NEXT: s_mov_b64 exec, s[46:47] ; GISEL-NEXT: s_mov_b64 exec, s[46:47]
; GISEL-NEXT: v_add_i32_e32 v0, vcc, 1, v2 ; GISEL-NEXT: v_add_i32_e32 v0, vcc, 1, v2
; GISEL-NEXT: v_readlane_b32 s4, v40, 15 ; GISEL-NEXT: v_readlane_b32 s4, v40, 15
; GISEL-NEXT: v_readlane_b32 s5, v40, 16 ; GISEL-NEXT: v_readlane_b32 s5, v40, 16
; GISEL-NEXT: v_readlane_b32 s49, v40, 14 ; GISEL-NEXT: v_readlane_b32 s49, v40, 14
; GISEL-NEXT: v_readlane_b32 s48, v40, 13 ; GISEL-NEXT: v_readlane_b32 s48, v40, 13
; GISEL-NEXT: v_readlane_b32 s47, v40, 12 ; GISEL-NEXT: v_readlane_b32 s47, v40, 12
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; GCN-NEXT: s_mov_b32 s44, s12 ; GCN-NEXT: s_mov_b32 s44, s12
; GCN-NEXT: s_mov_b64 s[34:35], s[10:11] ; GCN-NEXT: s_mov_b64 s[34:35], s[10:11]
; GCN-NEXT: s_mov_b64 s[36:37], s[8:9] ; GCN-NEXT: s_mov_b64 s[36:37], s[8:9]
; GCN-NEXT: s_mov_b64 s[38:39], s[6:7] ; GCN-NEXT: s_mov_b64 s[38:39], s[6:7]
; GCN-NEXT: s_mov_b64 s[40:41], s[4:5] ; GCN-NEXT: s_mov_b64 s[40:41], s[4:5]
; GCN-NEXT: v_and_b32_e32 v2, 1, v2 ; GCN-NEXT: v_and_b32_e32 v2, 1, v2
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
; GCN-NEXT: s_and_saveexec_b64 s[46:47], vcc ; GCN-NEXT: s_and_saveexec_b64 s[46:47], vcc
; GCN-NEXT: s_cbranch_execz BB5_4 ; GCN-NEXT: s_cbranch_execz .LBB5_4
; GCN-NEXT: ; %bb.1: ; %bb1 ; GCN-NEXT: ; %bb.1: ; %bb1
; GCN-NEXT: v_writelane_b32 v40, s30, 17 ; GCN-NEXT: v_writelane_b32 v40, s30, 17
; GCN-NEXT: v_writelane_b32 v40, s31, 18 ; GCN-NEXT: v_writelane_b32 v40, s31, 18
; GCN-NEXT: s_mov_b64 s[48:49], exec ; GCN-NEXT: s_mov_b64 s[48:49], exec
; GCN-NEXT: BB5_2: ; =>This Inner Loop Header: Depth=1 ; GCN-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: v_readfirstlane_b32 s16, v0 ; GCN-NEXT: v_readfirstlane_b32 s16, v0
; GCN-NEXT: v_readfirstlane_b32 s17, v1 ; GCN-NEXT: v_readfirstlane_b32 s17, v1
; GCN-NEXT: v_cmp_eq_u64_e32 vcc, s[16:17], v[0:1] ; GCN-NEXT: v_cmp_eq_u64_e32 vcc, s[16:17], v[0:1]
; GCN-NEXT: s_and_saveexec_b64 s[50:51], vcc ; GCN-NEXT: s_and_saveexec_b64 s[50:51], vcc
; GCN-NEXT: s_mov_b64 s[4:5], s[40:41] ; GCN-NEXT: s_mov_b64 s[4:5], s[40:41]
; GCN-NEXT: s_mov_b64 s[6:7], s[38:39] ; GCN-NEXT: s_mov_b64 s[6:7], s[38:39]
; GCN-NEXT: s_mov_b64 s[8:9], s[36:37] ; GCN-NEXT: s_mov_b64 s[8:9], s[36:37]
; GCN-NEXT: s_mov_b64 s[10:11], s[34:35] ; GCN-NEXT: s_mov_b64 s[10:11], s[34:35]
; GCN-NEXT: s_mov_b32 s12, s44 ; GCN-NEXT: s_mov_b32 s12, s44
; GCN-NEXT: s_mov_b32 s13, s43 ; GCN-NEXT: s_mov_b32 s13, s43
; GCN-NEXT: s_mov_b32 s14, s42 ; GCN-NEXT: s_mov_b32 s14, s42
; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17] ; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1
; GCN-NEXT: ; implicit-def: $vgpr31 ; GCN-NEXT: ; implicit-def: $vgpr31
; GCN-NEXT: s_xor_b64 exec, exec, s[50:51] ; GCN-NEXT: s_xor_b64 exec, exec, s[50:51]
; GCN-NEXT: s_cbranch_execnz BB5_2 ; GCN-NEXT: s_cbranch_execnz .LBB5_2
; GCN-NEXT: ; %bb.3: ; GCN-NEXT: ; %bb.3:
; GCN-NEXT: s_mov_b64 exec, s[48:49] ; GCN-NEXT: s_mov_b64 exec, s[48:49]
; GCN-NEXT: v_readlane_b32 s30, v40, 17 ; GCN-NEXT: v_readlane_b32 s30, v40, 17
; GCN-NEXT: v_readlane_b32 s31, v40, 18 ; GCN-NEXT: v_readlane_b32 s31, v40, 18
; GCN-NEXT: BB5_4: ; %bb2 ; GCN-NEXT: .LBB5_4: ; %bb2
; GCN-NEXT: s_or_b64 exec, exec, s[46:47] ; GCN-NEXT: s_or_b64 exec, exec, s[46:47]
; GCN-NEXT: v_readlane_b32 s51, v40, 16 ; GCN-NEXT: v_readlane_b32 s51, v40, 16
; GCN-NEXT: v_readlane_b32 s50, v40, 15 ; GCN-NEXT: v_readlane_b32 s50, v40, 15
; GCN-NEXT: v_readlane_b32 s49, v40, 14 ; GCN-NEXT: v_readlane_b32 s49, v40, 14
; GCN-NEXT: v_readlane_b32 s48, v40, 13 ; GCN-NEXT: v_readlane_b32 s48, v40, 13
; GCN-NEXT: v_readlane_b32 s47, v40, 12 ; GCN-NEXT: v_readlane_b32 s47, v40, 12
; GCN-NEXT: v_readlane_b32 s46, v40, 11 ; GCN-NEXT: v_readlane_b32 s46, v40, 11
; GCN-NEXT: v_readlane_b32 s44, v40, 10 ; GCN-NEXT: v_readlane_b32 s44, v40, 10
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; GISEL-NEXT: s_mov_b32 s44, s12 ; GISEL-NEXT: s_mov_b32 s44, s12
; GISEL-NEXT: s_mov_b64 s[34:35], s[10:11] ; GISEL-NEXT: s_mov_b64 s[34:35], s[10:11]
; GISEL-NEXT: s_mov_b64 s[36:37], s[8:9] ; GISEL-NEXT: s_mov_b64 s[36:37], s[8:9]
; GISEL-NEXT: s_mov_b64 s[38:39], s[6:7] ; GISEL-NEXT: s_mov_b64 s[38:39], s[6:7]
; GISEL-NEXT: s_mov_b64 s[40:41], s[4:5] ; GISEL-NEXT: s_mov_b64 s[40:41], s[4:5]
; GISEL-NEXT: v_and_b32_e32 v2, 1, v2 ; GISEL-NEXT: v_and_b32_e32 v2, 1, v2
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GISEL-NEXT: s_and_saveexec_b64 s[46:47], vcc ; GISEL-NEXT: s_and_saveexec_b64 s[46:47], vcc
; GISEL-NEXT: s_cbranch_execz BB5_4 ; GISEL-NEXT: s_cbranch_execz .LBB5_4
; GISEL-NEXT: ; %bb.1: ; %bb1 ; GISEL-NEXT: ; %bb.1: ; %bb1
; GISEL-NEXT: v_writelane_b32 v40, s30, 17 ; GISEL-NEXT: v_writelane_b32 v40, s30, 17
; GISEL-NEXT: v_writelane_b32 v40, s31, 18 ; GISEL-NEXT: v_writelane_b32 v40, s31, 18
; GISEL-NEXT: s_mov_b64 s[48:49], exec ; GISEL-NEXT: s_mov_b64 s[48:49], exec
; GISEL-NEXT: BB5_2: ; =>This Inner Loop Header: Depth=1 ; GISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
; GISEL-NEXT: v_readfirstlane_b32 s16, v0 ; GISEL-NEXT: v_readfirstlane_b32 s16, v0
; GISEL-NEXT: v_readfirstlane_b32 s17, v1 ; GISEL-NEXT: v_readfirstlane_b32 s17, v1
; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, s[16:17], v[0:1] ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, s[16:17], v[0:1]
; GISEL-NEXT: s_and_saveexec_b64 s[50:51], vcc ; GISEL-NEXT: s_and_saveexec_b64 s[50:51], vcc
; GISEL-NEXT: s_mov_b64 s[4:5], s[40:41] ; GISEL-NEXT: s_mov_b64 s[4:5], s[40:41]
; GISEL-NEXT: s_mov_b64 s[6:7], s[38:39] ; GISEL-NEXT: s_mov_b64 s[6:7], s[38:39]
; GISEL-NEXT: s_mov_b64 s[8:9], s[36:37] ; GISEL-NEXT: s_mov_b64 s[8:9], s[36:37]
; GISEL-NEXT: s_mov_b64 s[10:11], s[34:35] ; GISEL-NEXT: s_mov_b64 s[10:11], s[34:35]
; GISEL-NEXT: s_mov_b32 s12, s44 ; GISEL-NEXT: s_mov_b32 s12, s44
; GISEL-NEXT: s_mov_b32 s13, s43 ; GISEL-NEXT: s_mov_b32 s13, s43
; GISEL-NEXT: s_mov_b32 s14, s42 ; GISEL-NEXT: s_mov_b32 s14, s42
; GISEL-NEXT: s_swappc_b64 s[30:31], s[16:17] ; GISEL-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1
; GISEL-NEXT: ; implicit-def: $vgpr31 ; GISEL-NEXT: ; implicit-def: $vgpr31
; GISEL-NEXT: s_xor_b64 exec, exec, s[50:51] ; GISEL-NEXT: s_xor_b64 exec, exec, s[50:51]
; GISEL-NEXT: s_cbranch_execnz BB5_2 ; GISEL-NEXT: s_cbranch_execnz .LBB5_2
; GISEL-NEXT: ; %bb.3: ; GISEL-NEXT: ; %bb.3:
; GISEL-NEXT: s_mov_b64 exec, s[48:49] ; GISEL-NEXT: s_mov_b64 exec, s[48:49]
; GISEL-NEXT: v_readlane_b32 s30, v40, 17 ; GISEL-NEXT: v_readlane_b32 s30, v40, 17
; GISEL-NEXT: v_readlane_b32 s31, v40, 18 ; GISEL-NEXT: v_readlane_b32 s31, v40, 18
; GISEL-NEXT: BB5_4: ; %bb2 ; GISEL-NEXT: .LBB5_4: ; %bb2
; GISEL-NEXT: s_or_b64 exec, exec, s[46:47] ; GISEL-NEXT: s_or_b64 exec, exec, s[46:47]
; GISEL-NEXT: v_readlane_b32 s51, v40, 16 ; GISEL-NEXT: v_readlane_b32 s51, v40, 16
; GISEL-NEXT: v_readlane_b32 s50, v40, 15 ; GISEL-NEXT: v_readlane_b32 s50, v40, 15
; GISEL-NEXT: v_readlane_b32 s49, v40, 14 ; GISEL-NEXT: v_readlane_b32 s49, v40, 14
; GISEL-NEXT: v_readlane_b32 s48, v40, 13 ; GISEL-NEXT: v_readlane_b32 s48, v40, 13
; GISEL-NEXT: v_readlane_b32 s47, v40, 12 ; GISEL-NEXT: v_readlane_b32 s47, v40, 12
; GISEL-NEXT: v_readlane_b32 s46, v40, 11 ; GISEL-NEXT: v_readlane_b32 s46, v40, 11
; GISEL-NEXT: v_readlane_b32 s44, v40, 10 ; GISEL-NEXT: v_readlane_b32 s44, v40, 10
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_writelane_b32 v40, s59, 25 ; GCN-NEXT: v_writelane_b32 v40, s59, 25
; GCN-NEXT: v_writelane_b32 v40, s60, 26 ; GCN-NEXT: v_writelane_b32 v40, s60, 26
; GCN-NEXT: v_writelane_b32 v40, s61, 27 ; GCN-NEXT: v_writelane_b32 v40, s61, 27
; GCN-NEXT: v_writelane_b32 v40, s62, 28 ; GCN-NEXT: v_writelane_b32 v40, s62, 28
; GCN-NEXT: v_writelane_b32 v40, s63, 29 ; GCN-NEXT: v_writelane_b32 v40, s63, 29
; GCN-NEXT: s_mov_b64 s[6:7], s[30:31] ; GCN-NEXT: s_mov_b64 s[6:7], s[30:31]
; GCN-NEXT: s_mov_b64 s[8:9], exec ; GCN-NEXT: s_mov_b64 s[8:9], exec
; GCN-NEXT: s_movk_i32 s4, 0x7b ; GCN-NEXT: s_movk_i32 s4, 0x7b
; GCN-NEXT: BB6_1: ; =>This Inner Loop Header: Depth=1 ; GCN-NEXT: .LBB6_1: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: v_readfirstlane_b32 s12, v0 ; GCN-NEXT: v_readfirstlane_b32 s12, v0
; GCN-NEXT: v_readfirstlane_b32 s13, v1 ; GCN-NEXT: v_readfirstlane_b32 s13, v1
; GCN-NEXT: v_cmp_eq_u64_e32 vcc, s[12:13], v[0:1] ; GCN-NEXT: v_cmp_eq_u64_e32 vcc, s[12:13], v[0:1]
; GCN-NEXT: s_and_saveexec_b64 s[10:11], vcc ; GCN-NEXT: s_and_saveexec_b64 s[10:11], vcc
; GCN-NEXT: s_swappc_b64 s[30:31], s[12:13] ; GCN-NEXT: s_swappc_b64 s[30:31], s[12:13]
; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1
; GCN-NEXT: s_xor_b64 exec, exec, s[10:11] ; GCN-NEXT: s_xor_b64 exec, exec, s[10:11]
; GCN-NEXT: s_cbranch_execnz BB6_1 ; GCN-NEXT: s_cbranch_execnz .LBB6_1
; GCN-NEXT: ; %bb.2: ; GCN-NEXT: ; %bb.2:
; GCN-NEXT: s_mov_b64 exec, s[8:9] ; GCN-NEXT: s_mov_b64 exec, s[8:9]
; GCN-NEXT: v_readlane_b32 s63, v40, 29 ; GCN-NEXT: v_readlane_b32 s63, v40, 29
; GCN-NEXT: v_readlane_b32 s62, v40, 28 ; GCN-NEXT: v_readlane_b32 s62, v40, 28
; GCN-NEXT: v_readlane_b32 s61, v40, 27 ; GCN-NEXT: v_readlane_b32 s61, v40, 27
; GCN-NEXT: v_readlane_b32 s60, v40, 26 ; GCN-NEXT: v_readlane_b32 s60, v40, 26
; GCN-NEXT: v_readlane_b32 s59, v40, 25 ; GCN-NEXT: v_readlane_b32 s59, v40, 25
; GCN-NEXT: v_readlane_b32 s58, v40, 24 ; GCN-NEXT: v_readlane_b32 s58, v40, 24
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
; GISEL-NEXT: v_writelane_b32 v40, s59, 25 ; GISEL-NEXT: v_writelane_b32 v40, s59, 25
; GISEL-NEXT: v_writelane_b32 v40, s60, 26 ; GISEL-NEXT: v_writelane_b32 v40, s60, 26
; GISEL-NEXT: v_writelane_b32 v40, s61, 27 ; GISEL-NEXT: v_writelane_b32 v40, s61, 27
; GISEL-NEXT: v_writelane_b32 v40, s62, 28 ; GISEL-NEXT: v_writelane_b32 v40, s62, 28
; GISEL-NEXT: v_writelane_b32 v40, s63, 29 ; GISEL-NEXT: v_writelane_b32 v40, s63, 29
; GISEL-NEXT: s_mov_b64 s[6:7], s[30:31] ; GISEL-NEXT: s_mov_b64 s[6:7], s[30:31]
; GISEL-NEXT: s_movk_i32 s4, 0x7b ; GISEL-NEXT: s_movk_i32 s4, 0x7b
; GISEL-NEXT: s_mov_b64 s[8:9], exec ; GISEL-NEXT: s_mov_b64 s[8:9], exec
; GISEL-NEXT: BB6_1: ; =>This Inner Loop Header: Depth=1 ; GISEL-NEXT: .LBB6_1: ; =>This Inner Loop Header: Depth=1
; GISEL-NEXT: v_readfirstlane_b32 s10, v0 ; GISEL-NEXT: v_readfirstlane_b32 s10, v0
; GISEL-NEXT: v_readfirstlane_b32 s11, v1 ; GISEL-NEXT: v_readfirstlane_b32 s11, v1
; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, s[10:11], v[0:1] ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, s[10:11], v[0:1]
; GISEL-NEXT: s_and_saveexec_b64 s[12:13], vcc ; GISEL-NEXT: s_and_saveexec_b64 s[12:13], vcc
; GISEL-NEXT: s_swappc_b64 s[30:31], s[10:11] ; GISEL-NEXT: s_swappc_b64 s[30:31], s[10:11]
; GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1
; GISEL-NEXT: s_xor_b64 exec, exec, s[12:13] ; GISEL-NEXT: s_xor_b64 exec, exec, s[12:13]
; GISEL-NEXT: s_cbranch_execnz BB6_1 ; GISEL-NEXT: s_cbranch_execnz .LBB6_1
; GISEL-NEXT: ; %bb.2: ; GISEL-NEXT: ; %bb.2:
; GISEL-NEXT: s_mov_b64 exec, s[8:9] ; GISEL-NEXT: s_mov_b64 exec, s[8:9]
; GISEL-NEXT: v_readlane_b32 s63, v40, 29 ; GISEL-NEXT: v_readlane_b32 s63, v40, 29
; GISEL-NEXT: v_readlane_b32 s62, v40, 28 ; GISEL-NEXT: v_readlane_b32 s62, v40, 28
; GISEL-NEXT: v_readlane_b32 s61, v40, 27 ; GISEL-NEXT: v_readlane_b32 s61, v40, 27
; GISEL-NEXT: v_readlane_b32 s60, v40, 26 ; GISEL-NEXT: v_readlane_b32 s60, v40, 26
; GISEL-NEXT: v_readlane_b32 s59, v40, 25 ; GISEL-NEXT: v_readlane_b32 s59, v40, 25
; GISEL-NEXT: v_readlane_b32 s58, v40, 24 ; GISEL-NEXT: v_readlane_b32 s58, v40, 24
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_writelane_b32 v40, s59, 25 ; GCN-NEXT: v_writelane_b32 v40, s59, 25
; GCN-NEXT: v_writelane_b32 v40, s60, 26 ; GCN-NEXT: v_writelane_b32 v40, s60, 26
; GCN-NEXT: v_writelane_b32 v40, s61, 27 ; GCN-NEXT: v_writelane_b32 v40, s61, 27
; GCN-NEXT: v_writelane_b32 v40, s62, 28 ; GCN-NEXT: v_writelane_b32 v40, s62, 28
; GCN-NEXT: v_writelane_b32 v40, s63, 29 ; GCN-NEXT: v_writelane_b32 v40, s63, 29
; GCN-NEXT: s_mov_b64 s[4:5], s[30:31] ; GCN-NEXT: s_mov_b64 s[4:5], s[30:31]
; GCN-NEXT: v_mov_b32_e32 v41, v0 ; GCN-NEXT: v_mov_b32_e32 v41, v0
; GCN-NEXT: s_mov_b64 s[6:7], exec ; GCN-NEXT: s_mov_b64 s[6:7], exec
; GCN-NEXT: BB7_1: ; =>This Inner Loop Header: Depth=1 ; GCN-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: v_readfirstlane_b32 s10, v1 ; GCN-NEXT: v_readfirstlane_b32 s10, v1
; GCN-NEXT: v_readfirstlane_b32 s11, v2 ; GCN-NEXT: v_readfirstlane_b32 s11, v2
; GCN-NEXT: v_cmp_eq_u64_e32 vcc, s[10:11], v[1:2] ; GCN-NEXT: v_cmp_eq_u64_e32 vcc, s[10:11], v[1:2]
; GCN-NEXT: s_and_saveexec_b64 s[8:9], vcc ; GCN-NEXT: s_and_saveexec_b64 s[8:9], vcc
; GCN-NEXT: v_mov_b32_e32 v0, v41 ; GCN-NEXT: v_mov_b32_e32 v0, v41
; GCN-NEXT: s_swappc_b64 s[30:31], s[10:11] ; GCN-NEXT: s_swappc_b64 s[30:31], s[10:11]
; GCN-NEXT: ; implicit-def: $vgpr1_vgpr2 ; GCN-NEXT: ; implicit-def: $vgpr1_vgpr2
; GCN-NEXT: s_xor_b64 exec, exec, s[8:9] ; GCN-NEXT: s_xor_b64 exec, exec, s[8:9]
; GCN-NEXT: s_cbranch_execnz BB7_1 ; GCN-NEXT: s_cbranch_execnz .LBB7_1
; GCN-NEXT: ; %bb.2: ; GCN-NEXT: ; %bb.2:
; GCN-NEXT: s_mov_b64 exec, s[6:7] ; GCN-NEXT: s_mov_b64 exec, s[6:7]
; GCN-NEXT: v_mov_b32_e32 v0, v41 ; GCN-NEXT: v_mov_b32_e32 v0, v41
; GCN-NEXT: v_readlane_b32 s63, v40, 29 ; GCN-NEXT: v_readlane_b32 s63, v40, 29
; GCN-NEXT: v_readlane_b32 s62, v40, 28 ; GCN-NEXT: v_readlane_b32 s62, v40, 28
; GCN-NEXT: v_readlane_b32 s61, v40, 27 ; GCN-NEXT: v_readlane_b32 s61, v40, 27
; GCN-NEXT: v_readlane_b32 s60, v40, 26 ; GCN-NEXT: v_readlane_b32 s60, v40, 26
; GCN-NEXT: v_readlane_b32 s59, v40, 25 ; GCN-NEXT: v_readlane_b32 s59, v40, 25
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines
; GISEL-NEXT: v_writelane_b32 v40, s59, 25 ; GISEL-NEXT: v_writelane_b32 v40, s59, 25
; GISEL-NEXT: v_writelane_b32 v40, s60, 26 ; GISEL-NEXT: v_writelane_b32 v40, s60, 26
; GISEL-NEXT: v_writelane_b32 v40, s61, 27 ; GISEL-NEXT: v_writelane_b32 v40, s61, 27
; GISEL-NEXT: v_writelane_b32 v40, s62, 28 ; GISEL-NEXT: v_writelane_b32 v40, s62, 28
; GISEL-NEXT: v_writelane_b32 v40, s63, 29 ; GISEL-NEXT: v_writelane_b32 v40, s63, 29
; GISEL-NEXT: v_mov_b32_e32 v41, v0 ; GISEL-NEXT: v_mov_b32_e32 v41, v0
; GISEL-NEXT: s_mov_b64 s[4:5], s[30:31] ; GISEL-NEXT: s_mov_b64 s[4:5], s[30:31]
; GISEL-NEXT: s_mov_b64 s[6:7], exec ; GISEL-NEXT: s_mov_b64 s[6:7], exec
; GISEL-NEXT: BB7_1: ; =>This Inner Loop Header: Depth=1 ; GISEL-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1
; GISEL-NEXT: v_readfirstlane_b32 s8, v1 ; GISEL-NEXT: v_readfirstlane_b32 s8, v1
; GISEL-NEXT: v_readfirstlane_b32 s9, v2 ; GISEL-NEXT: v_readfirstlane_b32 s9, v2
; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, s[8:9], v[1:2] ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, s[8:9], v[1:2]
; GISEL-NEXT: s_and_saveexec_b64 s[10:11], vcc ; GISEL-NEXT: s_and_saveexec_b64 s[10:11], vcc
; GISEL-NEXT: v_mov_b32_e32 v0, v41 ; GISEL-NEXT: v_mov_b32_e32 v0, v41
; GISEL-NEXT: s_swappc_b64 s[30:31], s[8:9] ; GISEL-NEXT: s_swappc_b64 s[30:31], s[8:9]
; GISEL-NEXT: ; implicit-def: $vgpr1_vgpr2 ; GISEL-NEXT: ; implicit-def: $vgpr1_vgpr2
; GISEL-NEXT: s_xor_b64 exec, exec, s[10:11] ; GISEL-NEXT: s_xor_b64 exec, exec, s[10:11]
; GISEL-NEXT: s_cbranch_execnz BB7_1 ; GISEL-NEXT: s_cbranch_execnz .LBB7_1
; GISEL-NEXT: ; %bb.2: ; GISEL-NEXT: ; %bb.2:
; GISEL-NEXT: s_mov_b64 exec, s[6:7] ; GISEL-NEXT: s_mov_b64 exec, s[6:7]
; GISEL-NEXT: v_mov_b32_e32 v0, v41 ; GISEL-NEXT: v_mov_b32_e32 v0, v41
; GISEL-NEXT: v_readlane_b32 s63, v40, 29 ; GISEL-NEXT: v_readlane_b32 s63, v40, 29
; GISEL-NEXT: v_readlane_b32 s62, v40, 28 ; GISEL-NEXT: v_readlane_b32 s62, v40, 28
; GISEL-NEXT: v_readlane_b32 s61, v40, 27 ; GISEL-NEXT: v_readlane_b32 s61, v40, 27
; GISEL-NEXT: v_readlane_b32 s60, v40, 26 ; GISEL-NEXT: v_readlane_b32 s60, v40, 26
; GISEL-NEXT: v_readlane_b32 s59, v40, 25 ; GISEL-NEXT: v_readlane_b32 s59, v40, 25
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_writelane_b32 v40, s58, 24 ; GCN-NEXT: v_writelane_b32 v40, s58, 24
; GCN-NEXT: v_writelane_b32 v40, s59, 25 ; GCN-NEXT: v_writelane_b32 v40, s59, 25
; GCN-NEXT: v_writelane_b32 v40, s60, 26 ; GCN-NEXT: v_writelane_b32 v40, s60, 26
; GCN-NEXT: v_writelane_b32 v40, s61, 27 ; GCN-NEXT: v_writelane_b32 v40, s61, 27
; GCN-NEXT: v_writelane_b32 v40, s62, 28 ; GCN-NEXT: v_writelane_b32 v40, s62, 28
; GCN-NEXT: v_writelane_b32 v40, s63, 29 ; GCN-NEXT: v_writelane_b32 v40, s63, 29
; GCN-NEXT: s_mov_b64 s[4:5], s[30:31] ; GCN-NEXT: s_mov_b64 s[4:5], s[30:31]
; GCN-NEXT: s_mov_b64 s[6:7], exec ; GCN-NEXT: s_mov_b64 s[6:7], exec
; GCN-NEXT: BB8_1: ; =>This Inner Loop Header: Depth=1 ; GCN-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: v_readfirstlane_b32 s10, v1 ; GCN-NEXT: v_readfirstlane_b32 s10, v1
; GCN-NEXT: v_readfirstlane_b32 s11, v2 ; GCN-NEXT: v_readfirstlane_b32 s11, v2
; GCN-NEXT: v_cmp_eq_u64_e32 vcc, s[10:11], v[1:2] ; GCN-NEXT: v_cmp_eq_u64_e32 vcc, s[10:11], v[1:2]
; GCN-NEXT: s_and_saveexec_b64 s[8:9], vcc ; GCN-NEXT: s_and_saveexec_b64 s[8:9], vcc
; GCN-NEXT: s_swappc_b64 s[30:31], s[10:11] ; GCN-NEXT: s_swappc_b64 s[30:31], s[10:11]
; GCN-NEXT: v_mov_b32_e32 v3, v0 ; GCN-NEXT: v_mov_b32_e32 v3, v0
; GCN-NEXT: ; implicit-def: $vgpr1_vgpr2 ; GCN-NEXT: ; implicit-def: $vgpr1_vgpr2
; GCN-NEXT: ; implicit-def: $vgpr0 ; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: s_xor_b64 exec, exec, s[8:9] ; GCN-NEXT: s_xor_b64 exec, exec, s[8:9]
; GCN-NEXT: s_cbranch_execnz BB8_1 ; GCN-NEXT: s_cbranch_execnz .LBB8_1
; GCN-NEXT: ; %bb.2: ; GCN-NEXT: ; %bb.2:
; GCN-NEXT: s_mov_b64 exec, s[6:7] ; GCN-NEXT: s_mov_b64 exec, s[6:7]
; GCN-NEXT: v_mov_b32_e32 v0, v3 ; GCN-NEXT: v_mov_b32_e32 v0, v3
; GCN-NEXT: v_readlane_b32 s63, v40, 29 ; GCN-NEXT: v_readlane_b32 s63, v40, 29
; GCN-NEXT: v_readlane_b32 s62, v40, 28 ; GCN-NEXT: v_readlane_b32 s62, v40, 28
; GCN-NEXT: v_readlane_b32 s61, v40, 27 ; GCN-NEXT: v_readlane_b32 s61, v40, 27
; GCN-NEXT: v_readlane_b32 s60, v40, 26 ; GCN-NEXT: v_readlane_b32 s60, v40, 26
; GCN-NEXT: v_readlane_b32 s59, v40, 25 ; GCN-NEXT: v_readlane_b32 s59, v40, 25
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
; GISEL-NEXT: v_writelane_b32 v40, s58, 24 ; GISEL-NEXT: v_writelane_b32 v40, s58, 24
; GISEL-NEXT: v_writelane_b32 v40, s59, 25 ; GISEL-NEXT: v_writelane_b32 v40, s59, 25
; GISEL-NEXT: v_writelane_b32 v40, s60, 26 ; GISEL-NEXT: v_writelane_b32 v40, s60, 26
; GISEL-NEXT: v_writelane_b32 v40, s61, 27 ; GISEL-NEXT: v_writelane_b32 v40, s61, 27
; GISEL-NEXT: v_writelane_b32 v40, s62, 28 ; GISEL-NEXT: v_writelane_b32 v40, s62, 28
; GISEL-NEXT: v_writelane_b32 v40, s63, 29 ; GISEL-NEXT: v_writelane_b32 v40, s63, 29
; GISEL-NEXT: s_mov_b64 s[4:5], s[30:31] ; GISEL-NEXT: s_mov_b64 s[4:5], s[30:31]
; GISEL-NEXT: s_mov_b64 s[6:7], exec ; GISEL-NEXT: s_mov_b64 s[6:7], exec
; GISEL-NEXT: BB8_1: ; =>This Inner Loop Header: Depth=1 ; GISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
; GISEL-NEXT: v_readfirstlane_b32 s8, v1 ; GISEL-NEXT: v_readfirstlane_b32 s8, v1
; GISEL-NEXT: v_readfirstlane_b32 s9, v2 ; GISEL-NEXT: v_readfirstlane_b32 s9, v2
; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, s[8:9], v[1:2] ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, s[8:9], v[1:2]
; GISEL-NEXT: s_and_saveexec_b64 s[10:11], vcc ; GISEL-NEXT: s_and_saveexec_b64 s[10:11], vcc
; GISEL-NEXT: s_swappc_b64 s[30:31], s[8:9] ; GISEL-NEXT: s_swappc_b64 s[30:31], s[8:9]
; GISEL-NEXT: v_mov_b32_e32 v3, v0 ; GISEL-NEXT: v_mov_b32_e32 v3, v0
; GISEL-NEXT: ; implicit-def: $vgpr1_vgpr2 ; GISEL-NEXT: ; implicit-def: $vgpr1_vgpr2
; GISEL-NEXT: ; implicit-def: $vgpr0 ; GISEL-NEXT: ; implicit-def: $vgpr0
; GISEL-NEXT: s_xor_b64 exec, exec, s[10:11] ; GISEL-NEXT: s_xor_b64 exec, exec, s[10:11]
; GISEL-NEXT: s_cbranch_execnz BB8_1 ; GISEL-NEXT: s_cbranch_execnz .LBB8_1
; GISEL-NEXT: ; %bb.2: ; GISEL-NEXT: ; %bb.2:
; GISEL-NEXT: s_mov_b64 exec, s[6:7] ; GISEL-NEXT: s_mov_b64 exec, s[6:7]
; GISEL-NEXT: v_mov_b32_e32 v0, v3 ; GISEL-NEXT: v_mov_b32_e32 v0, v3
; GISEL-NEXT: v_readlane_b32 s63, v40, 29 ; GISEL-NEXT: v_readlane_b32 s63, v40, 29
; GISEL-NEXT: v_readlane_b32 s62, v40, 28 ; GISEL-NEXT: v_readlane_b32 s62, v40, 28
; GISEL-NEXT: v_readlane_b32 s61, v40, 27 ; GISEL-NEXT: v_readlane_b32 s61, v40, 27
; GISEL-NEXT: v_readlane_b32 s60, v40, 26 ; GISEL-NEXT: v_readlane_b32 s60, v40, 26
; GISEL-NEXT: v_readlane_b32 s59, v40, 25 ; GISEL-NEXT: v_readlane_b32 s59, v40, 25
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_writelane_b32 v40, s58, 24 ; GCN-NEXT: v_writelane_b32 v40, s58, 24
; GCN-NEXT: v_writelane_b32 v40, s59, 25 ; GCN-NEXT: v_writelane_b32 v40, s59, 25
; GCN-NEXT: v_writelane_b32 v40, s60, 26 ; GCN-NEXT: v_writelane_b32 v40, s60, 26
; GCN-NEXT: v_writelane_b32 v40, s61, 27 ; GCN-NEXT: v_writelane_b32 v40, s61, 27
; GCN-NEXT: v_writelane_b32 v40, s62, 28 ; GCN-NEXT: v_writelane_b32 v40, s62, 28
; GCN-NEXT: v_writelane_b32 v40, s63, 29 ; GCN-NEXT: v_writelane_b32 v40, s63, 29
; GCN-NEXT: s_mov_b64 s[4:5], s[30:31] ; GCN-NEXT: s_mov_b64 s[4:5], s[30:31]
; GCN-NEXT: s_mov_b64 s[6:7], exec ; GCN-NEXT: s_mov_b64 s[6:7], exec
; GCN-NEXT: BB9_1: ; =>This Inner Loop Header: Depth=1 ; GCN-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: v_readfirstlane_b32 s10, v0 ; GCN-NEXT: v_readfirstlane_b32 s10, v0
; GCN-NEXT: v_readfirstlane_b32 s11, v1 ; GCN-NEXT: v_readfirstlane_b32 s11, v1
; GCN-NEXT: v_cmp_eq_u64_e32 vcc, s[10:11], v[0:1] ; GCN-NEXT: v_cmp_eq_u64_e32 vcc, s[10:11], v[0:1]
; GCN-NEXT: s_and_saveexec_b64 s[8:9], vcc ; GCN-NEXT: s_and_saveexec_b64 s[8:9], vcc
; GCN-NEXT: s_swappc_b64 s[30:31], s[10:11] ; GCN-NEXT: s_swappc_b64 s[30:31], s[10:11]
; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1
; GCN-NEXT: s_xor_b64 exec, exec, s[8:9] ; GCN-NEXT: s_xor_b64 exec, exec, s[8:9]
; GCN-NEXT: s_cbranch_execnz BB9_1 ; GCN-NEXT: s_cbranch_execnz .LBB9_1
; GCN-NEXT: ; %bb.2: ; GCN-NEXT: ; %bb.2:
; GCN-NEXT: s_mov_b64 exec, s[6:7] ; GCN-NEXT: s_mov_b64 exec, s[6:7]
; GCN-NEXT: v_readlane_b32 s63, v40, 29 ; GCN-NEXT: v_readlane_b32 s63, v40, 29
; GCN-NEXT: v_readlane_b32 s62, v40, 28 ; GCN-NEXT: v_readlane_b32 s62, v40, 28
; GCN-NEXT: v_readlane_b32 s61, v40, 27 ; GCN-NEXT: v_readlane_b32 s61, v40, 27
; GCN-NEXT: v_readlane_b32 s60, v40, 26 ; GCN-NEXT: v_readlane_b32 s60, v40, 26
; GCN-NEXT: v_readlane_b32 s59, v40, 25 ; GCN-NEXT: v_readlane_b32 s59, v40, 25
; GCN-NEXT: v_readlane_b32 s58, v40, 24 ; GCN-NEXT: v_readlane_b32 s58, v40, 24
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; GISEL-NEXT: v_writelane_b32 v40, s58, 24 ; GISEL-NEXT: v_writelane_b32 v40, s58, 24
; GISEL-NEXT: v_writelane_b32 v40, s59, 25 ; GISEL-NEXT: v_writelane_b32 v40, s59, 25
; GISEL-NEXT: v_writelane_b32 v40, s60, 26 ; GISEL-NEXT: v_writelane_b32 v40, s60, 26
; GISEL-NEXT: v_writelane_b32 v40, s61, 27 ; GISEL-NEXT: v_writelane_b32 v40, s61, 27
; GISEL-NEXT: v_writelane_b32 v40, s62, 28 ; GISEL-NEXT: v_writelane_b32 v40, s62, 28
; GISEL-NEXT: v_writelane_b32 v40, s63, 29 ; GISEL-NEXT: v_writelane_b32 v40, s63, 29
; GISEL-NEXT: s_mov_b64 s[4:5], s[30:31] ; GISEL-NEXT: s_mov_b64 s[4:5], s[30:31]
; GISEL-NEXT: s_mov_b64 s[6:7], exec ; GISEL-NEXT: s_mov_b64 s[6:7], exec
; GISEL-NEXT: BB9_1: ; =>This Inner Loop Header: Depth=1 ; GISEL-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1
; GISEL-NEXT: v_readfirstlane_b32 s8, v0 ; GISEL-NEXT: v_readfirstlane_b32 s8, v0
; GISEL-NEXT: v_readfirstlane_b32 s9, v1 ; GISEL-NEXT: v_readfirstlane_b32 s9, v1
; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, s[8:9], v[0:1] ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, s[8:9], v[0:1]
; GISEL-NEXT: s_and_saveexec_b64 s[10:11], vcc ; GISEL-NEXT: s_and_saveexec_b64 s[10:11], vcc
; GISEL-NEXT: s_swappc_b64 s[30:31], s[8:9] ; GISEL-NEXT: s_swappc_b64 s[30:31], s[8:9]
; GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1
; GISEL-NEXT: s_xor_b64 exec, exec, s[10:11] ; GISEL-NEXT: s_xor_b64 exec, exec, s[10:11]
; GISEL-NEXT: s_cbranch_execnz BB9_1 ; GISEL-NEXT: s_cbranch_execnz .LBB9_1
; GISEL-NEXT: ; %bb.2: ; GISEL-NEXT: ; %bb.2:
; GISEL-NEXT: s_mov_b64 exec, s[6:7] ; GISEL-NEXT: s_mov_b64 exec, s[6:7]
; GISEL-NEXT: v_readlane_b32 s63, v40, 29 ; GISEL-NEXT: v_readlane_b32 s63, v40, 29
; GISEL-NEXT: v_readlane_b32 s62, v40, 28 ; GISEL-NEXT: v_readlane_b32 s62, v40, 28
; GISEL-NEXT: v_readlane_b32 s61, v40, 27 ; GISEL-NEXT: v_readlane_b32 s61, v40, 27
; GISEL-NEXT: v_readlane_b32 s60, v40, 26 ; GISEL-NEXT: v_readlane_b32 s60, v40, 26
; GISEL-NEXT: v_readlane_b32 s59, v40, 25 ; GISEL-NEXT: v_readlane_b32 s59, v40, 25
; GISEL-NEXT: v_readlane_b32 s58, v40, 24 ; GISEL-NEXT: v_readlane_b32 s58, v40, 24
Show All 34 Lines

llvm/test/CodeGen/AMDGPU/infinite-loop.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=SI %s
; RUN: opt -mtriple=amdgcn-- -S -amdgpu-unify-divergent-exit-nodes -verify -simplifycfg-require-and-preserve-domtree=1 %s | FileCheck -check-prefix=IR %s ; RUN: opt -mtriple=amdgcn-- -S -amdgpu-unify-divergent-exit-nodes -verify -simplifycfg-require-and-preserve-domtree=1 %s | FileCheck -check-prefix=IR %s
define amdgpu_kernel void @infinite_loop(i32 addrspace(1)* %out) { define amdgpu_kernel void @infinite_loop(i32 addrspace(1)* %out) {
; SI-LABEL: infinite_loop: ; SI-LABEL: infinite_loop:
; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: v_mov_b32_e32 v0, 0x3e7 ; SI-NEXT: v_mov_b32_e32 v0, 0x3e7
; SI-NEXT: BB0_1: ; %loop ; SI-NEXT: .LBB0_1: ; %loop
; SI-NEXT: ; =>This Inner Loop Header: Depth=1 ; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_branch BB0_1 ; SI-NEXT: s_branch .LBB0_1
; IR-LABEL: @infinite_loop( ; IR-LABEL: @infinite_loop(
; IR-NEXT: entry: ; IR-NEXT: entry:
; IR-NEXT: br label [[LOOP:%.*]] ; IR-NEXT: br label [[LOOP:%.*]]
; IR: loop: ; IR: loop:
; IR-NEXT: store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4 ; IR-NEXT: store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4
; IR-NEXT: br label [[LOOP]] ; IR-NEXT: br label [[LOOP]]
entry: entry:
br label %loop br label %loop
loop: loop:
store volatile i32 999, i32 addrspace(1)* %out, align 4 store volatile i32 999, i32 addrspace(1)* %out, align 4
br label %loop br label %loop
} }
define amdgpu_kernel void @infinite_loop_ret(i32 addrspace(1)* %out) { define amdgpu_kernel void @infinite_loop_ret(i32 addrspace(1)* %out) {
; SI-LABEL: infinite_loop_ret: ; SI-LABEL: infinite_loop_ret:
; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 ; SI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; SI-NEXT: s_and_saveexec_b64 s[2:3], vcc ; SI-NEXT: s_and_saveexec_b64 s[2:3], vcc
; SI-NEXT: s_cbranch_execz BB1_3 ; SI-NEXT: s_cbranch_execz .LBB1_3
; SI-NEXT: ; %bb.1: ; %loop.preheader ; SI-NEXT: ; %bb.1: ; %loop.preheader
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: v_mov_b32_e32 v0, 0x3e7 ; SI-NEXT: v_mov_b32_e32 v0, 0x3e7
; SI-NEXT: s_and_b64 vcc, exec, -1 ; SI-NEXT: s_and_b64 vcc, exec, -1
; SI-NEXT: BB1_2: ; %loop ; SI-NEXT: .LBB1_2: ; %loop
; SI-NEXT: ; =>This Inner Loop Header: Depth=1 ; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b64 vcc, vcc ; SI-NEXT: s_mov_b64 vcc, vcc
; SI-NEXT: s_cbranch_vccnz BB1_2 ; SI-NEXT: s_cbranch_vccnz .LBB1_2
; SI-NEXT: BB1_3: ; %UnifiedReturnBlock ; SI-NEXT: .LBB1_3: ; %UnifiedReturnBlock
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; IR-LABEL: @infinite_loop_ret( ; IR-LABEL: @infinite_loop_ret(
; IR-NEXT: entry: ; IR-NEXT: entry:
; IR-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x() ; IR-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()
; IR-NEXT: [[COND:%.*]] = icmp eq i32 [[TMP]], 1 ; IR-NEXT: [[COND:%.*]] = icmp eq i32 [[TMP]], 1
; IR-NEXT: br i1 [[COND]], label [[LOOP:%.*]], label [[UNIFIEDRETURNBLOCK:%.*]] ; IR-NEXT: br i1 [[COND]], label [[LOOP:%.*]], label [[UNIFIEDRETURNBLOCK:%.*]]
; IR: loop: ; IR: loop:
; IR-NEXT: store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4 ; IR-NEXT: store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4
Show All 13 Linesreturn:
ret void ret void
} }
define amdgpu_kernel void @infinite_loops(i32 addrspace(1)* %out) { define amdgpu_kernel void @infinite_loops(i32 addrspace(1)* %out) {
; SI-LABEL: infinite_loops: ; SI-LABEL: infinite_loops:
; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT: s_mov_b64 s[2:3], -1 ; SI-NEXT: s_mov_b64 s[2:3], -1
; SI-NEXT: s_cbranch_scc1 BB2_4 ; SI-NEXT: s_cbranch_scc1 .LBB2_4
; SI-NEXT: ; %bb.1: ; SI-NEXT: ; %bb.1:
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: v_mov_b32_e32 v0, 0x378 ; SI-NEXT: v_mov_b32_e32 v0, 0x378
; SI-NEXT: s_and_b64 vcc, exec, -1 ; SI-NEXT: s_and_b64 vcc, exec, -1
; SI-NEXT: BB2_2: ; %loop2 ; SI-NEXT: .LBB2_2: ; %loop2
; SI-NEXT: ; =>This Inner Loop Header: Depth=1 ; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b64 vcc, vcc ; SI-NEXT: s_mov_b64 vcc, vcc
; SI-NEXT: s_cbranch_vccnz BB2_2 ; SI-NEXT: s_cbranch_vccnz .LBB2_2
; SI-NEXT: ; %bb.3: ; %Flow ; SI-NEXT: ; %bb.3: ; %Flow
; SI-NEXT: s_mov_b64 s[2:3], 0 ; SI-NEXT: s_mov_b64 s[2:3], 0
; SI-NEXT: BB2_4: ; %Flow2 ; SI-NEXT: .LBB2_4: ; %Flow2
; SI-NEXT: s_and_b64 vcc, exec, s[2:3] ; SI-NEXT: s_and_b64 vcc, exec, s[2:3]
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b64 vcc, vcc ; SI-NEXT: s_mov_b64 vcc, vcc
; SI-NEXT: s_cbranch_vccz BB2_7 ; SI-NEXT: s_cbranch_vccz .LBB2_7
; SI-NEXT: ; %bb.5: ; SI-NEXT: ; %bb.5:
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, 0x3e7 ; SI-NEXT: v_mov_b32_e32 v0, 0x3e7
; SI-NEXT: s_and_b64 vcc, exec, 0 ; SI-NEXT: s_and_b64 vcc, exec, 0
; SI-NEXT: BB2_6: ; %loop1 ; SI-NEXT: .LBB2_6: ; %loop1
; SI-NEXT: ; =>This Inner Loop Header: Depth=1 ; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b64 vcc, vcc ; SI-NEXT: s_mov_b64 vcc, vcc
; SI-NEXT: s_cbranch_vccz BB2_6 ; SI-NEXT: s_cbranch_vccz .LBB2_6
; SI-NEXT: BB2_7: ; %DummyReturnBlock ; SI-NEXT: .LBB2_7: ; %DummyReturnBlock
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; IR-LABEL: @infinite_loops( ; IR-LABEL: @infinite_loops(
; IR-NEXT: entry: ; IR-NEXT: entry:
; IR-NEXT: br i1 undef, label [[LOOP1:%.*]], label [[LOOP2:%.*]] ; IR-NEXT: br i1 undef, label [[LOOP1:%.*]], label [[LOOP2:%.*]]
; IR: loop1: ; IR: loop1:
; IR-NEXT: store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4 ; IR-NEXT: store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4
; IR-NEXT: br i1 true, label [[LOOP1]], label [[DUMMYRETURNBLOCK:%.*]] ; IR-NEXT: br i1 true, label [[LOOP1]], label [[DUMMYRETURNBLOCK:%.*]]
; IR: loop2: ; IR: loop2:
Show All 13 Linesloop2:
br label %loop2 br label %loop2
} }
define amdgpu_kernel void @infinite_loop_nest_ret(i32 addrspace(1)* %out) { define amdgpu_kernel void @infinite_loop_nest_ret(i32 addrspace(1)* %out) {
; SI-LABEL: infinite_loop_nest_ret: ; SI-LABEL: infinite_loop_nest_ret:
; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 ; SI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; SI-NEXT: s_and_saveexec_b64 s[2:3], vcc ; SI-NEXT: s_and_saveexec_b64 s[2:3], vcc
; SI-NEXT: s_cbranch_execz BB3_5 ; SI-NEXT: s_cbranch_execz .LBB3_5
; SI-NEXT: ; %bb.1: ; %outer_loop.preheader ; SI-NEXT: ; %bb.1: ; %outer_loop.preheader
; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; SI-NEXT: v_cmp_ne_u32_e64 s[0:1], 3, v0 ; SI-NEXT: v_cmp_ne_u32_e64 s[0:1], 3, v0
; SI-NEXT: s_mov_b32 s7, 0xf000 ; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1 ; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: v_mov_b32_e32 v0, 0x3e7 ; SI-NEXT: v_mov_b32_e32 v0, 0x3e7
; SI-NEXT: BB3_2: ; %outer_loop ; SI-NEXT: .LBB3_2: ; %outer_loop
; SI-NEXT: ; =>This Loop Header: Depth=1 ; SI-NEXT: ; =>This Loop Header: Depth=1
; SI-NEXT: ; Child Loop BB3_3 Depth 2 ; SI-NEXT: ; Child Loop BB3_3 Depth 2
; SI-NEXT: s_mov_b64 s[2:3], 0 ; SI-NEXT: s_mov_b64 s[2:3], 0
; SI-NEXT: BB3_3: ; %inner_loop ; SI-NEXT: .LBB3_3: ; %inner_loop
; SI-NEXT: ; Parent Loop BB3_2 Depth=1 ; SI-NEXT: ; Parent Loop BB3_2 Depth=1
; SI-NEXT: ; => This Inner Loop Header: Depth=2 ; SI-NEXT: ; => This Inner Loop Header: Depth=2
; SI-NEXT: s_and_b64 s[8:9], exec, s[0:1] ; SI-NEXT: s_and_b64 s[8:9], exec, s[0:1]
; SI-NEXT: s_or_b64 s[2:3], s[8:9], s[2:3] ; SI-NEXT: s_or_b64 s[2:3], s[8:9], s[2:3]
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_andn2_b64 exec, exec, s[2:3] ; SI-NEXT: s_andn2_b64 exec, exec, s[2:3]
; SI-NEXT: s_cbranch_execnz BB3_3 ; SI-NEXT: s_cbranch_execnz .LBB3_3
; SI-NEXT: ; %bb.4: ; %loop.exit.guard ; SI-NEXT: ; %bb.4: ; %loop.exit.guard
; SI-NEXT: ; in Loop: Header=BB3_2 Depth=1 ; SI-NEXT: ; in Loop: Header=BB3_2 Depth=1
; SI-NEXT: s_or_b64 exec, exec, s[2:3] ; SI-NEXT: s_or_b64 exec, exec, s[2:3]
; SI-NEXT: s_mov_b64 vcc, 0 ; SI-NEXT: s_mov_b64 vcc, 0
; SI-NEXT: s_branch BB3_2 ; SI-NEXT: s_branch .LBB3_2
; SI-NEXT: BB3_5: ; %UnifiedReturnBlock ; SI-NEXT: .LBB3_5: ; %UnifiedReturnBlock
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; IR-LABEL: @infinite_loop_nest_ret( ; IR-LABEL: @infinite_loop_nest_ret(
; IR-NEXT: entry: ; IR-NEXT: entry:
; IR-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x() ; IR-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()
; IR-NEXT: [[COND1:%.*]] = icmp eq i32 [[TMP]], 1 ; IR-NEXT: [[COND1:%.*]] = icmp eq i32 [[TMP]], 1
; IR-NEXT: br i1 [[COND1]], label [[OUTER_LOOP:%.*]], label [[UNIFIEDRETURNBLOCK:%.*]] ; IR-NEXT: br i1 [[COND1]], label [[OUTER_LOOP:%.*]], label [[UNIFIEDRETURNBLOCK:%.*]]
; IR: outer_loop: ; IR: outer_loop:
; IR-NEXT: br label [[INNER_LOOP:%.*]] ; IR-NEXT: br label [[INNER_LOOP:%.*]]
Show All 28 Lines

llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll

Show First 20 Lines • Show All 1,528 Lines • ▼ Show 20 Lines
; the compiler doesn't crash. ; the compiler doesn't crash.
define amdgpu_kernel void @insert_split_bb(<2 x i32> addrspace(1)* %out, i32 addrspace(1)* %in, i32 %a, i32 %b) { define amdgpu_kernel void @insert_split_bb(<2 x i32> addrspace(1)* %out, i32 addrspace(1)* %in, i32 %a, i32 %b) {
; SI-LABEL: insert_split_bb: ; SI-LABEL: insert_split_bb:
; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dword s6, s[4:5], 0x4 ; SI-NEXT: s_load_dword s6, s[4:5], 0x4
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_cmp_lg_u32 s6, 0 ; SI-NEXT: s_cmp_lg_u32 s6, 0
; SI-NEXT: s_cbranch_scc0 BB30_2 ; SI-NEXT: s_cbranch_scc0 .LBB30_2
; SI-NEXT: ; %bb.1: ; %else ; SI-NEXT: ; %bb.1: ; %else
; SI-NEXT: s_load_dword s7, s[2:3], 0x1 ; SI-NEXT: s_load_dword s7, s[2:3], 0x1
; SI-NEXT: s_mov_b64 s[4:5], 0 ; SI-NEXT: s_mov_b64 s[4:5], 0
; SI-NEXT: s_andn2_b64 vcc, exec, s[4:5] ; SI-NEXT: s_andn2_b64 vcc, exec, s[4:5]
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b64 vcc, vcc ; SI-NEXT: s_mov_b64 vcc, vcc
; SI-NEXT: s_cbranch_vccz BB30_3 ; SI-NEXT: s_cbranch_vccz .LBB30_3
; SI-NEXT: s_branch BB30_4 ; SI-NEXT: s_branch .LBB30_4
; SI-NEXT: BB30_2: ; SI-NEXT: .LBB30_2:
; SI-NEXT: BB30_3: ; %if ; SI-NEXT: .LBB30_3: ; %if
; SI-NEXT: s_load_dword s7, s[2:3], 0x0 ; SI-NEXT: s_load_dword s7, s[2:3], 0x0
; SI-NEXT: BB30_4: ; %endif ; SI-NEXT: .LBB30_4: ; %endif
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s6 ; SI-NEXT: v_mov_b32_e32 v0, s6
; SI-NEXT: s_mov_b32 s3, 0x100f000 ; SI-NEXT: s_mov_b32 s3, 0x100f000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: v_mov_b32_e32 v1, s7 ; SI-NEXT: v_mov_b32_e32 v1, s7
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: insert_split_bb: ; VI-LABEL: insert_split_bb:
; VI: ; %bb.0: ; %entry ; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dword s6, s[4:5], 0x10 ; VI-NEXT: s_load_dword s6, s[4:5], 0x10
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_cmp_lg_u32 s6, 0 ; VI-NEXT: s_cmp_lg_u32 s6, 0
; VI-NEXT: s_cbranch_scc0 BB30_2 ; VI-NEXT: s_cbranch_scc0 .LBB30_2
; VI-NEXT: ; %bb.1: ; %else ; VI-NEXT: ; %bb.1: ; %else
; VI-NEXT: s_load_dword s7, s[2:3], 0x4 ; VI-NEXT: s_load_dword s7, s[2:3], 0x4
; VI-NEXT: s_cbranch_execz BB30_3 ; VI-NEXT: s_cbranch_execz .LBB30_3
; VI-NEXT: s_branch BB30_4 ; VI-NEXT: s_branch .LBB30_4
; VI-NEXT: BB30_2: ; VI-NEXT: .LBB30_2:
; VI-NEXT: BB30_3: ; %if ; VI-NEXT: .LBB30_3: ; %if
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_load_dword s7, s[2:3], 0x0 ; VI-NEXT: s_load_dword s7, s[2:3], 0x0
; VI-NEXT: BB30_4: ; %endif ; VI-NEXT: .LBB30_4: ; %endif
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s6 ; VI-NEXT: v_mov_b32_e32 v0, s6
; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; VI-NEXT: s_mov_b32 s3, 0x1100f000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: v_mov_b32_e32 v1, s7 ; VI-NEXT: v_mov_b32_e32 v1, s7
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
entry: entry:
▲ Show 20 Lines • Show All 331 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll

Show All 11 Lines
define amdgpu_ps void @return_void(float %0) #0 { define amdgpu_ps void @return_void(float %0) #0 {
; CHECK-LABEL: return_void: ; CHECK-LABEL: return_void:
; CHECK: ; %bb.0: ; %main_body ; CHECK: ; %bb.0: ; %main_body
; CHECK-NEXT: s_mov_b64 s[0:1], exec ; CHECK-NEXT: s_mov_b64 s[0:1], exec
; CHECK-NEXT: s_mov_b32 s2, 0x41200000 ; CHECK-NEXT: s_mov_b32 s2, 0x41200000
; CHECK-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v0 ; CHECK-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v0
; CHECK-NEXT: s_and_saveexec_b64 s[2:3], vcc ; CHECK-NEXT: s_and_saveexec_b64 s[2:3], vcc
; CHECK-NEXT: s_xor_b64 s[2:3], exec, s[2:3] ; CHECK-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; CHECK-NEXT: s_cbranch_execz BB0_3 ; CHECK-NEXT: s_cbranch_execz .LBB0_3
; CHECK-NEXT: BB0_1: ; %loop ; CHECK-NEXT: .LBB0_1: ; %loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; CHECK-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; CHECK-NEXT: s_cbranch_scc0 BB0_6 ; CHECK-NEXT: s_cbranch_scc0 .LBB0_6
; CHECK-NEXT: ; %bb.2: ; %loop ; CHECK-NEXT: ; %bb.2: ; %loop
; CHECK-NEXT: ; in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: ; in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT: s_mov_b64 exec, 0 ; CHECK-NEXT: s_mov_b64 exec, 0
; CHECK-NEXT: s_mov_b64 vcc, 0 ; CHECK-NEXT: s_mov_b64 vcc, 0
; CHECK-NEXT: s_branch BB0_1 ; CHECK-NEXT: s_branch .LBB0_1
; CHECK-NEXT: BB0_3: ; %Flow1 ; CHECK-NEXT: .LBB0_3: ; %Flow1
; CHECK-NEXT: s_or_saveexec_b64 s[0:1], s[2:3] ; CHECK-NEXT: s_or_saveexec_b64 s[0:1], s[2:3]
; CHECK-NEXT: s_xor_b64 exec, exec, s[0:1] ; CHECK-NEXT: s_xor_b64 exec, exec, s[0:1]
; CHECK-NEXT: s_cbranch_execz BB0_5 ; CHECK-NEXT: s_cbranch_execz .LBB0_5
; CHECK-NEXT: ; %bb.4: ; %end ; CHECK-NEXT: ; %bb.4: ; %end
; CHECK-NEXT: v_mov_b32_e32 v0, 1.0 ; CHECK-NEXT: v_mov_b32_e32 v0, 1.0
; CHECK-NEXT: v_mov_b32_e32 v1, 0 ; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: exp mrt0 v1, v1, v1, v0 done vm ; CHECK-NEXT: exp mrt0 v1, v1, v1, v0 done vm
; CHECK-NEXT: BB0_5: ; %UnifiedReturnBlock ; CHECK-NEXT: .LBB0_5: ; %UnifiedReturnBlock
; CHECK-NEXT: s_endpgm ; CHECK-NEXT: s_endpgm
; CHECK-NEXT: BB0_6: ; CHECK-NEXT: .LBB0_6:
; CHECK-NEXT: s_mov_b64 exec, 0 ; CHECK-NEXT: s_mov_b64 exec, 0
; CHECK-NEXT: exp null off, off, off, off done vm ; CHECK-NEXT: exp null off, off, off, off done vm
; CHECK-NEXT: s_endpgm ; CHECK-NEXT: s_endpgm
main_body: main_body:
%cmp = fcmp olt float %0, 1.000000e+01 %cmp = fcmp olt float %0, 1.000000e+01
br i1 %cmp, label %end, label %loop br i1 %cmp, label %end, label %loop
loop: loop:
call void @llvm.amdgcn.kill(i1 false) #3 call void @llvm.amdgcn.kill(i1 false) #3
br label %loop br label %loop
end: end:
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float 0., float 0., float 0., float 1., i1 true, i1 true) #3 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float 0., float 0., float 0., float 1., i1 true, i1 true) #3
ret void ret void
} }
define amdgpu_ps void @return_void_compr(float %0) #0 { define amdgpu_ps void @return_void_compr(float %0) #0 {
; CHECK-LABEL: return_void_compr: ; CHECK-LABEL: return_void_compr:
; CHECK: ; %bb.0: ; %main_body ; CHECK: ; %bb.0: ; %main_body
; CHECK-NEXT: s_mov_b64 s[0:1], exec ; CHECK-NEXT: s_mov_b64 s[0:1], exec
; CHECK-NEXT: s_mov_b32 s2, 0x41200000 ; CHECK-NEXT: s_mov_b32 s2, 0x41200000
; CHECK-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v0 ; CHECK-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v0
; CHECK-NEXT: s_and_saveexec_b64 s[2:3], vcc ; CHECK-NEXT: s_and_saveexec_b64 s[2:3], vcc
; CHECK-NEXT: s_xor_b64 s[2:3], exec, s[2:3] ; CHECK-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; CHECK-NEXT: s_cbranch_execz BB1_3 ; CHECK-NEXT: s_cbranch_execz .LBB1_3
; CHECK-NEXT: BB1_1: ; %loop ; CHECK-NEXT: .LBB1_1: ; %loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; CHECK-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; CHECK-NEXT: s_cbranch_scc0 BB1_6 ; CHECK-NEXT: s_cbranch_scc0 .LBB1_6
; CHECK-NEXT: ; %bb.2: ; %loop ; CHECK-NEXT: ; %bb.2: ; %loop
; CHECK-NEXT: ; in Loop: Header=BB1_1 Depth=1 ; CHECK-NEXT: ; in Loop: Header=BB1_1 Depth=1
; CHECK-NEXT: s_mov_b64 exec, 0 ; CHECK-NEXT: s_mov_b64 exec, 0
; CHECK-NEXT: s_mov_b64 vcc, 0 ; CHECK-NEXT: s_mov_b64 vcc, 0
; CHECK-NEXT: s_branch BB1_1 ; CHECK-NEXT: s_branch .LBB1_1
; CHECK-NEXT: BB1_3: ; %Flow1 ; CHECK-NEXT: .LBB1_3: ; %Flow1
; CHECK-NEXT: s_or_saveexec_b64 s[0:1], s[2:3] ; CHECK-NEXT: s_or_saveexec_b64 s[0:1], s[2:3]
; CHECK-NEXT: s_xor_b64 exec, exec, s[0:1] ; CHECK-NEXT: s_xor_b64 exec, exec, s[0:1]
; CHECK-NEXT: s_cbranch_execz BB1_5 ; CHECK-NEXT: s_cbranch_execz .LBB1_5
; CHECK-NEXT: ; %bb.4: ; %end ; CHECK-NEXT: ; %bb.4: ; %end
; CHECK-NEXT: v_mov_b32_e32 v0, 0 ; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: exp mrt0 v0, off, v0, off done compr vm ; CHECK-NEXT: exp mrt0 v0, off, v0, off done compr vm
; CHECK-NEXT: BB1_5: ; %UnifiedReturnBlock ; CHECK-NEXT: .LBB1_5: ; %UnifiedReturnBlock
; CHECK-NEXT: s_endpgm ; CHECK-NEXT: s_endpgm
; CHECK-NEXT: BB1_6: ; CHECK-NEXT: .LBB1_6:
; CHECK-NEXT: s_mov_b64 exec, 0 ; CHECK-NEXT: s_mov_b64 exec, 0
; CHECK-NEXT: exp null off, off, off, off done vm ; CHECK-NEXT: exp null off, off, off, off done vm
; CHECK-NEXT: s_endpgm ; CHECK-NEXT: s_endpgm
main_body: main_body:
%cmp = fcmp olt float %0, 1.000000e+01 %cmp = fcmp olt float %0, 1.000000e+01
br i1 %cmp, label %end, label %loop br i1 %cmp, label %end, label %loop
loop: loop:
call void @llvm.amdgcn.kill(i1 false) #3 call void @llvm.amdgcn.kill(i1 false) #3
br label %loop br label %loop
end: end:
call void @llvm.amdgcn.exp.compr.v2i16(i32 0, i32 5, <2 x i16> < i16 0, i16 0 >, <2 x i16> < i16 0, i16 0 >, i1 true, i1 true) #3 call void @llvm.amdgcn.exp.compr.v2i16(i32 0, i32 5, <2 x i16> < i16 0, i16 0 >, <2 x i16> < i16 0, i16 0 >, i1 true, i1 true) #3
ret void ret void
} }
; test the case where there's only a kill in an infinite loop ; test the case where there's only a kill in an infinite loop
define amdgpu_ps void @only_kill() #0 { define amdgpu_ps void @only_kill() #0 {
; CHECK-LABEL: only_kill: ; CHECK-LABEL: only_kill:
; CHECK: ; %bb.0: ; %main_body ; CHECK: ; %bb.0: ; %main_body
; CHECK-NEXT: s_mov_b64 s[0:1], exec ; CHECK-NEXT: s_mov_b64 s[0:1], exec
; CHECK-NEXT: BB2_1: ; %loop ; CHECK-NEXT: .LBB2_1: ; %loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; CHECK-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; CHECK-NEXT: s_cbranch_scc0 BB2_3 ; CHECK-NEXT: s_cbranch_scc0 .LBB2_3
; CHECK-NEXT: ; %bb.2: ; %loop ; CHECK-NEXT: ; %bb.2: ; %loop
; CHECK-NEXT: ; in Loop: Header=BB2_1 Depth=1 ; CHECK-NEXT: ; in Loop: Header=BB2_1 Depth=1
; CHECK-NEXT: s_mov_b64 exec, 0 ; CHECK-NEXT: s_mov_b64 exec, 0
; CHECK-NEXT: s_branch BB2_1 ; CHECK-NEXT: s_branch .LBB2_1
; CHECK-NEXT: BB2_3: ; CHECK-NEXT: .LBB2_3:
; CHECK-NEXT: s_mov_b64 exec, 0 ; CHECK-NEXT: s_mov_b64 exec, 0
; CHECK-NEXT: exp null off, off, off, off done vm ; CHECK-NEXT: exp null off, off, off, off done vm
; CHECK-NEXT: s_endpgm ; CHECK-NEXT: s_endpgm
main_body: main_body:
br label %loop br label %loop
loop: loop:
call void @llvm.amdgcn.kill(i1 false) #3 call void @llvm.amdgcn.kill(i1 false) #3
br label %loop br label %loop
} }
; Check that the epilog is the final block ; Check that the epilog is the final block
define amdgpu_ps float @return_nonvoid(float %0) #0 { define amdgpu_ps float @return_nonvoid(float %0) #0 {
; CHECK-LABEL: return_nonvoid: ; CHECK-LABEL: return_nonvoid:
; CHECK: ; %bb.0: ; %main_body ; CHECK: ; %bb.0: ; %main_body
; CHECK-NEXT: s_mov_b64 s[0:1], exec ; CHECK-NEXT: s_mov_b64 s[0:1], exec
; CHECK-NEXT: s_mov_b32 s2, 0x41200000 ; CHECK-NEXT: s_mov_b32 s2, 0x41200000
; CHECK-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v0 ; CHECK-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v0
; CHECK-NEXT: s_and_saveexec_b64 s[2:3], vcc ; CHECK-NEXT: s_and_saveexec_b64 s[2:3], vcc
; CHECK-NEXT: s_xor_b64 s[2:3], exec, s[2:3] ; CHECK-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; CHECK-NEXT: s_cbranch_execz BB3_3 ; CHECK-NEXT: s_cbranch_execz .LBB3_3
; CHECK-NEXT: BB3_1: ; %loop ; CHECK-NEXT: .LBB3_1: ; %loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; CHECK-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; CHECK-NEXT: s_cbranch_scc0 BB3_4 ; CHECK-NEXT: s_cbranch_scc0 .LBB3_4
; CHECK-NEXT: ; %bb.2: ; %loop ; CHECK-NEXT: ; %bb.2: ; %loop
; CHECK-NEXT: ; in Loop: Header=BB3_1 Depth=1 ; CHECK-NEXT: ; in Loop: Header=BB3_1 Depth=1
; CHECK-NEXT: s_mov_b64 exec, 0 ; CHECK-NEXT: s_mov_b64 exec, 0
; CHECK-NEXT: s_mov_b64 vcc, exec ; CHECK-NEXT: s_mov_b64 vcc, exec
; CHECK-NEXT: s_cbranch_execnz BB3_1 ; CHECK-NEXT: s_cbranch_execnz .LBB3_1
; CHECK-NEXT: BB3_3: ; %Flow1 ; CHECK-NEXT: .LBB3_3: ; %Flow1
; CHECK-NEXT: s_or_b64 exec, exec, s[2:3] ; CHECK-NEXT: s_or_b64 exec, exec, s[2:3]
; CHECK-NEXT: v_mov_b32_e32 v0, 0 ; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: s_branch BB3_5 ; CHECK-NEXT: s_branch .LBB3_5
; CHECK-NEXT: BB3_4: ; CHECK-NEXT: .LBB3_4:
; CHECK-NEXT: s_mov_b64 exec, 0 ; CHECK-NEXT: s_mov_b64 exec, 0
; CHECK-NEXT: exp null off, off, off, off done vm ; CHECK-NEXT: exp null off, off, off, off done vm
; CHECK-NEXT: s_endpgm ; CHECK-NEXT: s_endpgm
; CHECK-NEXT: BB3_5: ; CHECK-NEXT: .LBB3_5:
main_body: main_body:
%cmp = fcmp olt float %0, 1.000000e+01 %cmp = fcmp olt float %0, 1.000000e+01
br i1 %cmp, label %end, label %loop br i1 %cmp, label %end, label %loop
loop: loop:
call void @llvm.amdgcn.kill(i1 false) #3 call void @llvm.amdgcn.kill(i1 false) #3
br label %loop br label %loop
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llvm/test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; Make sure that m0 is not reinitialized in the loop. ; Make sure that m0 is not reinitialized in the loop.
; GCN-LABEL: {{^}}copy_local_to_global_loop_m0_init: ; GCN-LABEL: {{^}}copy_local_to_global_loop_m0_init:
; GCN: s_cbranch_scc1 BB0_3 ; GCN: s_cbranch_scc1 .LBB0_3
; Initialize in preheader ; Initialize in preheader
; GCN: s_mov_b32 m0, -1 ; GCN: s_mov_b32 m0, -1
; GCN: BB0_2: ; GCN: .LBB0_2:
; GCN-NOT: m0 ; GCN-NOT: m0
; GCN: ds_read_b32 ; GCN: ds_read_b32
; GCN-NOT: m0 ; GCN-NOT: m0
; GCN: buffer_store_dword ; GCN: buffer_store_dword
; GCN: s_cbranch_scc0 BB0_2 ; GCN: s_cbranch_scc0 .LBB0_2
; GCN: BB0_3: ; GCN: .LBB0_3:
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @copy_local_to_global_loop_m0_init(i32 addrspace(1)* noalias nocapture %out, i32 addrspace(3)* noalias nocapture readonly %in, i32 %n) #0 { define amdgpu_kernel void @copy_local_to_global_loop_m0_init(i32 addrspace(1)* noalias nocapture %out, i32 addrspace(3)* noalias nocapture readonly %in, i32 %n) #0 {
bb: bb:
%tmp = icmp sgt i32 %n, 0 %tmp = icmp sgt i32 %n, 0
br i1 %tmp, label %.lr.ph.preheader, label %._crit_edge br i1 %tmp, label %.lr.ph.preheader, label %._crit_edge
.lr.ph.preheader: ; preds = %bb .lr.ph.preheader: ; preds = %bb
br label %.lr.ph br label %.lr.ph
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llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll

Show All 11 Lines
; Minimum offset ; Minimum offset
; GCN-LABEL: {{^}}gws_barrier_offset0: ; GCN-LABEL: {{^}}gws_barrier_offset0:
; NOLOOP-DAG: s_load_dword [[BAR_NUM:s[0-9]+]] ; NOLOOP-DAG: s_load_dword [[BAR_NUM:s[0-9]+]]
; NOLOOP-DAG: s_mov_b32 m0, 0{{$}} ; NOLOOP-DAG: s_mov_b32 m0, 0{{$}}
; NOLOOP: v_mov_b32_e32 v0, [[BAR_NUM]] ; NOLOOP: v_mov_b32_e32 v0, [[BAR_NUM]]
; NOLOOP: ds_gws_barrier v0 gds{{$}} ; NOLOOP: ds_gws_barrier v0 gds{{$}}
; LOOP: s_mov_b32 m0, 0{{$}} ; LOOP: s_mov_b32 m0, 0{{$}}
; LOOP: [[LOOP:BB[0-9]+_[0-9]+]]: ; LOOP: [[LOOP:.LBB[0-9]+_[0-9]+]]:
; LOOP-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, 8, 1), 0 ; LOOP-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, 8, 1), 0
; LOOP-NEXT: ds_gws_barrier v0 gds ; LOOP-NEXT: ds_gws_barrier v0 gds
; LOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; LOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; LOOP-NEXT: s_getreg_b32 [[GETREG:s[0-9]+]], hwreg(HW_REG_TRAPSTS, 8, 1) ; LOOP-NEXT: s_getreg_b32 [[GETREG:s[0-9]+]], hwreg(HW_REG_TRAPSTS, 8, 1)
; LOOP-NEXT: s_cmp_lg_u32 [[GETREG]], 0 ; LOOP-NEXT: s_cmp_lg_u32 [[GETREG]], 0
; LOOP-NEXT: s_cbranch_scc1 [[LOOP]] ; LOOP-NEXT: s_cbranch_scc1 [[LOOP]]
; MIR-LABEL: name: gws_barrier_offset0{{$}} ; MIR-LABEL: name: gws_barrier_offset0{{$}}
▲ Show 20 Lines • Show All 211 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.init.ll

; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP,NOLOOP-SDAG %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP,NOLOOP-SDAG %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -asm-verbose=0 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP,NOLOOP-SDAG %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -asm-verbose=0 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP,NOLOOP-SDAG %s
; Minimum offset ; Minimum offset
; GCN-LABEL: {{^}}gws_init_offset0: ; GCN-LABEL: {{^}}gws_init_offset0:
; GCN-DAG: s_load_dword [[BAR_NUM:s[0-9]+]] ; GCN-DAG: s_load_dword [[BAR_NUM:s[0-9]+]]
; GCN-DAG: s_mov_b32 m0, 0{{$}} ; GCN-DAG: s_mov_b32 m0, 0{{$}}
; GCN: v_mov_b32_e32 v0, [[BAR_NUM]] ; GCN: v_mov_b32_e32 v0, [[BAR_NUM]]
; NOLOOP: ds_gws_init v0 gds{{$}} ; NOLOOP: ds_gws_init v0 gds{{$}}
; LOOP: [[LOOP:BB[0-9]+_[0-9]+]]: ; LOOP: [[LOOP:.LBB[0-9]+_[0-9]+]]:
; LOOP-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, 8, 1), 0 ; LOOP-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, 8, 1), 0
; LOOP-NEXT: ds_gws_init v0 gds ; LOOP-NEXT: ds_gws_init v0 gds
; LOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; LOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; LOOP-NEXT: s_getreg_b32 [[GETREG:s[0-9]+]], hwreg(HW_REG_TRAPSTS, 8, 1) ; LOOP-NEXT: s_getreg_b32 [[GETREG:s[0-9]+]], hwreg(HW_REG_TRAPSTS, 8, 1)
; LOOP-NEXT: s_cmp_lg_u32 [[GETREG]], 0 ; LOOP-NEXT: s_cmp_lg_u32 [[GETREG]], 0
; LOOP-NEXT: s_cbranch_scc1 [[LOOP]] ; LOOP-NEXT: s_cbranch_scc1 [[LOOP]]
define amdgpu_kernel void @gws_init_offset0(i32 %val) #0 { define amdgpu_kernel void @gws_init_offset0(i32 %val) #0 {
call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 0) call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 0)
ret void ret void
} }
; Maximum offset ; Maximum offset
; GCN-LABEL: {{^}}gws_init_offset63: ; GCN-LABEL: {{^}}gws_init_offset63:
; NOLOOP-DAG: s_load_dword [[BAR_NUM:s[0-9]+]] ; NOLOOP-DAG: s_load_dword [[BAR_NUM:s[0-9]+]]
; NOLOOP-DAG: s_mov_b32 m0, 0{{$}} ; NOLOOP-DAG: s_mov_b32 m0, 0{{$}}
; NOLOOP-DAG: v_mov_b32_e32 v0, [[BAR_NUM]] ; NOLOOP-DAG: v_mov_b32_e32 v0, [[BAR_NUM]]
; NOLOOP: ds_gws_init v0 offset:63 gds{{$}} ; NOLOOP: ds_gws_init v0 offset:63 gds{{$}}
; LOOP: s_mov_b32 m0, 0{{$}} ; LOOP: s_mov_b32 m0, 0{{$}}
; LOOP: [[LOOP:BB[0-9]+_[0-9]+]]: ; LOOP: [[LOOP:.LBB[0-9]+_[0-9]+]]:
; LOOP-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, 8, 1), 0 ; LOOP-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, 8, 1), 0
; LOOP-NEXT: ds_gws_init v0 offset:63 gds ; LOOP-NEXT: ds_gws_init v0 offset:63 gds
; LOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; LOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; LOOP-NEXT: s_getreg_b32 [[GETREG:s[0-9]+]], hwreg(HW_REG_TRAPSTS, 8, 1) ; LOOP-NEXT: s_getreg_b32 [[GETREG:s[0-9]+]], hwreg(HW_REG_TRAPSTS, 8, 1)
; LOOP-NEXT: s_cmp_lg_u32 [[GETREG]], 0 ; LOOP-NEXT: s_cmp_lg_u32 [[GETREG]], 0
; LOOP-NEXT: s_cbranch_scc1 [[LOOP]] ; LOOP-NEXT: s_cbranch_scc1 [[LOOP]]
define amdgpu_kernel void @gws_init_offset63(i32 %val) #0 { define amdgpu_kernel void @gws_init_offset63(i32 %val) #0 {
call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 63) call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 63)
▲ Show 20 Lines • Show All 123 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.br.ll

; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %s
; GCN-LABEL: {{^}}gws_sema_br_offset0: ; GCN-LABEL: {{^}}gws_sema_br_offset0:
; NOLOOP-DAG: s_load_dword [[BAR_NUM:s[0-9]+]] ; NOLOOP-DAG: s_load_dword [[BAR_NUM:s[0-9]+]]
; NOLOOP-DAG: s_mov_b32 m0, 0{{$}} ; NOLOOP-DAG: s_mov_b32 m0, 0{{$}}
; NOLOOP: v_mov_b32_e32 v0, [[BAR_NUM]] ; NOLOOP: v_mov_b32_e32 v0, [[BAR_NUM]]
; NOLOOP: ds_gws_sema_br v0 gds{{$}} ; NOLOOP: ds_gws_sema_br v0 gds{{$}}
; LOOP: s_mov_b32 m0, 0{{$}} ; LOOP: s_mov_b32 m0, 0{{$}}
; LOOP: [[LOOP:BB[0-9]+_[0-9]+]]: ; LOOP: [[LOOP:.LBB[0-9]+_[0-9]+]]:
; LOOP-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, 8, 1), 0 ; LOOP-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, 8, 1), 0
; LOOP-NEXT: ds_gws_sema_br v0 gds ; LOOP-NEXT: ds_gws_sema_br v0 gds
; LOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; LOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; LOOP-NEXT: s_getreg_b32 [[GETREG:s[0-9]+]], hwreg(HW_REG_TRAPSTS, 8, 1) ; LOOP-NEXT: s_getreg_b32 [[GETREG:s[0-9]+]], hwreg(HW_REG_TRAPSTS, 8, 1)
; LOOP-NEXT: s_cmp_lg_u32 [[GETREG]], 0 ; LOOP-NEXT: s_cmp_lg_u32 [[GETREG]], 0
; LOOP-NEXT: s_cbranch_scc1 [[LOOP]] ; LOOP-NEXT: s_cbranch_scc1 [[LOOP]]
define amdgpu_kernel void @gws_sema_br_offset0(i32 %val) #0 { define amdgpu_kernel void @gws_sema_br_offset0(i32 %val) #0 {
call void @llvm.amdgcn.ds.gws.sema.br(i32 %val, i32 0) call void @llvm.amdgcn.ds.gws.sema.br(i32 %val, i32 0)
ret void ret void
} }
declare void @llvm.amdgcn.ds.gws.sema.br(i32, i32) #0 declare void @llvm.amdgcn.ds.gws.sema.br(i32, i32) #0
attributes #0 = { convergent inaccessiblememonly nounwind } attributes #0 = { convergent inaccessiblememonly nounwind }

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.p.ll

; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %s
; GCN-LABEL: {{^}}gws_sema_p_offset0: ; GCN-LABEL: {{^}}gws_sema_p_offset0:
; NOLOOP-DAG: s_mov_b32 m0, 0{{$}} ; NOLOOP-DAG: s_mov_b32 m0, 0{{$}}
; NOLOOP: ds_gws_sema_p gds{{$}} ; NOLOOP: ds_gws_sema_p gds{{$}}
; LOOP: s_mov_b32 m0, 0{{$}} ; LOOP: s_mov_b32 m0, 0{{$}}
; LOOP: [[LOOP:BB[0-9]+_[0-9]+]]: ; LOOP: [[LOOP:.LBB[0-9]+_[0-9]+]]:
; LOOP-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, 8, 1), 0 ; LOOP-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, 8, 1), 0
; LOOP-NEXT: ds_gws_sema_p gds ; LOOP-NEXT: ds_gws_sema_p gds
; LOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; LOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; LOOP-NEXT: s_getreg_b32 [[GETREG:s[0-9]+]], hwreg(HW_REG_TRAPSTS, 8, 1) ; LOOP-NEXT: s_getreg_b32 [[GETREG:s[0-9]+]], hwreg(HW_REG_TRAPSTS, 8, 1)
; LOOP-NEXT: s_cmp_lg_u32 [[GETREG]], 0 ; LOOP-NEXT: s_cmp_lg_u32 [[GETREG]], 0
; LOOP-NEXT: s_cbranch_scc1 [[LOOP]] ; LOOP-NEXT: s_cbranch_scc1 [[LOOP]]
define amdgpu_kernel void @gws_sema_p_offset0(i32 %val) #0 { define amdgpu_kernel void @gws_sema_p_offset0(i32 %val) #0 {
call void @llvm.amdgcn.ds.gws.sema.p(i32 0) call void @llvm.amdgcn.ds.gws.sema.p(i32 0)
ret void ret void
} }
declare void @llvm.amdgcn.ds.gws.sema.p(i32) #0 declare void @llvm.amdgcn.ds.gws.sema.p(i32) #0
attributes #0 = { convergent inaccessiblememonly nounwind } attributes #0 = { convergent inaccessiblememonly nounwind }

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.release.all.ll

; RUN: not --crash llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - < %s 2>&1 | FileCheck -enable-var-scope -check-prefix=GFX6ERR-SDAG %s ; RUN: not --crash llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - < %s 2>&1 | FileCheck -enable-var-scope -check-prefix=GFX6ERR-SDAG %s
; RUN: not --crash llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - < %s 2>&1 | FileCheck -enable-var-scope -check-prefix=GFX6ERR-GISEL %s ; RUN: not --crash llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - < %s 2>&1 | FileCheck -enable-var-scope -check-prefix=GFX6ERR-GISEL %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %s
; GFX6ERR-SDAG: LLVM ERROR: Cannot select: intrinsic %llvm.amdgcn.ds.gws.sema.release.all ; GFX6ERR-SDAG: LLVM ERROR: Cannot select: intrinsic %llvm.amdgcn.ds.gws.sema.release.all
; GFX6ERR-GISEL: LLVM ERROR: cannot select: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.gws.sema.release.all), %{{[0-9]+}}:sgpr(s32) :: (store (s32) into custom "GWSResource") (in function: gws_sema_release_all_offset0) ; GFX6ERR-GISEL: LLVM ERROR: cannot select: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.gws.sema.release.all), %{{[0-9]+}}:sgpr(s32) :: (store (s32) into custom "GWSResource") (in function: gws_sema_release_all_offset0)
; GCN-LABEL: {{^}}gws_sema_release_all_offset0: ; GCN-LABEL: {{^}}gws_sema_release_all_offset0:
; NOLOOP-DAG: s_mov_b32 m0, 0{{$}} ; NOLOOP-DAG: s_mov_b32 m0, 0{{$}}
; NOLOOP: ds_gws_sema_release_all gds{{$}} ; NOLOOP: ds_gws_sema_release_all gds{{$}}
; LOOP: s_mov_b32 m0, 0{{$}} ; LOOP: s_mov_b32 m0, 0{{$}}
; LOOP: [[LOOP:BB[0-9]+_[0-9]+]]: ; LOOP: [[LOOP:.LBB[0-9]+_[0-9]+]]:
; LOOP-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, 8, 1), 0 ; LOOP-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, 8, 1), 0
; LOOP-NEXT: ds_gws_sema_release_all gds ; LOOP-NEXT: ds_gws_sema_release_all gds
; LOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; LOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; LOOP-NEXT: s_getreg_b32 [[GETREG:s[0-9]+]], hwreg(HW_REG_TRAPSTS, 8, 1) ; LOOP-NEXT: s_getreg_b32 [[GETREG:s[0-9]+]], hwreg(HW_REG_TRAPSTS, 8, 1)
; LOOP-NEXT: s_cmp_lg_u32 [[GETREG]], 0 ; LOOP-NEXT: s_cmp_lg_u32 [[GETREG]], 0
; LOOP-NEXT: s_cbranch_scc1 [[LOOP]] ; LOOP-NEXT: s_cbranch_scc1 [[LOOP]]
define amdgpu_kernel void @gws_sema_release_all_offset0(i32 %val) #0 { define amdgpu_kernel void @gws_sema_release_all_offset0(i32 %val) #0 {
call void @llvm.amdgcn.ds.gws.sema.release.all(i32 0) call void @llvm.amdgcn.ds.gws.sema.release.all(i32 0)
ret void ret void
} }
declare void @llvm.amdgcn.ds.gws.sema.release.all(i32) #0 declare void @llvm.amdgcn.ds.gws.sema.release.all(i32) #0
attributes #0 = { convergent inaccessiblememonly nounwind } attributes #0 = { convergent inaccessiblememonly nounwind }

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.v.ll

; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %s
; GCN-LABEL: {{^}}gws_sema_v_offset0: ; GCN-LABEL: {{^}}gws_sema_v_offset0:
; NOLOOP-DAG: s_mov_b32 m0, 0{{$}} ; NOLOOP-DAG: s_mov_b32 m0, 0{{$}}
; NOLOOP: ds_gws_sema_v gds{{$}} ; NOLOOP: ds_gws_sema_v gds{{$}}
; LOOP: s_mov_b32 m0, 0{{$}} ; LOOP: s_mov_b32 m0, 0{{$}}
; LOOP: [[LOOP:BB[0-9]+_[0-9]+]]: ; LOOP: [[LOOP:.LBB[0-9]+_[0-9]+]]:
; LOOP-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, 8, 1), 0 ; LOOP-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, 8, 1), 0
; LOOP-NEXT: ds_gws_sema_v gds ; LOOP-NEXT: ds_gws_sema_v gds
; LOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; LOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; LOOP-NEXT: s_getreg_b32 [[GETREG:s[0-9]+]], hwreg(HW_REG_TRAPSTS, 8, 1) ; LOOP-NEXT: s_getreg_b32 [[GETREG:s[0-9]+]], hwreg(HW_REG_TRAPSTS, 8, 1)
; LOOP-NEXT: s_cmp_lg_u32 [[GETREG]], 0 ; LOOP-NEXT: s_cmp_lg_u32 [[GETREG]], 0
; LOOP-NEXT: s_cbranch_scc1 [[LOOP]] ; LOOP-NEXT: s_cbranch_scc1 [[LOOP]]
define amdgpu_kernel void @gws_sema_v_offset0(i32 %val) #0 { define amdgpu_kernel void @gws_sema_v_offset0(i32 %val) #0 {
call void @llvm.amdgcn.ds.gws.sema.v(i32 0) call void @llvm.amdgcn.ds.gws.sema.v(i32 0)
ret void ret void
} }
declare void @llvm.amdgcn.ds.gws.sema.v(i32) #0 declare void @llvm.amdgcn.ds.gws.sema.v(i32) #0
attributes #0 = { convergent inaccessiblememonly nounwind } attributes #0 = { convergent inaccessiblememonly nounwind }

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll

Show All 12 Linesdefine amdgpu_cs float @ds_ordered_swap(i32 addrspace(2)* inreg %gds, i32 %value) {
%r = bitcast i32 %val to float %r = bitcast i32 %val to float
ret float %r ret float %r
} }
; FUNC-LABEL: {{^}}ds_ordered_swap_conditional: ; FUNC-LABEL: {{^}}ds_ordered_swap_conditional:
; GCN: v_cmp_ne_u32_e32 vcc, 0, v[[VALUE:[0-9]+]] ; GCN: v_cmp_ne_u32_e32 vcc, 0, v[[VALUE:[0-9]+]]
; GCN: s_and_saveexec_b64 s[[SAVED:\[[0-9]+:[0-9]+\]]], vcc ; GCN: s_and_saveexec_b64 s[[SAVED:\[[0-9]+:[0-9]+\]]], vcc
; // We have to use s_cbranch, because ds_ordered_count has side effects with EXEC=0 ; // We have to use s_cbranch, because ds_ordered_count has side effects with EXEC=0
; GCN: s_cbranch_execz [[BB:BB._.]] ; GCN: s_cbranch_execz [[BB:.LBB._.]]
; GCN: s_mov_b32 m0, s0 ; GCN: s_mov_b32 m0, s0
; VIGFX9-NEXT: s_nop 0 ; VIGFX9-NEXT: s_nop 0
; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[VALUE]] offset:4868 gds ; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[VALUE]] offset:4868 gds
; GCN-NEXT: [[BB]]: ; GCN-NEXT: [[BB]]:
; // Wait for expcnt(0) before modifying EXEC ; // Wait for expcnt(0) before modifying EXEC
; GCN-NEXT: s_waitcnt expcnt(0) ; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: s_or_b64 exec, exec, s[[SAVED]] ; GCN-NEXT: s_or_b64 exec, exec, s[[SAVED]]
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
Show All 16 Lines

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll

Show First 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; GCN-NEXT: s_buffer_load_dword s0, s[0:3], 0x0 ; GCN-NEXT: s_buffer_load_dword s0, s[0:3], 0x0
; GCN-NEXT: v_mov_b32_e32 v0, s6 ; GCN-NEXT: v_mov_b32_e32 v0, s6
; GCN-NEXT: s_not_b64 exec, exec ; GCN-NEXT: s_not_b64 exec, exec
; GCN-NEXT: v_mov_b32_e32 v0, 42 ; GCN-NEXT: v_mov_b32_e32 v0, 42
; GCN-NEXT: s_not_b64 exec, exec ; GCN-NEXT: s_not_b64 exec, exec
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_cmp_lg_u32 s0, 56 ; GCN-NEXT: s_cmp_lg_u32 s0, 56
; GCN-NEXT: s_mov_b64 s[0:1], -1 ; GCN-NEXT: s_mov_b64 s[0:1], -1
; GCN-NEXT: s_cbranch_scc1 BB2_3 ; GCN-NEXT: s_cbranch_scc1 .LBB2_3
; GCN-NEXT: ; %bb.1: ; %Flow ; GCN-NEXT: ; %bb.1: ; %Flow
; GCN-NEXT: s_andn2_b64 vcc, exec, s[0:1] ; GCN-NEXT: s_andn2_b64 vcc, exec, s[0:1]
; GCN-NEXT: s_cbranch_vccz BB2_4 ; GCN-NEXT: s_cbranch_vccz .LBB2_4
; GCN-NEXT: BB2_2: ; %.exit ; GCN-NEXT: .LBB2_2: ; %.exit
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; GCN-NEXT: BB2_3: ; %.one ; GCN-NEXT: .LBB2_3: ; %.one
; GCN-NEXT: v_add_u32_e32 v1, vcc, 1, v0 ; GCN-NEXT: v_add_u32_e32 v1, vcc, 1, v0
; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: buffer_store_dword v1, off, s[4:7], 0 ; GCN-NEXT: buffer_store_dword v1, off, s[4:7], 0
; GCN-NEXT: s_cbranch_execnz BB2_2 ; GCN-NEXT: s_cbranch_execnz .LBB2_2
; GCN-NEXT: BB2_4: ; %.zero ; GCN-NEXT: .LBB2_4: ; %.zero
; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
%val = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 0, i32 0) %val = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 0, i32 0)
%cmp = icmp eq i32 %val, 56 %cmp = icmp eq i32 %val, 56
%tmp = call i32 @llvm.amdgcn.set.inactive.i32(i32 %in, i32 42) #0 %tmp = call i32 @llvm.amdgcn.set.inactive.i32(i32 %in, i32 42) #0
br i1 %cmp, label %.zero, label %.one br i1 %cmp, label %.zero, label %.one
Show All 19 Lines

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=gfx1010 -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s ; RUN: llc -mcpu=gfx1010 -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
; RUN: llc -mcpu=gfx900 -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 %s ; RUN: llc -mcpu=gfx900 -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 %s
; RUN: llc -mcpu=gfx810 -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8 %s ; RUN: llc -mcpu=gfx810 -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8 %s
@esgs_ring = external addrspace(3) global [0 x i32], align 65536 @esgs_ring = external addrspace(3) global [0 x i32], align 65536
define amdgpu_gs void @main(<4 x i32> %arg, i32 %arg1) { define amdgpu_gs void @main(<4 x i32> %arg, i32 %arg1) {
; GFX10-LABEL: main: ; GFX10-LABEL: main:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_mov_b32 s1, exec_lo ; GFX10-NEXT: s_mov_b32 s1, exec_lo
; GFX10-NEXT: BB0_1: ; =>This Inner Loop Header: Depth=1 ; GFX10-NEXT: .LBB0_1: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_readfirstlane_b32 s4, v0 ; GFX10-NEXT: v_readfirstlane_b32 s4, v0
; GFX10-NEXT: v_readfirstlane_b32 s5, v1 ; GFX10-NEXT: v_readfirstlane_b32 s5, v1
; GFX10-NEXT: v_readfirstlane_b32 s6, v2 ; GFX10-NEXT: v_readfirstlane_b32 s6, v2
; GFX10-NEXT: v_readfirstlane_b32 s7, v3 ; GFX10-NEXT: v_readfirstlane_b32 s7, v3
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1] ; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX10-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3] ; GFX10-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX10-NEXT: s_and_b32 s0, vcc_lo, s0 ; GFX10-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX10-NEXT: s_and_saveexec_b32 s0, s0 ; GFX10-NEXT: s_and_saveexec_b32 s0, s0
; GFX10-NEXT: buffer_load_format_d16_xyz v[5:6], v4, s[4:7], 0 idxen ; GFX10-NEXT: buffer_load_format_d16_xyz v[5:6], v4, s[4:7], 0 idxen
; GFX10-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3 ; GFX10-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX10-NEXT: ; implicit-def: $vgpr4 ; GFX10-NEXT: ; implicit-def: $vgpr4
; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s0 ; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX10-NEXT: s_cbranch_execnz BB0_1 ; GFX10-NEXT: s_cbranch_execnz .LBB0_1
; GFX10-NEXT: ; %bb.2: ; GFX10-NEXT: ; %bb.2:
; GFX10-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-NEXT: s_mov_b32 exec_lo, s1
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v5 ; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v5
; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v6 ; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v6
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: ds_write2_b32 v2, v0, v1 offset0:7 offset1:8 ; GFX10-NEXT: ds_write2_b32 v2, v0, v1 offset0:7 offset1:8
; ;
; GFX9-LABEL: main: ; GFX9-LABEL: main:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_mov_b64 s[2:3], exec ; GFX9-NEXT: s_mov_b64 s[2:3], exec
; GFX9-NEXT: BB0_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-NEXT: .LBB0_1: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_readfirstlane_b32 s4, v0 ; GFX9-NEXT: v_readfirstlane_b32 s4, v0
; GFX9-NEXT: v_readfirstlane_b32 s5, v1 ; GFX9-NEXT: v_readfirstlane_b32 s5, v1
; GFX9-NEXT: v_readfirstlane_b32 s6, v2 ; GFX9-NEXT: v_readfirstlane_b32 s6, v2
; GFX9-NEXT: v_readfirstlane_b32 s7, v3 ; GFX9-NEXT: v_readfirstlane_b32 s7, v3
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, s[4:5], v[0:1] ; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, s[4:5], v[0:1]
; GFX9-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], v[2:3] ; GFX9-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], v[2:3]
; GFX9-NEXT: s_and_b64 s[0:1], vcc, s[0:1] ; GFX9-NEXT: s_and_b64 s[0:1], vcc, s[0:1]
; GFX9-NEXT: s_and_saveexec_b64 s[0:1], s[0:1] ; GFX9-NEXT: s_and_saveexec_b64 s[0:1], s[0:1]
; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_format_d16_xyz v[5:6], v4, s[4:7], 0 idxen ; GFX9-NEXT: buffer_load_format_d16_xyz v[5:6], v4, s[4:7], 0 idxen
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3 ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9-NEXT: ; implicit-def: $vgpr4 ; GFX9-NEXT: ; implicit-def: $vgpr4
; GFX9-NEXT: s_xor_b64 exec, exec, s[0:1] ; GFX9-NEXT: s_xor_b64 exec, exec, s[0:1]
; GFX9-NEXT: s_cbranch_execnz BB0_1 ; GFX9-NEXT: s_cbranch_execnz .LBB0_1
; GFX9-NEXT: ; %bb.2: ; GFX9-NEXT: ; %bb.2:
; GFX9-NEXT: s_mov_b64 exec, s[2:3] ; GFX9-NEXT: s_mov_b64 exec, s[2:3]
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v5 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v5
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v6 ; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v6
; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: ds_write2_b32 v2, v0, v1 offset0:7 offset1:8 ; GFX9-NEXT: ds_write2_b32 v2, v0, v1 offset0:7 offset1:8
; ;
; GFX8-LABEL: main: ; GFX8-LABEL: main:
; GFX8: ; %bb.0: ; %bb ; GFX8: ; %bb.0: ; %bb
; GFX8-NEXT: s_mov_b64 s[2:3], exec ; GFX8-NEXT: s_mov_b64 s[2:3], exec
; GFX8-NEXT: BB0_1: ; =>This Inner Loop Header: Depth=1 ; GFX8-NEXT: .LBB0_1: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: v_readfirstlane_b32 s4, v0 ; GFX8-NEXT: v_readfirstlane_b32 s4, v0
; GFX8-NEXT: v_readfirstlane_b32 s5, v1 ; GFX8-NEXT: v_readfirstlane_b32 s5, v1
; GFX8-NEXT: v_readfirstlane_b32 s6, v2 ; GFX8-NEXT: v_readfirstlane_b32 s6, v2
; GFX8-NEXT: v_readfirstlane_b32 s7, v3 ; GFX8-NEXT: v_readfirstlane_b32 s7, v3
; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, s[4:5], v[0:1] ; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, s[4:5], v[0:1]
; GFX8-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], v[2:3] ; GFX8-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], v[2:3]
; GFX8-NEXT: s_and_b64 s[0:1], vcc, s[0:1] ; GFX8-NEXT: s_and_b64 s[0:1], vcc, s[0:1]
; GFX8-NEXT: s_and_saveexec_b64 s[0:1], s[0:1] ; GFX8-NEXT: s_and_saveexec_b64 s[0:1], s[0:1]
; GFX8-NEXT: s_nop 0 ; GFX8-NEXT: s_nop 0
; GFX8-NEXT: buffer_load_format_d16_xyz v[5:6], v4, s[4:7], 0 idxen ; GFX8-NEXT: buffer_load_format_d16_xyz v[5:6], v4, s[4:7], 0 idxen
; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3 ; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX8-NEXT: ; implicit-def: $vgpr4 ; GFX8-NEXT: ; implicit-def: $vgpr4
; GFX8-NEXT: s_xor_b64 exec, exec, s[0:1] ; GFX8-NEXT: s_xor_b64 exec, exec, s[0:1]
; GFX8-NEXT: s_cbranch_execnz BB0_1 ; GFX8-NEXT: s_cbranch_execnz .LBB0_1
; GFX8-NEXT: ; %bb.2: ; GFX8-NEXT: ; %bb.2:
; GFX8-NEXT: s_mov_b64 exec, s[2:3] ; GFX8-NEXT: s_mov_b64 exec, s[2:3]
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v5 ; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v5
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v6 ; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v6
; GFX8-NEXT: v_mov_b32_e32 v2, 0 ; GFX8-NEXT: v_mov_b32_e32 v2, 0
; GFX8-NEXT: s_mov_b32 m0, -1 ; GFX8-NEXT: s_mov_b32 m0, -1
; GFX8-NEXT: ds_write2_b32 v2, v0, v1 offset0:7 offset1:8 ; GFX8-NEXT: ds_write2_b32 v2, v0, v1 offset0:7 offset1:8
Show All 26 Lines

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.demote.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 %s
; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10-32 %s ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10-32 %s
; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10-64 %s ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10-64 %s
define amdgpu_ps void @static_exact(float %arg0, float %arg1) { define amdgpu_ps void @static_exact(float %arg0, float %arg1) {
; SI-LABEL: static_exact: ; SI-LABEL: static_exact:
; SI: ; %bb.0: ; %.entry ; SI: ; %bb.0: ; %.entry
; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0 ; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0
; SI-NEXT: s_andn2_b64 exec, exec, exec ; SI-NEXT: s_andn2_b64 exec, exec, exec
; SI-NEXT: s_cbranch_scc0 BB0_2 ; SI-NEXT: s_cbranch_scc0 .LBB0_2
; SI-NEXT: ; %bb.1: ; %.entry ; SI-NEXT: ; %bb.1: ; %.entry
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc ; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc
; SI-NEXT: exp mrt1 v0, v0, v0, v0 done vm ; SI-NEXT: exp mrt1 v0, v0, v0, v0 done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; SI-NEXT: BB0_2: ; SI-NEXT: .LBB0_2:
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: exp null off, off, off, off done vm ; SI-NEXT: exp null off, off, off, off done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; GFX9-LABEL: static_exact: ; GFX9-LABEL: static_exact:
; GFX9: ; %bb.0: ; %.entry ; GFX9: ; %bb.0: ; %.entry
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0
; GFX9-NEXT: s_andn2_b64 exec, exec, exec ; GFX9-NEXT: s_andn2_b64 exec, exec, exec
; GFX9-NEXT: s_cbranch_scc0 BB0_2 ; GFX9-NEXT: s_cbranch_scc0 .LBB0_2
; GFX9-NEXT: ; %bb.1: ; %.entry ; GFX9-NEXT: ; %bb.1: ; %.entry
; GFX9-NEXT: s_mov_b64 exec, 0 ; GFX9-NEXT: s_mov_b64 exec, 0
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc
; GFX9-NEXT: exp mrt1 v0, v0, v0, v0 done vm ; GFX9-NEXT: exp mrt1 v0, v0, v0, v0 done vm
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; GFX9-NEXT: BB0_2: ; GFX9-NEXT: .LBB0_2:
; GFX9-NEXT: s_mov_b64 exec, 0 ; GFX9-NEXT: s_mov_b64 exec, 0
; GFX9-NEXT: exp null off, off, off, off done vm ; GFX9-NEXT: exp null off, off, off, off done vm
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-32-LABEL: static_exact: ; GFX10-32-LABEL: static_exact:
; GFX10-32: ; %bb.0: ; %.entry ; GFX10-32: ; %bb.0: ; %.entry
; GFX10-32-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v0 ; GFX10-32-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v0
; GFX10-32-NEXT: s_andn2_b32 exec_lo, exec_lo, exec_lo ; GFX10-32-NEXT: s_andn2_b32 exec_lo, exec_lo, exec_lo
; GFX10-32-NEXT: s_cbranch_scc0 BB0_2 ; GFX10-32-NEXT: s_cbranch_scc0 .LBB0_2
; GFX10-32-NEXT: ; %bb.1: ; %.entry ; GFX10-32-NEXT: ; %bb.1: ; %.entry
; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-32-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo ; GFX10-32-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
; GFX10-32-NEXT: exp mrt1 v0, v0, v0, v0 done vm ; GFX10-32-NEXT: exp mrt1 v0, v0, v0, v0 done vm
; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: s_endpgm
; GFX10-32-NEXT: BB0_2: ; GFX10-32-NEXT: .LBB0_2:
; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-32-NEXT: exp null off, off, off, off done vm ; GFX10-32-NEXT: exp null off, off, off, off done vm
; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: s_endpgm
; ;
; GFX10-64-LABEL: static_exact: ; GFX10-64-LABEL: static_exact:
; GFX10-64: ; %bb.0: ; %.entry ; GFX10-64: ; %bb.0: ; %.entry
; GFX10-64-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0 ; GFX10-64-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0
; GFX10-64-NEXT: s_andn2_b64 exec, exec, exec ; GFX10-64-NEXT: s_andn2_b64 exec, exec, exec
; GFX10-64-NEXT: s_cbranch_scc0 BB0_2 ; GFX10-64-NEXT: s_cbranch_scc0 .LBB0_2
; GFX10-64-NEXT: ; %bb.1: ; %.entry ; GFX10-64-NEXT: ; %bb.1: ; %.entry
; GFX10-64-NEXT: s_mov_b64 exec, 0 ; GFX10-64-NEXT: s_mov_b64 exec, 0
; GFX10-64-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc ; GFX10-64-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc
; GFX10-64-NEXT: exp mrt1 v0, v0, v0, v0 done vm ; GFX10-64-NEXT: exp mrt1 v0, v0, v0, v0 done vm
; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: s_endpgm
; GFX10-64-NEXT: BB0_2: ; GFX10-64-NEXT: .LBB0_2:
; GFX10-64-NEXT: s_mov_b64 exec, 0 ; GFX10-64-NEXT: s_mov_b64 exec, 0
; GFX10-64-NEXT: exp null off, off, off, off done vm ; GFX10-64-NEXT: exp null off, off, off, off done vm
; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: s_endpgm
.entry: .entry:
%c0 = fcmp olt float %arg0, 0.000000e+00 %c0 = fcmp olt float %arg0, 0.000000e+00
%c1 = fcmp oge float %arg1, 0.0 %c1 = fcmp oge float %arg1, 0.0
call void @llvm.amdgcn.wqm.demote(i1 false) call void @llvm.amdgcn.wqm.demote(i1 false)
%tmp1 = select i1 %c0, float 1.000000e+00, float 0.000000e+00 %tmp1 = select i1 %c0, float 1.000000e+00, float 0.000000e+00
call void @llvm.amdgcn.exp.f32(i32 1, i32 15, float %tmp1, float %tmp1, float %tmp1, float %tmp1, i1 true, i1 true) #0 call void @llvm.amdgcn.exp.f32(i32 1, i32 15, float %tmp1, float %tmp1, float %tmp1, float %tmp1, i1 true, i1 true) #0
ret void ret void
} }
define amdgpu_ps void @dynamic_exact(float %arg0, float %arg1) { define amdgpu_ps void @dynamic_exact(float %arg0, float %arg1) {
; SI-LABEL: dynamic_exact: ; SI-LABEL: dynamic_exact:
; SI: ; %bb.0: ; %.entry ; SI: ; %bb.0: ; %.entry
; SI-NEXT: v_cmp_le_f32_e64 s[0:1], 0, v1 ; SI-NEXT: v_cmp_le_f32_e64 s[0:1], 0, v1
; SI-NEXT: s_mov_b64 s[2:3], exec ; SI-NEXT: s_mov_b64 s[2:3], exec
; SI-NEXT: s_xor_b64 s[0:1], s[0:1], exec ; SI-NEXT: s_xor_b64 s[0:1], s[0:1], exec
; SI-NEXT: s_andn2_b64 s[2:3], s[2:3], s[0:1] ; SI-NEXT: s_andn2_b64 s[2:3], s[2:3], s[0:1]
; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0 ; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0
; SI-NEXT: s_cbranch_scc0 BB1_2 ; SI-NEXT: s_cbranch_scc0 .LBB1_2
; SI-NEXT: ; %bb.1: ; %.entry ; SI-NEXT: ; %bb.1: ; %.entry
; SI-NEXT: s_and_b64 exec, exec, s[2:3] ; SI-NEXT: s_and_b64 exec, exec, s[2:3]
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc ; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc
; SI-NEXT: exp mrt1 v0, v0, v0, v0 done vm ; SI-NEXT: exp mrt1 v0, v0, v0, v0 done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; SI-NEXT: BB1_2: ; SI-NEXT: .LBB1_2:
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: exp null off, off, off, off done vm ; SI-NEXT: exp null off, off, off, off done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; GFX9-LABEL: dynamic_exact: ; GFX9-LABEL: dynamic_exact:
; GFX9: ; %bb.0: ; %.entry ; GFX9: ; %bb.0: ; %.entry
; GFX9-NEXT: v_cmp_le_f32_e64 s[0:1], 0, v1 ; GFX9-NEXT: v_cmp_le_f32_e64 s[0:1], 0, v1
; GFX9-NEXT: s_mov_b64 s[2:3], exec ; GFX9-NEXT: s_mov_b64 s[2:3], exec
; GFX9-NEXT: s_xor_b64 s[0:1], s[0:1], exec ; GFX9-NEXT: s_xor_b64 s[0:1], s[0:1], exec
; GFX9-NEXT: s_andn2_b64 s[2:3], s[2:3], s[0:1] ; GFX9-NEXT: s_andn2_b64 s[2:3], s[2:3], s[0:1]
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0
; GFX9-NEXT: s_cbranch_scc0 BB1_2 ; GFX9-NEXT: s_cbranch_scc0 .LBB1_2
; GFX9-NEXT: ; %bb.1: ; %.entry ; GFX9-NEXT: ; %bb.1: ; %.entry
; GFX9-NEXT: s_and_b64 exec, exec, s[2:3] ; GFX9-NEXT: s_and_b64 exec, exec, s[2:3]
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc
; GFX9-NEXT: exp mrt1 v0, v0, v0, v0 done vm ; GFX9-NEXT: exp mrt1 v0, v0, v0, v0 done vm
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; GFX9-NEXT: BB1_2: ; GFX9-NEXT: .LBB1_2:
; GFX9-NEXT: s_mov_b64 exec, 0 ; GFX9-NEXT: s_mov_b64 exec, 0
; GFX9-NEXT: exp null off, off, off, off done vm ; GFX9-NEXT: exp null off, off, off, off done vm
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-32-LABEL: dynamic_exact: ; GFX10-32-LABEL: dynamic_exact:
; GFX10-32: ; %bb.0: ; %.entry ; GFX10-32: ; %bb.0: ; %.entry
; GFX10-32-NEXT: v_cmp_le_f32_e64 s0, 0, v1 ; GFX10-32-NEXT: v_cmp_le_f32_e64 s0, 0, v1
; GFX10-32-NEXT: s_mov_b32 s1, exec_lo ; GFX10-32-NEXT: s_mov_b32 s1, exec_lo
; GFX10-32-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v0 ; GFX10-32-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v0
; GFX10-32-NEXT: s_xor_b32 s0, s0, exec_lo ; GFX10-32-NEXT: s_xor_b32 s0, s0, exec_lo
; GFX10-32-NEXT: s_andn2_b32 s1, s1, s0 ; GFX10-32-NEXT: s_andn2_b32 s1, s1, s0
; GFX10-32-NEXT: s_cbranch_scc0 BB1_2 ; GFX10-32-NEXT: s_cbranch_scc0 .LBB1_2
; GFX10-32-NEXT: ; %bb.1: ; %.entry ; GFX10-32-NEXT: ; %bb.1: ; %.entry
; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s1 ; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s1
; GFX10-32-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo ; GFX10-32-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
; GFX10-32-NEXT: exp mrt1 v0, v0, v0, v0 done vm ; GFX10-32-NEXT: exp mrt1 v0, v0, v0, v0 done vm
; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: s_endpgm
; GFX10-32-NEXT: BB1_2: ; GFX10-32-NEXT: .LBB1_2:
; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-32-NEXT: exp null off, off, off, off done vm ; GFX10-32-NEXT: exp null off, off, off, off done vm
; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: s_endpgm
; ;
; GFX10-64-LABEL: dynamic_exact: ; GFX10-64-LABEL: dynamic_exact:
; GFX10-64: ; %bb.0: ; %.entry ; GFX10-64: ; %bb.0: ; %.entry
; GFX10-64-NEXT: v_cmp_le_f32_e64 s[0:1], 0, v1 ; GFX10-64-NEXT: v_cmp_le_f32_e64 s[0:1], 0, v1
; GFX10-64-NEXT: s_mov_b64 s[2:3], exec ; GFX10-64-NEXT: s_mov_b64 s[2:3], exec
; GFX10-64-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0 ; GFX10-64-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0
; GFX10-64-NEXT: s_xor_b64 s[0:1], s[0:1], exec ; GFX10-64-NEXT: s_xor_b64 s[0:1], s[0:1], exec
; GFX10-64-NEXT: s_andn2_b64 s[2:3], s[2:3], s[0:1] ; GFX10-64-NEXT: s_andn2_b64 s[2:3], s[2:3], s[0:1]
; GFX10-64-NEXT: s_cbranch_scc0 BB1_2 ; GFX10-64-NEXT: s_cbranch_scc0 .LBB1_2
; GFX10-64-NEXT: ; %bb.1: ; %.entry ; GFX10-64-NEXT: ; %bb.1: ; %.entry
; GFX10-64-NEXT: s_and_b64 exec, exec, s[2:3] ; GFX10-64-NEXT: s_and_b64 exec, exec, s[2:3]
; GFX10-64-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc ; GFX10-64-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc
; GFX10-64-NEXT: exp mrt1 v0, v0, v0, v0 done vm ; GFX10-64-NEXT: exp mrt1 v0, v0, v0, v0 done vm
; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: s_endpgm
; GFX10-64-NEXT: BB1_2: ; GFX10-64-NEXT: .LBB1_2:
; GFX10-64-NEXT: s_mov_b64 exec, 0 ; GFX10-64-NEXT: s_mov_b64 exec, 0
; GFX10-64-NEXT: exp null off, off, off, off done vm ; GFX10-64-NEXT: exp null off, off, off, off done vm
; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: s_endpgm
.entry: .entry:
%c0 = fcmp olt float %arg0, 0.000000e+00 %c0 = fcmp olt float %arg0, 0.000000e+00
%c1 = fcmp oge float %arg1, 0.0 %c1 = fcmp oge float %arg1, 0.0
call void @llvm.amdgcn.wqm.demote(i1 %c1) call void @llvm.amdgcn.wqm.demote(i1 %c1)
%tmp1 = select i1 %c0, float 1.000000e+00, float 0.000000e+00 %tmp1 = select i1 %c0, float 1.000000e+00, float 0.000000e+00
Show All 9 Lines
; SI-NEXT: s_mov_b64 s[2:3], exec ; SI-NEXT: s_mov_b64 s[2:3], exec
; SI-NEXT: v_or_b32_e32 v0, v0, v1 ; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 1, v0 ; SI-NEXT: v_and_b32_e32 v1, 1, v0
; SI-NEXT: v_and_b32_e32 v0, 1, v0 ; SI-NEXT: v_and_b32_e32 v0, 1, v0
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; SI-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v0 ; SI-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v0
; SI-NEXT: s_and_saveexec_b64 s[4:5], s[0:1] ; SI-NEXT: s_and_saveexec_b64 s[4:5], s[0:1]
; SI-NEXT: s_xor_b64 s[0:1], exec, s[4:5] ; SI-NEXT: s_xor_b64 s[0:1], exec, s[4:5]
; SI-NEXT: s_cbranch_execz BB2_3 ; SI-NEXT: s_cbranch_execz .LBB2_3
; SI-NEXT: ; %bb.1: ; %.demote ; SI-NEXT: ; %bb.1: ; %.demote
; SI-NEXT: s_andn2_b64 s[2:3], s[2:3], exec ; SI-NEXT: s_andn2_b64 s[2:3], s[2:3], exec
; SI-NEXT: s_cbranch_scc0 BB2_4 ; SI-NEXT: s_cbranch_scc0 .LBB2_4
; SI-NEXT: ; %bb.2: ; %.demote ; SI-NEXT: ; %bb.2: ; %.demote
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: BB2_3: ; %.continue ; SI-NEXT: .LBB2_3: ; %.continue
; SI-NEXT: s_or_b64 exec, exec, s[0:1] ; SI-NEXT: s_or_b64 exec, exec, s[0:1]
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc ; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc
; SI-NEXT: exp mrt1 v0, v0, v0, v0 done vm ; SI-NEXT: exp mrt1 v0, v0, v0, v0 done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; SI-NEXT: BB2_4: ; SI-NEXT: .LBB2_4:
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: exp null off, off, off, off done vm ; SI-NEXT: exp null off, off, off, off done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; GFX9-LABEL: branch: ; GFX9-LABEL: branch:
; GFX9: ; %bb.0: ; %.entry ; GFX9: ; %bb.0: ; %.entry
; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_i32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX9-NEXT: s_mov_b64 s[2:3], exec ; GFX9-NEXT: s_mov_b64 s[2:3], exec
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: v_and_b32_e32 v1, 1, v0 ; GFX9-NEXT: v_and_b32_e32 v1, 1, v0
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v0 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v0
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], s[0:1] ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_xor_b64 s[0:1], exec, s[4:5] ; GFX9-NEXT: s_xor_b64 s[0:1], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz BB2_3 ; GFX9-NEXT: s_cbranch_execz .LBB2_3
; GFX9-NEXT: ; %bb.1: ; %.demote ; GFX9-NEXT: ; %bb.1: ; %.demote
; GFX9-NEXT: s_andn2_b64 s[2:3], s[2:3], exec ; GFX9-NEXT: s_andn2_b64 s[2:3], s[2:3], exec
; GFX9-NEXT: s_cbranch_scc0 BB2_4 ; GFX9-NEXT: s_cbranch_scc0 .LBB2_4
; GFX9-NEXT: ; %bb.2: ; %.demote ; GFX9-NEXT: ; %bb.2: ; %.demote
; GFX9-NEXT: s_mov_b64 exec, 0 ; GFX9-NEXT: s_mov_b64 exec, 0
; GFX9-NEXT: BB2_3: ; %.continue ; GFX9-NEXT: .LBB2_3: ; %.continue
; GFX9-NEXT: s_or_b64 exec, exec, s[0:1] ; GFX9-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc
; GFX9-NEXT: exp mrt1 v0, v0, v0, v0 done vm ; GFX9-NEXT: exp mrt1 v0, v0, v0, v0 done vm
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; GFX9-NEXT: BB2_4: ; GFX9-NEXT: .LBB2_4:
; GFX9-NEXT: s_mov_b64 exec, 0 ; GFX9-NEXT: s_mov_b64 exec, 0
; GFX9-NEXT: exp null off, off, off, off done vm ; GFX9-NEXT: exp null off, off, off, off done vm
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-32-LABEL: branch: ; GFX10-32-LABEL: branch:
; GFX10-32: ; %bb.0: ; %.entry ; GFX10-32: ; %bb.0: ; %.entry
; GFX10-32-NEXT: v_cvt_i32_f32_e32 v0, v0 ; GFX10-32-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX10-32-NEXT: v_cvt_i32_f32_e32 v1, v1 ; GFX10-32-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX10-32-NEXT: s_mov_b32 s1, exec_lo ; GFX10-32-NEXT: s_mov_b32 s1, exec_lo
; GFX10-32-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX10-32-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-32-NEXT: v_and_b32_e32 v1, 1, v0 ; GFX10-32-NEXT: v_and_b32_e32 v1, 1, v0
; GFX10-32-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX10-32-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 ; GFX10-32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
; GFX10-32-NEXT: v_cmp_eq_u32_e64 s0, 1, v0 ; GFX10-32-NEXT: v_cmp_eq_u32_e64 s0, 1, v0
; GFX10-32-NEXT: s_and_saveexec_b32 s2, s0 ; GFX10-32-NEXT: s_and_saveexec_b32 s2, s0
; GFX10-32-NEXT: s_xor_b32 s0, exec_lo, s2 ; GFX10-32-NEXT: s_xor_b32 s0, exec_lo, s2
; GFX10-32-NEXT: s_cbranch_execz BB2_3 ; GFX10-32-NEXT: s_cbranch_execz .LBB2_3
; GFX10-32-NEXT: ; %bb.1: ; %.demote ; GFX10-32-NEXT: ; %bb.1: ; %.demote
; GFX10-32-NEXT: s_andn2_b32 s1, s1, exec_lo ; GFX10-32-NEXT: s_andn2_b32 s1, s1, exec_lo
; GFX10-32-NEXT: s_cbranch_scc0 BB2_4 ; GFX10-32-NEXT: s_cbranch_scc0 .LBB2_4
; GFX10-32-NEXT: ; %bb.2: ; %.demote ; GFX10-32-NEXT: ; %bb.2: ; %.demote
; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-32-NEXT: BB2_3: ; %.continue ; GFX10-32-NEXT: .LBB2_3: ; %.continue
; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s0 ; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX10-32-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo ; GFX10-32-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
; GFX10-32-NEXT: exp mrt1 v0, v0, v0, v0 done vm ; GFX10-32-NEXT: exp mrt1 v0, v0, v0, v0 done vm
; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: s_endpgm
; GFX10-32-NEXT: BB2_4: ; GFX10-32-NEXT: .LBB2_4:
; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-32-NEXT: exp null off, off, off, off done vm ; GFX10-32-NEXT: exp null off, off, off, off done vm
; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: s_endpgm
; ;
; GFX10-64-LABEL: branch: ; GFX10-64-LABEL: branch:
; GFX10-64: ; %bb.0: ; %.entry ; GFX10-64: ; %bb.0: ; %.entry
; GFX10-64-NEXT: v_cvt_i32_f32_e32 v0, v0 ; GFX10-64-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX10-64-NEXT: v_cvt_i32_f32_e32 v1, v1 ; GFX10-64-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX10-64-NEXT: s_mov_b64 s[2:3], exec ; GFX10-64-NEXT: s_mov_b64 s[2:3], exec
; GFX10-64-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX10-64-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-64-NEXT: v_and_b32_e32 v1, 1, v0 ; GFX10-64-NEXT: v_and_b32_e32 v1, 1, v0
; GFX10-64-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX10-64-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; GFX10-64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; GFX10-64-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v0 ; GFX10-64-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v0
; GFX10-64-NEXT: s_and_saveexec_b64 s[4:5], s[0:1] ; GFX10-64-NEXT: s_and_saveexec_b64 s[4:5], s[0:1]
; GFX10-64-NEXT: s_xor_b64 s[0:1], exec, s[4:5] ; GFX10-64-NEXT: s_xor_b64 s[0:1], exec, s[4:5]
; GFX10-64-NEXT: s_cbranch_execz BB2_3 ; GFX10-64-NEXT: s_cbranch_execz .LBB2_3
; GFX10-64-NEXT: ; %bb.1: ; %.demote ; GFX10-64-NEXT: ; %bb.1: ; %.demote
; GFX10-64-NEXT: s_andn2_b64 s[2:3], s[2:3], exec ; GFX10-64-NEXT: s_andn2_b64 s[2:3], s[2:3], exec
; GFX10-64-NEXT: s_cbranch_scc0 BB2_4 ; GFX10-64-NEXT: s_cbranch_scc0 .LBB2_4
; GFX10-64-NEXT: ; %bb.2: ; %.demote ; GFX10-64-NEXT: ; %bb.2: ; %.demote
; GFX10-64-NEXT: s_mov_b64 exec, 0 ; GFX10-64-NEXT: s_mov_b64 exec, 0
; GFX10-64-NEXT: BB2_3: ; %.continue ; GFX10-64-NEXT: .LBB2_3: ; %.continue
; GFX10-64-NEXT: s_or_b64 exec, exec, s[0:1] ; GFX10-64-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX10-64-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc ; GFX10-64-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc
; GFX10-64-NEXT: exp mrt1 v0, v0, v0, v0 done vm ; GFX10-64-NEXT: exp mrt1 v0, v0, v0, v0 done vm
; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: s_endpgm
; GFX10-64-NEXT: BB2_4: ; GFX10-64-NEXT: .LBB2_4:
; GFX10-64-NEXT: s_mov_b64 exec, 0 ; GFX10-64-NEXT: s_mov_b64 exec, 0
; GFX10-64-NEXT: exp null off, off, off, off done vm ; GFX10-64-NEXT: exp null off, off, off, off done vm
; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: s_endpgm
.entry: .entry:
%i0 = fptosi float %arg0 to i32 %i0 = fptosi float %arg0 to i32
%i1 = fptosi float %arg1 to i32 %i1 = fptosi float %arg1 to i32
%c0 = or i32 %i0, %i1 %c0 = or i32 %i0, %i1
%c1 = and i32 %c0, 1 %c1 = and i32 %c0, 1
Show All 14 Lines
define amdgpu_ps <4 x float> @wqm_demote_1(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, i32 %idx, float %data, float %coord, float %coord2, float %z) { define amdgpu_ps <4 x float> @wqm_demote_1(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, i32 %idx, float %data, float %coord, float %coord2, float %z) {
; SI-LABEL: wqm_demote_1: ; SI-LABEL: wqm_demote_1:
; SI: ; %bb.0: ; %.entry ; SI: ; %bb.0: ; %.entry
; SI-NEXT: s_mov_b64 s[12:13], exec ; SI-NEXT: s_mov_b64 s[12:13], exec
; SI-NEXT: s_wqm_b64 exec, exec ; SI-NEXT: s_wqm_b64 exec, exec
; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v1 ; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v1
; SI-NEXT: s_and_saveexec_b64 s[14:15], vcc ; SI-NEXT: s_and_saveexec_b64 s[14:15], vcc
; SI-NEXT: s_xor_b64 s[14:15], exec, s[14:15] ; SI-NEXT: s_xor_b64 s[14:15], exec, s[14:15]
; SI-NEXT: s_cbranch_execz BB3_3 ; SI-NEXT: s_cbranch_execz .LBB3_3
; SI-NEXT: ; %bb.1: ; %.demote ; SI-NEXT: ; %bb.1: ; %.demote
; SI-NEXT: s_andn2_b64 s[12:13], s[12:13], exec ; SI-NEXT: s_andn2_b64 s[12:13], s[12:13], exec
; SI-NEXT: s_cbranch_scc0 BB3_4 ; SI-NEXT: s_cbranch_scc0 .LBB3_4
; SI-NEXT: ; %bb.2: ; %.demote ; SI-NEXT: ; %bb.2: ; %.demote
; SI-NEXT: s_wqm_b64 s[16:17], s[12:13] ; SI-NEXT: s_wqm_b64 s[16:17], s[12:13]
; SI-NEXT: s_and_b64 exec, exec, s[16:17] ; SI-NEXT: s_and_b64 exec, exec, s[16:17]
; SI-NEXT: BB3_3: ; %.continue ; SI-NEXT: .LBB3_3: ; %.continue
; SI-NEXT: s_or_b64 exec, exec, s[14:15] ; SI-NEXT: s_or_b64 exec, exec, s[14:15]
; SI-NEXT: image_sample v0, v0, s[0:7], s[8:11] dmask:0x1 ; SI-NEXT: image_sample v0, v0, s[0:7], s[8:11] dmask:0x1
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_f32_e32 v0, v0, v0 ; SI-NEXT: v_add_f32_e32 v0, v0, v0
; SI-NEXT: s_and_b64 exec, exec, s[12:13] ; SI-NEXT: s_and_b64 exec, exec, s[12:13]
; SI-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf ; SI-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_branch BB3_5 ; SI-NEXT: s_branch .LBB3_5
; SI-NEXT: BB3_4: ; SI-NEXT: .LBB3_4:
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: exp null off, off, off, off done vm ; SI-NEXT: exp null off, off, off, off done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; SI-NEXT: BB3_5: ; SI-NEXT: .LBB3_5:
; ;
; GFX9-LABEL: wqm_demote_1: ; GFX9-LABEL: wqm_demote_1:
; GFX9: ; %bb.0: ; %.entry ; GFX9: ; %bb.0: ; %.entry
; GFX9-NEXT: s_mov_b64 s[12:13], exec ; GFX9-NEXT: s_mov_b64 s[12:13], exec
; GFX9-NEXT: s_wqm_b64 exec, exec ; GFX9-NEXT: s_wqm_b64 exec, exec
; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v1 ; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v1
; GFX9-NEXT: s_and_saveexec_b64 s[14:15], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[14:15], vcc
; GFX9-NEXT: s_xor_b64 s[14:15], exec, s[14:15] ; GFX9-NEXT: s_xor_b64 s[14:15], exec, s[14:15]
; GFX9-NEXT: s_cbranch_execz BB3_3 ; GFX9-NEXT: s_cbranch_execz .LBB3_3
; GFX9-NEXT: ; %bb.1: ; %.demote ; GFX9-NEXT: ; %bb.1: ; %.demote
; GFX9-NEXT: s_andn2_b64 s[12:13], s[12:13], exec ; GFX9-NEXT: s_andn2_b64 s[12:13], s[12:13], exec
; GFX9-NEXT: s_cbranch_scc0 BB3_4 ; GFX9-NEXT: s_cbranch_scc0 .LBB3_4
; GFX9-NEXT: ; %bb.2: ; %.demote ; GFX9-NEXT: ; %bb.2: ; %.demote
; GFX9-NEXT: s_wqm_b64 s[16:17], s[12:13] ; GFX9-NEXT: s_wqm_b64 s[16:17], s[12:13]
; GFX9-NEXT: s_and_b64 exec, exec, s[16:17] ; GFX9-NEXT: s_and_b64 exec, exec, s[16:17]
; GFX9-NEXT: BB3_3: ; %.continue ; GFX9-NEXT: .LBB3_3: ; %.continue
; GFX9-NEXT: s_or_b64 exec, exec, s[14:15] ; GFX9-NEXT: s_or_b64 exec, exec, s[14:15]
; GFX9-NEXT: image_sample v0, v0, s[0:7], s[8:11] dmask:0x1 ; GFX9-NEXT: image_sample v0, v0, s[0:7], s[8:11] dmask:0x1
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_f32_e32 v0, v0, v0 ; GFX9-NEXT: v_add_f32_e32 v0, v0, v0
; GFX9-NEXT: s_and_b64 exec, exec, s[12:13] ; GFX9-NEXT: s_and_b64 exec, exec, s[12:13]
; GFX9-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf ; GFX9-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_branch BB3_5 ; GFX9-NEXT: s_branch .LBB3_5
; GFX9-NEXT: BB3_4: ; GFX9-NEXT: .LBB3_4:
; GFX9-NEXT: s_mov_b64 exec, 0 ; GFX9-NEXT: s_mov_b64 exec, 0
; GFX9-NEXT: exp null off, off, off, off done vm ; GFX9-NEXT: exp null off, off, off, off done vm
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; GFX9-NEXT: BB3_5: ; GFX9-NEXT: .LBB3_5:
; ;
; GFX10-32-LABEL: wqm_demote_1: ; GFX10-32-LABEL: wqm_demote_1:
; GFX10-32: ; %bb.0: ; %.entry ; GFX10-32: ; %bb.0: ; %.entry
; GFX10-32-NEXT: s_mov_b32 s12, exec_lo ; GFX10-32-NEXT: s_mov_b32 s12, exec_lo
; GFX10-32-NEXT: s_wqm_b32 exec_lo, exec_lo ; GFX10-32-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX10-32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v1 ; GFX10-32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v1
; GFX10-32-NEXT: s_and_saveexec_b32 s13, vcc_lo ; GFX10-32-NEXT: s_and_saveexec_b32 s13, vcc_lo
; GFX10-32-NEXT: s_xor_b32 s13, exec_lo, s13 ; GFX10-32-NEXT: s_xor_b32 s13, exec_lo, s13
; GFX10-32-NEXT: s_cbranch_execz BB3_3 ; GFX10-32-NEXT: s_cbranch_execz .LBB3_3
; GFX10-32-NEXT: ; %bb.1: ; %.demote ; GFX10-32-NEXT: ; %bb.1: ; %.demote
; GFX10-32-NEXT: s_andn2_b32 s12, s12, exec_lo ; GFX10-32-NEXT: s_andn2_b32 s12, s12, exec_lo
; GFX10-32-NEXT: s_cbranch_scc0 BB3_4 ; GFX10-32-NEXT: s_cbranch_scc0 .LBB3_4
; GFX10-32-NEXT: ; %bb.2: ; %.demote ; GFX10-32-NEXT: ; %bb.2: ; %.demote
; GFX10-32-NEXT: s_wqm_b32 s14, s12 ; GFX10-32-NEXT: s_wqm_b32 s14, s12
; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s14 ; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s14
; GFX10-32-NEXT: BB3_3: ; %.continue ; GFX10-32-NEXT: .LBB3_3: ; %.continue
; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s13 ; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s13
; GFX10-32-NEXT: image_sample v0, v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D ; GFX10-32-NEXT: image_sample v0, v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D
; GFX10-32-NEXT: s_waitcnt vmcnt(0) ; GFX10-32-NEXT: s_waitcnt vmcnt(0)
; GFX10-32-NEXT: v_add_f32_e32 v0, v0, v0 ; GFX10-32-NEXT: v_add_f32_e32 v0, v0, v0
; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s12
; GFX10-32-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; GFX10-32-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10-32-NEXT: s_waitcnt vmcnt(0) ; GFX10-32-NEXT: s_waitcnt vmcnt(0)
; GFX10-32-NEXT: s_branch BB3_5 ; GFX10-32-NEXT: s_branch .LBB3_5
; GFX10-32-NEXT: BB3_4: ; GFX10-32-NEXT: .LBB3_4:
; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-32-NEXT: exp null off, off, off, off done vm ; GFX10-32-NEXT: exp null off, off, off, off done vm
; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: s_endpgm
; GFX10-32-NEXT: BB3_5: ; GFX10-32-NEXT: .LBB3_5:
; ;
; GFX10-64-LABEL: wqm_demote_1: ; GFX10-64-LABEL: wqm_demote_1:
; GFX10-64: ; %bb.0: ; %.entry ; GFX10-64: ; %bb.0: ; %.entry
; GFX10-64-NEXT: s_mov_b64 s[12:13], exec ; GFX10-64-NEXT: s_mov_b64 s[12:13], exec
; GFX10-64-NEXT: s_wqm_b64 exec, exec ; GFX10-64-NEXT: s_wqm_b64 exec, exec
; GFX10-64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v1 ; GFX10-64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v1
; GFX10-64-NEXT: s_and_saveexec_b64 s[14:15], vcc ; GFX10-64-NEXT: s_and_saveexec_b64 s[14:15], vcc
; GFX10-64-NEXT: s_xor_b64 s[14:15], exec, s[14:15] ; GFX10-64-NEXT: s_xor_b64 s[14:15], exec, s[14:15]
; GFX10-64-NEXT: s_cbranch_execz BB3_3 ; GFX10-64-NEXT: s_cbranch_execz .LBB3_3
; GFX10-64-NEXT: ; %bb.1: ; %.demote ; GFX10-64-NEXT: ; %bb.1: ; %.demote
; GFX10-64-NEXT: s_andn2_b64 s[12:13], s[12:13], exec ; GFX10-64-NEXT: s_andn2_b64 s[12:13], s[12:13], exec
; GFX10-64-NEXT: s_cbranch_scc0 BB3_4 ; GFX10-64-NEXT: s_cbranch_scc0 .LBB3_4
; GFX10-64-NEXT: ; %bb.2: ; %.demote ; GFX10-64-NEXT: ; %bb.2: ; %.demote
; GFX10-64-NEXT: s_wqm_b64 s[16:17], s[12:13] ; GFX10-64-NEXT: s_wqm_b64 s[16:17], s[12:13]
; GFX10-64-NEXT: s_and_b64 exec, exec, s[16:17] ; GFX10-64-NEXT: s_and_b64 exec, exec, s[16:17]
; GFX10-64-NEXT: BB3_3: ; %.continue ; GFX10-64-NEXT: .LBB3_3: ; %.continue
; GFX10-64-NEXT: s_or_b64 exec, exec, s[14:15] ; GFX10-64-NEXT: s_or_b64 exec, exec, s[14:15]
; GFX10-64-NEXT: image_sample v0, v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D ; GFX10-64-NEXT: image_sample v0, v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D
; GFX10-64-NEXT: s_waitcnt vmcnt(0) ; GFX10-64-NEXT: s_waitcnt vmcnt(0)
; GFX10-64-NEXT: v_add_f32_e32 v0, v0, v0 ; GFX10-64-NEXT: v_add_f32_e32 v0, v0, v0
; GFX10-64-NEXT: s_and_b64 exec, exec, s[12:13] ; GFX10-64-NEXT: s_and_b64 exec, exec, s[12:13]
; GFX10-64-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; GFX10-64-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10-64-NEXT: s_waitcnt vmcnt(0) ; GFX10-64-NEXT: s_waitcnt vmcnt(0)
; GFX10-64-NEXT: s_branch BB3_5 ; GFX10-64-NEXT: s_branch .LBB3_5
; GFX10-64-NEXT: BB3_4: ; GFX10-64-NEXT: .LBB3_4:
; GFX10-64-NEXT: s_mov_b64 exec, 0 ; GFX10-64-NEXT: s_mov_b64 exec, 0
; GFX10-64-NEXT: exp null off, off, off, off done vm ; GFX10-64-NEXT: exp null off, off, off, off done vm
; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: s_endpgm
; GFX10-64-NEXT: BB3_5: ; GFX10-64-NEXT: .LBB3_5:
.entry: .entry:
%z.cmp = fcmp olt float %z, 0.0 %z.cmp = fcmp olt float %z, 0.0
br i1 %z.cmp, label %.continue, label %.demote br i1 %z.cmp, label %.continue, label %.demote
.demote: .demote:
call void @llvm.amdgcn.wqm.demote(i1 false) call void @llvm.amdgcn.wqm.demote(i1 false)
br label %.continue br label %.continue
Show All 12 Lines
; SI: ; %bb.0: ; %.entry ; SI: ; %bb.0: ; %.entry
; SI-NEXT: s_mov_b64 s[12:13], exec ; SI-NEXT: s_mov_b64 s[12:13], exec
; SI-NEXT: s_wqm_b64 exec, exec ; SI-NEXT: s_wqm_b64 exec, exec
; SI-NEXT: image_sample v0, v0, s[0:7], s[8:11] dmask:0x1 ; SI-NEXT: image_sample v0, v0, s[0:7], s[8:11] dmask:0x1
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0 ; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0
; SI-NEXT: s_and_saveexec_b64 s[14:15], vcc ; SI-NEXT: s_and_saveexec_b64 s[14:15], vcc
; SI-NEXT: s_xor_b64 s[14:15], exec, s[14:15] ; SI-NEXT: s_xor_b64 s[14:15], exec, s[14:15]
; SI-NEXT: s_cbranch_execz BB4_3 ; SI-NEXT: s_cbranch_execz .LBB4_3
; SI-NEXT: ; %bb.1: ; %.demote ; SI-NEXT: ; %bb.1: ; %.demote
; SI-NEXT: s_andn2_b64 s[12:13], s[12:13], exec ; SI-NEXT: s_andn2_b64 s[12:13], s[12:13], exec
; SI-NEXT: s_cbranch_scc0 BB4_4 ; SI-NEXT: s_cbranch_scc0 .LBB4_4
; SI-NEXT: ; %bb.2: ; %.demote ; SI-NEXT: ; %bb.2: ; %.demote
; SI-NEXT: s_wqm_b64 s[16:17], s[12:13] ; SI-NEXT: s_wqm_b64 s[16:17], s[12:13]
; SI-NEXT: s_and_b64 exec, exec, s[16:17] ; SI-NEXT: s_and_b64 exec, exec, s[16:17]
; SI-NEXT: BB4_3: ; %.continue ; SI-NEXT: .LBB4_3: ; %.continue
; SI-NEXT: s_or_b64 exec, exec, s[14:15] ; SI-NEXT: s_or_b64 exec, exec, s[14:15]
; SI-NEXT: v_add_f32_e32 v0, v0, v0 ; SI-NEXT: v_add_f32_e32 v0, v0, v0
; SI-NEXT: s_and_b64 exec, exec, s[12:13] ; SI-NEXT: s_and_b64 exec, exec, s[12:13]
; SI-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf ; SI-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_branch BB4_5 ; SI-NEXT: s_branch .LBB4_5
; SI-NEXT: BB4_4: ; SI-NEXT: .LBB4_4:
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: exp null off, off, off, off done vm ; SI-NEXT: exp null off, off, off, off done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; SI-NEXT: BB4_5: ; SI-NEXT: .LBB4_5:
; ;
; GFX9-LABEL: wqm_demote_2: ; GFX9-LABEL: wqm_demote_2:
; GFX9: ; %bb.0: ; %.entry ; GFX9: ; %bb.0: ; %.entry
; GFX9-NEXT: s_mov_b64 s[12:13], exec ; GFX9-NEXT: s_mov_b64 s[12:13], exec
; GFX9-NEXT: s_wqm_b64 exec, exec ; GFX9-NEXT: s_wqm_b64 exec, exec
; GFX9-NEXT: image_sample v0, v0, s[0:7], s[8:11] dmask:0x1 ; GFX9-NEXT: image_sample v0, v0, s[0:7], s[8:11] dmask:0x1
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0
; GFX9-NEXT: s_and_saveexec_b64 s[14:15], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[14:15], vcc
; GFX9-NEXT: s_xor_b64 s[14:15], exec, s[14:15] ; GFX9-NEXT: s_xor_b64 s[14:15], exec, s[14:15]
; GFX9-NEXT: s_cbranch_execz BB4_3 ; GFX9-NEXT: s_cbranch_execz .LBB4_3
; GFX9-NEXT: ; %bb.1: ; %.demote ; GFX9-NEXT: ; %bb.1: ; %.demote
; GFX9-NEXT: s_andn2_b64 s[12:13], s[12:13], exec ; GFX9-NEXT: s_andn2_b64 s[12:13], s[12:13], exec
; GFX9-NEXT: s_cbranch_scc0 BB4_4 ; GFX9-NEXT: s_cbranch_scc0 .LBB4_4
; GFX9-NEXT: ; %bb.2: ; %.demote ; GFX9-NEXT: ; %bb.2: ; %.demote
; GFX9-NEXT: s_wqm_b64 s[16:17], s[12:13] ; GFX9-NEXT: s_wqm_b64 s[16:17], s[12:13]
; GFX9-NEXT: s_and_b64 exec, exec, s[16:17] ; GFX9-NEXT: s_and_b64 exec, exec, s[16:17]
; GFX9-NEXT: BB4_3: ; %.continue ; GFX9-NEXT: .LBB4_3: ; %.continue
; GFX9-NEXT: s_or_b64 exec, exec, s[14:15] ; GFX9-NEXT: s_or_b64 exec, exec, s[14:15]
; GFX9-NEXT: v_add_f32_e32 v0, v0, v0 ; GFX9-NEXT: v_add_f32_e32 v0, v0, v0
; GFX9-NEXT: s_and_b64 exec, exec, s[12:13] ; GFX9-NEXT: s_and_b64 exec, exec, s[12:13]
; GFX9-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf ; GFX9-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_branch BB4_5 ; GFX9-NEXT: s_branch .LBB4_5
; GFX9-NEXT: BB4_4: ; GFX9-NEXT: .LBB4_4:
; GFX9-NEXT: s_mov_b64 exec, 0 ; GFX9-NEXT: s_mov_b64 exec, 0
; GFX9-NEXT: exp null off, off, off, off done vm ; GFX9-NEXT: exp null off, off, off, off done vm
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; GFX9-NEXT: BB4_5: ; GFX9-NEXT: .LBB4_5:
; ;
; GFX10-32-LABEL: wqm_demote_2: ; GFX10-32-LABEL: wqm_demote_2:
; GFX10-32: ; %bb.0: ; %.entry ; GFX10-32: ; %bb.0: ; %.entry
; GFX10-32-NEXT: s_mov_b32 s12, exec_lo ; GFX10-32-NEXT: s_mov_b32 s12, exec_lo
; GFX10-32-NEXT: s_wqm_b32 exec_lo, exec_lo ; GFX10-32-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX10-32-NEXT: image_sample v0, v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D ; GFX10-32-NEXT: image_sample v0, v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D
; GFX10-32-NEXT: s_waitcnt vmcnt(0) ; GFX10-32-NEXT: s_waitcnt vmcnt(0)
; GFX10-32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v0 ; GFX10-32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v0
; GFX10-32-NEXT: s_and_saveexec_b32 s13, vcc_lo ; GFX10-32-NEXT: s_and_saveexec_b32 s13, vcc_lo
; GFX10-32-NEXT: s_xor_b32 s13, exec_lo, s13 ; GFX10-32-NEXT: s_xor_b32 s13, exec_lo, s13
; GFX10-32-NEXT: s_cbranch_execz BB4_3 ; GFX10-32-NEXT: s_cbranch_execz .LBB4_3
; GFX10-32-NEXT: ; %bb.1: ; %.demote ; GFX10-32-NEXT: ; %bb.1: ; %.demote
; GFX10-32-NEXT: s_andn2_b32 s12, s12, exec_lo ; GFX10-32-NEXT: s_andn2_b32 s12, s12, exec_lo
; GFX10-32-NEXT: s_cbranch_scc0 BB4_4 ; GFX10-32-NEXT: s_cbranch_scc0 .LBB4_4
; GFX10-32-NEXT: ; %bb.2: ; %.demote ; GFX10-32-NEXT: ; %bb.2: ; %.demote
; GFX10-32-NEXT: s_wqm_b32 s14, s12 ; GFX10-32-NEXT: s_wqm_b32 s14, s12
; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s14 ; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s14
; GFX10-32-NEXT: BB4_3: ; %.continue ; GFX10-32-NEXT: .LBB4_3: ; %.continue
; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s13 ; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s13
; GFX10-32-NEXT: v_add_f32_e32 v0, v0, v0 ; GFX10-32-NEXT: v_add_f32_e32 v0, v0, v0
; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s12
; GFX10-32-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; GFX10-32-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10-32-NEXT: s_waitcnt vmcnt(0) ; GFX10-32-NEXT: s_waitcnt vmcnt(0)
; GFX10-32-NEXT: s_branch BB4_5 ; GFX10-32-NEXT: s_branch .LBB4_5
; GFX10-32-NEXT: BB4_4: ; GFX10-32-NEXT: .LBB4_4:
; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-32-NEXT: exp null off, off, off, off done vm ; GFX10-32-NEXT: exp null off, off, off, off done vm
; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: s_endpgm
; GFX10-32-NEXT: BB4_5: ; GFX10-32-NEXT: .LBB4_5:
; ;
; GFX10-64-LABEL: wqm_demote_2: ; GFX10-64-LABEL: wqm_demote_2:
; GFX10-64: ; %bb.0: ; %.entry ; GFX10-64: ; %bb.0: ; %.entry
; GFX10-64-NEXT: s_mov_b64 s[12:13], exec ; GFX10-64-NEXT: s_mov_b64 s[12:13], exec
; GFX10-64-NEXT: s_wqm_b64 exec, exec ; GFX10-64-NEXT: s_wqm_b64 exec, exec
; GFX10-64-NEXT: image_sample v0, v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D ; GFX10-64-NEXT: image_sample v0, v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D
; GFX10-64-NEXT: s_waitcnt vmcnt(0) ; GFX10-64-NEXT: s_waitcnt vmcnt(0)
; GFX10-64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0 ; GFX10-64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0
; GFX10-64-NEXT: s_and_saveexec_b64 s[14:15], vcc ; GFX10-64-NEXT: s_and_saveexec_b64 s[14:15], vcc
; GFX10-64-NEXT: s_xor_b64 s[14:15], exec, s[14:15] ; GFX10-64-NEXT: s_xor_b64 s[14:15], exec, s[14:15]
; GFX10-64-NEXT: s_cbranch_execz BB4_3 ; GFX10-64-NEXT: s_cbranch_execz .LBB4_3
; GFX10-64-NEXT: ; %bb.1: ; %.demote ; GFX10-64-NEXT: ; %bb.1: ; %.demote
; GFX10-64-NEXT: s_andn2_b64 s[12:13], s[12:13], exec ; GFX10-64-NEXT: s_andn2_b64 s[12:13], s[12:13], exec
; GFX10-64-NEXT: s_cbranch_scc0 BB4_4 ; GFX10-64-NEXT: s_cbranch_scc0 .LBB4_4
; GFX10-64-NEXT: ; %bb.2: ; %.demote ; GFX10-64-NEXT: ; %bb.2: ; %.demote
; GFX10-64-NEXT: s_wqm_b64 s[16:17], s[12:13] ; GFX10-64-NEXT: s_wqm_b64 s[16:17], s[12:13]
; GFX10-64-NEXT: s_and_b64 exec, exec, s[16:17] ; GFX10-64-NEXT: s_and_b64 exec, exec, s[16:17]
; GFX10-64-NEXT: BB4_3: ; %.continue ; GFX10-64-NEXT: .LBB4_3: ; %.continue
; GFX10-64-NEXT: s_or_b64 exec, exec, s[14:15] ; GFX10-64-NEXT: s_or_b64 exec, exec, s[14:15]
; GFX10-64-NEXT: v_add_f32_e32 v0, v0, v0 ; GFX10-64-NEXT: v_add_f32_e32 v0, v0, v0
; GFX10-64-NEXT: s_and_b64 exec, exec, s[12:13] ; GFX10-64-NEXT: s_and_b64 exec, exec, s[12:13]
; GFX10-64-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; GFX10-64-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10-64-NEXT: s_waitcnt vmcnt(0) ; GFX10-64-NEXT: s_waitcnt vmcnt(0)
; GFX10-64-NEXT: s_branch BB4_5 ; GFX10-64-NEXT: s_branch .LBB4_5
; GFX10-64-NEXT: BB4_4: ; GFX10-64-NEXT: .LBB4_4:
; GFX10-64-NEXT: s_mov_b64 exec, 0 ; GFX10-64-NEXT: s_mov_b64 exec, 0
; GFX10-64-NEXT: exp null off, off, off, off done vm ; GFX10-64-NEXT: exp null off, off, off, off done vm
; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: s_endpgm
; GFX10-64-NEXT: BB4_5: ; GFX10-64-NEXT: .LBB4_5:
.entry: .entry:
%tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %coord, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0 %tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %coord, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0
%tex0 = extractelement <4 x float> %tex, i32 0 %tex0 = extractelement <4 x float> %tex, i32 0
%tex1 = extractelement <4 x float> %tex, i32 0 %tex1 = extractelement <4 x float> %tex, i32 0
%z.cmp = fcmp olt float %tex0, 0.0 %z.cmp = fcmp olt float %tex0, 0.0
br i1 %z.cmp, label %.continue, label %.demote br i1 %z.cmp, label %.continue, label %.demote
.demote: .demote:
Show All 12 Lines
; SI: ; %bb.0: ; %.entry ; SI: ; %bb.0: ; %.entry
; SI-NEXT: s_mov_b64 s[12:13], exec ; SI-NEXT: s_mov_b64 s[12:13], exec
; SI-NEXT: s_wqm_b64 exec, exec ; SI-NEXT: s_wqm_b64 exec, exec
; SI-NEXT: image_sample v0, v0, s[0:7], s[8:11] dmask:0x1 ; SI-NEXT: image_sample v0, v0, s[0:7], s[8:11] dmask:0x1
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0 ; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0
; SI-NEXT: s_xor_b64 s[14:15], vcc, exec ; SI-NEXT: s_xor_b64 s[14:15], vcc, exec
; SI-NEXT: s_andn2_b64 s[12:13], s[12:13], s[14:15] ; SI-NEXT: s_andn2_b64 s[12:13], s[12:13], s[14:15]
; SI-NEXT: s_cbranch_scc0 BB5_2 ; SI-NEXT: s_cbranch_scc0 .LBB5_2
; SI-NEXT: ; %bb.1: ; %.entry ; SI-NEXT: ; %bb.1: ; %.entry
; SI-NEXT: s_wqm_b64 s[14:15], s[12:13] ; SI-NEXT: s_wqm_b64 s[14:15], s[12:13]
; SI-NEXT: s_and_b64 exec, exec, s[14:15] ; SI-NEXT: s_and_b64 exec, exec, s[14:15]
; SI-NEXT: v_add_f32_e32 v0, v0, v0 ; SI-NEXT: v_add_f32_e32 v0, v0, v0
; SI-NEXT: s_and_b64 exec, exec, s[12:13] ; SI-NEXT: s_and_b64 exec, exec, s[12:13]
; SI-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf ; SI-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_branch BB5_3 ; SI-NEXT: s_branch .LBB5_3
; SI-NEXT: BB5_2: ; SI-NEXT: .LBB5_2:
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: exp null off, off, off, off done vm ; SI-NEXT: exp null off, off, off, off done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; SI-NEXT: BB5_3: ; SI-NEXT: .LBB5_3:
; ;
; GFX9-LABEL: wqm_demote_dynamic: ; GFX9-LABEL: wqm_demote_dynamic:
; GFX9: ; %bb.0: ; %.entry ; GFX9: ; %bb.0: ; %.entry
; GFX9-NEXT: s_mov_b64 s[12:13], exec ; GFX9-NEXT: s_mov_b64 s[12:13], exec
; GFX9-NEXT: s_wqm_b64 exec, exec ; GFX9-NEXT: s_wqm_b64 exec, exec
; GFX9-NEXT: image_sample v0, v0, s[0:7], s[8:11] dmask:0x1 ; GFX9-NEXT: image_sample v0, v0, s[0:7], s[8:11] dmask:0x1
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0
; GFX9-NEXT: s_xor_b64 s[14:15], vcc, exec ; GFX9-NEXT: s_xor_b64 s[14:15], vcc, exec
; GFX9-NEXT: s_andn2_b64 s[12:13], s[12:13], s[14:15] ; GFX9-NEXT: s_andn2_b64 s[12:13], s[12:13], s[14:15]
; GFX9-NEXT: s_cbranch_scc0 BB5_2 ; GFX9-NEXT: s_cbranch_scc0 .LBB5_2
; GFX9-NEXT: ; %bb.1: ; %.entry ; GFX9-NEXT: ; %bb.1: ; %.entry
; GFX9-NEXT: s_wqm_b64 s[14:15], s[12:13] ; GFX9-NEXT: s_wqm_b64 s[14:15], s[12:13]
; GFX9-NEXT: s_and_b64 exec, exec, s[14:15] ; GFX9-NEXT: s_and_b64 exec, exec, s[14:15]
; GFX9-NEXT: v_add_f32_e32 v0, v0, v0 ; GFX9-NEXT: v_add_f32_e32 v0, v0, v0
; GFX9-NEXT: s_and_b64 exec, exec, s[12:13] ; GFX9-NEXT: s_and_b64 exec, exec, s[12:13]
; GFX9-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf ; GFX9-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_branch BB5_3 ; GFX9-NEXT: s_branch .LBB5_3
; GFX9-NEXT: BB5_2: ; GFX9-NEXT: .LBB5_2:
; GFX9-NEXT: s_mov_b64 exec, 0 ; GFX9-NEXT: s_mov_b64 exec, 0
; GFX9-NEXT: exp null off, off, off, off done vm ; GFX9-NEXT: exp null off, off, off, off done vm
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; GFX9-NEXT: BB5_3: ; GFX9-NEXT: .LBB5_3:
; ;
; GFX10-32-LABEL: wqm_demote_dynamic: ; GFX10-32-LABEL: wqm_demote_dynamic:
; GFX10-32: ; %bb.0: ; %.entry ; GFX10-32: ; %bb.0: ; %.entry
; GFX10-32-NEXT: s_mov_b32 s12, exec_lo ; GFX10-32-NEXT: s_mov_b32 s12, exec_lo
; GFX10-32-NEXT: s_wqm_b32 exec_lo, exec_lo ; GFX10-32-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX10-32-NEXT: image_sample v0, v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D ; GFX10-32-NEXT: image_sample v0, v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D
; GFX10-32-NEXT: s_waitcnt vmcnt(0) ; GFX10-32-NEXT: s_waitcnt vmcnt(0)
; GFX10-32-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v0 ; GFX10-32-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v0
; GFX10-32-NEXT: s_xor_b32 s13, vcc_lo, exec_lo ; GFX10-32-NEXT: s_xor_b32 s13, vcc_lo, exec_lo
; GFX10-32-NEXT: s_andn2_b32 s12, s12, s13 ; GFX10-32-NEXT: s_andn2_b32 s12, s12, s13
; GFX10-32-NEXT: s_cbranch_scc0 BB5_2 ; GFX10-32-NEXT: s_cbranch_scc0 .LBB5_2
; GFX10-32-NEXT: ; %bb.1: ; %.entry ; GFX10-32-NEXT: ; %bb.1: ; %.entry
; GFX10-32-NEXT: s_wqm_b32 s13, s12 ; GFX10-32-NEXT: s_wqm_b32 s13, s12
; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s13 ; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s13
; GFX10-32-NEXT: v_add_f32_e32 v0, v0, v0 ; GFX10-32-NEXT: v_add_f32_e32 v0, v0, v0
; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s12
; GFX10-32-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; GFX10-32-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10-32-NEXT: s_waitcnt vmcnt(0) ; GFX10-32-NEXT: s_waitcnt vmcnt(0)
; GFX10-32-NEXT: s_branch BB5_3 ; GFX10-32-NEXT: s_branch .LBB5_3
; GFX10-32-NEXT: BB5_2: ; GFX10-32-NEXT: .LBB5_2:
; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-32-NEXT: exp null off, off, off, off done vm ; GFX10-32-NEXT: exp null off, off, off, off done vm
; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: s_endpgm
; GFX10-32-NEXT: BB5_3: ; GFX10-32-NEXT: .LBB5_3:
; ;
; GFX10-64-LABEL: wqm_demote_dynamic: ; GFX10-64-LABEL: wqm_demote_dynamic:
; GFX10-64: ; %bb.0: ; %.entry ; GFX10-64: ; %bb.0: ; %.entry
; GFX10-64-NEXT: s_mov_b64 s[12:13], exec ; GFX10-64-NEXT: s_mov_b64 s[12:13], exec
; GFX10-64-NEXT: s_wqm_b64 exec, exec ; GFX10-64-NEXT: s_wqm_b64 exec, exec
; GFX10-64-NEXT: image_sample v0, v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D ; GFX10-64-NEXT: image_sample v0, v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D
; GFX10-64-NEXT: s_waitcnt vmcnt(0) ; GFX10-64-NEXT: s_waitcnt vmcnt(0)
; GFX10-64-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0 ; GFX10-64-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0
; GFX10-64-NEXT: s_xor_b64 s[14:15], vcc, exec ; GFX10-64-NEXT: s_xor_b64 s[14:15], vcc, exec
; GFX10-64-NEXT: s_andn2_b64 s[12:13], s[12:13], s[14:15] ; GFX10-64-NEXT: s_andn2_b64 s[12:13], s[12:13], s[14:15]
; GFX10-64-NEXT: s_cbranch_scc0 BB5_2 ; GFX10-64-NEXT: s_cbranch_scc0 .LBB5_2
; GFX10-64-NEXT: ; %bb.1: ; %.entry ; GFX10-64-NEXT: ; %bb.1: ; %.entry
; GFX10-64-NEXT: s_wqm_b64 s[14:15], s[12:13] ; GFX10-64-NEXT: s_wqm_b64 s[14:15], s[12:13]
; GFX10-64-NEXT: s_and_b64 exec, exec, s[14:15] ; GFX10-64-NEXT: s_and_b64 exec, exec, s[14:15]
; GFX10-64-NEXT: v_add_f32_e32 v0, v0, v0 ; GFX10-64-NEXT: v_add_f32_e32 v0, v0, v0
; GFX10-64-NEXT: s_and_b64 exec, exec, s[12:13] ; GFX10-64-NEXT: s_and_b64 exec, exec, s[12:13]
; GFX10-64-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; GFX10-64-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10-64-NEXT: s_waitcnt vmcnt(0) ; GFX10-64-NEXT: s_waitcnt vmcnt(0)
; GFX10-64-NEXT: s_branch BB5_3 ; GFX10-64-NEXT: s_branch .LBB5_3
; GFX10-64-NEXT: BB5_2: ; GFX10-64-NEXT: .LBB5_2:
; GFX10-64-NEXT: s_mov_b64 exec, 0 ; GFX10-64-NEXT: s_mov_b64 exec, 0
; GFX10-64-NEXT: exp null off, off, off, off done vm ; GFX10-64-NEXT: exp null off, off, off, off done vm
; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: s_endpgm
; GFX10-64-NEXT: BB5_3: ; GFX10-64-NEXT: .LBB5_3:
.entry: .entry:
%tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %coord, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0 %tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %coord, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0
%tex0 = extractelement <4 x float> %tex, i32 0 %tex0 = extractelement <4 x float> %tex, i32 0
%tex1 = extractelement <4 x float> %tex, i32 0 %tex1 = extractelement <4 x float> %tex, i32 0
%z.cmp = fcmp olt float %tex0, 0.0 %z.cmp = fcmp olt float %tex0, 0.0
call void @llvm.amdgcn.wqm.demote(i1 %z.cmp) call void @llvm.amdgcn.wqm.demote(i1 %z.cmp)
%coord1 = fadd float %tex0, %tex1 %coord1 = fadd float %tex0, %tex1
%rtex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %coord1, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0 %rtex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %coord1, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0
ret <4 x float> %rtex ret <4 x float> %rtex
} }
define amdgpu_ps void @wqm_deriv(<2 x float> %input, float %arg, i32 %index) { define amdgpu_ps void @wqm_deriv(<2 x float> %input, float %arg, i32 %index) {
; SI-LABEL: wqm_deriv: ; SI-LABEL: wqm_deriv:
; SI: ; %bb.0: ; %.entry ; SI: ; %bb.0: ; %.entry
; SI-NEXT: s_mov_b64 s[0:1], exec ; SI-NEXT: s_mov_b64 s[0:1], exec
; SI-NEXT: s_wqm_b64 exec, exec ; SI-NEXT: s_wqm_b64 exec, exec
; SI-NEXT: v_cvt_i32_f32_e32 v0, v0 ; SI-NEXT: v_cvt_i32_f32_e32 v0, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: s_and_saveexec_b64 s[2:3], vcc ; SI-NEXT: s_and_saveexec_b64 s[2:3], vcc
; SI-NEXT: s_xor_b64 s[2:3], exec, s[2:3] ; SI-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; SI-NEXT: s_cbranch_execz BB6_3 ; SI-NEXT: s_cbranch_execz .LBB6_3
; SI-NEXT: ; %bb.1: ; %.demote0 ; SI-NEXT: ; %bb.1: ; %.demote0
; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; SI-NEXT: s_cbranch_scc0 BB6_7 ; SI-NEXT: s_cbranch_scc0 .LBB6_7
; SI-NEXT: ; %bb.2: ; %.demote0 ; SI-NEXT: ; %bb.2: ; %.demote0
; SI-NEXT: s_wqm_b64 s[4:5], s[0:1] ; SI-NEXT: s_wqm_b64 s[4:5], s[0:1]
; SI-NEXT: s_and_b64 exec, exec, s[4:5] ; SI-NEXT: s_and_b64 exec, exec, s[4:5]
; SI-NEXT: BB6_3: ; %.continue0 ; SI-NEXT: .LBB6_3: ; %.continue0
; SI-NEXT: s_or_b64 exec, exec, s[2:3] ; SI-NEXT: s_or_b64 exec, exec, s[2:3]
; SI-NEXT: s_mov_b64 s[2:3], s[0:1] ; SI-NEXT: s_mov_b64 s[2:3], s[0:1]
; SI-NEXT: v_cndmask_b32_e64 v0, 1.0, 0, s[2:3] ; SI-NEXT: v_cndmask_b32_e64 v0, 1.0, 0, s[2:3]
; SI-NEXT: v_mov_b32_e32 v1, v0 ; SI-NEXT: v_mov_b32_e32 v1, v0
; SI-NEXT: s_xor_b64 s[2:3], s[0:1], -1 ; SI-NEXT: s_xor_b64 s[2:3], s[0:1], -1
; SI-NEXT: s_nop 0 ; SI-NEXT: s_nop 0
; SI-NEXT: v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; SI-NEXT: v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
; SI-NEXT: s_nop 1 ; SI-NEXT: s_nop 1
; SI-NEXT: v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; SI-NEXT: v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
; SI-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $exec ; SI-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $exec
; SI-NEXT: s_and_b64 exec, exec, s[0:1] ; SI-NEXT: s_and_b64 exec, exec, s[0:1]
; SI-NEXT: v_cmp_neq_f32_e32 vcc, 0, v0 ; SI-NEXT: v_cmp_neq_f32_e32 vcc, 0, v0
; SI-NEXT: s_or_b64 s[2:3], s[2:3], vcc ; SI-NEXT: s_or_b64 s[2:3], s[2:3], vcc
; SI-NEXT: s_and_saveexec_b64 s[4:5], s[2:3] ; SI-NEXT: s_and_saveexec_b64 s[4:5], s[2:3]
; SI-NEXT: s_xor_b64 s[2:3], exec, s[4:5] ; SI-NEXT: s_xor_b64 s[2:3], exec, s[4:5]
; SI-NEXT: s_cbranch_execz BB6_6 ; SI-NEXT: s_cbranch_execz .LBB6_6
; SI-NEXT: ; %bb.4: ; %.demote1 ; SI-NEXT: ; %bb.4: ; %.demote1
; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; SI-NEXT: s_cbranch_scc0 BB6_7 ; SI-NEXT: s_cbranch_scc0 .LBB6_7
; SI-NEXT: ; %bb.5: ; %.demote1 ; SI-NEXT: ; %bb.5: ; %.demote1
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: BB6_6: ; %.continue1 ; SI-NEXT: .LBB6_6: ; %.continue1
; SI-NEXT: s_or_b64 exec, exec, s[2:3] ; SI-NEXT: s_or_b64 exec, exec, s[2:3]
; SI-NEXT: v_bfrev_b32_e32 v0, 60 ; SI-NEXT: v_bfrev_b32_e32 v0, 60
; SI-NEXT: v_mov_b32_e32 v1, 0x3c00 ; SI-NEXT: v_mov_b32_e32 v1, 0x3c00
; SI-NEXT: exp mrt0 v1, v1, v0, v0 done compr vm ; SI-NEXT: exp mrt0 v1, v1, v0, v0 done compr vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; SI-NEXT: BB6_7: ; SI-NEXT: .LBB6_7:
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: exp null off, off, off, off done vm ; SI-NEXT: exp null off, off, off, off done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; GFX9-LABEL: wqm_deriv: ; GFX9-LABEL: wqm_deriv:
; GFX9: ; %bb.0: ; %.entry ; GFX9: ; %bb.0: ; %.entry
; GFX9-NEXT: s_mov_b64 s[0:1], exec ; GFX9-NEXT: s_mov_b64 s[0:1], exec
; GFX9-NEXT: s_wqm_b64 exec, exec ; GFX9-NEXT: s_wqm_b64 exec, exec
; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-NEXT: s_xor_b64 s[2:3], exec, s[2:3] ; GFX9-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX9-NEXT: s_cbranch_execz BB6_3 ; GFX9-NEXT: s_cbranch_execz .LBB6_3
; GFX9-NEXT: ; %bb.1: ; %.demote0 ; GFX9-NEXT: ; %bb.1: ; %.demote0
; GFX9-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; GFX9-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; GFX9-NEXT: s_cbranch_scc0 BB6_7 ; GFX9-NEXT: s_cbranch_scc0 .LBB6_7
; GFX9-NEXT: ; %bb.2: ; %.demote0 ; GFX9-NEXT: ; %bb.2: ; %.demote0
; GFX9-NEXT: s_wqm_b64 s[4:5], s[0:1] ; GFX9-NEXT: s_wqm_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_and_b64 exec, exec, s[4:5] ; GFX9-NEXT: s_and_b64 exec, exec, s[4:5]
; GFX9-NEXT: BB6_3: ; %.continue0 ; GFX9-NEXT: .LBB6_3: ; %.continue0
; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX9-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX9-NEXT: s_mov_b64 s[2:3], s[0:1] ; GFX9-NEXT: s_mov_b64 s[2:3], s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v0, 1.0, 0, s[2:3] ; GFX9-NEXT: v_cndmask_b32_e64 v0, 1.0, 0, s[2:3]
; GFX9-NEXT: v_mov_b32_e32 v1, v0 ; GFX9-NEXT: v_mov_b32_e32 v1, v0
; GFX9-NEXT: s_xor_b64 s[2:3], s[0:1], -1 ; GFX9-NEXT: s_xor_b64 s[2:3], s[0:1], -1
; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: s_nop 0
; GFX9-NEXT: v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX9-NEXT: v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9-NEXT: s_nop 1 ; GFX9-NEXT: s_nop 1
; GFX9-NEXT: v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX9-NEXT: v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $exec ; GFX9-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $exec
; GFX9-NEXT: s_and_b64 exec, exec, s[0:1] ; GFX9-NEXT: s_and_b64 exec, exec, s[0:1]
; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, 0, v0
; GFX9-NEXT: s_or_b64 s[2:3], s[2:3], vcc ; GFX9-NEXT: s_or_b64 s[2:3], s[2:3], vcc
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], s[2:3] ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], s[2:3]
; GFX9-NEXT: s_xor_b64 s[2:3], exec, s[4:5] ; GFX9-NEXT: s_xor_b64 s[2:3], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz BB6_6 ; GFX9-NEXT: s_cbranch_execz .LBB6_6
; GFX9-NEXT: ; %bb.4: ; %.demote1 ; GFX9-NEXT: ; %bb.4: ; %.demote1
; GFX9-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; GFX9-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; GFX9-NEXT: s_cbranch_scc0 BB6_7 ; GFX9-NEXT: s_cbranch_scc0 .LBB6_7
; GFX9-NEXT: ; %bb.5: ; %.demote1 ; GFX9-NEXT: ; %bb.5: ; %.demote1
; GFX9-NEXT: s_mov_b64 exec, 0 ; GFX9-NEXT: s_mov_b64 exec, 0
; GFX9-NEXT: BB6_6: ; %.continue1 ; GFX9-NEXT: .LBB6_6: ; %.continue1
; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX9-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX9-NEXT: v_mov_b32_e32 v0, 0x3c00 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x3c00
; GFX9-NEXT: v_bfrev_b32_e32 v1, 60 ; GFX9-NEXT: v_bfrev_b32_e32 v1, 60
; GFX9-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm ; GFX9-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; GFX9-NEXT: BB6_7: ; GFX9-NEXT: .LBB6_7:
; GFX9-NEXT: s_mov_b64 exec, 0 ; GFX9-NEXT: s_mov_b64 exec, 0
; GFX9-NEXT: exp null off, off, off, off done vm ; GFX9-NEXT: exp null off, off, off, off done vm
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-32-LABEL: wqm_deriv: ; GFX10-32-LABEL: wqm_deriv:
; GFX10-32: ; %bb.0: ; %.entry ; GFX10-32: ; %bb.0: ; %.entry
; GFX10-32-NEXT: s_mov_b32 s0, exec_lo ; GFX10-32-NEXT: s_mov_b32 s0, exec_lo
; GFX10-32-NEXT: s_wqm_b32 exec_lo, exec_lo ; GFX10-32-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX10-32-NEXT: v_cvt_i32_f32_e32 v0, v0 ; GFX10-32-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX10-32-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 ; GFX10-32-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX10-32-NEXT: s_and_saveexec_b32 s1, vcc_lo ; GFX10-32-NEXT: s_and_saveexec_b32 s1, vcc_lo
; GFX10-32-NEXT: s_xor_b32 s1, exec_lo, s1 ; GFX10-32-NEXT: s_xor_b32 s1, exec_lo, s1
; GFX10-32-NEXT: s_cbranch_execz BB6_3 ; GFX10-32-NEXT: s_cbranch_execz .LBB6_3
; GFX10-32-NEXT: ; %bb.1: ; %.demote0 ; GFX10-32-NEXT: ; %bb.1: ; %.demote0
; GFX10-32-NEXT: s_andn2_b32 s0, s0, exec_lo ; GFX10-32-NEXT: s_andn2_b32 s0, s0, exec_lo
; GFX10-32-NEXT: s_cbranch_scc0 BB6_7 ; GFX10-32-NEXT: s_cbranch_scc0 .LBB6_7
; GFX10-32-NEXT: ; %bb.2: ; %.demote0 ; GFX10-32-NEXT: ; %bb.2: ; %.demote0
; GFX10-32-NEXT: s_wqm_b32 s2, s0 ; GFX10-32-NEXT: s_wqm_b32 s2, s0
; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s2 ; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s2
; GFX10-32-NEXT: BB6_3: ; %.continue0 ; GFX10-32-NEXT: .LBB6_3: ; %.continue0
; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s1 ; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX10-32-NEXT: s_mov_b32 s1, s0 ; GFX10-32-NEXT: s_mov_b32 s1, s0
; GFX10-32-NEXT: v_cndmask_b32_e64 v0, 1.0, 0, s1 ; GFX10-32-NEXT: v_cndmask_b32_e64 v0, 1.0, 0, s1
; GFX10-32-NEXT: v_mov_b32_e32 v1, v0 ; GFX10-32-NEXT: v_mov_b32_e32 v1, v0
; GFX10-32-NEXT: v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX10-32-NEXT: v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX10-32-NEXT: v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX10-32-NEXT: v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX10-32-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $exec ; GFX10-32-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $exec
; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s0 ; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s0
; GFX10-32-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v0 ; GFX10-32-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v0
; GFX10-32-NEXT: s_xor_b32 s1, s0, -1 ; GFX10-32-NEXT: s_xor_b32 s1, s0, -1
; GFX10-32-NEXT: s_or_b32 s1, s1, vcc_lo ; GFX10-32-NEXT: s_or_b32 s1, s1, vcc_lo
; GFX10-32-NEXT: s_and_saveexec_b32 s2, s1 ; GFX10-32-NEXT: s_and_saveexec_b32 s2, s1
; GFX10-32-NEXT: s_xor_b32 s1, exec_lo, s2 ; GFX10-32-NEXT: s_xor_b32 s1, exec_lo, s2
; GFX10-32-NEXT: s_cbranch_execz BB6_6 ; GFX10-32-NEXT: s_cbranch_execz .LBB6_6
; GFX10-32-NEXT: ; %bb.4: ; %.demote1 ; GFX10-32-NEXT: ; %bb.4: ; %.demote1
; GFX10-32-NEXT: s_andn2_b32 s0, s0, exec_lo ; GFX10-32-NEXT: s_andn2_b32 s0, s0, exec_lo
; GFX10-32-NEXT: s_cbranch_scc0 BB6_7 ; GFX10-32-NEXT: s_cbranch_scc0 .LBB6_7
; GFX10-32-NEXT: ; %bb.5: ; %.demote1 ; GFX10-32-NEXT: ; %bb.5: ; %.demote1
; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-32-NEXT: BB6_6: ; %.continue1 ; GFX10-32-NEXT: .LBB6_6: ; %.continue1
; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s1 ; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX10-32-NEXT: v_mov_b32_e32 v0, 0x3c00 ; GFX10-32-NEXT: v_mov_b32_e32 v0, 0x3c00
; GFX10-32-NEXT: v_bfrev_b32_e32 v1, 60 ; GFX10-32-NEXT: v_bfrev_b32_e32 v1, 60
; GFX10-32-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm ; GFX10-32-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm
; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: s_endpgm
; GFX10-32-NEXT: BB6_7: ; GFX10-32-NEXT: .LBB6_7:
; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-32-NEXT: exp null off, off, off, off done vm ; GFX10-32-NEXT: exp null off, off, off, off done vm
; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: s_endpgm
; ;
; GFX10-64-LABEL: wqm_deriv: ; GFX10-64-LABEL: wqm_deriv:
; GFX10-64: ; %bb.0: ; %.entry ; GFX10-64: ; %bb.0: ; %.entry
; GFX10-64-NEXT: s_mov_b64 s[0:1], exec ; GFX10-64-NEXT: s_mov_b64 s[0:1], exec
; GFX10-64-NEXT: s_wqm_b64 exec, exec ; GFX10-64-NEXT: s_wqm_b64 exec, exec
; GFX10-64-NEXT: v_cvt_i32_f32_e32 v0, v0 ; GFX10-64-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX10-64-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX10-64-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX10-64-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX10-64-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX10-64-NEXT: s_xor_b64 s[2:3], exec, s[2:3] ; GFX10-64-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX10-64-NEXT: s_cbranch_execz BB6_3 ; GFX10-64-NEXT: s_cbranch_execz .LBB6_3
; GFX10-64-NEXT: ; %bb.1: ; %.demote0 ; GFX10-64-NEXT: ; %bb.1: ; %.demote0
; GFX10-64-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; GFX10-64-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; GFX10-64-NEXT: s_cbranch_scc0 BB6_7 ; GFX10-64-NEXT: s_cbranch_scc0 .LBB6_7
; GFX10-64-NEXT: ; %bb.2: ; %.demote0 ; GFX10-64-NEXT: ; %bb.2: ; %.demote0
; GFX10-64-NEXT: s_wqm_b64 s[4:5], s[0:1] ; GFX10-64-NEXT: s_wqm_b64 s[4:5], s[0:1]
; GFX10-64-NEXT: s_and_b64 exec, exec, s[4:5] ; GFX10-64-NEXT: s_and_b64 exec, exec, s[4:5]
; GFX10-64-NEXT: BB6_3: ; %.continue0 ; GFX10-64-NEXT: .LBB6_3: ; %.continue0
; GFX10-64-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX10-64-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX10-64-NEXT: s_mov_b64 s[2:3], s[0:1] ; GFX10-64-NEXT: s_mov_b64 s[2:3], s[0:1]
; GFX10-64-NEXT: v_cndmask_b32_e64 v0, 1.0, 0, s[2:3] ; GFX10-64-NEXT: v_cndmask_b32_e64 v0, 1.0, 0, s[2:3]
; GFX10-64-NEXT: v_mov_b32_e32 v1, v0 ; GFX10-64-NEXT: v_mov_b32_e32 v1, v0
; GFX10-64-NEXT: v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX10-64-NEXT: v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX10-64-NEXT: v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX10-64-NEXT: v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX10-64-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $exec ; GFX10-64-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $exec
; GFX10-64-NEXT: s_and_b64 exec, exec, s[0:1] ; GFX10-64-NEXT: s_and_b64 exec, exec, s[0:1]
; GFX10-64-NEXT: v_cmp_neq_f32_e32 vcc, 0, v0 ; GFX10-64-NEXT: v_cmp_neq_f32_e32 vcc, 0, v0
; GFX10-64-NEXT: s_xor_b64 s[2:3], s[0:1], -1 ; GFX10-64-NEXT: s_xor_b64 s[2:3], s[0:1], -1
; GFX10-64-NEXT: s_or_b64 s[2:3], s[2:3], vcc ; GFX10-64-NEXT: s_or_b64 s[2:3], s[2:3], vcc
; GFX10-64-NEXT: s_and_saveexec_b64 s[4:5], s[2:3] ; GFX10-64-NEXT: s_and_saveexec_b64 s[4:5], s[2:3]
; GFX10-64-NEXT: s_xor_b64 s[2:3], exec, s[4:5] ; GFX10-64-NEXT: s_xor_b64 s[2:3], exec, s[4:5]
; GFX10-64-NEXT: s_cbranch_execz BB6_6 ; GFX10-64-NEXT: s_cbranch_execz .LBB6_6
; GFX10-64-NEXT: ; %bb.4: ; %.demote1 ; GFX10-64-NEXT: ; %bb.4: ; %.demote1
; GFX10-64-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; GFX10-64-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; GFX10-64-NEXT: s_cbranch_scc0 BB6_7 ; GFX10-64-NEXT: s_cbranch_scc0 .LBB6_7
; GFX10-64-NEXT: ; %bb.5: ; %.demote1 ; GFX10-64-NEXT: ; %bb.5: ; %.demote1
; GFX10-64-NEXT: s_mov_b64 exec, 0 ; GFX10-64-NEXT: s_mov_b64 exec, 0
; GFX10-64-NEXT: BB6_6: ; %.continue1 ; GFX10-64-NEXT: .LBB6_6: ; %.continue1
; GFX10-64-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX10-64-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX10-64-NEXT: v_mov_b32_e32 v0, 0x3c00 ; GFX10-64-NEXT: v_mov_b32_e32 v0, 0x3c00
; GFX10-64-NEXT: v_bfrev_b32_e32 v1, 60 ; GFX10-64-NEXT: v_bfrev_b32_e32 v1, 60
; GFX10-64-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm ; GFX10-64-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm
; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: s_endpgm
; GFX10-64-NEXT: BB6_7: ; GFX10-64-NEXT: .LBB6_7:
; GFX10-64-NEXT: s_mov_b64 exec, 0 ; GFX10-64-NEXT: s_mov_b64 exec, 0
; GFX10-64-NEXT: exp null off, off, off, off done vm ; GFX10-64-NEXT: exp null off, off, off, off done vm
; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: s_endpgm
.entry: .entry:
%p0 = extractelement <2 x float> %input, i32 0 %p0 = extractelement <2 x float> %input, i32 0
%p1 = extractelement <2 x float> %input, i32 1 %p1 = extractelement <2 x float> %input, i32 1
%x0 = call float @llvm.amdgcn.interp.p1(float %p0, i32 immarg 0, i32 immarg 0, i32 %index) #2 %x0 = call float @llvm.amdgcn.interp.p1(float %p0, i32 immarg 0, i32 immarg 0, i32 %index) #2
%x1 = call float @llvm.amdgcn.interp.p2(float %x0, float %p1, i32 immarg 0, i32 immarg 0, i32 %index) #2 %x1 = call float @llvm.amdgcn.interp.p2(float %x0, float %p1, i32 immarg 0, i32 immarg 0, i32 %index) #2
Show All 32 Lines
; SI: ; %bb.0: ; %.entry ; SI: ; %bb.0: ; %.entry
; SI-NEXT: s_mov_b64 s[0:1], exec ; SI-NEXT: s_mov_b64 s[0:1], exec
; SI-NEXT: s_wqm_b64 exec, exec ; SI-NEXT: s_wqm_b64 exec, exec
; SI-NEXT: v_cvt_i32_f32_e32 v0, v0 ; SI-NEXT: v_cvt_i32_f32_e32 v0, v0
; SI-NEXT: s_mov_b32 s6, 0 ; SI-NEXT: s_mov_b32 s6, 0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: s_and_saveexec_b64 s[2:3], vcc ; SI-NEXT: s_and_saveexec_b64 s[2:3], vcc
; SI-NEXT: s_xor_b64 s[2:3], exec, s[2:3] ; SI-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; SI-NEXT: s_cbranch_execz BB7_3 ; SI-NEXT: s_cbranch_execz .LBB7_3
; SI-NEXT: ; %bb.1: ; %.demote0 ; SI-NEXT: ; %bb.1: ; %.demote0
; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; SI-NEXT: s_cbranch_scc0 BB7_9 ; SI-NEXT: s_cbranch_scc0 .LBB7_9
; SI-NEXT: ; %bb.2: ; %.demote0 ; SI-NEXT: ; %bb.2: ; %.demote0
; SI-NEXT: s_wqm_b64 s[4:5], s[0:1] ; SI-NEXT: s_wqm_b64 s[4:5], s[0:1]
; SI-NEXT: s_and_b64 exec, exec, s[4:5] ; SI-NEXT: s_and_b64 exec, exec, s[4:5]
; SI-NEXT: BB7_3: ; %.continue0.preheader ; SI-NEXT: .LBB7_3: ; %.continue0.preheader
; SI-NEXT: s_or_b64 exec, exec, s[2:3] ; SI-NEXT: s_or_b64 exec, exec, s[2:3]
; SI-NEXT: s_mov_b64 s[2:3], 0 ; SI-NEXT: s_mov_b64 s[2:3], 0
; SI-NEXT: s_branch BB7_5 ; SI-NEXT: s_branch .LBB7_5
; SI-NEXT: BB7_4: ; %.continue1 ; SI-NEXT: .LBB7_4: ; %.continue1
; SI-NEXT: ; in Loop: Header=BB7_5 Depth=1 ; SI-NEXT: ; in Loop: Header=BB7_5 Depth=1
; SI-NEXT: s_or_b64 exec, exec, s[4:5] ; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_add_i32 s6, s6, 1 ; SI-NEXT: s_add_i32 s6, s6, 1
; SI-NEXT: v_cmp_ge_i32_e32 vcc, s6, v1 ; SI-NEXT: v_cmp_ge_i32_e32 vcc, s6, v1
; SI-NEXT: s_or_b64 s[2:3], vcc, s[2:3] ; SI-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; SI-NEXT: s_andn2_b64 exec, exec, s[2:3] ; SI-NEXT: s_andn2_b64 exec, exec, s[2:3]
; SI-NEXT: s_cbranch_execz BB7_8 ; SI-NEXT: s_cbranch_execz .LBB7_8
; SI-NEXT: BB7_5: ; %.continue0 ; SI-NEXT: .LBB7_5: ; %.continue0
; SI-NEXT: ; =>This Inner Loop Header: Depth=1 ; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v0, s6 ; SI-NEXT: v_mov_b32_e32 v0, s6
; SI-NEXT: s_mov_b64 s[4:5], s[0:1] ; SI-NEXT: s_mov_b64 s[4:5], s[0:1]
; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[4:5] ; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[4:5]
; SI-NEXT: v_mov_b32_e32 v2, v0 ; SI-NEXT: v_mov_b32_e32 v2, v0
; SI-NEXT: s_xor_b64 s[4:5], s[0:1], -1 ; SI-NEXT: s_xor_b64 s[4:5], s[0:1], -1
; SI-NEXT: s_nop 0 ; SI-NEXT: s_nop 0
; SI-NEXT: v_mov_b32_dpp v2, v2 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; SI-NEXT: v_mov_b32_dpp v2, v2 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
; SI-NEXT: s_nop 1 ; SI-NEXT: s_nop 1
; SI-NEXT: v_subrev_f32_dpp v0, v0, v2 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; SI-NEXT: v_subrev_f32_dpp v0, v0, v2 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
; SI-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $exec ; SI-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $exec
; SI-NEXT: v_cmp_neq_f32_e32 vcc, 0, v0 ; SI-NEXT: v_cmp_neq_f32_e32 vcc, 0, v0
; SI-NEXT: s_or_b64 s[4:5], s[4:5], vcc ; SI-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; SI-NEXT: s_and_saveexec_b64 s[8:9], s[4:5] ; SI-NEXT: s_and_saveexec_b64 s[8:9], s[4:5]
; SI-NEXT: s_xor_b64 s[4:5], exec, s[8:9] ; SI-NEXT: s_xor_b64 s[4:5], exec, s[8:9]
; SI-NEXT: s_cbranch_execz BB7_4 ; SI-NEXT: s_cbranch_execz .LBB7_4
; SI-NEXT: ; %bb.6: ; %.demote1 ; SI-NEXT: ; %bb.6: ; %.demote1
; SI-NEXT: ; in Loop: Header=BB7_5 Depth=1 ; SI-NEXT: ; in Loop: Header=BB7_5 Depth=1
; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; SI-NEXT: s_cbranch_scc0 BB7_9 ; SI-NEXT: s_cbranch_scc0 .LBB7_9
; SI-NEXT: ; %bb.7: ; %.demote1 ; SI-NEXT: ; %bb.7: ; %.demote1
; SI-NEXT: ; in Loop: Header=BB7_5 Depth=1 ; SI-NEXT: ; in Loop: Header=BB7_5 Depth=1
; SI-NEXT: s_wqm_b64 s[8:9], s[0:1] ; SI-NEXT: s_wqm_b64 s[8:9], s[0:1]
; SI-NEXT: s_and_b64 exec, exec, s[8:9] ; SI-NEXT: s_and_b64 exec, exec, s[8:9]
; SI-NEXT: s_branch BB7_4 ; SI-NEXT: s_branch .LBB7_4
; SI-NEXT: BB7_8: ; %.return ; SI-NEXT: .LBB7_8: ; %.return
; SI-NEXT: s_or_b64 exec, exec, s[2:3] ; SI-NEXT: s_or_b64 exec, exec, s[2:3]
; SI-NEXT: s_and_b64 exec, exec, s[0:1] ; SI-NEXT: s_and_b64 exec, exec, s[0:1]
; SI-NEXT: v_bfrev_b32_e32 v0, 60 ; SI-NEXT: v_bfrev_b32_e32 v0, 60
; SI-NEXT: v_mov_b32_e32 v1, 0x3c00 ; SI-NEXT: v_mov_b32_e32 v1, 0x3c00
; SI-NEXT: exp mrt0 v1, v1, v0, v0 done compr vm ; SI-NEXT: exp mrt0 v1, v1, v0, v0 done compr vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; SI-NEXT: BB7_9: ; SI-NEXT: .LBB7_9:
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: exp null off, off, off, off done vm ; SI-NEXT: exp null off, off, off, off done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; GFX9-LABEL: wqm_deriv_loop: ; GFX9-LABEL: wqm_deriv_loop:
; GFX9: ; %bb.0: ; %.entry ; GFX9: ; %bb.0: ; %.entry
; GFX9-NEXT: s_mov_b64 s[0:1], exec ; GFX9-NEXT: s_mov_b64 s[0:1], exec
; GFX9-NEXT: s_wqm_b64 exec, exec ; GFX9-NEXT: s_wqm_b64 exec, exec
; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX9-NEXT: s_mov_b32 s6, 0 ; GFX9-NEXT: s_mov_b32 s6, 0
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-NEXT: s_xor_b64 s[2:3], exec, s[2:3] ; GFX9-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX9-NEXT: s_cbranch_execz BB7_3 ; GFX9-NEXT: s_cbranch_execz .LBB7_3
; GFX9-NEXT: ; %bb.1: ; %.demote0 ; GFX9-NEXT: ; %bb.1: ; %.demote0
; GFX9-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; GFX9-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; GFX9-NEXT: s_cbranch_scc0 BB7_9 ; GFX9-NEXT: s_cbranch_scc0 .LBB7_9
; GFX9-NEXT: ; %bb.2: ; %.demote0 ; GFX9-NEXT: ; %bb.2: ; %.demote0
; GFX9-NEXT: s_wqm_b64 s[4:5], s[0:1] ; GFX9-NEXT: s_wqm_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_and_b64 exec, exec, s[4:5] ; GFX9-NEXT: s_and_b64 exec, exec, s[4:5]
; GFX9-NEXT: BB7_3: ; %.continue0.preheader ; GFX9-NEXT: .LBB7_3: ; %.continue0.preheader
; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX9-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX9-NEXT: s_mov_b64 s[2:3], 0 ; GFX9-NEXT: s_mov_b64 s[2:3], 0
; GFX9-NEXT: s_branch BB7_5 ; GFX9-NEXT: s_branch .LBB7_5
; GFX9-NEXT: BB7_4: ; %.continue1 ; GFX9-NEXT: .LBB7_4: ; %.continue1
; GFX9-NEXT: ; in Loop: Header=BB7_5 Depth=1 ; GFX9-NEXT: ; in Loop: Header=BB7_5 Depth=1
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_add_i32 s6, s6, 1 ; GFX9-NEXT: s_add_i32 s6, s6, 1
; GFX9-NEXT: v_cmp_ge_i32_e32 vcc, s6, v1 ; GFX9-NEXT: v_cmp_ge_i32_e32 vcc, s6, v1
; GFX9-NEXT: s_or_b64 s[2:3], vcc, s[2:3] ; GFX9-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX9-NEXT: s_andn2_b64 exec, exec, s[2:3] ; GFX9-NEXT: s_andn2_b64 exec, exec, s[2:3]
; GFX9-NEXT: s_cbranch_execz BB7_8 ; GFX9-NEXT: s_cbranch_execz .LBB7_8
; GFX9-NEXT: BB7_5: ; %.continue0 ; GFX9-NEXT: .LBB7_5: ; %.continue0
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mov_b32_e32 v0, s6 ; GFX9-NEXT: v_mov_b32_e32 v0, s6
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1] ; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[4:5] ; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[4:5]
; GFX9-NEXT: v_mov_b32_e32 v2, v0 ; GFX9-NEXT: v_mov_b32_e32 v2, v0
; GFX9-NEXT: s_xor_b64 s[4:5], s[0:1], -1 ; GFX9-NEXT: s_xor_b64 s[4:5], s[0:1], -1
; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: s_nop 0
; GFX9-NEXT: v_mov_b32_dpp v2, v2 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX9-NEXT: v_mov_b32_dpp v2, v2 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9-NEXT: s_nop 1 ; GFX9-NEXT: s_nop 1
; GFX9-NEXT: v_subrev_f32_dpp v0, v0, v2 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX9-NEXT: v_subrev_f32_dpp v0, v0, v2 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $exec ; GFX9-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $exec
; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, 0, v0
; GFX9-NEXT: s_or_b64 s[4:5], s[4:5], vcc ; GFX9-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GFX9-NEXT: s_and_saveexec_b64 s[8:9], s[4:5] ; GFX9-NEXT: s_and_saveexec_b64 s[8:9], s[4:5]
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[8:9] ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[8:9]
; GFX9-NEXT: s_cbranch_execz BB7_4 ; GFX9-NEXT: s_cbranch_execz .LBB7_4
; GFX9-NEXT: ; %bb.6: ; %.demote1 ; GFX9-NEXT: ; %bb.6: ; %.demote1
; GFX9-NEXT: ; in Loop: Header=BB7_5 Depth=1 ; GFX9-NEXT: ; in Loop: Header=BB7_5 Depth=1
; GFX9-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; GFX9-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; GFX9-NEXT: s_cbranch_scc0 BB7_9 ; GFX9-NEXT: s_cbranch_scc0 .LBB7_9
; GFX9-NEXT: ; %bb.7: ; %.demote1 ; GFX9-NEXT: ; %bb.7: ; %.demote1
; GFX9-NEXT: ; in Loop: Header=BB7_5 Depth=1 ; GFX9-NEXT: ; in Loop: Header=BB7_5 Depth=1
; GFX9-NEXT: s_wqm_b64 s[8:9], s[0:1] ; GFX9-NEXT: s_wqm_b64 s[8:9], s[0:1]
; GFX9-NEXT: s_and_b64 exec, exec, s[8:9] ; GFX9-NEXT: s_and_b64 exec, exec, s[8:9]
; GFX9-NEXT: s_branch BB7_4 ; GFX9-NEXT: s_branch .LBB7_4
; GFX9-NEXT: BB7_8: ; %.return ; GFX9-NEXT: .LBB7_8: ; %.return
; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX9-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX9-NEXT: s_and_b64 exec, exec, s[0:1] ; GFX9-NEXT: s_and_b64 exec, exec, s[0:1]
; GFX9-NEXT: v_mov_b32_e32 v0, 0x3c00 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x3c00
; GFX9-NEXT: v_bfrev_b32_e32 v1, 60 ; GFX9-NEXT: v_bfrev_b32_e32 v1, 60
; GFX9-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm ; GFX9-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; GFX9-NEXT: BB7_9: ; GFX9-NEXT: .LBB7_9:
; GFX9-NEXT: s_mov_b64 exec, 0 ; GFX9-NEXT: s_mov_b64 exec, 0
; GFX9-NEXT: exp null off, off, off, off done vm ; GFX9-NEXT: exp null off, off, off, off done vm
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-32-LABEL: wqm_deriv_loop: ; GFX10-32-LABEL: wqm_deriv_loop:
; GFX10-32: ; %bb.0: ; %.entry ; GFX10-32: ; %bb.0: ; %.entry
; GFX10-32-NEXT: s_mov_b32 s0, exec_lo ; GFX10-32-NEXT: s_mov_b32 s0, exec_lo
; GFX10-32-NEXT: s_wqm_b32 exec_lo, exec_lo ; GFX10-32-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX10-32-NEXT: v_cvt_i32_f32_e32 v0, v0 ; GFX10-32-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX10-32-NEXT: s_mov_b32 s2, 0 ; GFX10-32-NEXT: s_mov_b32 s2, 0
; GFX10-32-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 ; GFX10-32-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX10-32-NEXT: s_and_saveexec_b32 s1, vcc_lo ; GFX10-32-NEXT: s_and_saveexec_b32 s1, vcc_lo
; GFX10-32-NEXT: s_xor_b32 s1, exec_lo, s1 ; GFX10-32-NEXT: s_xor_b32 s1, exec_lo, s1
; GFX10-32-NEXT: s_cbranch_execz BB7_3 ; GFX10-32-NEXT: s_cbranch_execz .LBB7_3
; GFX10-32-NEXT: ; %bb.1: ; %.demote0 ; GFX10-32-NEXT: ; %bb.1: ; %.demote0
; GFX10-32-NEXT: s_andn2_b32 s0, s0, exec_lo ; GFX10-32-NEXT: s_andn2_b32 s0, s0, exec_lo
; GFX10-32-NEXT: s_cbranch_scc0 BB7_9 ; GFX10-32-NEXT: s_cbranch_scc0 .LBB7_9
; GFX10-32-NEXT: ; %bb.2: ; %.demote0 ; GFX10-32-NEXT: ; %bb.2: ; %.demote0
; GFX10-32-NEXT: s_wqm_b32 s3, s0 ; GFX10-32-NEXT: s_wqm_b32 s3, s0
; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s3 ; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s3
; GFX10-32-NEXT: BB7_3: ; %.continue0.preheader ; GFX10-32-NEXT: .LBB7_3: ; %.continue0.preheader
; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s1 ; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX10-32-NEXT: s_mov_b32 s3, 0 ; GFX10-32-NEXT: s_mov_b32 s3, 0
; GFX10-32-NEXT: s_branch BB7_5 ; GFX10-32-NEXT: s_branch .LBB7_5
; GFX10-32-NEXT: BB7_4: ; %.continue1 ; GFX10-32-NEXT: .LBB7_4: ; %.continue1
; GFX10-32-NEXT: ; in Loop: Header=BB7_5 Depth=1 ; GFX10-32-NEXT: ; in Loop: Header=BB7_5 Depth=1
; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s1 ; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX10-32-NEXT: s_add_i32 s3, s3, 1 ; GFX10-32-NEXT: s_add_i32 s3, s3, 1
; GFX10-32-NEXT: v_cmp_ge_i32_e32 vcc_lo, s3, v1 ; GFX10-32-NEXT: v_cmp_ge_i32_e32 vcc_lo, s3, v1
; GFX10-32-NEXT: s_or_b32 s2, vcc_lo, s2 ; GFX10-32-NEXT: s_or_b32 s2, vcc_lo, s2
; GFX10-32-NEXT: s_andn2_b32 exec_lo, exec_lo, s2 ; GFX10-32-NEXT: s_andn2_b32 exec_lo, exec_lo, s2
; GFX10-32-NEXT: s_cbranch_execz BB7_8 ; GFX10-32-NEXT: s_cbranch_execz .LBB7_8
; GFX10-32-NEXT: BB7_5: ; %.continue0 ; GFX10-32-NEXT: .LBB7_5: ; %.continue0
; GFX10-32-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-32-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-32-NEXT: s_mov_b32 s1, s0 ; GFX10-32-NEXT: s_mov_b32 s1, s0
; GFX10-32-NEXT: v_cndmask_b32_e64 v0, s3, 0, s1 ; GFX10-32-NEXT: v_cndmask_b32_e64 v0, s3, 0, s1
; GFX10-32-NEXT: s_xor_b32 s1, s0, -1 ; GFX10-32-NEXT: s_xor_b32 s1, s0, -1
; GFX10-32-NEXT: v_mov_b32_e32 v2, v0 ; GFX10-32-NEXT: v_mov_b32_e32 v2, v0
; GFX10-32-NEXT: v_mov_b32_dpp v2, v2 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX10-32-NEXT: v_mov_b32_dpp v2, v2 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX10-32-NEXT: v_subrev_f32_dpp v0, v0, v2 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX10-32-NEXT: v_subrev_f32_dpp v0, v0, v2 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX10-32-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $exec ; GFX10-32-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $exec
; GFX10-32-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v0 ; GFX10-32-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v0
; GFX10-32-NEXT: s_or_b32 s1, s1, vcc_lo ; GFX10-32-NEXT: s_or_b32 s1, s1, vcc_lo
; GFX10-32-NEXT: s_and_saveexec_b32 s4, s1 ; GFX10-32-NEXT: s_and_saveexec_b32 s4, s1
; GFX10-32-NEXT: s_xor_b32 s1, exec_lo, s4 ; GFX10-32-NEXT: s_xor_b32 s1, exec_lo, s4
; GFX10-32-NEXT: s_cbranch_execz BB7_4 ; GFX10-32-NEXT: s_cbranch_execz .LBB7_4
; GFX10-32-NEXT: ; %bb.6: ; %.demote1 ; GFX10-32-NEXT: ; %bb.6: ; %.demote1
; GFX10-32-NEXT: ; in Loop: Header=BB7_5 Depth=1 ; GFX10-32-NEXT: ; in Loop: Header=BB7_5 Depth=1
; GFX10-32-NEXT: s_andn2_b32 s0, s0, exec_lo ; GFX10-32-NEXT: s_andn2_b32 s0, s0, exec_lo
; GFX10-32-NEXT: s_cbranch_scc0 BB7_9 ; GFX10-32-NEXT: s_cbranch_scc0 .LBB7_9
; GFX10-32-NEXT: ; %bb.7: ; %.demote1 ; GFX10-32-NEXT: ; %bb.7: ; %.demote1
; GFX10-32-NEXT: ; in Loop: Header=BB7_5 Depth=1 ; GFX10-32-NEXT: ; in Loop: Header=BB7_5 Depth=1
; GFX10-32-NEXT: s_wqm_b32 s4, s0 ; GFX10-32-NEXT: s_wqm_b32 s4, s0
; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s4 ; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s4
; GFX10-32-NEXT: s_branch BB7_4 ; GFX10-32-NEXT: s_branch .LBB7_4
; GFX10-32-NEXT: BB7_8: ; %.return ; GFX10-32-NEXT: .LBB7_8: ; %.return
; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s2 ; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s0 ; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s0
; GFX10-32-NEXT: v_mov_b32_e32 v0, 0x3c00 ; GFX10-32-NEXT: v_mov_b32_e32 v0, 0x3c00
; GFX10-32-NEXT: v_bfrev_b32_e32 v1, 60 ; GFX10-32-NEXT: v_bfrev_b32_e32 v1, 60
; GFX10-32-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm ; GFX10-32-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm
; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: s_endpgm
; GFX10-32-NEXT: BB7_9: ; GFX10-32-NEXT: .LBB7_9:
; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-32-NEXT: exp null off, off, off, off done vm ; GFX10-32-NEXT: exp null off, off, off, off done vm
; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: s_endpgm
; ;
; GFX10-64-LABEL: wqm_deriv_loop: ; GFX10-64-LABEL: wqm_deriv_loop:
; GFX10-64: ; %bb.0: ; %.entry ; GFX10-64: ; %bb.0: ; %.entry
; GFX10-64-NEXT: s_mov_b64 s[0:1], exec ; GFX10-64-NEXT: s_mov_b64 s[0:1], exec
; GFX10-64-NEXT: s_wqm_b64 exec, exec ; GFX10-64-NEXT: s_wqm_b64 exec, exec
; GFX10-64-NEXT: v_cvt_i32_f32_e32 v0, v0 ; GFX10-64-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX10-64-NEXT: s_mov_b32 s6, 0 ; GFX10-64-NEXT: s_mov_b32 s6, 0
; GFX10-64-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX10-64-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX10-64-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX10-64-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX10-64-NEXT: s_xor_b64 s[2:3], exec, s[2:3] ; GFX10-64-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX10-64-NEXT: s_cbranch_execz BB7_3 ; GFX10-64-NEXT: s_cbranch_execz .LBB7_3
; GFX10-64-NEXT: ; %bb.1: ; %.demote0 ; GFX10-64-NEXT: ; %bb.1: ; %.demote0
; GFX10-64-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; GFX10-64-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; GFX10-64-NEXT: s_cbranch_scc0 BB7_9 ; GFX10-64-NEXT: s_cbranch_scc0 .LBB7_9
; GFX10-64-NEXT: ; %bb.2: ; %.demote0 ; GFX10-64-NEXT: ; %bb.2: ; %.demote0
; GFX10-64-NEXT: s_wqm_b64 s[4:5], s[0:1] ; GFX10-64-NEXT: s_wqm_b64 s[4:5], s[0:1]
; GFX10-64-NEXT: s_and_b64 exec, exec, s[4:5] ; GFX10-64-NEXT: s_and_b64 exec, exec, s[4:5]
; GFX10-64-NEXT: BB7_3: ; %.continue0.preheader ; GFX10-64-NEXT: .LBB7_3: ; %.continue0.preheader
; GFX10-64-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX10-64-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX10-64-NEXT: s_mov_b64 s[2:3], 0 ; GFX10-64-NEXT: s_mov_b64 s[2:3], 0
; GFX10-64-NEXT: s_branch BB7_5 ; GFX10-64-NEXT: s_branch .LBB7_5
; GFX10-64-NEXT: BB7_4: ; %.continue1 ; GFX10-64-NEXT: .LBB7_4: ; %.continue1
; GFX10-64-NEXT: ; in Loop: Header=BB7_5 Depth=1 ; GFX10-64-NEXT: ; in Loop: Header=BB7_5 Depth=1
; GFX10-64-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX10-64-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX10-64-NEXT: s_add_i32 s6, s6, 1 ; GFX10-64-NEXT: s_add_i32 s6, s6, 1
; GFX10-64-NEXT: v_cmp_ge_i32_e32 vcc, s6, v1 ; GFX10-64-NEXT: v_cmp_ge_i32_e32 vcc, s6, v1
; GFX10-64-NEXT: s_or_b64 s[2:3], vcc, s[2:3] ; GFX10-64-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX10-64-NEXT: s_andn2_b64 exec, exec, s[2:3] ; GFX10-64-NEXT: s_andn2_b64 exec, exec, s[2:3]
; GFX10-64-NEXT: s_cbranch_execz BB7_8 ; GFX10-64-NEXT: s_cbranch_execz .LBB7_8
; GFX10-64-NEXT: BB7_5: ; %.continue0 ; GFX10-64-NEXT: .LBB7_5: ; %.continue0
; GFX10-64-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-64-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-64-NEXT: s_mov_b64 s[4:5], s[0:1] ; GFX10-64-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX10-64-NEXT: v_cndmask_b32_e64 v0, s6, 0, s[4:5] ; GFX10-64-NEXT: v_cndmask_b32_e64 v0, s6, 0, s[4:5]
; GFX10-64-NEXT: s_xor_b64 s[4:5], s[0:1], -1 ; GFX10-64-NEXT: s_xor_b64 s[4:5], s[0:1], -1
; GFX10-64-NEXT: v_mov_b32_e32 v2, v0 ; GFX10-64-NEXT: v_mov_b32_e32 v2, v0
; GFX10-64-NEXT: v_mov_b32_dpp v2, v2 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX10-64-NEXT: v_mov_b32_dpp v2, v2 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX10-64-NEXT: v_subrev_f32_dpp v0, v0, v2 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX10-64-NEXT: v_subrev_f32_dpp v0, v0, v2 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX10-64-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $exec ; GFX10-64-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $exec
; GFX10-64-NEXT: v_cmp_neq_f32_e32 vcc, 0, v0 ; GFX10-64-NEXT: v_cmp_neq_f32_e32 vcc, 0, v0
; GFX10-64-NEXT: s_or_b64 s[4:5], s[4:5], vcc ; GFX10-64-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GFX10-64-NEXT: s_and_saveexec_b64 s[8:9], s[4:5] ; GFX10-64-NEXT: s_and_saveexec_b64 s[8:9], s[4:5]
; GFX10-64-NEXT: s_xor_b64 s[4:5], exec, s[8:9] ; GFX10-64-NEXT: s_xor_b64 s[4:5], exec, s[8:9]
; GFX10-64-NEXT: s_cbranch_execz BB7_4 ; GFX10-64-NEXT: s_cbranch_execz .LBB7_4
; GFX10-64-NEXT: ; %bb.6: ; %.demote1 ; GFX10-64-NEXT: ; %bb.6: ; %.demote1
; GFX10-64-NEXT: ; in Loop: Header=BB7_5 Depth=1 ; GFX10-64-NEXT: ; in Loop: Header=BB7_5 Depth=1
; GFX10-64-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; GFX10-64-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; GFX10-64-NEXT: s_cbranch_scc0 BB7_9 ; GFX10-64-NEXT: s_cbranch_scc0 .LBB7_9
; GFX10-64-NEXT: ; %bb.7: ; %.demote1 ; GFX10-64-NEXT: ; %bb.7: ; %.demote1
; GFX10-64-NEXT: ; in Loop: Header=BB7_5 Depth=1 ; GFX10-64-NEXT: ; in Loop: Header=BB7_5 Depth=1
; GFX10-64-NEXT: s_wqm_b64 s[8:9], s[0:1] ; GFX10-64-NEXT: s_wqm_b64 s[8:9], s[0:1]
; GFX10-64-NEXT: s_and_b64 exec, exec, s[8:9] ; GFX10-64-NEXT: s_and_b64 exec, exec, s[8:9]
; GFX10-64-NEXT: s_branch BB7_4 ; GFX10-64-NEXT: s_branch .LBB7_4
; GFX10-64-NEXT: BB7_8: ; %.return ; GFX10-64-NEXT: .LBB7_8: ; %.return
; GFX10-64-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX10-64-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX10-64-NEXT: s_and_b64 exec, exec, s[0:1] ; GFX10-64-NEXT: s_and_b64 exec, exec, s[0:1]
; GFX10-64-NEXT: v_mov_b32_e32 v0, 0x3c00 ; GFX10-64-NEXT: v_mov_b32_e32 v0, 0x3c00
; GFX10-64-NEXT: v_bfrev_b32_e32 v1, 60 ; GFX10-64-NEXT: v_bfrev_b32_e32 v1, 60
; GFX10-64-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm ; GFX10-64-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm
; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: s_endpgm
; GFX10-64-NEXT: BB7_9: ; GFX10-64-NEXT: .LBB7_9:
; GFX10-64-NEXT: s_mov_b64 exec, 0 ; GFX10-64-NEXT: s_mov_b64 exec, 0
; GFX10-64-NEXT: exp null off, off, off, off done vm ; GFX10-64-NEXT: exp null off, off, off, off done vm
; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: s_endpgm
.entry: .entry:
%p0 = extractelement <2 x float> %input, i32 0 %p0 = extractelement <2 x float> %input, i32 0
%p1 = extractelement <2 x float> %input, i32 1 %p1 = extractelement <2 x float> %input, i32 1
%x0 = call float @llvm.amdgcn.interp.p1(float %p0, i32 immarg 0, i32 immarg 0, i32 %index) #2 %x0 = call float @llvm.amdgcn.interp.p1(float %p0, i32 immarg 0, i32 immarg 0, i32 %index) #2
%x1 = call float @llvm.amdgcn.interp.p2(float %x0, float %p1, i32 immarg 0, i32 immarg 0, i32 %index) #2 %x1 = call float @llvm.amdgcn.interp.p2(float %x0, float %p1, i32 immarg 0, i32 immarg 0, i32 %index) #2
▲ Show 20 Lines • Show All 89 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll

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; MUBUF-NEXT: v_mov_b32_e32 v1, 0x3000 ; MUBUF-NEXT: v_mov_b32_e32 v1, 0x3000
; MUBUF-NEXT: s_addc_u32 s1, s1, 0 ; MUBUF-NEXT: s_addc_u32 s1, s1, 0
; MUBUF-NEXT: v_add_u32_e32 v0, 64, v1 ; MUBUF-NEXT: v_add_u32_e32 v0, 64, v1
; MUBUF-NEXT: v_mov_b32_e32 v2, 0 ; MUBUF-NEXT: v_mov_b32_e32 v2, 0
; MUBUF-NEXT: v_mov_b32_e32 v3, 0x2000 ; MUBUF-NEXT: v_mov_b32_e32 v3, 0x2000
; MUBUF-NEXT: s_mov_b32 s6, 0 ; MUBUF-NEXT: s_mov_b32 s6, 0
; MUBUF-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen ; MUBUF-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: BB0_1: ; %loadstoreloop ; MUBUF-NEXT: .LBB0_1: ; %loadstoreloop
; MUBUF-NEXT: ; =>This Inner Loop Header: Depth=1 ; MUBUF-NEXT: ; =>This Inner Loop Header: Depth=1
; MUBUF-NEXT: v_add_u32_e32 v3, s6, v1 ; MUBUF-NEXT: v_add_u32_e32 v3, s6, v1
; MUBUF-NEXT: s_add_i32 s6, s6, 1 ; MUBUF-NEXT: s_add_i32 s6, s6, 1
; MUBUF-NEXT: s_cmpk_lt_u32 s6, 0x2120 ; MUBUF-NEXT: s_cmpk_lt_u32 s6, 0x2120
; MUBUF-NEXT: buffer_store_byte v2, v3, s[0:3], 0 offen ; MUBUF-NEXT: buffer_store_byte v2, v3, s[0:3], 0 offen
; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: s_cbranch_scc1 BB0_1 ; MUBUF-NEXT: s_cbranch_scc1 .LBB0_1
; MUBUF-NEXT: ; %bb.2: ; %split ; MUBUF-NEXT: ; %bb.2: ; %split
; MUBUF-NEXT: v_mov_b32_e32 v1, 0x3000 ; MUBUF-NEXT: v_mov_b32_e32 v1, 0x3000
; MUBUF-NEXT: v_add_u32_e32 v1, 0x20d0, v1 ; MUBUF-NEXT: v_add_u32_e32 v1, 0x20d0, v1
; MUBUF-NEXT: buffer_load_dword v2, v1, s[0:3], 0 offen glc ; MUBUF-NEXT: buffer_load_dword v2, v1, s[0:3], 0 offen glc
; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: buffer_load_dword v3, v1, s[0:3], 0 offen offset:4 glc ; MUBUF-NEXT: buffer_load_dword v3, v1, s[0:3], 0 offen offset:4 glc
; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: buffer_load_dword v4, v0, s[0:3], 0 offen glc ; MUBUF-NEXT: buffer_load_dword v4, v0, s[0:3], 0 offen glc
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; FLATSCR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; FLATSCR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s2, s5 ; FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s2, s5
; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s3, 0 ; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
; FLATSCR-NEXT: v_mov_b32_e32 v0, 0 ; FLATSCR-NEXT: v_mov_b32_e32 v0, 0
; FLATSCR-NEXT: s_movk_i32 vcc_hi, 0x2000 ; FLATSCR-NEXT: s_movk_i32 vcc_hi, 0x2000
; FLATSCR-NEXT: s_mov_b32 s2, 0 ; FLATSCR-NEXT: s_mov_b32 s2, 0
; FLATSCR-NEXT: scratch_store_dword off, v0, vcc_hi ; FLATSCR-NEXT: scratch_store_dword off, v0, vcc_hi
; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: BB0_1: ; %loadstoreloop ; FLATSCR-NEXT: .LBB0_1: ; %loadstoreloop
; FLATSCR-NEXT: ; =>This Inner Loop Header: Depth=1 ; FLATSCR-NEXT: ; =>This Inner Loop Header: Depth=1
; FLATSCR-NEXT: s_add_i32 s3, s2, 0x3000 ; FLATSCR-NEXT: s_add_i32 s3, s2, 0x3000
; FLATSCR-NEXT: s_add_i32 s2, s2, 1 ; FLATSCR-NEXT: s_add_i32 s2, s2, 1
; FLATSCR-NEXT: s_cmpk_lt_u32 s2, 0x2120 ; FLATSCR-NEXT: s_cmpk_lt_u32 s2, 0x2120
; FLATSCR-NEXT: scratch_store_byte off, v0, s3 ; FLATSCR-NEXT: scratch_store_byte off, v0, s3
; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: s_cbranch_scc1 BB0_1 ; FLATSCR-NEXT: s_cbranch_scc1 .LBB0_1
; FLATSCR-NEXT: ; %bb.2: ; %split ; FLATSCR-NEXT: ; %bb.2: ; %split
; FLATSCR-NEXT: s_movk_i32 s2, 0x2000 ; FLATSCR-NEXT: s_movk_i32 s2, 0x2000
; FLATSCR-NEXT: s_addk_i32 s2, 0x3000 ; FLATSCR-NEXT: s_addk_i32 s2, 0x3000
; FLATSCR-NEXT: scratch_load_dwordx2 v[0:1], off, s2 offset:208 glc ; FLATSCR-NEXT: scratch_load_dwordx2 v[0:1], off, s2 offset:208 glc
; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: s_movk_i32 s2, 0x3000 ; FLATSCR-NEXT: s_movk_i32 s2, 0x3000
; FLATSCR-NEXT: scratch_load_dwordx2 v[2:3], off, s2 offset:64 glc ; FLATSCR-NEXT: scratch_load_dwordx2 v[2:3], off, s2 offset:64 glc
; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0)
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; MUBUF-NEXT: v_lshrrev_b32_e64 v3, 6, s33 ; MUBUF-NEXT: v_lshrrev_b32_e64 v3, 6, s33
; MUBUF-NEXT: v_add_u32_e32 v3, 0x1000, v3 ; MUBUF-NEXT: v_add_u32_e32 v3, 0x1000, v3
; MUBUF-NEXT: v_add_u32_e32 v2, 64, v3 ; MUBUF-NEXT: v_add_u32_e32 v2, 64, v3
; MUBUF-NEXT: v_mov_b32_e32 v4, 0 ; MUBUF-NEXT: v_mov_b32_e32 v4, 0
; MUBUF-NEXT: s_mov_b32 s4, 0 ; MUBUF-NEXT: s_mov_b32 s4, 0
; MUBUF-NEXT: s_add_i32 s32, s32, 0x180000 ; MUBUF-NEXT: s_add_i32 s32, s32, 0x180000
; MUBUF-NEXT: buffer_store_dword v4, off, s[0:3], s33 ; MUBUF-NEXT: buffer_store_dword v4, off, s[0:3], s33
; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: BB1_1: ; %loadstoreloop ; MUBUF-NEXT: .LBB1_1: ; %loadstoreloop
; MUBUF-NEXT: ; =>This Inner Loop Header: Depth=1 ; MUBUF-NEXT: ; =>This Inner Loop Header: Depth=1
; MUBUF-NEXT: v_add_u32_e32 v5, s4, v3 ; MUBUF-NEXT: v_add_u32_e32 v5, s4, v3
; MUBUF-NEXT: s_add_i32 s4, s4, 1 ; MUBUF-NEXT: s_add_i32 s4, s4, 1
; MUBUF-NEXT: s_cmpk_lt_u32 s4, 0x2120 ; MUBUF-NEXT: s_cmpk_lt_u32 s4, 0x2120
; MUBUF-NEXT: buffer_store_byte v4, v5, s[0:3], 0 offen ; MUBUF-NEXT: buffer_store_byte v4, v5, s[0:3], 0 offen
; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: s_cbranch_scc1 BB1_1 ; MUBUF-NEXT: s_cbranch_scc1 .LBB1_1
; MUBUF-NEXT: ; %bb.2: ; %split ; MUBUF-NEXT: ; %bb.2: ; %split
; MUBUF-NEXT: v_lshrrev_b32_e64 v3, 6, s33 ; MUBUF-NEXT: v_lshrrev_b32_e64 v3, 6, s33
; MUBUF-NEXT: v_add_u32_e32 v3, 0x1000, v3 ; MUBUF-NEXT: v_add_u32_e32 v3, 0x1000, v3
; MUBUF-NEXT: v_add_u32_e32 v3, 0x20d0, v3 ; MUBUF-NEXT: v_add_u32_e32 v3, 0x20d0, v3
; MUBUF-NEXT: buffer_load_dword v4, v3, s[0:3], 0 offen glc ; MUBUF-NEXT: buffer_load_dword v4, v3, s[0:3], 0 offen glc
; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: buffer_load_dword v5, v3, s[0:3], 0 offen offset:4 glc ; MUBUF-NEXT: buffer_load_dword v5, v3, s[0:3], 0 offen offset:4 glc
; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_waitcnt vmcnt(0)
Show All 15 Lines
; FLATSCR-NEXT: s_mov_b32 s2, s33 ; FLATSCR-NEXT: s_mov_b32 s2, s33
; FLATSCR-NEXT: s_add_i32 s33, s32, 0x1fff ; FLATSCR-NEXT: s_add_i32 s33, s32, 0x1fff
; FLATSCR-NEXT: s_and_b32 s33, s33, 0xffffe000 ; FLATSCR-NEXT: s_and_b32 s33, s33, 0xffffe000
; FLATSCR-NEXT: v_mov_b32_e32 v2, 0 ; FLATSCR-NEXT: v_mov_b32_e32 v2, 0
; FLATSCR-NEXT: s_mov_b32 s0, 0 ; FLATSCR-NEXT: s_mov_b32 s0, 0
; FLATSCR-NEXT: s_addk_i32 s32, 0x6000 ; FLATSCR-NEXT: s_addk_i32 s32, 0x6000
; FLATSCR-NEXT: scratch_store_dword off, v2, s33 ; FLATSCR-NEXT: scratch_store_dword off, v2, s33
; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: BB1_1: ; %loadstoreloop ; FLATSCR-NEXT: .LBB1_1: ; %loadstoreloop
; FLATSCR-NEXT: ; =>This Inner Loop Header: Depth=1 ; FLATSCR-NEXT: ; =>This Inner Loop Header: Depth=1
; FLATSCR-NEXT: s_add_i32 vcc_hi, s33, 0x1000 ; FLATSCR-NEXT: s_add_i32 vcc_hi, s33, 0x1000
; FLATSCR-NEXT: s_add_i32 s1, s0, vcc_hi ; FLATSCR-NEXT: s_add_i32 s1, s0, vcc_hi
; FLATSCR-NEXT: s_add_i32 s0, s0, 1 ; FLATSCR-NEXT: s_add_i32 s0, s0, 1
; FLATSCR-NEXT: s_cmpk_lt_u32 s0, 0x2120 ; FLATSCR-NEXT: s_cmpk_lt_u32 s0, 0x2120
; FLATSCR-NEXT: scratch_store_byte off, v2, s1 ; FLATSCR-NEXT: scratch_store_byte off, v2, s1
; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: s_cbranch_scc1 BB1_1 ; FLATSCR-NEXT: s_cbranch_scc1 .LBB1_1
; FLATSCR-NEXT: ; %bb.2: ; %split ; FLATSCR-NEXT: ; %bb.2: ; %split
; FLATSCR-NEXT: s_movk_i32 s0, 0x2000 ; FLATSCR-NEXT: s_movk_i32 s0, 0x2000
; FLATSCR-NEXT: s_add_i32 s1, s33, 0x1000 ; FLATSCR-NEXT: s_add_i32 s1, s33, 0x1000
; FLATSCR-NEXT: s_add_i32 s0, s0, s1 ; FLATSCR-NEXT: s_add_i32 s0, s0, s1
; FLATSCR-NEXT: scratch_load_dwordx2 v[2:3], off, s0 offset:208 glc ; FLATSCR-NEXT: scratch_load_dwordx2 v[2:3], off, s0 offset:208 glc
; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: s_add_i32 s0, s33, 0x1000 ; FLATSCR-NEXT: s_add_i32 s0, s33, 0x1000
; FLATSCR-NEXT: scratch_load_dwordx2 v[4:5], off, s0 offset:64 glc ; FLATSCR-NEXT: scratch_load_dwordx2 v[4:5], off, s0 offset:64 glc
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; MUBUF-NEXT: s_add_u32 s0, s0, s9 ; MUBUF-NEXT: s_add_u32 s0, s0, s9
; MUBUF-NEXT: s_addc_u32 s1, s1, 0 ; MUBUF-NEXT: s_addc_u32 s1, s1, 0
; MUBUF-NEXT: v_mov_b32_e32 v0, 0x4000 ; MUBUF-NEXT: v_mov_b32_e32 v0, 0x4000
; MUBUF-NEXT: v_mov_b32_e32 v1, 0 ; MUBUF-NEXT: v_mov_b32_e32 v1, 0
; MUBUF-NEXT: v_mov_b32_e32 v2, 0x2000 ; MUBUF-NEXT: v_mov_b32_e32 v2, 0x2000
; MUBUF-NEXT: s_mov_b32 s6, 0 ; MUBUF-NEXT: s_mov_b32 s6, 0
; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: BB2_1: ; %loadstoreloop ; MUBUF-NEXT: .LBB2_1: ; %loadstoreloop
; MUBUF-NEXT: ; =>This Inner Loop Header: Depth=1 ; MUBUF-NEXT: ; =>This Inner Loop Header: Depth=1
; MUBUF-NEXT: v_add_u32_e32 v2, s6, v0 ; MUBUF-NEXT: v_add_u32_e32 v2, s6, v0
; MUBUF-NEXT: s_add_i32 s6, s6, 1 ; MUBUF-NEXT: s_add_i32 s6, s6, 1
; MUBUF-NEXT: s_cmpk_lt_u32 s6, 0x2120 ; MUBUF-NEXT: s_cmpk_lt_u32 s6, 0x2120
; MUBUF-NEXT: buffer_store_byte v1, v2, s[0:3], 0 offen ; MUBUF-NEXT: buffer_store_byte v1, v2, s[0:3], 0 offen
; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: s_cbranch_scc1 BB2_1 ; MUBUF-NEXT: s_cbranch_scc1 .LBB2_1
; MUBUF-NEXT: ; %bb.2: ; %split ; MUBUF-NEXT: ; %bb.2: ; %split
; MUBUF-NEXT: v_mov_b32_e32 v0, 0x4000 ; MUBUF-NEXT: v_mov_b32_e32 v0, 0x4000
; MUBUF-NEXT: v_or_b32_e32 v2, 0x12d4, v0 ; MUBUF-NEXT: v_or_b32_e32 v2, 0x12d4, v0
; MUBUF-NEXT: buffer_load_dword v5, v2, s[0:3], 0 offen glc ; MUBUF-NEXT: buffer_load_dword v5, v2, s[0:3], 0 offen glc
; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: v_or_b32_e32 v2, 0x12d0, v0 ; MUBUF-NEXT: v_or_b32_e32 v2, 0x12d0, v0
; MUBUF-NEXT: v_or_b32_e32 v1, 0x12c0, v0 ; MUBUF-NEXT: v_or_b32_e32 v1, 0x12c0, v0
; MUBUF-NEXT: buffer_load_dword v4, v2, s[0:3], 0 offen glc ; MUBUF-NEXT: buffer_load_dword v4, v2, s[0:3], 0 offen glc
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; FLATSCR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; FLATSCR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s2, s5 ; FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s2, s5
; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s3, 0 ; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
; FLATSCR-NEXT: v_mov_b32_e32 v0, 0 ; FLATSCR-NEXT: v_mov_b32_e32 v0, 0
; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0 ; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0
; FLATSCR-NEXT: s_mov_b32 s2, 0 ; FLATSCR-NEXT: s_mov_b32 s2, 0
; FLATSCR-NEXT: scratch_store_dword off, v0, vcc_hi offset:1024 ; FLATSCR-NEXT: scratch_store_dword off, v0, vcc_hi offset:1024
; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: BB2_1: ; %loadstoreloop ; FLATSCR-NEXT: .LBB2_1: ; %loadstoreloop
; FLATSCR-NEXT: ; =>This Inner Loop Header: Depth=1 ; FLATSCR-NEXT: ; =>This Inner Loop Header: Depth=1
; FLATSCR-NEXT: s_add_i32 s3, s2, 0x2000 ; FLATSCR-NEXT: s_add_i32 s3, s2, 0x2000
; FLATSCR-NEXT: s_add_i32 s2, s2, 1 ; FLATSCR-NEXT: s_add_i32 s2, s2, 1
; FLATSCR-NEXT: s_cmpk_lt_u32 s2, 0x2120 ; FLATSCR-NEXT: s_cmpk_lt_u32 s2, 0x2120
; FLATSCR-NEXT: scratch_store_byte off, v0, s3 ; FLATSCR-NEXT: scratch_store_byte off, v0, s3
; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: s_cbranch_scc1 BB2_1 ; FLATSCR-NEXT: s_cbranch_scc1 .LBB2_1
; FLATSCR-NEXT: ; %bb.2: ; %split ; FLATSCR-NEXT: ; %bb.2: ; %split
; FLATSCR-NEXT: s_movk_i32 s2, 0x1000 ; FLATSCR-NEXT: s_movk_i32 s2, 0x1000
; FLATSCR-NEXT: s_addk_i32 s2, 0x2000 ; FLATSCR-NEXT: s_addk_i32 s2, 0x2000
; FLATSCR-NEXT: scratch_load_dwordx2 v[8:9], off, s2 offset:720 glc ; FLATSCR-NEXT: scratch_load_dwordx2 v[8:9], off, s2 offset:720 glc
; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: scratch_load_dwordx4 v[0:3], off, s2 offset:704 glc ; FLATSCR-NEXT: scratch_load_dwordx4 v[0:3], off, s2 offset:704 glc
; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: s_movk_i32 s2, 0x2000 ; FLATSCR-NEXT: s_movk_i32 s2, 0x2000
Show All 36 Lines

llvm/test/CodeGen/AMDGPU/loop-live-out-copy-undef-subrange.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck %s
; This example used to produce a verifier error resulting from the ; This example used to produce a verifier error resulting from the
; register coalescer leaving behind a false live interval when a live ; register coalescer leaving behind a false live interval when a live
; out copy introduced new liveness for a subregister. ; out copy introduced new liveness for a subregister.
define <3 x float> @liveout_undef_subrange(<3 x float> %arg) { define <3 x float> @liveout_undef_subrange(<3 x float> %arg) {
; CHECK-LABEL: liveout_undef_subrange: ; CHECK-LABEL: liveout_undef_subrange:
; CHECK: ; %bb.0: ; %bb ; CHECK: ; %bb.0: ; %bb
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_add_f32_e32 v3, v2, v2 ; CHECK-NEXT: v_add_f32_e32 v3, v2, v2
; CHECK-NEXT: v_add_f32_e32 v1, v1, v1 ; CHECK-NEXT: v_add_f32_e32 v1, v1, v1
; CHECK-NEXT: v_add_f32_e32 v0, v0, v0 ; CHECK-NEXT: v_add_f32_e32 v0, v0, v0
; CHECK-NEXT: BB0_1: ; %bb1 ; CHECK-NEXT: .LBB0_1: ; %bb1
; CHECK-NEXT: ; =>This Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Loop Header: Depth=1
; CHECK-NEXT: ; Child Loop BB0_2 Depth 2 ; CHECK-NEXT: ; Child Loop BB0_2 Depth 2
; CHECK-NEXT: s_mov_b64 s[4:5], 0 ; CHECK-NEXT: s_mov_b64 s[4:5], 0
; CHECK-NEXT: BB0_2: ; %bb1 ; CHECK-NEXT: .LBB0_2: ; %bb1
; CHECK-NEXT: ; Parent Loop BB0_1 Depth=1 ; CHECK-NEXT: ; Parent Loop BB0_1 Depth=1
; CHECK-NEXT: ; => This Inner Loop Header: Depth=2 ; CHECK-NEXT: ; => This Inner Loop Header: Depth=2
; CHECK-NEXT: v_cmp_neq_f32_e32 vcc, 0, v2 ; CHECK-NEXT: v_cmp_neq_f32_e32 vcc, 0, v2
; CHECK-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; CHECK-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; CHECK-NEXT: s_andn2_b64 exec, exec, s[4:5] ; CHECK-NEXT: s_andn2_b64 exec, exec, s[4:5]
; CHECK-NEXT: s_cbranch_execnz BB0_2 ; CHECK-NEXT: s_cbranch_execnz .LBB0_2
; CHECK-NEXT: ; %bb.3: ; %bb2 ; CHECK-NEXT: ; %bb.3: ; %bb2
; CHECK-NEXT: ; in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: ; in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT: s_or_b64 exec, exec, s[4:5] ; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
; CHECK-NEXT: v_mul_f32_e32 v2, v3, v2 ; CHECK-NEXT: v_mul_f32_e32 v2, v3, v2
; CHECK-NEXT: s_branch BB0_1 ; CHECK-NEXT: s_branch .LBB0_1
bb: bb:
br label %bb1 br label %bb1
bb1: ; preds = %bb3, %bb bb1: ; preds = %bb3, %bb
%i = phi <3 x float> [ %arg, %bb ], [ %i11, %bb3 ] %i = phi <3 x float> [ %arg, %bb ], [ %i11, %bb3 ]
%i2 = extractelement <3 x float> %i, i64 2 %i2 = extractelement <3 x float> %i, i64 2
%i3 = fmul float %i2, 1.000000e+00 %i3 = fmul float %i2, 1.000000e+00
%i4 = fmul nsz <3 x float> %arg, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00> %i4 = fmul nsz <3 x float> %arg, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00>
Show All 13 Lines

llvm/test/CodeGen/AMDGPU/loop-prefetch.ll

; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs -asm-verbose=0 < %s | FileCheck --check-prefixes=GCN,GFX10,GFX10-ASM %s ; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs -asm-verbose=0 < %s | FileCheck --check-prefixes=GCN,GFX10,GFX10-ASM %s
; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s -filetype=obj | llvm-objdump -d --arch-name=amdgcn --mcpu=gfx1030 - | FileCheck --check-prefixes=GCN,GFX10,GFX10-DIS %s ; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s -filetype=obj | llvm-objdump -d --arch-name=amdgcn --mcpu=gfx1030 --symbolize-operands - | FileCheck --check-prefixes=GCN,GFX10,GFX10-DIS %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=GFX8 %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=GFX8 %s
; GFX8-NOT: s_inst_prefetch ; GFX8-NOT: s_inst_prefetch
; GFX8-NOT: .palign 6 ; GFX8-NOT: .palign 6
; GCN-LABEL: test_loop_64 ; GCN-LABEL: test_loop_64
; GFX10: s_movk_i32 s{{[0-9]+}}, 0x400 ; GFX10: s_movk_i32 s{{[0-9]+}}, 0x400
; GFX10-DIS-NEXT: {{^$}} ; GFX10-DIS-NEXT: {{^$}}
; GFX10-ASM-NEXT: [[L1:BB[0-9_]+]]: ; GFX10-ASM-NEXT: [[L1:.LBB[0-9_]+]]:
; GFX10-DIS-NEXT: <[[L1:BB[0-9_]+]]>: ; GFX10-DIS-NEXT: <[[L1:L[0-9]+]]>:
; GFX10: s_sleep 0 ; GFX10: s_sleep 0
; GFX10: s_cbranch_scc0 [[L1]] ; GFX10: s_cbranch_scc0 [[L1]]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
define amdgpu_kernel void @test_loop_64(i32 addrspace(1)* nocapture %arg) { define amdgpu_kernel void @test_loop_64(i32 addrspace(1)* nocapture %arg) {
bb: bb:
br label %bb2 br label %bb2
bb1: ; preds = %bb2 bb1: ; preds = %bb2
ret void ret void
bb2: ; preds = %bb2, %bb bb2: ; preds = %bb2, %bb
%tmp1 = phi i32 [ 0, %bb ], [ %tmp2, %bb2 ] %tmp1 = phi i32 [ 0, %bb ], [ %tmp2, %bb2 ]
%tmp2 = add nuw nsw i32 %tmp1, 1 %tmp2 = add nuw nsw i32 %tmp1, 1
%tmp3 = icmp eq i32 %tmp2, 1024 %tmp3 = icmp eq i32 %tmp2, 1024
tail call void @llvm.amdgcn.s.sleep(i32 0) tail call void @llvm.amdgcn.s.sleep(i32 0)
br i1 %tmp3, label %bb1, label %bb2 br i1 %tmp3, label %bb1, label %bb2
} }
; GCN-LABEL: test_loop_128 ; GCN-LABEL: test_loop_128
; GFX10: s_movk_i32 s{{[0-9]+}}, 0x400 ; GFX10: s_movk_i32 s{{[0-9]+}}, 0x400
; GFX10-ASM-NEXT: .p2align 6 ; GFX10-ASM-NEXT: .p2align 6
; GFX10-DIS-NEXT: s_nop 0 ; GFX10-DIS-NEXT: s_nop 0
; GFX10-NOT: s_inst_prefetch ; GFX10-NOT: s_inst_prefetch
; GFX10-ASM: [[L1:BB[0-9_]+]]: ; GFX10-ASM: [[L1:.LBB[0-9_]+]]:
; GFX10-DIS: <[[L1:BB[0-9_]+]]>: ; GFX10-DIS: <[[L1:L[0-9]+]]>:
; GFX10: s_sleep 0 ; GFX10: s_sleep 0
; GFX10: s_cbranch_scc0 [[L1]] ; GFX10: s_cbranch_scc0 [[L1]]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
define amdgpu_kernel void @test_loop_128(i32 addrspace(1)* nocapture %arg) { define amdgpu_kernel void @test_loop_128(i32 addrspace(1)* nocapture %arg) {
bb: bb:
br label %bb2 br label %bb2
bb1: ; preds = %bb2 bb1: ; preds = %bb2
Show All 23 Lines
} }
; GCN-LABEL: test_loop_192 ; GCN-LABEL: test_loop_192
; GFX10: s_movk_i32 s{{[0-9]+}}, 0x400 ; GFX10: s_movk_i32 s{{[0-9]+}}, 0x400
; GFX10-NEXT: s_inst_prefetch 0x1 ; GFX10-NEXT: s_inst_prefetch 0x1
; GFX10-ASM-NEXT: .p2align 6 ; GFX10-ASM-NEXT: .p2align 6
; GFX10-DIS-NEXT: s_nop 0 ; GFX10-DIS-NEXT: s_nop 0
; GFX10-NOT: s_inst_prefetch ; GFX10-NOT: s_inst_prefetch
; GFX10-ASM: [[L1:BB[0-9_]+]]: ; GFX10-ASM: [[L1:.LBB[0-9_]+]]:
; GFX10-DIS: <[[L1:BB[0-9_]+]]>: ; GFX10-DIS: <[[L1:L[0-9]+]]>:
; GFX10: s_sleep 0 ; GFX10: s_sleep 0
; GFX10: s_cbranch_scc0 [[L1]] ; GFX10: s_cbranch_scc0 [[L1]]
; GFX10-NEXT: s_inst_prefetch 0x2 ; GFX10-NEXT: s_inst_prefetch 0x2
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
define amdgpu_kernel void @test_loop_192(i32 addrspace(1)* nocapture %arg) { define amdgpu_kernel void @test_loop_192(i32 addrspace(1)* nocapture %arg) {
bb: bb:
br label %bb2 br label %bb2
Show All 39 Linesbb2: ; preds = %bb2, %bb
tail call void @llvm.amdgcn.s.sleep(i32 0) tail call void @llvm.amdgcn.s.sleep(i32 0)
tail call void @llvm.amdgcn.s.sleep(i32 0) tail call void @llvm.amdgcn.s.sleep(i32 0)
br i1 %tmp3, label %bb1, label %bb2 br i1 %tmp3, label %bb1, label %bb2
} }
; GCN-LABEL: test_loop_256 ; GCN-LABEL: test_loop_256
; GFX10: s_movk_i32 s{{[0-9]+}}, 0x400 ; GFX10: s_movk_i32 s{{[0-9]+}}, 0x400
; GFX10-DIS-NEXT: {{^$}} ; GFX10-DIS-NEXT: {{^$}}
; GFX10-ASM-NEXT: [[L1:BB[0-9_]+]]: ; GFX10-ASM-NEXT: [[L1:.LBB[0-9_]+]]:
; GFX10-DIS-NEXT: <[[L1:BB[0-9_]+]]>: ; GFX10-DIS-NEXT: <[[L1:L[0-9]+]]>:
; GFX10: s_sleep 0 ; GFX10: s_sleep 0
; GFX10: s_cbranch_scc0 [[L1]] ; GFX10: s_cbranch_scc0 [[L1]]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
define amdgpu_kernel void @test_loop_256(i32 addrspace(1)* nocapture %arg) { define amdgpu_kernel void @test_loop_256(i32 addrspace(1)* nocapture %arg) {
bb: bb:
br label %bb2 br label %bb2
bb1: ; preds = %bb2 bb1: ; preds = %bb2
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Linesbb2: ; preds = %bb2, %bb
br i1 %tmp3, label %bb1, label %bb2 br i1 %tmp3, label %bb1, label %bb2
} }
; GCN-LABEL: test_loop_prefetch_inner_outer ; GCN-LABEL: test_loop_prefetch_inner_outer
; GFX10: s_inst_prefetch 0x1 ; GFX10: s_inst_prefetch 0x1
; GFX10-ASM-NEXT: .p2align 6 ; GFX10-ASM-NEXT: .p2align 6
; GFX10-DIS-NEXT: s_nop 0 ; GFX10-DIS-NEXT: s_nop 0
; GFX10-NOT: s_inst_prefetch ; GFX10-NOT: s_inst_prefetch
; GFX10-ASM: [[L1:BB[0-9_]+]]: ; GFX10-ASM: [[L1:.LBB[0-9_]+]]:
; GFX10-DIS: <[[L1:BB[0-9_]+]]>: ; GFX10-DIS: <[[L1:L[0-9]+]]>:
; GFX10-NOT: s_inst_prefetch ; GFX10-NOT: s_inst_prefetch
; GFX10-ASM: .p2align 6 ; GFX10-ASM: .p2align 6
; GFX10-DIS: s_nop 0 ; GFX10-DIS: s_nop 0
; GFX10-NOT: s_inst_prefetch ; GFX10-NOT: s_inst_prefetch
; GFX10-ASM: [[L2:BB[0-9_]+]]: ; GFX10-ASM: [[L2:.LBB[0-9_]+]]:
; GFX10-DIS: <[[L2:BB[0-9_]+]]>: ; GFX10-DIS: <[[L2:L[0-9]+]]>:
; GFX10-NOT: s_inst_prefetch ; GFX10-NOT: s_inst_prefetch
; GFX10: s_sleep 0 ; GFX10: s_sleep 0
; GFX10: s_cbranch_scc{{[01]}} [[L2]] ; GFX10: s_cbranch_scc{{[01]}} [[L2]]
; GFX10-NOT: s_inst_prefetch ; GFX10-NOT: s_inst_prefetch
; GFX10: s_cbranch_scc{{[01]}} [[L1]] ; GFX10: s_cbranch_scc{{[01]}} [[L1]]
; GFX10-NEXT: s_inst_prefetch 0x2 ; GFX10-NEXT: s_inst_prefetch 0x2
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
define amdgpu_kernel void @test_loop_prefetch_inner_outer(i32 addrspace(1)* nocapture %arg) { define amdgpu_kernel void @test_loop_prefetch_inner_outer(i32 addrspace(1)* nocapture %arg) {
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
bb4: bb4:
br i1 %tmp3, label %bb1, label %bb2 br i1 %tmp3, label %bb1, label %bb2
} }
; GCN-LABEL: test_loop_prefetch_inner_outer_noouter ; GCN-LABEL: test_loop_prefetch_inner_outer_noouter
; GFX10-NOT: .p2align 6 ; GFX10-NOT: .p2align 6
; GFX10-NOT: s_nop ; GFX10-NOT: s_nop
; GFX10-NOT: s_inst_prefetch ; GFX10-NOT: s_inst_prefetch
; GFX10-ASM: [[L0:BB[0-9_]+]]: ; GFX10-ASM: [[L0:.LBB[0-9_]+]]:
; GFX10-DIS: <[[L0:BB[0-9_]+]]>: ; GFX10-DIS: <[[L0:L[0-9]+]]>:
; GFX10: s_inst_prefetch 0x1 ; GFX10: s_inst_prefetch 0x1
; GFX10-ASM-NEXT: .p2align 6 ; GFX10-ASM-NEXT: .p2align 6
; GFX10-DIS-NEXT: s_nop 0 ; GFX10-DIS-NEXT: s_nop 0
; GFX10-NOT: s_inst_prefetch ; GFX10-NOT: s_inst_prefetch
; GFX10-ASM: [[L1:BB[0-9_]+]]: ; GFX10-ASM: [[L1:.LBB[0-9_]+]]:
; GFX10-DIS: <[[L1:BB[0-9_]+]]>: ; GFX10-DIS: <[[L1:L[0-9]+]]>:
; GFX10-NOT: s_inst_prefetch ; GFX10-NOT: s_inst_prefetch
; GFX10-ASM: .p2align 6 ; GFX10-ASM: .p2align 6
; GFX10-DIS: s_nop 0 ; GFX10-DIS: s_nop 0
; GFX10-NOT: s_inst_prefetch ; GFX10-NOT: s_inst_prefetch
; GFX10-ASM: [[L2:BB[0-9_]+]]: ; GFX10-ASM: [[L2:.LBB[0-9_]+]]:
; GFX10-DIS: <[[L2:BB[0-9_]+]]>: ; GFX10-DIS: <[[L2:L[0-9]+]]>:
; GFX10-NOT: s_inst_prefetch ; GFX10-NOT: s_inst_prefetch
; GFX10: s_sleep 0 ; GFX10: s_sleep 0
; GFX10: s_cbranch_scc{{[01]}} [[L2]] ; GFX10: s_cbranch_scc{{[01]}} [[L2]]
; GFX10-NOT: s_inst_prefetch ; GFX10-NOT: s_inst_prefetch
; GFX10: s_cbranch_scc{{[01]}} [[L1]] ; GFX10: s_cbranch_scc{{[01]}} [[L1]]
; GFX10-NEXT: s_inst_prefetch 0x2 ; GFX10-NEXT: s_inst_prefetch 0x2
; GFX10: s_cbranch_scc{{[01]}} [[L0]] ; GFX10: s_cbranch_scc{{[01]}} [[L0]]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
▲ Show 20 Lines • Show All 83 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/loop_break.ll

Show All 33 Lines
; GCN-NEXT: s_load_dword s3, s[0:1], 0x9 ; GCN-NEXT: s_load_dword s3, s[0:1], 0x9
; GCN-NEXT: s_mov_b64 s[0:1], 0 ; GCN-NEXT: s_mov_b64 s[0:1], 0
; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s3, v0 ; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s3, v0
; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: ; implicit-def: $sgpr4_sgpr5 ; GCN-NEXT: ; implicit-def: $sgpr4_sgpr5
; GCN-NEXT: ; implicit-def: $sgpr6 ; GCN-NEXT: ; implicit-def: $sgpr6
; GCN-NEXT: BB0_1: ; %bb1 ; GCN-NEXT: .LBB0_1: ; %bb1
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: s_add_i32 s6, s6, 1 ; GCN-NEXT: s_add_i32 s6, s6, 1
; GCN-NEXT: s_or_b64 s[4:5], s[4:5], exec ; GCN-NEXT: s_or_b64 s[4:5], s[4:5], exec
; GCN-NEXT: s_cmp_gt_i32 s6, -1 ; GCN-NEXT: s_cmp_gt_i32 s6, -1
; GCN-NEXT: s_cbranch_scc1 BB0_3 ; GCN-NEXT: s_cbranch_scc1 .LBB0_3
; GCN-NEXT: ; %bb.2: ; %bb4 ; GCN-NEXT: ; %bb.2: ; %bb4
; GCN-NEXT: ; in Loop: Header=BB0_1 Depth=1 ; GCN-NEXT: ; in Loop: Header=BB0_1 Depth=1
; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc ; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1 ; GCN-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1
; GCN-NEXT: s_andn2_b64 s[4:5], s[4:5], exec ; GCN-NEXT: s_andn2_b64 s[4:5], s[4:5], exec
; GCN-NEXT: s_and_b64 s[8:9], vcc, exec ; GCN-NEXT: s_and_b64 s[8:9], vcc, exec
; GCN-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9] ; GCN-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
; GCN-NEXT: BB0_3: ; %Flow ; GCN-NEXT: .LBB0_3: ; %Flow
; GCN-NEXT: ; in Loop: Header=BB0_1 Depth=1 ; GCN-NEXT: ; in Loop: Header=BB0_1 Depth=1
; GCN-NEXT: s_and_b64 s[8:9], exec, s[4:5] ; GCN-NEXT: s_and_b64 s[8:9], exec, s[4:5]
; GCN-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1] ; GCN-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1]
; GCN-NEXT: s_andn2_b64 exec, exec, s[0:1] ; GCN-NEXT: s_andn2_b64 exec, exec, s[0:1]
; GCN-NEXT: s_cbranch_execnz BB0_1 ; GCN-NEXT: s_cbranch_execnz .LBB0_1
; GCN-NEXT: ; %bb.4: ; %bb9 ; GCN-NEXT: ; %bb.4: ; %bb9
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
bb: bb:
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%my.tmp = sub i32 %id, %arg %my.tmp = sub i32 %id, %arg
br label %bb1 br label %bb1
bb1: bb1:
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; GCN-NEXT: s_load_dword s3, s[0:1], 0x9 ; GCN-NEXT: s_load_dword s3, s[0:1], 0x9
; GCN-NEXT: s_mov_b64 s[0:1], 0 ; GCN-NEXT: s_mov_b64 s[0:1], 0
; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s3, v0 ; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s3, v0
; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: ; implicit-def: $sgpr4_sgpr5 ; GCN-NEXT: ; implicit-def: $sgpr4_sgpr5
; GCN-NEXT: ; implicit-def: $sgpr6 ; GCN-NEXT: ; implicit-def: $sgpr6
; GCN-NEXT: BB1_1: ; %bb1 ; GCN-NEXT: .LBB1_1: ; %bb1
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: s_andn2_b64 s[4:5], s[4:5], exec ; GCN-NEXT: s_andn2_b64 s[4:5], s[4:5], exec
; GCN-NEXT: s_cmp_gt_i32 s6, -1 ; GCN-NEXT: s_cmp_gt_i32 s6, -1
; GCN-NEXT: s_cbranch_scc1 BB1_3 ; GCN-NEXT: s_cbranch_scc1 .LBB1_3
; GCN-NEXT: ; %bb.2: ; %bb4 ; GCN-NEXT: ; %bb.2: ; %bb4
; GCN-NEXT: ; in Loop: Header=BB1_1 Depth=1 ; GCN-NEXT: ; in Loop: Header=BB1_1 Depth=1
; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc ; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1 ; GCN-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1
; GCN-NEXT: s_andn2_b64 s[4:5], s[4:5], exec ; GCN-NEXT: s_andn2_b64 s[4:5], s[4:5], exec
; GCN-NEXT: s_and_b64 s[8:9], vcc, exec ; GCN-NEXT: s_and_b64 s[8:9], vcc, exec
; GCN-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9] ; GCN-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
; GCN-NEXT: BB1_3: ; %Flow ; GCN-NEXT: .LBB1_3: ; %Flow
; GCN-NEXT: ; in Loop: Header=BB1_1 Depth=1 ; GCN-NEXT: ; in Loop: Header=BB1_1 Depth=1
; GCN-NEXT: s_add_i32 s6, s6, 1 ; GCN-NEXT: s_add_i32 s6, s6, 1
; GCN-NEXT: s_and_b64 s[8:9], exec, s[4:5] ; GCN-NEXT: s_and_b64 s[8:9], exec, s[4:5]
; GCN-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1] ; GCN-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1]
; GCN-NEXT: s_andn2_b64 exec, exec, s[0:1] ; GCN-NEXT: s_andn2_b64 exec, exec, s[0:1]
; GCN-NEXT: s_cbranch_execnz BB1_1 ; GCN-NEXT: s_cbranch_execnz .LBB1_1
; GCN-NEXT: ; %bb.4: ; %bb9 ; GCN-NEXT: ; %bb.4: ; %bb9
; GCN-NEXT: s_or_b64 exec, exec, s[0:1] ; GCN-NEXT: s_or_b64 exec, exec, s[0:1]
; GCN-NEXT: v_mov_b32_e32 v0, 7 ; GCN-NEXT: v_mov_b32_e32 v0, 7
; GCN-NEXT: s_mov_b32 m0, -1 ; GCN-NEXT: s_mov_b32 m0, -1
; GCN-NEXT: ds_write_b32 v0, v0 ; GCN-NEXT: ds_write_b32 v0, v0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
bb: bb:
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
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; GCN-NEXT: s_load_dword s3, s[0:1], 0x9 ; GCN-NEXT: s_load_dword s3, s[0:1], 0x9
; GCN-NEXT: s_mov_b64 s[0:1], 0 ; GCN-NEXT: s_mov_b64 s[0:1], 0
; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s3, v0 ; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s3, v0
; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: ; implicit-def: $sgpr4_sgpr5 ; GCN-NEXT: ; implicit-def: $sgpr4_sgpr5
; GCN-NEXT: ; implicit-def: $sgpr6 ; GCN-NEXT: ; implicit-def: $sgpr6
; GCN-NEXT: BB2_1: ; %bb1 ; GCN-NEXT: .LBB2_1: ; %bb1
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: s_or_b64 s[4:5], s[4:5], exec ; GCN-NEXT: s_or_b64 s[4:5], s[4:5], exec
; GCN-NEXT: s_cmp_gt_i32 s6, -1 ; GCN-NEXT: s_cmp_gt_i32 s6, -1
; GCN-NEXT: s_cbranch_scc1 BB2_3 ; GCN-NEXT: s_cbranch_scc1 .LBB2_3
; GCN-NEXT: ; %bb.2: ; %bb4 ; GCN-NEXT: ; %bb.2: ; %bb4
; GCN-NEXT: ; in Loop: Header=BB2_1 Depth=1 ; GCN-NEXT: ; in Loop: Header=BB2_1 Depth=1
; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc ; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1 ; GCN-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1
; GCN-NEXT: s_andn2_b64 s[4:5], s[4:5], exec ; GCN-NEXT: s_andn2_b64 s[4:5], s[4:5], exec
; GCN-NEXT: s_and_b64 s[8:9], vcc, exec ; GCN-NEXT: s_and_b64 s[8:9], vcc, exec
; GCN-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9] ; GCN-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
; GCN-NEXT: BB2_3: ; %Flow ; GCN-NEXT: .LBB2_3: ; %Flow
; GCN-NEXT: ; in Loop: Header=BB2_1 Depth=1 ; GCN-NEXT: ; in Loop: Header=BB2_1 Depth=1
; GCN-NEXT: s_add_i32 s6, s6, 1 ; GCN-NEXT: s_add_i32 s6, s6, 1
; GCN-NEXT: s_and_b64 s[8:9], exec, s[4:5] ; GCN-NEXT: s_and_b64 s[8:9], exec, s[4:5]
; GCN-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1] ; GCN-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1]
; GCN-NEXT: s_andn2_b64 exec, exec, s[0:1] ; GCN-NEXT: s_andn2_b64 exec, exec, s[0:1]
; GCN-NEXT: s_cbranch_execnz BB2_1 ; GCN-NEXT: s_cbranch_execnz .LBB2_1
; GCN-NEXT: ; %bb.4: ; %bb9 ; GCN-NEXT: ; %bb.4: ; %bb9
; GCN-NEXT: s_or_b64 exec, exec, s[0:1] ; GCN-NEXT: s_or_b64 exec, exec, s[0:1]
; GCN-NEXT: v_mov_b32_e32 v0, 7 ; GCN-NEXT: v_mov_b32_e32 v0, 7
; GCN-NEXT: s_mov_b32 m0, -1 ; GCN-NEXT: s_mov_b32 m0, -1
; GCN-NEXT: ds_write_b32 v0, v0 ; GCN-NEXT: ds_write_b32 v0, v0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
bb: bb:
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
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; GCN-NEXT: s_load_dword s3, s[0:1], 0x9 ; GCN-NEXT: s_load_dword s3, s[0:1], 0x9
; GCN-NEXT: s_mov_b64 s[0:1], 0 ; GCN-NEXT: s_mov_b64 s[0:1], 0
; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s3, v0 ; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s3, v0
; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: ; implicit-def: $sgpr4_sgpr5 ; GCN-NEXT: ; implicit-def: $sgpr4_sgpr5
; GCN-NEXT: ; implicit-def: $sgpr6 ; GCN-NEXT: ; implicit-def: $sgpr6
; GCN-NEXT: BB3_1: ; %bb1 ; GCN-NEXT: .LBB3_1: ; %bb1
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: s_or_b64 s[4:5], s[4:5], exec ; GCN-NEXT: s_or_b64 s[4:5], s[4:5], exec
; GCN-NEXT: s_cmp_gt_i32 s6, -1 ; GCN-NEXT: s_cmp_gt_i32 s6, -1
; GCN-NEXT: s_cbranch_scc1 BB3_3 ; GCN-NEXT: s_cbranch_scc1 .LBB3_3
; GCN-NEXT: ; %bb.2: ; %bb4 ; GCN-NEXT: ; %bb.2: ; %bb4
; GCN-NEXT: ; in Loop: Header=BB3_1 Depth=1 ; GCN-NEXT: ; in Loop: Header=BB3_1 Depth=1
; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc ; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1 ; GCN-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1
; GCN-NEXT: s_andn2_b64 s[4:5], s[4:5], exec ; GCN-NEXT: s_andn2_b64 s[4:5], s[4:5], exec
; GCN-NEXT: s_and_b64 s[8:9], vcc, exec ; GCN-NEXT: s_and_b64 s[8:9], vcc, exec
; GCN-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9] ; GCN-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
; GCN-NEXT: BB3_3: ; %Flow ; GCN-NEXT: .LBB3_3: ; %Flow
; GCN-NEXT: ; in Loop: Header=BB3_1 Depth=1 ; GCN-NEXT: ; in Loop: Header=BB3_1 Depth=1
; GCN-NEXT: s_add_i32 s6, s6, 1 ; GCN-NEXT: s_add_i32 s6, s6, 1
; GCN-NEXT: s_and_b64 s[8:9], exec, s[4:5] ; GCN-NEXT: s_and_b64 s[8:9], exec, s[4:5]
; GCN-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1] ; GCN-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1]
; GCN-NEXT: s_andn2_b64 exec, exec, s[0:1] ; GCN-NEXT: s_andn2_b64 exec, exec, s[0:1]
; GCN-NEXT: s_cbranch_execnz BB3_1 ; GCN-NEXT: s_cbranch_execnz .LBB3_1
; GCN-NEXT: ; %bb.4: ; %bb9 ; GCN-NEXT: ; %bb.4: ; %bb9
; GCN-NEXT: s_or_b64 exec, exec, s[0:1] ; GCN-NEXT: s_or_b64 exec, exec, s[0:1]
; GCN-NEXT: v_mov_b32_e32 v0, 7 ; GCN-NEXT: v_mov_b32_e32 v0, 7
; GCN-NEXT: s_mov_b32 m0, -1 ; GCN-NEXT: s_mov_b32 m0, -1
; GCN-NEXT: ds_write_b32 v0, v0 ; GCN-NEXT: ds_write_b32 v0, v0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
bb: bb:
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
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; GCN-NEXT: s_load_dword s3, s[0:1], 0x9 ; GCN-NEXT: s_load_dword s3, s[0:1], 0x9
; GCN-NEXT: s_mov_b64 s[0:1], 0 ; GCN-NEXT: s_mov_b64 s[0:1], 0
; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s3, v0 ; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s3, v0
; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: ; implicit-def: $sgpr4_sgpr5 ; GCN-NEXT: ; implicit-def: $sgpr4_sgpr5
; GCN-NEXT: ; implicit-def: $sgpr6 ; GCN-NEXT: ; implicit-def: $sgpr6
; GCN-NEXT: BB4_1: ; %bb1 ; GCN-NEXT: .LBB4_1: ; %bb1
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: s_andn2_b64 s[4:5], s[4:5], exec ; GCN-NEXT: s_andn2_b64 s[4:5], s[4:5], exec
; GCN-NEXT: s_cmp_gt_i32 s6, -1 ; GCN-NEXT: s_cmp_gt_i32 s6, -1
; GCN-NEXT: s_cbranch_scc1 BB4_3 ; GCN-NEXT: s_cbranch_scc1 .LBB4_3
; GCN-NEXT: ; %bb.2: ; %bb4 ; GCN-NEXT: ; %bb.2: ; %bb4
; GCN-NEXT: ; in Loop: Header=BB4_1 Depth=1 ; GCN-NEXT: ; in Loop: Header=BB4_1 Depth=1
; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc ; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1 ; GCN-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1
; GCN-NEXT: s_andn2_b64 s[4:5], s[4:5], exec ; GCN-NEXT: s_andn2_b64 s[4:5], s[4:5], exec
; GCN-NEXT: s_and_b64 s[8:9], vcc, exec ; GCN-NEXT: s_and_b64 s[8:9], vcc, exec
; GCN-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9] ; GCN-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
; GCN-NEXT: BB4_3: ; %Flow ; GCN-NEXT: .LBB4_3: ; %Flow
; GCN-NEXT: ; in Loop: Header=BB4_1 Depth=1 ; GCN-NEXT: ; in Loop: Header=BB4_1 Depth=1
; GCN-NEXT: s_add_i32 s6, s6, 1 ; GCN-NEXT: s_add_i32 s6, s6, 1
; GCN-NEXT: s_and_b64 s[8:9], exec, s[4:5] ; GCN-NEXT: s_and_b64 s[8:9], exec, s[4:5]
; GCN-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1] ; GCN-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1]
; GCN-NEXT: s_andn2_b64 exec, exec, s[0:1] ; GCN-NEXT: s_andn2_b64 exec, exec, s[0:1]
; GCN-NEXT: s_cbranch_execnz BB4_1 ; GCN-NEXT: s_cbranch_execnz .LBB4_1
; GCN-NEXT: ; %bb.4: ; %bb9 ; GCN-NEXT: ; %bb.4: ; %bb9
; GCN-NEXT: s_or_b64 exec, exec, s[0:1] ; GCN-NEXT: s_or_b64 exec, exec, s[0:1]
; GCN-NEXT: v_mov_b32_e32 v0, 7 ; GCN-NEXT: v_mov_b32_e32 v0, 7
; GCN-NEXT: s_mov_b32 m0, -1 ; GCN-NEXT: s_mov_b32 m0, -1
; GCN-NEXT: ds_write_b32 v0, v0 ; GCN-NEXT: ds_write_b32 v0, v0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
bb: bb:
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
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; GCN-NEXT: s_load_dword s3, s[0:1], 0x9 ; GCN-NEXT: s_load_dword s3, s[0:1], 0x9
; GCN-NEXT: s_mov_b64 s[0:1], 0 ; GCN-NEXT: s_mov_b64 s[0:1], 0
; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s3, v0 ; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s3, v0
; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: ; implicit-def: $sgpr4_sgpr5 ; GCN-NEXT: ; implicit-def: $sgpr4_sgpr5
; GCN-NEXT: ; implicit-def: $sgpr6 ; GCN-NEXT: ; implicit-def: $sgpr6
; GCN-NEXT: BB5_1: ; %bb1 ; GCN-NEXT: .LBB5_1: ; %bb1
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: s_or_b64 s[4:5], s[4:5], exec ; GCN-NEXT: s_or_b64 s[4:5], s[4:5], exec
; GCN-NEXT: s_cmp_gt_i32 s6, -1 ; GCN-NEXT: s_cmp_gt_i32 s6, -1
; GCN-NEXT: s_cbranch_scc1 BB5_3 ; GCN-NEXT: s_cbranch_scc1 .LBB5_3
; GCN-NEXT: ; %bb.2: ; %bb4 ; GCN-NEXT: ; %bb.2: ; %bb4
; GCN-NEXT: ; in Loop: Header=BB5_1 Depth=1 ; GCN-NEXT: ; in Loop: Header=BB5_1 Depth=1
; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc ; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1 ; GCN-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1
; GCN-NEXT: s_andn2_b64 s[4:5], s[4:5], exec ; GCN-NEXT: s_andn2_b64 s[4:5], s[4:5], exec
; GCN-NEXT: s_and_b64 s[8:9], vcc, exec ; GCN-NEXT: s_and_b64 s[8:9], vcc, exec
; GCN-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9] ; GCN-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
; GCN-NEXT: BB5_3: ; %Flow ; GCN-NEXT: .LBB5_3: ; %Flow
; GCN-NEXT: ; in Loop: Header=BB5_1 Depth=1 ; GCN-NEXT: ; in Loop: Header=BB5_1 Depth=1
; GCN-NEXT: s_xor_b64 s[8:9], s[4:5], -1 ; GCN-NEXT: s_xor_b64 s[8:9], s[4:5], -1
; GCN-NEXT: s_add_i32 s6, s6, 1 ; GCN-NEXT: s_add_i32 s6, s6, 1
; GCN-NEXT: s_and_b64 s[8:9], exec, s[8:9] ; GCN-NEXT: s_and_b64 s[8:9], exec, s[8:9]
; GCN-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1] ; GCN-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1]
; GCN-NEXT: s_andn2_b64 exec, exec, s[0:1] ; GCN-NEXT: s_andn2_b64 exec, exec, s[0:1]
; GCN-NEXT: s_cbranch_execnz BB5_1 ; GCN-NEXT: s_cbranch_execnz .LBB5_1
; GCN-NEXT: ; %bb.4: ; %bb9 ; GCN-NEXT: ; %bb.4: ; %bb9
; GCN-NEXT: s_or_b64 exec, exec, s[0:1] ; GCN-NEXT: s_or_b64 exec, exec, s[0:1]
; GCN-NEXT: v_mov_b32_e32 v0, 7 ; GCN-NEXT: v_mov_b32_e32 v0, 7
; GCN-NEXT: s_mov_b32 m0, -1 ; GCN-NEXT: s_mov_b32 m0, -1
; GCN-NEXT: ds_write_b32 v0, v0 ; GCN-NEXT: ds_write_b32 v0, v0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
bb: bb:
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
Show All 28 Lines

llvm/test/CodeGen/AMDGPU/mfma-loop.ll

; RUN: llc -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX908,GFX908_A %s ; RUN: llc -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX908,GFX908_A %s
; RUN: llc -march=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX90A,GFX908_A %s ; RUN: llc -march=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX90A,GFX908_A %s
; GCN-LABEL: {{^}}test_mfma_loop_zeroinit: ; GCN-LABEL: {{^}}test_mfma_loop_zeroinit:
; GFX908-COUNT-32: v_accvgpr_write_b32 a{{[0-9]+}}, 0{{$}} ; GFX908-COUNT-32: v_accvgpr_write_b32 a{{[0-9]+}}, 0{{$}}
; GFX90A: v_accvgpr_write_b32 [[LEAD:a[0-9]+]], 0 ; GFX90A: v_accvgpr_write_b32 [[LEAD:a[0-9]+]], 0
; GFX90A-COUNT-31: v_accvgpr_mov_b32 a{{[0-9]+}}, [[LEAD]] ; GFX90A-COUNT-31: v_accvgpr_mov_b32 a{{[0-9]+}}, [[LEAD]]
; Check that we do not copy agprs to vgprs and back inside the loop. ; Check that we do not copy agprs to vgprs and back inside the loop.
; GCN: [[LOOP:BB[0-9_]+]]: ; GCN: [[LOOP:.LBB[0-9_]+]]:
; GCN-NOT: v_accvgpr ; GCN-NOT: v_accvgpr
; GFX908_A: v_mfma_f32_32x32x1f32 ; GFX908_A: v_mfma_f32_32x32x1f32
; GCN-NOT: v_accvgpr ; GCN-NOT: v_accvgpr
; GCN: s_cbranch_scc1 [[LOOP]] ; GCN: s_cbranch_scc1 [[LOOP]]
; Final result should be read only once after the loop. ; Final result should be read only once after the loop.
; GFX908-COUNT-32: v_accvgpr_read_b32 ; GFX908-COUNT-32: v_accvgpr_read_b32
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; 3 vgprs are needed to avoid wait states between writes. ; 3 vgprs are needed to avoid wait states between writes.
; Check that we do not use 32 temp sgprs as well. ; Check that we do not use 32 temp sgprs as well.
; GFX908_A: v_mov_b32_e32 [[TMP:v[0-9]+]], 0x42f60000 ; GFX908_A: v_mov_b32_e32 [[TMP:v[0-9]+]], 0x42f60000
; GFX908-COUNT-32: v_accvgpr_write_b32 a{{[0-9]+}}, [[TMP]] ; GFX908-COUNT-32: v_accvgpr_write_b32 a{{[0-9]+}}, [[TMP]]
; GFX90A: v_accvgpr_write_b32 [[LEAD:a[0-9]+]], [[TMP]] ; GFX90A: v_accvgpr_write_b32 [[LEAD:a[0-9]+]], [[TMP]]
; GFX90A-COUNT-31: v_accvgpr_mov_b32 a{{[0-9]+}}, [[LEAD]] ; GFX90A-COUNT-31: v_accvgpr_mov_b32 a{{[0-9]+}}, [[LEAD]]
; GCN: [[LOOP:BB[0-9_]+]]: ; GCN: [[LOOP:.LBB[0-9_]+]]:
; GCN-NOT: v_accvgpr ; GCN-NOT: v_accvgpr
; GFX908_A: v_mfma_f32_32x32x1f32 ; GFX908_A: v_mfma_f32_32x32x1f32
; GCN-NOT: v_accvgpr ; GCN-NOT: v_accvgpr
; GCN: s_cbranch_scc1 [[LOOP]] ; GCN: s_cbranch_scc1 [[LOOP]]
; GFX908-COUNT-32: v_accvgpr_read_b32 ; GFX908-COUNT-32: v_accvgpr_read_b32
; GFX90A-NOT: v_accvgpr_read_b32 ; GFX90A-NOT: v_accvgpr_read_b32
; GFX908-COUNT-8: global_store_dwordx4 v{{[0-9]+}}, v[{{[0-9:]+}}] ; GFX908-COUNT-8: global_store_dwordx4 v{{[0-9]+}}, v[{{[0-9:]+}}]
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; GCN-LABEL: {{^}}test_mfma_loop_non_splat: ; GCN-LABEL: {{^}}test_mfma_loop_non_splat:
; GCN: v_accvgpr_write_b32 [[LEAD:a[0-9]+]], 0{{$}} ; GCN: v_accvgpr_write_b32 [[LEAD:a[0-9]+]], 0{{$}}
; GCN: v_accvgpr_write_b32 a{{[0-9]+}}, 1.0{{$}} ; GCN: v_accvgpr_write_b32 a{{[0-9]+}}, 1.0{{$}}
; GFX908-COUNT-30: v_accvgpr_write_b32 a{{[0-9]+}}, 0{{$}} ; GFX908-COUNT-30: v_accvgpr_write_b32 a{{[0-9]+}}, 0{{$}}
; GFX90A-COUNT-30: v_accvgpr_mov_b32 a{{[0-9]+}}, [[LEAD]]{{$}} ; GFX90A-COUNT-30: v_accvgpr_mov_b32 a{{[0-9]+}}, [[LEAD]]{{$}}
; GCN: [[LOOP:BB[0-9_]+]]: ; GCN: [[LOOP:.LBB[0-9_]+]]:
; GCN-NOT: v_accvgpr ; GCN-NOT: v_accvgpr
; GFX908_A: v_mfma_f32_32x32x1f32 ; GFX908_A: v_mfma_f32_32x32x1f32
; GCN-NOT: v_accvgpr ; GCN-NOT: v_accvgpr
; GCN: s_cbranch_scc1 [[LOOP]] ; GCN: s_cbranch_scc1 [[LOOP]]
; GFX908-COUNT-32: v_accvgpr_read_b32 ; GFX908-COUNT-32: v_accvgpr_read_b32
; GFX90A-NOT: v_accvgpr_read_b32 ; GFX90A-NOT: v_accvgpr_read_b32
; GFX908-COUNT-8: global_store_dwordx4 v{{[0-9]+}}, v[{{[0-9:]+}}] ; GFX908-COUNT-8: global_store_dwordx4 v{{[0-9]+}}, v[{{[0-9:]+}}]
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; GFX90A: v_mov_b32_e32 [[TMP:v[0-9]+]], 0x4{{[0-9a-f]+}} ; GFX90A: v_mov_b32_e32 [[TMP:v[0-9]+]], 0x4{{[0-9a-f]+}}
; GFX90A: v_accvgpr_write_b32 a{{[0-9]+}}, [[TMP]] ; GFX90A: v_accvgpr_write_b32 a{{[0-9]+}}, [[TMP]]
; GFX90A: v_mov_b32_e32 [[TMP:v[0-9]+]], 0x4{{[0-9a-f]+}} ; GFX90A: v_mov_b32_e32 [[TMP:v[0-9]+]], 0x4{{[0-9a-f]+}}
; GFX90A: v_accvgpr_write_b32 a{{[0-9]+}}, [[TMP]] ; GFX90A: v_accvgpr_write_b32 a{{[0-9]+}}, [[TMP]]
; GFX90A: v_mov_b32_e32 [[TMP:v[0-9]+]], 0x4{{[0-9a-f]+}} ; GFX90A: v_mov_b32_e32 [[TMP:v[0-9]+]], 0x4{{[0-9a-f]+}}
; GFX90A: v_accvgpr_write_b32 a{{[0-9]+}}, [[TMP]] ; GFX90A: v_accvgpr_write_b32 a{{[0-9]+}}, [[TMP]]
; GCN: [[LOOP:BB[0-9_]+]]: ; GCN: [[LOOP:.LBB[0-9_]+]]:
; GCN-NOT: v_accvgpr ; GCN-NOT: v_accvgpr
; GFX908_A: v_mfma_f32_32x32x1f32 ; GFX908_A: v_mfma_f32_32x32x1f32
; GCN-NOT: v_accvgpr ; GCN-NOT: v_accvgpr
; GCN: s_cbranch_scc1 [[LOOP]] ; GCN: s_cbranch_scc1 [[LOOP]]
; GFX908-COUNT-32: v_accvgpr_read_b32 ; GFX908-COUNT-32: v_accvgpr_read_b32
; GFX90A-NOT: v_accvgpr_read_b32 ; GFX90A-NOT: v_accvgpr_read_b32
; GFX908-COUNT-8: global_store_dwordx4 v{{[0-9]+}}, v[{{[0-9:]+}}] ; GFX908-COUNT-8: global_store_dwordx4 v{{[0-9]+}}, v[{{[0-9:]+}}]
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store <32 x float> %mai.1, <32 x float> addrspace(1)* %arg store <32 x float> %mai.1, <32 x float> addrspace(1)* %arg
ret void ret void
} }
; GCN-LABEL: {{^}}test_mfma_loop_vgpr_init: ; GCN-LABEL: {{^}}test_mfma_loop_vgpr_init:
; GCN-COUNT-32: v_accvgpr_write_b32 a{{[0-9]+}}, v0{{$}} ; GCN-COUNT-32: v_accvgpr_write_b32 a{{[0-9]+}}, v0{{$}}
; GCN: [[LOOP:BB[0-9_]+]]: ; GCN: [[LOOP:.LBB[0-9_]+]]:
; GCN-NOT: v_accvgpr ; GCN-NOT: v_accvgpr
; GFX908_A: v_mfma_f32_32x32x1f32 ; GFX908_A: v_mfma_f32_32x32x1f32
; GCN-NOT: v_accvgpr ; GCN-NOT: v_accvgpr
; GCN: s_cbranch_scc1 [[LOOP]] ; GCN: s_cbranch_scc1 [[LOOP]]
; GFX908-COUNT-32: v_accvgpr_read_b32 ; GFX908-COUNT-32: v_accvgpr_read_b32
; GFX90A-NOT: v_accvgpr_read_b32 ; GFX90A-NOT: v_accvgpr_read_b32
; GFX908-COUNT-8: global_store_dwordx4 v{{[0-9]+}}, v[{{[0-9:]+}}] ; GFX908-COUNT-8: global_store_dwordx4 v{{[0-9]+}}, v[{{[0-9:]+}}]
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; GCN-LABEL: {{^}}test_mfma_loop_sgpr_init: ; GCN-LABEL: {{^}}test_mfma_loop_sgpr_init:
; GFX908_A: v_mov_b32_e32 [[TMP:v[0-9]+]], s{{[0-9]+}} ; GFX908_A: v_mov_b32_e32 [[TMP:v[0-9]+]], s{{[0-9]+}}
; GFX908-COUNT-32: v_accvgpr_write_b32 a{{[0-9]+}}, [[TMP]] ; GFX908-COUNT-32: v_accvgpr_write_b32 a{{[0-9]+}}, [[TMP]]
; GFX90A: v_accvgpr_write_b32 [[LEAD:a[0-9]+]], [[TMP]] ; GFX90A: v_accvgpr_write_b32 [[LEAD:a[0-9]+]], [[TMP]]
; GFX90A-COUNT-31: v_accvgpr_mov_b32 a{{[0-9]+}}, [[LEAD]] ; GFX90A-COUNT-31: v_accvgpr_mov_b32 a{{[0-9]+}}, [[LEAD]]
; GCN: [[LOOP:BB[0-9_]+]]: ; GCN: [[LOOP:.LBB[0-9_]+]]:
; GCN-NOT: v_accvgpr ; GCN-NOT: v_accvgpr
; GFX908_A: v_mfma_f32_32x32x1f32 ; GFX908_A: v_mfma_f32_32x32x1f32
; GCN-NOT: v_accvgpr ; GCN-NOT: v_accvgpr
; GCN: s_cbranch_scc1 [[LOOP]] ; GCN: s_cbranch_scc1 [[LOOP]]
; GFX908-COUNT-32: v_accvgpr_read_b32 ; GFX908-COUNT-32: v_accvgpr_read_b32
; GFX90A-NOT: v_accvgpr_read_b32 ; GFX90A-NOT: v_accvgpr_read_b32
; GFX908-COUNT-8: global_store_dwordx4 v{{[0-9]+}}, v[{{[0-9:]+}}] ; GFX908-COUNT-8: global_store_dwordx4 v{{[0-9]+}}, v[{{[0-9:]+}}]
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; GFX908-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, 0{{$}} ; GFX908-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, 0{{$}}
; GFX908-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, 0{{$}} ; GFX908-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, 0{{$}}
; GFX908-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, 0{{$}} ; GFX908-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, 0{{$}}
; GFX908-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, 0{{$}} ; GFX908-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, 0{{$}}
; GFX90A-DAG: v_accvgpr_write_b32 [[LEAD:a[0-9]+]], 0 ; GFX90A-DAG: v_accvgpr_write_b32 [[LEAD:a[0-9]+]], 0
; GFX90A-COUNT-28: v_accvgpr_mov_b32 a{{[0-9]+}}, [[LEAD]] ; GFX90A-COUNT-28: v_accvgpr_mov_b32 a{{[0-9]+}}, [[LEAD]]
; GCN: [[LOOP:BB[0-9_]+]]: ; GCN: [[LOOP:.LBB[0-9_]+]]:
; GCN-NOT: v_accvgpr ; GCN-NOT: v_accvgpr
; GFX908_A: v_mfma_f32_32x32x1f32 ; GFX908_A: v_mfma_f32_32x32x1f32
; GCN-NOT: v_accvgpr ; GCN-NOT: v_accvgpr
; GCN: s_cbranch_scc1 [[LOOP]] ; GCN: s_cbranch_scc1 [[LOOP]]
; GFX908-COUNT-32: v_accvgpr_read_b32 ; GFX908-COUNT-32: v_accvgpr_read_b32
; GFX90A-NOT: v_accvgpr_read_b32 ; GFX90A-NOT: v_accvgpr_read_b32
; GFX908-COUNT-8: global_store_dwordx4 v{{[0-9]+}}, v[{{[0-9:]+}}] ; GFX908-COUNT-8: global_store_dwordx4 v{{[0-9]+}}, v[{{[0-9:]+}}]
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; GFX908-COUNT-32: v_accvgpr_write_b32 a{{[0-9]+}}, 0 ; GFX908-COUNT-32: v_accvgpr_write_b32 a{{[0-9]+}}, 0
; GFX908: v_mfma_f32_32x32x1f32 a[{{[0-9:]+}}], v{{[0-9]+}}, v{{[0-9]+}}, a[{{[0-9:]+}}] ; GFX908: v_mfma_f32_32x32x1f32 a[{{[0-9:]+}}], v{{[0-9]+}}, v{{[0-9]+}}, a[{{[0-9:]+}}]
; GFX90A-NOT: v_accvgpr ; GFX90A-NOT: v_accvgpr
; GFX90A: v_mfma_f32_32x32x1f32 a[{{[0-9:]+}}], v{{[0-9]+}}, v{{[0-9]+}}, 0{{$}} ; GFX90A: v_mfma_f32_32x32x1f32 a[{{[0-9:]+}}], v{{[0-9]+}}, v{{[0-9]+}}, 0{{$}}
; GFX90A-NOT: v_accvgpr ; GFX90A-NOT: v_accvgpr
; GCN-NOT: v_accvgpr ; GCN-NOT: v_accvgpr
; GCN: [[LOOP:BB[0-9_]+]]: ; GCN: [[LOOP:.LBB[0-9_]+]]:
; GCN-NOT: v_accvgpr ; GCN-NOT: v_accvgpr
; GFX908_A: v_mfma_f32_32x32x1f32 ; GFX908_A: v_mfma_f32_32x32x1f32
; GCN-NOT: v_accvgpr ; GCN-NOT: v_accvgpr
; GCN: s_cbranch_scc1 [[LOOP]] ; GCN: s_cbranch_scc1 [[LOOP]]
; GFX908-COUNT-32: v_accvgpr_read_b32 ; GFX908-COUNT-32: v_accvgpr_read_b32
; GFX90A-NOT: v_accvgpr_read_b32 ; GFX90A-NOT: v_accvgpr_read_b32
; GFX908-COUNT-8: global_store_dwordx4 v{{[0-9]+}}, v[{{[0-9:]+}}] ; GFX908-COUNT-8: global_store_dwordx4 v{{[0-9]+}}, v[{{[0-9:]+}}]
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; Check that we are using only one tmp VGPR. ; Check that we are using only one tmp VGPR.
; GCN: v_accvgpr_read_b32 [[TMP:v[0-9]+]], a{{[0-9]+}} ; GCN: v_accvgpr_read_b32 [[TMP:v[0-9]+]], a{{[0-9]+}}
; GFX908-COUNT-31: v_accvgpr_write_b32 a{{[0-9]+}}, [[TMP]]{{$}} ; GFX908-COUNT-31: v_accvgpr_write_b32 a{{[0-9]+}}, [[TMP]]{{$}}
; GFX90A: v_accvgpr_write_b32 [[LEAD:a[0-9]+]], [[TMP]]{{$}} ; GFX90A: v_accvgpr_write_b32 [[LEAD:a[0-9]+]], [[TMP]]{{$}}
; GFX90A-COUNT-29: v_accvgpr_mov_b32 a{{[0-9]+}}, [[LEAD]] ; GFX90A-COUNT-29: v_accvgpr_mov_b32 a{{[0-9]+}}, [[LEAD]]
; GCN: [[LOOP:BB[0-9_]+]]: ; GCN: [[LOOP:.LBB[0-9_]+]]:
; GCN-NOT: v_accvgpr ; GCN-NOT: v_accvgpr
; GFX908_A: v_mfma_f32_32x32x1f32 ; GFX908_A: v_mfma_f32_32x32x1f32
; GCN-NOT: v_accvgpr ; GCN-NOT: v_accvgpr
; GCN: s_cbranch_scc1 [[LOOP]] ; GCN: s_cbranch_scc1 [[LOOP]]
; GFX908-COUNT-32: v_accvgpr_read_b32 ; GFX908-COUNT-32: v_accvgpr_read_b32
; GFX90A-NOT: v_accvgpr_read_b32 ; GFX90A-NOT: v_accvgpr_read_b32
; GFX908-COUNT-8: global_store_dwordx4 v{{[0-9]+}}, v[{{[0-9:]+}}] ; GFX908-COUNT-8: global_store_dwordx4 v{{[0-9]+}}, v[{{[0-9:]+}}]
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; GCN-LABEL: {{^}}test_mfma_nested_loop_zeroinit: ; GCN-LABEL: {{^}}test_mfma_nested_loop_zeroinit:
; GFX908-COUNT-32: v_accvgpr_write_b32 a{{[0-9]+}}, 0{{$}} ; GFX908-COUNT-32: v_accvgpr_write_b32 a{{[0-9]+}}, 0{{$}}
; GFX90A: v_accvgpr_write_b32 [[LEAD:a[0-9]+]], 0 ; GFX90A: v_accvgpr_write_b32 [[LEAD:a[0-9]+]], 0
; GFX90A-COUNT-31: v_accvgpr_mov_b32 a{{[0-9]+}}, [[LEAD]] ; GFX90A-COUNT-31: v_accvgpr_mov_b32 a{{[0-9]+}}, [[LEAD]]
; Check that we do not copy agprs to vgprs and back in an outer loop. ; Check that we do not copy agprs to vgprs and back in an outer loop.
; GCN: [[OUTER_LOOP:BB[0-9_]+]]: ; GCN: [[OUTER_LOOP:.LBB[0-9_]+]]:
; GCN-NOT: v_accvgpr ; GCN-NOT: v_accvgpr
; GCN: [[INNER_LOOP:BB[0-9_]+]]: ; GCN: [[INNER_LOOP:.LBB[0-9_]+]]:
; GCN-NOT: v_accvgpr ; GCN-NOT: v_accvgpr
; GFX908_A: v_mfma_f32_32x32x1f32 ; GFX908_A: v_mfma_f32_32x32x1f32
; GCN-NOT: v_accvgpr ; GCN-NOT: v_accvgpr
; GCN: s_cbranch_scc1 [[INNER_LOOP]] ; GCN: s_cbranch_scc1 [[INNER_LOOP]]
; GCN-NOT: v_accvgpr ; GCN-NOT: v_accvgpr
; GCN: s_cbranch_scc1 [[OUTER_LOOP]] ; GCN: s_cbranch_scc1 [[OUTER_LOOP]]
; Final result should be read only once after the loop. ; Final result should be read only once after the loop.
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llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll

; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=W64 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=W64
; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -verify-machineinstrs -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=W32 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -verify-machineinstrs -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=W32
; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=W64 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=W64
; RUN: llc -O0 -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=W64-O0 ; RUN: llc -O0 -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=W64-O0
; Test that we correctly legalize VGPR Rsrc operands in MUBUF instructions. ; Test that we correctly legalize VGPR Rsrc operands in MUBUF instructions.
; W64-LABEL: mubuf_vgpr ; W64-LABEL: mubuf_vgpr
; W64: s_mov_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], exec ; W64: s_mov_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], exec
; W64: [[LOOPBB:BB[0-9]+_[0-9]+]]: ; W64: [[LOOPBB:.LBB[0-9]+_[0-9]+]]:
; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]]
; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]]
; W64-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]]
; W64-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]]
; W64: v_cmp_eq_u64_e32 vcc, s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}} ; W64: v_cmp_eq_u64_e32 vcc, s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}}
; W64: v_cmp_eq_u64_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}} ; W64: v_cmp_eq_u64_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}}
; W64: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[CMP0]] ; W64: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[CMP0]]
; W64: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[AND]] ; W64: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[AND]]
; W64: buffer_load_format_x [[RES:v[0-9]+]], v{{[0-9]+}}, s{{\[}}[[SRSRC0]]:[[SRSRC3]]{{\]}}, 0 idxen ; W64: buffer_load_format_x [[RES:v[0-9]+]], v{{[0-9]+}}, s{{\[}}[[SRSRC0]]:[[SRSRC3]]{{\]}}, 0 idxen
; W64: s_xor_b64 exec, exec, [[AND]] ; W64: s_xor_b64 exec, exec, [[AND]]
; W64: s_cbranch_execnz [[LOOPBB]] ; W64: s_cbranch_execnz [[LOOPBB]]
; W64: s_mov_b64 exec, [[SAVEEXEC]] ; W64: s_mov_b64 exec, [[SAVEEXEC]]
; W64: v_mov_b32_e32 v0, [[RES]] ; W64: v_mov_b32_e32 v0, [[RES]]
; W32-LABEL: mubuf_vgpr ; W32-LABEL: mubuf_vgpr
; W32: s_mov_b32 [[SAVEEXEC:s[0-9]+]], exec_lo ; W32: s_mov_b32 [[SAVEEXEC:s[0-9]+]], exec_lo
; W32: [[LOOPBB:BB[0-9]+_[0-9]+]]: ; W32: [[LOOPBB:.LBB[0-9]+_[0-9]+]]:
; W32-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]]
; W32-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]]
; W32-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]]
; W32-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]]
; W32: v_cmp_eq_u64_e32 vcc_lo, s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}} ; W32: v_cmp_eq_u64_e32 vcc_lo, s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}}
; W32: v_cmp_eq_u64_e64 [[CMP0:s[0-9]+]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}} ; W32: v_cmp_eq_u64_e64 [[CMP0:s[0-9]+]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}}
; W32: s_and_b32 [[AND:s[0-9]+]], vcc_lo, [[CMP0]] ; W32: s_and_b32 [[AND:s[0-9]+]], vcc_lo, [[CMP0]]
; W32: s_and_saveexec_b32 [[SAVE:s[0-9]+]], [[AND]] ; W32: s_and_saveexec_b32 [[SAVE:s[0-9]+]], [[AND]]
; W32: buffer_load_format_x [[RES:v[0-9]+]], v{{[0-9]+}}, s{{\[}}[[SRSRC0]]:[[SRSRC3]]{{\]}}, 0 idxen ; W32: buffer_load_format_x [[RES:v[0-9]+]], v{{[0-9]+}}, s{{\[}}[[SRSRC0]]:[[SRSRC3]]{{\]}}, 0 idxen
; W32: s_xor_b32 exec_lo, exec_lo, [[SAVE]] ; W32: s_xor_b32 exec_lo, exec_lo, [[SAVE]]
; W32: s_cbranch_execnz [[LOOPBB]] ; W32: s_cbranch_execnz [[LOOPBB]]
; W32: s_mov_b32 exec_lo, [[SAVEEXEC]] ; W32: s_mov_b32 exec_lo, [[SAVEEXEC]]
; W32: v_mov_b32_e32 v0, [[RES]] ; W32: v_mov_b32_e32 v0, [[RES]]
define float @mubuf_vgpr(<4 x i32> %i, i32 %c) #0 { define float @mubuf_vgpr(<4 x i32> %i, i32 %c) #0 {
%call = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %i, i32 %c, i32 0, i32 0, i32 0) #1 %call = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %i, i32 %c, i32 0, i32 0, i32 0) #1
ret float %call ret float %call
} }
; W64-LABEL: mubuf_vgpr_adjacent_in_block ; W64-LABEL: mubuf_vgpr_adjacent_in_block
; W64: s_mov_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], exec ; W64: s_mov_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], exec
; W64: [[LOOPBB0:BB[0-9]+_[0-9]+]]: ; W64: [[LOOPBB0:.LBB[0-9]+_[0-9]+]]:
; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]]
; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]]
; W64-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]]
; W64-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]]
; W64: v_cmp_eq_u64_e32 vcc, s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}} ; W64: v_cmp_eq_u64_e32 vcc, s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}}
; W64: v_cmp_eq_u64_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}} ; W64: v_cmp_eq_u64_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}}
; W64: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[CMP0]] ; W64: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[CMP0]]
; W64: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[AND]] ; W64: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[AND]]
; W64: buffer_load_format_x [[RES0:v[0-9]+]], v{{[0-9]+}}, s{{\[}}[[SRSRC0]]:[[SRSRC3]]{{\]}}, 0 idxen ; W64: buffer_load_format_x [[RES0:v[0-9]+]], v{{[0-9]+}}, s{{\[}}[[SRSRC0]]:[[SRSRC3]]{{\]}}, 0 idxen
; W64: s_xor_b64 exec, exec, [[SAVE]] ; W64: s_xor_b64 exec, exec, [[SAVE]]
; W64: s_cbranch_execnz [[LOOPBB0]] ; W64: s_cbranch_execnz [[LOOPBB0]]
; W64: s_mov_b64 exec, [[SAVEEXEC]] ; W64: s_mov_b64 exec, [[SAVEEXEC]]
; FIXME: redundant s_mov ; FIXME: redundant s_mov
; W64: s_mov_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], exec ; W64: s_mov_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], exec
; W64: [[LOOPBB1:BB[0-9]+_[0-9]+]]: ; W64: [[LOOPBB1:.LBB[0-9]+_[0-9]+]]:
; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]]
; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]]
; W64-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]]
; W64-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]]
; W64: v_cmp_eq_u64_e32 vcc, s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}} ; W64: v_cmp_eq_u64_e32 vcc, s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}}
; W64: v_cmp_eq_u64_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}} ; W64: v_cmp_eq_u64_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}}
; W64: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[CMP0]] ; W64: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[CMP0]]
; W64: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[AND]] ; W64: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[AND]]
; W64: buffer_load_format_x [[RES1:v[0-9]+]], v{{[0-9]+}}, s{{\[}}[[SRSRC0]]:[[SRSRC3]]{{\]}}, 0 idxen ; W64: buffer_load_format_x [[RES1:v[0-9]+]], v{{[0-9]+}}, s{{\[}}[[SRSRC0]]:[[SRSRC3]]{{\]}}, 0 idxen
; W64: s_xor_b64 exec, exec, [[SAVE]] ; W64: s_xor_b64 exec, exec, [[SAVE]]
; W64: s_cbranch_execnz [[LOOPBB1]] ; W64: s_cbranch_execnz [[LOOPBB1]]
; W64: s_mov_b64 exec, [[SAVEEXEC]] ; W64: s_mov_b64 exec, [[SAVEEXEC]]
; W64-DAG: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES0]], off ; W64-DAG: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES0]], off
; W64-DAG: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES1]], off ; W64-DAG: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES1]], off
; W32-LABEL: mubuf_vgpr_adjacent_in_block ; W32-LABEL: mubuf_vgpr_adjacent_in_block
; W32: s_mov_b32 [[SAVEEXEC:s[0-9]+]], exec_lo ; W32: s_mov_b32 [[SAVEEXEC:s[0-9]+]], exec_lo
; W32: [[LOOPBB0:BB[0-9]+_[0-9]+]]: ; W32: [[LOOPBB0:.LBB[0-9]+_[0-9]+]]:
; W32-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]]
; W32-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]]
; W32-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]]
; W32-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]]
; W32: v_cmp_eq_u64_e32 vcc_lo, s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}} ; W32: v_cmp_eq_u64_e32 vcc_lo, s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}}
; W32: v_cmp_eq_u64_e64 [[CMP0:s[0-9]+]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}} ; W32: v_cmp_eq_u64_e64 [[CMP0:s[0-9]+]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}}
; W32: s_and_b32 [[AND:s[0-9]+]], vcc_lo, [[CMP0]] ; W32: s_and_b32 [[AND:s[0-9]+]], vcc_lo, [[CMP0]]
; W32: s_and_saveexec_b32 [[SAVE:s[0-9]+]], [[AND]] ; W32: s_and_saveexec_b32 [[SAVE:s[0-9]+]], [[AND]]
; W32: buffer_load_format_x [[RES0:v[0-9]+]], v{{[0-9]+}}, s{{\[}}[[SRSRC0]]:[[SRSRC3]]{{\]}}, 0 idxen ; W32: buffer_load_format_x [[RES0:v[0-9]+]], v{{[0-9]+}}, s{{\[}}[[SRSRC0]]:[[SRSRC3]]{{\]}}, 0 idxen
; W32: s_xor_b32 exec_lo, exec_lo, [[SAVE]] ; W32: s_xor_b32 exec_lo, exec_lo, [[SAVE]]
; W32: s_cbranch_execnz [[LOOPBB0]] ; W32: s_cbranch_execnz [[LOOPBB0]]
; W32: s_mov_b32 exec_lo, [[SAVEEXEC]] ; W32: s_mov_b32 exec_lo, [[SAVEEXEC]]
; FIXME: redundant s_mov ; FIXME: redundant s_mov
; W32: s_mov_b32 [[SAVEEXEC:s[0-9]+]], exec_lo ; W32: s_mov_b32 [[SAVEEXEC:s[0-9]+]], exec_lo
; W32: [[LOOPBB1:BB[0-9]+_[0-9]+]]: ; W32: [[LOOPBB1:.LBB[0-9]+_[0-9]+]]:
; W32-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]]
; W32-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]]
; W32-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]]
; W32-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]]
; W32: v_cmp_eq_u64_e32 vcc_lo, s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}} ; W32: v_cmp_eq_u64_e32 vcc_lo, s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}}
; W32: v_cmp_eq_u64_e64 [[CMP0:s[0-9]+]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}} ; W32: v_cmp_eq_u64_e64 [[CMP0:s[0-9]+]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}}
; W32: s_and_b32 [[AND:s[0-9]+]], vcc_lo, [[CMP0]] ; W32: s_and_b32 [[AND:s[0-9]+]], vcc_lo, [[CMP0]]
; W32: s_and_saveexec_b32 [[SAVE:s[0-9]+]], [[AND]] ; W32: s_and_saveexec_b32 [[SAVE:s[0-9]+]], [[AND]]
Show All 15 Lines
} }
; W64-LABEL: mubuf_vgpr_outside_entry ; W64-LABEL: mubuf_vgpr_outside_entry
; W64-DAG: v_mov_b32_e32 [[IDX:v[0-9]+]], s{{[0-9]+}} ; W64-DAG: v_mov_b32_e32 [[IDX:v[0-9]+]], s{{[0-9]+}}
; W64-DAG: s_mov_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], exec ; W64-DAG: s_mov_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], exec
; W64: [[LOOPBB0:BB[0-9]+_[0-9]+]]: ; W64: [[LOOPBB0:.LBB[0-9]+_[0-9]+]]:
; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]]
; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]]
; W64-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]]
; W64-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]]
; W64: v_cmp_eq_u64_e32 vcc, s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}} ; W64: v_cmp_eq_u64_e32 vcc, s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}}
; W64: v_cmp_eq_u64_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}} ; W64: v_cmp_eq_u64_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}}
; W64: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[CMP0]] ; W64: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[CMP0]]
; W64: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[AND]] ; W64: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[AND]]
; W64: buffer_load_format_x [[RES:v[0-9]+]], [[IDX]], s{{\[}}[[SRSRC0]]:[[SRSRC3]]{{\]}}, 0 idxen ; W64: buffer_load_format_x [[RES:v[0-9]+]], [[IDX]], s{{\[}}[[SRSRC0]]:[[SRSRC3]]{{\]}}, 0 idxen
; W64: s_xor_b64 exec, exec, [[SAVE]] ; W64: s_xor_b64 exec, exec, [[SAVE]]
; W64: s_cbranch_execnz [[LOOPBB0]] ; W64: s_cbranch_execnz [[LOOPBB0]]
; W64: s_mov_b64 exec, [[SAVEEXEC]] ; W64: s_mov_b64 exec, [[SAVEEXEC]]
; W64: s_cbranch_execz [[TERMBB:BB[0-9]+_[0-9]+]] ; W64: s_cbranch_execz [[TERMBB:.LBB[0-9]+_[0-9]+]]
; W64: ; %bb.{{[0-9]+}}: ; W64: ; %bb.{{[0-9]+}}:
; W64-DAG: v_mov_b32_e32 [[IDX:v[0-9]+]], s{{[0-9]+}} ; W64-DAG: v_mov_b32_e32 [[IDX:v[0-9]+]], s{{[0-9]+}}
; W64-DAG: s_mov_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], exec ; W64-DAG: s_mov_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], exec
; W64: [[LOOPBB1:BB[0-9]+_[0-9]+]]: ; W64: [[LOOPBB1:.LBB[0-9]+_[0-9]+]]:
; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]]
; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]]
; W64-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]]
; W64-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]]
; W64: v_cmp_eq_u64_e32 vcc, s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}} ; W64: v_cmp_eq_u64_e32 vcc, s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}}
; W64: v_cmp_eq_u64_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}} ; W64: v_cmp_eq_u64_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}}
; W64: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[CMP0]] ; W64: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[CMP0]]
; W64: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[AND]] ; W64: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[AND]]
; W64: buffer_load_format_x [[RES]], [[IDX]], s{{\[}}[[SRSRC0]]:[[SRSRC3]]{{\]}}, 0 idxen ; W64: buffer_load_format_x [[RES]], [[IDX]], s{{\[}}[[SRSRC0]]:[[SRSRC3]]{{\]}}, 0 idxen
; W64: s_xor_b64 exec, exec, [[SAVE]] ; W64: s_xor_b64 exec, exec, [[SAVE]]
; W64: s_cbranch_execnz [[LOOPBB1]] ; W64: s_cbranch_execnz [[LOOPBB1]]
; W64: s_mov_b64 exec, [[SAVEEXEC]] ; W64: s_mov_b64 exec, [[SAVEEXEC]]
; W64: [[TERMBB]]: ; W64: [[TERMBB]]:
; W64: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES]], off ; W64: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES]], off
; W32-LABEL: mubuf_vgpr_outside_entry ; W32-LABEL: mubuf_vgpr_outside_entry
; W32-DAG: v_mov_b32_e32 [[IDX:v[0-9]+]], s4 ; W32-DAG: v_mov_b32_e32 [[IDX:v[0-9]+]], s4
; W32-DAG: s_mov_b32 [[SAVEEXEC:s[0-9]+]], exec_lo ; W32-DAG: s_mov_b32 [[SAVEEXEC:s[0-9]+]], exec_lo
; W32: [[LOOPBB0:BB[0-9]+_[0-9]+]]: ; W32: [[LOOPBB0:.LBB[0-9]+_[0-9]+]]:
; W32-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]]
; W32-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]]
; W32-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]]
; W32-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]]
; W32: v_cmp_eq_u64_e32 vcc_lo, s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}} ; W32: v_cmp_eq_u64_e32 vcc_lo, s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}}
; W32: v_cmp_eq_u64_e64 [[CMP0:s[0-9]+]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}} ; W32: v_cmp_eq_u64_e64 [[CMP0:s[0-9]+]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}}
; W32: s_and_b32 [[AND:s[0-9]+]], vcc_lo, [[CMP0]] ; W32: s_and_b32 [[AND:s[0-9]+]], vcc_lo, [[CMP0]]
; W32: s_and_saveexec_b32 [[SAVE:s[0-9]+]], [[AND]] ; W32: s_and_saveexec_b32 [[SAVE:s[0-9]+]], [[AND]]
; W32: buffer_load_format_x [[RES:v[0-9]+]], [[IDX]], s{{\[}}[[SRSRC0]]:[[SRSRC3]]{{\]}}, 0 idxen ; W32: buffer_load_format_x [[RES:v[0-9]+]], [[IDX]], s{{\[}}[[SRSRC0]]:[[SRSRC3]]{{\]}}, 0 idxen
; W32: s_xor_b32 exec_lo, exec_lo, [[SAVE]] ; W32: s_xor_b32 exec_lo, exec_lo, [[SAVE]]
; W32: s_cbranch_execnz [[LOOPBB0]] ; W32: s_cbranch_execnz [[LOOPBB0]]
; W32: s_mov_b32 exec_lo, [[SAVEEXEC]] ; W32: s_mov_b32 exec_lo, [[SAVEEXEC]]
; W32: s_cbranch_execz [[TERMBB:BB[0-9]+_[0-9]+]] ; W32: s_cbranch_execz [[TERMBB:.LBB[0-9]+_[0-9]+]]
; W32: ; %bb.{{[0-9]+}}: ; W32: ; %bb.{{[0-9]+}}:
; W32-DAG: v_mov_b32_e32 [[IDX:v[0-9]+]], s4 ; W32-DAG: v_mov_b32_e32 [[IDX:v[0-9]+]], s4
; W32-DAG: s_mov_b32 [[SAVEEXEC:s[0-9]+]], exec_lo ; W32-DAG: s_mov_b32 [[SAVEEXEC:s[0-9]+]], exec_lo
; W32: [[LOOPBB1:BB[0-9]+_[0-9]+]]: ; W32: [[LOOPBB1:.LBB[0-9]+_[0-9]+]]:
; W32-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]]
; W32-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]]
; W32-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]]
; W32-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]]
; W32: v_cmp_eq_u64_e32 vcc_lo, s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}} ; W32: v_cmp_eq_u64_e32 vcc_lo, s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}}
; W32: v_cmp_eq_u64_e64 [[CMP0:s[0-9]+]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}} ; W32: v_cmp_eq_u64_e64 [[CMP0:s[0-9]+]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}}
; W32: s_and_b32 [[AND:s[0-9]+]], vcc_lo, [[CMP0]] ; W32: s_and_b32 [[AND:s[0-9]+]], vcc_lo, [[CMP0]]
; W32: s_and_saveexec_b32 [[SAVE:s[0-9]+]], [[AND]] ; W32: s_and_saveexec_b32 [[SAVE:s[0-9]+]], [[AND]]
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; W64-O0-LABEL: mubuf_vgpr_outside_entry ; W64-O0-LABEL: mubuf_vgpr_outside_entry
; W64-O0-DAG: s_mov_b32 [[IDX_S:s[0-9]+]], s{{[0-9]+}} ; W64-O0-DAG: s_mov_b32 [[IDX_S:s[0-9]+]], s{{[0-9]+}}
; W64-O0-DAG: v_mov_b32_e32 [[IDX_V:v[0-9]+]], s{{[0-9]+}} ; W64-O0-DAG: v_mov_b32_e32 [[IDX_V:v[0-9]+]], s{{[0-9]+}}
; W64-O0-DAG: s_mov_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], exec ; W64-O0-DAG: s_mov_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], exec
; W64-O0-DAG: buffer_store_dword [[IDX_V]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} ; 4-byte Folded Spill ; W64-O0-DAG: buffer_store_dword [[IDX_V]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} ; 4-byte Folded Spill
; W64-O0: [[LOOPBB0:BB[0-9]+_[0-9]+]]: ; =>This Inner Loop Header: Depth=1 ; W64-O0: [[LOOPBB0:.LBB[0-9]+_[0-9]+]]: ; =>This Inner Loop Header: Depth=1
; W64-O0: buffer_load_dword [[IDX:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, s32 ; 4-byte Folded Reload ; W64-O0: buffer_load_dword [[IDX:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, s32 ; 4-byte Folded Reload
; W64-O0: buffer_load_dword v[[VRSRC0:[0-9]+]], off, s[0:3], s32 offset:28 ; 4-byte Folded Reload ; W64-O0: buffer_load_dword v[[VRSRC0:[0-9]+]], off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; W64-O0: buffer_load_dword v[[VRSRC1:[0-9]+]], off, s[0:3], s32 offset:32 ; 4-byte Folded Reload ; W64-O0: buffer_load_dword v[[VRSRC1:[0-9]+]], off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
; W64-O0: buffer_load_dword v[[VRSRC2:[0-9]+]], off, s[0:3], s32 offset:36 ; 4-byte Folded Reload ; W64-O0: buffer_load_dword v[[VRSRC2:[0-9]+]], off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
; W64-O0: buffer_load_dword v[[VRSRC3:[0-9]+]], off, s[0:3], s32 offset:40 ; 4-byte Folded Reload ; W64-O0: buffer_load_dword v[[VRSRC3:[0-9]+]], off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; W64-O0: s_waitcnt vmcnt(0) ; W64-O0: s_waitcnt vmcnt(0)
; W64-O0-DAG: v_readfirstlane_b32 s[[S0:[0-9]+]], v[[VRSRC0]] ; W64-O0-DAG: v_readfirstlane_b32 s[[S0:[0-9]+]], v[[VRSRC0]]
; W64-O0-DAG: v_readfirstlane_b32 s[[SRSRCTMP1:[0-9]+]], v[[VRSRC1]] ; W64-O0-DAG: v_readfirstlane_b32 s[[SRSRCTMP1:[0-9]+]], v[[VRSRC1]]
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; W64-O0: s_waitcnt vmcnt(0) ; W64-O0: s_waitcnt vmcnt(0)
; W64-O0: buffer_store_dword [[RES]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:[[RES_OFF_TMP:[0-9]+]] ; 4-byte Folded Spill ; W64-O0: buffer_store_dword [[RES]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:[[RES_OFF_TMP:[0-9]+]] ; 4-byte Folded Spill
; W64-O0: s_xor_b64 exec, exec, [[SAVE]] ; W64-O0: s_xor_b64 exec, exec, [[SAVE]]
; W64-O0-NEXT: s_cbranch_execnz [[LOOPBB0]] ; W64-O0-NEXT: s_cbranch_execnz [[LOOPBB0]]
; XXX-W64-O0: s_mov_b64 exec, [[SAVEEXEC]] ; XXX-W64-O0: s_mov_b64 exec, [[SAVEEXEC]]
; W64-O0: buffer_load_dword [[RES:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:[[RES_OFF_TMP]] ; 4-byte Folded Reload ; W64-O0: buffer_load_dword [[RES:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:[[RES_OFF_TMP]] ; 4-byte Folded Reload
; W64-O0: buffer_store_dword [[RES]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:[[RES_OFF:[0-9]+]] ; 4-byte Folded Spill ; W64-O0: buffer_store_dword [[RES]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:[[RES_OFF:[0-9]+]] ; 4-byte Folded Spill
; W64-O0: s_cbranch_execz [[TERMBB:BB[0-9]+_[0-9]+]] ; W64-O0: s_cbranch_execz [[TERMBB:.LBB[0-9]+_[0-9]+]]
; W64-O0: ; %bb.{{[0-9]+}}: ; %bb1 ; W64-O0: ; %bb.{{[0-9]+}}: ; %bb1
; W64-O0-DAG: buffer_store_dword {{v[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s32 offset:[[IDX_OFF:[0-9]+]] ; 4-byte Folded Spill ; W64-O0-DAG: buffer_store_dword {{v[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s32 offset:[[IDX_OFF:[0-9]+]] ; 4-byte Folded Spill
; W64-O0-DAG: s_mov_b64 s{{\[}}[[SAVEEXEC0:[0-9]+]]:[[SAVEEXEC1:[0-9]+]]{{\]}}, exec ; W64-O0-DAG: s_mov_b64 s{{\[}}[[SAVEEXEC0:[0-9]+]]:[[SAVEEXEC1:[0-9]+]]{{\]}}, exec
; W64-O0: v_writelane_b32 [[VSAVEEXEC:v[0-9]+]], s[[SAVEEXEC0]], [[SAVEEXEC_IDX0:[0-9]+]] ; W64-O0: v_writelane_b32 [[VSAVEEXEC:v[0-9]+]], s[[SAVEEXEC0]], [[SAVEEXEC_IDX0:[0-9]+]]
; W64-O0: v_writelane_b32 [[VSAVEEXEC]], s[[SAVEEXEC1]], [[SAVEEXEC_IDX1:[0-9]+]] ; W64-O0: v_writelane_b32 [[VSAVEEXEC]], s[[SAVEEXEC1]], [[SAVEEXEC_IDX1:[0-9]+]]
; W64-O0: [[LOOPBB1:BB[0-9]+_[0-9]+]]: ; =>This Inner Loop Header: Depth=1 ; W64-O0: [[LOOPBB1:.LBB[0-9]+_[0-9]+]]: ; =>This Inner Loop Header: Depth=1
; W64-O0: buffer_load_dword [[IDX:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, s32 offset:[[IDX_OFF]] ; 4-byte Folded Reload ; W64-O0: buffer_load_dword [[IDX:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, s32 offset:[[IDX_OFF]] ; 4-byte Folded Reload
; W64-O0: buffer_load_dword v[[VRSRC0:[0-9]+]], off, s[0:3], s32 offset:4 ; 4-byte Folded Reload ; W64-O0: buffer_load_dword v[[VRSRC0:[0-9]+]], off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; W64-O0: buffer_load_dword v[[VRSRC1:[0-9]+]], off, s[0:3], s32 offset:8 ; 4-byte Folded Reload ; W64-O0: buffer_load_dword v[[VRSRC1:[0-9]+]], off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; W64-O0: buffer_load_dword v[[VRSRC2:[0-9]+]], off, s[0:3], s32 offset:12 ; 4-byte Folded Reload ; W64-O0: buffer_load_dword v[[VRSRC2:[0-9]+]], off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; W64-O0: buffer_load_dword v[[VRSRC3:[0-9]+]], off, s[0:3], s32 offset:16 ; 4-byte Folded Reload ; W64-O0: buffer_load_dword v[[VRSRC3:[0-9]+]], off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; W64-O0: s_waitcnt vmcnt(0) ; W64-O0: s_waitcnt vmcnt(0)
; W64-O0-DAG: v_readfirstlane_b32 s[[S0:[0-9]+]], v[[VRSRC0]] ; W64-O0-DAG: v_readfirstlane_b32 s[[S0:[0-9]+]], v[[VRSRC0]]
; W64-O0-DAG: v_readfirstlane_b32 s[[SRSRCTMP1:[0-9]+]], v[[VRSRC1]] ; W64-O0-DAG: v_readfirstlane_b32 s[[SRSRCTMP1:[0-9]+]], v[[VRSRC1]]
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llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll

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; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: global_load_dword v5, v[0:1], off ; GFX9-NEXT: global_load_dword v5, v[0:1], off
; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2 ; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX9-NEXT: v_sub_u32_e32 v4, v4, v1 ; GFX9-NEXT: v_sub_u32_e32 v4, v4, v1
; GFX9-NEXT: s_mov_b64 s[4:5], 0 ; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ds_write_b32 v0, v5 ; GFX9-NEXT: ds_write_b32 v0, v5
; GFX9-NEXT: BB0_1: ; %bb23 ; GFX9-NEXT: .LBB0_1: ; %bb23
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mul_u32_u24_e32 v5, v0, v2 ; GFX9-NEXT: v_mul_u32_u24_e32 v5, v0, v2
; GFX9-NEXT: v_add_u32_e32 v0, v0, v1 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
; GFX9-NEXT: v_sub_u32_e32 v5, v4, v5 ; GFX9-NEXT: v_sub_u32_e32 v5, v4, v5
; GFX9-NEXT: v_add_u32_e32 v5, v5, v0 ; GFX9-NEXT: v_add_u32_e32 v5, v5, v0
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v5, v3 ; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v5, v3
; GFX9-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GFX9-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX9-NEXT: s_andn2_b64 exec, exec, s[4:5] ; GFX9-NEXT: s_andn2_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_cbranch_execnz BB0_1 ; GFX9-NEXT: s_cbranch_execnz .LBB0_1
; GFX9-NEXT: ; %bb.2: ; %.loopexit ; GFX9-NEXT: ; %bb.2: ; %.loopexit
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
bb: bb:
%tmp22 = and i32 %arg6, 16777215 %tmp22 = and i32 %arg6, 16777215
br label %bb23 br label %bb23
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define void @lsr_order_mul24_1(i32 %arg, i32 %arg1, i32 %arg2, float addrspace(3)* nocapture %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, float addrspace(1)* nocapture readonly %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15, i32 %arg16, i1 zeroext %arg17, i1 zeroext %arg18) #0 { define void @lsr_order_mul24_1(i32 %arg, i32 %arg1, i32 %arg2, float addrspace(3)* nocapture %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, float addrspace(1)* nocapture readonly %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15, i32 %arg16, i1 zeroext %arg17, i1 zeroext %arg18) #0 {
; GFX9-LABEL: lsr_order_mul24_1: ; GFX9-LABEL: lsr_order_mul24_1:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_and_b32_e32 v5, 1, v18 ; GFX9-NEXT: v_and_b32_e32 v5, 1, v18
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v5 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v5
; GFX9-NEXT: v_cmp_lt_u32_e64 s[4:5], v0, v1 ; GFX9-NEXT: v_cmp_lt_u32_e64 s[4:5], v0, v1
; GFX9-NEXT: s_and_saveexec_b64 s[8:9], s[4:5] ; GFX9-NEXT: s_and_saveexec_b64 s[8:9], s[4:5]
; GFX9-NEXT: s_cbranch_execz BB1_3 ; GFX9-NEXT: s_cbranch_execz .LBB1_3
; GFX9-NEXT: ; %bb.1: ; %bb19 ; GFX9-NEXT: ; %bb.1: ; %bb19
; GFX9-NEXT: v_cvt_f32_u32_e32 v7, v6 ; GFX9-NEXT: v_cvt_f32_u32_e32 v7, v6
; GFX9-NEXT: v_add_u32_e32 v4, v4, v0 ; GFX9-NEXT: v_add_u32_e32 v4, v4, v0
; GFX9-NEXT: v_and_b32_e32 v5, 0xffffff, v6 ; GFX9-NEXT: v_and_b32_e32 v5, 0xffffff, v6
; GFX9-NEXT: v_lshl_add_u32 v6, v4, 2, v3 ; GFX9-NEXT: v_lshl_add_u32 v6, v4, 2, v3
; GFX9-NEXT: v_rcp_iflag_f32_e32 v7, v7 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v7, v7
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 2, v2 ; GFX9-NEXT: v_lshlrev_b32_e32 v8, 2, v2
; GFX9-NEXT: v_add_u32_e32 v9, v17, v12 ; GFX9-NEXT: v_add_u32_e32 v9, v17, v12
; GFX9-NEXT: s_mov_b64 s[10:11], 0 ; GFX9-NEXT: s_mov_b64 s[10:11], 0
; GFX9-NEXT: v_mov_b32_e32 v3, 0x3727c5ac ; GFX9-NEXT: v_mov_b32_e32 v3, 0x3727c5ac
; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: BB1_2: ; %bb23 ; GFX9-NEXT: .LBB1_2: ; %bb23
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_cvt_f32_u32_e32 v3, v0 ; GFX9-NEXT: v_cvt_f32_u32_e32 v3, v0
; GFX9-NEXT: v_add_u32_e32 v12, v17, v0 ; GFX9-NEXT: v_add_u32_e32 v12, v17, v0
; GFX9-NEXT: v_add_u32_e32 v19, v9, v0 ; GFX9-NEXT: v_add_u32_e32 v19, v9, v0
; GFX9-NEXT: v_add_u32_e32 v0, v0, v2 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
; GFX9-NEXT: v_madak_f32 v3, v3, v7, 0x3727c5ac ; GFX9-NEXT: v_madak_f32 v3, v3, v7, 0x3727c5ac
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX9-NEXT: v_mul_u32_u24_e32 v18, v3, v5 ; GFX9-NEXT: v_mul_u32_u24_e32 v18, v3, v5
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; GFX9-NEXT: global_load_dword v3, v[18:19], off ; GFX9-NEXT: global_load_dword v3, v[18:19], off
; GFX9-NEXT: v_cmp_ge_u32_e64 s[6:7], v0, v1 ; GFX9-NEXT: v_cmp_ge_u32_e64 s[6:7], v0, v1
; GFX9-NEXT: s_or_b64 s[10:11], s[6:7], s[10:11] ; GFX9-NEXT: s_or_b64 s[10:11], s[6:7], s[10:11]
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[4:5] ; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[4:5]
; GFX9-NEXT: ds_write_b32 v6, v3 ; GFX9-NEXT: ds_write_b32 v6, v3
; GFX9-NEXT: v_add_u32_e32 v6, v6, v8 ; GFX9-NEXT: v_add_u32_e32 v6, v6, v8
; GFX9-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GFX9-NEXT: s_andn2_b64 exec, exec, s[10:11]
; GFX9-NEXT: s_cbranch_execnz BB1_2 ; GFX9-NEXT: s_cbranch_execnz .LBB1_2
; GFX9-NEXT: BB1_3: ; %Flow3 ; GFX9-NEXT: .LBB1_3: ; %Flow3
; GFX9-NEXT: s_or_b64 exec, exec, s[8:9] ; GFX9-NEXT: s_or_b64 exec, exec, s[8:9]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
bb: bb:
%tmp = icmp ult i32 %arg, %arg1 %tmp = icmp ult i32 %arg, %arg1
br i1 %tmp, label %bb19, label %.loopexit br i1 %tmp, label %bb19, label %.loopexit
bb19: ; preds = %bb bb19: ; preds = %bb
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llvm/test/CodeGen/AMDGPU/mul_int24.ll

Show First 20 Lines • Show All 702 Lines • ▼ Show 20 Lines
} }
define amdgpu_kernel void @simplify_i24_crash(<2 x i32> addrspace(1)* %out, i32 %arg0, <2 x i32> %arg1, <2 x i32> %arg2) { define amdgpu_kernel void @simplify_i24_crash(<2 x i32> addrspace(1)* %out, i32 %arg0, <2 x i32> %arg1, <2 x i32> %arg2) {
; SI-LABEL: simplify_i24_crash: ; SI-LABEL: simplify_i24_crash:
; SI: ; %bb.0: ; %bb ; SI: ; %bb.0: ; %bb
; SI-NEXT: s_load_dword s2, s[0:1], 0xb ; SI-NEXT: s_load_dword s2, s[0:1], 0xb
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_cmp_lg_u32 s2, 0 ; SI-NEXT: s_cmp_lg_u32 s2, 0
; SI-NEXT: s_cbranch_scc0 BB8_2 ; SI-NEXT: s_cbranch_scc0 .LBB8_2
; SI-NEXT: ; %bb.1: ; %bb7 ; SI-NEXT: ; %bb.1: ; %bb7
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; SI-NEXT: BB8_2: ; %bb11 ; SI-NEXT: .LBB8_2: ; %bb11
; SI-NEXT: s_load_dword s2, s[0:1], 0xd ; SI-NEXT: s_load_dword s2, s[0:1], 0xd
; SI-NEXT: s_load_dword s4, s[0:1], 0xf ; SI-NEXT: s_load_dword s4, s[0:1], 0xf
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_bfe_i32 s2, s2, 0x180000 ; SI-NEXT: s_bfe_i32 s2, s2, 0x180000
; SI-NEXT: s_bfe_i32 s4, s4, 0x180000 ; SI-NEXT: s_bfe_i32 s4, s4, 0x180000
; SI-NEXT: s_mul_i32 s4, s2, s4 ; SI-NEXT: s_mul_i32 s4, s2, s4
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: v_mov_b32_e32 v0, s4 ; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s4 ; SI-NEXT: v_mov_b32_e32 v1, s4
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: simplify_i24_crash: ; VI-LABEL: simplify_i24_crash:
; VI: ; %bb.0: ; %bb ; VI: ; %bb.0: ; %bb
; VI-NEXT: s_load_dword s2, s[0:1], 0x2c ; VI-NEXT: s_load_dword s2, s[0:1], 0x2c
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_cmp_lg_u32 s2, 0 ; VI-NEXT: s_cmp_lg_u32 s2, 0
; VI-NEXT: s_cbranch_scc0 BB8_2 ; VI-NEXT: s_cbranch_scc0 .LBB8_2
; VI-NEXT: ; %bb.1: ; %bb7 ; VI-NEXT: ; %bb.1: ; %bb7
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; VI-NEXT: BB8_2: ; %bb11 ; VI-NEXT: .LBB8_2: ; %bb11
; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; VI-NEXT: s_load_dword s2, s[0:1], 0x34 ; VI-NEXT: s_load_dword s2, s[0:1], 0x34
; VI-NEXT: s_load_dword s0, s[0:1], 0x3c ; VI-NEXT: s_load_dword s0, s[0:1], 0x3c
; VI-NEXT: s_mov_b32 s7, 0xf000 ; VI-NEXT: s_mov_b32 s7, 0xf000
; VI-NEXT: s_mov_b32 s6, -1 ; VI-NEXT: s_mov_b32 s6, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_bfe_i32 s1, s2, 0x180000 ; VI-NEXT: s_bfe_i32 s1, s2, 0x180000
; VI-NEXT: s_bfe_i32 s0, s0, 0x180000 ; VI-NEXT: s_bfe_i32 s0, s0, 0x180000
; VI-NEXT: s_mul_i32 s1, s1, s0 ; VI-NEXT: s_mul_i32 s1, s1, s0
; VI-NEXT: v_mov_b32_e32 v0, s1 ; VI-NEXT: v_mov_b32_e32 v0, s1
; VI-NEXT: v_mov_b32_e32 v1, s1 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: simplify_i24_crash: ; GFX9-LABEL: simplify_i24_crash:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_load_dword s2, s[0:1], 0x2c ; GFX9-NEXT: s_load_dword s2, s[0:1], 0x2c
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_cmp_lg_u32 s2, 0 ; GFX9-NEXT: s_cmp_lg_u32 s2, 0
; GFX9-NEXT: s_cbranch_scc0 BB8_2 ; GFX9-NEXT: s_cbranch_scc0 .LBB8_2
; GFX9-NEXT: ; %bb.1: ; %bb7 ; GFX9-NEXT: ; %bb.1: ; %bb7
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; GFX9-NEXT: BB8_2: ; %bb11 ; GFX9-NEXT: .LBB8_2: ; %bb11
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; GFX9-NEXT: s_load_dword s2, s[0:1], 0x34 ; GFX9-NEXT: s_load_dword s2, s[0:1], 0x34
; GFX9-NEXT: s_load_dword s3, s[0:1], 0x3c ; GFX9-NEXT: s_load_dword s3, s[0:1], 0x3c
; GFX9-NEXT: s_mov_b32 s7, 0xf000 ; GFX9-NEXT: s_mov_b32 s7, 0xf000
; GFX9-NEXT: s_mov_b32 s6, -1 ; GFX9-NEXT: s_mov_b32 s6, -1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_bfe_i32 s0, s2, 0x180000 ; GFX9-NEXT: s_bfe_i32 s0, s2, 0x180000
; GFX9-NEXT: s_bfe_i32 s1, s3, 0x180000 ; GFX9-NEXT: s_bfe_i32 s1, s3, 0x180000
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llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll

Show First 20 Lines • Show All 356 Lines • ▼ Show 20 Linesexit1: ; preds = %LeafBlock, %LeafBlock1
store i32 17, i32 addrspace(3)* undef store i32 17, i32 addrspace(3)* undef
ret float 2.0 ret float 2.0
} }
; IR-LABEL: @uniform_branch_to_multi_divergent_region_exit_ret_ret_return_value( ; IR-LABEL: @uniform_branch_to_multi_divergent_region_exit_ret_ret_return_value(
; GCN-LABEL: {{^}}uniform_branch_to_multi_divergent_region_exit_ret_ret_return_value: ; GCN-LABEL: {{^}}uniform_branch_to_multi_divergent_region_exit_ret_ret_return_value:
; GCN: s_cmp_gt_i32 s0, 1 ; GCN: s_cmp_gt_i32 s0, 1
; GCN: s_cbranch_scc0 [[FLOW:BB[0-9]+_[0-9]+]] ; GCN: s_cbranch_scc0 [[FLOW:.LBB[0-9]+_[0-9]+]]
; GCN: v_cmp_ne_u32_e32 vcc, 7, v0 ; GCN: v_cmp_ne_u32_e32 vcc, 7, v0
; GCN: {{^}}[[FLOW]]: ; GCN: {{^}}[[FLOW]]:
; GCN: s_or_b64 exec, exec ; GCN: s_or_b64 exec, exec
; GCN: v_mov_b32_e32 v0, 2.0 ; GCN: v_mov_b32_e32 v0, 2.0
; GCN-NOT: s_and_b64 exec, exec ; GCN-NOT: s_and_b64 exec, exec
; GCN: v_mov_b32_e32 v0, 1.0 ; GCN: v_mov_b32_e32 v0, 1.0
; GCN: {{^BB[0-9]+_[0-9]+}}: ; %UnifiedReturnBlock ; GCN: {{^.LBB[0-9]+_[0-9]+}}: ; %UnifiedReturnBlock
; GCN-NEXT: s_or_b64 exec, exec ; GCN-NEXT: s_or_b64 exec, exec
; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN-NEXT: ; return ; GCN-NEXT: ; return
define amdgpu_ps float @uniform_branch_to_multi_divergent_region_exit_ret_ret_return_value(i32 inreg %sgpr, i32 %vgpr) #0 { define amdgpu_ps float @uniform_branch_to_multi_divergent_region_exit_ret_ret_return_value(i32 inreg %sgpr, i32 %vgpr) #0 {
entry: entry:
%uniform.cond = icmp slt i32 %sgpr, 2 %uniform.cond = icmp slt i32 %sgpr, 2
br i1 %uniform.cond, label %LeafBlock, label %LeafBlock1 br i1 %uniform.cond, label %LeafBlock, label %LeafBlock1
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llvm/test/CodeGen/AMDGPU/multilevel-break.ll

Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; OPT-NEXT: [[TMP51]] = icmp eq i32 [[TMP47]], [[CONT:%.*]] ; OPT-NEXT: [[TMP51]] = icmp eq i32 [[TMP47]], [[CONT:%.*]]
; OPT-NEXT: [[TMP51_INV]] = xor i1 [[TMP51]], true ; OPT-NEXT: [[TMP51_INV]] = xor i1 [[TMP51]], true
; OPT-NEXT: br label [[FLOW]] ; OPT-NEXT: br label [[FLOW]]
; ;
; GCN-LABEL: multi_else_break: ; GCN-LABEL: multi_else_break:
; GCN: ; %bb.0: ; %main_body ; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_mov_b64 s[0:1], 0 ; GCN-NEXT: s_mov_b64 s[0:1], 0
; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: s_branch BB0_2 ; GCN-NEXT: s_branch .LBB0_2
; GCN-NEXT: BB0_1: ; %loop.exit.guard ; GCN-NEXT: .LBB0_1: ; %loop.exit.guard
; GCN-NEXT: ; in Loop: Header=BB0_2 Depth=1 ; GCN-NEXT: ; in Loop: Header=BB0_2 Depth=1
; GCN-NEXT: s_or_b64 exec, exec, s[4:5] ; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_and_b64 s[2:3], exec, s[2:3] ; GCN-NEXT: s_and_b64 s[2:3], exec, s[2:3]
; GCN-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1] ; GCN-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
; GCN-NEXT: s_andn2_b64 exec, exec, s[0:1] ; GCN-NEXT: s_andn2_b64 exec, exec, s[0:1]
; GCN-NEXT: s_cbranch_execz BB0_6 ; GCN-NEXT: s_cbranch_execz .LBB0_6
; GCN-NEXT: BB0_2: ; %LOOP.outer ; GCN-NEXT: .LBB0_2: ; %LOOP.outer
; GCN-NEXT: ; =>This Loop Header: Depth=1 ; GCN-NEXT: ; =>This Loop Header: Depth=1
; GCN-NEXT: ; Child Loop BB0_4 Depth 2 ; GCN-NEXT: ; Child Loop BB0_4 Depth 2
; GCN-NEXT: ; implicit-def: $sgpr6_sgpr7 ; GCN-NEXT: ; implicit-def: $sgpr6_sgpr7
; GCN-NEXT: ; implicit-def: $sgpr2_sgpr3 ; GCN-NEXT: ; implicit-def: $sgpr2_sgpr3
; GCN-NEXT: s_mov_b64 s[4:5], 0 ; GCN-NEXT: s_mov_b64 s[4:5], 0
; GCN-NEXT: s_branch BB0_4 ; GCN-NEXT: s_branch .LBB0_4
; GCN-NEXT: BB0_3: ; %Flow ; GCN-NEXT: .LBB0_3: ; %Flow
; GCN-NEXT: ; in Loop: Header=BB0_4 Depth=2 ; GCN-NEXT: ; in Loop: Header=BB0_4 Depth=2
; GCN-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-NEXT: s_and_b64 s[8:9], exec, s[6:7] ; GCN-NEXT: s_and_b64 s[8:9], exec, s[6:7]
; GCN-NEXT: s_or_b64 s[4:5], s[8:9], s[4:5] ; GCN-NEXT: s_or_b64 s[4:5], s[8:9], s[4:5]
; GCN-NEXT: s_andn2_b64 exec, exec, s[4:5] ; GCN-NEXT: s_andn2_b64 exec, exec, s[4:5]
; GCN-NEXT: s_cbranch_execz BB0_1 ; GCN-NEXT: s_cbranch_execz .LBB0_1
; GCN-NEXT: BB0_4: ; %LOOP ; GCN-NEXT: .LBB0_4: ; %LOOP
; GCN-NEXT: ; Parent Loop BB0_2 Depth=1 ; GCN-NEXT: ; Parent Loop BB0_2 Depth=1
; GCN-NEXT: ; => This Inner Loop Header: Depth=2 ; GCN-NEXT: ; => This Inner Loop Header: Depth=2
; GCN-NEXT: v_cmp_lt_i32_e32 vcc, v0, v4 ; GCN-NEXT: v_cmp_lt_i32_e32 vcc, v0, v4
; GCN-NEXT: s_or_b64 s[2:3], s[2:3], exec ; GCN-NEXT: s_or_b64 s[2:3], s[2:3], exec
; GCN-NEXT: s_or_b64 s[6:7], s[6:7], exec ; GCN-NEXT: s_or_b64 s[6:7], s[6:7], exec
; GCN-NEXT: s_and_saveexec_b64 s[8:9], vcc ; GCN-NEXT: s_and_saveexec_b64 s[8:9], vcc
; GCN-NEXT: s_cbranch_execz BB0_3 ; GCN-NEXT: s_cbranch_execz .LBB0_3
; GCN-NEXT: ; %bb.5: ; %ENDIF ; GCN-NEXT: ; %bb.5: ; %ENDIF
; GCN-NEXT: ; in Loop: Header=BB0_4 Depth=2 ; GCN-NEXT: ; in Loop: Header=BB0_4 Depth=2
; GCN-NEXT: v_add_i32_e32 v0, vcc, 1, v0 ; GCN-NEXT: v_add_i32_e32 v0, vcc, 1, v0
; GCN-NEXT: s_andn2_b64 s[2:3], s[2:3], exec ; GCN-NEXT: s_andn2_b64 s[2:3], s[2:3], exec
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, v5, v0 ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, v5, v0
; GCN-NEXT: s_andn2_b64 s[6:7], s[6:7], exec ; GCN-NEXT: s_andn2_b64 s[6:7], s[6:7], exec
; GCN-NEXT: s_and_b64 s[10:11], vcc, exec ; GCN-NEXT: s_and_b64 s[10:11], vcc, exec
; GCN-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11] ; GCN-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
; GCN-NEXT: s_branch BB0_3 ; GCN-NEXT: s_branch .LBB0_3
; GCN-NEXT: BB0_6: ; %IF ; GCN-NEXT: .LBB0_6: ; %IF
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
main_body: main_body:
br label %LOOP.outer br label %LOOP.outer
LOOP.outer: ; preds = %ENDIF, %main_body LOOP.outer: ; preds = %ENDIF, %main_body
%tmp43 = phi i32 [ 0, %main_body ], [ %tmp47, %ENDIF ] %tmp43 = phi i32 [ 0, %main_body ], [ %tmp47, %ENDIF ]
br label %LOOP br label %LOOP
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; GCN: ; %bb.0: ; %bb ; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_load_dword s2, s[0:1], 0x9 ; GCN-NEXT: s_load_dword s2, s[0:1], 0x9
; GCN-NEXT: s_mov_b64 s[0:1], 0 ; GCN-NEXT: s_mov_b64 s[0:1], 0
; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0 ; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0
; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: ; implicit-def: $sgpr4_sgpr5 ; GCN-NEXT: ; implicit-def: $sgpr4_sgpr5
; GCN-NEXT: s_branch BB1_2 ; GCN-NEXT: s_branch .LBB1_2
; GCN-NEXT: BB1_1: ; %Flow4 ; GCN-NEXT: .LBB1_1: ; %Flow4
; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1 ; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
; GCN-NEXT: s_and_b64 s[6:7], exec, s[6:7] ; GCN-NEXT: s_and_b64 s[6:7], exec, s[6:7]
; GCN-NEXT: s_or_b64 s[0:1], s[6:7], s[0:1] ; GCN-NEXT: s_or_b64 s[0:1], s[6:7], s[0:1]
; GCN-NEXT: s_andn2_b64 s[4:5], s[4:5], exec ; GCN-NEXT: s_andn2_b64 s[4:5], s[4:5], exec
; GCN-NEXT: s_and_b64 s[6:7], s[8:9], exec ; GCN-NEXT: s_and_b64 s[6:7], s[8:9], exec
; GCN-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] ; GCN-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
; GCN-NEXT: s_andn2_b64 exec, exec, s[0:1] ; GCN-NEXT: s_andn2_b64 exec, exec, s[0:1]
; GCN-NEXT: s_cbranch_execz BB1_9 ; GCN-NEXT: s_cbranch_execz .LBB1_9
; GCN-NEXT: BB1_2: ; %bb1 ; GCN-NEXT: .LBB1_2: ; %bb1
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc ; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cmp_gt_i32_e32 vcc, 1, v1 ; GCN-NEXT: v_cmp_gt_i32_e32 vcc, 1, v1
; GCN-NEXT: s_mov_b64 s[6:7], -1 ; GCN-NEXT: s_mov_b64 s[6:7], -1
; GCN-NEXT: s_and_b64 vcc, exec, vcc ; GCN-NEXT: s_and_b64 vcc, exec, vcc
; GCN-NEXT: ; implicit-def: $sgpr8_sgpr9 ; GCN-NEXT: ; implicit-def: $sgpr8_sgpr9
; GCN-NEXT: s_mov_b64 s[10:11], -1 ; GCN-NEXT: s_mov_b64 s[10:11], -1
; GCN-NEXT: s_cbranch_vccnz BB1_6 ; GCN-NEXT: s_cbranch_vccnz .LBB1_6
; GCN-NEXT: ; %bb.3: ; %LeafBlock1 ; GCN-NEXT: ; %bb.3: ; %LeafBlock1
; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1 ; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
; GCN-NEXT: s_mov_b64 s[6:7], -1 ; GCN-NEXT: s_mov_b64 s[6:7], -1
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
; GCN-NEXT: s_and_b64 vcc, exec, vcc ; GCN-NEXT: s_and_b64 vcc, exec, vcc
; GCN-NEXT: s_mov_b64 s[8:9], -1 ; GCN-NEXT: s_mov_b64 s[8:9], -1
; GCN-NEXT: s_cbranch_vccz BB1_5 ; GCN-NEXT: s_cbranch_vccz .LBB1_5
; GCN-NEXT: ; %bb.4: ; %case1 ; GCN-NEXT: ; %bb.4: ; %case1
; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1 ; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
; GCN-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc ; GCN-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cmp_ge_i32_e32 vcc, v0, v2 ; GCN-NEXT: v_cmp_ge_i32_e32 vcc, v0, v2
; GCN-NEXT: s_mov_b64 s[8:9], 0 ; GCN-NEXT: s_mov_b64 s[8:9], 0
; GCN-NEXT: s_orn2_b64 s[6:7], vcc, exec ; GCN-NEXT: s_orn2_b64 s[6:7], vcc, exec
; GCN-NEXT: BB1_5: ; %Flow3 ; GCN-NEXT: .LBB1_5: ; %Flow3
; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1 ; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
; GCN-NEXT: s_mov_b64 s[10:11], 0 ; GCN-NEXT: s_mov_b64 s[10:11], 0
; GCN-NEXT: BB1_6: ; %Flow ; GCN-NEXT: .LBB1_6: ; %Flow
; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1 ; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
; GCN-NEXT: s_and_b64 vcc, exec, s[10:11] ; GCN-NEXT: s_and_b64 vcc, exec, s[10:11]
; GCN-NEXT: s_cbranch_vccz BB1_1 ; GCN-NEXT: s_cbranch_vccz .LBB1_1
; GCN-NEXT: ; %bb.7: ; %LeafBlock ; GCN-NEXT: ; %bb.7: ; %LeafBlock
; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1 ; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; GCN-NEXT: s_and_b64 vcc, exec, vcc ; GCN-NEXT: s_and_b64 vcc, exec, vcc
; GCN-NEXT: s_mov_b64 s[8:9], -1 ; GCN-NEXT: s_mov_b64 s[8:9], -1
; GCN-NEXT: s_cbranch_vccz BB1_1 ; GCN-NEXT: s_cbranch_vccz .LBB1_1
; GCN-NEXT: ; %bb.8: ; %case0 ; GCN-NEXT: ; %bb.8: ; %case0
; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1 ; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc ; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_mov_b64 s[8:9], 0 ; GCN-NEXT: s_mov_b64 s[8:9], 0
; GCN-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1 ; GCN-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1
; GCN-NEXT: s_andn2_b64 s[6:7], s[6:7], exec ; GCN-NEXT: s_andn2_b64 s[6:7], s[6:7], exec
; GCN-NEXT: s_and_b64 s[10:11], vcc, exec ; GCN-NEXT: s_and_b64 s[10:11], vcc, exec
; GCN-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11] ; GCN-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
; GCN-NEXT: s_branch BB1_1 ; GCN-NEXT: s_branch .LBB1_1
; GCN-NEXT: BB1_9: ; %loop.exit.guard ; GCN-NEXT: .LBB1_9: ; %loop.exit.guard
; GCN-NEXT: s_or_b64 exec, exec, s[0:1] ; GCN-NEXT: s_or_b64 exec, exec, s[0:1]
; GCN-NEXT: s_and_saveexec_b64 s[0:1], s[4:5] ; GCN-NEXT: s_and_saveexec_b64 s[0:1], s[4:5]
; GCN-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GCN-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
bb: bb:
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%tmp = sub i32 %id, %arg %tmp = sub i32 %id, %arg
br label %bb1 br label %bb1
Show All 29 Lines

llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll

Show All 13 Lines
; GCN-NEXT: s_load_dword s0, s[0:1], 0x9 ; GCN-NEXT: s_load_dword s0, s[0:1], 0x9
; GCN-NEXT: v_lshlrev_b32_e32 v0, 3, v0 ; GCN-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; GCN-NEXT: s_mov_b32 m0, -1 ; GCN-NEXT: s_mov_b32 m0, -1
; GCN-NEXT: s_mov_b64 s[2:3], -1 ; GCN-NEXT: s_mov_b64 s[2:3], -1
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_add_i32_e32 v0, vcc, s0, v0 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; GCN-NEXT: ds_read_b64 v[0:1], v0 ; GCN-NEXT: ds_read_b64 v[0:1], v0
; GCN-NEXT: s_and_b64 s[0:1], exec, -1 ; GCN-NEXT: s_and_b64 s[0:1], exec, -1
; GCN-NEXT: s_branch BB0_2 ; GCN-NEXT: s_branch .LBB0_2
; GCN-NEXT: BB0_1: ; %bb10 ; GCN-NEXT: .LBB0_1: ; %bb10
; GCN-NEXT: ; in Loop: Header=BB0_2 Depth=1 ; GCN-NEXT: ; in Loop: Header=BB0_2 Depth=1
; GCN-NEXT: s_mov_b64 s[4:5], 0 ; GCN-NEXT: s_mov_b64 s[4:5], 0
; GCN-NEXT: s_andn2_b64 vcc, exec, s[2:3] ; GCN-NEXT: s_andn2_b64 vcc, exec, s[2:3]
; GCN-NEXT: s_cbranch_vccz BB0_4 ; GCN-NEXT: s_cbranch_vccz .LBB0_4
; GCN-NEXT: BB0_2: ; %bb5 ; GCN-NEXT: .LBB0_2: ; %bb5
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: s_mov_b64 vcc, s[0:1] ; GCN-NEXT: s_mov_b64 vcc, s[0:1]
; GCN-NEXT: s_cbranch_vccnz BB0_1 ; GCN-NEXT: s_cbranch_vccnz .LBB0_1
; GCN-NEXT: ; %bb.3: ; in Loop: Header=BB0_2 Depth=1 ; GCN-NEXT: ; %bb.3: ; in Loop: Header=BB0_2 Depth=1
; GCN-NEXT: s_mov_b64 s[4:5], -1 ; GCN-NEXT: s_mov_b64 s[4:5], -1
; GCN-NEXT: s_andn2_b64 vcc, exec, s[2:3] ; GCN-NEXT: s_andn2_b64 vcc, exec, s[2:3]
; GCN-NEXT: s_cbranch_vccnz BB0_2 ; GCN-NEXT: s_cbranch_vccnz .LBB0_2
; GCN-NEXT: BB0_4: ; %loop.exit.guard ; GCN-NEXT: .LBB0_4: ; %loop.exit.guard
; GCN-NEXT: s_and_b64 vcc, exec, s[4:5] ; GCN-NEXT: s_and_b64 vcc, exec, s[4:5]
; GCN-NEXT: s_cbranch_vccz BB0_7 ; GCN-NEXT: s_cbranch_vccz .LBB0_7
; GCN-NEXT: ; %bb.5: ; %bb8 ; GCN-NEXT: ; %bb.5: ; %bb8
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: ds_read_b32 v0, v0 ; GCN-NEXT: ds_read_b32 v0, v0
; GCN-NEXT: s_and_b64 vcc, exec, 0 ; GCN-NEXT: s_and_b64 vcc, exec, 0
; GCN-NEXT: BB0_6: ; %bb9 ; GCN-NEXT: .LBB0_6: ; %bb9
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: s_mov_b64 vcc, vcc ; GCN-NEXT: s_mov_b64 vcc, vcc
; GCN-NEXT: s_cbranch_vccz BB0_6 ; GCN-NEXT: s_cbranch_vccz .LBB0_6
; GCN-NEXT: BB0_7: ; %DummyReturnBlock ; GCN-NEXT: .LBB0_7: ; %DummyReturnBlock
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; IR-LABEL: @reduced_nested_loop_conditions( ; IR-LABEL: @reduced_nested_loop_conditions(
; IR-NEXT: bb: ; IR-NEXT: bb:
; IR-NEXT: [[MY_TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x() #4 ; IR-NEXT: [[MY_TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x() #4
; IR-NEXT: [[MY_TMP1:%.*]] = getelementptr inbounds i64, i64 addrspace(3)* [[ARG:%.*]], i32 [[MY_TMP]] ; IR-NEXT: [[MY_TMP1:%.*]] = getelementptr inbounds i64, i64 addrspace(3)* [[ARG:%.*]], i32 [[MY_TMP]]
; IR-NEXT: [[MY_TMP2:%.*]] = load volatile i64, i64 addrspace(3)* [[MY_TMP1]] ; IR-NEXT: [[MY_TMP2:%.*]] = load volatile i64, i64 addrspace(3)* [[MY_TMP1]]
; IR-NEXT: br label [[BB5:%.*]] ; IR-NEXT: br label [[BB5:%.*]]
; IR: bb3: ; IR: bb3:
▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Lines
; GCN-LABEL: nested_loop_conditions: ; GCN-LABEL: nested_loop_conditions:
; GCN: ; %bb.0: ; %bb ; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: buffer_load_dword v0, off, s[0:3], 0 ; GCN-NEXT: buffer_load_dword v0, off, s[0:3], 0
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cmp_lt_i32_e32 vcc, 8, v0 ; GCN-NEXT: v_cmp_lt_i32_e32 vcc, 8, v0
; GCN-NEXT: s_and_b64 vcc, exec, vcc ; GCN-NEXT: s_and_b64 vcc, exec, vcc
; GCN-NEXT: s_cbranch_vccnz BB1_6 ; GCN-NEXT: s_cbranch_vccnz .LBB1_6
; GCN-NEXT: ; %bb.1: ; %bb14.lr.ph ; GCN-NEXT: ; %bb.1: ; %bb14.lr.ph
; GCN-NEXT: buffer_load_dword v0, off, s[0:3], 0 ; GCN-NEXT: buffer_load_dword v0, off, s[0:3], 0
; GCN-NEXT: s_branch BB1_3 ; GCN-NEXT: s_branch .LBB1_3
; GCN-NEXT: BB1_2: ; in Loop: Header=BB1_3 Depth=1 ; GCN-NEXT: .LBB1_2: ; in Loop: Header=BB1_3 Depth=1
; GCN-NEXT: s_mov_b64 s[0:1], -1 ; GCN-NEXT: s_mov_b64 s[0:1], -1
; GCN-NEXT: ; implicit-def: $vgpr0 ; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: s_cbranch_execnz BB1_6 ; GCN-NEXT: s_cbranch_execnz .LBB1_6
; GCN-NEXT: BB1_3: ; %bb14 ; GCN-NEXT: .LBB1_3: ; %bb14
; GCN-NEXT: ; =>This Loop Header: Depth=1 ; GCN-NEXT: ; =>This Loop Header: Depth=1
; GCN-NEXT: ; Child Loop BB1_4 Depth 2 ; GCN-NEXT: ; Child Loop BB1_4 Depth 2
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 1, v0 ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 1, v0
; GCN-NEXT: s_and_b64 vcc, exec, vcc ; GCN-NEXT: s_and_b64 vcc, exec, vcc
; GCN-NEXT: s_cbranch_vccnz BB1_2 ; GCN-NEXT: s_cbranch_vccnz .LBB1_2
; GCN-NEXT: BB1_4: ; %bb18 ; GCN-NEXT: .LBB1_4: ; %bb18
; GCN-NEXT: ; Parent Loop BB1_3 Depth=1 ; GCN-NEXT: ; Parent Loop BB1_3 Depth=1
; GCN-NEXT: ; => This Inner Loop Header: Depth=2 ; GCN-NEXT: ; => This Inner Loop Header: Depth=2
; GCN-NEXT: buffer_load_dword v0, off, s[0:3], 0 ; GCN-NEXT: buffer_load_dword v0, off, s[0:3], 0
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cmp_lt_i32_e32 vcc, 8, v0 ; GCN-NEXT: v_cmp_lt_i32_e32 vcc, 8, v0
; GCN-NEXT: s_and_b64 vcc, exec, vcc ; GCN-NEXT: s_and_b64 vcc, exec, vcc
; GCN-NEXT: s_cbranch_vccnz BB1_4 ; GCN-NEXT: s_cbranch_vccnz .LBB1_4
; GCN-NEXT: ; %bb.5: ; %bb21 ; GCN-NEXT: ; %bb.5: ; %bb21
; GCN-NEXT: ; in Loop: Header=BB1_3 Depth=1 ; GCN-NEXT: ; in Loop: Header=BB1_3 Depth=1
; GCN-NEXT: buffer_load_dword v0, off, s[0:3], 0 ; GCN-NEXT: buffer_load_dword v0, off, s[0:3], 0
; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0 ; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cmp_lt_i32_e64 s[0:1], 8, v1 ; GCN-NEXT: v_cmp_lt_i32_e64 s[0:1], 8, v1
; GCN-NEXT: s_and_b64 vcc, exec, s[0:1] ; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: s_cbranch_vccz BB1_3 ; GCN-NEXT: s_cbranch_vccz .LBB1_3
; GCN-NEXT: BB1_6: ; %bb31 ; GCN-NEXT: .LBB1_6: ; %bb31
; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; IR-LABEL: @nested_loop_conditions( ; IR-LABEL: @nested_loop_conditions(
; IR-NEXT: bb: ; IR-NEXT: bb:
; IR-NEXT: [[MY_TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x() #4 ; IR-NEXT: [[MY_TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x() #4
; IR-NEXT: [[MY_TMP1:%.*]] = zext i32 [[MY_TMP]] to i64 ; IR-NEXT: [[MY_TMP1:%.*]] = zext i32 [[MY_TMP]] to i64
▲ Show 20 Lines • Show All 150 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll

Show All 16 Lines
; MUBUF: ; %bb.0: ; %entry ; MUBUF: ; %bb.0: ; %entry
; MUBUF-NEXT: s_add_u32 s0, s0, s9 ; MUBUF-NEXT: s_add_u32 s0, s0, s9
; MUBUF-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x8 ; MUBUF-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x8
; MUBUF-NEXT: s_addc_u32 s1, s1, 0 ; MUBUF-NEXT: s_addc_u32 s1, s1, 0
; MUBUF-NEXT: s_movk_i32 s32, 0x400 ; MUBUF-NEXT: s_movk_i32 s32, 0x400
; MUBUF-NEXT: s_mov_b32 s33, 0 ; MUBUF-NEXT: s_mov_b32 s33, 0
; MUBUF-NEXT: s_waitcnt lgkmcnt(0) ; MUBUF-NEXT: s_waitcnt lgkmcnt(0)
; MUBUF-NEXT: s_cmp_lg_u32 s8, 0 ; MUBUF-NEXT: s_cmp_lg_u32 s8, 0
; MUBUF-NEXT: s_cbranch_scc1 BB0_3 ; MUBUF-NEXT: s_cbranch_scc1 .LBB0_3
; MUBUF-NEXT: ; %bb.1: ; %bb.0 ; MUBUF-NEXT: ; %bb.1: ; %bb.0
; MUBUF-NEXT: s_cmp_lg_u32 s9, 0 ; MUBUF-NEXT: s_cmp_lg_u32 s9, 0
; MUBUF-NEXT: s_cbranch_scc1 BB0_3 ; MUBUF-NEXT: s_cbranch_scc1 .LBB0_3
; MUBUF-NEXT: ; %bb.2: ; %bb.1 ; MUBUF-NEXT: ; %bb.2: ; %bb.1
; MUBUF-NEXT: s_add_i32 s6, s32, 0x1000 ; MUBUF-NEXT: s_add_i32 s6, s32, 0x1000
; MUBUF-NEXT: s_lshl_b32 s7, s10, 2 ; MUBUF-NEXT: s_lshl_b32 s7, s10, 2
; MUBUF-NEXT: s_mov_b32 s32, s6 ; MUBUF-NEXT: s_mov_b32 s32, s6
; MUBUF-NEXT: v_mov_b32_e32 v1, 0 ; MUBUF-NEXT: v_mov_b32_e32 v1, 0
; MUBUF-NEXT: v_mov_b32_e32 v2, s6 ; MUBUF-NEXT: v_mov_b32_e32 v2, s6
; MUBUF-NEXT: v_mov_b32_e32 v3, 1 ; MUBUF-NEXT: v_mov_b32_e32 v3, 1
; MUBUF-NEXT: s_add_i32 s6, s6, s7 ; MUBUF-NEXT: s_add_i32 s6, s6, s7
; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; MUBUF-NEXT: buffer_store_dword v3, v2, s[0:3], 0 offen offset:4 ; MUBUF-NEXT: buffer_store_dword v3, v2, s[0:3], 0 offen offset:4
; MUBUF-NEXT: v_mov_b32_e32 v2, s6 ; MUBUF-NEXT: v_mov_b32_e32 v2, s6
; MUBUF-NEXT: buffer_load_dword v2, v2, s[0:3], 0 offen ; MUBUF-NEXT: buffer_load_dword v2, v2, s[0:3], 0 offen
; MUBUF-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 ; MUBUF-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: v_add_u32_e32 v0, v2, v0 ; MUBUF-NEXT: v_add_u32_e32 v0, v2, v0
; MUBUF-NEXT: s_waitcnt lgkmcnt(0) ; MUBUF-NEXT: s_waitcnt lgkmcnt(0)
; MUBUF-NEXT: global_store_dword v1, v0, s[4:5] ; MUBUF-NEXT: global_store_dword v1, v0, s[4:5]
; MUBUF-NEXT: BB0_3: ; %bb.2 ; MUBUF-NEXT: .LBB0_3: ; %bb.2
; MUBUF-NEXT: v_mov_b32_e32 v0, 0 ; MUBUF-NEXT: v_mov_b32_e32 v0, 0
; MUBUF-NEXT: global_store_dword v[0:1], v0, off ; MUBUF-NEXT: global_store_dword v[0:1], v0, off
; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: s_endpgm ; MUBUF-NEXT: s_endpgm
; ;
; FLATSCR-LABEL: kernel_non_entry_block_static_alloca_uniformly_reached_align4: ; FLATSCR-LABEL: kernel_non_entry_block_static_alloca_uniformly_reached_align4:
; FLATSCR: ; %bb.0: ; %entry ; FLATSCR: ; %bb.0: ; %entry
; FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s2, s5 ; FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s2, s5
; FLATSCR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8 ; FLATSCR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s3, 0 ; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
; FLATSCR-NEXT: s_mov_b32 s32, 16 ; FLATSCR-NEXT: s_mov_b32 s32, 16
; FLATSCR-NEXT: s_mov_b32 s33, 0 ; FLATSCR-NEXT: s_mov_b32 s33, 0
; FLATSCR-NEXT: s_waitcnt lgkmcnt(0) ; FLATSCR-NEXT: s_waitcnt lgkmcnt(0)
; FLATSCR-NEXT: s_cmp_lg_u32 s4, 0 ; FLATSCR-NEXT: s_cmp_lg_u32 s4, 0
; FLATSCR-NEXT: s_cbranch_scc1 BB0_3 ; FLATSCR-NEXT: s_cbranch_scc1 .LBB0_3
; FLATSCR-NEXT: ; %bb.1: ; %bb.0 ; FLATSCR-NEXT: ; %bb.1: ; %bb.0
; FLATSCR-NEXT: s_cmp_lg_u32 s5, 0 ; FLATSCR-NEXT: s_cmp_lg_u32 s5, 0
; FLATSCR-NEXT: s_cbranch_scc1 BB0_3 ; FLATSCR-NEXT: s_cbranch_scc1 .LBB0_3
; FLATSCR-NEXT: ; %bb.2: ; %bb.1 ; FLATSCR-NEXT: ; %bb.2: ; %bb.1
; FLATSCR-NEXT: v_mov_b32_e32 v1, 0 ; FLATSCR-NEXT: v_mov_b32_e32 v1, 0
; FLATSCR-NEXT: s_add_i32 s2, s32, 0x1000 ; FLATSCR-NEXT: s_add_i32 s2, s32, 0x1000
; FLATSCR-NEXT: v_mov_b32_e32 v2, 1 ; FLATSCR-NEXT: v_mov_b32_e32 v2, 1
; FLATSCR-NEXT: s_lshl_b32 s3, s6, 2 ; FLATSCR-NEXT: s_lshl_b32 s3, s6, 2
; FLATSCR-NEXT: s_mov_b32 s32, s2 ; FLATSCR-NEXT: s_mov_b32 s32, s2
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[1:2], s2 ; FLATSCR-NEXT: scratch_store_dwordx2 off, v[1:2], s2
; FLATSCR-NEXT: s_add_i32 s2, s2, s3 ; FLATSCR-NEXT: s_add_i32 s2, s2, s3
; FLATSCR-NEXT: scratch_load_dword v2, off, s2 ; FLATSCR-NEXT: scratch_load_dword v2, off, s2
; FLATSCR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; FLATSCR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: v_add_u32_e32 v0, v2, v0 ; FLATSCR-NEXT: v_add_u32_e32 v0, v2, v0
; FLATSCR-NEXT: s_waitcnt lgkmcnt(0) ; FLATSCR-NEXT: s_waitcnt lgkmcnt(0)
; FLATSCR-NEXT: global_store_dword v1, v0, s[0:1] ; FLATSCR-NEXT: global_store_dword v1, v0, s[0:1]
; FLATSCR-NEXT: BB0_3: ; %bb.2 ; FLATSCR-NEXT: .LBB0_3: ; %bb.2
; FLATSCR-NEXT: v_mov_b32_e32 v0, 0 ; FLATSCR-NEXT: v_mov_b32_e32 v0, 0
; FLATSCR-NEXT: global_store_dword v[0:1], v0, off ; FLATSCR-NEXT: global_store_dword v[0:1], v0, off
; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: s_endpgm ; FLATSCR-NEXT: s_endpgm
entry: entry:
%cond0 = icmp eq i32 %arg.cond0, 0 %cond0 = icmp eq i32 %arg.cond0, 0
br i1 %cond0, label %bb.0, label %bb.2 br i1 %cond0, label %bb.0, label %bb.2
Show All 31 Lines
; MUBUF: ; %bb.0: ; %entry ; MUBUF: ; %bb.0: ; %entry
; MUBUF-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x8 ; MUBUF-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x8
; MUBUF-NEXT: s_add_u32 s0, s0, s9 ; MUBUF-NEXT: s_add_u32 s0, s0, s9
; MUBUF-NEXT: s_addc_u32 s1, s1, 0 ; MUBUF-NEXT: s_addc_u32 s1, s1, 0
; MUBUF-NEXT: s_movk_i32 s32, 0x1000 ; MUBUF-NEXT: s_movk_i32 s32, 0x1000
; MUBUF-NEXT: s_mov_b32 s33, 0 ; MUBUF-NEXT: s_mov_b32 s33, 0
; MUBUF-NEXT: s_waitcnt lgkmcnt(0) ; MUBUF-NEXT: s_waitcnt lgkmcnt(0)
; MUBUF-NEXT: s_cmp_lg_u32 s6, 0 ; MUBUF-NEXT: s_cmp_lg_u32 s6, 0
; MUBUF-NEXT: s_cbranch_scc1 BB1_2 ; MUBUF-NEXT: s_cbranch_scc1 .LBB1_2
; MUBUF-NEXT: ; %bb.1: ; %bb.0 ; MUBUF-NEXT: ; %bb.1: ; %bb.0
; MUBUF-NEXT: s_add_i32 s6, s32, 0x1000 ; MUBUF-NEXT: s_add_i32 s6, s32, 0x1000
; MUBUF-NEXT: s_and_b32 s6, s6, 0xfffff000 ; MUBUF-NEXT: s_and_b32 s6, s6, 0xfffff000
; MUBUF-NEXT: s_lshl_b32 s7, s7, 2 ; MUBUF-NEXT: s_lshl_b32 s7, s7, 2
; MUBUF-NEXT: s_mov_b32 s32, s6 ; MUBUF-NEXT: s_mov_b32 s32, s6
; MUBUF-NEXT: v_mov_b32_e32 v1, 0 ; MUBUF-NEXT: v_mov_b32_e32 v1, 0
; MUBUF-NEXT: v_mov_b32_e32 v2, s6 ; MUBUF-NEXT: v_mov_b32_e32 v2, s6
; MUBUF-NEXT: v_mov_b32_e32 v3, 1 ; MUBUF-NEXT: v_mov_b32_e32 v3, 1
; MUBUF-NEXT: s_add_i32 s6, s6, s7 ; MUBUF-NEXT: s_add_i32 s6, s6, s7
; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; MUBUF-NEXT: buffer_store_dword v3, v2, s[0:3], 0 offen offset:4 ; MUBUF-NEXT: buffer_store_dword v3, v2, s[0:3], 0 offen offset:4
; MUBUF-NEXT: v_mov_b32_e32 v2, s6 ; MUBUF-NEXT: v_mov_b32_e32 v2, s6
; MUBUF-NEXT: buffer_load_dword v2, v2, s[0:3], 0 offen ; MUBUF-NEXT: buffer_load_dword v2, v2, s[0:3], 0 offen
; MUBUF-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 ; MUBUF-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: v_add_u32_e32 v0, v2, v0 ; MUBUF-NEXT: v_add_u32_e32 v0, v2, v0
; MUBUF-NEXT: s_waitcnt lgkmcnt(0) ; MUBUF-NEXT: s_waitcnt lgkmcnt(0)
; MUBUF-NEXT: global_store_dword v1, v0, s[4:5] ; MUBUF-NEXT: global_store_dword v1, v0, s[4:5]
; MUBUF-NEXT: BB1_2: ; %bb.1 ; MUBUF-NEXT: .LBB1_2: ; %bb.1
; MUBUF-NEXT: v_mov_b32_e32 v0, 0 ; MUBUF-NEXT: v_mov_b32_e32 v0, 0
; MUBUF-NEXT: global_store_dword v[0:1], v0, off ; MUBUF-NEXT: global_store_dword v[0:1], v0, off
; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: s_endpgm ; MUBUF-NEXT: s_endpgm
; ;
; FLATSCR-LABEL: kernel_non_entry_block_static_alloca_uniformly_reached_align64: ; FLATSCR-LABEL: kernel_non_entry_block_static_alloca_uniformly_reached_align64:
; FLATSCR: ; %bb.0: ; %entry ; FLATSCR: ; %bb.0: ; %entry
; FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s2, s5 ; FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s2, s5
; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s3, 0 ; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
; FLATSCR-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x8 ; FLATSCR-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x8
; FLATSCR-NEXT: s_mov_b32 s32, 64 ; FLATSCR-NEXT: s_mov_b32 s32, 64
; FLATSCR-NEXT: s_mov_b32 s33, 0 ; FLATSCR-NEXT: s_mov_b32 s33, 0
; FLATSCR-NEXT: s_waitcnt lgkmcnt(0) ; FLATSCR-NEXT: s_waitcnt lgkmcnt(0)
; FLATSCR-NEXT: s_cmp_lg_u32 s2, 0 ; FLATSCR-NEXT: s_cmp_lg_u32 s2, 0
; FLATSCR-NEXT: s_cbranch_scc1 BB1_2 ; FLATSCR-NEXT: s_cbranch_scc1 .LBB1_2
; FLATSCR-NEXT: ; %bb.1: ; %bb.0 ; FLATSCR-NEXT: ; %bb.1: ; %bb.0
; FLATSCR-NEXT: s_add_i32 s2, s32, 0x1000 ; FLATSCR-NEXT: s_add_i32 s2, s32, 0x1000
; FLATSCR-NEXT: v_mov_b32_e32 v1, 0 ; FLATSCR-NEXT: v_mov_b32_e32 v1, 0
; FLATSCR-NEXT: s_and_b32 s2, s2, 0xfffff000 ; FLATSCR-NEXT: s_and_b32 s2, s2, 0xfffff000
; FLATSCR-NEXT: v_mov_b32_e32 v2, 1 ; FLATSCR-NEXT: v_mov_b32_e32 v2, 1
; FLATSCR-NEXT: s_lshl_b32 s3, s3, 2 ; FLATSCR-NEXT: s_lshl_b32 s3, s3, 2
; FLATSCR-NEXT: s_mov_b32 s32, s2 ; FLATSCR-NEXT: s_mov_b32 s32, s2
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[1:2], s2 ; FLATSCR-NEXT: scratch_store_dwordx2 off, v[1:2], s2
; FLATSCR-NEXT: s_add_i32 s2, s2, s3 ; FLATSCR-NEXT: s_add_i32 s2, s2, s3
; FLATSCR-NEXT: scratch_load_dword v2, off, s2 ; FLATSCR-NEXT: scratch_load_dword v2, off, s2
; FLATSCR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; FLATSCR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: v_add_u32_e32 v0, v2, v0 ; FLATSCR-NEXT: v_add_u32_e32 v0, v2, v0
; FLATSCR-NEXT: s_waitcnt lgkmcnt(0) ; FLATSCR-NEXT: s_waitcnt lgkmcnt(0)
; FLATSCR-NEXT: global_store_dword v1, v0, s[0:1] ; FLATSCR-NEXT: global_store_dword v1, v0, s[0:1]
; FLATSCR-NEXT: BB1_2: ; %bb.1 ; FLATSCR-NEXT: .LBB1_2: ; %bb.1
; FLATSCR-NEXT: v_mov_b32_e32 v0, 0 ; FLATSCR-NEXT: v_mov_b32_e32 v0, 0
; FLATSCR-NEXT: global_store_dword v[0:1], v0, off ; FLATSCR-NEXT: global_store_dword v[0:1], v0, off
; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: s_endpgm ; FLATSCR-NEXT: s_endpgm
entry: entry:
%cond = icmp eq i32 %arg.cond, 0 %cond = icmp eq i32 %arg.cond, 0
br i1 %cond, label %bb.0, label %bb.1 br i1 %cond, label %bb.0, label %bb.1
Show All 26 Lines
; MUBUF-LABEL: func_non_entry_block_static_alloca_align4: ; MUBUF-LABEL: func_non_entry_block_static_alloca_align4:
; MUBUF: ; %bb.0: ; %entry ; MUBUF: ; %bb.0: ; %entry
; MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; MUBUF-NEXT: s_mov_b32 s7, s33 ; MUBUF-NEXT: s_mov_b32 s7, s33
; MUBUF-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; MUBUF-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; MUBUF-NEXT: s_mov_b32 s33, s32 ; MUBUF-NEXT: s_mov_b32 s33, s32
; MUBUF-NEXT: s_addk_i32 s32, 0x400 ; MUBUF-NEXT: s_addk_i32 s32, 0x400
; MUBUF-NEXT: s_and_saveexec_b64 s[4:5], vcc ; MUBUF-NEXT: s_and_saveexec_b64 s[4:5], vcc
; MUBUF-NEXT: s_cbranch_execz BB2_3 ; MUBUF-NEXT: s_cbranch_execz .LBB2_3
; MUBUF-NEXT: ; %bb.1: ; %bb.0 ; MUBUF-NEXT: ; %bb.1: ; %bb.0
; MUBUF-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 ; MUBUF-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; MUBUF-NEXT: s_and_b64 exec, exec, vcc ; MUBUF-NEXT: s_and_b64 exec, exec, vcc
; MUBUF-NEXT: s_cbranch_execz BB2_3 ; MUBUF-NEXT: s_cbranch_execz .LBB2_3
; MUBUF-NEXT: ; %bb.2: ; %bb.1 ; MUBUF-NEXT: ; %bb.2: ; %bb.1
; MUBUF-NEXT: s_add_i32 s6, s32, 0x1000 ; MUBUF-NEXT: s_add_i32 s6, s32, 0x1000
; MUBUF-NEXT: v_mov_b32_e32 v2, 0 ; MUBUF-NEXT: v_mov_b32_e32 v2, 0
; MUBUF-NEXT: v_mov_b32_e32 v3, s6 ; MUBUF-NEXT: v_mov_b32_e32 v3, s6
; MUBUF-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen ; MUBUF-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; MUBUF-NEXT: v_mov_b32_e32 v2, 1 ; MUBUF-NEXT: v_mov_b32_e32 v2, 1
; MUBUF-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen offset:4 ; MUBUF-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen offset:4
; MUBUF-NEXT: v_lshl_add_u32 v2, v4, 2, s6 ; MUBUF-NEXT: v_lshl_add_u32 v2, v4, 2, s6
; MUBUF-NEXT: buffer_load_dword v2, v2, s[0:3], 0 offen ; MUBUF-NEXT: buffer_load_dword v2, v2, s[0:3], 0 offen
; MUBUF-NEXT: v_and_b32_e32 v3, 0x3ff, v5 ; MUBUF-NEXT: v_and_b32_e32 v3, 0x3ff, v5
; MUBUF-NEXT: s_mov_b32 s32, s6 ; MUBUF-NEXT: s_mov_b32 s32, s6
; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: v_add_u32_e32 v2, v2, v3 ; MUBUF-NEXT: v_add_u32_e32 v2, v2, v3
; MUBUF-NEXT: global_store_dword v[0:1], v2, off ; MUBUF-NEXT: global_store_dword v[0:1], v2, off
; MUBUF-NEXT: BB2_3: ; %bb.2 ; MUBUF-NEXT: .LBB2_3: ; %bb.2
; MUBUF-NEXT: s_or_b64 exec, exec, s[4:5] ; MUBUF-NEXT: s_or_b64 exec, exec, s[4:5]
; MUBUF-NEXT: v_mov_b32_e32 v0, 0 ; MUBUF-NEXT: v_mov_b32_e32 v0, 0
; MUBUF-NEXT: global_store_dword v[0:1], v0, off ; MUBUF-NEXT: global_store_dword v[0:1], v0, off
; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: s_addk_i32 s32, 0xfc00 ; MUBUF-NEXT: s_addk_i32 s32, 0xfc00
; MUBUF-NEXT: s_mov_b32 s33, s7 ; MUBUF-NEXT: s_mov_b32 s33, s7
; MUBUF-NEXT: s_setpc_b64 s[30:31] ; MUBUF-NEXT: s_setpc_b64 s[30:31]
; ;
; FLATSCR-LABEL: func_non_entry_block_static_alloca_align4: ; FLATSCR-LABEL: func_non_entry_block_static_alloca_align4:
; FLATSCR: ; %bb.0: ; %entry ; FLATSCR: ; %bb.0: ; %entry
; FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; FLATSCR-NEXT: s_mov_b32 s3, s33 ; FLATSCR-NEXT: s_mov_b32 s3, s33
; FLATSCR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; FLATSCR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; FLATSCR-NEXT: s_mov_b32 s33, s32 ; FLATSCR-NEXT: s_mov_b32 s33, s32
; FLATSCR-NEXT: s_add_i32 s32, s32, 16 ; FLATSCR-NEXT: s_add_i32 s32, s32, 16
; FLATSCR-NEXT: s_and_saveexec_b64 s[0:1], vcc ; FLATSCR-NEXT: s_and_saveexec_b64 s[0:1], vcc
; FLATSCR-NEXT: s_cbranch_execz BB2_3 ; FLATSCR-NEXT: s_cbranch_execz .LBB2_3
; FLATSCR-NEXT: ; %bb.1: ; %bb.0 ; FLATSCR-NEXT: ; %bb.1: ; %bb.0
; FLATSCR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 ; FLATSCR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; FLATSCR-NEXT: s_and_b64 exec, exec, vcc ; FLATSCR-NEXT: s_and_b64 exec, exec, vcc
; FLATSCR-NEXT: s_cbranch_execz BB2_3 ; FLATSCR-NEXT: s_cbranch_execz .LBB2_3
; FLATSCR-NEXT: ; %bb.2: ; %bb.1 ; FLATSCR-NEXT: ; %bb.2: ; %bb.1
; FLATSCR-NEXT: s_add_i32 s2, s32, 0x1000 ; FLATSCR-NEXT: s_add_i32 s2, s32, 0x1000
; FLATSCR-NEXT: v_mov_b32_e32 v2, 0 ; FLATSCR-NEXT: v_mov_b32_e32 v2, 0
; FLATSCR-NEXT: v_mov_b32_e32 v3, 1 ; FLATSCR-NEXT: v_mov_b32_e32 v3, 1
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[2:3], s2 ; FLATSCR-NEXT: scratch_store_dwordx2 off, v[2:3], s2
; FLATSCR-NEXT: v_lshl_add_u32 v2, v4, 2, s2 ; FLATSCR-NEXT: v_lshl_add_u32 v2, v4, 2, s2
; FLATSCR-NEXT: scratch_load_dword v2, v2, off ; FLATSCR-NEXT: scratch_load_dword v2, v2, off
; FLATSCR-NEXT: v_and_b32_e32 v3, 0x3ff, v5 ; FLATSCR-NEXT: v_and_b32_e32 v3, 0x3ff, v5
; FLATSCR-NEXT: s_mov_b32 s32, s2 ; FLATSCR-NEXT: s_mov_b32 s32, s2
; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: v_add_u32_e32 v2, v2, v3 ; FLATSCR-NEXT: v_add_u32_e32 v2, v2, v3
; FLATSCR-NEXT: global_store_dword v[0:1], v2, off ; FLATSCR-NEXT: global_store_dword v[0:1], v2, off
; FLATSCR-NEXT: BB2_3: ; %bb.2 ; FLATSCR-NEXT: .LBB2_3: ; %bb.2
; FLATSCR-NEXT: s_or_b64 exec, exec, s[0:1] ; FLATSCR-NEXT: s_or_b64 exec, exec, s[0:1]
; FLATSCR-NEXT: v_mov_b32_e32 v0, 0 ; FLATSCR-NEXT: v_mov_b32_e32 v0, 0
; FLATSCR-NEXT: global_store_dword v[0:1], v0, off ; FLATSCR-NEXT: global_store_dword v[0:1], v0, off
; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: s_add_i32 s32, s32, -16 ; FLATSCR-NEXT: s_add_i32 s32, s32, -16
; FLATSCR-NEXT: s_mov_b32 s33, s3 ; FLATSCR-NEXT: s_mov_b32 s33, s3
; FLATSCR-NEXT: s_setpc_b64 s[30:31] ; FLATSCR-NEXT: s_setpc_b64 s[30:31]
Show All 29 Lines
; MUBUF: ; %bb.0: ; %entry ; MUBUF: ; %bb.0: ; %entry
; MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; MUBUF-NEXT: s_mov_b32 s7, s33 ; MUBUF-NEXT: s_mov_b32 s7, s33
; MUBUF-NEXT: s_add_i32 s33, s32, 0xfc0 ; MUBUF-NEXT: s_add_i32 s33, s32, 0xfc0
; MUBUF-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; MUBUF-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; MUBUF-NEXT: s_and_b32 s33, s33, 0xfffff000 ; MUBUF-NEXT: s_and_b32 s33, s33, 0xfffff000
; MUBUF-NEXT: s_addk_i32 s32, 0x2000 ; MUBUF-NEXT: s_addk_i32 s32, 0x2000
; MUBUF-NEXT: s_and_saveexec_b64 s[4:5], vcc ; MUBUF-NEXT: s_and_saveexec_b64 s[4:5], vcc
; MUBUF-NEXT: s_cbranch_execz BB3_2 ; MUBUF-NEXT: s_cbranch_execz .LBB3_2
; MUBUF-NEXT: ; %bb.1: ; %bb.0 ; MUBUF-NEXT: ; %bb.1: ; %bb.0
; MUBUF-NEXT: s_add_i32 s6, s32, 0x1000 ; MUBUF-NEXT: s_add_i32 s6, s32, 0x1000
; MUBUF-NEXT: s_and_b32 s6, s6, 0xfffff000 ; MUBUF-NEXT: s_and_b32 s6, s6, 0xfffff000
; MUBUF-NEXT: v_mov_b32_e32 v2, 0 ; MUBUF-NEXT: v_mov_b32_e32 v2, 0
; MUBUF-NEXT: v_mov_b32_e32 v5, s6 ; MUBUF-NEXT: v_mov_b32_e32 v5, s6
; MUBUF-NEXT: buffer_store_dword v2, v5, s[0:3], 0 offen ; MUBUF-NEXT: buffer_store_dword v2, v5, s[0:3], 0 offen
; MUBUF-NEXT: v_mov_b32_e32 v2, 1 ; MUBUF-NEXT: v_mov_b32_e32 v2, 1
; MUBUF-NEXT: buffer_store_dword v2, v5, s[0:3], 0 offen offset:4 ; MUBUF-NEXT: buffer_store_dword v2, v5, s[0:3], 0 offen offset:4
; MUBUF-NEXT: v_lshl_add_u32 v2, v3, 2, s6 ; MUBUF-NEXT: v_lshl_add_u32 v2, v3, 2, s6
; MUBUF-NEXT: buffer_load_dword v2, v2, s[0:3], 0 offen ; MUBUF-NEXT: buffer_load_dword v2, v2, s[0:3], 0 offen
; MUBUF-NEXT: v_and_b32_e32 v3, 0x3ff, v4 ; MUBUF-NEXT: v_and_b32_e32 v3, 0x3ff, v4
; MUBUF-NEXT: s_mov_b32 s32, s6 ; MUBUF-NEXT: s_mov_b32 s32, s6
; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: v_add_u32_e32 v2, v2, v3 ; MUBUF-NEXT: v_add_u32_e32 v2, v2, v3
; MUBUF-NEXT: global_store_dword v[0:1], v2, off ; MUBUF-NEXT: global_store_dword v[0:1], v2, off
; MUBUF-NEXT: BB3_2: ; %bb.1 ; MUBUF-NEXT: .LBB3_2: ; %bb.1
; MUBUF-NEXT: s_or_b64 exec, exec, s[4:5] ; MUBUF-NEXT: s_or_b64 exec, exec, s[4:5]
; MUBUF-NEXT: v_mov_b32_e32 v0, 0 ; MUBUF-NEXT: v_mov_b32_e32 v0, 0
; MUBUF-NEXT: global_store_dword v[0:1], v0, off ; MUBUF-NEXT: global_store_dword v[0:1], v0, off
; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: s_addk_i32 s32, 0xe000 ; MUBUF-NEXT: s_addk_i32 s32, 0xe000
; MUBUF-NEXT: s_mov_b32 s33, s7 ; MUBUF-NEXT: s_mov_b32 s33, s7
; MUBUF-NEXT: s_setpc_b64 s[30:31] ; MUBUF-NEXT: s_setpc_b64 s[30:31]
; ;
; FLATSCR-LABEL: func_non_entry_block_static_alloca_align64: ; FLATSCR-LABEL: func_non_entry_block_static_alloca_align64:
; FLATSCR: ; %bb.0: ; %entry ; FLATSCR: ; %bb.0: ; %entry
; FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; FLATSCR-NEXT: s_mov_b32 s3, s33 ; FLATSCR-NEXT: s_mov_b32 s3, s33
; FLATSCR-NEXT: s_add_i32 s33, s32, 63 ; FLATSCR-NEXT: s_add_i32 s33, s32, 63
; FLATSCR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; FLATSCR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; FLATSCR-NEXT: s_andn2_b32 s33, s33, 63 ; FLATSCR-NEXT: s_andn2_b32 s33, s33, 63
; FLATSCR-NEXT: s_addk_i32 s32, 0x80 ; FLATSCR-NEXT: s_addk_i32 s32, 0x80
; FLATSCR-NEXT: s_and_saveexec_b64 s[0:1], vcc ; FLATSCR-NEXT: s_and_saveexec_b64 s[0:1], vcc
; FLATSCR-NEXT: s_cbranch_execz BB3_2 ; FLATSCR-NEXT: s_cbranch_execz .LBB3_2
; FLATSCR-NEXT: ; %bb.1: ; %bb.0 ; FLATSCR-NEXT: ; %bb.1: ; %bb.0
; FLATSCR-NEXT: s_add_i32 s2, s32, 0x1000 ; FLATSCR-NEXT: s_add_i32 s2, s32, 0x1000
; FLATSCR-NEXT: s_and_b32 s2, s2, 0xfffff000 ; FLATSCR-NEXT: s_and_b32 s2, s2, 0xfffff000
; FLATSCR-NEXT: v_mov_b32_e32 v5, 0 ; FLATSCR-NEXT: v_mov_b32_e32 v5, 0
; FLATSCR-NEXT: v_mov_b32_e32 v6, 1 ; FLATSCR-NEXT: v_mov_b32_e32 v6, 1
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[5:6], s2 ; FLATSCR-NEXT: scratch_store_dwordx2 off, v[5:6], s2
; FLATSCR-NEXT: v_lshl_add_u32 v2, v3, 2, s2 ; FLATSCR-NEXT: v_lshl_add_u32 v2, v3, 2, s2
; FLATSCR-NEXT: scratch_load_dword v2, v2, off ; FLATSCR-NEXT: scratch_load_dword v2, v2, off
; FLATSCR-NEXT: v_and_b32_e32 v3, 0x3ff, v4 ; FLATSCR-NEXT: v_and_b32_e32 v3, 0x3ff, v4
; FLATSCR-NEXT: s_mov_b32 s32, s2 ; FLATSCR-NEXT: s_mov_b32 s32, s2
; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: v_add_u32_e32 v2, v2, v3 ; FLATSCR-NEXT: v_add_u32_e32 v2, v2, v3
; FLATSCR-NEXT: global_store_dword v[0:1], v2, off ; FLATSCR-NEXT: global_store_dword v[0:1], v2, off
; FLATSCR-NEXT: BB3_2: ; %bb.1 ; FLATSCR-NEXT: .LBB3_2: ; %bb.1
; FLATSCR-NEXT: s_or_b64 exec, exec, s[0:1] ; FLATSCR-NEXT: s_or_b64 exec, exec, s[0:1]
; FLATSCR-NEXT: v_mov_b32_e32 v0, 0 ; FLATSCR-NEXT: v_mov_b32_e32 v0, 0
; FLATSCR-NEXT: global_store_dword v[0:1], v0, off ; FLATSCR-NEXT: global_store_dword v[0:1], v0, off
; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: s_addk_i32 s32, 0xff80 ; FLATSCR-NEXT: s_addk_i32 s32, 0xff80
; FLATSCR-NEXT: s_mov_b32 s33, s3 ; FLATSCR-NEXT: s_mov_b32 s33, s3
; FLATSCR-NEXT: s_setpc_b64 s[30:31] ; FLATSCR-NEXT: s_setpc_b64 s[30:31]
entry: entry:
Show All 24 Lines

llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}negated_cond: ; GCN-LABEL: {{^}}negated_cond:
; GCN: BB0_1: ; GCN: .LBB0_1:
; GCN: v_cmp_eq_u32_e64 [[CC:[^,]+]], ; GCN: v_cmp_eq_u32_e64 [[CC:[^,]+]],
; GCN: BB0_3: ; GCN: .LBB0_3:
; GCN-NOT: v_cndmask_b32 ; GCN-NOT: v_cndmask_b32
; GCN-NOT: v_cmp ; GCN-NOT: v_cmp
; GCN: s_andn2_b64 vcc, exec, [[CC]] ; GCN: s_andn2_b64 vcc, exec, [[CC]]
; GCN: s_cbranch_vccnz BB0_2 ; GCN: s_cbranch_vccnz .LBB0_2
define amdgpu_kernel void @negated_cond(i32 addrspace(1)* %arg1) { define amdgpu_kernel void @negated_cond(i32 addrspace(1)* %arg1) {
bb: bb:
br label %bb1 br label %bb1
bb1: bb1:
%tmp1 = load i32, i32 addrspace(1)* %arg1 %tmp1 = load i32, i32 addrspace(1)* %arg1
%tmp2 = icmp eq i32 %tmp1, 0 %tmp2 = icmp eq i32 %tmp1, 0
br label %bb2 br label %bb2
Show All 13 Linesbb4:
store i32 0, i32 addrspace(1)* %gep store i32 0, i32 addrspace(1)* %gep
%tmp7 = icmp eq i32 %tmp6, 32 %tmp7 = icmp eq i32 %tmp6, 32
br i1 %tmp7, label %bb1, label %bb2 br i1 %tmp7, label %bb1, label %bb2
} }
; GCN-LABEL: {{^}}negated_cond_dominated_blocks: ; GCN-LABEL: {{^}}negated_cond_dominated_blocks:
; GCN: s_cmp_lg_u32 ; GCN: s_cmp_lg_u32
; GCN: s_cselect_b64 [[CC1:[^,]+]], -1, 0 ; GCN: s_cselect_b64 [[CC1:[^,]+]], -1, 0
; GCN: s_branch [[BB1:BB[0-9]+_[0-9]+]] ; GCN: s_branch [[BB1:.LBB[0-9]+_[0-9]+]]
; GCN: [[BB0:BB[0-9]+_[0-9]+]] ; GCN: [[BB0:.LBB[0-9]+_[0-9]+]]
; GCN-NOT: v_cndmask_b32 ; GCN-NOT: v_cndmask_b32
; GCN-NOT: v_cmp ; GCN-NOT: v_cmp
; GCN: [[BB1]]: ; GCN: [[BB1]]:
; GCN: s_mov_b64 [[CC2:[^,]+]], -1 ; GCN: s_mov_b64 [[CC2:[^,]+]], -1
; GCN: s_mov_b64 vcc, [[CC1]] ; GCN: s_mov_b64 vcc, [[CC1]]
; GCN: s_cbranch_vccz [[BB2:BB[0-9]+_[0-9]+]] ; GCN: s_cbranch_vccz [[BB2:.LBB[0-9]+_[0-9]+]]
; GCN: s_mov_b64 [[CC2]], 0 ; GCN: s_mov_b64 [[CC2]], 0
; GCN: [[BB2]]: ; GCN: [[BB2]]:
; GCN: s_andn2_b64 vcc, exec, [[CC2]] ; GCN: s_andn2_b64 vcc, exec, [[CC2]]
; GCN: s_cbranch_vccnz [[BB0]] ; GCN: s_cbranch_vccnz [[BB0]]
define amdgpu_kernel void @negated_cond_dominated_blocks(i32 addrspace(1)* %arg1) { define amdgpu_kernel void @negated_cond_dominated_blocks(i32 addrspace(1)* %arg1) {
bb: bb:
br label %bb2 br label %bb2
Show All 28 Lines

llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll

Show First 20 Lines • Show All 196 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_writelane_b32 v2, s7, 3 ; GCN-NEXT: v_writelane_b32 v2, s7, 3
; GCN-NEXT: v_writelane_b32 v2, s8, 4 ; GCN-NEXT: v_writelane_b32 v2, s8, 4
; GCN-NEXT: v_writelane_b32 v2, s9, 5 ; GCN-NEXT: v_writelane_b32 v2, s9, 5
; GCN-NEXT: v_writelane_b32 v2, s10, 6 ; GCN-NEXT: v_writelane_b32 v2, s10, 6
; GCN-NEXT: v_writelane_b32 v2, s11, 7 ; GCN-NEXT: v_writelane_b32 v2, s11, 7
; GCN-NEXT: s_mov_b32 s1, 0 ; GCN-NEXT: s_mov_b32 s1, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_cmp_lg_u32 s0, s1 ; GCN-NEXT: s_cmp_lg_u32 s0, s1
; GCN-NEXT: s_cbranch_scc1 BB0_2 ; GCN-NEXT: s_cbranch_scc1 .LBB0_2
; GCN-NEXT: ; %bb.1: ; %bb0 ; GCN-NEXT: ; %bb.1: ; %bb0
; GCN-NEXT: v_readlane_b32 s8, v1, 56 ; GCN-NEXT: v_readlane_b32 s8, v1, 56
; GCN-NEXT: v_readlane_b32 s9, v1, 57 ; GCN-NEXT: v_readlane_b32 s9, v1, 57
; GCN-NEXT: v_readlane_b32 s10, v1, 58 ; GCN-NEXT: v_readlane_b32 s10, v1, 58
; GCN-NEXT: v_readlane_b32 s11, v1, 59 ; GCN-NEXT: v_readlane_b32 s11, v1, 59
; GCN-NEXT: v_readlane_b32 s12, v1, 60 ; GCN-NEXT: v_readlane_b32 s12, v1, 60
; GCN-NEXT: v_readlane_b32 s13, v1, 61 ; GCN-NEXT: v_readlane_b32 s13, v1, 61
; GCN-NEXT: v_readlane_b32 s14, v1, 62 ; GCN-NEXT: v_readlane_b32 s14, v1, 62
▲ Show 20 Lines • Show All 172 Lines • ▼ Show 20 Lines
; GCN-NEXT: ; use s[16:23] ; GCN-NEXT: ; use s[16:23]
; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: ;;#ASMEND
; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: ;;#ASMSTART
; GCN-NEXT: ; use s[8:15] ; GCN-NEXT: ; use s[8:15]
; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: ;;#ASMEND
; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: ;;#ASMSTART
; GCN-NEXT: ; use s[0:7] ; GCN-NEXT: ; use s[0:7]
; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: ;;#ASMEND
; GCN-NEXT: BB0_2: ; %ret ; GCN-NEXT: .LBB0_2: ; %ret
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
%wide.sgpr0 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0 %wide.sgpr0 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
%wide.sgpr1 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0 %wide.sgpr1 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
%wide.sgpr2 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0 %wide.sgpr2 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
%wide.sgpr3 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0 %wide.sgpr3 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
%wide.sgpr4 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0 %wide.sgpr4 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
%wide.sgpr5 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0 %wide.sgpr5 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
%wide.sgpr6 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0 %wide.sgpr6 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
▲ Show 20 Lines • Show All 130 Lines • ▼ Show 20 Lines
; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: ;;#ASMSTART
; GCN-NEXT: ; def s[2:3] ; GCN-NEXT: ; def s[2:3]
; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: ;;#ASMEND
; GCN-NEXT: v_writelane_b32 v1, s2, 8 ; GCN-NEXT: v_writelane_b32 v1, s2, 8
; GCN-NEXT: v_writelane_b32 v1, s3, 9 ; GCN-NEXT: v_writelane_b32 v1, s3, 9
; GCN-NEXT: s_mov_b32 s1, 0 ; GCN-NEXT: s_mov_b32 s1, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_cmp_lg_u32 s0, s1 ; GCN-NEXT: s_cmp_lg_u32 s0, s1
; GCN-NEXT: s_cbranch_scc1 BB1_2 ; GCN-NEXT: s_cbranch_scc1 .LBB1_2
; GCN-NEXT: ; %bb.1: ; %bb0 ; GCN-NEXT: ; %bb.1: ; %bb0
; GCN-NEXT: v_readlane_b32 s16, v1, 8 ; GCN-NEXT: v_readlane_b32 s16, v1, 8
; GCN-NEXT: v_readlane_b32 s17, v1, 9 ; GCN-NEXT: v_readlane_b32 s17, v1, 9
; GCN-NEXT: v_readlane_b32 s20, v1, 0 ; GCN-NEXT: v_readlane_b32 s20, v1, 0
; GCN-NEXT: v_readlane_b32 s21, v1, 1 ; GCN-NEXT: v_readlane_b32 s21, v1, 1
; GCN-NEXT: v_readlane_b32 s22, v1, 2 ; GCN-NEXT: v_readlane_b32 s22, v1, 2
; GCN-NEXT: v_readlane_b32 s23, v1, 3 ; GCN-NEXT: v_readlane_b32 s23, v1, 3
; GCN-NEXT: v_readlane_b32 s24, v1, 4 ; GCN-NEXT: v_readlane_b32 s24, v1, 4
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; GCN-NEXT: ; use s[20:27] ; GCN-NEXT: ; use s[20:27]
; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: ;;#ASMEND
; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: ;;#ASMSTART
; GCN-NEXT: ; use s[16:17] ; GCN-NEXT: ; use s[16:17]
; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: ;;#ASMEND
; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: ;;#ASMSTART
; GCN-NEXT: ; use s[0:15] ; GCN-NEXT: ; use s[0:15]
; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: ;;#ASMEND
; GCN-NEXT: BB1_2: ; %ret ; GCN-NEXT: .LBB1_2: ; %ret
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
%wide.sgpr0 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0 %wide.sgpr0 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0
%wide.sgpr1 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0 %wide.sgpr1 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0
%wide.sgpr2 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0 %wide.sgpr2 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0
%wide.sgpr5 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0 %wide.sgpr5 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0
%wide.sgpr3 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0 %wide.sgpr3 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
%wide.sgpr4 = call <2 x i32> asm sideeffect "; def $0", "=s" () #0 %wide.sgpr4 = call <2 x i32> asm sideeffect "; def $0", "=s" () #0
▲ Show 20 Lines • Show All 124 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_writelane_b32 v0, s3, 1 ; GCN-NEXT: v_writelane_b32 v0, s3, 1
; GCN-NEXT: buffer_store_dword v0, off, s[52:55], 0 offset:4 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v0, off, s[52:55], 0 offset:4 ; 4-byte Folded Spill
; GCN-NEXT: buffer_load_dword v0, off, s[52:55], 0 ; GCN-NEXT: buffer_load_dword v0, off, s[52:55], 0
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_mov_b64 exec, s[4:5] ; GCN-NEXT: s_mov_b64 exec, s[4:5]
; GCN-NEXT: s_mov_b32 s1, 0 ; GCN-NEXT: s_mov_b32 s1, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_cmp_lg_u32 s0, s1 ; GCN-NEXT: s_cmp_lg_u32 s0, s1
; GCN-NEXT: s_cbranch_scc1 BB2_2 ; GCN-NEXT: s_cbranch_scc1 .LBB2_2
; GCN-NEXT: ; %bb.1: ; %bb0 ; GCN-NEXT: ; %bb.1: ; %bb0
; GCN-NEXT: v_readlane_b32 s36, v31, 32 ; GCN-NEXT: v_readlane_b32 s36, v31, 32
; GCN-NEXT: v_readlane_b32 s37, v31, 33 ; GCN-NEXT: v_readlane_b32 s37, v31, 33
; GCN-NEXT: v_readlane_b32 s38, v31, 34 ; GCN-NEXT: v_readlane_b32 s38, v31, 34
; GCN-NEXT: v_readlane_b32 s39, v31, 35 ; GCN-NEXT: v_readlane_b32 s39, v31, 35
; GCN-NEXT: v_readlane_b32 s40, v31, 36 ; GCN-NEXT: v_readlane_b32 s40, v31, 36
; GCN-NEXT: v_readlane_b32 s41, v31, 37 ; GCN-NEXT: v_readlane_b32 s41, v31, 37
; GCN-NEXT: v_readlane_b32 s42, v31, 38 ; GCN-NEXT: v_readlane_b32 s42, v31, 38
▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Lines
; GCN-NEXT: ; use s[36:51] ; GCN-NEXT: ; use s[36:51]
; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: ;;#ASMEND
; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: ;;#ASMSTART
; GCN-NEXT: ; use s[4:19] ; GCN-NEXT: ; use s[4:19]
; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: ;;#ASMEND
; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: ;;#ASMSTART
; GCN-NEXT: ; use s[0:1] ; GCN-NEXT: ; use s[0:1]
; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: ;;#ASMEND
; GCN-NEXT: BB2_2: ; %ret ; GCN-NEXT: .LBB2_2: ; %ret
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
call void asm sideeffect "", "~{v[0:7]}" () #0 call void asm sideeffect "", "~{v[0:7]}" () #0
call void asm sideeffect "", "~{v[8:15]}" () #0 call void asm sideeffect "", "~{v[8:15]}" () #0
call void asm sideeffect "", "~{v[16:23]}" () #0 call void asm sideeffect "", "~{v[16:23]}" () #0
call void asm sideeffect "", "~{v[24:27]}"() #0 call void asm sideeffect "", "~{v[24:27]}"() #0
call void asm sideeffect "", "~{v[28:29]}"() #0 call void asm sideeffect "", "~{v[28:29]}"() #0
call void asm sideeffect "", "~{v30}"() #0 call void asm sideeffect "", "~{v30}"() #0
▲ Show 20 Lines • Show All 127 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_writelane_b32 v0, s3, 1 ; GCN-NEXT: v_writelane_b32 v0, s3, 1
; GCN-NEXT: buffer_store_dword v0, off, s[52:55], 0 offset:4 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v0, off, s[52:55], 0 offset:4 ; 4-byte Folded Spill
; GCN-NEXT: buffer_load_dword v0, off, s[52:55], 0 ; GCN-NEXT: buffer_load_dword v0, off, s[52:55], 0
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_mov_b64 exec, s[4:5] ; GCN-NEXT: s_mov_b64 exec, s[4:5]
; GCN-NEXT: s_mov_b32 s1, 0 ; GCN-NEXT: s_mov_b32 s1, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_cmp_lg_u32 s0, s1 ; GCN-NEXT: s_cmp_lg_u32 s0, s1
; GCN-NEXT: s_cbranch_scc1 BB3_2 ; GCN-NEXT: s_cbranch_scc1 .LBB3_2
; GCN-NEXT: ; %bb.1: ; %bb0 ; GCN-NEXT: ; %bb.1: ; %bb0
; GCN-NEXT: v_readlane_b32 s36, v31, 32 ; GCN-NEXT: v_readlane_b32 s36, v31, 32
; GCN-NEXT: v_readlane_b32 s37, v31, 33 ; GCN-NEXT: v_readlane_b32 s37, v31, 33
; GCN-NEXT: v_readlane_b32 s38, v31, 34 ; GCN-NEXT: v_readlane_b32 s38, v31, 34
; GCN-NEXT: v_readlane_b32 s39, v31, 35 ; GCN-NEXT: v_readlane_b32 s39, v31, 35
; GCN-NEXT: v_readlane_b32 s40, v31, 36 ; GCN-NEXT: v_readlane_b32 s40, v31, 36
; GCN-NEXT: v_readlane_b32 s41, v31, 37 ; GCN-NEXT: v_readlane_b32 s41, v31, 37
; GCN-NEXT: v_readlane_b32 s42, v31, 38 ; GCN-NEXT: v_readlane_b32 s42, v31, 38
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
; GCN-NEXT: ; use s[4:19] ; GCN-NEXT: ; use s[4:19]
; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: ;;#ASMEND
; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: ;;#ASMSTART
; GCN-NEXT: ; use s[0:1] ; GCN-NEXT: ; use s[0:1]
; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: ;;#ASMEND
; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: ;;#ASMSTART
; GCN-NEXT: ; use v0 ; GCN-NEXT: ; use v0
; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: ;;#ASMEND
; GCN-NEXT: BB3_2: ; %ret ; GCN-NEXT: .LBB3_2: ; %ret
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
call void asm sideeffect "", "~{v[0:7]}" () #0 call void asm sideeffect "", "~{v[0:7]}" () #0
call void asm sideeffect "", "~{v[8:15]}" () #0 call void asm sideeffect "", "~{v[8:15]}" () #0
call void asm sideeffect "", "~{v[16:23]}" () #0 call void asm sideeffect "", "~{v[16:23]}" () #0
call void asm sideeffect "", "~{v[24:27]}"() #0 call void asm sideeffect "", "~{v[24:27]}"() #0
call void asm sideeffect "", "~{v[28:29]}"() #0 call void asm sideeffect "", "~{v[28:29]}"() #0
call void asm sideeffect "", "~{v30}"() #0 call void asm sideeffect "", "~{v30}"() #0
Show All 24 Lines

llvm/test/CodeGen/AMDGPU/remat-fp64-constants.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs --stress-regalloc=10 < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs --stress-regalloc=10 < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs --stress-regalloc=10 < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs --stress-regalloc=10 < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}test_remat_sgpr: ; GCN-LABEL: {{^}}test_remat_sgpr:
; GCN-NOT: v_writelane_b32 ; GCN-NOT: v_writelane_b32
; GCN: {{^}}[[LOOP:BB[0-9_]+]]: ; GCN: {{^}}[[LOOP:.LBB[0-9_]+]]:
; GCN-COUNT-6: s_mov_b32 s{{[0-9]+}}, 0x ; GCN-COUNT-6: s_mov_b32 s{{[0-9]+}}, 0x
; GCN-NOT: v_writelane_b32 ; GCN-NOT: v_writelane_b32
; GCN: s_cbranch_{{[^ ]+}} [[LOOP]] ; GCN: s_cbranch_{{[^ ]+}} [[LOOP]]
; GCN: .sgpr_spill_count: 0 ; GCN: .sgpr_spill_count: 0
define amdgpu_kernel void @test_remat_sgpr(double addrspace(1)* %arg, double addrspace(1)* %arg1) { define amdgpu_kernel void @test_remat_sgpr(double addrspace(1)* %arg, double addrspace(1)* %arg1) {
bb: bb:
%i = tail call i32 @llvm.amdgcn.workitem.id.x() %i = tail call i32 @llvm.amdgcn.workitem.id.x()
br label %bb3 br label %bb3
Show All 31 Lines

llvm/test/CodeGen/AMDGPU/ret_jump.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s
; This should end with an no-op sequence of exec mask manipulations ; This should end with an no-op sequence of exec mask manipulations
; Mask should be in original state after executed unreachable block ; Mask should be in original state after executed unreachable block
; GCN-LABEL: {{^}}uniform_br_trivial_ret_divergent_br_trivial_unreachable: ; GCN-LABEL: {{^}}uniform_br_trivial_ret_divergent_br_trivial_unreachable:
; GCN: s_cbranch_scc1 [[RET_BB:BB[0-9]+_[0-9]+]] ; GCN: s_cbranch_scc1 [[RET_BB:.LBB[0-9]+_[0-9]+]]
; GCN-NEXT: ; %else ; GCN-NEXT: ; %else
; GCN: s_and_saveexec_b64 [[SAVE_EXEC:s\[[0-9]+:[0-9]+\]]], vcc ; GCN: s_and_saveexec_b64 [[SAVE_EXEC:s\[[0-9]+:[0-9]+\]]], vcc
; GCN: ; %bb.{{[0-9]+}}: ; %unreachable.bb ; GCN: ; %bb.{{[0-9]+}}: ; %unreachable.bb
; GCN-NEXT: ; divergent unreachable ; GCN-NEXT: ; divergent unreachable
Show All 34 Lines
ret.bb: ; preds = %else, %main_body ret.bb: ; preds = %else, %main_body
ret <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef ret <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef
} }
; GCN-LABEL: {{^}}uniform_br_nontrivial_ret_divergent_br_nontrivial_unreachable: ; GCN-LABEL: {{^}}uniform_br_nontrivial_ret_divergent_br_nontrivial_unreachable:
; GCN: s_cbranch_vccz ; GCN: s_cbranch_vccz
; GCN: ; %bb.{{[0-9]+}}: ; %Flow ; GCN: ; %bb.{{[0-9]+}}: ; %Flow
; GCN: s_cbranch_execnz [[RETURN:BB[0-9]+_[0-9]+]] ; GCN: s_cbranch_execnz [[RETURN:.LBB[0-9]+_[0-9]+]]
; GCN: ; %UnifiedReturnBlock ; GCN: ; %UnifiedReturnBlock
; GCN-NEXT: s_or_b64 exec, exec ; GCN-NEXT: s_or_b64 exec, exec
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN: BB{{[0-9]+_[0-9]+}}: ; %else ; GCN: .LBB{{[0-9]+_[0-9]+}}: ; %else
; GCN: s_and_saveexec_b64 [[SAVE_EXEC:s\[[0-9]+:[0-9]+\]]], vcc ; GCN: s_and_saveexec_b64 [[SAVE_EXEC:s\[[0-9]+:[0-9]+\]]], vcc
; GCN-NEXT: s_cbranch_execz BB1_{{[0-9]+}} ; GCN-NEXT: s_cbranch_execz .LBB1_{{[0-9]+}}
; GCN-NEXT: ; %unreachable.bb ; GCN-NEXT: ; %unreachable.bb
; GCN: ds_write_b32 ; GCN: ds_write_b32
; GCN: ; divergent unreachable ; GCN: ; divergent unreachable
; GCN: ; %ret.bb ; GCN: ; %ret.bb
; GCN: store_dword ; GCN: store_dword
define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @uniform_br_nontrivial_ret_divergent_br_nontrivial_unreachable([9 x <4 x i32>] addrspace(4)* inreg %arg, [17 x <4 x i32>] addrspace(4)* inreg %arg1, [17 x <8 x i32>] addrspace(4)* inreg %arg2, i32 addrspace(4)* inreg %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, i32 inreg %arg18, i32 %arg19, float %arg20, i32 %arg21) #0 { define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @uniform_br_nontrivial_ret_divergent_br_nontrivial_unreachable([9 x <4 x i32>] addrspace(4)* inreg %arg, [17 x <4 x i32>] addrspace(4)* inreg %arg1, [17 x <8 x i32>] addrspace(4)* inreg %arg2, i32 addrspace(4)* inreg %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, i32 inreg %arg18, i32 %arg19, float %arg20, i32 %arg21) #0 {
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/salu-to-valu.ll

Show First 20 Lines • Show All 434 Lines • ▼ Show 20 Lines
} }
; Make sure we legalize vopc operands after moving an sopc to the value. ; Make sure we legalize vopc operands after moving an sopc to the value.
; {{^}}sopc_vopc_legalize_bug: ; {{^}}sopc_vopc_legalize_bug:
; GCN: s_load_dword [[SGPR:s[0-9]+]] ; GCN: s_load_dword [[SGPR:s[0-9]+]]
; GCN: v_cmp_le_u32_e32 vcc, [[SGPR]], v{{[0-9]+}} ; GCN: v_cmp_le_u32_e32 vcc, [[SGPR]], v{{[0-9]+}}
; GCN: s_and_b64 vcc, exec, vcc ; GCN: s_and_b64 vcc, exec, vcc
; GCN: s_cbranch_vccnz [[EXIT:[A-Z0-9_]+]] ; GCN: s_cbranch_vccnz [[EXIT:.L[A-Z0-9_]+]]
; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1 ; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
; GCN-NOHSA: buffer_store_dword [[ONE]] ; GCN-NOHSA: buffer_store_dword [[ONE]]
; GCN-HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[ONE]] ; GCN-HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[ONE]]
; GCN: {{^}}[[EXIT]]: ; GCN: {{^}}[[EXIT]]:
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @sopc_vopc_legalize_bug(i32 %cond, i32 addrspace(1)* %out, i32 addrspace(1)* %in) { define amdgpu_kernel void @sopc_vopc_legalize_bug(i32 %cond, i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
bb3: ; preds = %bb2 bb3: ; preds = %bb2
%tmp0 = bitcast i32 %cond to float %tmp0 = bitcast i32 %cond to float
Show All 30 Linesbb4:
%tmp5 = phi i32 [ %tmp3, %bb2 ], [ %tmp, %bb1 ] %tmp5 = phi i32 [ %tmp3, %bb2 ], [ %tmp, %bb1 ]
store volatile i32 %tmp5, i32 addrspace(1)* undef store volatile i32 %tmp5, i32 addrspace(1)* undef
br label %bb1 br label %bb1
} }
; GCN-LABEL: {{^}}phi_imm_in_sgprs ; GCN-LABEL: {{^}}phi_imm_in_sgprs
; GCN: s_movk_i32 [[A:s[0-9]+]], 0x400 ; GCN: s_movk_i32 [[A:s[0-9]+]], 0x400
; GCN: s_movk_i32 [[B:s[0-9]+]], 0x400 ; GCN: s_movk_i32 [[B:s[0-9]+]], 0x400
; GCN: [[LOOP_LABEL:[0-9a-zA-Z_]+]]: ; GCN: [[LOOP_LABEL:.L[0-9a-zA-Z_]+]]:
; GCN: s_xor_b32 [[B]], [[B]], [[A]] ; GCN: s_xor_b32 [[B]], [[B]], [[A]]
; GCN: s_cbranch_scc{{[01]}} [[LOOP_LABEL]] ; GCN: s_cbranch_scc{{[01]}} [[LOOP_LABEL]]
define amdgpu_kernel void @phi_imm_in_sgprs(i32 addrspace(3)* %out, i32 %cond) { define amdgpu_kernel void @phi_imm_in_sgprs(i32 addrspace(3)* %out, i32 %cond) {
entry: entry:
br label %loop br label %loop
loop: loop:
%i = phi i32 [0, %entry], [%i.add, %loop] %i = phi i32 [0, %entry], [%i.add, %loop]
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llvm/test/CodeGen/AMDGPU/sdiv64.ll

Show First 20 Lines • Show All 169 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: s_subb_u32 s13, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s13, 0, 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[20:21], s[12:13], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[20:21], s[12:13], 63
; GCN-IR-NEXT: s_mov_b32 s15, 0 ; GCN-IR-NEXT: s_mov_b32 s15, 0
; GCN-IR-NEXT: s_or_b64 s[18:19], s[18:19], s[20:21] ; GCN-IR-NEXT: s_or_b64 s[18:19], s[18:19], s[20:21]
; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[20:21], s[12:13], 63 ; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[20:21], s[12:13], 63
; GCN-IR-NEXT: s_xor_b64 s[22:23], s[18:19], -1 ; GCN-IR-NEXT: s_xor_b64 s[22:23], s[18:19], -1
; GCN-IR-NEXT: s_and_b64 s[20:21], s[22:23], s[20:21] ; GCN-IR-NEXT: s_and_b64 s[20:21], s[22:23], s[20:21]
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[20:21] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[20:21]
; GCN-IR-NEXT: s_cbranch_vccz BB0_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_5
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s18, s12, 1 ; GCN-IR-NEXT: s_add_u32 s18, s12, 1
; GCN-IR-NEXT: v_mov_b32_e32 v0, s12 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s12
; GCN-IR-NEXT: s_addc_u32 s19, s13, 0 ; GCN-IR-NEXT: s_addc_u32 s19, s13, 0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s13 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s13
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[18:19], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[18:19], v[0:1]
; GCN-IR-NEXT: s_sub_i32 s12, 63, s12 ; GCN-IR-NEXT: s_sub_i32 s12, 63, s12
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[10:11], s12 ; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[10:11], s12
; GCN-IR-NEXT: s_cbranch_vccz BB0_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[18:19], s[10:11], s18 ; GCN-IR-NEXT: s_lshr_b64 s[18:19], s[10:11], s18
; GCN-IR-NEXT: s_add_u32 s20, s6, -1 ; GCN-IR-NEXT: s_add_u32 s20, s6, -1
; GCN-IR-NEXT: s_addc_u32 s21, s7, -1 ; GCN-IR-NEXT: s_addc_u32 s21, s7, -1
; GCN-IR-NEXT: s_not_b64 s[8:9], s[14:15] ; GCN-IR-NEXT: s_not_b64 s[8:9], s[14:15]
; GCN-IR-NEXT: s_add_u32 s10, s8, s16 ; GCN-IR-NEXT: s_add_u32 s10, s8, s16
; GCN-IR-NEXT: s_mov_b32 s17, s15 ; GCN-IR-NEXT: s_mov_b32 s17, s15
; GCN-IR-NEXT: s_addc_u32 s11, s9, s15 ; GCN-IR-NEXT: s_addc_u32 s11, s9, s15
; GCN-IR-NEXT: s_mov_b64 s[14:15], 0 ; GCN-IR-NEXT: s_mov_b64 s[14:15], 0
; GCN-IR-NEXT: s_mov_b32 s9, 0 ; GCN-IR-NEXT: s_mov_b32 s9, 0
; GCN-IR-NEXT: BB0_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB0_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[16:17], s[18:19], 1 ; GCN-IR-NEXT: s_lshl_b64 s[16:17], s[18:19], 1
; GCN-IR-NEXT: s_lshr_b32 s8, s13, 31 ; GCN-IR-NEXT: s_lshr_b32 s8, s13, 31
; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1 ; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1
; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[8:9] ; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[8:9]
; GCN-IR-NEXT: s_or_b64 s[12:13], s[14:15], s[12:13] ; GCN-IR-NEXT: s_or_b64 s[12:13], s[14:15], s[12:13]
; GCN-IR-NEXT: s_sub_u32 s8, s20, s16 ; GCN-IR-NEXT: s_sub_u32 s8, s20, s16
; GCN-IR-NEXT: s_subb_u32 s8, s21, s17 ; GCN-IR-NEXT: s_subb_u32 s8, s21, s17
; GCN-IR-NEXT: s_ashr_i32 s14, s8, 31 ; GCN-IR-NEXT: s_ashr_i32 s14, s8, 31
; GCN-IR-NEXT: s_mov_b32 s15, s14 ; GCN-IR-NEXT: s_mov_b32 s15, s14
; GCN-IR-NEXT: s_and_b32 s8, s14, 1 ; GCN-IR-NEXT: s_and_b32 s8, s14, 1
; GCN-IR-NEXT: s_and_b64 s[18:19], s[14:15], s[6:7] ; GCN-IR-NEXT: s_and_b64 s[18:19], s[14:15], s[6:7]
; GCN-IR-NEXT: s_sub_u32 s18, s16, s18 ; GCN-IR-NEXT: s_sub_u32 s18, s16, s18
; GCN-IR-NEXT: v_mov_b32_e32 v0, s10 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s10
; GCN-IR-NEXT: s_subb_u32 s19, s17, s19 ; GCN-IR-NEXT: s_subb_u32 s19, s17, s19
; GCN-IR-NEXT: v_mov_b32_e32 v1, s11 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s11
; GCN-IR-NEXT: s_add_u32 s10, s10, 1 ; GCN-IR-NEXT: s_add_u32 s10, s10, 1
; GCN-IR-NEXT: s_addc_u32 s11, s11, 0 ; GCN-IR-NEXT: s_addc_u32 s11, s11, 0
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
; GCN-IR-NEXT: s_mov_b64 s[14:15], s[8:9] ; GCN-IR-NEXT: s_mov_b64 s[14:15], s[8:9]
; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_cbranch_vccz BB0_3 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_3
; GCN-IR-NEXT: BB0_4: ; %Flow6 ; GCN-IR-NEXT: .LBB0_4: ; %Flow6
; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[12:13], 1 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[12:13], 1
; GCN-IR-NEXT: s_or_b64 s[6:7], s[8:9], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[6:7], s[8:9], s[6:7]
; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
; GCN-IR-NEXT: v_mov_b32_e32 v1, s7 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s7
; GCN-IR-NEXT: s_branch BB0_6 ; GCN-IR-NEXT: s_branch .LBB0_6
; GCN-IR-NEXT: BB0_5: ; GCN-IR-NEXT: .LBB0_5:
; GCN-IR-NEXT: v_mov_b32_e32 v0, s11 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s11
; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[18:19] ; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[18:19]
; GCN-IR-NEXT: v_mov_b32_e32 v0, s10 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s10
; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[18:19] ; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[18:19]
; GCN-IR-NEXT: BB0_6: ; %udiv-end ; GCN-IR-NEXT: .LBB0_6: ; %udiv-end
; GCN-IR-NEXT: s_xor_b64 s[0:1], s[2:3], s[0:1] ; GCN-IR-NEXT: s_xor_b64 s[0:1], s[2:3], s[0:1]
; GCN-IR-NEXT: v_xor_b32_e32 v0, s0, v0 ; GCN-IR-NEXT: v_xor_b32_e32 v0, s0, v0
; GCN-IR-NEXT: v_xor_b32_e32 v1, s1, v1 ; GCN-IR-NEXT: v_xor_b32_e32 v1, s1, v1
; GCN-IR-NEXT: v_mov_b32_e32 v2, s1 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s1
; GCN-IR-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0 ; GCN-IR-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: s_mov_b32 s6, -1
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
▲ Show 20 Lines • Show All 163 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: v_mov_b32_e32 v17, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v17, 0
; GCN-IR-NEXT: v_mov_b32_e32 v6, v4 ; GCN-IR-NEXT: v_mov_b32_e32 v6, v4
; GCN-IR-NEXT: v_mov_b32_e32 v1, v5 ; GCN-IR-NEXT: v_mov_b32_e32 v1, v5
; GCN-IR-NEXT: v_cndmask_b32_e64 v10, v12, 0, s[6:7] ; GCN-IR-NEXT: v_cndmask_b32_e64 v10, v12, 0, s[6:7]
; GCN-IR-NEXT: s_and_b64 s[4:5], s[8:9], s[4:5] ; GCN-IR-NEXT: s_and_b64 s[4:5], s[8:9], s[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v16, v17 ; GCN-IR-NEXT: v_mov_b32_e32 v16, v17
; GCN-IR-NEXT: v_cndmask_b32_e64 v9, v11, 0, s[6:7] ; GCN-IR-NEXT: v_cndmask_b32_e64 v9, v11, 0, s[6:7]
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB1_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB1_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, 1, v7 ; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, 1, v7
; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, 0, v8, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, 0, v8, vcc
; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[14:15], v[7:8] ; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[14:15], v[7:8]
; GCN-IR-NEXT: v_sub_i32_e64 v7, s[4:5], 63, v7 ; GCN-IR-NEXT: v_sub_i32_e64 v7, s[4:5], 63, v7
; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[11:12], v7 ; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[11:12], v7
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB1_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB1_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_add_i32_e32 v18, vcc, -1, v2 ; GCN-IR-NEXT: v_add_i32_e32 v18, vcc, -1, v2
; GCN-IR-NEXT: v_addc_u32_e32 v19, vcc, -1, v3, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v19, vcc, -1, v3, vcc
; GCN-IR-NEXT: v_not_b32_e32 v0, v0 ; GCN-IR-NEXT: v_not_b32_e32 v0, v0
; GCN-IR-NEXT: v_lshr_b64 v[14:15], v[11:12], v14 ; GCN-IR-NEXT: v_lshr_b64 v[14:15], v[11:12], v14
; GCN-IR-NEXT: v_not_b32_e32 v9, v17 ; GCN-IR-NEXT: v_not_b32_e32 v9, v17
; GCN-IR-NEXT: v_add_i32_e32 v11, vcc, v0, v13 ; GCN-IR-NEXT: v_add_i32_e32 v11, vcc, v0, v13
; GCN-IR-NEXT: v_addc_u32_e32 v12, vcc, v9, v16, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v12, vcc, v9, v16, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v16, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v16, 0
; GCN-IR-NEXT: v_mov_b32_e32 v17, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v17, 0
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: BB1_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB1_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[14:15], v[14:15], 1 ; GCN-IR-NEXT: v_lshl_b64 v[14:15], v[14:15], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 31, v8 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 31, v8
; GCN-IR-NEXT: v_or_b32_e32 v0, v14, v0 ; GCN-IR-NEXT: v_or_b32_e32 v0, v14, v0
; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1 ; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1
; GCN-IR-NEXT: v_sub_i32_e32 v9, vcc, v18, v0 ; GCN-IR-NEXT: v_sub_i32_e32 v9, vcc, v18, v0
; GCN-IR-NEXT: v_subb_u32_e32 v9, vcc, v19, v15, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v9, vcc, v19, v15, vcc
; GCN-IR-NEXT: v_or_b32_e32 v7, v16, v7 ; GCN-IR-NEXT: v_or_b32_e32 v7, v16, v7
; GCN-IR-NEXT: v_add_i32_e32 v16, vcc, 1, v11 ; GCN-IR-NEXT: v_add_i32_e32 v16, vcc, 1, v11
; GCN-IR-NEXT: v_or_b32_e32 v8, v17, v8 ; GCN-IR-NEXT: v_or_b32_e32 v8, v17, v8
; GCN-IR-NEXT: v_ashrrev_i32_e32 v13, 31, v9 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v13, 31, v9
; GCN-IR-NEXT: v_addc_u32_e32 v17, vcc, 0, v12, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v17, vcc, 0, v12, vcc
; GCN-IR-NEXT: v_and_b32_e32 v9, 1, v13 ; GCN-IR-NEXT: v_and_b32_e32 v9, 1, v13
; GCN-IR-NEXT: v_and_b32_e32 v20, v13, v3 ; GCN-IR-NEXT: v_and_b32_e32 v20, v13, v3
; GCN-IR-NEXT: v_and_b32_e32 v13, v13, v2 ; GCN-IR-NEXT: v_and_b32_e32 v13, v13, v2
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[16:17], v[11:12] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[16:17], v[11:12]
; GCN-IR-NEXT: v_mov_b32_e32 v11, v16 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v16
; GCN-IR-NEXT: v_sub_i32_e64 v14, s[4:5], v0, v13 ; GCN-IR-NEXT: v_sub_i32_e64 v14, s[4:5], v0, v13
; GCN-IR-NEXT: v_mov_b32_e32 v12, v17 ; GCN-IR-NEXT: v_mov_b32_e32 v12, v17
; GCN-IR-NEXT: v_mov_b32_e32 v17, v10 ; GCN-IR-NEXT: v_mov_b32_e32 v17, v10
; GCN-IR-NEXT: v_subb_u32_e64 v15, s[4:5], v15, v20, s[4:5] ; GCN-IR-NEXT: v_subb_u32_e64 v15, s[4:5], v15, v20, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v16, v9 ; GCN-IR-NEXT: v_mov_b32_e32 v16, v9
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execnz BB1_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB1_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: BB1_5: ; %Flow3 ; GCN-IR-NEXT: .LBB1_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[7:8], 1 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[7:8], 1
; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v3 ; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v3
; GCN-IR-NEXT: v_or_b32_e32 v9, v9, v2 ; GCN-IR-NEXT: v_or_b32_e32 v9, v9, v2
; GCN-IR-NEXT: BB1_6: ; %Flow4 ; GCN-IR-NEXT: .LBB1_6: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_xor_b32_e32 v0, v5, v4 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v5, v4
; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v6 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v6
; GCN-IR-NEXT: v_xor_b32_e32 v3, v9, v0 ; GCN-IR-NEXT: v_xor_b32_e32 v3, v9, v0
; GCN-IR-NEXT: v_xor_b32_e32 v2, v10, v1 ; GCN-IR-NEXT: v_xor_b32_e32 v2, v10, v1
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v3, v0 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v3, v0
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc
; GCN-IR-NEXT: s_setpc_b64 s[30:31] ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
▲ Show 20 Lines • Show All 549 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: s_subb_u32 s13, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s13, 0, 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[20:21], s[12:13], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[20:21], s[12:13], 63
; GCN-IR-NEXT: s_mov_b32 s15, 0 ; GCN-IR-NEXT: s_mov_b32 s15, 0
; GCN-IR-NEXT: s_or_b64 s[18:19], s[18:19], s[20:21] ; GCN-IR-NEXT: s_or_b64 s[18:19], s[18:19], s[20:21]
; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[20:21], s[12:13], 63 ; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[20:21], s[12:13], 63
; GCN-IR-NEXT: s_xor_b64 s[22:23], s[18:19], -1 ; GCN-IR-NEXT: s_xor_b64 s[22:23], s[18:19], -1
; GCN-IR-NEXT: s_and_b64 s[20:21], s[22:23], s[20:21] ; GCN-IR-NEXT: s_and_b64 s[20:21], s[22:23], s[20:21]
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[20:21] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[20:21]
; GCN-IR-NEXT: s_cbranch_vccz BB9_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB9_5
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s18, s12, 1 ; GCN-IR-NEXT: s_add_u32 s18, s12, 1
; GCN-IR-NEXT: v_mov_b32_e32 v0, s12 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s12
; GCN-IR-NEXT: s_addc_u32 s19, s13, 0 ; GCN-IR-NEXT: s_addc_u32 s19, s13, 0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s13 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s13
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[18:19], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[18:19], v[0:1]
; GCN-IR-NEXT: s_sub_i32 s12, 63, s12 ; GCN-IR-NEXT: s_sub_i32 s12, 63, s12
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[10:11], s12 ; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[10:11], s12
; GCN-IR-NEXT: s_cbranch_vccz BB9_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB9_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[18:19], s[10:11], s18 ; GCN-IR-NEXT: s_lshr_b64 s[18:19], s[10:11], s18
; GCN-IR-NEXT: s_add_u32 s20, s6, -1 ; GCN-IR-NEXT: s_add_u32 s20, s6, -1
; GCN-IR-NEXT: s_addc_u32 s21, s7, -1 ; GCN-IR-NEXT: s_addc_u32 s21, s7, -1
; GCN-IR-NEXT: s_not_b64 s[8:9], s[14:15] ; GCN-IR-NEXT: s_not_b64 s[8:9], s[14:15]
; GCN-IR-NEXT: s_add_u32 s10, s8, s16 ; GCN-IR-NEXT: s_add_u32 s10, s8, s16
; GCN-IR-NEXT: s_mov_b32 s17, s15 ; GCN-IR-NEXT: s_mov_b32 s17, s15
; GCN-IR-NEXT: s_addc_u32 s11, s9, s15 ; GCN-IR-NEXT: s_addc_u32 s11, s9, s15
; GCN-IR-NEXT: s_mov_b64 s[14:15], 0 ; GCN-IR-NEXT: s_mov_b64 s[14:15], 0
; GCN-IR-NEXT: s_mov_b32 s9, 0 ; GCN-IR-NEXT: s_mov_b32 s9, 0
; GCN-IR-NEXT: BB9_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB9_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[16:17], s[18:19], 1 ; GCN-IR-NEXT: s_lshl_b64 s[16:17], s[18:19], 1
; GCN-IR-NEXT: s_lshr_b32 s8, s13, 31 ; GCN-IR-NEXT: s_lshr_b32 s8, s13, 31
; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1 ; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1
; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[8:9] ; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[8:9]
; GCN-IR-NEXT: s_or_b64 s[12:13], s[14:15], s[12:13] ; GCN-IR-NEXT: s_or_b64 s[12:13], s[14:15], s[12:13]
; GCN-IR-NEXT: s_sub_u32 s8, s20, s16 ; GCN-IR-NEXT: s_sub_u32 s8, s20, s16
; GCN-IR-NEXT: s_subb_u32 s8, s21, s17 ; GCN-IR-NEXT: s_subb_u32 s8, s21, s17
; GCN-IR-NEXT: s_ashr_i32 s14, s8, 31 ; GCN-IR-NEXT: s_ashr_i32 s14, s8, 31
; GCN-IR-NEXT: s_mov_b32 s15, s14 ; GCN-IR-NEXT: s_mov_b32 s15, s14
; GCN-IR-NEXT: s_and_b32 s8, s14, 1 ; GCN-IR-NEXT: s_and_b32 s8, s14, 1
; GCN-IR-NEXT: s_and_b64 s[18:19], s[14:15], s[6:7] ; GCN-IR-NEXT: s_and_b64 s[18:19], s[14:15], s[6:7]
; GCN-IR-NEXT: s_sub_u32 s18, s16, s18 ; GCN-IR-NEXT: s_sub_u32 s18, s16, s18
; GCN-IR-NEXT: v_mov_b32_e32 v0, s10 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s10
; GCN-IR-NEXT: s_subb_u32 s19, s17, s19 ; GCN-IR-NEXT: s_subb_u32 s19, s17, s19
; GCN-IR-NEXT: v_mov_b32_e32 v1, s11 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s11
; GCN-IR-NEXT: s_add_u32 s10, s10, 1 ; GCN-IR-NEXT: s_add_u32 s10, s10, 1
; GCN-IR-NEXT: s_addc_u32 s11, s11, 0 ; GCN-IR-NEXT: s_addc_u32 s11, s11, 0
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
; GCN-IR-NEXT: s_mov_b64 s[14:15], s[8:9] ; GCN-IR-NEXT: s_mov_b64 s[14:15], s[8:9]
; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_cbranch_vccz BB9_3 ; GCN-IR-NEXT: s_cbranch_vccz .LBB9_3
; GCN-IR-NEXT: BB9_4: ; %Flow3 ; GCN-IR-NEXT: .LBB9_4: ; %Flow3
; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[12:13], 1 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[12:13], 1
; GCN-IR-NEXT: s_or_b64 s[6:7], s[8:9], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[6:7], s[8:9], s[6:7]
; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
; GCN-IR-NEXT: v_mov_b32_e32 v1, s7 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s7
; GCN-IR-NEXT: s_branch BB9_6 ; GCN-IR-NEXT: s_branch .LBB9_6
; GCN-IR-NEXT: BB9_5: ; GCN-IR-NEXT: .LBB9_5:
; GCN-IR-NEXT: v_mov_b32_e32 v0, s11 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s11
; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[18:19] ; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[18:19]
; GCN-IR-NEXT: v_mov_b32_e32 v0, s10 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s10
; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[18:19] ; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[18:19]
; GCN-IR-NEXT: BB9_6: ; %udiv-end ; GCN-IR-NEXT: .LBB9_6: ; %udiv-end
; GCN-IR-NEXT: s_xor_b64 s[0:1], s[2:3], s[0:1] ; GCN-IR-NEXT: s_xor_b64 s[0:1], s[2:3], s[0:1]
; GCN-IR-NEXT: v_xor_b32_e32 v0, s0, v0 ; GCN-IR-NEXT: v_xor_b32_e32 v0, s0, v0
; GCN-IR-NEXT: v_xor_b32_e32 v1, s1, v1 ; GCN-IR-NEXT: v_xor_b32_e32 v1, s1, v1
; GCN-IR-NEXT: v_mov_b32_e32 v2, s1 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s1
; GCN-IR-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0 ; GCN-IR-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: s_mov_b32 s6, -1
▲ Show 20 Lines • Show All 142 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[12:13], s[2:3], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[12:13], s[2:3], 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[14:15], s[10:11], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[14:15], s[10:11], 63
; GCN-IR-NEXT: s_mov_b64 s[6:7], 0 ; GCN-IR-NEXT: s_mov_b64 s[6:7], 0
; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[14:15] ; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[14:15]
; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[14:15], s[10:11], 63 ; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[14:15], s[10:11], 63
; GCN-IR-NEXT: s_xor_b64 s[16:17], s[12:13], -1 ; GCN-IR-NEXT: s_xor_b64 s[16:17], s[12:13], -1
; GCN-IR-NEXT: s_and_b64 s[14:15], s[16:17], s[14:15] ; GCN-IR-NEXT: s_and_b64 s[14:15], s[16:17], s[14:15]
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[14:15] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[14:15]
; GCN-IR-NEXT: s_cbranch_vccz BB10_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB10_5
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s12, s10, 1 ; GCN-IR-NEXT: s_add_u32 s12, s10, 1
; GCN-IR-NEXT: v_mov_b32_e32 v0, s10 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s10
; GCN-IR-NEXT: s_addc_u32 s13, s11, 0 ; GCN-IR-NEXT: s_addc_u32 s13, s11, 0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s11 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s11
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[12:13], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[12:13], v[0:1]
; GCN-IR-NEXT: s_sub_i32 s9, 63, s10 ; GCN-IR-NEXT: s_sub_i32 s9, 63, s10
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_lshl_b64 s[10:11], 24, s9 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], 24, s9
; GCN-IR-NEXT: s_cbranch_vccz BB10_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB10_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[14:15], 24, s12 ; GCN-IR-NEXT: s_lshr_b64 s[14:15], 24, s12
; GCN-IR-NEXT: s_add_u32 s16, s2, -1 ; GCN-IR-NEXT: s_add_u32 s16, s2, -1
; GCN-IR-NEXT: s_addc_u32 s17, s3, -1 ; GCN-IR-NEXT: s_addc_u32 s17, s3, -1
; GCN-IR-NEXT: s_sub_u32 s8, 58, s8 ; GCN-IR-NEXT: s_sub_u32 s8, 58, s8
; GCN-IR-NEXT: s_subb_u32 s9, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s9, 0, 0
; GCN-IR-NEXT: s_mov_b64 s[12:13], 0 ; GCN-IR-NEXT: s_mov_b64 s[12:13], 0
; GCN-IR-NEXT: s_mov_b32 s7, 0 ; GCN-IR-NEXT: s_mov_b32 s7, 0
; GCN-IR-NEXT: BB10_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB10_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[14:15], s[14:15], 1 ; GCN-IR-NEXT: s_lshl_b64 s[14:15], s[14:15], 1
; GCN-IR-NEXT: s_lshr_b32 s6, s11, 31 ; GCN-IR-NEXT: s_lshr_b32 s6, s11, 31
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1
; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[6:7]
; GCN-IR-NEXT: s_or_b64 s[10:11], s[12:13], s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[12:13], s[10:11]
; GCN-IR-NEXT: s_sub_u32 s6, s16, s14 ; GCN-IR-NEXT: s_sub_u32 s6, s16, s14
; GCN-IR-NEXT: s_subb_u32 s6, s17, s15 ; GCN-IR-NEXT: s_subb_u32 s6, s17, s15
; GCN-IR-NEXT: s_ashr_i32 s12, s6, 31 ; GCN-IR-NEXT: s_ashr_i32 s12, s6, 31
; GCN-IR-NEXT: s_mov_b32 s13, s12 ; GCN-IR-NEXT: s_mov_b32 s13, s12
; GCN-IR-NEXT: s_and_b32 s6, s12, 1 ; GCN-IR-NEXT: s_and_b32 s6, s12, 1
; GCN-IR-NEXT: s_and_b64 s[18:19], s[12:13], s[2:3] ; GCN-IR-NEXT: s_and_b64 s[18:19], s[12:13], s[2:3]
; GCN-IR-NEXT: s_sub_u32 s14, s14, s18 ; GCN-IR-NEXT: s_sub_u32 s14, s14, s18
; GCN-IR-NEXT: v_mov_b32_e32 v0, s8 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s8
; GCN-IR-NEXT: s_subb_u32 s15, s15, s19 ; GCN-IR-NEXT: s_subb_u32 s15, s15, s19
; GCN-IR-NEXT: v_mov_b32_e32 v1, s9 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s9
; GCN-IR-NEXT: s_add_u32 s8, s8, 1 ; GCN-IR-NEXT: s_add_u32 s8, s8, 1
; GCN-IR-NEXT: s_addc_u32 s9, s9, 0 ; GCN-IR-NEXT: s_addc_u32 s9, s9, 0
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
; GCN-IR-NEXT: s_mov_b64 s[12:13], s[6:7] ; GCN-IR-NEXT: s_mov_b64 s[12:13], s[6:7]
; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_cbranch_vccz BB10_3 ; GCN-IR-NEXT: s_cbranch_vccz .LBB10_3
; GCN-IR-NEXT: BB10_4: ; %Flow5 ; GCN-IR-NEXT: .LBB10_4: ; %Flow5
; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[10:11], 1 ; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[10:11], 1
; GCN-IR-NEXT: s_or_b64 s[2:3], s[6:7], s[2:3] ; GCN-IR-NEXT: s_or_b64 s[2:3], s[6:7], s[2:3]
; GCN-IR-NEXT: v_mov_b32_e32 v0, s2 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s2
; GCN-IR-NEXT: v_mov_b32_e32 v1, s3 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s3
; GCN-IR-NEXT: s_branch BB10_6 ; GCN-IR-NEXT: s_branch .LBB10_6
; GCN-IR-NEXT: BB10_5: ; GCN-IR-NEXT: .LBB10_5:
; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
; GCN-IR-NEXT: v_cndmask_b32_e64 v0, 24, 0, s[12:13] ; GCN-IR-NEXT: v_cndmask_b32_e64 v0, 24, 0, s[12:13]
; GCN-IR-NEXT: BB10_6: ; %udiv-end ; GCN-IR-NEXT: .LBB10_6: ; %udiv-end
; GCN-IR-NEXT: v_xor_b32_e32 v0, s4, v0 ; GCN-IR-NEXT: v_xor_b32_e32 v0, s4, v0
; GCN-IR-NEXT: v_xor_b32_e32 v1, s5, v1 ; GCN-IR-NEXT: v_xor_b32_e32 v1, s5, v1
; GCN-IR-NEXT: v_mov_b32_e32 v2, s5 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s5
; GCN-IR-NEXT: v_subrev_i32_e32 v0, vcc, s4, v0 ; GCN-IR-NEXT: v_subrev_i32_e32 v0, vcc, s4, v0
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: s_mov_b32 s2, -1
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
▲ Show 20 Lines • Show All 133 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5]
; GCN-IR-NEXT: v_cndmask_b32_e64 v6, 24, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v6, 24, 0, s[4:5]
; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1
; GCN-IR-NEXT: v_mov_b32_e32 v3, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v3, v2
; GCN-IR-NEXT: v_mov_b32_e32 v7, v9 ; GCN-IR-NEXT: v_mov_b32_e32 v7, v9
; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB11_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB11_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v4 ; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v4
; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v5, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[10:11], v[4:5] ; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[10:11], v[4:5]
; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v4 ; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v4
; GCN-IR-NEXT: v_lshl_b64 v[4:5], 24, v4 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], 24, v4
; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB11_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB11_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, -1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, -1, v0
; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, -1, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, -1, v1, vcc
; GCN-IR-NEXT: v_lshr_b64 v[10:11], 24, v10 ; GCN-IR-NEXT: v_lshr_b64 v[10:11], 24, v10
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, 58, v8 ; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, 58, v8
; GCN-IR-NEXT: v_mov_b32_e32 v12, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v12, 0
; GCN-IR-NEXT: v_subb_u32_e32 v9, vcc, 0, v9, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v9, vcc, 0, v9, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v13, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v13, 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: BB11_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB11_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1 ; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5
; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6 ; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v14, v10 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v14, v10
; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v15, v11, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v15, v11, vcc
; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4 ; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4
; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v6 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v6
; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v12 ; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v12
; GCN-IR-NEXT: v_and_b32_e32 v16, v12, v1 ; GCN-IR-NEXT: v_and_b32_e32 v16, v12, v1
; GCN-IR-NEXT: v_and_b32_e32 v17, v12, v0 ; GCN-IR-NEXT: v_and_b32_e32 v17, v12, v0
; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v8 ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v8
; GCN-IR-NEXT: v_or_b32_e32 v5, v13, v5 ; GCN-IR-NEXT: v_or_b32_e32 v5, v13, v5
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v9, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v9, vcc
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9]
; GCN-IR-NEXT: v_mov_b32_e32 v8, v12 ; GCN-IR-NEXT: v_mov_b32_e32 v8, v12
; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v10, v17 ; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v10, v17
; GCN-IR-NEXT: v_mov_b32_e32 v9, v13 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v13
; GCN-IR-NEXT: v_mov_b32_e32 v13, v7 ; GCN-IR-NEXT: v_mov_b32_e32 v13, v7
; GCN-IR-NEXT: v_subb_u32_e64 v11, s[4:5], v11, v16, s[4:5] ; GCN-IR-NEXT: v_subb_u32_e64 v11, s[4:5], v11, v16, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v12, v6 ; GCN-IR-NEXT: v_mov_b32_e32 v12, v6
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execnz BB11_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB11_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: BB11_5: ; %Flow3 ; GCN-IR-NEXT: .LBB11_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[4:5], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[4:5], 1
; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v1 ; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v1
; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v0 ; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v0
; GCN-IR-NEXT: BB11_6: ; %Flow4 ; GCN-IR-NEXT: .LBB11_6: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_xor_b32_e32 v0, v6, v2 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v6, v2
; GCN-IR-NEXT: v_xor_b32_e32 v1, v7, v3 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v7, v3
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
; GCN-IR-NEXT: s_setpc_b64 s[30:31] ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = sdiv i64 24, %x %result = sdiv i64 24, %x
ret i64 %result ret i64 %result
▲ Show 20 Lines • Show All 132 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[4:5]
; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1
; GCN-IR-NEXT: v_mov_b32_e32 v3, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v3, v2
; GCN-IR-NEXT: v_mov_b32_e32 v7, v9 ; GCN-IR-NEXT: v_mov_b32_e32 v7, v9
; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB12_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB12_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v4 ; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v4
; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v5, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[10:11], v[4:5] ; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[10:11], v[4:5]
; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v4 ; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v4
; GCN-IR-NEXT: v_lshl_b64 v[4:5], s[8:9], v4 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], s[8:9], v4
; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB12_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB12_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, -1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, -1, v0
; GCN-IR-NEXT: s_mov_b64 s[4:5], 0x8000 ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0x8000
; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, -1, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, -1, v1, vcc
; GCN-IR-NEXT: v_lshr_b64 v[10:11], s[4:5], v10 ; GCN-IR-NEXT: v_lshr_b64 v[10:11], s[4:5], v10
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, 47, v8 ; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, 47, v8
; GCN-IR-NEXT: v_mov_b32_e32 v12, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v12, 0
; GCN-IR-NEXT: v_subb_u32_e32 v9, vcc, 0, v9, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v9, vcc, 0, v9, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v13, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v13, 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: BB12_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB12_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1 ; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5
; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6 ; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v14, v10 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v14, v10
; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v15, v11, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v15, v11, vcc
; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4 ; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4
; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v6 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v6
; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v12 ; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v12
; GCN-IR-NEXT: v_and_b32_e32 v16, v12, v1 ; GCN-IR-NEXT: v_and_b32_e32 v16, v12, v1
; GCN-IR-NEXT: v_and_b32_e32 v17, v12, v0 ; GCN-IR-NEXT: v_and_b32_e32 v17, v12, v0
; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v8 ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v8
; GCN-IR-NEXT: v_or_b32_e32 v5, v13, v5 ; GCN-IR-NEXT: v_or_b32_e32 v5, v13, v5
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v9, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v9, vcc
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9]
; GCN-IR-NEXT: v_mov_b32_e32 v8, v12 ; GCN-IR-NEXT: v_mov_b32_e32 v8, v12
; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v10, v17 ; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v10, v17
; GCN-IR-NEXT: v_mov_b32_e32 v9, v13 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v13
; GCN-IR-NEXT: v_mov_b32_e32 v13, v7 ; GCN-IR-NEXT: v_mov_b32_e32 v13, v7
; GCN-IR-NEXT: v_subb_u32_e64 v11, s[4:5], v11, v16, s[4:5] ; GCN-IR-NEXT: v_subb_u32_e64 v11, s[4:5], v11, v16, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v12, v6 ; GCN-IR-NEXT: v_mov_b32_e32 v12, v6
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execnz BB12_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB12_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: BB12_5: ; %Flow3 ; GCN-IR-NEXT: .LBB12_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[4:5], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[4:5], 1
; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v1 ; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v1
; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v0 ; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v0
; GCN-IR-NEXT: BB12_6: ; %Flow4 ; GCN-IR-NEXT: .LBB12_6: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_xor_b32_e32 v0, v6, v2 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v6, v2
; GCN-IR-NEXT: v_xor_b32_e32 v1, v7, v3 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v7, v3
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
; GCN-IR-NEXT: s_setpc_b64 s[30:31] ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = sdiv i64 32768, %x %result = sdiv i64 32768, %x
ret i64 %result ret i64 %result
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; GCN-IR-NEXT: v_mov_b32_e32 v1, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v1, v2
; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[3:4] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[3:4]
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v8, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v8, 0, s[4:5]
; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v7, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v7, 0, s[4:5]
; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB13_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB13_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v3 ; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v3
; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v4, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v4, vcc
; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[9:10], v[3:4] ; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[9:10], v[3:4]
; GCN-IR-NEXT: v_sub_i32_e64 v3, s[4:5], 63, v3 ; GCN-IR-NEXT: v_sub_i32_e64 v3, s[4:5], 63, v3
; GCN-IR-NEXT: v_lshl_b64 v[3:4], v[7:8], v3 ; GCN-IR-NEXT: v_lshl_b64 v[3:4], v[7:8], v3
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB13_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB13_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_lshr_b64 v[9:10], v[7:8], v9 ; GCN-IR-NEXT: v_lshr_b64 v[9:10], v[7:8], v9
; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 0xffffffcf, v0 ; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 0xffffffcf, v0
; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
; GCN-IR-NEXT: v_addc_u32_e64 v8, s[4:5], 0, -1, vcc ; GCN-IR-NEXT: v_addc_u32_e64 v8, s[4:5], 0, -1, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v12, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v12, 0
; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff ; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff
; GCN-IR-NEXT: BB13_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB13_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[9:10], v[9:10], 1 ; GCN-IR-NEXT: v_lshl_b64 v[9:10], v[9:10], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 31, v4 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 31, v4
; GCN-IR-NEXT: v_or_b32_e32 v0, v9, v0 ; GCN-IR-NEXT: v_or_b32_e32 v0, v9, v0
; GCN-IR-NEXT: v_lshl_b64 v[3:4], v[3:4], 1 ; GCN-IR-NEXT: v_lshl_b64 v[3:4], v[3:4], 1
; GCN-IR-NEXT: v_sub_i32_e32 v5, vcc, s12, v0 ; GCN-IR-NEXT: v_sub_i32_e32 v5, vcc, s12, v0
; GCN-IR-NEXT: v_subb_u32_e32 v5, vcc, 0, v10, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v5, vcc, 0, v10, vcc
; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3 ; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3
; GCN-IR-NEXT: v_add_i32_e32 v11, vcc, 1, v7 ; GCN-IR-NEXT: v_add_i32_e32 v11, vcc, 1, v7
; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4 ; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4
; GCN-IR-NEXT: v_ashrrev_i32_e32 v9, 31, v5 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v9, 31, v5
; GCN-IR-NEXT: v_addc_u32_e32 v12, vcc, 0, v8, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v12, vcc, 0, v8, vcc
; GCN-IR-NEXT: v_and_b32_e32 v5, 1, v9 ; GCN-IR-NEXT: v_and_b32_e32 v5, 1, v9
; GCN-IR-NEXT: v_and_b32_e32 v9, 0x8000, v9 ; GCN-IR-NEXT: v_and_b32_e32 v9, 0x8000, v9
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[11:12], v[7:8] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[11:12], v[7:8]
; GCN-IR-NEXT: v_mov_b32_e32 v7, v11 ; GCN-IR-NEXT: v_mov_b32_e32 v7, v11
; GCN-IR-NEXT: v_sub_i32_e64 v9, s[4:5], v0, v9 ; GCN-IR-NEXT: v_sub_i32_e64 v9, s[4:5], v0, v9
; GCN-IR-NEXT: v_mov_b32_e32 v8, v12 ; GCN-IR-NEXT: v_mov_b32_e32 v8, v12
; GCN-IR-NEXT: v_mov_b32_e32 v12, v6 ; GCN-IR-NEXT: v_mov_b32_e32 v12, v6
; GCN-IR-NEXT: v_subbrev_u32_e64 v10, s[4:5], 0, v10, s[4:5] ; GCN-IR-NEXT: v_subbrev_u32_e64 v10, s[4:5], 0, v10, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v11, v5 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v5
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execnz BB13_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB13_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: BB13_5: ; %Flow3 ; GCN-IR-NEXT: .LBB13_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: v_lshl_b64 v[3:4], v[3:4], 1 ; GCN-IR-NEXT: v_lshl_b64 v[3:4], v[3:4], 1
; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v4 ; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v4
; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v3 ; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v3
; GCN-IR-NEXT: BB13_6: ; %Flow4 ; GCN-IR-NEXT: .LBB13_6: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_xor_b32_e32 v0, v5, v2 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v5, v2
; GCN-IR-NEXT: v_xor_b32_e32 v3, v6, v1 ; GCN-IR-NEXT: v_xor_b32_e32 v3, v6, v1
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc
; GCN-IR-NEXT: s_setpc_b64 s[30:31] ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = sdiv i64 %x, 32768 %result = sdiv i64 %x, 32768
ret i64 %result ret i64 %result
▲ Show 20 Lines • Show All 243 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll

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define amdgpu_kernel void @sgpr_if_else_salu_br(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) { define amdgpu_kernel void @sgpr_if_else_salu_br(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
; SI-LABEL: sgpr_if_else_salu_br: ; SI-LABEL: sgpr_if_else_salu_br:
; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; SI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xb ; SI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xb
; SI-NEXT: s_load_dword s0, s[0:1], 0xf ; SI-NEXT: s_load_dword s0, s[0:1], 0xf
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_cmp_lg_u32 s8, 0 ; SI-NEXT: s_cmp_lg_u32 s8, 0
; SI-NEXT: s_cbranch_scc0 BB0_2 ; SI-NEXT: s_cbranch_scc0 .LBB0_2
; SI-NEXT: ; %bb.1: ; %else ; SI-NEXT: ; %bb.1: ; %else
; SI-NEXT: s_add_i32 s2, s11, s0 ; SI-NEXT: s_add_i32 s2, s11, s0
; SI-NEXT: s_cbranch_execz BB0_3 ; SI-NEXT: s_cbranch_execz .LBB0_3
; SI-NEXT: s_branch BB0_4 ; SI-NEXT: s_branch .LBB0_4
; SI-NEXT: BB0_2: ; SI-NEXT: .LBB0_2:
; SI-NEXT: ; implicit-def: $sgpr2 ; SI-NEXT: ; implicit-def: $sgpr2
; SI-NEXT: BB0_3: ; %if ; SI-NEXT: .LBB0_3: ; %if
; SI-NEXT: s_sub_i32 s2, s9, s10 ; SI-NEXT: s_sub_i32 s2, s9, s10
; SI-NEXT: BB0_4: ; %endif ; SI-NEXT: .LBB0_4: ; %endif
; SI-NEXT: s_add_i32 s0, s2, s8 ; SI-NEXT: s_add_i32 s0, s2, s8
; SI-NEXT: s_mov_b32 s7, 0xf000 ; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1 ; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: v_mov_b32_e32 v0, s0 ; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
entry: entry:
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define amdgpu_kernel void @sgpr_if_else_salu_br_opt(i32 addrspace(1)* %out, [8 x i32], i32 %a, [8 x i32], i32 %b, [8 x i32], i32 %c, [8 x i32], i32 %d, [8 x i32], i32 %e) { define amdgpu_kernel void @sgpr_if_else_salu_br_opt(i32 addrspace(1)* %out, [8 x i32], i32 %a, [8 x i32], i32 %b, [8 x i32], i32 %c, [8 x i32], i32 %d, [8 x i32], i32 %e) {
; SI-LABEL: sgpr_if_else_salu_br_opt: ; SI-LABEL: sgpr_if_else_salu_br_opt:
; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dword s6, s[0:1], 0x13 ; SI-NEXT: s_load_dword s6, s[0:1], 0x13
; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_cmp_lg_u32 s6, 0 ; SI-NEXT: s_cmp_lg_u32 s6, 0
; SI-NEXT: s_cbranch_scc0 BB1_2 ; SI-NEXT: s_cbranch_scc0 .LBB1_2
; SI-NEXT: ; %bb.1: ; %else ; SI-NEXT: ; %bb.1: ; %else
; SI-NEXT: s_load_dword s2, s[0:1], 0x2e ; SI-NEXT: s_load_dword s2, s[0:1], 0x2e
; SI-NEXT: s_load_dword s3, s[0:1], 0x37 ; SI-NEXT: s_load_dword s3, s[0:1], 0x37
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_add_i32 s7, s2, s3 ; SI-NEXT: s_add_i32 s7, s2, s3
; SI-NEXT: s_cbranch_execz BB1_3 ; SI-NEXT: s_cbranch_execz .LBB1_3
; SI-NEXT: s_branch BB1_4 ; SI-NEXT: s_branch .LBB1_4
; SI-NEXT: BB1_2: ; SI-NEXT: .LBB1_2:
; SI-NEXT: ; implicit-def: $sgpr7 ; SI-NEXT: ; implicit-def: $sgpr7
; SI-NEXT: BB1_3: ; %if ; SI-NEXT: .LBB1_3: ; %if
; SI-NEXT: s_load_dword s2, s[0:1], 0x1c ; SI-NEXT: s_load_dword s2, s[0:1], 0x1c
; SI-NEXT: s_load_dword s0, s[0:1], 0x25 ; SI-NEXT: s_load_dword s0, s[0:1], 0x25
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_add_i32 s7, s2, s0 ; SI-NEXT: s_add_i32 s7, s2, s0
; SI-NEXT: BB1_4: ; %endif ; SI-NEXT: .LBB1_4: ; %endif
; SI-NEXT: s_add_i32 s0, s7, s6 ; SI-NEXT: s_add_i32 s0, s7, s6
; SI-NEXT: s_mov_b32 s7, 0xf000 ; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1 ; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: v_mov_b32_e32 v0, s0 ; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
entry: entry:
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; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: v_cvt_f32_u32_e32 v0, v0 ; SI-NEXT: v_cvt_f32_u32_e32 v0, v0
; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xc ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xc
; SI-NEXT: ; implicit-def: $sgpr8 ; SI-NEXT: ; implicit-def: $sgpr8
; SI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v0 ; SI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v0
; SI-NEXT: s_and_saveexec_b64 s[6:7], vcc ; SI-NEXT: s_and_saveexec_b64 s[6:7], vcc
; SI-NEXT: s_xor_b64 s[6:7], exec, s[6:7] ; SI-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
; SI-NEXT: s_cbranch_execz BB2_2 ; SI-NEXT: s_cbranch_execz .LBB2_2
; SI-NEXT: ; %bb.1: ; %else ; SI-NEXT: ; %bb.1: ; %else
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_add_i32 s8, s2, s3 ; SI-NEXT: s_add_i32 s8, s2, s3
; SI-NEXT: BB2_2: ; %Flow ; SI-NEXT: .LBB2_2: ; %Flow
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_or_saveexec_b64 s[2:3], s[6:7] ; SI-NEXT: s_or_saveexec_b64 s[2:3], s[6:7]
; SI-NEXT: v_mov_b32_e32 v0, s8 ; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: s_xor_b64 exec, exec, s[2:3] ; SI-NEXT: s_xor_b64 exec, exec, s[2:3]
; SI-NEXT: ; %bb.3: ; %if ; SI-NEXT: ; %bb.3: ; %if
; SI-NEXT: s_add_i32 s0, s0, s1 ; SI-NEXT: s_add_i32 s0, s0, s1
; SI-NEXT: v_mov_b32_e32 v0, s0 ; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: ; %bb.4: ; %endif ; SI-NEXT: ; %bb.4: ; %endif
Show All 27 Lines
; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
; SI-NEXT: s_mov_b32 s2, 0 ; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: ; implicit-def: $sgpr8_sgpr9 ; SI-NEXT: ; implicit-def: $sgpr8_sgpr9
; SI-NEXT: s_and_saveexec_b64 s[10:11], vcc ; SI-NEXT: s_and_saveexec_b64 s[10:11], vcc
; SI-NEXT: s_xor_b64 s[10:11], exec, s[10:11] ; SI-NEXT: s_xor_b64 s[10:11], exec, s[10:11]
; SI-NEXT: s_cbranch_execz BB3_2 ; SI-NEXT: s_cbranch_execz .LBB3_2
; SI-NEXT: ; %bb.1: ; %else ; SI-NEXT: ; %bb.1: ; %else
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SI-NEXT: v_mov_b32_e32 v1, 0 ; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 ; SI-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v0 ; SI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v0
; SI-NEXT: s_and_b64 s[8:9], vcc, exec ; SI-NEXT: s_and_b64 s[8:9], vcc, exec
; SI-NEXT: ; implicit-def: $vgpr0 ; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: BB3_2: ; %Flow ; SI-NEXT: .LBB3_2: ; %Flow
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_or_saveexec_b64 s[0:1], s[10:11] ; SI-NEXT: s_or_saveexec_b64 s[0:1], s[10:11]
; SI-NEXT: s_xor_b64 exec, exec, s[0:1] ; SI-NEXT: s_xor_b64 exec, exec, s[0:1]
; SI-NEXT: s_cbranch_execz BB3_4 ; SI-NEXT: s_cbranch_execz .LBB3_4
; SI-NEXT: ; %bb.3: ; %if ; SI-NEXT: ; %bb.3: ; %if
; SI-NEXT: s_mov_b32 s15, 0xf000 ; SI-NEXT: s_mov_b32 s15, 0xf000
; SI-NEXT: s_mov_b32 s14, 0 ; SI-NEXT: s_mov_b32 s14, 0
; SI-NEXT: s_mov_b64 s[12:13], s[6:7] ; SI-NEXT: s_mov_b64 s[12:13], s[6:7]
; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SI-NEXT: v_mov_b32_e32 v1, 0 ; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: buffer_load_dword v0, v[0:1], s[12:15], 0 addr64 ; SI-NEXT: buffer_load_dword v0, v[0:1], s[12:15], 0 addr64
; SI-NEXT: s_andn2_b64 s[2:3], s[8:9], exec ; SI-NEXT: s_andn2_b64 s[2:3], s[8:9], exec
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; SI-NEXT: s_and_b64 s[6:7], vcc, exec ; SI-NEXT: s_and_b64 s[6:7], vcc, exec
; SI-NEXT: s_or_b64 s[8:9], s[2:3], s[6:7] ; SI-NEXT: s_or_b64 s[8:9], s[2:3], s[6:7]
; SI-NEXT: BB3_4: ; %endif ; SI-NEXT: .LBB3_4: ; %endif
; SI-NEXT: s_or_b64 exec, exec, s[0:1] ; SI-NEXT: s_or_b64 exec, exec, s[0:1]
; SI-NEXT: s_mov_b32 s7, 0xf000 ; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1 ; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[8:9] ; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[8:9]
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0
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llvm/test/CodeGen/AMDGPU/sgpr-copy.ll

Show First 20 Lines • Show All 309 Lines • ▼ Show 20 LinesENDIF69: ; preds = %LOOP68
br label %LOOP68 br label %LOOP68
} }
; This test checks that image_sample resource descriptors aren't loaded into ; This test checks that image_sample resource descriptors aren't loaded into
; vgprs. The verifier will fail if this happens. ; vgprs. The verifier will fail if this happens.
; CHECK-LABEL:{{^}}sample_rsrc ; CHECK-LABEL:{{^}}sample_rsrc
; CHECK: s_cmp_eq_u32 ; CHECK: s_cmp_eq_u32
; CHECK: s_cbranch_scc0 [[END:BB[0-9]+_[0-9]+]] ; CHECK: s_cbranch_scc0 [[END:.LBB[0-9]+_[0-9]+]]
; CHECK: v_add_{{[iu]}}32_e32 v[[ADD:[0-9]+]], vcc, 1, v{{[0-9]+}} ; CHECK: v_add_{{[iu]}}32_e32 v[[ADD:[0-9]+]], vcc, 1, v{{[0-9]+}}
; [[END]]: ; [[END]]:
; CHECK: image_sample v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+}}:[[ADD]]{{\]}} ; CHECK: image_sample v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+}}:[[ADD]]{{\]}}
; CHECK: s_endpgm ; CHECK: s_endpgm
define amdgpu_ps void @sample_rsrc([6 x <4 x i32>] addrspace(4)* inreg %arg, [17 x <4 x i32>] addrspace(4)* inreg %arg1, [16 x <4 x i32>] addrspace(4)* inreg %arg2, [32 x <8 x i32>] addrspace(4)* inreg %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 { define amdgpu_ps void @sample_rsrc([6 x <4 x i32>] addrspace(4)* inreg %arg, [17 x <4 x i32>] addrspace(4)* inreg %arg1, [16 x <4 x i32>] addrspace(4)* inreg %arg2, [32 x <8 x i32>] addrspace(4)* inreg %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 {
bb: bb:
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llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll

Show First 20 Lines • Show All 105 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_writelane_b32 v0, s7, 1 ; GCN-NEXT: v_writelane_b32 v0, s7, 1
; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4 ; 4-byte Folded Spill
; GCN-NEXT: buffer_load_dword v0, off, s[0:3], 0 ; GCN-NEXT: buffer_load_dword v0, off, s[0:3], 0
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_mov_b64 exec, s[8:9] ; GCN-NEXT: s_mov_b64 exec, s[8:9]
; GCN-NEXT: s_mov_b32 s5, 0 ; GCN-NEXT: s_mov_b32 s5, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_cmp_lg_u32 s4, s5 ; GCN-NEXT: s_cmp_lg_u32 s4, s5
; GCN-NEXT: s_cbranch_scc1 BB0_2 ; GCN-NEXT: s_cbranch_scc1 .LBB0_2
; GCN-NEXT: ; %bb.1: ; %bb0 ; GCN-NEXT: ; %bb.1: ; %bb0
; GCN-NEXT: v_readlane_b32 s4, v23, 0 ; GCN-NEXT: v_readlane_b32 s4, v23, 0
; GCN-NEXT: v_readlane_b32 s5, v23, 1 ; GCN-NEXT: v_readlane_b32 s5, v23, 1
; GCN-NEXT: v_readlane_b32 s6, v23, 2 ; GCN-NEXT: v_readlane_b32 s6, v23, 2
; GCN-NEXT: v_readlane_b32 s7, v23, 3 ; GCN-NEXT: v_readlane_b32 s7, v23, 3
; GCN-NEXT: v_readlane_b32 s8, v23, 4 ; GCN-NEXT: v_readlane_b32 s8, v23, 4
; GCN-NEXT: v_readlane_b32 s9, v23, 5 ; GCN-NEXT: v_readlane_b32 s9, v23, 5
; GCN-NEXT: v_readlane_b32 s10, v23, 6 ; GCN-NEXT: v_readlane_b32 s10, v23, 6
▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Lines
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_mov_b64 exec, s[6:7] ; GCN-NEXT: s_mov_b64 exec, s[6:7]
; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: ;;#ASMSTART
; GCN-NEXT: ; use s[8:23] ; GCN-NEXT: ; use s[8:23]
; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: ;;#ASMEND
; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: ;;#ASMSTART
; GCN-NEXT: ; use s[4:5] ; GCN-NEXT: ; use s[4:5]
; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: ;;#ASMEND
; GCN-NEXT: BB0_2: ; %ret ; GCN-NEXT: .LBB0_2: ; %ret
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
call void asm sideeffect "", "~{v[0:7]}" () #0 call void asm sideeffect "", "~{v[0:7]}" () #0
call void asm sideeffect "", "~{v[8:15]}" () #0 call void asm sideeffect "", "~{v[8:15]}" () #0
call void asm sideeffect "", "~{v[16:19]}"() #0 call void asm sideeffect "", "~{v[16:19]}"() #0
call void asm sideeffect "", "~{v[20:21]}"() #0 call void asm sideeffect "", "~{v[20:21]}"() #0
call void asm sideeffect "", "~{v22}"() #0 call void asm sideeffect "", "~{v22}"() #0
%wide.sgpr0 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0 %wide.sgpr0 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0
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llvm/test/CodeGen/AMDGPU/si-annotate-cf-kill.ll

Show All 13 Lines
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc ; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: ; %bb.1: ; %if1 ; SI-NEXT: ; %bb.1: ; %if1
; SI-NEXT: s_xor_b64 s[2:3], exec, -1 ; SI-NEXT: s_xor_b64 s[2:3], exec, -1
; SI-NEXT: ; %bb.2: ; %endif1 ; SI-NEXT: ; %bb.2: ; %endif1
; SI-NEXT: s_or_b64 exec, exec, s[4:5] ; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_wqm_b64 s[4:5], s[2:3] ; SI-NEXT: s_wqm_b64 s[4:5], s[2:3]
; SI-NEXT: s_xor_b64 s[4:5], s[4:5], exec ; SI-NEXT: s_xor_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], s[4:5] ; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], s[4:5]
; SI-NEXT: s_cbranch_scc0 BB0_6 ; SI-NEXT: s_cbranch_scc0 .LBB0_6
; SI-NEXT: ; %bb.3: ; %endif1 ; SI-NEXT: ; %bb.3: ; %endif1
; SI-NEXT: s_and_b64 exec, exec, s[0:1] ; SI-NEXT: s_and_b64 exec, exec, s[0:1]
; SI-NEXT: v_mov_b32_e32 v0, 0 ; SI-NEXT: v_mov_b32_e32 v0, 0
; SI-NEXT: s_and_saveexec_b64 s[0:1], s[2:3] ; SI-NEXT: s_and_saveexec_b64 s[0:1], s[2:3]
; SI-NEXT: s_cbranch_execz BB0_5 ; SI-NEXT: s_cbranch_execz .LBB0_5
; SI-NEXT: ; %bb.4: ; %if2 ; SI-NEXT: ; %bb.4: ; %if2
; SI-NEXT: s_mov_b32 s3, 0 ; SI-NEXT: s_mov_b32 s3, 0
; SI-NEXT: v_add_f32_e32 v0, 1.0, v2 ; SI-NEXT: v_add_f32_e32 v0, 1.0, v2
; SI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0 ; SI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
; SI-NEXT: v_cvt_i32_f32_e32 v0, v0 ; SI-NEXT: v_cvt_i32_f32_e32 v0, v0
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_atomic_swap v0, off, s[4:7], 0 offset:4 glc ; SI-NEXT: buffer_atomic_swap v0, off, s[4:7], 0 offset:4 glc
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT: v_cvt_f32_i32_e32 v0, v0 ; SI-NEXT: v_cvt_f32_i32_e32 v0, v0
; SI-NEXT: BB0_5: ; %endif2 ; SI-NEXT: .LBB0_5: ; %endif2
; SI-NEXT: s_or_b64 exec, exec, s[0:1] ; SI-NEXT: s_or_b64 exec, exec, s[0:1]
; SI-NEXT: s_branch BB0_7 ; SI-NEXT: s_branch .LBB0_7
; SI-NEXT: BB0_6: ; SI-NEXT: .LBB0_6:
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: exp null off, off, off, off done vm ; SI-NEXT: exp null off, off, off, off done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; SI-NEXT: BB0_7: ; SI-NEXT: .LBB0_7:
; ;
; FLAT-LABEL: uniform_kill: ; FLAT-LABEL: uniform_kill:
; FLAT: ; %bb.0: ; %entry ; FLAT: ; %bb.0: ; %entry
; FLAT-NEXT: v_cvt_i32_f32_e32 v0, v0 ; FLAT-NEXT: v_cvt_i32_f32_e32 v0, v0
; FLAT-NEXT: s_mov_b64 s[0:1], exec ; FLAT-NEXT: s_mov_b64 s[0:1], exec
; FLAT-NEXT: s_mov_b64 s[2:3], -1 ; FLAT-NEXT: s_mov_b64 s[2:3], -1
; FLAT-NEXT: v_or_b32_e32 v0, v1, v0 ; FLAT-NEXT: v_or_b32_e32 v0, v1, v0
; FLAT-NEXT: v_and_b32_e32 v0, 1, v0 ; FLAT-NEXT: v_and_b32_e32 v0, 1, v0
; FLAT-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 ; FLAT-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; FLAT-NEXT: s_and_saveexec_b64 s[4:5], vcc ; FLAT-NEXT: s_and_saveexec_b64 s[4:5], vcc
; FLAT-NEXT: ; %bb.1: ; %if1 ; FLAT-NEXT: ; %bb.1: ; %if1
; FLAT-NEXT: s_xor_b64 s[2:3], exec, -1 ; FLAT-NEXT: s_xor_b64 s[2:3], exec, -1
; FLAT-NEXT: ; %bb.2: ; %endif1 ; FLAT-NEXT: ; %bb.2: ; %endif1
; FLAT-NEXT: s_or_b64 exec, exec, s[4:5] ; FLAT-NEXT: s_or_b64 exec, exec, s[4:5]
; FLAT-NEXT: s_wqm_b64 s[4:5], s[2:3] ; FLAT-NEXT: s_wqm_b64 s[4:5], s[2:3]
; FLAT-NEXT: s_xor_b64 s[4:5], s[4:5], exec ; FLAT-NEXT: s_xor_b64 s[4:5], s[4:5], exec
; FLAT-NEXT: s_andn2_b64 s[0:1], s[0:1], s[4:5] ; FLAT-NEXT: s_andn2_b64 s[0:1], s[0:1], s[4:5]
; FLAT-NEXT: s_cbranch_scc0 BB0_6 ; FLAT-NEXT: s_cbranch_scc0 .LBB0_6
; FLAT-NEXT: ; %bb.3: ; %endif1 ; FLAT-NEXT: ; %bb.3: ; %endif1
; FLAT-NEXT: s_and_b64 exec, exec, s[0:1] ; FLAT-NEXT: s_and_b64 exec, exec, s[0:1]
; FLAT-NEXT: v_mov_b32_e32 v0, 0 ; FLAT-NEXT: v_mov_b32_e32 v0, 0
; FLAT-NEXT: s_and_saveexec_b64 s[0:1], s[2:3] ; FLAT-NEXT: s_and_saveexec_b64 s[0:1], s[2:3]
; FLAT-NEXT: s_cbranch_execz BB0_5 ; FLAT-NEXT: s_cbranch_execz .LBB0_5
; FLAT-NEXT: ; %bb.4: ; %if2 ; FLAT-NEXT: ; %bb.4: ; %if2
; FLAT-NEXT: s_mov_b32 s3, 0 ; FLAT-NEXT: s_mov_b32 s3, 0
; FLAT-NEXT: v_add_f32_e32 v0, 1.0, v2 ; FLAT-NEXT: v_add_f32_e32 v0, 1.0, v2
; FLAT-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0 ; FLAT-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
; FLAT-NEXT: v_cvt_i32_f32_e32 v0, v0 ; FLAT-NEXT: v_cvt_i32_f32_e32 v0, v0
; FLAT-NEXT: s_waitcnt lgkmcnt(0) ; FLAT-NEXT: s_waitcnt lgkmcnt(0)
; FLAT-NEXT: buffer_atomic_swap v0, off, s[4:7], 0 offset:4 glc ; FLAT-NEXT: buffer_atomic_swap v0, off, s[4:7], 0 offset:4 glc
; FLAT-NEXT: s_waitcnt vmcnt(0) ; FLAT-NEXT: s_waitcnt vmcnt(0)
; FLAT-NEXT: v_cvt_f32_i32_e32 v0, v0 ; FLAT-NEXT: v_cvt_f32_i32_e32 v0, v0
; FLAT-NEXT: BB0_5: ; %endif2 ; FLAT-NEXT: .LBB0_5: ; %endif2
; FLAT-NEXT: s_or_b64 exec, exec, s[0:1] ; FLAT-NEXT: s_or_b64 exec, exec, s[0:1]
; FLAT-NEXT: s_branch BB0_7 ; FLAT-NEXT: s_branch .LBB0_7
; FLAT-NEXT: BB0_6: ; FLAT-NEXT: .LBB0_6:
; FLAT-NEXT: s_mov_b64 exec, 0 ; FLAT-NEXT: s_mov_b64 exec, 0
; FLAT-NEXT: exp null off, off, off, off done vm ; FLAT-NEXT: exp null off, off, off, off done vm
; FLAT-NEXT: s_endpgm ; FLAT-NEXT: s_endpgm
; FLAT-NEXT: BB0_7: ; FLAT-NEXT: .LBB0_7:
entry: entry:
%.1 = fptosi float %a to i32 %.1 = fptosi float %a to i32
%.2 = or i32 %b, %.1 %.2 = or i32 %b, %.1
%.3 = and i32 %.2, 1 %.3 = and i32 %.2, 1
%.not = icmp eq i32 %.3, 0 %.not = icmp eq i32 %.3, 0
br i1 %.not, label %endif1, label %if1 br i1 %.not, label %endif1, label %if1
if1: if1:
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llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI %s ; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI %s
; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck --check-prefix=FLAT %s ; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck --check-prefix=FLAT %s
define amdgpu_kernel void @break_inserted_outside_of_loop(i32 addrspace(1)* %out, i32 %a) { define amdgpu_kernel void @break_inserted_outside_of_loop(i32 addrspace(1)* %out, i32 %a) {
; SI-LABEL: break_inserted_outside_of_loop: ; SI-LABEL: break_inserted_outside_of_loop:
; SI: ; %bb.0: ; %main_body ; SI: ; %bb.0: ; %main_body
; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; SI-NEXT: s_load_dword s0, s[0:1], 0xb ; SI-NEXT: s_load_dword s0, s[0:1], 0xb
; SI-NEXT: v_mbcnt_lo_u32_b32_e64 v0, -1, 0 ; SI-NEXT: v_mbcnt_lo_u32_b32_e64 v0, -1, 0
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v0, s0, v0 ; SI-NEXT: v_and_b32_e32 v0, s0, v0
; SI-NEXT: v_and_b32_e32 v0, 1, v0 ; SI-NEXT: v_and_b32_e32 v0, 1, v0
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 ; SI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; SI-NEXT: s_mov_b64 s[0:1], 0 ; SI-NEXT: s_mov_b64 s[0:1], 0
; SI-NEXT: BB0_1: ; %ENDIF ; SI-NEXT: .LBB0_1: ; %ENDIF
; SI-NEXT: ; =>This Inner Loop Header: Depth=1 ; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_and_b64 s[2:3], exec, vcc ; SI-NEXT: s_and_b64 s[2:3], exec, vcc
; SI-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1] ; SI-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
; SI-NEXT: s_andn2_b64 exec, exec, s[0:1] ; SI-NEXT: s_andn2_b64 exec, exec, s[0:1]
; SI-NEXT: s_cbranch_execnz BB0_1 ; SI-NEXT: s_cbranch_execnz .LBB0_1
; SI-NEXT: ; %bb.2: ; %ENDLOOP ; SI-NEXT: ; %bb.2: ; %ENDLOOP
; SI-NEXT: s_or_b64 exec, exec, s[0:1] ; SI-NEXT: s_or_b64 exec, exec, s[0:1]
; SI-NEXT: s_mov_b32 s7, 0xf000 ; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1 ; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: v_mov_b32_e32 v0, 0 ; SI-NEXT: v_mov_b32_e32 v0, 0
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; FLAT-LABEL: break_inserted_outside_of_loop: ; FLAT-LABEL: break_inserted_outside_of_loop:
; FLAT: ; %bb.0: ; %main_body ; FLAT: ; %bb.0: ; %main_body
; FLAT-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; FLAT-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; FLAT-NEXT: s_load_dword s0, s[0:1], 0x2c ; FLAT-NEXT: s_load_dword s0, s[0:1], 0x2c
; FLAT-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0 ; FLAT-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
; FLAT-NEXT: s_waitcnt lgkmcnt(0) ; FLAT-NEXT: s_waitcnt lgkmcnt(0)
; FLAT-NEXT: v_and_b32_e32 v0, s0, v0 ; FLAT-NEXT: v_and_b32_e32 v0, s0, v0
; FLAT-NEXT: v_and_b32_e32 v0, 1, v0 ; FLAT-NEXT: v_and_b32_e32 v0, 1, v0
; FLAT-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 ; FLAT-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; FLAT-NEXT: s_mov_b64 s[0:1], 0 ; FLAT-NEXT: s_mov_b64 s[0:1], 0
; FLAT-NEXT: BB0_1: ; %ENDIF ; FLAT-NEXT: .LBB0_1: ; %ENDIF
; FLAT-NEXT: ; =>This Inner Loop Header: Depth=1 ; FLAT-NEXT: ; =>This Inner Loop Header: Depth=1
; FLAT-NEXT: s_and_b64 s[2:3], exec, vcc ; FLAT-NEXT: s_and_b64 s[2:3], exec, vcc
; FLAT-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1] ; FLAT-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
; FLAT-NEXT: s_andn2_b64 exec, exec, s[0:1] ; FLAT-NEXT: s_andn2_b64 exec, exec, s[0:1]
; FLAT-NEXT: s_cbranch_execnz BB0_1 ; FLAT-NEXT: s_cbranch_execnz .LBB0_1
; FLAT-NEXT: ; %bb.2: ; %ENDLOOP ; FLAT-NEXT: ; %bb.2: ; %ENDLOOP
; FLAT-NEXT: s_or_b64 exec, exec, s[0:1] ; FLAT-NEXT: s_or_b64 exec, exec, s[0:1]
; FLAT-NEXT: s_mov_b32 s7, 0xf000 ; FLAT-NEXT: s_mov_b32 s7, 0xf000
; FLAT-NEXT: s_mov_b32 s6, -1 ; FLAT-NEXT: s_mov_b32 s6, -1
; FLAT-NEXT: v_mov_b32_e32 v0, 0 ; FLAT-NEXT: v_mov_b32_e32 v0, 0
; FLAT-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; FLAT-NEXT: buffer_store_dword v0, off, s[4:7], 0
; FLAT-NEXT: s_endpgm ; FLAT-NEXT: s_endpgm
main_body: main_body:
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define amdgpu_kernel void @phi_cond_outside_loop(i32 %b) { define amdgpu_kernel void @phi_cond_outside_loop(i32 %b) {
; SI-LABEL: phi_cond_outside_loop: ; SI-LABEL: phi_cond_outside_loop:
; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: v_mbcnt_lo_u32_b32_e64 v0, -1, 0 ; SI-NEXT: v_mbcnt_lo_u32_b32_e64 v0, -1, 0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: s_mov_b64 s[2:3], 0 ; SI-NEXT: s_mov_b64 s[2:3], 0
; SI-NEXT: s_mov_b64 s[4:5], 0 ; SI-NEXT: s_mov_b64 s[4:5], 0
; SI-NEXT: s_and_saveexec_b64 s[6:7], vcc ; SI-NEXT: s_and_saveexec_b64 s[6:7], vcc
; SI-NEXT: s_cbranch_execz BB1_2 ; SI-NEXT: s_cbranch_execz .LBB1_2
; SI-NEXT: ; %bb.1: ; %else ; SI-NEXT: ; %bb.1: ; %else
; SI-NEXT: s_load_dword s0, s[0:1], 0x9 ; SI-NEXT: s_load_dword s0, s[0:1], 0x9
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_cmp_eq_u32 s0, 0 ; SI-NEXT: s_cmp_eq_u32 s0, 0
; SI-NEXT: s_cselect_b64 s[0:1], -1, 0 ; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
; SI-NEXT: s_and_b64 s[4:5], s[0:1], exec ; SI-NEXT: s_and_b64 s[4:5], s[0:1], exec
; SI-NEXT: BB1_2: ; %endif ; SI-NEXT: .LBB1_2: ; %endif
; SI-NEXT: s_or_b64 exec, exec, s[6:7] ; SI-NEXT: s_or_b64 exec, exec, s[6:7]
; SI-NEXT: BB1_3: ; %loop ; SI-NEXT: .LBB1_3: ; %loop
; SI-NEXT: ; =>This Inner Loop Header: Depth=1 ; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_and_b64 s[0:1], exec, s[4:5] ; SI-NEXT: s_and_b64 s[0:1], exec, s[4:5]
; SI-NEXT: s_or_b64 s[2:3], s[0:1], s[2:3] ; SI-NEXT: s_or_b64 s[2:3], s[0:1], s[2:3]
; SI-NEXT: s_andn2_b64 exec, exec, s[2:3] ; SI-NEXT: s_andn2_b64 exec, exec, s[2:3]
; SI-NEXT: s_cbranch_execnz BB1_3 ; SI-NEXT: s_cbranch_execnz .LBB1_3
; SI-NEXT: ; %bb.4: ; %exit ; SI-NEXT: ; %bb.4: ; %exit
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; FLAT-LABEL: phi_cond_outside_loop: ; FLAT-LABEL: phi_cond_outside_loop:
; FLAT: ; %bb.0: ; %entry ; FLAT: ; %bb.0: ; %entry
; FLAT-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0 ; FLAT-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
; FLAT-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; FLAT-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; FLAT-NEXT: s_mov_b64 s[2:3], 0 ; FLAT-NEXT: s_mov_b64 s[2:3], 0
; FLAT-NEXT: s_mov_b64 s[4:5], 0 ; FLAT-NEXT: s_mov_b64 s[4:5], 0
; FLAT-NEXT: s_and_saveexec_b64 s[6:7], vcc ; FLAT-NEXT: s_and_saveexec_b64 s[6:7], vcc
; FLAT-NEXT: s_cbranch_execz BB1_2 ; FLAT-NEXT: s_cbranch_execz .LBB1_2
; FLAT-NEXT: ; %bb.1: ; %else ; FLAT-NEXT: ; %bb.1: ; %else
; FLAT-NEXT: s_load_dword s0, s[0:1], 0x24 ; FLAT-NEXT: s_load_dword s0, s[0:1], 0x24
; FLAT-NEXT: s_waitcnt lgkmcnt(0) ; FLAT-NEXT: s_waitcnt lgkmcnt(0)
; FLAT-NEXT: s_cmp_eq_u32 s0, 0 ; FLAT-NEXT: s_cmp_eq_u32 s0, 0
; FLAT-NEXT: s_cselect_b64 s[0:1], -1, 0 ; FLAT-NEXT: s_cselect_b64 s[0:1], -1, 0
; FLAT-NEXT: s_and_b64 s[4:5], s[0:1], exec ; FLAT-NEXT: s_and_b64 s[4:5], s[0:1], exec
; FLAT-NEXT: BB1_2: ; %endif ; FLAT-NEXT: .LBB1_2: ; %endif
; FLAT-NEXT: s_or_b64 exec, exec, s[6:7] ; FLAT-NEXT: s_or_b64 exec, exec, s[6:7]
; FLAT-NEXT: BB1_3: ; %loop ; FLAT-NEXT: .LBB1_3: ; %loop
; FLAT-NEXT: ; =>This Inner Loop Header: Depth=1 ; FLAT-NEXT: ; =>This Inner Loop Header: Depth=1
; FLAT-NEXT: s_and_b64 s[0:1], exec, s[4:5] ; FLAT-NEXT: s_and_b64 s[0:1], exec, s[4:5]
; FLAT-NEXT: s_or_b64 s[2:3], s[0:1], s[2:3] ; FLAT-NEXT: s_or_b64 s[2:3], s[0:1], s[2:3]
; FLAT-NEXT: s_andn2_b64 exec, exec, s[2:3] ; FLAT-NEXT: s_andn2_b64 exec, exec, s[2:3]
; FLAT-NEXT: s_cbranch_execnz BB1_3 ; FLAT-NEXT: s_cbranch_execnz .LBB1_3
; FLAT-NEXT: ; %bb.4: ; %exit ; FLAT-NEXT: ; %bb.4: ; %exit
; FLAT-NEXT: s_endpgm ; FLAT-NEXT: s_endpgm
entry: entry:
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
%0 = icmp eq i32 %tid , 0 %0 = icmp eq i32 %tid , 0
br i1 %0, label %if, label %else br i1 %0, label %if, label %else
if: if:
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; SI-NEXT: s_cselect_b64 s[2:3], -1, 0 ; SI-NEXT: s_cselect_b64 s[2:3], -1, 0
; SI-NEXT: s_and_b64 s[2:3], s[4:5], s[2:3] ; SI-NEXT: s_and_b64 s[2:3], s[4:5], s[2:3]
; SI-NEXT: s_and_b64 s[0:1], exec, s[0:1] ; SI-NEXT: s_and_b64 s[0:1], exec, s[0:1]
; SI-NEXT: s_and_b64 s[2:3], exec, s[2:3] ; SI-NEXT: s_and_b64 s[2:3], exec, s[2:3]
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s8 ; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s8
; SI-NEXT: s_and_b64 s[4:5], exec, s[4:5] ; SI-NEXT: s_and_b64 s[4:5], exec, s[4:5]
; SI-NEXT: v_mov_b32_e32 v0, 3 ; SI-NEXT: v_mov_b32_e32 v0, 3
; SI-NEXT: s_branch BB3_4 ; SI-NEXT: s_branch .LBB3_4
; SI-NEXT: BB3_1: ; %Flow6 ; SI-NEXT: .LBB3_1: ; %Flow6
; SI-NEXT: ; in Loop: Header=BB3_4 Depth=1 ; SI-NEXT: ; in Loop: Header=BB3_4 Depth=1
; SI-NEXT: s_mov_b64 s[8:9], 0 ; SI-NEXT: s_mov_b64 s[8:9], 0
; SI-NEXT: BB3_2: ; %Flow5 ; SI-NEXT: .LBB3_2: ; %Flow5
; SI-NEXT: ; in Loop: Header=BB3_4 Depth=1 ; SI-NEXT: ; in Loop: Header=BB3_4 Depth=1
; SI-NEXT: s_mov_b64 s[12:13], 0 ; SI-NEXT: s_mov_b64 s[12:13], 0
; SI-NEXT: BB3_3: ; %Flow ; SI-NEXT: .LBB3_3: ; %Flow
; SI-NEXT: ; in Loop: Header=BB3_4 Depth=1 ; SI-NEXT: ; in Loop: Header=BB3_4 Depth=1
; SI-NEXT: s_and_b64 vcc, exec, s[10:11] ; SI-NEXT: s_and_b64 vcc, exec, s[10:11]
; SI-NEXT: s_cbranch_vccnz BB3_8 ; SI-NEXT: s_cbranch_vccnz .LBB3_8
; SI-NEXT: BB3_4: ; %while.cond ; SI-NEXT: .LBB3_4: ; %while.cond
; SI-NEXT: ; =>This Inner Loop Header: Depth=1 ; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_mov_b64 s[12:13], -1 ; SI-NEXT: s_mov_b64 s[12:13], -1
; SI-NEXT: s_mov_b64 s[8:9], -1 ; SI-NEXT: s_mov_b64 s[8:9], -1
; SI-NEXT: s_mov_b64 s[10:11], -1 ; SI-NEXT: s_mov_b64 s[10:11], -1
; SI-NEXT: s_mov_b64 vcc, s[0:1] ; SI-NEXT: s_mov_b64 vcc, s[0:1]
; SI-NEXT: s_cbranch_vccz BB3_3 ; SI-NEXT: s_cbranch_vccz .LBB3_3
; SI-NEXT: ; %bb.5: ; %convex.exit ; SI-NEXT: ; %bb.5: ; %convex.exit
; SI-NEXT: ; in Loop: Header=BB3_4 Depth=1 ; SI-NEXT: ; in Loop: Header=BB3_4 Depth=1
; SI-NEXT: s_mov_b64 s[8:9], -1 ; SI-NEXT: s_mov_b64 s[8:9], -1
; SI-NEXT: s_mov_b64 s[10:11], -1 ; SI-NEXT: s_mov_b64 s[10:11], -1
; SI-NEXT: s_mov_b64 vcc, s[2:3] ; SI-NEXT: s_mov_b64 vcc, s[2:3]
; SI-NEXT: s_cbranch_vccz BB3_2 ; SI-NEXT: s_cbranch_vccz .LBB3_2
; SI-NEXT: ; %bb.6: ; %if.end ; SI-NEXT: ; %bb.6: ; %if.end
; SI-NEXT: ; in Loop: Header=BB3_4 Depth=1 ; SI-NEXT: ; in Loop: Header=BB3_4 Depth=1
; SI-NEXT: s_mov_b64 s[10:11], -1 ; SI-NEXT: s_mov_b64 s[10:11], -1
; SI-NEXT: s_mov_b64 vcc, s[4:5] ; SI-NEXT: s_mov_b64 vcc, s[4:5]
; SI-NEXT: s_cbranch_vccz BB3_1 ; SI-NEXT: s_cbranch_vccz .LBB3_1
; SI-NEXT: ; %bb.7: ; %if.else ; SI-NEXT: ; %bb.7: ; %if.else
; SI-NEXT: ; in Loop: Header=BB3_4 Depth=1 ; SI-NEXT: ; in Loop: Header=BB3_4 Depth=1
; SI-NEXT: s_mov_b64 s[10:11], 0 ; SI-NEXT: s_mov_b64 s[10:11], 0
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_branch BB3_1 ; SI-NEXT: s_branch .LBB3_1
; SI-NEXT: BB3_8: ; %loop.exit.guard4 ; SI-NEXT: .LBB3_8: ; %loop.exit.guard4
; SI-NEXT: ; in Loop: Header=BB3_4 Depth=1 ; SI-NEXT: ; in Loop: Header=BB3_4 Depth=1
; SI-NEXT: s_and_b64 vcc, exec, s[8:9] ; SI-NEXT: s_and_b64 vcc, exec, s[8:9]
; SI-NEXT: s_cbranch_vccz BB3_4 ; SI-NEXT: s_cbranch_vccz .LBB3_4
; SI-NEXT: ; %bb.9: ; %loop.exit.guard ; SI-NEXT: ; %bb.9: ; %loop.exit.guard
; SI-NEXT: s_and_b64 vcc, exec, s[12:13] ; SI-NEXT: s_and_b64 vcc, exec, s[12:13]
; SI-NEXT: s_cbranch_vccz BB3_13 ; SI-NEXT: s_cbranch_vccz .LBB3_13
; SI-NEXT: ; %bb.10: ; %for.cond.preheader ; SI-NEXT: ; %bb.10: ; %for.cond.preheader
; SI-NEXT: s_cmpk_lt_i32 s14, 0x3e8 ; SI-NEXT: s_cmpk_lt_i32 s14, 0x3e8
; SI-NEXT: s_cbranch_scc0 BB3_13 ; SI-NEXT: s_cbranch_scc0 .LBB3_13
; SI-NEXT: ; %bb.11: ; %for.body ; SI-NEXT: ; %bb.11: ; %for.body
; SI-NEXT: s_and_b64 vcc, exec, 0 ; SI-NEXT: s_and_b64 vcc, exec, 0
; SI-NEXT: BB3_12: ; %self.loop ; SI-NEXT: .LBB3_12: ; %self.loop
; SI-NEXT: ; =>This Inner Loop Header: Depth=1 ; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_mov_b64 vcc, vcc ; SI-NEXT: s_mov_b64 vcc, vcc
; SI-NEXT: s_cbranch_vccz BB3_12 ; SI-NEXT: s_cbranch_vccz .LBB3_12
; SI-NEXT: BB3_13: ; %DummyReturnBlock ; SI-NEXT: .LBB3_13: ; %DummyReturnBlock
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; FLAT-LABEL: loop_land_info_assert: ; FLAT-LABEL: loop_land_info_assert:
; FLAT: ; %bb.0: ; %entry ; FLAT: ; %bb.0: ; %entry
; FLAT-NEXT: s_mov_b32 s7, 0xf000 ; FLAT-NEXT: s_mov_b32 s7, 0xf000
; FLAT-NEXT: s_mov_b32 s6, -1 ; FLAT-NEXT: s_mov_b32 s6, -1
; FLAT-NEXT: buffer_load_dword v0, off, s[4:7], 0 ; FLAT-NEXT: buffer_load_dword v0, off, s[4:7], 0
; FLAT-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; FLAT-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; FLAT-NEXT: s_load_dword s14, s[0:1], 0x30 ; FLAT-NEXT: s_load_dword s14, s[0:1], 0x30
; FLAT-NEXT: s_brev_b32 s8, 44 ; FLAT-NEXT: s_brev_b32 s8, 44
; FLAT-NEXT: s_waitcnt lgkmcnt(0) ; FLAT-NEXT: s_waitcnt lgkmcnt(0)
; FLAT-NEXT: s_cmp_lt_i32 s2, 1 ; FLAT-NEXT: s_cmp_lt_i32 s2, 1
; FLAT-NEXT: s_cselect_b64 s[4:5], -1, 0 ; FLAT-NEXT: s_cselect_b64 s[4:5], -1, 0
; FLAT-NEXT: s_cmp_lt_i32 s3, 4 ; FLAT-NEXT: s_cmp_lt_i32 s3, 4
; FLAT-NEXT: s_cselect_b64 s[0:1], -1, 0 ; FLAT-NEXT: s_cselect_b64 s[0:1], -1, 0
; FLAT-NEXT: s_cmp_gt_i32 s3, 3 ; FLAT-NEXT: s_cmp_gt_i32 s3, 3
; FLAT-NEXT: s_cselect_b64 s[2:3], -1, 0 ; FLAT-NEXT: s_cselect_b64 s[2:3], -1, 0
; FLAT-NEXT: s_and_b64 s[2:3], s[4:5], s[2:3] ; FLAT-NEXT: s_and_b64 s[2:3], s[4:5], s[2:3]
; FLAT-NEXT: s_and_b64 s[0:1], exec, s[0:1] ; FLAT-NEXT: s_and_b64 s[0:1], exec, s[0:1]
; FLAT-NEXT: s_and_b64 s[2:3], exec, s[2:3] ; FLAT-NEXT: s_and_b64 s[2:3], exec, s[2:3]
; FLAT-NEXT: s_waitcnt vmcnt(0) ; FLAT-NEXT: s_waitcnt vmcnt(0)
; FLAT-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s8 ; FLAT-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s8
; FLAT-NEXT: s_and_b64 s[4:5], exec, s[4:5] ; FLAT-NEXT: s_and_b64 s[4:5], exec, s[4:5]
; FLAT-NEXT: v_mov_b32_e32 v0, 3 ; FLAT-NEXT: v_mov_b32_e32 v0, 3
; FLAT-NEXT: s_branch BB3_4 ; FLAT-NEXT: s_branch .LBB3_4
; FLAT-NEXT: BB3_1: ; %Flow6 ; FLAT-NEXT: .LBB3_1: ; %Flow6
; FLAT-NEXT: ; in Loop: Header=BB3_4 Depth=1 ; FLAT-NEXT: ; in Loop: Header=BB3_4 Depth=1
; FLAT-NEXT: s_mov_b64 s[8:9], 0 ; FLAT-NEXT: s_mov_b64 s[8:9], 0
; FLAT-NEXT: BB3_2: ; %Flow5 ; FLAT-NEXT: .LBB3_2: ; %Flow5
; FLAT-NEXT: ; in Loop: Header=BB3_4 Depth=1 ; FLAT-NEXT: ; in Loop: Header=BB3_4 Depth=1
; FLAT-NEXT: s_mov_b64 s[12:13], 0 ; FLAT-NEXT: s_mov_b64 s[12:13], 0
; FLAT-NEXT: BB3_3: ; %Flow ; FLAT-NEXT: .LBB3_3: ; %Flow
; FLAT-NEXT: ; in Loop: Header=BB3_4 Depth=1 ; FLAT-NEXT: ; in Loop: Header=BB3_4 Depth=1
; FLAT-NEXT: s_and_b64 vcc, exec, s[10:11] ; FLAT-NEXT: s_and_b64 vcc, exec, s[10:11]
; FLAT-NEXT: s_cbranch_vccnz BB3_8 ; FLAT-NEXT: s_cbranch_vccnz .LBB3_8
; FLAT-NEXT: BB3_4: ; %while.cond ; FLAT-NEXT: .LBB3_4: ; %while.cond
; FLAT-NEXT: ; =>This Inner Loop Header: Depth=1 ; FLAT-NEXT: ; =>This Inner Loop Header: Depth=1
; FLAT-NEXT: s_mov_b64 s[12:13], -1 ; FLAT-NEXT: s_mov_b64 s[12:13], -1
; FLAT-NEXT: s_mov_b64 s[8:9], -1 ; FLAT-NEXT: s_mov_b64 s[8:9], -1
; FLAT-NEXT: s_mov_b64 s[10:11], -1 ; FLAT-NEXT: s_mov_b64 s[10:11], -1
; FLAT-NEXT: s_mov_b64 vcc, s[0:1] ; FLAT-NEXT: s_mov_b64 vcc, s[0:1]
; FLAT-NEXT: s_cbranch_vccz BB3_3 ; FLAT-NEXT: s_cbranch_vccz .LBB3_3
; FLAT-NEXT: ; %bb.5: ; %convex.exit ; FLAT-NEXT: ; %bb.5: ; %convex.exit
; FLAT-NEXT: ; in Loop: Header=BB3_4 Depth=1 ; FLAT-NEXT: ; in Loop: Header=BB3_4 Depth=1
; FLAT-NEXT: s_mov_b64 s[8:9], -1 ; FLAT-NEXT: s_mov_b64 s[8:9], -1
; FLAT-NEXT: s_mov_b64 s[10:11], -1 ; FLAT-NEXT: s_mov_b64 s[10:11], -1
; FLAT-NEXT: s_mov_b64 vcc, s[2:3] ; FLAT-NEXT: s_mov_b64 vcc, s[2:3]
; FLAT-NEXT: s_cbranch_vccz BB3_2 ; FLAT-NEXT: s_cbranch_vccz .LBB3_2
; FLAT-NEXT: ; %bb.6: ; %if.end ; FLAT-NEXT: ; %bb.6: ; %if.end
; FLAT-NEXT: ; in Loop: Header=BB3_4 Depth=1 ; FLAT-NEXT: ; in Loop: Header=BB3_4 Depth=1
; FLAT-NEXT: s_mov_b64 s[10:11], -1 ; FLAT-NEXT: s_mov_b64 s[10:11], -1
; FLAT-NEXT: s_mov_b64 vcc, s[4:5] ; FLAT-NEXT: s_mov_b64 vcc, s[4:5]
; FLAT-NEXT: s_cbranch_vccz BB3_1 ; FLAT-NEXT: s_cbranch_vccz .LBB3_1
; FLAT-NEXT: ; %bb.7: ; %if.else ; FLAT-NEXT: ; %bb.7: ; %if.else
; FLAT-NEXT: ; in Loop: Header=BB3_4 Depth=1 ; FLAT-NEXT: ; in Loop: Header=BB3_4 Depth=1
; FLAT-NEXT: s_mov_b64 s[10:11], 0 ; FLAT-NEXT: s_mov_b64 s[10:11], 0
; FLAT-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; FLAT-NEXT: buffer_store_dword v0, off, s[4:7], 0
; FLAT-NEXT: s_waitcnt vmcnt(0) ; FLAT-NEXT: s_waitcnt vmcnt(0)
; FLAT-NEXT: s_branch BB3_1 ; FLAT-NEXT: s_branch .LBB3_1
; FLAT-NEXT: BB3_8: ; %loop.exit.guard4 ; FLAT-NEXT: .LBB3_8: ; %loop.exit.guard4
; FLAT-NEXT: ; in Loop: Header=BB3_4 Depth=1 ; FLAT-NEXT: ; in Loop: Header=BB3_4 Depth=1
; FLAT-NEXT: s_and_b64 vcc, exec, s[8:9] ; FLAT-NEXT: s_and_b64 vcc, exec, s[8:9]
; FLAT-NEXT: s_cbranch_vccz BB3_4 ; FLAT-NEXT: s_cbranch_vccz .LBB3_4
; FLAT-NEXT: ; %bb.9: ; %loop.exit.guard ; FLAT-NEXT: ; %bb.9: ; %loop.exit.guard
; FLAT-NEXT: s_and_b64 vcc, exec, s[12:13] ; FLAT-NEXT: s_and_b64 vcc, exec, s[12:13]
; FLAT-NEXT: s_cbranch_vccz BB3_13 ; FLAT-NEXT: s_cbranch_vccz .LBB3_13
; FLAT-NEXT: ; %bb.10: ; %for.cond.preheader ; FLAT-NEXT: ; %bb.10: ; %for.cond.preheader
; FLAT-NEXT: s_cmpk_lt_i32 s14, 0x3e8 ; FLAT-NEXT: s_cmpk_lt_i32 s14, 0x3e8
; FLAT-NEXT: s_cbranch_scc0 BB3_13 ; FLAT-NEXT: s_cbranch_scc0 .LBB3_13
; FLAT-NEXT: ; %bb.11: ; %for.body ; FLAT-NEXT: ; %bb.11: ; %for.body
; FLAT-NEXT: s_and_b64 vcc, exec, 0 ; FLAT-NEXT: s_and_b64 vcc, exec, 0
; FLAT-NEXT: BB3_12: ; %self.loop ; FLAT-NEXT: .LBB3_12: ; %self.loop
; FLAT-NEXT: ; =>This Inner Loop Header: Depth=1 ; FLAT-NEXT: ; =>This Inner Loop Header: Depth=1
; FLAT-NEXT: s_mov_b64 vcc, vcc ; FLAT-NEXT: s_mov_b64 vcc, vcc
; FLAT-NEXT: s_cbranch_vccz BB3_12 ; FLAT-NEXT: s_cbranch_vccz .LBB3_12
; FLAT-NEXT: BB3_13: ; %DummyReturnBlock ; FLAT-NEXT: .LBB3_13: ; %DummyReturnBlock
; FLAT-NEXT: s_endpgm ; FLAT-NEXT: s_endpgm
entry: entry:
%cmp = icmp sgt i32 %c0, 0 %cmp = icmp sgt i32 %c0, 0
br label %while.cond.outer br label %while.cond.outer
while.cond.outer: while.cond.outer:
%tmp = load float, float addrspace(1)* undef %tmp = load float, float addrspace(1)* undef
br label %while.cond br label %while.cond
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llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -mcpu=kaveri -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mcpu=kaveri -verify-machineinstrs < %s | FileCheck %s
define amdgpu_kernel void @test(i32 %arg, i32 %arg1) { define amdgpu_kernel void @test(i32 %arg, i32 %arg1) {
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: ; %bb.0: ; %bb ; CHECK: ; %bb.0: ; %bb
; CHECK-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; CHECK-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; CHECK-NEXT: s_waitcnt lgkmcnt(0) ; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: s_cmp_eq_u32 s0, 0 ; CHECK-NEXT: s_cmp_eq_u32 s0, 0
; CHECK-NEXT: s_cselect_b64 s[2:3], -1, 0 ; CHECK-NEXT: s_cselect_b64 s[2:3], -1, 0
; CHECK-NEXT: s_cmp_eq_u32 s1, 0 ; CHECK-NEXT: s_cmp_eq_u32 s1, 0
; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 ; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0
; CHECK-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1] ; CHECK-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
; CHECK-NEXT: s_and_b64 vcc, exec, s[0:1] ; CHECK-NEXT: s_and_b64 vcc, exec, s[0:1]
; CHECK-NEXT: s_cbranch_vccnz BB0_3 ; CHECK-NEXT: s_cbranch_vccnz .LBB0_3
; CHECK-NEXT: ; %bb.1: ; %bb9 ; CHECK-NEXT: ; %bb.1: ; %bb9
; CHECK-NEXT: s_and_b64 vcc, exec, 0 ; CHECK-NEXT: s_and_b64 vcc, exec, 0
; CHECK-NEXT: BB0_2: ; %bb10 ; CHECK-NEXT: .LBB0_2: ; %bb10
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: s_mov_b64 vcc, vcc ; CHECK-NEXT: s_mov_b64 vcc, vcc
; CHECK-NEXT: s_cbranch_vccz BB0_2 ; CHECK-NEXT: s_cbranch_vccz .LBB0_2
; CHECK-NEXT: BB0_3: ; %DummyReturnBlock ; CHECK-NEXT: .LBB0_3: ; %DummyReturnBlock
; CHECK-NEXT: s_endpgm ; CHECK-NEXT: s_endpgm
bb: bb:
%tmp = icmp ne i32 %arg, 0 %tmp = icmp ne i32 %arg, 0
%tmp7 = icmp ne i32 %arg1, 0 %tmp7 = icmp ne i32 %arg1, 0
%tmp8 = and i1 %tmp, %tmp7 %tmp8 = and i1 %tmp, %tmp7
br i1 %tmp8, label %bb9, label %bb11 br i1 %tmp8, label %bb9, label %bb11
bb9: ; preds = %bb bb9: ; preds = %bb
br label %bb10 br label %bb10
bb10: ; preds = %bb10, %bb9 bb10: ; preds = %bb10, %bb9
br label %bb10 br label %bb10
bb11: ; preds = %bb bb11: ; preds = %bb
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll

; RUN: llc -march=amdgcn -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}lower_control_flow_unreachable_terminator: ; GCN-LABEL: {{^}}lower_control_flow_unreachable_terminator:
; GCN: v_cmp_eq_u32 ; GCN: v_cmp_eq_u32
; GCN: s_and_saveexec_b64 ; GCN: s_and_saveexec_b64
; GCN-NEXT: s_cbranch_execz BB0_{{[0-9]+}} ; GCN-NEXT: s_cbranch_execz .LBB0_{{[0-9]+}}
; GCN-NEXT: ; %bb.{{[0-9]+}}: ; %unreachable ; GCN-NEXT: ; %bb.{{[0-9]+}}: ; %unreachable
; GCN: ds_write_b32 ; GCN: ds_write_b32
; GCN: ; divergent unreachable ; GCN: ; divergent unreachable
; GCN-NEXT: BB0_{{[0-9]+}}: ; %UnifiedReturnBlock ; GCN-NEXT: BB0_{{[0-9]+}}: ; %UnifiedReturnBlock
; GCN: s_endpgm ; GCN: s_endpgm
Show All 9 Lines
ret: ret:
ret void ret void
} }
; GCN-LABEL: {{^}}lower_control_flow_unreachable_terminator_swap_block_order: ; GCN-LABEL: {{^}}lower_control_flow_unreachable_terminator_swap_block_order:
; GCN: v_cmp_ne_u32 ; GCN: v_cmp_ne_u32
; GCN: s_and_saveexec_b64 ; GCN: s_and_saveexec_b64
; GCN-NEXT: s_cbranch_execz BB1_{{[0-9]+}} ; GCN-NEXT: s_cbranch_execz .LBB1_{{[0-9]+}}
; GCN-NEXT: ; %bb.{{[0-9]+}}: ; %unreachable ; GCN-NEXT: ; %bb.{{[0-9]+}}: ; %unreachable
; GCN: ds_write_b32 ; GCN: ds_write_b32
; GCN: ; divergent unreachable ; GCN: ; divergent unreachable
; GCN: BB1_{{[0-9]+}}: ; GCN: BB1_{{[0-9]+}}:
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @lower_control_flow_unreachable_terminator_swap_block_order() #0 { define amdgpu_kernel void @lower_control_flow_unreachable_terminator_swap_block_order() #0 {
bb: bb:
%tmp15 = tail call i32 @llvm.amdgcn.workitem.id.y() %tmp15 = tail call i32 @llvm.amdgcn.workitem.id.y()
%tmp63 = icmp eq i32 %tmp15, 32 %tmp63 = icmp eq i32 %tmp15, 32
br i1 %tmp63, label %ret, label %unreachable br i1 %tmp63, label %ret, label %unreachable
ret: ret:
ret void ret void
unreachable: unreachable:
store volatile i32 0, i32 addrspace(3)* undef, align 4 store volatile i32 0, i32 addrspace(3)* undef, align 4
unreachable unreachable
} }
; GCN-LABEL: {{^}}uniform_lower_control_flow_unreachable_terminator: ; GCN-LABEL: {{^}}uniform_lower_control_flow_unreachable_terminator:
; GCN: s_cmp_lg_u32 ; GCN: s_cmp_lg_u32
; GCN: s_cbranch_scc0 [[UNREACHABLE:BB[0-9]+_[0-9]+]] ; GCN: s_cbranch_scc0 [[UNREACHABLE:.LBB[0-9]+_[0-9]+]]
; GCN-NEXT: %bb.{{[0-9]+}}: ; %ret ; GCN-NEXT: %bb.{{[0-9]+}}: ; %ret
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; GCN: [[UNREACHABLE]]: ; GCN: [[UNREACHABLE]]:
; GCN: ds_write_b32 ; GCN: ds_write_b32
define amdgpu_kernel void @uniform_lower_control_flow_unreachable_terminator(i32 %arg0) #0 { define amdgpu_kernel void @uniform_lower_control_flow_unreachable_terminator(i32 %arg0) #0 {
bb: bb:
Show All 16 Lines

llvm/test/CodeGen/AMDGPU/skip-branch-trap.ll

; RUN: llc -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
; FIXME: merge with trap.ll ; FIXME: merge with trap.ll
; An s_cbranch_execnz is required to avoid trapping if all lanes are 0 ; An s_cbranch_execnz is required to avoid trapping if all lanes are 0
; GCN-LABEL: {{^}}trap_divergent_branch: ; GCN-LABEL: {{^}}trap_divergent_branch:
; GCN: s_and_saveexec_b64 ; GCN: s_and_saveexec_b64
; GCN: s_cbranch_execnz [[TRAP:BB[0-9]+_[0-9]+]] ; GCN: s_cbranch_execnz [[TRAP:.LBB[0-9]+_[0-9]+]]
; GCN: ; %bb.{{[0-9]+}}: ; GCN: ; %bb.{{[0-9]+}}:
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; GCN: [[TRAP]]: ; GCN: [[TRAP]]:
; GCN: s_trap 2 ; GCN: s_trap 2
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @trap_divergent_branch(i32 addrspace(1)* nocapture readonly %arg) { define amdgpu_kernel void @trap_divergent_branch(i32 addrspace(1)* nocapture readonly %arg) {
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %id %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %id
%divergent.val = load i32, i32 addrspace(1)* %gep %divergent.val = load i32, i32 addrspace(1)* %gep
%cmp = icmp eq i32 %divergent.val, 0 %cmp = icmp eq i32 %divergent.val, 0
br i1 %cmp, label %bb, label %end br i1 %cmp, label %bb, label %end
bb: bb:
call void @llvm.trap() call void @llvm.trap()
br label %end br label %end
end: end:
ret void ret void
} }
; GCN-LABEL: {{^}}debugtrap_divergent_branch: ; GCN-LABEL: {{^}}debugtrap_divergent_branch:
; GCN: s_and_saveexec_b64 ; GCN: s_and_saveexec_b64
; GCN: s_cbranch_execz [[ENDPGM:BB[0-9]+_[0-9]+]] ; GCN: s_cbranch_execz [[ENDPGM:.LBB[0-9]+_[0-9]+]]
; GCN: ; %bb.{{[0-9]+}}: ; GCN: ; %bb.{{[0-9]+}}:
; GCN: s_trap 3 ; GCN: s_trap 3
; GCN-NEXT: [[ENDPGM]]: ; GCN-NEXT: [[ENDPGM]]:
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @debugtrap_divergent_branch(i32 addrspace(1)* nocapture readonly %arg) { define amdgpu_kernel void @debugtrap_divergent_branch(i32 addrspace(1)* nocapture readonly %arg) {
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %id %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %id
%divergent.val = load i32, i32 addrspace(1)* %gep %divergent.val = load i32, i32 addrspace(1)* %gep
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llvm/test/CodeGen/AMDGPU/skip-if-dead.ll

Show All 9 Lines; GCN-NEXT: s_endpgm
call void @llvm.amdgcn.kill(i1 true) call void @llvm.amdgcn.kill(i1 true)
ret void ret void
} }
define amdgpu_ps void @test_kill_depth_0_imm_neg() #0 { define amdgpu_ps void @test_kill_depth_0_imm_neg() #0 {
; WAVE64-LABEL: test_kill_depth_0_imm_neg: ; WAVE64-LABEL: test_kill_depth_0_imm_neg:
; WAVE64: ; %bb.0: ; WAVE64: ; %bb.0:
; WAVE64-NEXT: s_andn2_b64 exec, exec, exec ; WAVE64-NEXT: s_andn2_b64 exec, exec, exec
; WAVE64-NEXT: s_cbranch_scc0 BB1_1 ; WAVE64-NEXT: s_cbranch_scc0 .LBB1_1
; WAVE64-NEXT: s_endpgm ; WAVE64-NEXT: s_endpgm
; WAVE64-NEXT: BB1_1: ; WAVE64-NEXT: .LBB1_1:
; WAVE64-NEXT: s_mov_b64 exec, 0 ; WAVE64-NEXT: s_mov_b64 exec, 0
; WAVE64-NEXT: exp null off, off, off, off done vm ; WAVE64-NEXT: exp null off, off, off, off done vm
; WAVE64-NEXT: s_endpgm ; WAVE64-NEXT: s_endpgm
; ;
; GFX10-WAVE32-LABEL: test_kill_depth_0_imm_neg: ; GFX10-WAVE32-LABEL: test_kill_depth_0_imm_neg:
; GFX10-WAVE32: ; %bb.0: ; GFX10-WAVE32: ; %bb.0:
; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, exec_lo ; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, exec_lo
; GFX10-WAVE32-NEXT: s_cbranch_scc0 BB1_1 ; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB1_1
; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: s_endpgm
; GFX10-WAVE32-NEXT: BB1_1: ; GFX10-WAVE32-NEXT: .LBB1_1:
; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm ; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm
; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: s_endpgm
call void @llvm.amdgcn.kill(i1 false) call void @llvm.amdgcn.kill(i1 false)
ret void ret void
} }
; FIXME: Ideally only one early-exit would be emitted ; FIXME: Ideally only one early-exit would be emitted
define amdgpu_ps void @test_kill_depth_0_imm_neg_x2() #0 { define amdgpu_ps void @test_kill_depth_0_imm_neg_x2() #0 {
; WAVE64-LABEL: test_kill_depth_0_imm_neg_x2: ; WAVE64-LABEL: test_kill_depth_0_imm_neg_x2:
; WAVE64: ; %bb.0: ; WAVE64: ; %bb.0:
; WAVE64-NEXT: s_mov_b64 s[0:1], exec ; WAVE64-NEXT: s_mov_b64 s[0:1], exec
; WAVE64-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; WAVE64-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; WAVE64-NEXT: s_cbranch_scc0 BB2_2 ; WAVE64-NEXT: s_cbranch_scc0 .LBB2_2
; WAVE64-NEXT: ; %bb.1: ; WAVE64-NEXT: ; %bb.1:
; WAVE64-NEXT: s_mov_b64 exec, 0 ; WAVE64-NEXT: s_mov_b64 exec, 0
; WAVE64-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; WAVE64-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; WAVE64-NEXT: s_cbranch_scc0 BB2_2 ; WAVE64-NEXT: s_cbranch_scc0 .LBB2_2
; WAVE64-NEXT: s_endpgm ; WAVE64-NEXT: s_endpgm
; WAVE64-NEXT: BB2_2: ; WAVE64-NEXT: .LBB2_2:
; WAVE64-NEXT: s_mov_b64 exec, 0 ; WAVE64-NEXT: s_mov_b64 exec, 0
; WAVE64-NEXT: exp null off, off, off, off done vm ; WAVE64-NEXT: exp null off, off, off, off done vm
; WAVE64-NEXT: s_endpgm ; WAVE64-NEXT: s_endpgm
; ;
; GFX10-WAVE32-LABEL: test_kill_depth_0_imm_neg_x2: ; GFX10-WAVE32-LABEL: test_kill_depth_0_imm_neg_x2:
; GFX10-WAVE32: ; %bb.0: ; GFX10-WAVE32: ; %bb.0:
; GFX10-WAVE32-NEXT: s_mov_b32 s0, exec_lo ; GFX10-WAVE32-NEXT: s_mov_b32 s0, exec_lo
; GFX10-WAVE32-NEXT: s_andn2_b32 s0, s0, exec_lo ; GFX10-WAVE32-NEXT: s_andn2_b32 s0, s0, exec_lo
; GFX10-WAVE32-NEXT: s_cbranch_scc0 BB2_2 ; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB2_2
; GFX10-WAVE32-NEXT: ; %bb.1: ; GFX10-WAVE32-NEXT: ; %bb.1:
; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-WAVE32-NEXT: s_andn2_b32 s0, s0, exec_lo ; GFX10-WAVE32-NEXT: s_andn2_b32 s0, s0, exec_lo
; GFX10-WAVE32-NEXT: s_cbranch_scc0 BB2_2 ; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB2_2
; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: s_endpgm
; GFX10-WAVE32-NEXT: BB2_2: ; GFX10-WAVE32-NEXT: .LBB2_2:
; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm ; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm
; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: s_endpgm
call void @llvm.amdgcn.kill(i1 false) call void @llvm.amdgcn.kill(i1 false)
call void @llvm.amdgcn.kill(i1 false) call void @llvm.amdgcn.kill(i1 false)
ret void ret void
} }
define amdgpu_ps void @test_kill_depth_var(float %x) #0 { define amdgpu_ps void @test_kill_depth_var(float %x) #0 {
; WAVE64-LABEL: test_kill_depth_var: ; WAVE64-LABEL: test_kill_depth_var:
; WAVE64: ; %bb.0: ; WAVE64: ; %bb.0:
; WAVE64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0 ; WAVE64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0
; WAVE64-NEXT: s_andn2_b64 exec, exec, vcc ; WAVE64-NEXT: s_andn2_b64 exec, exec, vcc
; WAVE64-NEXT: s_cbranch_scc0 BB3_1 ; WAVE64-NEXT: s_cbranch_scc0 .LBB3_1
; WAVE64-NEXT: s_endpgm ; WAVE64-NEXT: s_endpgm
; WAVE64-NEXT: BB3_1: ; WAVE64-NEXT: .LBB3_1:
; WAVE64-NEXT: s_mov_b64 exec, 0 ; WAVE64-NEXT: s_mov_b64 exec, 0
; WAVE64-NEXT: exp null off, off, off, off done vm ; WAVE64-NEXT: exp null off, off, off, off done vm
; WAVE64-NEXT: s_endpgm ; WAVE64-NEXT: s_endpgm
; ;
; GFX10-WAVE32-LABEL: test_kill_depth_var: ; GFX10-WAVE32-LABEL: test_kill_depth_var:
; GFX10-WAVE32: ; %bb.0: ; GFX10-WAVE32: ; %bb.0:
; GFX10-WAVE32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v0 ; GFX10-WAVE32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v0
; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, vcc_lo ; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, vcc_lo
; GFX10-WAVE32-NEXT: s_cbranch_scc0 BB3_1 ; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB3_1
; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: s_endpgm
; GFX10-WAVE32-NEXT: BB3_1: ; GFX10-WAVE32-NEXT: .LBB3_1:
; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm ; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm
; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: s_endpgm
%cmp = fcmp olt float %x, 0.0 %cmp = fcmp olt float %x, 0.0
call void @llvm.amdgcn.kill(i1 %cmp) call void @llvm.amdgcn.kill(i1 %cmp)
ret void ret void
} }
; FIXME: Ideally only one early-exit would be emitted ; FIXME: Ideally only one early-exit would be emitted
define amdgpu_ps void @test_kill_depth_var_x2_same(float %x) #0 { define amdgpu_ps void @test_kill_depth_var_x2_same(float %x) #0 {
; SI-LABEL: test_kill_depth_var_x2_same: ; SI-LABEL: test_kill_depth_var_x2_same:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_mov_b64 s[0:1], exec ; SI-NEXT: s_mov_b64 s[0:1], exec
; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0 ; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0
; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc ; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc
; SI-NEXT: s_cbranch_scc0 BB4_2 ; SI-NEXT: s_cbranch_scc0 .LBB4_2
; SI-NEXT: ; %bb.1: ; SI-NEXT: ; %bb.1:
; SI-NEXT: s_andn2_b64 exec, exec, vcc ; SI-NEXT: s_andn2_b64 exec, exec, vcc
; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0 ; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0
; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc ; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc
; SI-NEXT: s_cbranch_scc0 BB4_2 ; SI-NEXT: s_cbranch_scc0 .LBB4_2
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; SI-NEXT: BB4_2: ; SI-NEXT: .LBB4_2:
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: exp null off, off, off, off done vm ; SI-NEXT: exp null off, off, off, off done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; GFX10-WAVE64-LABEL: test_kill_depth_var_x2_same: ; GFX10-WAVE64-LABEL: test_kill_depth_var_x2_same:
; GFX10-WAVE64: ; %bb.0: ; GFX10-WAVE64: ; %bb.0:
; GFX10-WAVE64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0 ; GFX10-WAVE64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0
; GFX10-WAVE64-NEXT: s_mov_b64 s[0:1], exec ; GFX10-WAVE64-NEXT: s_mov_b64 s[0:1], exec
; GFX10-WAVE64-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc ; GFX10-WAVE64-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc
; GFX10-WAVE64-NEXT: s_cbranch_scc0 BB4_2 ; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB4_2
; GFX10-WAVE64-NEXT: ; %bb.1: ; GFX10-WAVE64-NEXT: ; %bb.1:
; GFX10-WAVE64-NEXT: s_andn2_b64 exec, exec, vcc ; GFX10-WAVE64-NEXT: s_andn2_b64 exec, exec, vcc
; GFX10-WAVE64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0 ; GFX10-WAVE64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0
; GFX10-WAVE64-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc ; GFX10-WAVE64-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc
; GFX10-WAVE64-NEXT: s_cbranch_scc0 BB4_2 ; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB4_2
; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: s_endpgm
; GFX10-WAVE64-NEXT: BB4_2: ; GFX10-WAVE64-NEXT: .LBB4_2:
; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0 ; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0
; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm ; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm
; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: s_endpgm
; ;
; GFX10-WAVE32-LABEL: test_kill_depth_var_x2_same: ; GFX10-WAVE32-LABEL: test_kill_depth_var_x2_same:
; GFX10-WAVE32: ; %bb.0: ; GFX10-WAVE32: ; %bb.0:
; GFX10-WAVE32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v0 ; GFX10-WAVE32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v0
; GFX10-WAVE32-NEXT: s_mov_b32 s0, exec_lo ; GFX10-WAVE32-NEXT: s_mov_b32 s0, exec_lo
; GFX10-WAVE32-NEXT: s_andn2_b32 s0, s0, vcc_lo ; GFX10-WAVE32-NEXT: s_andn2_b32 s0, s0, vcc_lo
; GFX10-WAVE32-NEXT: s_cbranch_scc0 BB4_2 ; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB4_2
; GFX10-WAVE32-NEXT: ; %bb.1: ; GFX10-WAVE32-NEXT: ; %bb.1:
; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, vcc_lo ; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, vcc_lo
; GFX10-WAVE32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v0 ; GFX10-WAVE32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v0
; GFX10-WAVE32-NEXT: s_andn2_b32 s0, s0, vcc_lo ; GFX10-WAVE32-NEXT: s_andn2_b32 s0, s0, vcc_lo
; GFX10-WAVE32-NEXT: s_cbranch_scc0 BB4_2 ; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB4_2
; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: s_endpgm
; GFX10-WAVE32-NEXT: BB4_2: ; GFX10-WAVE32-NEXT: .LBB4_2:
; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm ; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm
; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: s_endpgm
%cmp = fcmp olt float %x, 0.0 %cmp = fcmp olt float %x, 0.0
call void @llvm.amdgcn.kill(i1 %cmp) call void @llvm.amdgcn.kill(i1 %cmp)
call void @llvm.amdgcn.kill(i1 %cmp) call void @llvm.amdgcn.kill(i1 %cmp)
ret void ret void
} }
; FIXME: Ideally only one early-exit would be emitted ; FIXME: Ideally only one early-exit would be emitted
define amdgpu_ps void @test_kill_depth_var_x2(float %x, float %y) #0 { define amdgpu_ps void @test_kill_depth_var_x2(float %x, float %y) #0 {
; SI-LABEL: test_kill_depth_var_x2: ; SI-LABEL: test_kill_depth_var_x2:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_mov_b64 s[0:1], exec ; SI-NEXT: s_mov_b64 s[0:1], exec
; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0 ; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0
; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc ; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc
; SI-NEXT: s_cbranch_scc0 BB5_2 ; SI-NEXT: s_cbranch_scc0 .LBB5_2
; SI-NEXT: ; %bb.1: ; SI-NEXT: ; %bb.1:
; SI-NEXT: s_andn2_b64 exec, exec, vcc ; SI-NEXT: s_andn2_b64 exec, exec, vcc
; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v1 ; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v1
; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc ; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc
; SI-NEXT: s_cbranch_scc0 BB5_2 ; SI-NEXT: s_cbranch_scc0 .LBB5_2
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; SI-NEXT: BB5_2: ; SI-NEXT: .LBB5_2:
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: exp null off, off, off, off done vm ; SI-NEXT: exp null off, off, off, off done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; GFX10-WAVE64-LABEL: test_kill_depth_var_x2: ; GFX10-WAVE64-LABEL: test_kill_depth_var_x2:
; GFX10-WAVE64: ; %bb.0: ; GFX10-WAVE64: ; %bb.0:
; GFX10-WAVE64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0 ; GFX10-WAVE64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0
; GFX10-WAVE64-NEXT: s_mov_b64 s[0:1], exec ; GFX10-WAVE64-NEXT: s_mov_b64 s[0:1], exec
; GFX10-WAVE64-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc ; GFX10-WAVE64-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc
; GFX10-WAVE64-NEXT: s_cbranch_scc0 BB5_2 ; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB5_2
; GFX10-WAVE64-NEXT: ; %bb.1: ; GFX10-WAVE64-NEXT: ; %bb.1:
; GFX10-WAVE64-NEXT: s_andn2_b64 exec, exec, vcc ; GFX10-WAVE64-NEXT: s_andn2_b64 exec, exec, vcc
; GFX10-WAVE64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v1 ; GFX10-WAVE64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v1
; GFX10-WAVE64-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc ; GFX10-WAVE64-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc
; GFX10-WAVE64-NEXT: s_cbranch_scc0 BB5_2 ; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB5_2
; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: s_endpgm
; GFX10-WAVE64-NEXT: BB5_2: ; GFX10-WAVE64-NEXT: .LBB5_2:
; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0 ; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0
; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm ; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm
; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: s_endpgm
; ;
; GFX10-WAVE32-LABEL: test_kill_depth_var_x2: ; GFX10-WAVE32-LABEL: test_kill_depth_var_x2:
; GFX10-WAVE32: ; %bb.0: ; GFX10-WAVE32: ; %bb.0:
; GFX10-WAVE32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v0 ; GFX10-WAVE32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v0
; GFX10-WAVE32-NEXT: s_mov_b32 s0, exec_lo ; GFX10-WAVE32-NEXT: s_mov_b32 s0, exec_lo
; GFX10-WAVE32-NEXT: s_andn2_b32 s0, s0, vcc_lo ; GFX10-WAVE32-NEXT: s_andn2_b32 s0, s0, vcc_lo
; GFX10-WAVE32-NEXT: s_cbranch_scc0 BB5_2 ; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB5_2
; GFX10-WAVE32-NEXT: ; %bb.1: ; GFX10-WAVE32-NEXT: ; %bb.1:
; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, vcc_lo ; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, vcc_lo
; GFX10-WAVE32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v1 ; GFX10-WAVE32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v1
; GFX10-WAVE32-NEXT: s_andn2_b32 s0, s0, vcc_lo ; GFX10-WAVE32-NEXT: s_andn2_b32 s0, s0, vcc_lo
; GFX10-WAVE32-NEXT: s_cbranch_scc0 BB5_2 ; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB5_2
; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: s_endpgm
; GFX10-WAVE32-NEXT: BB5_2: ; GFX10-WAVE32-NEXT: .LBB5_2:
; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm ; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm
; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: s_endpgm
%cmp.x = fcmp olt float %x, 0.0 %cmp.x = fcmp olt float %x, 0.0
call void @llvm.amdgcn.kill(i1 %cmp.x) call void @llvm.amdgcn.kill(i1 %cmp.x)
%cmp.y = fcmp olt float %y, 0.0 %cmp.y = fcmp olt float %y, 0.0
call void @llvm.amdgcn.kill(i1 %cmp.y) call void @llvm.amdgcn.kill(i1 %cmp.y)
ret void ret void
} }
define amdgpu_ps void @test_kill_depth_var_x2_instructions(float %x) #0 { define amdgpu_ps void @test_kill_depth_var_x2_instructions(float %x) #0 {
; SI-LABEL: test_kill_depth_var_x2_instructions: ; SI-LABEL: test_kill_depth_var_x2_instructions:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_mov_b64 s[0:1], exec ; SI-NEXT: s_mov_b64 s[0:1], exec
; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0 ; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0
; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc ; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc
; SI-NEXT: s_cbranch_scc0 BB6_2 ; SI-NEXT: s_cbranch_scc0 .LBB6_2
; SI-NEXT: ; %bb.1: ; SI-NEXT: ; %bb.1:
; SI-NEXT: s_andn2_b64 exec, exec, vcc ; SI-NEXT: s_andn2_b64 exec, exec, vcc
; SI-NEXT: ;;#ASMSTART ; SI-NEXT: ;;#ASMSTART
; SI-NEXT: v_mov_b32_e64 v7, -1 ; SI-NEXT: v_mov_b32_e64 v7, -1
; SI-NEXT: ;;#ASMEND ; SI-NEXT: ;;#ASMEND
; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v7 ; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v7
; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc ; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc
; SI-NEXT: s_cbranch_scc0 BB6_2 ; SI-NEXT: s_cbranch_scc0 .LBB6_2
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; SI-NEXT: BB6_2: ; SI-NEXT: .LBB6_2:
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: exp null off, off, off, off done vm ; SI-NEXT: exp null off, off, off, off done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; GFX10-WAVE64-LABEL: test_kill_depth_var_x2_instructions: ; GFX10-WAVE64-LABEL: test_kill_depth_var_x2_instructions:
; GFX10-WAVE64: ; %bb.0: ; GFX10-WAVE64: ; %bb.0:
; GFX10-WAVE64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0 ; GFX10-WAVE64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0
; GFX10-WAVE64-NEXT: s_mov_b64 s[0:1], exec ; GFX10-WAVE64-NEXT: s_mov_b64 s[0:1], exec
; GFX10-WAVE64-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc ; GFX10-WAVE64-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc
; GFX10-WAVE64-NEXT: s_cbranch_scc0 BB6_2 ; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB6_2
; GFX10-WAVE64-NEXT: ; %bb.1: ; GFX10-WAVE64-NEXT: ; %bb.1:
; GFX10-WAVE64-NEXT: s_andn2_b64 exec, exec, vcc ; GFX10-WAVE64-NEXT: s_andn2_b64 exec, exec, vcc
; GFX10-WAVE64-NEXT: ;;#ASMSTART ; GFX10-WAVE64-NEXT: ;;#ASMSTART
; GFX10-WAVE64-NEXT: v_mov_b32_e64 v7, -1 ; GFX10-WAVE64-NEXT: v_mov_b32_e64 v7, -1
; GFX10-WAVE64-NEXT: ;;#ASMEND ; GFX10-WAVE64-NEXT: ;;#ASMEND
; GFX10-WAVE64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v7 ; GFX10-WAVE64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v7
; GFX10-WAVE64-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc ; GFX10-WAVE64-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc
; GFX10-WAVE64-NEXT: s_cbranch_scc0 BB6_2 ; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB6_2
; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: s_endpgm
; GFX10-WAVE64-NEXT: BB6_2: ; GFX10-WAVE64-NEXT: .LBB6_2:
; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0 ; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0
; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm ; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm
; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: s_endpgm
; ;
; GFX10-WAVE32-LABEL: test_kill_depth_var_x2_instructions: ; GFX10-WAVE32-LABEL: test_kill_depth_var_x2_instructions:
; GFX10-WAVE32: ; %bb.0: ; GFX10-WAVE32: ; %bb.0:
; GFX10-WAVE32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v0 ; GFX10-WAVE32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v0
; GFX10-WAVE32-NEXT: s_mov_b32 s0, exec_lo ; GFX10-WAVE32-NEXT: s_mov_b32 s0, exec_lo
; GFX10-WAVE32-NEXT: s_andn2_b32 s0, s0, vcc_lo ; GFX10-WAVE32-NEXT: s_andn2_b32 s0, s0, vcc_lo
; GFX10-WAVE32-NEXT: s_cbranch_scc0 BB6_2 ; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB6_2
; GFX10-WAVE32-NEXT: ; %bb.1: ; GFX10-WAVE32-NEXT: ; %bb.1:
; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, vcc_lo ; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, vcc_lo
; GFX10-WAVE32-NEXT: ;;#ASMSTART ; GFX10-WAVE32-NEXT: ;;#ASMSTART
; GFX10-WAVE32-NEXT: v_mov_b32_e64 v7, -1 ; GFX10-WAVE32-NEXT: v_mov_b32_e64 v7, -1
; GFX10-WAVE32-NEXT: ;;#ASMEND ; GFX10-WAVE32-NEXT: ;;#ASMEND
; GFX10-WAVE32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v7 ; GFX10-WAVE32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v7
; GFX10-WAVE32-NEXT: s_andn2_b32 s0, s0, vcc_lo ; GFX10-WAVE32-NEXT: s_andn2_b32 s0, s0, vcc_lo
; GFX10-WAVE32-NEXT: s_cbranch_scc0 BB6_2 ; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB6_2
; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: s_endpgm
; GFX10-WAVE32-NEXT: BB6_2: ; GFX10-WAVE32-NEXT: .LBB6_2:
; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm ; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm
; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: s_endpgm
%cmp.x = fcmp olt float %x, 0.0 %cmp.x = fcmp olt float %x, 0.0
call void @llvm.amdgcn.kill(i1 %cmp.x) call void @llvm.amdgcn.kill(i1 %cmp.x)
%y = call float asm sideeffect "v_mov_b32_e64 v7, -1", "={v7}"() %y = call float asm sideeffect "v_mov_b32_e64 v7, -1", "={v7}"()
%cmp.y = fcmp olt float %y, 0.0 %cmp.y = fcmp olt float %y, 0.0
call void @llvm.amdgcn.kill(i1 %cmp.y) call void @llvm.amdgcn.kill(i1 %cmp.y)
ret void ret void
} }
; FIXME: why does the skip depend on the asm length in the same block? ; FIXME: why does the skip depend on the asm length in the same block?
define amdgpu_ps float @test_kill_control_flow(i32 inreg %arg) #0 { define amdgpu_ps float @test_kill_control_flow(i32 inreg %arg) #0 {
; SI-LABEL: test_kill_control_flow: ; SI-LABEL: test_kill_control_flow:
; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: s_cmp_lg_u32 s0, 0 ; SI-NEXT: s_cmp_lg_u32 s0, 0
; SI-NEXT: s_cbranch_scc0 BB7_2 ; SI-NEXT: s_cbranch_scc0 .LBB7_2
; SI-NEXT: ; %bb.1: ; %exit ; SI-NEXT: ; %bb.1: ; %exit
; SI-NEXT: v_mov_b32_e32 v0, 1.0 ; SI-NEXT: v_mov_b32_e32 v0, 1.0
; SI-NEXT: s_branch BB7_5 ; SI-NEXT: s_branch .LBB7_5
; SI-NEXT: BB7_2: ; %bb ; SI-NEXT: .LBB7_2: ; %bb
; SI-NEXT: s_mov_b64 s[2:3], exec ; SI-NEXT: s_mov_b64 s[2:3], exec
; SI-NEXT: ;;#ASMSTART ; SI-NEXT: ;;#ASMSTART
; SI-NEXT: v_mov_b32_e64 v7, -1 ; SI-NEXT: v_mov_b32_e64 v7, -1
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: ;;#ASMEND ; SI-NEXT: ;;#ASMEND
; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v7 ; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v7
; SI-NEXT: s_andn2_b64 s[2:3], s[2:3], vcc ; SI-NEXT: s_andn2_b64 s[2:3], s[2:3], vcc
; SI-NEXT: s_cbranch_scc0 BB7_4 ; SI-NEXT: s_cbranch_scc0 .LBB7_4
; SI-NEXT: ; %bb.3: ; %bb ; SI-NEXT: ; %bb.3: ; %bb
; SI-NEXT: s_andn2_b64 exec, exec, vcc ; SI-NEXT: s_andn2_b64 exec, exec, vcc
; SI-NEXT: v_mov_b32_e32 v0, 1.0 ; SI-NEXT: v_mov_b32_e32 v0, 1.0
; SI-NEXT: s_branch BB7_5 ; SI-NEXT: s_branch .LBB7_5
; SI-NEXT: BB7_4: ; SI-NEXT: .LBB7_4:
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: exp null off, off, off, off done vm ; SI-NEXT: exp null off, off, off, off done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; SI-NEXT: BB7_5: ; SI-NEXT: .LBB7_5:
; ;
; GFX10-WAVE64-LABEL: test_kill_control_flow: ; GFX10-WAVE64-LABEL: test_kill_control_flow:
; GFX10-WAVE64: ; %bb.0: ; %entry ; GFX10-WAVE64: ; %bb.0: ; %entry
; GFX10-WAVE64-NEXT: s_cmp_lg_u32 s0, 0 ; GFX10-WAVE64-NEXT: s_cmp_lg_u32 s0, 0
; GFX10-WAVE64-NEXT: s_cbranch_scc0 BB7_2 ; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB7_2
; GFX10-WAVE64-NEXT: ; %bb.1: ; %exit ; GFX10-WAVE64-NEXT: ; %bb.1: ; %exit
; GFX10-WAVE64-NEXT: v_mov_b32_e32 v0, 1.0 ; GFX10-WAVE64-NEXT: v_mov_b32_e32 v0, 1.0
; GFX10-WAVE64-NEXT: s_branch BB7_5 ; GFX10-WAVE64-NEXT: s_branch .LBB7_5
; GFX10-WAVE64-NEXT: BB7_2: ; %bb ; GFX10-WAVE64-NEXT: .LBB7_2: ; %bb
; GFX10-WAVE64-NEXT: ;;#ASMSTART ; GFX10-WAVE64-NEXT: ;;#ASMSTART
; GFX10-WAVE64-NEXT: v_mov_b32_e64 v7, -1 ; GFX10-WAVE64-NEXT: v_mov_b32_e64 v7, -1
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: ;;#ASMEND ; GFX10-WAVE64-NEXT: ;;#ASMEND
; GFX10-WAVE64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v7 ; GFX10-WAVE64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v7
; GFX10-WAVE64-NEXT: s_mov_b64 s[2:3], exec ; GFX10-WAVE64-NEXT: s_mov_b64 s[2:3], exec
; GFX10-WAVE64-NEXT: s_andn2_b64 s[2:3], s[2:3], vcc ; GFX10-WAVE64-NEXT: s_andn2_b64 s[2:3], s[2:3], vcc
; GFX10-WAVE64-NEXT: s_cbranch_scc0 BB7_4 ; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB7_4
; GFX10-WAVE64-NEXT: ; %bb.3: ; %bb ; GFX10-WAVE64-NEXT: ; %bb.3: ; %bb
; GFX10-WAVE64-NEXT: s_andn2_b64 exec, exec, vcc ; GFX10-WAVE64-NEXT: s_andn2_b64 exec, exec, vcc
; GFX10-WAVE64-NEXT: v_mov_b32_e32 v0, 1.0 ; GFX10-WAVE64-NEXT: v_mov_b32_e32 v0, 1.0
; GFX10-WAVE64-NEXT: s_branch BB7_5 ; GFX10-WAVE64-NEXT: s_branch .LBB7_5
; GFX10-WAVE64-NEXT: BB7_4: ; GFX10-WAVE64-NEXT: .LBB7_4:
; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0 ; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0
; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm ; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm
; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: s_endpgm
; GFX10-WAVE64-NEXT: BB7_5: ; GFX10-WAVE64-NEXT: .LBB7_5:
; ;
; GFX10-WAVE32-LABEL: test_kill_control_flow: ; GFX10-WAVE32-LABEL: test_kill_control_flow:
; GFX10-WAVE32: ; %bb.0: ; %entry ; GFX10-WAVE32: ; %bb.0: ; %entry
; GFX10-WAVE32-NEXT: s_cmp_lg_u32 s0, 0 ; GFX10-WAVE32-NEXT: s_cmp_lg_u32 s0, 0
; GFX10-WAVE32-NEXT: s_cbranch_scc0 BB7_2 ; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB7_2
; GFX10-WAVE32-NEXT: ; %bb.1: ; %exit ; GFX10-WAVE32-NEXT: ; %bb.1: ; %exit
; GFX10-WAVE32-NEXT: v_mov_b32_e32 v0, 1.0 ; GFX10-WAVE32-NEXT: v_mov_b32_e32 v0, 1.0
; GFX10-WAVE32-NEXT: s_branch BB7_5 ; GFX10-WAVE32-NEXT: s_branch .LBB7_5
; GFX10-WAVE32-NEXT: BB7_2: ; %bb ; GFX10-WAVE32-NEXT: .LBB7_2: ; %bb
; GFX10-WAVE32-NEXT: ;;#ASMSTART ; GFX10-WAVE32-NEXT: ;;#ASMSTART
; GFX10-WAVE32-NEXT: v_mov_b32_e64 v7, -1 ; GFX10-WAVE32-NEXT: v_mov_b32_e64 v7, -1
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: ;;#ASMEND ; GFX10-WAVE32-NEXT: ;;#ASMEND
; GFX10-WAVE32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v7 ; GFX10-WAVE32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v7
; GFX10-WAVE32-NEXT: s_mov_b32 s1, exec_lo ; GFX10-WAVE32-NEXT: s_mov_b32 s1, exec_lo
; GFX10-WAVE32-NEXT: s_andn2_b32 s1, s1, vcc_lo ; GFX10-WAVE32-NEXT: s_andn2_b32 s1, s1, vcc_lo
; GFX10-WAVE32-NEXT: s_cbranch_scc0 BB7_4 ; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB7_4
; GFX10-WAVE32-NEXT: ; %bb.3: ; %bb ; GFX10-WAVE32-NEXT: ; %bb.3: ; %bb
; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, vcc_lo ; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, vcc_lo
; GFX10-WAVE32-NEXT: v_mov_b32_e32 v0, 1.0 ; GFX10-WAVE32-NEXT: v_mov_b32_e32 v0, 1.0
; GFX10-WAVE32-NEXT: s_branch BB7_5 ; GFX10-WAVE32-NEXT: s_branch .LBB7_5
; GFX10-WAVE32-NEXT: BB7_4: ; GFX10-WAVE32-NEXT: .LBB7_4:
; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm ; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm
; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: s_endpgm
; GFX10-WAVE32-NEXT: BB7_5: ; GFX10-WAVE32-NEXT: .LBB7_5:
entry: entry:
%cmp = icmp eq i32 %arg, 0 %cmp = icmp eq i32 %arg, 0
br i1 %cmp, label %bb, label %exit br i1 %cmp, label %bb, label %exit
bb: bb:
%var = call float asm sideeffect "v_mov_b32_e64 v7, -1 %var = call float asm sideeffect "v_mov_b32_e64 v7, -1
v_nop_e64 v_nop_e64
v_nop_e64 v_nop_e64
Show All 14 Linesexit:
ret float 1.0 ret float 1.0
} }
define amdgpu_ps void @test_kill_control_flow_remainder(i32 inreg %arg) #0 { define amdgpu_ps void @test_kill_control_flow_remainder(i32 inreg %arg) #0 {
; SI-LABEL: test_kill_control_flow_remainder: ; SI-LABEL: test_kill_control_flow_remainder:
; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: s_cmp_lg_u32 s0, 0 ; SI-NEXT: s_cmp_lg_u32 s0, 0
; SI-NEXT: v_mov_b32_e32 v9, 0 ; SI-NEXT: v_mov_b32_e32 v9, 0
; SI-NEXT: s_cbranch_scc1 BB8_3 ; SI-NEXT: s_cbranch_scc1 .LBB8_3
; SI-NEXT: ; %bb.1: ; %bb ; SI-NEXT: ; %bb.1: ; %bb
; SI-NEXT: s_mov_b64 s[2:3], exec ; SI-NEXT: s_mov_b64 s[2:3], exec
; SI-NEXT: ;;#ASMSTART ; SI-NEXT: ;;#ASMSTART
; SI-NEXT: v_mov_b32_e64 v7, -1 ; SI-NEXT: v_mov_b32_e64 v7, -1
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: ;;#ASMEND ; SI-NEXT: ;;#ASMEND
; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v7 ; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v7
; SI-NEXT: s_andn2_b64 s[2:3], s[2:3], vcc ; SI-NEXT: s_andn2_b64 s[2:3], s[2:3], vcc
; SI-NEXT: ;;#ASMSTART ; SI-NEXT: ;;#ASMSTART
; SI-NEXT: v_mov_b32_e64 v8, -1 ; SI-NEXT: v_mov_b32_e64 v8, -1
; SI-NEXT: ;;#ASMEND ; SI-NEXT: ;;#ASMEND
; SI-NEXT: s_cbranch_scc0 BB8_4 ; SI-NEXT: s_cbranch_scc0 .LBB8_4
; SI-NEXT: ; %bb.2: ; %bb ; SI-NEXT: ; %bb.2: ; %bb
; SI-NEXT: s_andn2_b64 exec, exec, vcc ; SI-NEXT: s_andn2_b64 exec, exec, vcc
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: buffer_store_dword v8, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v8, off, s[0:3], 0
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: ;;#ASMSTART ; SI-NEXT: ;;#ASMSTART
; SI-NEXT: v_mov_b32_e64 v9, -2 ; SI-NEXT: v_mov_b32_e64 v9, -2
; SI-NEXT: ;;#ASMEND ; SI-NEXT: ;;#ASMEND
; SI-NEXT: BB8_3: ; %exit ; SI-NEXT: .LBB8_3: ; %exit
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; SI-NEXT: BB8_4: ; SI-NEXT: .LBB8_4:
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: exp null off, off, off, off done vm ; SI-NEXT: exp null off, off, off, off done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; GFX10-WAVE64-LABEL: test_kill_control_flow_remainder: ; GFX10-WAVE64-LABEL: test_kill_control_flow_remainder:
; GFX10-WAVE64: ; %bb.0: ; %entry ; GFX10-WAVE64: ; %bb.0: ; %entry
; GFX10-WAVE64-NEXT: v_mov_b32_e32 v9, 0 ; GFX10-WAVE64-NEXT: v_mov_b32_e32 v9, 0
; GFX10-WAVE64-NEXT: s_cmp_lg_u32 s0, 0 ; GFX10-WAVE64-NEXT: s_cmp_lg_u32 s0, 0
; GFX10-WAVE64-NEXT: s_cbranch_scc0 BB8_2 ; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB8_2
; GFX10-WAVE64-NEXT: ; %bb.1: ; %exit ; GFX10-WAVE64-NEXT: ; %bb.1: ; %exit
; GFX10-WAVE64-NEXT: global_store_dword v[0:1], v9, off ; GFX10-WAVE64-NEXT: global_store_dword v[0:1], v9, off
; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: s_endpgm
; GFX10-WAVE64-NEXT: BB8_2: ; %bb ; GFX10-WAVE64-NEXT: .LBB8_2: ; %bb
; GFX10-WAVE64-NEXT: ;;#ASMSTART ; GFX10-WAVE64-NEXT: ;;#ASMSTART
; GFX10-WAVE64-NEXT: v_mov_b32_e64 v7, -1 ; GFX10-WAVE64-NEXT: v_mov_b32_e64 v7, -1
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: ;;#ASMEND ; GFX10-WAVE64-NEXT: ;;#ASMEND
; GFX10-WAVE64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v7 ; GFX10-WAVE64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v7
; GFX10-WAVE64-NEXT: s_mov_b64 s[2:3], exec ; GFX10-WAVE64-NEXT: s_mov_b64 s[2:3], exec
; GFX10-WAVE64-NEXT: ;;#ASMSTART ; GFX10-WAVE64-NEXT: ;;#ASMSTART
; GFX10-WAVE64-NEXT: v_mov_b32_e64 v8, -1 ; GFX10-WAVE64-NEXT: v_mov_b32_e64 v8, -1
; GFX10-WAVE64-NEXT: ;;#ASMEND ; GFX10-WAVE64-NEXT: ;;#ASMEND
; GFX10-WAVE64-NEXT: s_andn2_b64 s[2:3], s[2:3], vcc ; GFX10-WAVE64-NEXT: s_andn2_b64 s[2:3], s[2:3], vcc
; GFX10-WAVE64-NEXT: s_cbranch_scc0 BB8_4 ; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB8_4
; GFX10-WAVE64-NEXT: ; %bb.3: ; %bb ; GFX10-WAVE64-NEXT: ; %bb.3: ; %bb
; GFX10-WAVE64-NEXT: s_andn2_b64 exec, exec, vcc ; GFX10-WAVE64-NEXT: s_andn2_b64 exec, exec, vcc
; GFX10-WAVE64-NEXT: global_store_dword v[0:1], v8, off ; GFX10-WAVE64-NEXT: global_store_dword v[0:1], v8, off
; GFX10-WAVE64-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-WAVE64-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WAVE64-NEXT: ;;#ASMSTART ; GFX10-WAVE64-NEXT: ;;#ASMSTART
; GFX10-WAVE64-NEXT: v_mov_b32_e64 v9, -2 ; GFX10-WAVE64-NEXT: v_mov_b32_e64 v9, -2
; GFX10-WAVE64-NEXT: ;;#ASMEND ; GFX10-WAVE64-NEXT: ;;#ASMEND
; GFX10-WAVE64-NEXT: global_store_dword v[0:1], v9, off ; GFX10-WAVE64-NEXT: global_store_dword v[0:1], v9, off
; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: s_endpgm
; GFX10-WAVE64-NEXT: BB8_4: ; GFX10-WAVE64-NEXT: .LBB8_4:
; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0 ; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0
; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm ; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm
; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: s_endpgm
; ;
; GFX10-WAVE32-LABEL: test_kill_control_flow_remainder: ; GFX10-WAVE32-LABEL: test_kill_control_flow_remainder:
; GFX10-WAVE32: ; %bb.0: ; %entry ; GFX10-WAVE32: ; %bb.0: ; %entry
; GFX10-WAVE32-NEXT: v_mov_b32_e32 v9, 0 ; GFX10-WAVE32-NEXT: v_mov_b32_e32 v9, 0
; GFX10-WAVE32-NEXT: s_cmp_lg_u32 s0, 0 ; GFX10-WAVE32-NEXT: s_cmp_lg_u32 s0, 0
; GFX10-WAVE32-NEXT: s_cbranch_scc0 BB8_2 ; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB8_2
; GFX10-WAVE32-NEXT: ; %bb.1: ; %exit ; GFX10-WAVE32-NEXT: ; %bb.1: ; %exit
; GFX10-WAVE32-NEXT: global_store_dword v[0:1], v9, off ; GFX10-WAVE32-NEXT: global_store_dword v[0:1], v9, off
; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: s_endpgm
; GFX10-WAVE32-NEXT: BB8_2: ; %bb ; GFX10-WAVE32-NEXT: .LBB8_2: ; %bb
; GFX10-WAVE32-NEXT: ;;#ASMSTART ; GFX10-WAVE32-NEXT: ;;#ASMSTART
; GFX10-WAVE32-NEXT: v_mov_b32_e64 v7, -1 ; GFX10-WAVE32-NEXT: v_mov_b32_e64 v7, -1
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: ;;#ASMEND ; GFX10-WAVE32-NEXT: ;;#ASMEND
; GFX10-WAVE32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v7 ; GFX10-WAVE32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v7
; GFX10-WAVE32-NEXT: s_mov_b32 s1, exec_lo ; GFX10-WAVE32-NEXT: s_mov_b32 s1, exec_lo
; GFX10-WAVE32-NEXT: ;;#ASMSTART ; GFX10-WAVE32-NEXT: ;;#ASMSTART
; GFX10-WAVE32-NEXT: v_mov_b32_e64 v8, -1 ; GFX10-WAVE32-NEXT: v_mov_b32_e64 v8, -1
; GFX10-WAVE32-NEXT: ;;#ASMEND ; GFX10-WAVE32-NEXT: ;;#ASMEND
; GFX10-WAVE32-NEXT: s_andn2_b32 s1, s1, vcc_lo ; GFX10-WAVE32-NEXT: s_andn2_b32 s1, s1, vcc_lo
; GFX10-WAVE32-NEXT: s_cbranch_scc0 BB8_4 ; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB8_4
; GFX10-WAVE32-NEXT: ; %bb.3: ; %bb ; GFX10-WAVE32-NEXT: ; %bb.3: ; %bb
; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, vcc_lo ; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, vcc_lo
; GFX10-WAVE32-NEXT: global_store_dword v[0:1], v8, off ; GFX10-WAVE32-NEXT: global_store_dword v[0:1], v8, off
; GFX10-WAVE32-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-WAVE32-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WAVE32-NEXT: ;;#ASMSTART ; GFX10-WAVE32-NEXT: ;;#ASMSTART
; GFX10-WAVE32-NEXT: v_mov_b32_e64 v9, -2 ; GFX10-WAVE32-NEXT: v_mov_b32_e64 v9, -2
; GFX10-WAVE32-NEXT: ;;#ASMEND ; GFX10-WAVE32-NEXT: ;;#ASMEND
; GFX10-WAVE32-NEXT: global_store_dword v[0:1], v9, off ; GFX10-WAVE32-NEXT: global_store_dword v[0:1], v9, off
; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: s_endpgm
; GFX10-WAVE32-NEXT: BB8_4: ; GFX10-WAVE32-NEXT: .LBB8_4:
; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm ; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm
; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: s_endpgm
entry: entry:
%cmp = icmp eq i32 %arg, 0 %cmp = icmp eq i32 %arg, 0
br i1 %cmp, label %bb, label %exit br i1 %cmp, label %bb, label %exit
bb: bb:
Show All 26 Lines
define amdgpu_ps float @test_kill_control_flow_return(i32 inreg %arg) #0 { define amdgpu_ps float @test_kill_control_flow_return(i32 inreg %arg) #0 {
; SI-LABEL: test_kill_control_flow_return: ; SI-LABEL: test_kill_control_flow_return:
; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: s_cmp_eq_u32 s0, 1 ; SI-NEXT: s_cmp_eq_u32 s0, 1
; SI-NEXT: s_cselect_b64 s[4:5], -1, 0 ; SI-NEXT: s_cselect_b64 s[4:5], -1, 0
; SI-NEXT: s_mov_b64 s[2:3], exec ; SI-NEXT: s_mov_b64 s[2:3], exec
; SI-NEXT: s_xor_b64 s[4:5], s[4:5], exec ; SI-NEXT: s_xor_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_andn2_b64 s[2:3], s[2:3], s[4:5] ; SI-NEXT: s_andn2_b64 s[2:3], s[2:3], s[4:5]
; SI-NEXT: s_cbranch_scc0 BB9_4 ; SI-NEXT: s_cbranch_scc0 .LBB9_4
; SI-NEXT: ; %bb.1: ; %entry ; SI-NEXT: ; %bb.1: ; %entry
; SI-NEXT: s_and_b64 exec, exec, s[2:3] ; SI-NEXT: s_and_b64 exec, exec, s[2:3]
; SI-NEXT: s_cmp_lg_u32 s0, 0 ; SI-NEXT: s_cmp_lg_u32 s0, 0
; SI-NEXT: v_mov_b32_e32 v0, 0 ; SI-NEXT: v_mov_b32_e32 v0, 0
; SI-NEXT: s_cbranch_scc0 BB9_3 ; SI-NEXT: s_cbranch_scc0 .LBB9_3
; SI-NEXT: ; %bb.2: ; %exit ; SI-NEXT: ; %bb.2: ; %exit
; SI-NEXT: s_branch BB9_5 ; SI-NEXT: s_branch .LBB9_5
; SI-NEXT: BB9_3: ; %bb ; SI-NEXT: .LBB9_3: ; %bb
; SI-NEXT: ;;#ASMSTART ; SI-NEXT: ;;#ASMSTART
; SI-NEXT: v_mov_b32_e64 v7, -1 ; SI-NEXT: v_mov_b32_e64 v7, -1
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: ;;#ASMEND ; SI-NEXT: ;;#ASMEND
; SI-NEXT: v_mov_b32_e32 v0, v7 ; SI-NEXT: v_mov_b32_e32 v0, v7
; SI-NEXT: s_branch BB9_5 ; SI-NEXT: s_branch .LBB9_5
; SI-NEXT: BB9_4: ; SI-NEXT: .LBB9_4:
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: exp null off, off, off, off done vm ; SI-NEXT: exp null off, off, off, off done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; SI-NEXT: BB9_5: ; SI-NEXT: .LBB9_5:
; ;
; GFX10-WAVE64-LABEL: test_kill_control_flow_return: ; GFX10-WAVE64-LABEL: test_kill_control_flow_return:
; GFX10-WAVE64: ; %bb.0: ; %entry ; GFX10-WAVE64: ; %bb.0: ; %entry
; GFX10-WAVE64-NEXT: s_cmp_eq_u32 s0, 1 ; GFX10-WAVE64-NEXT: s_cmp_eq_u32 s0, 1
; GFX10-WAVE64-NEXT: s_mov_b64 s[2:3], exec ; GFX10-WAVE64-NEXT: s_mov_b64 s[2:3], exec
; GFX10-WAVE64-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GFX10-WAVE64-NEXT: s_cselect_b64 s[4:5], -1, 0
; GFX10-WAVE64-NEXT: s_xor_b64 s[4:5], s[4:5], exec ; GFX10-WAVE64-NEXT: s_xor_b64 s[4:5], s[4:5], exec
; GFX10-WAVE64-NEXT: s_andn2_b64 s[2:3], s[2:3], s[4:5] ; GFX10-WAVE64-NEXT: s_andn2_b64 s[2:3], s[2:3], s[4:5]
; GFX10-WAVE64-NEXT: s_cbranch_scc0 BB9_4 ; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB9_4
; GFX10-WAVE64-NEXT: ; %bb.1: ; %entry ; GFX10-WAVE64-NEXT: ; %bb.1: ; %entry
; GFX10-WAVE64-NEXT: s_and_b64 exec, exec, s[2:3] ; GFX10-WAVE64-NEXT: s_and_b64 exec, exec, s[2:3]
; GFX10-WAVE64-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-WAVE64-NEXT: v_mov_b32_e32 v0, 0
; GFX10-WAVE64-NEXT: s_cmp_lg_u32 s0, 0 ; GFX10-WAVE64-NEXT: s_cmp_lg_u32 s0, 0
; GFX10-WAVE64-NEXT: s_cbranch_scc0 BB9_3 ; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB9_3
; GFX10-WAVE64-NEXT: ; %bb.2: ; %exit ; GFX10-WAVE64-NEXT: ; %bb.2: ; %exit
; GFX10-WAVE64-NEXT: s_branch BB9_5 ; GFX10-WAVE64-NEXT: s_branch .LBB9_5
; GFX10-WAVE64-NEXT: BB9_3: ; %bb ; GFX10-WAVE64-NEXT: .LBB9_3: ; %bb
; GFX10-WAVE64-NEXT: ;;#ASMSTART ; GFX10-WAVE64-NEXT: ;;#ASMSTART
; GFX10-WAVE64-NEXT: v_mov_b32_e64 v7, -1 ; GFX10-WAVE64-NEXT: v_mov_b32_e64 v7, -1
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: ;;#ASMEND ; GFX10-WAVE64-NEXT: ;;#ASMEND
; GFX10-WAVE64-NEXT: v_mov_b32_e32 v0, v7 ; GFX10-WAVE64-NEXT: v_mov_b32_e32 v0, v7
; GFX10-WAVE64-NEXT: s_branch BB9_5 ; GFX10-WAVE64-NEXT: s_branch .LBB9_5
; GFX10-WAVE64-NEXT: BB9_4: ; GFX10-WAVE64-NEXT: .LBB9_4:
; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0 ; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0
; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm ; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm
; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: s_endpgm
; GFX10-WAVE64-NEXT: BB9_5: ; GFX10-WAVE64-NEXT: .LBB9_5:
; ;
; GFX10-WAVE32-LABEL: test_kill_control_flow_return: ; GFX10-WAVE32-LABEL: test_kill_control_flow_return:
; GFX10-WAVE32: ; %bb.0: ; %entry ; GFX10-WAVE32: ; %bb.0: ; %entry
; GFX10-WAVE32-NEXT: s_cmp_eq_u32 s0, 1 ; GFX10-WAVE32-NEXT: s_cmp_eq_u32 s0, 1
; GFX10-WAVE32-NEXT: s_mov_b32 s1, exec_lo ; GFX10-WAVE32-NEXT: s_mov_b32 s1, exec_lo
; GFX10-WAVE32-NEXT: s_cselect_b32 s2, -1, 0 ; GFX10-WAVE32-NEXT: s_cselect_b32 s2, -1, 0
; GFX10-WAVE32-NEXT: s_xor_b32 s2, s2, exec_lo ; GFX10-WAVE32-NEXT: s_xor_b32 s2, s2, exec_lo
; GFX10-WAVE32-NEXT: s_andn2_b32 s1, s1, s2 ; GFX10-WAVE32-NEXT: s_andn2_b32 s1, s1, s2
; GFX10-WAVE32-NEXT: s_cbranch_scc0 BB9_4 ; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB9_4
; GFX10-WAVE32-NEXT: ; %bb.1: ; %entry ; GFX10-WAVE32-NEXT: ; %bb.1: ; %entry
; GFX10-WAVE32-NEXT: s_and_b32 exec_lo, exec_lo, s1 ; GFX10-WAVE32-NEXT: s_and_b32 exec_lo, exec_lo, s1
; GFX10-WAVE32-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-WAVE32-NEXT: v_mov_b32_e32 v0, 0
; GFX10-WAVE32-NEXT: s_cmp_lg_u32 s0, 0 ; GFX10-WAVE32-NEXT: s_cmp_lg_u32 s0, 0
; GFX10-WAVE32-NEXT: s_cbranch_scc0 BB9_3 ; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB9_3
; GFX10-WAVE32-NEXT: ; %bb.2: ; %exit ; GFX10-WAVE32-NEXT: ; %bb.2: ; %exit
; GFX10-WAVE32-NEXT: s_branch BB9_5 ; GFX10-WAVE32-NEXT: s_branch .LBB9_5
; GFX10-WAVE32-NEXT: BB9_3: ; %bb ; GFX10-WAVE32-NEXT: .LBB9_3: ; %bb
; GFX10-WAVE32-NEXT: ;;#ASMSTART ; GFX10-WAVE32-NEXT: ;;#ASMSTART
; GFX10-WAVE32-NEXT: v_mov_b32_e64 v7, -1 ; GFX10-WAVE32-NEXT: v_mov_b32_e64 v7, -1
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: ;;#ASMEND ; GFX10-WAVE32-NEXT: ;;#ASMEND
; GFX10-WAVE32-NEXT: v_mov_b32_e32 v0, v7 ; GFX10-WAVE32-NEXT: v_mov_b32_e32 v0, v7
; GFX10-WAVE32-NEXT: s_branch BB9_5 ; GFX10-WAVE32-NEXT: s_branch .LBB9_5
; GFX10-WAVE32-NEXT: BB9_4: ; GFX10-WAVE32-NEXT: .LBB9_4:
; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm ; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm
; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: s_endpgm
; GFX10-WAVE32-NEXT: BB9_5: ; GFX10-WAVE32-NEXT: .LBB9_5:
entry: entry:
%kill = icmp eq i32 %arg, 1 %kill = icmp eq i32 %arg, 1
%cmp = icmp eq i32 %arg, 0 %cmp = icmp eq i32 %arg, 0
call void @llvm.amdgcn.kill(i1 %kill) call void @llvm.amdgcn.kill(i1 %kill)
br i1 %cmp, label %bb, label %exit br i1 %cmp, label %bb, label %exit
bb: bb:
%var = call float asm sideeffect "v_mov_b32_e64 v7, -1 %var = call float asm sideeffect "v_mov_b32_e64 v7, -1
Show All 16 Lines
define amdgpu_ps void @test_kill_divergent_loop(i32 %arg) #0 { define amdgpu_ps void @test_kill_divergent_loop(i32 %arg) #0 {
; SI-LABEL: test_kill_divergent_loop: ; SI-LABEL: test_kill_divergent_loop:
; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: s_mov_b64 s[0:1], exec ; SI-NEXT: s_mov_b64 s[0:1], exec
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; SI-NEXT: s_and_saveexec_b64 s[2:3], vcc ; SI-NEXT: s_and_saveexec_b64 s[2:3], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[2:3] ; SI-NEXT: s_xor_b64 s[4:5], exec, s[2:3]
; SI-NEXT: s_cbranch_execz BB10_4 ; SI-NEXT: s_cbranch_execz .LBB10_4
; SI-NEXT: ; %bb.1: ; %bb.preheader ; SI-NEXT: ; %bb.1: ; %bb.preheader
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: BB10_2: ; %bb ; SI-NEXT: .LBB10_2: ; %bb
; SI-NEXT: ; =>This Inner Loop Header: Depth=1 ; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: ;;#ASMSTART ; SI-NEXT: ;;#ASMSTART
; SI-NEXT: v_mov_b32_e64 v7, -1 ; SI-NEXT: v_mov_b32_e64 v7, -1
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: v_nop_e64 ; SI-NEXT: v_nop_e64
; SI-NEXT: ;;#ASMEND ; SI-NEXT: ;;#ASMEND
; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v7 ; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v7
; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc ; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc
; SI-NEXT: s_cbranch_scc0 BB10_5 ; SI-NEXT: s_cbranch_scc0 .LBB10_5
; SI-NEXT: ; %bb.3: ; %bb ; SI-NEXT: ; %bb.3: ; %bb
; SI-NEXT: ; in Loop: Header=BB10_2 Depth=1 ; SI-NEXT: ; in Loop: Header=BB10_2 Depth=1
; SI-NEXT: s_andn2_b64 exec, exec, vcc ; SI-NEXT: s_andn2_b64 exec, exec, vcc
; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc ; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; SI-NEXT: s_and_b64 vcc, exec, vcc ; SI-NEXT: s_and_b64 vcc, exec, vcc
; SI-NEXT: s_cbranch_vccnz BB10_2 ; SI-NEXT: s_cbranch_vccnz .LBB10_2
; SI-NEXT: BB10_4: ; %Flow1 ; SI-NEXT: .LBB10_4: ; %Flow1
; SI-NEXT: s_or_b64 exec, exec, s[4:5] ; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: v_mov_b32_e32 v0, 8 ; SI-NEXT: v_mov_b32_e32 v0, 8
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; SI-NEXT: BB10_5: ; SI-NEXT: .LBB10_5:
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: exp null off, off, off, off done vm ; SI-NEXT: exp null off, off, off, off done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; GFX10-WAVE64-LABEL: test_kill_divergent_loop: ; GFX10-WAVE64-LABEL: test_kill_divergent_loop:
; GFX10-WAVE64: ; %bb.0: ; %entry ; GFX10-WAVE64: ; %bb.0: ; %entry
; GFX10-WAVE64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX10-WAVE64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX10-WAVE64-NEXT: s_mov_b64 s[0:1], exec ; GFX10-WAVE64-NEXT: s_mov_b64 s[0:1], exec
; GFX10-WAVE64-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX10-WAVE64-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX10-WAVE64-NEXT: s_xor_b64 s[2:3], exec, s[2:3] ; GFX10-WAVE64-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX10-WAVE64-NEXT: s_cbranch_execz BB10_3 ; GFX10-WAVE64-NEXT: s_cbranch_execz .LBB10_3
; GFX10-WAVE64-NEXT: BB10_1: ; %bb ; GFX10-WAVE64-NEXT: .LBB10_1: ; %bb
; GFX10-WAVE64-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-WAVE64-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-WAVE64-NEXT: ;;#ASMSTART ; GFX10-WAVE64-NEXT: ;;#ASMSTART
; GFX10-WAVE64-NEXT: v_mov_b32_e64 v7, -1 ; GFX10-WAVE64-NEXT: v_mov_b32_e64 v7, -1
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: v_nop_e64 ; GFX10-WAVE64-NEXT: v_nop_e64
; GFX10-WAVE64-NEXT: ;;#ASMEND ; GFX10-WAVE64-NEXT: ;;#ASMEND
; GFX10-WAVE64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v7 ; GFX10-WAVE64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v7
; GFX10-WAVE64-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc ; GFX10-WAVE64-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc
; GFX10-WAVE64-NEXT: s_cbranch_scc0 BB10_4 ; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB10_4
; GFX10-WAVE64-NEXT: ; %bb.2: ; %bb ; GFX10-WAVE64-NEXT: ; %bb.2: ; %bb
; GFX10-WAVE64-NEXT: ; in Loop: Header=BB10_1 Depth=1 ; GFX10-WAVE64-NEXT: ; in Loop: Header=BB10_1 Depth=1
; GFX10-WAVE64-NEXT: s_andn2_b64 exec, exec, vcc ; GFX10-WAVE64-NEXT: s_andn2_b64 exec, exec, vcc
; GFX10-WAVE64-NEXT: global_load_dword v0, v[0:1], off glc dlc ; GFX10-WAVE64-NEXT: global_load_dword v0, v[0:1], off glc dlc
; GFX10-WAVE64-NEXT: s_waitcnt vmcnt(0) ; GFX10-WAVE64-NEXT: s_waitcnt vmcnt(0)
; GFX10-WAVE64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX10-WAVE64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX10-WAVE64-NEXT: s_and_b64 vcc, exec, vcc ; GFX10-WAVE64-NEXT: s_and_b64 vcc, exec, vcc
; GFX10-WAVE64-NEXT: s_cbranch_vccnz BB10_1 ; GFX10-WAVE64-NEXT: s_cbranch_vccnz .LBB10_1
; GFX10-WAVE64-NEXT: BB10_3: ; %Flow1 ; GFX10-WAVE64-NEXT: .LBB10_3: ; %Flow1
; GFX10-WAVE64-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX10-WAVE64-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX10-WAVE64-NEXT: v_mov_b32_e32 v0, 8 ; GFX10-WAVE64-NEXT: v_mov_b32_e32 v0, 8
; GFX10-WAVE64-NEXT: global_store_dword v[0:1], v0, off ; GFX10-WAVE64-NEXT: global_store_dword v[0:1], v0, off
; GFX10-WAVE64-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-WAVE64-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: s_endpgm
; GFX10-WAVE64-NEXT: BB10_4: ; GFX10-WAVE64-NEXT: .LBB10_4:
; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0 ; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0
; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm ; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm
; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: s_endpgm
; ;
; GFX10-WAVE32-LABEL: test_kill_divergent_loop: ; GFX10-WAVE32-LABEL: test_kill_divergent_loop:
; GFX10-WAVE32: ; %bb.0: ; %entry ; GFX10-WAVE32: ; %bb.0: ; %entry
; GFX10-WAVE32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX10-WAVE32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX10-WAVE32-NEXT: s_mov_b32 s0, exec_lo ; GFX10-WAVE32-NEXT: s_mov_b32 s0, exec_lo
; GFX10-WAVE32-NEXT: s_and_saveexec_b32 s1, vcc_lo ; GFX10-WAVE32-NEXT: s_and_saveexec_b32 s1, vcc_lo
; GFX10-WAVE32-NEXT: s_xor_b32 s1, exec_lo, s1 ; GFX10-WAVE32-NEXT: s_xor_b32 s1, exec_lo, s1
; GFX10-WAVE32-NEXT: s_cbranch_execz BB10_3 ; GFX10-WAVE32-NEXT: s_cbranch_execz .LBB10_3
; GFX10-WAVE32-NEXT: BB10_1: ; %bb ; GFX10-WAVE32-NEXT: .LBB10_1: ; %bb
; GFX10-WAVE32-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-WAVE32-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-WAVE32-NEXT: ;;#ASMSTART ; GFX10-WAVE32-NEXT: ;;#ASMSTART
; GFX10-WAVE32-NEXT: v_mov_b32_e64 v7, -1 ; GFX10-WAVE32-NEXT: v_mov_b32_e64 v7, -1
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: v_nop_e64 ; GFX10-WAVE32-NEXT: v_nop_e64
; GFX10-WAVE32-NEXT: ;;#ASMEND ; GFX10-WAVE32-NEXT: ;;#ASMEND
; GFX10-WAVE32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v7 ; GFX10-WAVE32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v7
; GFX10-WAVE32-NEXT: s_andn2_b32 s0, s0, vcc_lo ; GFX10-WAVE32-NEXT: s_andn2_b32 s0, s0, vcc_lo
; GFX10-WAVE32-NEXT: s_cbranch_scc0 BB10_4 ; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB10_4
; GFX10-WAVE32-NEXT: ; %bb.2: ; %bb ; GFX10-WAVE32-NEXT: ; %bb.2: ; %bb
; GFX10-WAVE32-NEXT: ; in Loop: Header=BB10_1 Depth=1 ; GFX10-WAVE32-NEXT: ; in Loop: Header=BB10_1 Depth=1
; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, vcc_lo ; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, vcc_lo
; GFX10-WAVE32-NEXT: global_load_dword v0, v[0:1], off glc dlc ; GFX10-WAVE32-NEXT: global_load_dword v0, v[0:1], off glc dlc
; GFX10-WAVE32-NEXT: s_waitcnt vmcnt(0) ; GFX10-WAVE32-NEXT: s_waitcnt vmcnt(0)
; GFX10-WAVE32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX10-WAVE32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX10-WAVE32-NEXT: s_and_b32 vcc_lo, exec_lo, vcc_lo ; GFX10-WAVE32-NEXT: s_and_b32 vcc_lo, exec_lo, vcc_lo
; GFX10-WAVE32-NEXT: s_cbranch_vccnz BB10_1 ; GFX10-WAVE32-NEXT: s_cbranch_vccnz .LBB10_1
; GFX10-WAVE32-NEXT: BB10_3: ; %Flow1 ; GFX10-WAVE32-NEXT: .LBB10_3: ; %Flow1
; GFX10-WAVE32-NEXT: s_or_b32 exec_lo, exec_lo, s1 ; GFX10-WAVE32-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX10-WAVE32-NEXT: v_mov_b32_e32 v0, 8 ; GFX10-WAVE32-NEXT: v_mov_b32_e32 v0, 8
; GFX10-WAVE32-NEXT: global_store_dword v[0:1], v0, off ; GFX10-WAVE32-NEXT: global_store_dword v[0:1], v0, off
; GFX10-WAVE32-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-WAVE32-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: s_endpgm
; GFX10-WAVE32-NEXT: BB10_4: ; GFX10-WAVE32-NEXT: .LBB10_4:
; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm ; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm
; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: s_endpgm
entry: entry:
%cmp = icmp eq i32 %arg, 0 %cmp = icmp eq i32 %arg, 0
br i1 %cmp, label %bb, label %exit br i1 %cmp, label %bb, label %exit
bb: bb:
Show All 23 Lines
define amdgpu_ps void @phi_use_def_before_kill(float inreg %x) #0 { define amdgpu_ps void @phi_use_def_before_kill(float inreg %x) #0 {
; SI-LABEL: phi_use_def_before_kill: ; SI-LABEL: phi_use_def_before_kill:
; SI: ; %bb.0: ; %bb ; SI: ; %bb.0: ; %bb
; SI-NEXT: v_add_f32_e64 v1, s0, 1.0 ; SI-NEXT: v_add_f32_e64 v1, s0, 1.0
; SI-NEXT: v_cmp_lt_f32_e32 vcc, 0, v1 ; SI-NEXT: v_cmp_lt_f32_e32 vcc, 0, v1
; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc ; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc
; SI-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v1 ; SI-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v1
; SI-NEXT: s_andn2_b64 exec, exec, vcc ; SI-NEXT: s_andn2_b64 exec, exec, vcc
; SI-NEXT: s_cbranch_scc0 BB11_6 ; SI-NEXT: s_cbranch_scc0 .LBB11_6
; SI-NEXT: ; %bb.1: ; %bb ; SI-NEXT: ; %bb.1: ; %bb
; SI-NEXT: s_andn2_b64 exec, exec, vcc ; SI-NEXT: s_andn2_b64 exec, exec, vcc
; SI-NEXT: s_cbranch_scc0 BB11_3 ; SI-NEXT: s_cbranch_scc0 .LBB11_3
; SI-NEXT: ; %bb.2: ; %bb8 ; SI-NEXT: ; %bb.2: ; %bb8
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: v_mov_b32_e32 v0, 8 ; SI-NEXT: v_mov_b32_e32 v0, 8
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, 4.0 ; SI-NEXT: v_mov_b32_e32 v0, 4.0
; SI-NEXT: BB11_3: ; %phibb ; SI-NEXT: .LBB11_3: ; %phibb
; SI-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0 ; SI-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0
; SI-NEXT: s_and_b64 vcc, exec, vcc ; SI-NEXT: s_and_b64 vcc, exec, vcc
; SI-NEXT: s_cbranch_vccz BB11_5 ; SI-NEXT: s_cbranch_vccz .LBB11_5
; SI-NEXT: ; %bb.4: ; %bb10 ; SI-NEXT: ; %bb.4: ; %bb10
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: v_mov_b32_e32 v0, 9 ; SI-NEXT: v_mov_b32_e32 v0, 9
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: BB11_5: ; %end ; SI-NEXT: .LBB11_5: ; %end
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; SI-NEXT: BB11_6: ; SI-NEXT: .LBB11_6:
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: exp null off, off, off, off done vm ; SI-NEXT: exp null off, off, off, off done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; GFX10-WAVE64-LABEL: phi_use_def_before_kill: ; GFX10-WAVE64-LABEL: phi_use_def_before_kill:
; GFX10-WAVE64: ; %bb.0: ; %bb ; GFX10-WAVE64: ; %bb.0: ; %bb
; GFX10-WAVE64-NEXT: v_add_f32_e64 v1, s0, 1.0 ; GFX10-WAVE64-NEXT: v_add_f32_e64 v1, s0, 1.0
; GFX10-WAVE64-NEXT: v_cmp_lt_f32_e32 vcc, 0, v1 ; GFX10-WAVE64-NEXT: v_cmp_lt_f32_e32 vcc, 0, v1
; GFX10-WAVE64-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc ; GFX10-WAVE64-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc
; GFX10-WAVE64-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v1 ; GFX10-WAVE64-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v1
; GFX10-WAVE64-NEXT: s_andn2_b64 exec, exec, vcc ; GFX10-WAVE64-NEXT: s_andn2_b64 exec, exec, vcc
; GFX10-WAVE64-NEXT: s_cbranch_scc0 BB11_6 ; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB11_6
; GFX10-WAVE64-NEXT: ; %bb.1: ; %bb ; GFX10-WAVE64-NEXT: ; %bb.1: ; %bb
; GFX10-WAVE64-NEXT: s_andn2_b64 exec, exec, vcc ; GFX10-WAVE64-NEXT: s_andn2_b64 exec, exec, vcc
; GFX10-WAVE64-NEXT: s_cbranch_scc0 BB11_3 ; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB11_3
; GFX10-WAVE64-NEXT: ; %bb.2: ; %bb8 ; GFX10-WAVE64-NEXT: ; %bb.2: ; %bb8
; GFX10-WAVE64-NEXT: v_mov_b32_e32 v1, 8 ; GFX10-WAVE64-NEXT: v_mov_b32_e32 v1, 8
; GFX10-WAVE64-NEXT: v_mov_b32_e32 v0, 4.0 ; GFX10-WAVE64-NEXT: v_mov_b32_e32 v0, 4.0
; GFX10-WAVE64-NEXT: global_store_dword v[0:1], v1, off ; GFX10-WAVE64-NEXT: global_store_dword v[0:1], v1, off
; GFX10-WAVE64-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-WAVE64-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WAVE64-NEXT: BB11_3: ; %phibb ; GFX10-WAVE64-NEXT: .LBB11_3: ; %phibb
; GFX10-WAVE64-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0 ; GFX10-WAVE64-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0
; GFX10-WAVE64-NEXT: s_and_b64 vcc, exec, vcc ; GFX10-WAVE64-NEXT: s_and_b64 vcc, exec, vcc
; GFX10-WAVE64-NEXT: s_cbranch_vccz BB11_5 ; GFX10-WAVE64-NEXT: s_cbranch_vccz .LBB11_5
; GFX10-WAVE64-NEXT: ; %bb.4: ; %bb10 ; GFX10-WAVE64-NEXT: ; %bb.4: ; %bb10
; GFX10-WAVE64-NEXT: v_mov_b32_e32 v0, 9 ; GFX10-WAVE64-NEXT: v_mov_b32_e32 v0, 9
; GFX10-WAVE64-NEXT: global_store_dword v[0:1], v0, off ; GFX10-WAVE64-NEXT: global_store_dword v[0:1], v0, off
; GFX10-WAVE64-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-WAVE64-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WAVE64-NEXT: BB11_5: ; %end ; GFX10-WAVE64-NEXT: .LBB11_5: ; %end
; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: s_endpgm
; GFX10-WAVE64-NEXT: BB11_6: ; GFX10-WAVE64-NEXT: .LBB11_6:
; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0 ; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0
; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm ; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm
; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: s_endpgm
; ;
; GFX10-WAVE32-LABEL: phi_use_def_before_kill: ; GFX10-WAVE32-LABEL: phi_use_def_before_kill:
; GFX10-WAVE32: ; %bb.0: ; %bb ; GFX10-WAVE32: ; %bb.0: ; %bb
; GFX10-WAVE32-NEXT: v_add_f32_e64 v1, s0, 1.0 ; GFX10-WAVE32-NEXT: v_add_f32_e64 v1, s0, 1.0
; GFX10-WAVE32-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v1 ; GFX10-WAVE32-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v1
; GFX10-WAVE32-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo ; GFX10-WAVE32-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
; GFX10-WAVE32-NEXT: v_cmp_nlt_f32_e32 vcc_lo, 0, v1 ; GFX10-WAVE32-NEXT: v_cmp_nlt_f32_e32 vcc_lo, 0, v1
; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, vcc_lo ; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, vcc_lo
; GFX10-WAVE32-NEXT: s_cbranch_scc0 BB11_6 ; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB11_6
; GFX10-WAVE32-NEXT: ; %bb.1: ; %bb ; GFX10-WAVE32-NEXT: ; %bb.1: ; %bb
; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, vcc_lo ; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, vcc_lo
; GFX10-WAVE32-NEXT: s_cbranch_scc0 BB11_3 ; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB11_3
; GFX10-WAVE32-NEXT: ; %bb.2: ; %bb8 ; GFX10-WAVE32-NEXT: ; %bb.2: ; %bb8
; GFX10-WAVE32-NEXT: v_mov_b32_e32 v1, 8 ; GFX10-WAVE32-NEXT: v_mov_b32_e32 v1, 8
; GFX10-WAVE32-NEXT: v_mov_b32_e32 v0, 4.0 ; GFX10-WAVE32-NEXT: v_mov_b32_e32 v0, 4.0
; GFX10-WAVE32-NEXT: global_store_dword v[0:1], v1, off ; GFX10-WAVE32-NEXT: global_store_dword v[0:1], v1, off
; GFX10-WAVE32-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-WAVE32-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WAVE32-NEXT: BB11_3: ; %phibb ; GFX10-WAVE32-NEXT: .LBB11_3: ; %phibb
; GFX10-WAVE32-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0 ; GFX10-WAVE32-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0
; GFX10-WAVE32-NEXT: s_and_b32 vcc_lo, exec_lo, vcc_lo ; GFX10-WAVE32-NEXT: s_and_b32 vcc_lo, exec_lo, vcc_lo
; GFX10-WAVE32-NEXT: s_cbranch_vccz BB11_5 ; GFX10-WAVE32-NEXT: s_cbranch_vccz .LBB11_5
; GFX10-WAVE32-NEXT: ; %bb.4: ; %bb10 ; GFX10-WAVE32-NEXT: ; %bb.4: ; %bb10
; GFX10-WAVE32-NEXT: v_mov_b32_e32 v0, 9 ; GFX10-WAVE32-NEXT: v_mov_b32_e32 v0, 9
; GFX10-WAVE32-NEXT: global_store_dword v[0:1], v0, off ; GFX10-WAVE32-NEXT: global_store_dword v[0:1], v0, off
; GFX10-WAVE32-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-WAVE32-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WAVE32-NEXT: BB11_5: ; %end ; GFX10-WAVE32-NEXT: .LBB11_5: ; %end
; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: s_endpgm
; GFX10-WAVE32-NEXT: BB11_6: ; GFX10-WAVE32-NEXT: .LBB11_6:
; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm ; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm
; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: s_endpgm
bb: bb:
%tmp = fadd float %x, 1.000000e+00 %tmp = fadd float %x, 1.000000e+00
%tmp1 = fcmp olt float 0.000000e+00, %tmp %tmp1 = fcmp olt float 0.000000e+00, %tmp
%tmp2 = select i1 %tmp1, float -1.000000e+00, float 0.000000e+00 %tmp2 = select i1 %tmp1, float -1.000000e+00, float 0.000000e+00
%cmp.tmp2 = fcmp olt float %tmp2, 0.0 %cmp.tmp2 = fcmp olt float %tmp2, 0.0
Show All 17 Linesend:
ret void ret void
} }
define amdgpu_ps void @no_skip_no_successors(float inreg %arg, float inreg %arg1) #0 { define amdgpu_ps void @no_skip_no_successors(float inreg %arg, float inreg %arg1) #0 {
; SI-LABEL: no_skip_no_successors: ; SI-LABEL: no_skip_no_successors:
; SI: ; %bb.0: ; %bb ; SI: ; %bb.0: ; %bb
; SI-NEXT: v_cmp_nge_f32_e64 s[4:5], s1, 0 ; SI-NEXT: v_cmp_nge_f32_e64 s[4:5], s1, 0
; SI-NEXT: s_and_b64 vcc, exec, s[4:5] ; SI-NEXT: s_and_b64 vcc, exec, s[4:5]
; SI-NEXT: s_cbranch_vccz BB12_3 ; SI-NEXT: s_cbranch_vccz .LBB12_3
; SI-NEXT: ; %bb.1: ; %bb6 ; SI-NEXT: ; %bb.1: ; %bb6
; SI-NEXT: s_mov_b64 s[2:3], exec ; SI-NEXT: s_mov_b64 s[2:3], exec
; SI-NEXT: s_andn2_b64 s[2:3], s[2:3], exec ; SI-NEXT: s_andn2_b64 s[2:3], s[2:3], exec
; SI-NEXT: s_cbranch_scc0 BB12_5 ; SI-NEXT: s_cbranch_scc0 .LBB12_5
; SI-NEXT: ; %bb.2: ; %bb6 ; SI-NEXT: ; %bb.2: ; %bb6
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: BB12_3: ; %bb3 ; SI-NEXT: .LBB12_3: ; %bb3
; SI-NEXT: v_mov_b32_e32 v0, 0x3e7ae148 ; SI-NEXT: v_mov_b32_e32 v0, 0x3e7ae148
; SI-NEXT: v_cmp_nge_f32_e32 vcc, s0, v0 ; SI-NEXT: v_cmp_nge_f32_e32 vcc, s0, v0
; SI-NEXT: s_and_b64 vcc, exec, vcc ; SI-NEXT: s_and_b64 vcc, exec, vcc
; SI-NEXT: ; %bb.4: ; %bb5 ; SI-NEXT: ; %bb.4: ; %bb5
; SI-NEXT: BB12_5: ; SI-NEXT: .LBB12_5:
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: exp null off, off, off, off done vm ; SI-NEXT: exp null off, off, off, off done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; GFX10-WAVE64-LABEL: no_skip_no_successors: ; GFX10-WAVE64-LABEL: no_skip_no_successors:
; GFX10-WAVE64: ; %bb.0: ; %bb ; GFX10-WAVE64: ; %bb.0: ; %bb
; GFX10-WAVE64-NEXT: v_cmp_nge_f32_e64 s[4:5], s1, 0 ; GFX10-WAVE64-NEXT: v_cmp_nge_f32_e64 s[4:5], s1, 0
; GFX10-WAVE64-NEXT: s_and_b64 vcc, exec, s[4:5] ; GFX10-WAVE64-NEXT: s_and_b64 vcc, exec, s[4:5]
; GFX10-WAVE64-NEXT: s_cbranch_vccz BB12_3 ; GFX10-WAVE64-NEXT: s_cbranch_vccz .LBB12_3
; GFX10-WAVE64-NEXT: ; %bb.1: ; %bb6 ; GFX10-WAVE64-NEXT: ; %bb.1: ; %bb6
; GFX10-WAVE64-NEXT: s_mov_b64 s[2:3], exec ; GFX10-WAVE64-NEXT: s_mov_b64 s[2:3], exec
; GFX10-WAVE64-NEXT: s_andn2_b64 s[2:3], s[2:3], exec ; GFX10-WAVE64-NEXT: s_andn2_b64 s[2:3], s[2:3], exec
; GFX10-WAVE64-NEXT: s_cbranch_scc0 BB12_5 ; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB12_5
; GFX10-WAVE64-NEXT: ; %bb.2: ; %bb6 ; GFX10-WAVE64-NEXT: ; %bb.2: ; %bb6
; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0 ; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0
; GFX10-WAVE64-NEXT: BB12_3: ; %bb3 ; GFX10-WAVE64-NEXT: .LBB12_3: ; %bb3
; GFX10-WAVE64-NEXT: v_cmp_nle_f32_e64 s[0:1], 0x3e7ae148, s0 ; GFX10-WAVE64-NEXT: v_cmp_nle_f32_e64 s[0:1], 0x3e7ae148, s0
; GFX10-WAVE64-NEXT: s_and_b64 vcc, exec, s[0:1] ; GFX10-WAVE64-NEXT: s_and_b64 vcc, exec, s[0:1]
; GFX10-WAVE64-NEXT: ; %bb.4: ; %bb5 ; GFX10-WAVE64-NEXT: ; %bb.4: ; %bb5
; GFX10-WAVE64-NEXT: BB12_5: ; GFX10-WAVE64-NEXT: .LBB12_5:
; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0 ; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0
; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm ; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm
; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: s_endpgm
; ;
; GFX10-WAVE32-LABEL: no_skip_no_successors: ; GFX10-WAVE32-LABEL: no_skip_no_successors:
; GFX10-WAVE32: ; %bb.0: ; %bb ; GFX10-WAVE32: ; %bb.0: ; %bb
; GFX10-WAVE32-NEXT: v_cmp_nge_f32_e64 s1, s1, 0 ; GFX10-WAVE32-NEXT: v_cmp_nge_f32_e64 s1, s1, 0
; GFX10-WAVE32-NEXT: s_and_b32 vcc_lo, exec_lo, s1 ; GFX10-WAVE32-NEXT: s_and_b32 vcc_lo, exec_lo, s1
; GFX10-WAVE32-NEXT: s_cbranch_vccz BB12_3 ; GFX10-WAVE32-NEXT: s_cbranch_vccz .LBB12_3
; GFX10-WAVE32-NEXT: ; %bb.1: ; %bb6 ; GFX10-WAVE32-NEXT: ; %bb.1: ; %bb6
; GFX10-WAVE32-NEXT: s_mov_b32 s2, exec_lo ; GFX10-WAVE32-NEXT: s_mov_b32 s2, exec_lo
; GFX10-WAVE32-NEXT: s_andn2_b32 s2, s2, exec_lo ; GFX10-WAVE32-NEXT: s_andn2_b32 s2, s2, exec_lo
; GFX10-WAVE32-NEXT: s_cbranch_scc0 BB12_5 ; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB12_5
; GFX10-WAVE32-NEXT: ; %bb.2: ; %bb6 ; GFX10-WAVE32-NEXT: ; %bb.2: ; %bb6
; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-WAVE32-NEXT: BB12_3: ; %bb3 ; GFX10-WAVE32-NEXT: .LBB12_3: ; %bb3
; GFX10-WAVE32-NEXT: v_cmp_nle_f32_e64 s0, 0x3e7ae148, s0 ; GFX10-WAVE32-NEXT: v_cmp_nle_f32_e64 s0, 0x3e7ae148, s0
; GFX10-WAVE32-NEXT: s_and_b32 vcc_lo, exec_lo, s0 ; GFX10-WAVE32-NEXT: s_and_b32 vcc_lo, exec_lo, s0
; GFX10-WAVE32-NEXT: ; %bb.4: ; %bb5 ; GFX10-WAVE32-NEXT: ; %bb.4: ; %bb5
; GFX10-WAVE32-NEXT: BB12_5: ; GFX10-WAVE32-NEXT: .LBB12_5:
; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm ; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm
; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: s_endpgm
bb: bb:
%tmp = fcmp ult float %arg1, 0.000000e+00 %tmp = fcmp ult float %arg1, 0.000000e+00
%tmp2 = fcmp ult float %arg, 0x3FCF5C2900000000 %tmp2 = fcmp ult float %arg, 0x3FCF5C2900000000
br i1 %tmp, label %bb6, label %bb3 br i1 %tmp, label %bb6, label %bb3
Show All 18 Lines
; SI-LABEL: if_after_kill_block: ; SI-LABEL: if_after_kill_block:
; SI: ; %bb.0: ; %bb ; SI: ; %bb.0: ; %bb
; SI-NEXT: s_mov_b64 s[2:3], exec ; SI-NEXT: s_mov_b64 s[2:3], exec
; SI-NEXT: s_wqm_b64 exec, exec ; SI-NEXT: s_wqm_b64 exec, exec
; SI-NEXT: s_mov_b32 s0, 0 ; SI-NEXT: s_mov_b32 s0, 0
; SI-NEXT: v_cmp_nle_f32_e32 vcc, 0, v1 ; SI-NEXT: v_cmp_nle_f32_e32 vcc, 0, v1
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc ; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] ; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz BB13_3 ; SI-NEXT: s_cbranch_execz .LBB13_3
; SI-NEXT: ; %bb.1: ; %bb3 ; SI-NEXT: ; %bb.1: ; %bb3
; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0 ; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0
; SI-NEXT: s_andn2_b64 s[2:3], s[2:3], vcc ; SI-NEXT: s_andn2_b64 s[2:3], s[2:3], vcc
; SI-NEXT: s_cbranch_scc0 BB13_6 ; SI-NEXT: s_cbranch_scc0 .LBB13_6
; SI-NEXT: ; %bb.2: ; %bb3 ; SI-NEXT: ; %bb.2: ; %bb3
; SI-NEXT: s_andn2_b64 exec, exec, vcc ; SI-NEXT: s_andn2_b64 exec, exec, vcc
; SI-NEXT: BB13_3: ; %bb4 ; SI-NEXT: .LBB13_3: ; %bb4
; SI-NEXT: s_or_b64 exec, exec, s[4:5] ; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_mov_b32 s1, s0 ; SI-NEXT: s_mov_b32 s1, s0
; SI-NEXT: s_mov_b32 s2, s0 ; SI-NEXT: s_mov_b32 s2, s0
; SI-NEXT: s_mov_b32 s3, s0 ; SI-NEXT: s_mov_b32 s3, s0
; SI-NEXT: s_mov_b32 s4, s0 ; SI-NEXT: s_mov_b32 s4, s0
; SI-NEXT: s_mov_b32 s5, s0 ; SI-NEXT: s_mov_b32 s5, s0
; SI-NEXT: s_mov_b32 s6, s0 ; SI-NEXT: s_mov_b32 s6, s0
; SI-NEXT: s_mov_b32 s7, s0 ; SI-NEXT: s_mov_b32 s7, s0
; SI-NEXT: image_sample_c v0, v[2:3], s[0:7], s[0:3] dmask:0x10 ; SI-NEXT: image_sample_c v0, v[2:3], s[0:7], s[0:3] dmask:0x10
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cmp_neq_f32_e32 vcc, 0, v0 ; SI-NEXT: v_cmp_neq_f32_e32 vcc, 0, v0
; SI-NEXT: s_and_saveexec_b64 s[0:1], vcc ; SI-NEXT: s_and_saveexec_b64 s[0:1], vcc
; SI-NEXT: s_cbranch_execz BB13_5 ; SI-NEXT: s_cbranch_execz .LBB13_5
; SI-NEXT: ; %bb.4: ; %bb8 ; SI-NEXT: ; %bb.4: ; %bb8
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: v_mov_b32_e32 v0, 9 ; SI-NEXT: v_mov_b32_e32 v0, 9
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: BB13_5: ; %UnifiedReturnBlock ; SI-NEXT: .LBB13_5: ; %UnifiedReturnBlock
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; SI-NEXT: BB13_6: ; SI-NEXT: .LBB13_6:
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: exp null off, off, off, off done vm ; SI-NEXT: exp null off, off, off, off done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; GFX10-WAVE64-LABEL: if_after_kill_block: ; GFX10-WAVE64-LABEL: if_after_kill_block:
; GFX10-WAVE64: ; %bb.0: ; %bb ; GFX10-WAVE64: ; %bb.0: ; %bb
; GFX10-WAVE64-NEXT: s_mov_b64 s[2:3], exec ; GFX10-WAVE64-NEXT: s_mov_b64 s[2:3], exec
; GFX10-WAVE64-NEXT: s_wqm_b64 exec, exec ; GFX10-WAVE64-NEXT: s_wqm_b64 exec, exec
; GFX10-WAVE64-NEXT: v_cmp_nle_f32_e32 vcc, 0, v1 ; GFX10-WAVE64-NEXT: v_cmp_nle_f32_e32 vcc, 0, v1
; GFX10-WAVE64-NEXT: s_mov_b32 s0, 0 ; GFX10-WAVE64-NEXT: s_mov_b32 s0, 0
; GFX10-WAVE64-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX10-WAVE64-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX10-WAVE64-NEXT: s_xor_b64 s[4:5], exec, s[4:5] ; GFX10-WAVE64-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX10-WAVE64-NEXT: s_cbranch_execz BB13_3 ; GFX10-WAVE64-NEXT: s_cbranch_execz .LBB13_3
; GFX10-WAVE64-NEXT: ; %bb.1: ; %bb3 ; GFX10-WAVE64-NEXT: ; %bb.1: ; %bb3
; GFX10-WAVE64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0 ; GFX10-WAVE64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0
; GFX10-WAVE64-NEXT: s_andn2_b64 s[2:3], s[2:3], vcc ; GFX10-WAVE64-NEXT: s_andn2_b64 s[2:3], s[2:3], vcc
; GFX10-WAVE64-NEXT: s_cbranch_scc0 BB13_6 ; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB13_6
; GFX10-WAVE64-NEXT: ; %bb.2: ; %bb3 ; GFX10-WAVE64-NEXT: ; %bb.2: ; %bb3
; GFX10-WAVE64-NEXT: s_andn2_b64 exec, exec, vcc ; GFX10-WAVE64-NEXT: s_andn2_b64 exec, exec, vcc
; GFX10-WAVE64-NEXT: BB13_3: ; %bb4 ; GFX10-WAVE64-NEXT: .LBB13_3: ; %bb4
; GFX10-WAVE64-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX10-WAVE64-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX10-WAVE64-NEXT: s_mov_b32 s1, s0 ; GFX10-WAVE64-NEXT: s_mov_b32 s1, s0
; GFX10-WAVE64-NEXT: s_mov_b32 s2, s0 ; GFX10-WAVE64-NEXT: s_mov_b32 s2, s0
; GFX10-WAVE64-NEXT: s_mov_b32 s3, s0 ; GFX10-WAVE64-NEXT: s_mov_b32 s3, s0
; GFX10-WAVE64-NEXT: s_mov_b32 s4, s0 ; GFX10-WAVE64-NEXT: s_mov_b32 s4, s0
; GFX10-WAVE64-NEXT: s_mov_b32 s5, s0 ; GFX10-WAVE64-NEXT: s_mov_b32 s5, s0
; GFX10-WAVE64-NEXT: s_mov_b32 s6, s0 ; GFX10-WAVE64-NEXT: s_mov_b32 s6, s0
; GFX10-WAVE64-NEXT: s_mov_b32 s7, s0 ; GFX10-WAVE64-NEXT: s_mov_b32 s7, s0
; GFX10-WAVE64-NEXT: image_sample_c v0, v[2:3], s[0:7], s[0:3] dmask:0x10 dim:SQ_RSRC_IMG_1D ; GFX10-WAVE64-NEXT: image_sample_c v0, v[2:3], s[0:7], s[0:3] dmask:0x10 dim:SQ_RSRC_IMG_1D
; GFX10-WAVE64-NEXT: s_waitcnt vmcnt(0) ; GFX10-WAVE64-NEXT: s_waitcnt vmcnt(0)
; GFX10-WAVE64-NEXT: v_cmp_neq_f32_e32 vcc, 0, v0 ; GFX10-WAVE64-NEXT: v_cmp_neq_f32_e32 vcc, 0, v0
; GFX10-WAVE64-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX10-WAVE64-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX10-WAVE64-NEXT: s_cbranch_execz BB13_5 ; GFX10-WAVE64-NEXT: s_cbranch_execz .LBB13_5
; GFX10-WAVE64-NEXT: ; %bb.4: ; %bb8 ; GFX10-WAVE64-NEXT: ; %bb.4: ; %bb8
; GFX10-WAVE64-NEXT: v_mov_b32_e32 v0, 9 ; GFX10-WAVE64-NEXT: v_mov_b32_e32 v0, 9
; GFX10-WAVE64-NEXT: global_store_dword v[0:1], v0, off ; GFX10-WAVE64-NEXT: global_store_dword v[0:1], v0, off
; GFX10-WAVE64-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-WAVE64-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WAVE64-NEXT: BB13_5: ; %UnifiedReturnBlock ; GFX10-WAVE64-NEXT: .LBB13_5: ; %UnifiedReturnBlock
; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: s_endpgm
; GFX10-WAVE64-NEXT: BB13_6: ; GFX10-WAVE64-NEXT: .LBB13_6:
; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0 ; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0
; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm ; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm
; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: s_endpgm
; ;
; GFX10-WAVE32-LABEL: if_after_kill_block: ; GFX10-WAVE32-LABEL: if_after_kill_block:
; GFX10-WAVE32: ; %bb.0: ; %bb ; GFX10-WAVE32: ; %bb.0: ; %bb
; GFX10-WAVE32-NEXT: s_mov_b32 s1, exec_lo ; GFX10-WAVE32-NEXT: s_mov_b32 s1, exec_lo
; GFX10-WAVE32-NEXT: s_wqm_b32 exec_lo, exec_lo ; GFX10-WAVE32-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX10-WAVE32-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0, v1 ; GFX10-WAVE32-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0, v1
; GFX10-WAVE32-NEXT: s_mov_b32 s0, 0 ; GFX10-WAVE32-NEXT: s_mov_b32 s0, 0
; GFX10-WAVE32-NEXT: s_and_saveexec_b32 s2, vcc_lo ; GFX10-WAVE32-NEXT: s_and_saveexec_b32 s2, vcc_lo
; GFX10-WAVE32-NEXT: s_xor_b32 s2, exec_lo, s2 ; GFX10-WAVE32-NEXT: s_xor_b32 s2, exec_lo, s2
; GFX10-WAVE32-NEXT: s_cbranch_execz BB13_3 ; GFX10-WAVE32-NEXT: s_cbranch_execz .LBB13_3
; GFX10-WAVE32-NEXT: ; %bb.1: ; %bb3 ; GFX10-WAVE32-NEXT: ; %bb.1: ; %bb3
; GFX10-WAVE32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v0 ; GFX10-WAVE32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v0
; GFX10-WAVE32-NEXT: s_andn2_b32 s1, s1, vcc_lo ; GFX10-WAVE32-NEXT: s_andn2_b32 s1, s1, vcc_lo
; GFX10-WAVE32-NEXT: s_cbranch_scc0 BB13_6 ; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB13_6
; GFX10-WAVE32-NEXT: ; %bb.2: ; %bb3 ; GFX10-WAVE32-NEXT: ; %bb.2: ; %bb3
; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, vcc_lo ; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, vcc_lo
; GFX10-WAVE32-NEXT: BB13_3: ; %bb4 ; GFX10-WAVE32-NEXT: .LBB13_3: ; %bb4
; GFX10-WAVE32-NEXT: s_or_b32 exec_lo, exec_lo, s2 ; GFX10-WAVE32-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX10-WAVE32-NEXT: s_mov_b32 s1, s0 ; GFX10-WAVE32-NEXT: s_mov_b32 s1, s0
; GFX10-WAVE32-NEXT: s_mov_b32 s2, s0 ; GFX10-WAVE32-NEXT: s_mov_b32 s2, s0
; GFX10-WAVE32-NEXT: s_mov_b32 s3, s0 ; GFX10-WAVE32-NEXT: s_mov_b32 s3, s0
; GFX10-WAVE32-NEXT: s_mov_b32 s4, s0 ; GFX10-WAVE32-NEXT: s_mov_b32 s4, s0
; GFX10-WAVE32-NEXT: s_mov_b32 s5, s0 ; GFX10-WAVE32-NEXT: s_mov_b32 s5, s0
; GFX10-WAVE32-NEXT: s_mov_b32 s6, s0 ; GFX10-WAVE32-NEXT: s_mov_b32 s6, s0
; GFX10-WAVE32-NEXT: s_mov_b32 s7, s0 ; GFX10-WAVE32-NEXT: s_mov_b32 s7, s0
; GFX10-WAVE32-NEXT: image_sample_c v0, v[2:3], s[0:7], s[0:3] dmask:0x10 dim:SQ_RSRC_IMG_1D ; GFX10-WAVE32-NEXT: image_sample_c v0, v[2:3], s[0:7], s[0:3] dmask:0x10 dim:SQ_RSRC_IMG_1D
; GFX10-WAVE32-NEXT: s_waitcnt vmcnt(0) ; GFX10-WAVE32-NEXT: s_waitcnt vmcnt(0)
; GFX10-WAVE32-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v0 ; GFX10-WAVE32-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v0
; GFX10-WAVE32-NEXT: s_and_saveexec_b32 s0, vcc_lo ; GFX10-WAVE32-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX10-WAVE32-NEXT: s_cbranch_execz BB13_5 ; GFX10-WAVE32-NEXT: s_cbranch_execz .LBB13_5
; GFX10-WAVE32-NEXT: ; %bb.4: ; %bb8 ; GFX10-WAVE32-NEXT: ; %bb.4: ; %bb8
; GFX10-WAVE32-NEXT: v_mov_b32_e32 v0, 9 ; GFX10-WAVE32-NEXT: v_mov_b32_e32 v0, 9
; GFX10-WAVE32-NEXT: global_store_dword v[0:1], v0, off ; GFX10-WAVE32-NEXT: global_store_dword v[0:1], v0, off
; GFX10-WAVE32-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-WAVE32-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WAVE32-NEXT: BB13_5: ; %UnifiedReturnBlock ; GFX10-WAVE32-NEXT: .LBB13_5: ; %UnifiedReturnBlock
; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: s_endpgm
; GFX10-WAVE32-NEXT: BB13_6: ; GFX10-WAVE32-NEXT: .LBB13_6:
; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm ; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm
; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: s_endpgm
bb: bb:
%tmp = fcmp ult float %arg1, 0.000000e+00 %tmp = fcmp ult float %arg1, 0.000000e+00
br i1 %tmp, label %bb3, label %bb4 br i1 %tmp, label %bb3, label %bb4
bb3: ; preds = %bb bb3: ; preds = %bb
Show All 29 Lines
; SI-NEXT: s_mov_b32 s9, s4 ; SI-NEXT: s_mov_b32 s9, s4
; SI-NEXT: s_mov_b32 s10, s4 ; SI-NEXT: s_mov_b32 s10, s4
; SI-NEXT: s_mov_b32 s11, s4 ; SI-NEXT: s_mov_b32 s11, s4
; SI-NEXT: image_sample_lz v1, v[1:3], s[4:11], s[0:3] dmask:0x1 da ; SI-NEXT: image_sample_lz v1, v[1:3], s[4:11], s[0:3] dmask:0x1 da
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cmp_ge_f32_e32 vcc, 0, v1 ; SI-NEXT: v_cmp_ge_f32_e32 vcc, 0, v1
; SI-NEXT: s_and_saveexec_b64 s[2:3], vcc ; SI-NEXT: s_and_saveexec_b64 s[2:3], vcc
; SI-NEXT: s_xor_b64 s[2:3], exec, s[2:3] ; SI-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; SI-NEXT: s_cbranch_execz BB14_3 ; SI-NEXT: s_cbranch_execz .LBB14_3
; SI-NEXT: ; %bb.1: ; %kill ; SI-NEXT: ; %bb.1: ; %kill
; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; SI-NEXT: ; implicit-def: $vgpr0 ; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1 ; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: s_cbranch_scc0 BB14_6 ; SI-NEXT: s_cbranch_scc0 .LBB14_6
; SI-NEXT: ; %bb.2: ; %kill ; SI-NEXT: ; %bb.2: ; %kill
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: BB14_3: ; %Flow ; SI-NEXT: .LBB14_3: ; %Flow
; SI-NEXT: s_or_saveexec_b64 s[0:1], s[2:3] ; SI-NEXT: s_or_saveexec_b64 s[0:1], s[2:3]
; SI-NEXT: ; implicit-def: $vgpr2 ; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: s_xor_b64 exec, exec, s[0:1] ; SI-NEXT: s_xor_b64 exec, exec, s[0:1]
; SI-NEXT: ; %bb.4: ; %live ; SI-NEXT: ; %bb.4: ; %live
; SI-NEXT: v_mul_f32_e32 v2, v0, v1 ; SI-NEXT: v_mul_f32_e32 v2, v0, v1
; SI-NEXT: ; %bb.5: ; %export ; SI-NEXT: ; %bb.5: ; %export
; SI-NEXT: s_or_b64 exec, exec, s[0:1] ; SI-NEXT: s_or_b64 exec, exec, s[0:1]
; SI-NEXT: exp mrt0 v2, v2, v2, v2 done vm ; SI-NEXT: exp mrt0 v2, v2, v2, v2 done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; SI-NEXT: BB14_6: ; SI-NEXT: .LBB14_6:
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: exp null off, off, off, off done vm ; SI-NEXT: exp null off, off, off, off done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; GFX10-WAVE64-LABEL: cbranch_kill: ; GFX10-WAVE64-LABEL: cbranch_kill:
; GFX10-WAVE64: ; %bb.0: ; %.entry ; GFX10-WAVE64: ; %bb.0: ; %.entry
; GFX10-WAVE64-NEXT: s_mov_b32 s4, 0 ; GFX10-WAVE64-NEXT: s_mov_b32 s4, 0
; GFX10-WAVE64-NEXT: s_mov_b64 s[0:1], exec ; GFX10-WAVE64-NEXT: s_mov_b64 s[0:1], exec
; GFX10-WAVE64-NEXT: s_mov_b32 s5, s4 ; GFX10-WAVE64-NEXT: s_mov_b32 s5, s4
; GFX10-WAVE64-NEXT: s_mov_b32 s6, s4 ; GFX10-WAVE64-NEXT: s_mov_b32 s6, s4
; GFX10-WAVE64-NEXT: s_mov_b32 s7, s4 ; GFX10-WAVE64-NEXT: s_mov_b32 s7, s4
; GFX10-WAVE64-NEXT: s_mov_b32 s8, s4 ; GFX10-WAVE64-NEXT: s_mov_b32 s8, s4
; GFX10-WAVE64-NEXT: s_mov_b32 s9, s4 ; GFX10-WAVE64-NEXT: s_mov_b32 s9, s4
; GFX10-WAVE64-NEXT: s_mov_b32 s10, s4 ; GFX10-WAVE64-NEXT: s_mov_b32 s10, s4
; GFX10-WAVE64-NEXT: s_mov_b32 s11, s4 ; GFX10-WAVE64-NEXT: s_mov_b32 s11, s4
; GFX10-WAVE64-NEXT: image_sample_lz v1, [v1, v1, v1], s[4:11], s[0:3] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY ; GFX10-WAVE64-NEXT: image_sample_lz v1, [v1, v1, v1], s[4:11], s[0:3] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY
; GFX10-WAVE64-NEXT: s_waitcnt vmcnt(0) ; GFX10-WAVE64-NEXT: s_waitcnt vmcnt(0)
; GFX10-WAVE64-NEXT: v_cmp_ge_f32_e32 vcc, 0, v1 ; GFX10-WAVE64-NEXT: v_cmp_ge_f32_e32 vcc, 0, v1
; GFX10-WAVE64-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX10-WAVE64-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX10-WAVE64-NEXT: s_xor_b64 s[2:3], exec, s[2:3] ; GFX10-WAVE64-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX10-WAVE64-NEXT: s_cbranch_execz BB14_3 ; GFX10-WAVE64-NEXT: s_cbranch_execz .LBB14_3
; GFX10-WAVE64-NEXT: ; %bb.1: ; %kill ; GFX10-WAVE64-NEXT: ; %bb.1: ; %kill
; GFX10-WAVE64-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; GFX10-WAVE64-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; GFX10-WAVE64-NEXT: ; implicit-def: $vgpr0 ; GFX10-WAVE64-NEXT: ; implicit-def: $vgpr0
; GFX10-WAVE64-NEXT: ; implicit-def: $vgpr1 ; GFX10-WAVE64-NEXT: ; implicit-def: $vgpr1
; GFX10-WAVE64-NEXT: s_cbranch_scc0 BB14_6 ; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB14_6
; GFX10-WAVE64-NEXT: ; %bb.2: ; %kill ; GFX10-WAVE64-NEXT: ; %bb.2: ; %kill
; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0 ; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0
; GFX10-WAVE64-NEXT: BB14_3: ; %Flow ; GFX10-WAVE64-NEXT: .LBB14_3: ; %Flow
; GFX10-WAVE64-NEXT: s_or_saveexec_b64 s[0:1], s[2:3] ; GFX10-WAVE64-NEXT: s_or_saveexec_b64 s[0:1], s[2:3]
; GFX10-WAVE64-NEXT: ; implicit-def: $vgpr2 ; GFX10-WAVE64-NEXT: ; implicit-def: $vgpr2
; GFX10-WAVE64-NEXT: s_xor_b64 exec, exec, s[0:1] ; GFX10-WAVE64-NEXT: s_xor_b64 exec, exec, s[0:1]
; GFX10-WAVE64-NEXT: ; %bb.4: ; %live ; GFX10-WAVE64-NEXT: ; %bb.4: ; %live
; GFX10-WAVE64-NEXT: v_mul_f32_e32 v2, v0, v1 ; GFX10-WAVE64-NEXT: v_mul_f32_e32 v2, v0, v1
; GFX10-WAVE64-NEXT: ; %bb.5: ; %export ; GFX10-WAVE64-NEXT: ; %bb.5: ; %export
; GFX10-WAVE64-NEXT: s_or_b64 exec, exec, s[0:1] ; GFX10-WAVE64-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX10-WAVE64-NEXT: exp mrt0 v2, v2, v2, v2 done vm ; GFX10-WAVE64-NEXT: exp mrt0 v2, v2, v2, v2 done vm
; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: s_endpgm
; GFX10-WAVE64-NEXT: BB14_6: ; GFX10-WAVE64-NEXT: .LBB14_6:
; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0 ; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0
; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm ; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm
; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: s_endpgm
; ;
; GFX10-WAVE32-LABEL: cbranch_kill: ; GFX10-WAVE32-LABEL: cbranch_kill:
; GFX10-WAVE32: ; %bb.0: ; %.entry ; GFX10-WAVE32: ; %bb.0: ; %.entry
; GFX10-WAVE32-NEXT: s_mov_b32 s4, 0 ; GFX10-WAVE32-NEXT: s_mov_b32 s4, 0
; GFX10-WAVE32-NEXT: s_mov_b32 s0, exec_lo ; GFX10-WAVE32-NEXT: s_mov_b32 s0, exec_lo
; GFX10-WAVE32-NEXT: s_mov_b32 s5, s4 ; GFX10-WAVE32-NEXT: s_mov_b32 s5, s4
; GFX10-WAVE32-NEXT: s_mov_b32 s6, s4 ; GFX10-WAVE32-NEXT: s_mov_b32 s6, s4
; GFX10-WAVE32-NEXT: s_mov_b32 s7, s4 ; GFX10-WAVE32-NEXT: s_mov_b32 s7, s4
; GFX10-WAVE32-NEXT: s_mov_b32 s8, s4 ; GFX10-WAVE32-NEXT: s_mov_b32 s8, s4
; GFX10-WAVE32-NEXT: s_mov_b32 s9, s4 ; GFX10-WAVE32-NEXT: s_mov_b32 s9, s4
; GFX10-WAVE32-NEXT: s_mov_b32 s10, s4 ; GFX10-WAVE32-NEXT: s_mov_b32 s10, s4
; GFX10-WAVE32-NEXT: s_mov_b32 s11, s4 ; GFX10-WAVE32-NEXT: s_mov_b32 s11, s4
; GFX10-WAVE32-NEXT: image_sample_lz v1, [v1, v1, v1], s[4:11], s[0:3] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY ; GFX10-WAVE32-NEXT: image_sample_lz v1, [v1, v1, v1], s[4:11], s[0:3] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY
; GFX10-WAVE32-NEXT: s_waitcnt vmcnt(0) ; GFX10-WAVE32-NEXT: s_waitcnt vmcnt(0)
; GFX10-WAVE32-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v1 ; GFX10-WAVE32-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v1
; GFX10-WAVE32-NEXT: s_and_saveexec_b32 s1, vcc_lo ; GFX10-WAVE32-NEXT: s_and_saveexec_b32 s1, vcc_lo
; GFX10-WAVE32-NEXT: s_xor_b32 s1, exec_lo, s1 ; GFX10-WAVE32-NEXT: s_xor_b32 s1, exec_lo, s1
; GFX10-WAVE32-NEXT: s_cbranch_execz BB14_3 ; GFX10-WAVE32-NEXT: s_cbranch_execz .LBB14_3
; GFX10-WAVE32-NEXT: ; %bb.1: ; %kill ; GFX10-WAVE32-NEXT: ; %bb.1: ; %kill
; GFX10-WAVE32-NEXT: s_andn2_b32 s0, s0, exec_lo ; GFX10-WAVE32-NEXT: s_andn2_b32 s0, s0, exec_lo
; GFX10-WAVE32-NEXT: ; implicit-def: $vgpr0 ; GFX10-WAVE32-NEXT: ; implicit-def: $vgpr0
; GFX10-WAVE32-NEXT: ; implicit-def: $vgpr1 ; GFX10-WAVE32-NEXT: ; implicit-def: $vgpr1
; GFX10-WAVE32-NEXT: s_cbranch_scc0 BB14_6 ; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB14_6
; GFX10-WAVE32-NEXT: ; %bb.2: ; %kill ; GFX10-WAVE32-NEXT: ; %bb.2: ; %kill
; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-WAVE32-NEXT: BB14_3: ; %Flow ; GFX10-WAVE32-NEXT: .LBB14_3: ; %Flow
; GFX10-WAVE32-NEXT: s_or_saveexec_b32 s0, s1 ; GFX10-WAVE32-NEXT: s_or_saveexec_b32 s0, s1
; GFX10-WAVE32-NEXT: ; implicit-def: $vgpr2 ; GFX10-WAVE32-NEXT: ; implicit-def: $vgpr2
; GFX10-WAVE32-NEXT: s_xor_b32 exec_lo, exec_lo, s0 ; GFX10-WAVE32-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX10-WAVE32-NEXT: ; %bb.4: ; %live ; GFX10-WAVE32-NEXT: ; %bb.4: ; %live
; GFX10-WAVE32-NEXT: v_mul_f32_e32 v2, v0, v1 ; GFX10-WAVE32-NEXT: v_mul_f32_e32 v2, v0, v1
; GFX10-WAVE32-NEXT: ; %bb.5: ; %export ; GFX10-WAVE32-NEXT: ; %bb.5: ; %export
; GFX10-WAVE32-NEXT: s_or_b32 exec_lo, exec_lo, s0 ; GFX10-WAVE32-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX10-WAVE32-NEXT: exp mrt0 v2, v2, v2, v2 done vm ; GFX10-WAVE32-NEXT: exp mrt0 v2, v2, v2, v2 done vm
; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: s_endpgm
; GFX10-WAVE32-NEXT: BB14_6: ; GFX10-WAVE32-NEXT: .LBB14_6:
; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm ; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm
; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: s_endpgm
.entry: .entry:
%sample = call float @llvm.amdgcn.image.sample.l.2darray.f32.f32(i32 1, float %val1, float %val1, float %val1, float 0.000000e+00, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0) %sample = call float @llvm.amdgcn.image.sample.l.2darray.f32.f32(i32 1, float %val1, float %val1, float %val1, float 0.000000e+00, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0)
%cond0 = fcmp ugt float %sample, 0.000000e+00 %cond0 = fcmp ugt float %sample, 0.000000e+00
br i1 %cond0, label %live, label %kill br i1 %cond0, label %live, label %kill
Show All 12 Lines
} }
define amdgpu_ps void @complex_loop(i32 inreg %cmpa, i32 %cmpb, i32 %cmpc) { define amdgpu_ps void @complex_loop(i32 inreg %cmpa, i32 %cmpb, i32 %cmpc) {
; SI-LABEL: complex_loop: ; SI-LABEL: complex_loop:
; SI: ; %bb.0: ; %.entry ; SI: ; %bb.0: ; %.entry
; SI-NEXT: s_cmp_lt_i32 s0, 1 ; SI-NEXT: s_cmp_lt_i32 s0, 1
; SI-NEXT: v_mov_b32_e32 v2, -1 ; SI-NEXT: v_mov_b32_e32 v2, -1
; SI-NEXT: s_cbranch_scc1 BB15_7 ; SI-NEXT: s_cbranch_scc1 .LBB15_7
; SI-NEXT: ; %bb.1: ; %.lr.ph ; SI-NEXT: ; %bb.1: ; %.lr.ph
; SI-NEXT: s_mov_b64 s[2:3], exec ; SI-NEXT: s_mov_b64 s[2:3], exec
; SI-NEXT: s_mov_b32 s6, 0 ; SI-NEXT: s_mov_b32 s6, 0
; SI-NEXT: s_mov_b64 s[0:1], 0 ; SI-NEXT: s_mov_b64 s[0:1], 0
; SI-NEXT: s_branch BB15_3 ; SI-NEXT: s_branch .LBB15_3
; SI-NEXT: BB15_2: ; %latch ; SI-NEXT: .LBB15_2: ; %latch
; SI-NEXT: ; in Loop: Header=BB15_3 Depth=1 ; SI-NEXT: ; in Loop: Header=BB15_3 Depth=1
; SI-NEXT: s_or_b64 exec, exec, s[4:5] ; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_add_i32 s6, s6, 1 ; SI-NEXT: s_add_i32 s6, s6, 1
; SI-NEXT: v_cmp_ge_i32_e32 vcc, s6, v1 ; SI-NEXT: v_cmp_ge_i32_e32 vcc, s6, v1
; SI-NEXT: s_or_b64 s[0:1], vcc, s[0:1] ; SI-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
; SI-NEXT: v_mov_b32_e32 v2, s6 ; SI-NEXT: v_mov_b32_e32 v2, s6
; SI-NEXT: s_andn2_b64 exec, exec, s[0:1] ; SI-NEXT: s_andn2_b64 exec, exec, s[0:1]
; SI-NEXT: s_cbranch_execz BB15_6 ; SI-NEXT: s_cbranch_execz .LBB15_6
; SI-NEXT: BB15_3: ; %hdr ; SI-NEXT: .LBB15_3: ; %hdr
; SI-NEXT: ; =>This Inner Loop Header: Depth=1 ; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_cmp_gt_u32_e32 vcc, s6, v0 ; SI-NEXT: v_cmp_gt_u32_e32 vcc, s6, v0
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc ; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] ; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz BB15_2 ; SI-NEXT: s_cbranch_execz .LBB15_2
; SI-NEXT: ; %bb.4: ; %kill ; SI-NEXT: ; %bb.4: ; %kill
; SI-NEXT: ; in Loop: Header=BB15_3 Depth=1 ; SI-NEXT: ; in Loop: Header=BB15_3 Depth=1
; SI-NEXT: s_andn2_b64 s[2:3], s[2:3], exec ; SI-NEXT: s_andn2_b64 s[2:3], s[2:3], exec
; SI-NEXT: s_cbranch_scc0 BB15_8 ; SI-NEXT: s_cbranch_scc0 .LBB15_8
; SI-NEXT: ; %bb.5: ; %kill ; SI-NEXT: ; %bb.5: ; %kill
; SI-NEXT: ; in Loop: Header=BB15_3 Depth=1 ; SI-NEXT: ; in Loop: Header=BB15_3 Depth=1
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: s_branch BB15_2 ; SI-NEXT: s_branch .LBB15_2
; SI-NEXT: BB15_6: ; %Flow ; SI-NEXT: .LBB15_6: ; %Flow
; SI-NEXT: s_or_b64 exec, exec, s[0:1] ; SI-NEXT: s_or_b64 exec, exec, s[0:1]
; SI-NEXT: BB15_7: ; %._crit_edge ; SI-NEXT: .LBB15_7: ; %._crit_edge
; SI-NEXT: exp mrt0 v2, v2, v0, v0 done vm ; SI-NEXT: exp mrt0 v2, v2, v0, v0 done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; SI-NEXT: BB15_8: ; SI-NEXT: .LBB15_8:
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: exp null off, off, off, off done vm ; SI-NEXT: exp null off, off, off, off done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; GFX10-WAVE64-LABEL: complex_loop: ; GFX10-WAVE64-LABEL: complex_loop:
; GFX10-WAVE64: ; %bb.0: ; %.entry ; GFX10-WAVE64: ; %bb.0: ; %.entry
; GFX10-WAVE64-NEXT: v_mov_b32_e32 v2, -1 ; GFX10-WAVE64-NEXT: v_mov_b32_e32 v2, -1
; GFX10-WAVE64-NEXT: s_cmp_lt_i32 s0, 1 ; GFX10-WAVE64-NEXT: s_cmp_lt_i32 s0, 1
; GFX10-WAVE64-NEXT: s_cbranch_scc1 BB15_7 ; GFX10-WAVE64-NEXT: s_cbranch_scc1 .LBB15_7
; GFX10-WAVE64-NEXT: ; %bb.1: ; %.lr.ph ; GFX10-WAVE64-NEXT: ; %bb.1: ; %.lr.ph
; GFX10-WAVE64-NEXT: s_mov_b64 s[2:3], exec ; GFX10-WAVE64-NEXT: s_mov_b64 s[2:3], exec
; GFX10-WAVE64-NEXT: s_mov_b32 s6, 0 ; GFX10-WAVE64-NEXT: s_mov_b32 s6, 0
; GFX10-WAVE64-NEXT: s_mov_b64 s[0:1], 0 ; GFX10-WAVE64-NEXT: s_mov_b64 s[0:1], 0
; GFX10-WAVE64-NEXT: s_branch BB15_3 ; GFX10-WAVE64-NEXT: s_branch .LBB15_3
; GFX10-WAVE64-NEXT: BB15_2: ; %latch ; GFX10-WAVE64-NEXT: .LBB15_2: ; %latch
; GFX10-WAVE64-NEXT: ; in Loop: Header=BB15_3 Depth=1 ; GFX10-WAVE64-NEXT: ; in Loop: Header=BB15_3 Depth=1
; GFX10-WAVE64-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX10-WAVE64-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX10-WAVE64-NEXT: s_add_i32 s6, s6, 1 ; GFX10-WAVE64-NEXT: s_add_i32 s6, s6, 1
; GFX10-WAVE64-NEXT: v_cmp_ge_i32_e32 vcc, s6, v1 ; GFX10-WAVE64-NEXT: v_cmp_ge_i32_e32 vcc, s6, v1
; GFX10-WAVE64-NEXT: v_mov_b32_e32 v2, s6 ; GFX10-WAVE64-NEXT: v_mov_b32_e32 v2, s6
; GFX10-WAVE64-NEXT: s_or_b64 s[0:1], vcc, s[0:1] ; GFX10-WAVE64-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
; GFX10-WAVE64-NEXT: s_andn2_b64 exec, exec, s[0:1] ; GFX10-WAVE64-NEXT: s_andn2_b64 exec, exec, s[0:1]
; GFX10-WAVE64-NEXT: s_cbranch_execz BB15_6 ; GFX10-WAVE64-NEXT: s_cbranch_execz .LBB15_6
; GFX10-WAVE64-NEXT: BB15_3: ; %hdr ; GFX10-WAVE64-NEXT: .LBB15_3: ; %hdr
; GFX10-WAVE64-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-WAVE64-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-WAVE64-NEXT: v_cmp_gt_u32_e32 vcc, s6, v0 ; GFX10-WAVE64-NEXT: v_cmp_gt_u32_e32 vcc, s6, v0
; GFX10-WAVE64-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX10-WAVE64-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX10-WAVE64-NEXT: s_xor_b64 s[4:5], exec, s[4:5] ; GFX10-WAVE64-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX10-WAVE64-NEXT: s_cbranch_execz BB15_2 ; GFX10-WAVE64-NEXT: s_cbranch_execz .LBB15_2
; GFX10-WAVE64-NEXT: ; %bb.4: ; %kill ; GFX10-WAVE64-NEXT: ; %bb.4: ; %kill
; GFX10-WAVE64-NEXT: ; in Loop: Header=BB15_3 Depth=1 ; GFX10-WAVE64-NEXT: ; in Loop: Header=BB15_3 Depth=1
; GFX10-WAVE64-NEXT: s_andn2_b64 s[2:3], s[2:3], exec ; GFX10-WAVE64-NEXT: s_andn2_b64 s[2:3], s[2:3], exec
; GFX10-WAVE64-NEXT: s_cbranch_scc0 BB15_8 ; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB15_8
; GFX10-WAVE64-NEXT: ; %bb.5: ; %kill ; GFX10-WAVE64-NEXT: ; %bb.5: ; %kill
; GFX10-WAVE64-NEXT: ; in Loop: Header=BB15_3 Depth=1 ; GFX10-WAVE64-NEXT: ; in Loop: Header=BB15_3 Depth=1
; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0 ; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0
; GFX10-WAVE64-NEXT: s_branch BB15_2 ; GFX10-WAVE64-NEXT: s_branch .LBB15_2
; GFX10-WAVE64-NEXT: BB15_6: ; %Flow ; GFX10-WAVE64-NEXT: .LBB15_6: ; %Flow
; GFX10-WAVE64-NEXT: s_or_b64 exec, exec, s[0:1] ; GFX10-WAVE64-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX10-WAVE64-NEXT: BB15_7: ; %._crit_edge ; GFX10-WAVE64-NEXT: .LBB15_7: ; %._crit_edge
; GFX10-WAVE64-NEXT: exp mrt0 v2, v2, v0, v0 done vm ; GFX10-WAVE64-NEXT: exp mrt0 v2, v2, v0, v0 done vm
; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: s_endpgm
; GFX10-WAVE64-NEXT: BB15_8: ; GFX10-WAVE64-NEXT: .LBB15_8:
; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0 ; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0
; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm ; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm
; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: s_endpgm
; ;
; GFX10-WAVE32-LABEL: complex_loop: ; GFX10-WAVE32-LABEL: complex_loop:
; GFX10-WAVE32: ; %bb.0: ; %.entry ; GFX10-WAVE32: ; %bb.0: ; %.entry
; GFX10-WAVE32-NEXT: v_mov_b32_e32 v2, -1 ; GFX10-WAVE32-NEXT: v_mov_b32_e32 v2, -1
; GFX10-WAVE32-NEXT: s_cmp_lt_i32 s0, 1 ; GFX10-WAVE32-NEXT: s_cmp_lt_i32 s0, 1
; GFX10-WAVE32-NEXT: s_cbranch_scc1 BB15_7 ; GFX10-WAVE32-NEXT: s_cbranch_scc1 .LBB15_7
; GFX10-WAVE32-NEXT: ; %bb.1: ; %.lr.ph ; GFX10-WAVE32-NEXT: ; %bb.1: ; %.lr.ph
; GFX10-WAVE32-NEXT: s_mov_b32 s1, exec_lo ; GFX10-WAVE32-NEXT: s_mov_b32 s1, exec_lo
; GFX10-WAVE32-NEXT: s_mov_b32 s0, 0 ; GFX10-WAVE32-NEXT: s_mov_b32 s0, 0
; GFX10-WAVE32-NEXT: s_mov_b32 s2, 0 ; GFX10-WAVE32-NEXT: s_mov_b32 s2, 0
; GFX10-WAVE32-NEXT: s_branch BB15_3 ; GFX10-WAVE32-NEXT: s_branch .LBB15_3
; GFX10-WAVE32-NEXT: BB15_2: ; %latch ; GFX10-WAVE32-NEXT: .LBB15_2: ; %latch
; GFX10-WAVE32-NEXT: ; in Loop: Header=BB15_3 Depth=1 ; GFX10-WAVE32-NEXT: ; in Loop: Header=BB15_3 Depth=1
; GFX10-WAVE32-NEXT: s_or_b32 exec_lo, exec_lo, s3 ; GFX10-WAVE32-NEXT: s_or_b32 exec_lo, exec_lo, s3
; GFX10-WAVE32-NEXT: s_add_i32 s2, s2, 1 ; GFX10-WAVE32-NEXT: s_add_i32 s2, s2, 1
; GFX10-WAVE32-NEXT: v_cmp_ge_i32_e32 vcc_lo, s2, v1 ; GFX10-WAVE32-NEXT: v_cmp_ge_i32_e32 vcc_lo, s2, v1
; GFX10-WAVE32-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-WAVE32-NEXT: v_mov_b32_e32 v2, s2
; GFX10-WAVE32-NEXT: s_or_b32 s0, vcc_lo, s0 ; GFX10-WAVE32-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, s0 ; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, s0
; GFX10-WAVE32-NEXT: s_cbranch_execz BB15_6 ; GFX10-WAVE32-NEXT: s_cbranch_execz .LBB15_6
; GFX10-WAVE32-NEXT: BB15_3: ; %hdr ; GFX10-WAVE32-NEXT: .LBB15_3: ; %hdr
; GFX10-WAVE32-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-WAVE32-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-WAVE32-NEXT: v_cmp_gt_u32_e32 vcc_lo, s2, v0 ; GFX10-WAVE32-NEXT: v_cmp_gt_u32_e32 vcc_lo, s2, v0
; GFX10-WAVE32-NEXT: s_and_saveexec_b32 s3, vcc_lo ; GFX10-WAVE32-NEXT: s_and_saveexec_b32 s3, vcc_lo
; GFX10-WAVE32-NEXT: s_xor_b32 s3, exec_lo, s3 ; GFX10-WAVE32-NEXT: s_xor_b32 s3, exec_lo, s3
; GFX10-WAVE32-NEXT: s_cbranch_execz BB15_2 ; GFX10-WAVE32-NEXT: s_cbranch_execz .LBB15_2
; GFX10-WAVE32-NEXT: ; %bb.4: ; %kill ; GFX10-WAVE32-NEXT: ; %bb.4: ; %kill
; GFX10-WAVE32-NEXT: ; in Loop: Header=BB15_3 Depth=1 ; GFX10-WAVE32-NEXT: ; in Loop: Header=BB15_3 Depth=1
; GFX10-WAVE32-NEXT: s_andn2_b32 s1, s1, exec_lo ; GFX10-WAVE32-NEXT: s_andn2_b32 s1, s1, exec_lo
; GFX10-WAVE32-NEXT: s_cbranch_scc0 BB15_8 ; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB15_8
; GFX10-WAVE32-NEXT: ; %bb.5: ; %kill ; GFX10-WAVE32-NEXT: ; %bb.5: ; %kill
; GFX10-WAVE32-NEXT: ; in Loop: Header=BB15_3 Depth=1 ; GFX10-WAVE32-NEXT: ; in Loop: Header=BB15_3 Depth=1
; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-WAVE32-NEXT: s_branch BB15_2 ; GFX10-WAVE32-NEXT: s_branch .LBB15_2
; GFX10-WAVE32-NEXT: BB15_6: ; %Flow ; GFX10-WAVE32-NEXT: .LBB15_6: ; %Flow
; GFX10-WAVE32-NEXT: s_or_b32 exec_lo, exec_lo, s0 ; GFX10-WAVE32-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX10-WAVE32-NEXT: BB15_7: ; %._crit_edge ; GFX10-WAVE32-NEXT: .LBB15_7: ; %._crit_edge
; GFX10-WAVE32-NEXT: exp mrt0 v2, v2, v0, v0 done vm ; GFX10-WAVE32-NEXT: exp mrt0 v2, v2, v0, v0 done vm
; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: s_endpgm
; GFX10-WAVE32-NEXT: BB15_8: ; GFX10-WAVE32-NEXT: .LBB15_8:
; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0
; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm ; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm
; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: s_endpgm
.entry: .entry:
%flaga = icmp sgt i32 %cmpa, 0 %flaga = icmp sgt i32 %cmpa, 0
br i1 %flaga, label %.lr.ph, label %._crit_edge br i1 %flaga, label %.lr.ph, label %._crit_edge
.lr.ph: .lr.ph:
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} }
define void @skip_mode_switch(i32 %arg) { define void @skip_mode_switch(i32 %arg) {
; SI-LABEL: skip_mode_switch: ; SI-LABEL: skip_mode_switch:
; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc ; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_cbranch_execz BB16_2 ; SI-NEXT: s_cbranch_execz .LBB16_2
; SI-NEXT: ; %bb.1: ; %bb.0 ; SI-NEXT: ; %bb.1: ; %bb.0
; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3 ; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3
; SI-NEXT: BB16_2: ; %bb.1 ; SI-NEXT: .LBB16_2: ; %bb.1
; SI-NEXT: s_or_b64 exec, exec, s[4:5] ; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31] ; SI-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-WAVE64-LABEL: skip_mode_switch: ; GFX10-WAVE64-LABEL: skip_mode_switch:
; GFX10-WAVE64: ; %bb.0: ; %entry ; GFX10-WAVE64: ; %bb.0: ; %entry
; GFX10-WAVE64-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-WAVE64-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-WAVE64-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-WAVE64-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WAVE64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX10-WAVE64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX10-WAVE64-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX10-WAVE64-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX10-WAVE64-NEXT: s_cbranch_execz BB16_2 ; GFX10-WAVE64-NEXT: s_cbranch_execz .LBB16_2
; GFX10-WAVE64-NEXT: ; %bb.1: ; %bb.0 ; GFX10-WAVE64-NEXT: ; %bb.1: ; %bb.0
; GFX10-WAVE64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3 ; GFX10-WAVE64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3
; GFX10-WAVE64-NEXT: BB16_2: ; %bb.1 ; GFX10-WAVE64-NEXT: .LBB16_2: ; %bb.1
; GFX10-WAVE64-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX10-WAVE64-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX10-WAVE64-NEXT: s_setpc_b64 s[30:31] ; GFX10-WAVE64-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-WAVE32-LABEL: skip_mode_switch: ; GFX10-WAVE32-LABEL: skip_mode_switch:
; GFX10-WAVE32: ; %bb.0: ; %entry ; GFX10-WAVE32: ; %bb.0: ; %entry
; GFX10-WAVE32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-WAVE32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-WAVE32-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-WAVE32-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WAVE32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX10-WAVE32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX10-WAVE32-NEXT: s_and_saveexec_b32 s4, vcc_lo ; GFX10-WAVE32-NEXT: s_and_saveexec_b32 s4, vcc_lo
; GFX10-WAVE32-NEXT: s_cbranch_execz BB16_2 ; GFX10-WAVE32-NEXT: s_cbranch_execz .LBB16_2
; GFX10-WAVE32-NEXT: ; %bb.1: ; %bb.0 ; GFX10-WAVE32-NEXT: ; %bb.1: ; %bb.0
; GFX10-WAVE32-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3 ; GFX10-WAVE32-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3
; GFX10-WAVE32-NEXT: BB16_2: ; %bb.1 ; GFX10-WAVE32-NEXT: .LBB16_2: ; %bb.1
; GFX10-WAVE32-NEXT: s_or_b32 exec_lo, exec_lo, s4 ; GFX10-WAVE32-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-WAVE32-NEXT: s_setpc_b64 s[30:31] ; GFX10-WAVE32-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%cmp = icmp eq i32 %arg, 0 %cmp = icmp eq i32 %arg, 0
br i1 %cmp, label %bb.0, label %bb.1 br i1 %cmp, label %bb.0, label %bb.1
bb.0: bb.0:
call void @llvm.amdgcn.s.setreg(i32 2049, i32 3) call void @llvm.amdgcn.s.setreg(i32 2049, i32 3)
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llvm/test/CodeGen/AMDGPU/smrd-vccz-bug.ll

; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VCCZ-BUG %s ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VCCZ-BUG %s
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VCCZ-BUG %s ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VCCZ-BUG %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-FUNC: {{^}}vccz_workaround: ; GCN-FUNC: {{^}}vccz_workaround:
; GCN: s_load_dword [[REG:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], ; GCN: s_load_dword [[REG:s[0-9]+]], s[{{[0-9]+:[0-9]+}}],
; GCN: v_cmp_neq_f32_e64 {{[^,]*}}, [[REG]], 0{{$}} ; GCN: v_cmp_neq_f32_e64 {{[^,]*}}, [[REG]], 0{{$}}
; VCCZ-BUG: s_waitcnt lgkmcnt(0) ; VCCZ-BUG: s_waitcnt lgkmcnt(0)
; VCCZ-BUG: s_mov_b64 vcc, vcc ; VCCZ-BUG: s_mov_b64 vcc, vcc
; GCN-NOT: s_mov_b64 vcc, vcc ; GCN-NOT: s_mov_b64 vcc, vcc
; GCN: s_cbranch_vccnz [[EXIT:[0-9A-Za-z_]+]] ; GCN: s_cbranch_vccnz [[EXIT:.L[0-9A-Za-z_]+]]
; GCN: buffer_store_dword ; GCN: buffer_store_dword
; GCN: [[EXIT]]: ; GCN: [[EXIT]]:
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @vccz_workaround(i32 addrspace(4)* %in, i32 addrspace(1)* %out, float %cond) { define amdgpu_kernel void @vccz_workaround(i32 addrspace(4)* %in, i32 addrspace(1)* %out, float %cond) {
entry: entry:
%cnd = fcmp oeq float 0.0, %cond %cnd = fcmp oeq float 0.0, %cond
%sgpr = load volatile i32, i32 addrspace(4)* %in %sgpr = load volatile i32, i32 addrspace(4)* %in
br i1 %cnd, label %if, label %endif br i1 %cnd, label %if, label %endif
if: if:
store i32 %sgpr, i32 addrspace(1)* %out store i32 %sgpr, i32 addrspace(1)* %out
br label %endif br label %endif
endif: endif:
ret void ret void
} }
; GCN-FUNC: {{^}}vccz_noworkaround: ; GCN-FUNC: {{^}}vccz_noworkaround:
; GCN: v_cmp_neq_f32_e32 vcc, 0, v{{[0-9]+}} ; GCN: v_cmp_neq_f32_e32 vcc, 0, v{{[0-9]+}}
; GCN-NOT: s_waitcnt lgkmcnt(0) ; GCN-NOT: s_waitcnt lgkmcnt(0)
; GCN-NOT: s_mov_b64 vcc, vcc ; GCN-NOT: s_mov_b64 vcc, vcc
; GCN: s_cbranch_vccnz [[EXIT:[0-9A-Za-z_]+]] ; GCN: s_cbranch_vccnz [[EXIT:.L[0-9A-Za-z_]+]]
; GCN: buffer_store_dword ; GCN: buffer_store_dword
; GCN: [[EXIT]]: ; GCN: [[EXIT]]:
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @vccz_noworkaround(float addrspace(1)* %in, float addrspace(1)* %out) { define amdgpu_kernel void @vccz_noworkaround(float addrspace(1)* %in, float addrspace(1)* %out) {
entry: entry:
%vgpr = load volatile float, float addrspace(1)* %in %vgpr = load volatile float, float addrspace(1)* %in
%cnd = fcmp oeq float 0.0, %vgpr %cnd = fcmp oeq float 0.0, %vgpr
br i1 %cnd, label %if, label %endif br i1 %cnd, label %if, label %endif
if: if:
store float %vgpr, float addrspace(1)* %out store float %vgpr, float addrspace(1)* %out
br label %endif br label %endif
endif: endif:
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/spill-cfg-position.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs -stress-regalloc=6 < %s | FileCheck %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs -stress-regalloc=6 < %s | FileCheck %s
; Inline spiller can decide to move a spill as early as possible in the basic block. ; Inline spiller can decide to move a spill as early as possible in the basic block.
; It will skip phis and label, but we also need to make sure it skips instructions ; It will skip phis and label, but we also need to make sure it skips instructions
; in the basic block prologue which restore exec mask. ; in the basic block prologue which restore exec mask.
; Make sure instruction to restore exec mask immediately follows label ; Make sure instruction to restore exec mask immediately follows label
; CHECK-LABEL: {{^}}spill_cfg_position: ; CHECK-LABEL: {{^}}spill_cfg_position:
; CHECK: s_cbranch_execz [[LABEL1:BB[0-9_]+]] ; CHECK: s_cbranch_execz [[LABEL1:.LBB[0-9_]+]]
; CHECK: {{^}}[[LABEL1]]: ; CHECK: {{^}}[[LABEL1]]:
; CHECK: s_cbranch_execz [[LABEL2:BB[0-9_]+]] ; CHECK: s_cbranch_execz [[LABEL2:.LBB[0-9_]+]]
; CHECK: {{^}}[[LABEL2]]: ; CHECK: {{^}}[[LABEL2]]:
; CHECK-NEXT: s_or_b64 exec ; CHECK-NEXT: s_or_b64 exec
; CHECK: buffer_ ; CHECK: buffer_
define amdgpu_kernel void @spill_cfg_position(i32 addrspace(1)* nocapture %arg) { define amdgpu_kernel void @spill_cfg_position(i32 addrspace(1)* nocapture %arg) {
bb: bb:
%tmp1 = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %tmp1 = tail call i32 @llvm.amdgcn.workitem.id.x() #0
%tmp14 = load i32, i32 addrspace(1)* %arg, align 4 %tmp14 = load i32, i32 addrspace(1)* %arg, align 4
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llvm/test/CodeGen/AMDGPU/spill-m0.ll

Show All 14 Lines
; TOVGPR: v_writelane_b32 [[SPILL_VREG:v[0-9]+]], [[M0_COPY]], [[M0_LANE:[0-9]+]] ; TOVGPR: v_writelane_b32 [[SPILL_VREG:v[0-9]+]], [[M0_COPY]], [[M0_LANE:[0-9]+]]
; TOVMEM: s_mov_b64 [[COPY_EXEC:s\[[0-9]+:[0-9]+\]]], exec ; TOVMEM: s_mov_b64 [[COPY_EXEC:s\[[0-9]+:[0-9]+\]]], exec
; TOVMEM: s_mov_b64 exec, 1 ; TOVMEM: s_mov_b64 exec, 1
; TOVMEM: v_writelane_b32 [[SPILL_VREG:v[0-9]+]], [[M0_COPY]], 0 ; TOVMEM: v_writelane_b32 [[SPILL_VREG:v[0-9]+]], [[M0_COPY]], 0
; TOVMEM: buffer_store_dword [[SPILL_VREG]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:4 ; 4-byte Folded Spill ; TOVMEM: buffer_store_dword [[SPILL_VREG]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:4 ; 4-byte Folded Spill
; TOVMEM: s_mov_b64 exec, [[COPY_EXEC]] ; TOVMEM: s_mov_b64 exec, [[COPY_EXEC]]
; GCN: s_cbranch_scc1 [[ENDIF:BB[0-9]+_[0-9]+]] ; GCN: s_cbranch_scc1 [[ENDIF:.LBB[0-9]+_[0-9]+]]
; GCN: [[ENDIF]]: ; GCN: [[ENDIF]]:
; TOVGPR: v_readlane_b32 [[M0_RESTORE:s[0-9]+]], [[SPILL_VREG]], [[M0_LANE]] ; TOVGPR: v_readlane_b32 [[M0_RESTORE:s[0-9]+]], [[SPILL_VREG]], [[M0_LANE]]
; TOVGPR: s_mov_b32 m0, [[M0_RESTORE]] ; TOVGPR: s_mov_b32 m0, [[M0_RESTORE]]
; TOVMEM: buffer_load_dword [[RELOAD_VREG:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:4 ; 4-byte Folded Reload ; TOVMEM: buffer_load_dword [[RELOAD_VREG:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:4 ; 4-byte Folded Reload
; TOVMEM: s_waitcnt vmcnt(0) ; TOVMEM: s_waitcnt vmcnt(0)
; TOVMEM: v_readlane_b32 [[M0_RESTORE:s[0-9]+]], [[RELOAD_VREG]], 0 ; TOVMEM: v_readlane_b32 [[M0_RESTORE:s[0-9]+]], [[RELOAD_VREG]], 0
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llvm/test/CodeGen/AMDGPU/srem64.ll

Show First 20 Lines • Show All 141 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: s_subb_u32 s11, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s11, 0, 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[16:17], s[10:11], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[16:17], s[10:11], 63
; GCN-IR-NEXT: s_mov_b32 s9, 0 ; GCN-IR-NEXT: s_mov_b32 s9, 0
; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17] ; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17]
; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[16:17], s[10:11], 63 ; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[16:17], s[10:11], 63
; GCN-IR-NEXT: s_xor_b64 s[18:19], s[14:15], -1 ; GCN-IR-NEXT: s_xor_b64 s[18:19], s[14:15], -1
; GCN-IR-NEXT: s_and_b64 s[16:17], s[18:19], s[16:17] ; GCN-IR-NEXT: s_and_b64 s[16:17], s[18:19], s[16:17]
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[16:17] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[16:17]
; GCN-IR-NEXT: s_cbranch_vccz BB0_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_5
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s14, s10, 1 ; GCN-IR-NEXT: s_add_u32 s14, s10, 1
; GCN-IR-NEXT: v_mov_b32_e32 v0, s10 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s10
; GCN-IR-NEXT: s_addc_u32 s15, s11, 0 ; GCN-IR-NEXT: s_addc_u32 s15, s11, 0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s11 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s11
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[14:15], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[14:15], v[0:1]
; GCN-IR-NEXT: s_sub_i32 s10, 63, s10 ; GCN-IR-NEXT: s_sub_i32 s10, 63, s10
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[6:7], s10 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[6:7], s10
; GCN-IR-NEXT: s_cbranch_vccz BB0_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[14:15], s[6:7], s14 ; GCN-IR-NEXT: s_lshr_b64 s[14:15], s[6:7], s14
; GCN-IR-NEXT: s_add_u32 s16, s0, -1 ; GCN-IR-NEXT: s_add_u32 s16, s0, -1
; GCN-IR-NEXT: s_addc_u32 s17, s1, -1 ; GCN-IR-NEXT: s_addc_u32 s17, s1, -1
; GCN-IR-NEXT: s_not_b64 s[2:3], s[8:9] ; GCN-IR-NEXT: s_not_b64 s[2:3], s[8:9]
; GCN-IR-NEXT: s_mov_b32 s13, s9 ; GCN-IR-NEXT: s_mov_b32 s13, s9
; GCN-IR-NEXT: s_add_u32 s8, s2, s12 ; GCN-IR-NEXT: s_add_u32 s8, s2, s12
; GCN-IR-NEXT: s_addc_u32 s9, s3, s9 ; GCN-IR-NEXT: s_addc_u32 s9, s3, s9
; GCN-IR-NEXT: s_mov_b64 s[12:13], 0 ; GCN-IR-NEXT: s_mov_b64 s[12:13], 0
; GCN-IR-NEXT: s_mov_b32 s3, 0 ; GCN-IR-NEXT: s_mov_b32 s3, 0
; GCN-IR-NEXT: BB0_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB0_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[14:15], s[14:15], 1 ; GCN-IR-NEXT: s_lshl_b64 s[14:15], s[14:15], 1
; GCN-IR-NEXT: s_lshr_b32 s2, s11, 31 ; GCN-IR-NEXT: s_lshr_b32 s2, s11, 31
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1
; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[2:3] ; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[2:3]
; GCN-IR-NEXT: s_or_b64 s[10:11], s[12:13], s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[12:13], s[10:11]
; GCN-IR-NEXT: s_sub_u32 s2, s16, s14 ; GCN-IR-NEXT: s_sub_u32 s2, s16, s14
; GCN-IR-NEXT: s_subb_u32 s2, s17, s15 ; GCN-IR-NEXT: s_subb_u32 s2, s17, s15
; GCN-IR-NEXT: s_ashr_i32 s12, s2, 31 ; GCN-IR-NEXT: s_ashr_i32 s12, s2, 31
; GCN-IR-NEXT: s_mov_b32 s13, s12 ; GCN-IR-NEXT: s_mov_b32 s13, s12
; GCN-IR-NEXT: s_and_b32 s2, s12, 1 ; GCN-IR-NEXT: s_and_b32 s2, s12, 1
; GCN-IR-NEXT: s_and_b64 s[18:19], s[12:13], s[0:1] ; GCN-IR-NEXT: s_and_b64 s[18:19], s[12:13], s[0:1]
; GCN-IR-NEXT: s_sub_u32 s14, s14, s18 ; GCN-IR-NEXT: s_sub_u32 s14, s14, s18
; GCN-IR-NEXT: v_mov_b32_e32 v0, s8 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s8
; GCN-IR-NEXT: s_subb_u32 s15, s15, s19 ; GCN-IR-NEXT: s_subb_u32 s15, s15, s19
; GCN-IR-NEXT: v_mov_b32_e32 v1, s9 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s9
; GCN-IR-NEXT: s_add_u32 s8, s8, 1 ; GCN-IR-NEXT: s_add_u32 s8, s8, 1
; GCN-IR-NEXT: s_addc_u32 s9, s9, 0 ; GCN-IR-NEXT: s_addc_u32 s9, s9, 0
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
; GCN-IR-NEXT: s_mov_b64 s[12:13], s[2:3] ; GCN-IR-NEXT: s_mov_b64 s[12:13], s[2:3]
; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_cbranch_vccz BB0_3 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_3
; GCN-IR-NEXT: BB0_4: ; %Flow6 ; GCN-IR-NEXT: .LBB0_4: ; %Flow6
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[10:11], 1 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[10:11], 1
; GCN-IR-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] ; GCN-IR-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
; GCN-IR-NEXT: v_mov_b32_e32 v0, s2 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s2
; GCN-IR-NEXT: v_mov_b32_e32 v1, s3 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s3
; GCN-IR-NEXT: s_branch BB0_6 ; GCN-IR-NEXT: s_branch .LBB0_6
; GCN-IR-NEXT: BB0_5: ; GCN-IR-NEXT: .LBB0_5:
; GCN-IR-NEXT: v_mov_b32_e32 v0, s7 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s7
; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[14:15] ; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[14:15]
; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[14:15] ; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[14:15]
; GCN-IR-NEXT: BB0_6: ; %udiv-end ; GCN-IR-NEXT: .LBB0_6: ; %udiv-end
; GCN-IR-NEXT: v_mul_lo_u32 v1, s0, v1 ; GCN-IR-NEXT: v_mul_lo_u32 v1, s0, v1
; GCN-IR-NEXT: v_mul_hi_u32 v2, s0, v0 ; GCN-IR-NEXT: v_mul_hi_u32 v2, s0, v0
; GCN-IR-NEXT: v_mul_lo_u32 v3, s1, v0 ; GCN-IR-NEXT: v_mul_lo_u32 v3, s1, v0
; GCN-IR-NEXT: v_mul_lo_u32 v0, s0, v0 ; GCN-IR-NEXT: v_mul_lo_u32 v0, s0, v0
; GCN-IR-NEXT: s_mov_b32 s11, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s11, 0xf000
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v3 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GCN-IR-NEXT: v_mov_b32_e32 v2, s7 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s7
▲ Show 20 Lines • Show All 165 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
; GCN-IR-NEXT: s_xor_b64 s[8:9], s[6:7], -1 ; GCN-IR-NEXT: s_xor_b64 s[8:9], s[6:7], -1
; GCN-IR-NEXT: v_mov_b32_e32 v2, v4 ; GCN-IR-NEXT: v_mov_b32_e32 v2, v4
; GCN-IR-NEXT: v_mov_b32_e32 v13, v11 ; GCN-IR-NEXT: v_mov_b32_e32 v13, v11
; GCN-IR-NEXT: v_cndmask_b32_e64 v10, v1, 0, s[6:7] ; GCN-IR-NEXT: v_cndmask_b32_e64 v10, v1, 0, s[6:7]
; GCN-IR-NEXT: s_and_b64 s[4:5], s[8:9], s[4:5] ; GCN-IR-NEXT: s_and_b64 s[4:5], s[8:9], s[4:5]
; GCN-IR-NEXT: v_cndmask_b32_e64 v9, v0, 0, s[6:7] ; GCN-IR-NEXT: v_cndmask_b32_e64 v9, v0, 0, s[6:7]
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB1_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB1_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, 1, v7 ; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, 1, v7
; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, 0, v8, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, 0, v8, vcc
; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[14:15], v[7:8] ; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[14:15], v[7:8]
; GCN-IR-NEXT: v_sub_i32_e64 v7, s[4:5], 63, v7 ; GCN-IR-NEXT: v_sub_i32_e64 v7, s[4:5], 63, v7
; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[0:1], v7 ; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[0:1], v7
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB1_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB1_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_add_i32_e32 v18, vcc, -1, v5 ; GCN-IR-NEXT: v_add_i32_e32 v18, vcc, -1, v5
; GCN-IR-NEXT: v_addc_u32_e32 v19, vcc, -1, v6, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v19, vcc, -1, v6, vcc
; GCN-IR-NEXT: v_not_b32_e32 v3, v3 ; GCN-IR-NEXT: v_not_b32_e32 v3, v3
; GCN-IR-NEXT: v_lshr_b64 v[14:15], v[0:1], v14 ; GCN-IR-NEXT: v_lshr_b64 v[14:15], v[0:1], v14
; GCN-IR-NEXT: v_not_b32_e32 v9, v11 ; GCN-IR-NEXT: v_not_b32_e32 v9, v11
; GCN-IR-NEXT: v_add_i32_e32 v11, vcc, v3, v12 ; GCN-IR-NEXT: v_add_i32_e32 v11, vcc, v3, v12
; GCN-IR-NEXT: v_mov_b32_e32 v16, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v16, 0
; GCN-IR-NEXT: v_addc_u32_e32 v12, vcc, v9, v13, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v12, vcc, v9, v13, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v17, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v17, 0
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: BB1_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB1_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[14:15], v[14:15], 1 ; GCN-IR-NEXT: v_lshl_b64 v[14:15], v[14:15], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v3, 31, v8 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v3, 31, v8
; GCN-IR-NEXT: v_or_b32_e32 v3, v14, v3 ; GCN-IR-NEXT: v_or_b32_e32 v3, v14, v3
; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1 ; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1
; GCN-IR-NEXT: v_sub_i32_e32 v9, vcc, v18, v3 ; GCN-IR-NEXT: v_sub_i32_e32 v9, vcc, v18, v3
; GCN-IR-NEXT: v_subb_u32_e32 v9, vcc, v19, v15, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v9, vcc, v19, v15, vcc
; GCN-IR-NEXT: v_or_b32_e32 v7, v16, v7 ; GCN-IR-NEXT: v_or_b32_e32 v7, v16, v7
; GCN-IR-NEXT: v_add_i32_e32 v16, vcc, 1, v11 ; GCN-IR-NEXT: v_add_i32_e32 v16, vcc, 1, v11
; GCN-IR-NEXT: v_or_b32_e32 v8, v17, v8 ; GCN-IR-NEXT: v_or_b32_e32 v8, v17, v8
; GCN-IR-NEXT: v_ashrrev_i32_e32 v13, 31, v9 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v13, 31, v9
; GCN-IR-NEXT: v_addc_u32_e32 v17, vcc, 0, v12, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v17, vcc, 0, v12, vcc
; GCN-IR-NEXT: v_and_b32_e32 v9, 1, v13 ; GCN-IR-NEXT: v_and_b32_e32 v9, 1, v13
; GCN-IR-NEXT: v_and_b32_e32 v20, v13, v6 ; GCN-IR-NEXT: v_and_b32_e32 v20, v13, v6
; GCN-IR-NEXT: v_and_b32_e32 v13, v13, v5 ; GCN-IR-NEXT: v_and_b32_e32 v13, v13, v5
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[16:17], v[11:12] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[16:17], v[11:12]
; GCN-IR-NEXT: v_mov_b32_e32 v11, v16 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v16
; GCN-IR-NEXT: v_sub_i32_e64 v14, s[4:5], v3, v13 ; GCN-IR-NEXT: v_sub_i32_e64 v14, s[4:5], v3, v13
; GCN-IR-NEXT: v_mov_b32_e32 v12, v17 ; GCN-IR-NEXT: v_mov_b32_e32 v12, v17
; GCN-IR-NEXT: v_mov_b32_e32 v17, v10 ; GCN-IR-NEXT: v_mov_b32_e32 v17, v10
; GCN-IR-NEXT: v_subb_u32_e64 v15, s[4:5], v15, v20, s[4:5] ; GCN-IR-NEXT: v_subb_u32_e64 v15, s[4:5], v15, v20, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v16, v9 ; GCN-IR-NEXT: v_mov_b32_e32 v16, v9
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execnz BB1_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB1_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: BB1_5: ; %Flow3 ; GCN-IR-NEXT: .LBB1_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1 ; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1
; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v8 ; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v8
; GCN-IR-NEXT: v_or_b32_e32 v9, v9, v7 ; GCN-IR-NEXT: v_or_b32_e32 v9, v9, v7
; GCN-IR-NEXT: BB1_6: ; %Flow4 ; GCN-IR-NEXT: .LBB1_6: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_mul_lo_u32 v3, v5, v10 ; GCN-IR-NEXT: v_mul_lo_u32 v3, v5, v10
; GCN-IR-NEXT: v_mul_hi_u32 v7, v5, v9 ; GCN-IR-NEXT: v_mul_hi_u32 v7, v5, v9
; GCN-IR-NEXT: v_mul_lo_u32 v6, v6, v9 ; GCN-IR-NEXT: v_mul_lo_u32 v6, v6, v9
; GCN-IR-NEXT: v_mul_lo_u32 v5, v5, v9 ; GCN-IR-NEXT: v_mul_lo_u32 v5, v5, v9
; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, v7, v3 ; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, v7, v3
; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, v3, v6 ; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, v3, v6
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v5 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v5
▲ Show 20 Lines • Show All 581 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: s_subb_u32 s13, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s13, 0, 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[18:19], s[12:13], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[18:19], s[12:13], 63
; GCN-IR-NEXT: s_mov_b32 s11, 0 ; GCN-IR-NEXT: s_mov_b32 s11, 0
; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[18:19] ; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[18:19]
; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[18:19], s[12:13], 63 ; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[18:19], s[12:13], 63
; GCN-IR-NEXT: s_xor_b64 s[20:21], s[16:17], -1 ; GCN-IR-NEXT: s_xor_b64 s[20:21], s[16:17], -1
; GCN-IR-NEXT: s_and_b64 s[18:19], s[20:21], s[18:19] ; GCN-IR-NEXT: s_and_b64 s[18:19], s[20:21], s[18:19]
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[18:19] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[18:19]
; GCN-IR-NEXT: s_cbranch_vccz BB8_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB8_5
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s16, s12, 1 ; GCN-IR-NEXT: s_add_u32 s16, s12, 1
; GCN-IR-NEXT: v_mov_b32_e32 v0, s12 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s12
; GCN-IR-NEXT: s_addc_u32 s17, s13, 0 ; GCN-IR-NEXT: s_addc_u32 s17, s13, 0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s13 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s13
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[16:17], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[16:17], v[0:1]
; GCN-IR-NEXT: s_sub_i32 s12, 63, s12 ; GCN-IR-NEXT: s_sub_i32 s12, 63, s12
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[2:3], s12 ; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[2:3], s12
; GCN-IR-NEXT: s_cbranch_vccz BB8_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB8_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[16:17], s[2:3], s16 ; GCN-IR-NEXT: s_lshr_b64 s[16:17], s[2:3], s16
; GCN-IR-NEXT: s_add_u32 s18, s8, -1 ; GCN-IR-NEXT: s_add_u32 s18, s8, -1
; GCN-IR-NEXT: s_addc_u32 s19, s9, -1 ; GCN-IR-NEXT: s_addc_u32 s19, s9, -1
; GCN-IR-NEXT: s_not_b64 s[6:7], s[10:11] ; GCN-IR-NEXT: s_not_b64 s[6:7], s[10:11]
; GCN-IR-NEXT: s_mov_b32 s15, s11 ; GCN-IR-NEXT: s_mov_b32 s15, s11
; GCN-IR-NEXT: s_add_u32 s10, s6, s14 ; GCN-IR-NEXT: s_add_u32 s10, s6, s14
; GCN-IR-NEXT: s_addc_u32 s11, s7, s11 ; GCN-IR-NEXT: s_addc_u32 s11, s7, s11
; GCN-IR-NEXT: s_mov_b64 s[14:15], 0 ; GCN-IR-NEXT: s_mov_b64 s[14:15], 0
; GCN-IR-NEXT: s_mov_b32 s7, 0 ; GCN-IR-NEXT: s_mov_b32 s7, 0
; GCN-IR-NEXT: BB8_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB8_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[16:17], s[16:17], 1 ; GCN-IR-NEXT: s_lshl_b64 s[16:17], s[16:17], 1
; GCN-IR-NEXT: s_lshr_b32 s6, s13, 31 ; GCN-IR-NEXT: s_lshr_b32 s6, s13, 31
; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1 ; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1
; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[6:7]
; GCN-IR-NEXT: s_or_b64 s[12:13], s[14:15], s[12:13] ; GCN-IR-NEXT: s_or_b64 s[12:13], s[14:15], s[12:13]
; GCN-IR-NEXT: s_sub_u32 s6, s18, s16 ; GCN-IR-NEXT: s_sub_u32 s6, s18, s16
; GCN-IR-NEXT: s_subb_u32 s6, s19, s17 ; GCN-IR-NEXT: s_subb_u32 s6, s19, s17
; GCN-IR-NEXT: s_ashr_i32 s14, s6, 31 ; GCN-IR-NEXT: s_ashr_i32 s14, s6, 31
; GCN-IR-NEXT: s_mov_b32 s15, s14 ; GCN-IR-NEXT: s_mov_b32 s15, s14
; GCN-IR-NEXT: s_and_b32 s6, s14, 1 ; GCN-IR-NEXT: s_and_b32 s6, s14, 1
; GCN-IR-NEXT: s_and_b64 s[20:21], s[14:15], s[8:9] ; GCN-IR-NEXT: s_and_b64 s[20:21], s[14:15], s[8:9]
; GCN-IR-NEXT: s_sub_u32 s16, s16, s20 ; GCN-IR-NEXT: s_sub_u32 s16, s16, s20
; GCN-IR-NEXT: v_mov_b32_e32 v0, s10 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s10
; GCN-IR-NEXT: s_subb_u32 s17, s17, s21 ; GCN-IR-NEXT: s_subb_u32 s17, s17, s21
; GCN-IR-NEXT: v_mov_b32_e32 v1, s11 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s11
; GCN-IR-NEXT: s_add_u32 s10, s10, 1 ; GCN-IR-NEXT: s_add_u32 s10, s10, 1
; GCN-IR-NEXT: s_addc_u32 s11, s11, 0 ; GCN-IR-NEXT: s_addc_u32 s11, s11, 0
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
; GCN-IR-NEXT: s_mov_b64 s[14:15], s[6:7] ; GCN-IR-NEXT: s_mov_b64 s[14:15], s[6:7]
; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_cbranch_vccz BB8_3 ; GCN-IR-NEXT: s_cbranch_vccz .LBB8_3
; GCN-IR-NEXT: BB8_4: ; %Flow6 ; GCN-IR-NEXT: .LBB8_4: ; %Flow6
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[12:13], 1 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[12:13], 1
; GCN-IR-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11] ; GCN-IR-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
; GCN-IR-NEXT: v_mov_b32_e32 v1, s7 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s7
; GCN-IR-NEXT: s_branch BB8_6 ; GCN-IR-NEXT: s_branch .LBB8_6
; GCN-IR-NEXT: BB8_5: ; GCN-IR-NEXT: .LBB8_5:
; GCN-IR-NEXT: v_mov_b32_e32 v0, s3 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s3
; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[16:17] ; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[16:17]
; GCN-IR-NEXT: v_mov_b32_e32 v0, s2 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s2
; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[16:17] ; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[16:17]
; GCN-IR-NEXT: BB8_6: ; %udiv-end ; GCN-IR-NEXT: .LBB8_6: ; %udiv-end
; GCN-IR-NEXT: v_mul_lo_u32 v1, s8, v1 ; GCN-IR-NEXT: v_mul_lo_u32 v1, s8, v1
; GCN-IR-NEXT: v_mul_hi_u32 v2, s8, v0 ; GCN-IR-NEXT: v_mul_hi_u32 v2, s8, v0
; GCN-IR-NEXT: v_mul_lo_u32 v3, s9, v0 ; GCN-IR-NEXT: v_mul_lo_u32 v3, s9, v0
; GCN-IR-NEXT: v_mul_lo_u32 v0, s8, v0 ; GCN-IR-NEXT: v_mul_lo_u32 v0, s8, v0
; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v3 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GCN-IR-NEXT: v_mov_b32_e32 v2, s3 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s3
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: s_subb_u32 s13, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s13, 0, 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[18:19], s[12:13], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[18:19], s[12:13], 63
; GCN-IR-NEXT: s_mov_b32 s11, 0 ; GCN-IR-NEXT: s_mov_b32 s11, 0
; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[18:19] ; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[18:19]
; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[18:19], s[12:13], 63 ; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[18:19], s[12:13], 63
; GCN-IR-NEXT: s_xor_b64 s[20:21], s[16:17], -1 ; GCN-IR-NEXT: s_xor_b64 s[20:21], s[16:17], -1
; GCN-IR-NEXT: s_and_b64 s[18:19], s[20:21], s[18:19] ; GCN-IR-NEXT: s_and_b64 s[18:19], s[20:21], s[18:19]
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[18:19] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[18:19]
; GCN-IR-NEXT: s_cbranch_vccz BB9_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB9_5
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s16, s12, 1 ; GCN-IR-NEXT: s_add_u32 s16, s12, 1
; GCN-IR-NEXT: v_mov_b32_e32 v0, s12 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s12
; GCN-IR-NEXT: s_addc_u32 s17, s13, 0 ; GCN-IR-NEXT: s_addc_u32 s17, s13, 0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s13 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s13
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[16:17], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[16:17], v[0:1]
; GCN-IR-NEXT: s_sub_i32 s12, 63, s12 ; GCN-IR-NEXT: s_sub_i32 s12, 63, s12
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[2:3], s12 ; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[2:3], s12
; GCN-IR-NEXT: s_cbranch_vccz BB9_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB9_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[16:17], s[2:3], s16 ; GCN-IR-NEXT: s_lshr_b64 s[16:17], s[2:3], s16
; GCN-IR-NEXT: s_add_u32 s18, s6, -1 ; GCN-IR-NEXT: s_add_u32 s18, s6, -1
; GCN-IR-NEXT: s_addc_u32 s19, s7, -1 ; GCN-IR-NEXT: s_addc_u32 s19, s7, -1
; GCN-IR-NEXT: s_not_b64 s[8:9], s[10:11] ; GCN-IR-NEXT: s_not_b64 s[8:9], s[10:11]
; GCN-IR-NEXT: s_mov_b32 s15, s11 ; GCN-IR-NEXT: s_mov_b32 s15, s11
; GCN-IR-NEXT: s_add_u32 s10, s8, s14 ; GCN-IR-NEXT: s_add_u32 s10, s8, s14
; GCN-IR-NEXT: s_addc_u32 s11, s9, s11 ; GCN-IR-NEXT: s_addc_u32 s11, s9, s11
; GCN-IR-NEXT: s_mov_b64 s[14:15], 0 ; GCN-IR-NEXT: s_mov_b64 s[14:15], 0
; GCN-IR-NEXT: s_mov_b32 s9, 0 ; GCN-IR-NEXT: s_mov_b32 s9, 0
; GCN-IR-NEXT: BB9_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB9_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[16:17], s[16:17], 1 ; GCN-IR-NEXT: s_lshl_b64 s[16:17], s[16:17], 1
; GCN-IR-NEXT: s_lshr_b32 s8, s13, 31 ; GCN-IR-NEXT: s_lshr_b32 s8, s13, 31
; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1 ; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1
; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[8:9] ; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[8:9]
; GCN-IR-NEXT: s_or_b64 s[12:13], s[14:15], s[12:13] ; GCN-IR-NEXT: s_or_b64 s[12:13], s[14:15], s[12:13]
; GCN-IR-NEXT: s_sub_u32 s8, s18, s16 ; GCN-IR-NEXT: s_sub_u32 s8, s18, s16
; GCN-IR-NEXT: s_subb_u32 s8, s19, s17 ; GCN-IR-NEXT: s_subb_u32 s8, s19, s17
; GCN-IR-NEXT: s_ashr_i32 s14, s8, 31 ; GCN-IR-NEXT: s_ashr_i32 s14, s8, 31
; GCN-IR-NEXT: s_mov_b32 s15, s14 ; GCN-IR-NEXT: s_mov_b32 s15, s14
; GCN-IR-NEXT: s_and_b32 s8, s14, 1 ; GCN-IR-NEXT: s_and_b32 s8, s14, 1
; GCN-IR-NEXT: s_and_b64 s[20:21], s[14:15], s[6:7] ; GCN-IR-NEXT: s_and_b64 s[20:21], s[14:15], s[6:7]
; GCN-IR-NEXT: s_sub_u32 s16, s16, s20 ; GCN-IR-NEXT: s_sub_u32 s16, s16, s20
; GCN-IR-NEXT: v_mov_b32_e32 v0, s10 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s10
; GCN-IR-NEXT: s_subb_u32 s17, s17, s21 ; GCN-IR-NEXT: s_subb_u32 s17, s17, s21
; GCN-IR-NEXT: v_mov_b32_e32 v1, s11 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s11
; GCN-IR-NEXT: s_add_u32 s10, s10, 1 ; GCN-IR-NEXT: s_add_u32 s10, s10, 1
; GCN-IR-NEXT: s_addc_u32 s11, s11, 0 ; GCN-IR-NEXT: s_addc_u32 s11, s11, 0
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
; GCN-IR-NEXT: s_mov_b64 s[14:15], s[8:9] ; GCN-IR-NEXT: s_mov_b64 s[14:15], s[8:9]
; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_cbranch_vccz BB9_3 ; GCN-IR-NEXT: s_cbranch_vccz .LBB9_3
; GCN-IR-NEXT: BB9_4: ; %Flow3 ; GCN-IR-NEXT: .LBB9_4: ; %Flow3
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[12:13], 1 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[12:13], 1
; GCN-IR-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11] ; GCN-IR-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v0, s8 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s8
; GCN-IR-NEXT: v_mov_b32_e32 v1, s9 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s9
; GCN-IR-NEXT: s_branch BB9_6 ; GCN-IR-NEXT: s_branch .LBB9_6
; GCN-IR-NEXT: BB9_5: ; GCN-IR-NEXT: .LBB9_5:
; GCN-IR-NEXT: v_mov_b32_e32 v0, s3 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s3
; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[16:17] ; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[16:17]
; GCN-IR-NEXT: v_mov_b32_e32 v0, s2 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s2
; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[16:17] ; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[16:17]
; GCN-IR-NEXT: BB9_6: ; %udiv-end ; GCN-IR-NEXT: .LBB9_6: ; %udiv-end
; GCN-IR-NEXT: v_mul_lo_u32 v1, s6, v1 ; GCN-IR-NEXT: v_mul_lo_u32 v1, s6, v1
; GCN-IR-NEXT: v_mul_hi_u32 v2, s6, v0 ; GCN-IR-NEXT: v_mul_hi_u32 v2, s6, v0
; GCN-IR-NEXT: v_mul_lo_u32 v3, s7, v0 ; GCN-IR-NEXT: v_mul_lo_u32 v3, s7, v0
; GCN-IR-NEXT: v_mul_lo_u32 v0, s6, v0 ; GCN-IR-NEXT: v_mul_lo_u32 v0, s6, v0
; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v3 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GCN-IR-NEXT: v_mov_b32_e32 v2, s3 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s3
▲ Show 20 Lines • Show All 144 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[4:5], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[4:5], 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[12:13], s[8:9], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[12:13], s[8:9], 63
; GCN-IR-NEXT: s_mov_b64 s[2:3], 0 ; GCN-IR-NEXT: s_mov_b64 s[2:3], 0
; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13]
; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[12:13], s[8:9], 63 ; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[12:13], s[8:9], 63
; GCN-IR-NEXT: s_xor_b64 s[14:15], s[10:11], -1 ; GCN-IR-NEXT: s_xor_b64 s[14:15], s[10:11], -1
; GCN-IR-NEXT: s_and_b64 s[12:13], s[14:15], s[12:13] ; GCN-IR-NEXT: s_and_b64 s[12:13], s[14:15], s[12:13]
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[12:13] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[12:13]
; GCN-IR-NEXT: s_cbranch_vccz BB10_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB10_5
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s10, s8, 1 ; GCN-IR-NEXT: s_add_u32 s10, s8, 1
; GCN-IR-NEXT: v_mov_b32_e32 v0, s8 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s8
; GCN-IR-NEXT: s_addc_u32 s11, s9, 0 ; GCN-IR-NEXT: s_addc_u32 s11, s9, 0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s9 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s9
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
; GCN-IR-NEXT: s_sub_i32 s7, 63, s8 ; GCN-IR-NEXT: s_sub_i32 s7, 63, s8
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_lshl_b64 s[8:9], 24, s7 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], 24, s7
; GCN-IR-NEXT: s_cbranch_vccz BB10_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB10_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[12:13], 24, s10 ; GCN-IR-NEXT: s_lshr_b64 s[12:13], 24, s10
; GCN-IR-NEXT: s_add_u32 s14, s4, -1 ; GCN-IR-NEXT: s_add_u32 s14, s4, -1
; GCN-IR-NEXT: s_addc_u32 s15, s5, -1 ; GCN-IR-NEXT: s_addc_u32 s15, s5, -1
; GCN-IR-NEXT: s_sub_u32 s6, 58, s6 ; GCN-IR-NEXT: s_sub_u32 s6, 58, s6
; GCN-IR-NEXT: s_subb_u32 s7, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s7, 0, 0
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: s_mov_b32 s3, 0 ; GCN-IR-NEXT: s_mov_b32 s3, 0
; GCN-IR-NEXT: BB10_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB10_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1 ; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1
; GCN-IR-NEXT: s_lshr_b32 s2, s9, 31 ; GCN-IR-NEXT: s_lshr_b32 s2, s9, 31
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1
; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[2:3] ; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[2:3]
; GCN-IR-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9] ; GCN-IR-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9]
; GCN-IR-NEXT: s_sub_u32 s2, s14, s12 ; GCN-IR-NEXT: s_sub_u32 s2, s14, s12
; GCN-IR-NEXT: s_subb_u32 s2, s15, s13 ; GCN-IR-NEXT: s_subb_u32 s2, s15, s13
; GCN-IR-NEXT: s_ashr_i32 s10, s2, 31 ; GCN-IR-NEXT: s_ashr_i32 s10, s2, 31
; GCN-IR-NEXT: s_mov_b32 s11, s10 ; GCN-IR-NEXT: s_mov_b32 s11, s10
; GCN-IR-NEXT: s_and_b32 s2, s10, 1 ; GCN-IR-NEXT: s_and_b32 s2, s10, 1
; GCN-IR-NEXT: s_and_b64 s[16:17], s[10:11], s[4:5] ; GCN-IR-NEXT: s_and_b64 s[16:17], s[10:11], s[4:5]
; GCN-IR-NEXT: s_sub_u32 s12, s12, s16 ; GCN-IR-NEXT: s_sub_u32 s12, s12, s16
; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
; GCN-IR-NEXT: s_subb_u32 s13, s13, s17 ; GCN-IR-NEXT: s_subb_u32 s13, s13, s17
; GCN-IR-NEXT: v_mov_b32_e32 v1, s7 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s7
; GCN-IR-NEXT: s_add_u32 s6, s6, 1 ; GCN-IR-NEXT: s_add_u32 s6, s6, 1
; GCN-IR-NEXT: s_addc_u32 s7, s7, 0 ; GCN-IR-NEXT: s_addc_u32 s7, s7, 0
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[6:7], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[6:7], v[0:1]
; GCN-IR-NEXT: s_mov_b64 s[10:11], s[2:3] ; GCN-IR-NEXT: s_mov_b64 s[10:11], s[2:3]
; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_cbranch_vccz BB10_3 ; GCN-IR-NEXT: s_cbranch_vccz .LBB10_3
; GCN-IR-NEXT: BB10_4: ; %Flow5 ; GCN-IR-NEXT: .LBB10_4: ; %Flow5
; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[8:9], 1 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[8:9], 1
; GCN-IR-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7]
; GCN-IR-NEXT: v_mov_b32_e32 v0, s2 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s2
; GCN-IR-NEXT: v_mov_b32_e32 v1, s3 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s3
; GCN-IR-NEXT: s_branch BB10_6 ; GCN-IR-NEXT: s_branch .LBB10_6
; GCN-IR-NEXT: BB10_5: ; GCN-IR-NEXT: .LBB10_5:
; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
; GCN-IR-NEXT: v_cndmask_b32_e64 v0, 24, 0, s[10:11] ; GCN-IR-NEXT: v_cndmask_b32_e64 v0, 24, 0, s[10:11]
; GCN-IR-NEXT: BB10_6: ; %udiv-end ; GCN-IR-NEXT: .LBB10_6: ; %udiv-end
; GCN-IR-NEXT: v_mul_lo_u32 v1, s4, v1 ; GCN-IR-NEXT: v_mul_lo_u32 v1, s4, v1
; GCN-IR-NEXT: v_mul_hi_u32 v2, s4, v0 ; GCN-IR-NEXT: v_mul_hi_u32 v2, s4, v0
; GCN-IR-NEXT: v_mul_lo_u32 v3, s5, v0 ; GCN-IR-NEXT: v_mul_lo_u32 v3, s5, v0
; GCN-IR-NEXT: v_mul_lo_u32 v0, s4, v0 ; GCN-IR-NEXT: v_mul_lo_u32 v0, s4, v0
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v3 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 24, v0 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 24, v0
▲ Show 20 Lines • Show All 130 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[3:4] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[3:4]
; GCN-IR-NEXT: v_cndmask_b32_e64 v2, 24, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v2, 24, 0, s[4:5]
; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1
; GCN-IR-NEXT: v_mov_b32_e32 v5, v7 ; GCN-IR-NEXT: v_mov_b32_e32 v5, v7
; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB11_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB11_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v3 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v3
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v4, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v4, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v3 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v3
; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[8:9], v[3:4] ; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[8:9], v[3:4]
; GCN-IR-NEXT: v_lshl_b64 v[2:3], 24, v2 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], 24, v2
; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB11_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB11_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc
; GCN-IR-NEXT: v_lshr_b64 v[8:9], 24, v8 ; GCN-IR-NEXT: v_lshr_b64 v[8:9], 24, v8
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 58, v6 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 58, v6
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_subb_u32_e32 v7, vcc, 0, v7, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v7, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: BB11_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB11_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 ; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4 ; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v12, v8 ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v12, v8
; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, v13, v9, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, v13, v9, vcc
; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2 ; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2
; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4
; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10 ; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10
; GCN-IR-NEXT: v_and_b32_e32 v14, v10, v1 ; GCN-IR-NEXT: v_and_b32_e32 v14, v10, v1
; GCN-IR-NEXT: v_and_b32_e32 v15, v10, v0 ; GCN-IR-NEXT: v_and_b32_e32 v15, v10, v0
; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v6 ; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v6
; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3 ; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3
; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v7, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[6:7] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[6:7]
; GCN-IR-NEXT: v_mov_b32_e32 v6, v10 ; GCN-IR-NEXT: v_mov_b32_e32 v6, v10
; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v8, v15 ; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v8, v15
; GCN-IR-NEXT: v_mov_b32_e32 v7, v11 ; GCN-IR-NEXT: v_mov_b32_e32 v7, v11
; GCN-IR-NEXT: v_mov_b32_e32 v11, v5 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v5
; GCN-IR-NEXT: v_subb_u32_e64 v9, s[4:5], v9, v14, s[4:5] ; GCN-IR-NEXT: v_subb_u32_e64 v9, s[4:5], v9, v14, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v10, v4 ; GCN-IR-NEXT: v_mov_b32_e32 v10, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execnz BB11_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB11_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: BB11_5: ; %Flow3 ; GCN-IR-NEXT: .LBB11_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v3 ; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v3
; GCN-IR-NEXT: v_or_b32_e32 v2, v4, v2 ; GCN-IR-NEXT: v_or_b32_e32 v2, v4, v2
; GCN-IR-NEXT: BB11_6: ; %Flow4 ; GCN-IR-NEXT: .LBB11_6: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_mul_lo_u32 v3, v0, v5 ; GCN-IR-NEXT: v_mul_lo_u32 v3, v0, v5
; GCN-IR-NEXT: v_mul_hi_u32 v4, v0, v2 ; GCN-IR-NEXT: v_mul_hi_u32 v4, v0, v2
; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, v2 ; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, v2
; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, v2 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, v2
; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v3, v1 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v3, v1
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 24, v0 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 24, v0
▲ Show 20 Lines • Show All 130 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[2:3] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[2:3]
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[4:5]
; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1
; GCN-IR-NEXT: v_mov_b32_e32 v5, v7 ; GCN-IR-NEXT: v_mov_b32_e32 v5, v7
; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB12_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB12_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v2 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v2
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v3, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v3, vcc
; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[8:9], v[2:3] ; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[8:9], v[2:3]
; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2
; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[8:9], v2 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[8:9], v2
; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB12_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB12_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0
; GCN-IR-NEXT: s_mov_b64 s[4:5], 0x8000 ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0x8000
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc
; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[4:5], v8 ; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[4:5], v8
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 47, v6 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 47, v6
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_subb_u32_e32 v7, vcc, 0, v7, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v7, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: BB12_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB12_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 ; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4 ; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v12, v8 ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v12, v8
; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, v13, v9, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, v13, v9, vcc
; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2 ; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2
; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4
; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10 ; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10
; GCN-IR-NEXT: v_and_b32_e32 v14, v10, v1 ; GCN-IR-NEXT: v_and_b32_e32 v14, v10, v1
; GCN-IR-NEXT: v_and_b32_e32 v15, v10, v0 ; GCN-IR-NEXT: v_and_b32_e32 v15, v10, v0
; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v6 ; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v6
; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3 ; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3
; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v7, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[6:7] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[6:7]
; GCN-IR-NEXT: v_mov_b32_e32 v6, v10 ; GCN-IR-NEXT: v_mov_b32_e32 v6, v10
; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v8, v15 ; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v8, v15
; GCN-IR-NEXT: v_mov_b32_e32 v7, v11 ; GCN-IR-NEXT: v_mov_b32_e32 v7, v11
; GCN-IR-NEXT: v_mov_b32_e32 v11, v5 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v5
; GCN-IR-NEXT: v_subb_u32_e64 v9, s[4:5], v9, v14, s[4:5] ; GCN-IR-NEXT: v_subb_u32_e64 v9, s[4:5], v9, v14, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v10, v4 ; GCN-IR-NEXT: v_mov_b32_e32 v10, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execnz BB12_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB12_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: BB12_5: ; %Flow3 ; GCN-IR-NEXT: .LBB12_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v3 ; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v3
; GCN-IR-NEXT: v_or_b32_e32 v4, v4, v2 ; GCN-IR-NEXT: v_or_b32_e32 v4, v4, v2
; GCN-IR-NEXT: BB12_6: ; %Flow4 ; GCN-IR-NEXT: .LBB12_6: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_mul_lo_u32 v2, v0, v5 ; GCN-IR-NEXT: v_mul_lo_u32 v2, v0, v5
; GCN-IR-NEXT: v_mul_hi_u32 v3, v0, v4 ; GCN-IR-NEXT: v_mul_hi_u32 v3, v0, v4
; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, v4 ; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, v4
; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, v4 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, v4
; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 0x8000, v0 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 0x8000, v0
Show All 35 Lines
; GCN-IR-NEXT: v_mov_b32_e32 v3, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v3, v2
; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5]
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
; GCN-IR-NEXT: v_cndmask_b32_e64 v7, v1, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v7, v1, 0, s[4:5]
; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v0, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v0, 0, s[4:5]
; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB13_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB13_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v4 ; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v4
; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v5, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[9:10], v[4:5] ; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[9:10], v[4:5]
; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v4 ; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v4
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4
; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB13_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB13_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_lshr_b64 v[10:11], v[0:1], v9 ; GCN-IR-NEXT: v_lshr_b64 v[10:11], v[0:1], v9
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 0xffffffcf, v8 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 0xffffffcf, v8
; GCN-IR-NEXT: v_mov_b32_e32 v12, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v12, 0
; GCN-IR-NEXT: v_addc_u32_e64 v9, s[4:5], 0, -1, vcc ; GCN-IR-NEXT: v_addc_u32_e64 v9, s[4:5], 0, -1, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v13, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v13, 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff ; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff
; GCN-IR-NEXT: BB13_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB13_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1 ; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5
; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6 ; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, s12, v10 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, s12, v10
; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, 0, v11, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, 0, v11, vcc
; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4 ; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4
; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v6 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v6
; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v12 ; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v12
; GCN-IR-NEXT: v_and_b32_e32 v14, 0x8000, v12 ; GCN-IR-NEXT: v_and_b32_e32 v14, 0x8000, v12
; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v8 ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v8
; GCN-IR-NEXT: v_or_b32_e32 v5, v13, v5 ; GCN-IR-NEXT: v_or_b32_e32 v5, v13, v5
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v9, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v9, vcc
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9]
; GCN-IR-NEXT: v_mov_b32_e32 v8, v12 ; GCN-IR-NEXT: v_mov_b32_e32 v8, v12
; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v10, v14 ; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v10, v14
; GCN-IR-NEXT: v_mov_b32_e32 v9, v13 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v13
; GCN-IR-NEXT: v_mov_b32_e32 v13, v7 ; GCN-IR-NEXT: v_mov_b32_e32 v13, v7
; GCN-IR-NEXT: v_subbrev_u32_e64 v11, s[4:5], 0, v11, s[4:5] ; GCN-IR-NEXT: v_subbrev_u32_e64 v11, s[4:5], 0, v11, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v12, v6 ; GCN-IR-NEXT: v_mov_b32_e32 v12, v6
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execnz BB13_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB13_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: BB13_5: ; %Flow3 ; GCN-IR-NEXT: .LBB13_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v5 ; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v5
; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v4 ; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v4
; GCN-IR-NEXT: BB13_6: ; %Flow4 ; GCN-IR-NEXT: .LBB13_6: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[6:7], 15 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[6:7], 15
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v4 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc
; GCN-IR-NEXT: v_xor_b32_e32 v0, v0, v2 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v0, v2
; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v3 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v3
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
▲ Show 20 Lines • Show All 264 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll

Show All 25 Lines
; MUBUF-NEXT: s_addc_u32 s5, s5, svm_eval_nodes@rel32@hi+12 ; MUBUF-NEXT: s_addc_u32 s5, s5, svm_eval_nodes@rel32@hi+12
; MUBUF-NEXT: s_waitcnt lgkmcnt(0) ; MUBUF-NEXT: s_waitcnt lgkmcnt(0)
; MUBUF-NEXT: v_mov_b32_e32 v0, s0 ; MUBUF-NEXT: v_mov_b32_e32 v0, s0
; MUBUF-NEXT: s_mov_b64 s[0:1], s[36:37] ; MUBUF-NEXT: s_mov_b64 s[0:1], s[36:37]
; MUBUF-NEXT: s_mov_b64 s[2:3], s[38:39] ; MUBUF-NEXT: s_mov_b64 s[2:3], s[38:39]
; MUBUF-NEXT: s_swappc_b64 s[30:31], s[4:5] ; MUBUF-NEXT: s_swappc_b64 s[30:31], s[4:5]
; MUBUF-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 ; MUBUF-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; MUBUF-NEXT: s_and_saveexec_b32 s0, vcc_lo ; MUBUF-NEXT: s_and_saveexec_b32 s0, vcc_lo
; MUBUF-NEXT: s_cbranch_execz BB0_2 ; MUBUF-NEXT: s_cbranch_execz .LBB0_2
; MUBUF-NEXT: ; %bb.1: ; %if.then4.i ; MUBUF-NEXT: ; %bb.1: ; %if.then4.i
; MUBUF-NEXT: s_clause 0x1 ; MUBUF-NEXT: s_clause 0x1
; MUBUF-NEXT: buffer_load_dword v0, v40, s[36:39], 0 offen ; MUBUF-NEXT: buffer_load_dword v0, v40, s[36:39], 0 offen
; MUBUF-NEXT: buffer_load_dword v1, v40, s[36:39], 0 offen offset:4 ; MUBUF-NEXT: buffer_load_dword v1, v40, s[36:39], 0 offen offset:4
; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: v_add_nc_u32_e32 v0, v1, v0 ; MUBUF-NEXT: v_add_nc_u32_e32 v0, v1, v0
; MUBUF-NEXT: v_mul_lo_u32 v0, 0x41c64e6d, v0 ; MUBUF-NEXT: v_mul_lo_u32 v0, 0x41c64e6d, v0
; MUBUF-NEXT: v_add_nc_u32_e32 v0, 0x3039, v0 ; MUBUF-NEXT: v_add_nc_u32_e32 v0, 0x3039, v0
; MUBUF-NEXT: buffer_store_dword v0, v0, s[36:39], 0 offen ; MUBUF-NEXT: buffer_store_dword v0, v0, s[36:39], 0 offen
; MUBUF-NEXT: BB0_2: ; %shader_eval_surface.exit ; MUBUF-NEXT: .LBB0_2: ; %shader_eval_surface.exit
; MUBUF-NEXT: s_endpgm ; MUBUF-NEXT: s_endpgm
; ;
; FLATSCR-LABEL: kernel_background_evaluate: ; FLATSCR-LABEL: kernel_background_evaluate:
; FLATSCR: ; %bb.0: ; %entry ; FLATSCR: ; %bb.0: ; %entry
; FLATSCR-NEXT: s_add_u32 s8, s8, s13 ; FLATSCR-NEXT: s_add_u32 s8, s8, s13
; FLATSCR-NEXT: s_movk_i32 s32, 0x6000 ; FLATSCR-NEXT: s_movk_i32 s32, 0x6000
; FLATSCR-NEXT: s_addc_u32 s9, s9, 0 ; FLATSCR-NEXT: s_addc_u32 s9, s9, 0
; FLATSCR-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s8 ; FLATSCR-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s8
; FLATSCR-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s9 ; FLATSCR-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s9
; FLATSCR-NEXT: s_load_dword s2, s[4:5], 0x24 ; FLATSCR-NEXT: s_load_dword s2, s[4:5], 0x24
; FLATSCR-NEXT: v_mov_b32_e32 v1, 0x2000 ; FLATSCR-NEXT: v_mov_b32_e32 v1, 0x2000
; FLATSCR-NEXT: v_mov_b32_e32 v2, 0x4000 ; FLATSCR-NEXT: v_mov_b32_e32 v2, 0x4000
; FLATSCR-NEXT: v_mov_b32_e32 v3, 0 ; FLATSCR-NEXT: v_mov_b32_e32 v3, 0
; FLATSCR-NEXT: v_mov_b32_e32 v4, 0x400000 ; FLATSCR-NEXT: v_mov_b32_e32 v4, 0x400000
; FLATSCR-NEXT: s_getpc_b64 s[0:1] ; FLATSCR-NEXT: s_getpc_b64 s[0:1]
; FLATSCR-NEXT: s_add_u32 s0, s0, svm_eval_nodes@rel32@lo+4 ; FLATSCR-NEXT: s_add_u32 s0, s0, svm_eval_nodes@rel32@lo+4
; FLATSCR-NEXT: s_addc_u32 s1, s1, svm_eval_nodes@rel32@hi+12 ; FLATSCR-NEXT: s_addc_u32 s1, s1, svm_eval_nodes@rel32@hi+12
; FLATSCR-NEXT: s_waitcnt lgkmcnt(0) ; FLATSCR-NEXT: s_waitcnt lgkmcnt(0)
; FLATSCR-NEXT: v_mov_b32_e32 v0, s2 ; FLATSCR-NEXT: v_mov_b32_e32 v0, s2
; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[0:1] ; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[0:1]
; FLATSCR-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 ; FLATSCR-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; FLATSCR-NEXT: s_and_saveexec_b32 s0, vcc_lo ; FLATSCR-NEXT: s_and_saveexec_b32 s0, vcc_lo
; FLATSCR-NEXT: s_cbranch_execz BB0_2 ; FLATSCR-NEXT: s_cbranch_execz .LBB0_2
; FLATSCR-NEXT: ; %bb.1: ; %if.then4.i ; FLATSCR-NEXT: ; %bb.1: ; %if.then4.i
; FLATSCR-NEXT: s_movk_i32 vcc_lo, 0x4000 ; FLATSCR-NEXT: s_movk_i32 vcc_lo, 0x4000
; FLATSCR-NEXT: scratch_load_dwordx2 v[0:1], off, vcc_lo offset:4 ; FLATSCR-NEXT: scratch_load_dwordx2 v[0:1], off, vcc_lo offset:4
; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: v_add_nc_u32_e32 v0, v1, v0 ; FLATSCR-NEXT: v_add_nc_u32_e32 v0, v1, v0
; FLATSCR-NEXT: v_mul_lo_u32 v0, 0x41c64e6d, v0 ; FLATSCR-NEXT: v_mul_lo_u32 v0, 0x41c64e6d, v0
; FLATSCR-NEXT: v_add_nc_u32_e32 v0, 0x3039, v0 ; FLATSCR-NEXT: v_add_nc_u32_e32 v0, 0x3039, v0
; FLATSCR-NEXT: scratch_store_dword off, v0, s0 ; FLATSCR-NEXT: scratch_store_dword off, v0, s0
; FLATSCR-NEXT: BB0_2: ; %shader_eval_surface.exit ; FLATSCR-NEXT: .LBB0_2: ; %shader_eval_surface.exit
; FLATSCR-NEXT: s_endpgm ; FLATSCR-NEXT: s_endpgm
entry: entry:
%sd = alloca < 1339 x i32>, align 8192, addrspace(5) %sd = alloca < 1339 x i32>, align 8192, addrspace(5)
%state = alloca <4 x i32>, align 16, addrspace(5) %state = alloca <4 x i32>, align 16, addrspace(5)
%rslt = call i32 @svm_eval_nodes(float addrspace(5)* %kg, <1339 x i32> addrspace(5)* %sd, <4 x i32> addrspace(5)* %state, i32 0, i32 4194304) %rslt = call i32 @svm_eval_nodes(float addrspace(5)* %kg, <1339 x i32> addrspace(5)* %sd, <4 x i32> addrspace(5)* %state, i32 0, i32 4194304)
%cmp = icmp eq i32 %rslt, 0 %cmp = icmp eq i32 %rslt, 0
br i1 %cmp, label %shader_eval_surface.exit, label %if.then4.i br i1 %cmp, label %shader_eval_surface.exit, label %if.then4.i
Show All 17 Lines

llvm/test/CodeGen/AMDGPU/subvector-test.mir

# RUN: llc -march=amdgcn -mcpu=gfx1010 -start-before=greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s # RUN: llc -march=amdgcn -mcpu=gfx1010 -start-before=greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
... ...
# GCN-LABEL: {{^}}"subvector-basic-bb" # GCN-LABEL: {{^}}"subvector-basic-bb"
# GCN: s_subvector_loop_begin [[RS:s[0-9]]], BB0_2 # GCN: s_subvector_loop_begin [[RS:s[0-9]]], .LBB0_2
# GCN: s_subvector_loop_end [[RS]], BB0_1 # GCN: s_subvector_loop_end [[RS]], .LBB0_1
name: subvector-basic-bb name: subvector-basic-bb
tracksRegLiveness: true tracksRegLiveness: true
machineFunctionInfo: machineFunctionInfo:
scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3 scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
frameOffsetReg: $sgpr5 frameOffsetReg: $sgpr5
stackPtrOffsetReg: $sgpr32 stackPtrOffsetReg: $sgpr32
body: | body: |
bb.0: bb.0:
Show All 23 Lines

llvm/test/CodeGen/AMDGPU/trap-abis.ll

Show First 20 Lines • Show All 358 Lines • ▼ Show 20 Lines
; NOHSA-TRAP-GFX900-V2: ; %bb.0: ; %entry ; NOHSA-TRAP-GFX900-V2: ; %bb.0: ; %entry
; NOHSA-TRAP-GFX900-V2-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24 ; NOHSA-TRAP-GFX900-V2-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
; NOHSA-TRAP-GFX900-V2-NEXT: v_mov_b32_e32 v0, 0 ; NOHSA-TRAP-GFX900-V2-NEXT: v_mov_b32_e32 v0, 0
; NOHSA-TRAP-GFX900-V2-NEXT: s_waitcnt lgkmcnt(0) ; NOHSA-TRAP-GFX900-V2-NEXT: s_waitcnt lgkmcnt(0)
; NOHSA-TRAP-GFX900-V2-NEXT: global_load_dword v1, v0, s[0:1] glc ; NOHSA-TRAP-GFX900-V2-NEXT: global_load_dword v1, v0, s[0:1] glc
; NOHSA-TRAP-GFX900-V2-NEXT: s_waitcnt vmcnt(0) ; NOHSA-TRAP-GFX900-V2-NEXT: s_waitcnt vmcnt(0)
; NOHSA-TRAP-GFX900-V2-NEXT: v_cmp_eq_u32_e32 vcc, -1, v1 ; NOHSA-TRAP-GFX900-V2-NEXT: v_cmp_eq_u32_e32 vcc, -1, v1
; NOHSA-TRAP-GFX900-V2-NEXT: s_and_b64 vcc, exec, vcc ; NOHSA-TRAP-GFX900-V2-NEXT: s_and_b64 vcc, exec, vcc
; NOHSA-TRAP-GFX900-V2-NEXT: s_cbranch_vccz BB1_2 ; NOHSA-TRAP-GFX900-V2-NEXT: s_cbranch_vccz .LBB1_2
; NOHSA-TRAP-GFX900-V2-NEXT: ; %bb.1: ; %ret ; NOHSA-TRAP-GFX900-V2-NEXT: ; %bb.1: ; %ret
; NOHSA-TRAP-GFX900-V2-NEXT: v_mov_b32_e32 v1, 3 ; NOHSA-TRAP-GFX900-V2-NEXT: v_mov_b32_e32 v1, 3
; NOHSA-TRAP-GFX900-V2-NEXT: global_store_dword v0, v1, s[0:1] ; NOHSA-TRAP-GFX900-V2-NEXT: global_store_dword v0, v1, s[0:1]
; NOHSA-TRAP-GFX900-V2-NEXT: s_waitcnt vmcnt(0) ; NOHSA-TRAP-GFX900-V2-NEXT: s_waitcnt vmcnt(0)
; NOHSA-TRAP-GFX900-V2-NEXT: s_endpgm ; NOHSA-TRAP-GFX900-V2-NEXT: s_endpgm
; NOHSA-TRAP-GFX900-V2-NEXT: BB1_2: ; %trap ; NOHSA-TRAP-GFX900-V2-NEXT: .LBB1_2: ; %trap
; NOHSA-TRAP-GFX900-V2-NEXT: s_endpgm ; NOHSA-TRAP-GFX900-V2-NEXT: s_endpgm
; ;
; NOHSA-TRAP-GFX900-V3-LABEL: non_entry_trap: ; NOHSA-TRAP-GFX900-V3-LABEL: non_entry_trap:
; NOHSA-TRAP-GFX900-V3: ; %bb.0: ; %entry ; NOHSA-TRAP-GFX900-V3: ; %bb.0: ; %entry
; NOHSA-TRAP-GFX900-V3-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24 ; NOHSA-TRAP-GFX900-V3-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
; NOHSA-TRAP-GFX900-V3-NEXT: v_mov_b32_e32 v0, 0 ; NOHSA-TRAP-GFX900-V3-NEXT: v_mov_b32_e32 v0, 0
; NOHSA-TRAP-GFX900-V3-NEXT: s_waitcnt lgkmcnt(0) ; NOHSA-TRAP-GFX900-V3-NEXT: s_waitcnt lgkmcnt(0)
; NOHSA-TRAP-GFX900-V3-NEXT: global_load_dword v1, v0, s[0:1] glc ; NOHSA-TRAP-GFX900-V3-NEXT: global_load_dword v1, v0, s[0:1] glc
; NOHSA-TRAP-GFX900-V3-NEXT: s_waitcnt vmcnt(0) ; NOHSA-TRAP-GFX900-V3-NEXT: s_waitcnt vmcnt(0)
; NOHSA-TRAP-GFX900-V3-NEXT: v_cmp_eq_u32_e32 vcc, -1, v1 ; NOHSA-TRAP-GFX900-V3-NEXT: v_cmp_eq_u32_e32 vcc, -1, v1
; NOHSA-TRAP-GFX900-V3-NEXT: s_and_b64 vcc, exec, vcc ; NOHSA-TRAP-GFX900-V3-NEXT: s_and_b64 vcc, exec, vcc
; NOHSA-TRAP-GFX900-V3-NEXT: s_cbranch_vccz BB1_2 ; NOHSA-TRAP-GFX900-V3-NEXT: s_cbranch_vccz .LBB1_2
; NOHSA-TRAP-GFX900-V3-NEXT: ; %bb.1: ; %ret ; NOHSA-TRAP-GFX900-V3-NEXT: ; %bb.1: ; %ret
; NOHSA-TRAP-GFX900-V3-NEXT: v_mov_b32_e32 v1, 3 ; NOHSA-TRAP-GFX900-V3-NEXT: v_mov_b32_e32 v1, 3
; NOHSA-TRAP-GFX900-V3-NEXT: global_store_dword v0, v1, s[0:1] ; NOHSA-TRAP-GFX900-V3-NEXT: global_store_dword v0, v1, s[0:1]
; NOHSA-TRAP-GFX900-V3-NEXT: s_waitcnt vmcnt(0) ; NOHSA-TRAP-GFX900-V3-NEXT: s_waitcnt vmcnt(0)
; NOHSA-TRAP-GFX900-V3-NEXT: s_endpgm ; NOHSA-TRAP-GFX900-V3-NEXT: s_endpgm
; NOHSA-TRAP-GFX900-V3-NEXT: BB1_2: ; %trap ; NOHSA-TRAP-GFX900-V3-NEXT: .LBB1_2: ; %trap
; NOHSA-TRAP-GFX900-V3-NEXT: s_endpgm ; NOHSA-TRAP-GFX900-V3-NEXT: s_endpgm
; ;
; NOHSA-TRAP-GFX900-V4-LABEL: non_entry_trap: ; NOHSA-TRAP-GFX900-V4-LABEL: non_entry_trap:
; NOHSA-TRAP-GFX900-V4: ; %bb.0: ; %entry ; NOHSA-TRAP-GFX900-V4: ; %bb.0: ; %entry
; NOHSA-TRAP-GFX900-V4-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24 ; NOHSA-TRAP-GFX900-V4-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
; NOHSA-TRAP-GFX900-V4-NEXT: v_mov_b32_e32 v0, 0 ; NOHSA-TRAP-GFX900-V4-NEXT: v_mov_b32_e32 v0, 0
; NOHSA-TRAP-GFX900-V4-NEXT: s_waitcnt lgkmcnt(0) ; NOHSA-TRAP-GFX900-V4-NEXT: s_waitcnt lgkmcnt(0)
; NOHSA-TRAP-GFX900-V4-NEXT: global_load_dword v1, v0, s[0:1] glc ; NOHSA-TRAP-GFX900-V4-NEXT: global_load_dword v1, v0, s[0:1] glc
; NOHSA-TRAP-GFX900-V4-NEXT: s_waitcnt vmcnt(0) ; NOHSA-TRAP-GFX900-V4-NEXT: s_waitcnt vmcnt(0)
; NOHSA-TRAP-GFX900-V4-NEXT: v_cmp_eq_u32_e32 vcc, -1, v1 ; NOHSA-TRAP-GFX900-V4-NEXT: v_cmp_eq_u32_e32 vcc, -1, v1
; NOHSA-TRAP-GFX900-V4-NEXT: s_and_b64 vcc, exec, vcc ; NOHSA-TRAP-GFX900-V4-NEXT: s_and_b64 vcc, exec, vcc
; NOHSA-TRAP-GFX900-V4-NEXT: s_cbranch_vccz BB1_2 ; NOHSA-TRAP-GFX900-V4-NEXT: s_cbranch_vccz .LBB1_2
; NOHSA-TRAP-GFX900-V4-NEXT: ; %bb.1: ; %ret ; NOHSA-TRAP-GFX900-V4-NEXT: ; %bb.1: ; %ret
; NOHSA-TRAP-GFX900-V4-NEXT: v_mov_b32_e32 v1, 3 ; NOHSA-TRAP-GFX900-V4-NEXT: v_mov_b32_e32 v1, 3
; NOHSA-TRAP-GFX900-V4-NEXT: global_store_dword v0, v1, s[0:1] ; NOHSA-TRAP-GFX900-V4-NEXT: global_store_dword v0, v1, s[0:1]
; NOHSA-TRAP-GFX900-V4-NEXT: s_waitcnt vmcnt(0) ; NOHSA-TRAP-GFX900-V4-NEXT: s_waitcnt vmcnt(0)
; NOHSA-TRAP-GFX900-V4-NEXT: s_endpgm ; NOHSA-TRAP-GFX900-V4-NEXT: s_endpgm
; NOHSA-TRAP-GFX900-V4-NEXT: BB1_2: ; %trap ; NOHSA-TRAP-GFX900-V4-NEXT: .LBB1_2: ; %trap
; NOHSA-TRAP-GFX900-V4-NEXT: s_endpgm ; NOHSA-TRAP-GFX900-V4-NEXT: s_endpgm
; ;
; HSA-TRAP-GFX803-V2-LABEL: non_entry_trap: ; HSA-TRAP-GFX803-V2-LABEL: non_entry_trap:
; HSA-TRAP-GFX803-V2: .amd_kernel_code_t ; HSA-TRAP-GFX803-V2: .amd_kernel_code_t
; HSA-TRAP-GFX803-V2-NEXT: amd_code_version_major = 1 ; HSA-TRAP-GFX803-V2-NEXT: amd_code_version_major = 1
; HSA-TRAP-GFX803-V2-NEXT: amd_code_version_minor = 2 ; HSA-TRAP-GFX803-V2-NEXT: amd_code_version_minor = 2
; HSA-TRAP-GFX803-V2-NEXT: amd_machine_kind = 1 ; HSA-TRAP-GFX803-V2-NEXT: amd_machine_kind = 1
; HSA-TRAP-GFX803-V2-NEXT: amd_machine_version_major = 8 ; HSA-TRAP-GFX803-V2-NEXT: amd_machine_version_major = 8
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; HSA-TRAP-GFX803-V2-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 ; HSA-TRAP-GFX803-V2-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
; HSA-TRAP-GFX803-V2-NEXT: s_waitcnt lgkmcnt(0) ; HSA-TRAP-GFX803-V2-NEXT: s_waitcnt lgkmcnt(0)
; HSA-TRAP-GFX803-V2-NEXT: v_mov_b32_e32 v0, s0 ; HSA-TRAP-GFX803-V2-NEXT: v_mov_b32_e32 v0, s0
; HSA-TRAP-GFX803-V2-NEXT: v_mov_b32_e32 v1, s1 ; HSA-TRAP-GFX803-V2-NEXT: v_mov_b32_e32 v1, s1
; HSA-TRAP-GFX803-V2-NEXT: flat_load_dword v0, v[0:1] glc ; HSA-TRAP-GFX803-V2-NEXT: flat_load_dword v0, v[0:1] glc
; HSA-TRAP-GFX803-V2-NEXT: s_waitcnt vmcnt(0) ; HSA-TRAP-GFX803-V2-NEXT: s_waitcnt vmcnt(0)
; HSA-TRAP-GFX803-V2-NEXT: v_cmp_eq_u32_e32 vcc, -1, v0 ; HSA-TRAP-GFX803-V2-NEXT: v_cmp_eq_u32_e32 vcc, -1, v0
; HSA-TRAP-GFX803-V2-NEXT: s_and_b64 vcc, exec, vcc ; HSA-TRAP-GFX803-V2-NEXT: s_and_b64 vcc, exec, vcc
; HSA-TRAP-GFX803-V2-NEXT: s_cbranch_vccz BB1_2 ; HSA-TRAP-GFX803-V2-NEXT: s_cbranch_vccz .LBB1_2
; HSA-TRAP-GFX803-V2-NEXT: ; %bb.1: ; %ret ; HSA-TRAP-GFX803-V2-NEXT: ; %bb.1: ; %ret
; HSA-TRAP-GFX803-V2-NEXT: v_mov_b32_e32 v0, s0 ; HSA-TRAP-GFX803-V2-NEXT: v_mov_b32_e32 v0, s0
; HSA-TRAP-GFX803-V2-NEXT: v_mov_b32_e32 v2, 3 ; HSA-TRAP-GFX803-V2-NEXT: v_mov_b32_e32 v2, 3
; HSA-TRAP-GFX803-V2-NEXT: v_mov_b32_e32 v1, s1 ; HSA-TRAP-GFX803-V2-NEXT: v_mov_b32_e32 v1, s1
; HSA-TRAP-GFX803-V2-NEXT: flat_store_dword v[0:1], v2 ; HSA-TRAP-GFX803-V2-NEXT: flat_store_dword v[0:1], v2
; HSA-TRAP-GFX803-V2-NEXT: s_waitcnt vmcnt(0) ; HSA-TRAP-GFX803-V2-NEXT: s_waitcnt vmcnt(0)
; HSA-TRAP-GFX803-V2-NEXT: s_endpgm ; HSA-TRAP-GFX803-V2-NEXT: s_endpgm
; HSA-TRAP-GFX803-V2-NEXT: BB1_2: ; %trap ; HSA-TRAP-GFX803-V2-NEXT: .LBB1_2: ; %trap
; HSA-TRAP-GFX803-V2-NEXT: s_mov_b64 s[0:1], s[4:5] ; HSA-TRAP-GFX803-V2-NEXT: s_mov_b64 s[0:1], s[4:5]
; HSA-TRAP-GFX803-V2-NEXT: s_trap 2 ; HSA-TRAP-GFX803-V2-NEXT: s_trap 2
; ;
; HSA-TRAP-GFX803-V3-LABEL: non_entry_trap: ; HSA-TRAP-GFX803-V3-LABEL: non_entry_trap:
; HSA-TRAP-GFX803-V3: ; %bb.0: ; %entry ; HSA-TRAP-GFX803-V3: ; %bb.0: ; %entry
; HSA-TRAP-GFX803-V3-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 ; HSA-TRAP-GFX803-V3-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
; HSA-TRAP-GFX803-V3-NEXT: s_waitcnt lgkmcnt(0) ; HSA-TRAP-GFX803-V3-NEXT: s_waitcnt lgkmcnt(0)
; HSA-TRAP-GFX803-V3-NEXT: v_mov_b32_e32 v0, s0 ; HSA-TRAP-GFX803-V3-NEXT: v_mov_b32_e32 v0, s0
; HSA-TRAP-GFX803-V3-NEXT: v_mov_b32_e32 v1, s1 ; HSA-TRAP-GFX803-V3-NEXT: v_mov_b32_e32 v1, s1
; HSA-TRAP-GFX803-V3-NEXT: flat_load_dword v0, v[0:1] glc ; HSA-TRAP-GFX803-V3-NEXT: flat_load_dword v0, v[0:1] glc
; HSA-TRAP-GFX803-V3-NEXT: s_waitcnt vmcnt(0) ; HSA-TRAP-GFX803-V3-NEXT: s_waitcnt vmcnt(0)
; HSA-TRAP-GFX803-V3-NEXT: v_cmp_eq_u32_e32 vcc, -1, v0 ; HSA-TRAP-GFX803-V3-NEXT: v_cmp_eq_u32_e32 vcc, -1, v0
; HSA-TRAP-GFX803-V3-NEXT: s_and_b64 vcc, exec, vcc ; HSA-TRAP-GFX803-V3-NEXT: s_and_b64 vcc, exec, vcc
; HSA-TRAP-GFX803-V3-NEXT: s_cbranch_vccz BB1_2 ; HSA-TRAP-GFX803-V3-NEXT: s_cbranch_vccz .LBB1_2
; HSA-TRAP-GFX803-V3-NEXT: ; %bb.1: ; %ret ; HSA-TRAP-GFX803-V3-NEXT: ; %bb.1: ; %ret
; HSA-TRAP-GFX803-V3-NEXT: v_mov_b32_e32 v0, s0 ; HSA-TRAP-GFX803-V3-NEXT: v_mov_b32_e32 v0, s0
; HSA-TRAP-GFX803-V3-NEXT: v_mov_b32_e32 v2, 3 ; HSA-TRAP-GFX803-V3-NEXT: v_mov_b32_e32 v2, 3
; HSA-TRAP-GFX803-V3-NEXT: v_mov_b32_e32 v1, s1 ; HSA-TRAP-GFX803-V3-NEXT: v_mov_b32_e32 v1, s1
; HSA-TRAP-GFX803-V3-NEXT: flat_store_dword v[0:1], v2 ; HSA-TRAP-GFX803-V3-NEXT: flat_store_dword v[0:1], v2
; HSA-TRAP-GFX803-V3-NEXT: s_waitcnt vmcnt(0) ; HSA-TRAP-GFX803-V3-NEXT: s_waitcnt vmcnt(0)
; HSA-TRAP-GFX803-V3-NEXT: s_endpgm ; HSA-TRAP-GFX803-V3-NEXT: s_endpgm
; HSA-TRAP-GFX803-V3-NEXT: BB1_2: ; %trap ; HSA-TRAP-GFX803-V3-NEXT: .LBB1_2: ; %trap
; HSA-TRAP-GFX803-V3-NEXT: s_mov_b64 s[0:1], s[4:5] ; HSA-TRAP-GFX803-V3-NEXT: s_mov_b64 s[0:1], s[4:5]
; HSA-TRAP-GFX803-V3-NEXT: s_trap 2 ; HSA-TRAP-GFX803-V3-NEXT: s_trap 2
; ;
; HSA-TRAP-GFX803-V4-LABEL: non_entry_trap: ; HSA-TRAP-GFX803-V4-LABEL: non_entry_trap:
; HSA-TRAP-GFX803-V4: ; %bb.0: ; %entry ; HSA-TRAP-GFX803-V4: ; %bb.0: ; %entry
; HSA-TRAP-GFX803-V4-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 ; HSA-TRAP-GFX803-V4-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
; HSA-TRAP-GFX803-V4-NEXT: s_waitcnt lgkmcnt(0) ; HSA-TRAP-GFX803-V4-NEXT: s_waitcnt lgkmcnt(0)
; HSA-TRAP-GFX803-V4-NEXT: v_mov_b32_e32 v0, s0 ; HSA-TRAP-GFX803-V4-NEXT: v_mov_b32_e32 v0, s0
; HSA-TRAP-GFX803-V4-NEXT: v_mov_b32_e32 v1, s1 ; HSA-TRAP-GFX803-V4-NEXT: v_mov_b32_e32 v1, s1
; HSA-TRAP-GFX803-V4-NEXT: flat_load_dword v0, v[0:1] glc ; HSA-TRAP-GFX803-V4-NEXT: flat_load_dword v0, v[0:1] glc
; HSA-TRAP-GFX803-V4-NEXT: s_waitcnt vmcnt(0) ; HSA-TRAP-GFX803-V4-NEXT: s_waitcnt vmcnt(0)
; HSA-TRAP-GFX803-V4-NEXT: v_cmp_eq_u32_e32 vcc, -1, v0 ; HSA-TRAP-GFX803-V4-NEXT: v_cmp_eq_u32_e32 vcc, -1, v0
; HSA-TRAP-GFX803-V4-NEXT: s_and_b64 vcc, exec, vcc ; HSA-TRAP-GFX803-V4-NEXT: s_and_b64 vcc, exec, vcc
; HSA-TRAP-GFX803-V4-NEXT: s_cbranch_vccz BB1_2 ; HSA-TRAP-GFX803-V4-NEXT: s_cbranch_vccz .LBB1_2
; HSA-TRAP-GFX803-V4-NEXT: ; %bb.1: ; %ret ; HSA-TRAP-GFX803-V4-NEXT: ; %bb.1: ; %ret
; HSA-TRAP-GFX803-V4-NEXT: v_mov_b32_e32 v0, s0 ; HSA-TRAP-GFX803-V4-NEXT: v_mov_b32_e32 v0, s0
; HSA-TRAP-GFX803-V4-NEXT: v_mov_b32_e32 v2, 3 ; HSA-TRAP-GFX803-V4-NEXT: v_mov_b32_e32 v2, 3
; HSA-TRAP-GFX803-V4-NEXT: v_mov_b32_e32 v1, s1 ; HSA-TRAP-GFX803-V4-NEXT: v_mov_b32_e32 v1, s1
; HSA-TRAP-GFX803-V4-NEXT: flat_store_dword v[0:1], v2 ; HSA-TRAP-GFX803-V4-NEXT: flat_store_dword v[0:1], v2
; HSA-TRAP-GFX803-V4-NEXT: s_waitcnt vmcnt(0) ; HSA-TRAP-GFX803-V4-NEXT: s_waitcnt vmcnt(0)
; HSA-TRAP-GFX803-V4-NEXT: s_endpgm ; HSA-TRAP-GFX803-V4-NEXT: s_endpgm
; HSA-TRAP-GFX803-V4-NEXT: BB1_2: ; %trap ; HSA-TRAP-GFX803-V4-NEXT: .LBB1_2: ; %trap
; HSA-TRAP-GFX803-V4-NEXT: s_mov_b64 s[0:1], s[4:5] ; HSA-TRAP-GFX803-V4-NEXT: s_mov_b64 s[0:1], s[4:5]
; HSA-TRAP-GFX803-V4-NEXT: s_trap 2 ; HSA-TRAP-GFX803-V4-NEXT: s_trap 2
; ;
; HSA-TRAP-GFX900-V2-LABEL: non_entry_trap: ; HSA-TRAP-GFX900-V2-LABEL: non_entry_trap:
; HSA-TRAP-GFX900-V2: .amd_kernel_code_t ; HSA-TRAP-GFX900-V2: .amd_kernel_code_t
; HSA-TRAP-GFX900-V2-NEXT: amd_code_version_major = 1 ; HSA-TRAP-GFX900-V2-NEXT: amd_code_version_major = 1
; HSA-TRAP-GFX900-V2-NEXT: amd_code_version_minor = 2 ; HSA-TRAP-GFX900-V2-NEXT: amd_code_version_minor = 2
; HSA-TRAP-GFX900-V2-NEXT: amd_machine_kind = 1 ; HSA-TRAP-GFX900-V2-NEXT: amd_machine_kind = 1
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; HSA-TRAP-GFX900-V2-NEXT: ; %bb.0: ; %entry ; HSA-TRAP-GFX900-V2-NEXT: ; %bb.0: ; %entry
; HSA-TRAP-GFX900-V2-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 ; HSA-TRAP-GFX900-V2-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
; HSA-TRAP-GFX900-V2-NEXT: v_mov_b32_e32 v0, 0 ; HSA-TRAP-GFX900-V2-NEXT: v_mov_b32_e32 v0, 0
; HSA-TRAP-GFX900-V2-NEXT: s_waitcnt lgkmcnt(0) ; HSA-TRAP-GFX900-V2-NEXT: s_waitcnt lgkmcnt(0)
; HSA-TRAP-GFX900-V2-NEXT: global_load_dword v1, v0, s[0:1] glc ; HSA-TRAP-GFX900-V2-NEXT: global_load_dword v1, v0, s[0:1] glc
; HSA-TRAP-GFX900-V2-NEXT: s_waitcnt vmcnt(0) ; HSA-TRAP-GFX900-V2-NEXT: s_waitcnt vmcnt(0)
; HSA-TRAP-GFX900-V2-NEXT: v_cmp_eq_u32_e32 vcc, -1, v1 ; HSA-TRAP-GFX900-V2-NEXT: v_cmp_eq_u32_e32 vcc, -1, v1
; HSA-TRAP-GFX900-V2-NEXT: s_and_b64 vcc, exec, vcc ; HSA-TRAP-GFX900-V2-NEXT: s_and_b64 vcc, exec, vcc
; HSA-TRAP-GFX900-V2-NEXT: s_cbranch_vccz BB1_2 ; HSA-TRAP-GFX900-V2-NEXT: s_cbranch_vccz .LBB1_2
; HSA-TRAP-GFX900-V2-NEXT: ; %bb.1: ; %ret ; HSA-TRAP-GFX900-V2-NEXT: ; %bb.1: ; %ret
; HSA-TRAP-GFX900-V2-NEXT: v_mov_b32_e32 v1, 3 ; HSA-TRAP-GFX900-V2-NEXT: v_mov_b32_e32 v1, 3
; HSA-TRAP-GFX900-V2-NEXT: global_store_dword v0, v1, s[0:1] ; HSA-TRAP-GFX900-V2-NEXT: global_store_dword v0, v1, s[0:1]
; HSA-TRAP-GFX900-V2-NEXT: s_waitcnt vmcnt(0) ; HSA-TRAP-GFX900-V2-NEXT: s_waitcnt vmcnt(0)
; HSA-TRAP-GFX900-V2-NEXT: s_endpgm ; HSA-TRAP-GFX900-V2-NEXT: s_endpgm
; HSA-TRAP-GFX900-V2-NEXT: BB1_2: ; %trap ; HSA-TRAP-GFX900-V2-NEXT: .LBB1_2: ; %trap
; HSA-TRAP-GFX900-V2-NEXT: s_mov_b64 s[0:1], s[4:5] ; HSA-TRAP-GFX900-V2-NEXT: s_mov_b64 s[0:1], s[4:5]
; HSA-TRAP-GFX900-V2-NEXT: s_trap 2 ; HSA-TRAP-GFX900-V2-NEXT: s_trap 2
; ;
; HSA-TRAP-GFX900-V3-LABEL: non_entry_trap: ; HSA-TRAP-GFX900-V3-LABEL: non_entry_trap:
; HSA-TRAP-GFX900-V3: ; %bb.0: ; %entry ; HSA-TRAP-GFX900-V3: ; %bb.0: ; %entry
; HSA-TRAP-GFX900-V3-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 ; HSA-TRAP-GFX900-V3-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
; HSA-TRAP-GFX900-V3-NEXT: v_mov_b32_e32 v0, 0 ; HSA-TRAP-GFX900-V3-NEXT: v_mov_b32_e32 v0, 0
; HSA-TRAP-GFX900-V3-NEXT: s_waitcnt lgkmcnt(0) ; HSA-TRAP-GFX900-V3-NEXT: s_waitcnt lgkmcnt(0)
; HSA-TRAP-GFX900-V3-NEXT: global_load_dword v1, v0, s[0:1] glc ; HSA-TRAP-GFX900-V3-NEXT: global_load_dword v1, v0, s[0:1] glc
; HSA-TRAP-GFX900-V3-NEXT: s_waitcnt vmcnt(0) ; HSA-TRAP-GFX900-V3-NEXT: s_waitcnt vmcnt(0)
; HSA-TRAP-GFX900-V3-NEXT: v_cmp_eq_u32_e32 vcc, -1, v1 ; HSA-TRAP-GFX900-V3-NEXT: v_cmp_eq_u32_e32 vcc, -1, v1
; HSA-TRAP-GFX900-V3-NEXT: s_and_b64 vcc, exec, vcc ; HSA-TRAP-GFX900-V3-NEXT: s_and_b64 vcc, exec, vcc
; HSA-TRAP-GFX900-V3-NEXT: s_cbranch_vccz BB1_2 ; HSA-TRAP-GFX900-V3-NEXT: s_cbranch_vccz .LBB1_2
; HSA-TRAP-GFX900-V3-NEXT: ; %bb.1: ; %ret ; HSA-TRAP-GFX900-V3-NEXT: ; %bb.1: ; %ret
; HSA-TRAP-GFX900-V3-NEXT: v_mov_b32_e32 v1, 3 ; HSA-TRAP-GFX900-V3-NEXT: v_mov_b32_e32 v1, 3
; HSA-TRAP-GFX900-V3-NEXT: global_store_dword v0, v1, s[0:1] ; HSA-TRAP-GFX900-V3-NEXT: global_store_dword v0, v1, s[0:1]
; HSA-TRAP-GFX900-V3-NEXT: s_waitcnt vmcnt(0) ; HSA-TRAP-GFX900-V3-NEXT: s_waitcnt vmcnt(0)
; HSA-TRAP-GFX900-V3-NEXT: s_endpgm ; HSA-TRAP-GFX900-V3-NEXT: s_endpgm
; HSA-TRAP-GFX900-V3-NEXT: BB1_2: ; %trap ; HSA-TRAP-GFX900-V3-NEXT: .LBB1_2: ; %trap
; HSA-TRAP-GFX900-V3-NEXT: s_mov_b64 s[0:1], s[4:5] ; HSA-TRAP-GFX900-V3-NEXT: s_mov_b64 s[0:1], s[4:5]
; HSA-TRAP-GFX900-V3-NEXT: s_trap 2 ; HSA-TRAP-GFX900-V3-NEXT: s_trap 2
; ;
; HSA-TRAP-GFX900-V4-LABEL: non_entry_trap: ; HSA-TRAP-GFX900-V4-LABEL: non_entry_trap:
; HSA-TRAP-GFX900-V4: ; %bb.0: ; %entry ; HSA-TRAP-GFX900-V4: ; %bb.0: ; %entry
; HSA-TRAP-GFX900-V4-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 ; HSA-TRAP-GFX900-V4-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
; HSA-TRAP-GFX900-V4-NEXT: v_mov_b32_e32 v0, 0 ; HSA-TRAP-GFX900-V4-NEXT: v_mov_b32_e32 v0, 0
; HSA-TRAP-GFX900-V4-NEXT: s_waitcnt lgkmcnt(0) ; HSA-TRAP-GFX900-V4-NEXT: s_waitcnt lgkmcnt(0)
; HSA-TRAP-GFX900-V4-NEXT: global_load_dword v1, v0, s[0:1] glc ; HSA-TRAP-GFX900-V4-NEXT: global_load_dword v1, v0, s[0:1] glc
; HSA-TRAP-GFX900-V4-NEXT: s_waitcnt vmcnt(0) ; HSA-TRAP-GFX900-V4-NEXT: s_waitcnt vmcnt(0)
; HSA-TRAP-GFX900-V4-NEXT: v_cmp_eq_u32_e32 vcc, -1, v1 ; HSA-TRAP-GFX900-V4-NEXT: v_cmp_eq_u32_e32 vcc, -1, v1
; HSA-TRAP-GFX900-V4-NEXT: s_and_b64 vcc, exec, vcc ; HSA-TRAP-GFX900-V4-NEXT: s_and_b64 vcc, exec, vcc
; HSA-TRAP-GFX900-V4-NEXT: s_cbranch_vccz BB1_2 ; HSA-TRAP-GFX900-V4-NEXT: s_cbranch_vccz .LBB1_2
; HSA-TRAP-GFX900-V4-NEXT: ; %bb.1: ; %ret ; HSA-TRAP-GFX900-V4-NEXT: ; %bb.1: ; %ret
; HSA-TRAP-GFX900-V4-NEXT: v_mov_b32_e32 v1, 3 ; HSA-TRAP-GFX900-V4-NEXT: v_mov_b32_e32 v1, 3
; HSA-TRAP-GFX900-V4-NEXT: global_store_dword v0, v1, s[0:1] ; HSA-TRAP-GFX900-V4-NEXT: global_store_dword v0, v1, s[0:1]
; HSA-TRAP-GFX900-V4-NEXT: s_waitcnt vmcnt(0) ; HSA-TRAP-GFX900-V4-NEXT: s_waitcnt vmcnt(0)
; HSA-TRAP-GFX900-V4-NEXT: s_endpgm ; HSA-TRAP-GFX900-V4-NEXT: s_endpgm
; HSA-TRAP-GFX900-V4-NEXT: BB1_2: ; %trap ; HSA-TRAP-GFX900-V4-NEXT: .LBB1_2: ; %trap
; HSA-TRAP-GFX900-V4-NEXT: s_trap 2 ; HSA-TRAP-GFX900-V4-NEXT: s_trap 2
; ;
; HSA-NOTRAP-GFX900-V2-LABEL: non_entry_trap: ; HSA-NOTRAP-GFX900-V2-LABEL: non_entry_trap:
; HSA-NOTRAP-GFX900-V2: .amd_kernel_code_t ; HSA-NOTRAP-GFX900-V2: .amd_kernel_code_t
; HSA-NOTRAP-GFX900-V2-NEXT: amd_code_version_major = 1 ; HSA-NOTRAP-GFX900-V2-NEXT: amd_code_version_major = 1
; HSA-NOTRAP-GFX900-V2-NEXT: amd_code_version_minor = 2 ; HSA-NOTRAP-GFX900-V2-NEXT: amd_code_version_minor = 2
; HSA-NOTRAP-GFX900-V2-NEXT: amd_machine_kind = 1 ; HSA-NOTRAP-GFX900-V2-NEXT: amd_machine_kind = 1
; HSA-NOTRAP-GFX900-V2-NEXT: amd_machine_version_major = 9 ; HSA-NOTRAP-GFX900-V2-NEXT: amd_machine_version_major = 9
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; HSA-NOTRAP-GFX900-V2-NEXT: ; %bb.0: ; %entry ; HSA-NOTRAP-GFX900-V2-NEXT: ; %bb.0: ; %entry
; HSA-NOTRAP-GFX900-V2-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 ; HSA-NOTRAP-GFX900-V2-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
; HSA-NOTRAP-GFX900-V2-NEXT: v_mov_b32_e32 v0, 0 ; HSA-NOTRAP-GFX900-V2-NEXT: v_mov_b32_e32 v0, 0
; HSA-NOTRAP-GFX900-V2-NEXT: s_waitcnt lgkmcnt(0) ; HSA-NOTRAP-GFX900-V2-NEXT: s_waitcnt lgkmcnt(0)
; HSA-NOTRAP-GFX900-V2-NEXT: global_load_dword v1, v0, s[0:1] glc ; HSA-NOTRAP-GFX900-V2-NEXT: global_load_dword v1, v0, s[0:1] glc
; HSA-NOTRAP-GFX900-V2-NEXT: s_waitcnt vmcnt(0) ; HSA-NOTRAP-GFX900-V2-NEXT: s_waitcnt vmcnt(0)
; HSA-NOTRAP-GFX900-V2-NEXT: v_cmp_eq_u32_e32 vcc, -1, v1 ; HSA-NOTRAP-GFX900-V2-NEXT: v_cmp_eq_u32_e32 vcc, -1, v1
; HSA-NOTRAP-GFX900-V2-NEXT: s_and_b64 vcc, exec, vcc ; HSA-NOTRAP-GFX900-V2-NEXT: s_and_b64 vcc, exec, vcc
; HSA-NOTRAP-GFX900-V2-NEXT: s_cbranch_vccz BB1_2 ; HSA-NOTRAP-GFX900-V2-NEXT: s_cbranch_vccz .LBB1_2
; HSA-NOTRAP-GFX900-V2-NEXT: ; %bb.1: ; %ret ; HSA-NOTRAP-GFX900-V2-NEXT: ; %bb.1: ; %ret
; HSA-NOTRAP-GFX900-V2-NEXT: v_mov_b32_e32 v1, 3 ; HSA-NOTRAP-GFX900-V2-NEXT: v_mov_b32_e32 v1, 3
; HSA-NOTRAP-GFX900-V2-NEXT: global_store_dword v0, v1, s[0:1] ; HSA-NOTRAP-GFX900-V2-NEXT: global_store_dword v0, v1, s[0:1]
; HSA-NOTRAP-GFX900-V2-NEXT: s_waitcnt vmcnt(0) ; HSA-NOTRAP-GFX900-V2-NEXT: s_waitcnt vmcnt(0)
; HSA-NOTRAP-GFX900-V2-NEXT: s_endpgm ; HSA-NOTRAP-GFX900-V2-NEXT: s_endpgm
; HSA-NOTRAP-GFX900-V2-NEXT: BB1_2: ; %trap ; HSA-NOTRAP-GFX900-V2-NEXT: .LBB1_2: ; %trap
; HSA-NOTRAP-GFX900-V2-NEXT: s_endpgm ; HSA-NOTRAP-GFX900-V2-NEXT: s_endpgm
; ;
; HSA-NOTRAP-GFX900-V3-LABEL: non_entry_trap: ; HSA-NOTRAP-GFX900-V3-LABEL: non_entry_trap:
; HSA-NOTRAP-GFX900-V3: ; %bb.0: ; %entry ; HSA-NOTRAP-GFX900-V3: ; %bb.0: ; %entry
; HSA-NOTRAP-GFX900-V3-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 ; HSA-NOTRAP-GFX900-V3-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
; HSA-NOTRAP-GFX900-V3-NEXT: v_mov_b32_e32 v0, 0 ; HSA-NOTRAP-GFX900-V3-NEXT: v_mov_b32_e32 v0, 0
; HSA-NOTRAP-GFX900-V3-NEXT: s_waitcnt lgkmcnt(0) ; HSA-NOTRAP-GFX900-V3-NEXT: s_waitcnt lgkmcnt(0)
; HSA-NOTRAP-GFX900-V3-NEXT: global_load_dword v1, v0, s[0:1] glc ; HSA-NOTRAP-GFX900-V3-NEXT: global_load_dword v1, v0, s[0:1] glc
; HSA-NOTRAP-GFX900-V3-NEXT: s_waitcnt vmcnt(0) ; HSA-NOTRAP-GFX900-V3-NEXT: s_waitcnt vmcnt(0)
; HSA-NOTRAP-GFX900-V3-NEXT: v_cmp_eq_u32_e32 vcc, -1, v1 ; HSA-NOTRAP-GFX900-V3-NEXT: v_cmp_eq_u32_e32 vcc, -1, v1
; HSA-NOTRAP-GFX900-V3-NEXT: s_and_b64 vcc, exec, vcc ; HSA-NOTRAP-GFX900-V3-NEXT: s_and_b64 vcc, exec, vcc
; HSA-NOTRAP-GFX900-V3-NEXT: s_cbranch_vccz BB1_2 ; HSA-NOTRAP-GFX900-V3-NEXT: s_cbranch_vccz .LBB1_2
; HSA-NOTRAP-GFX900-V3-NEXT: ; %bb.1: ; %ret ; HSA-NOTRAP-GFX900-V3-NEXT: ; %bb.1: ; %ret
; HSA-NOTRAP-GFX900-V3-NEXT: v_mov_b32_e32 v1, 3 ; HSA-NOTRAP-GFX900-V3-NEXT: v_mov_b32_e32 v1, 3
; HSA-NOTRAP-GFX900-V3-NEXT: global_store_dword v0, v1, s[0:1] ; HSA-NOTRAP-GFX900-V3-NEXT: global_store_dword v0, v1, s[0:1]
; HSA-NOTRAP-GFX900-V3-NEXT: s_waitcnt vmcnt(0) ; HSA-NOTRAP-GFX900-V3-NEXT: s_waitcnt vmcnt(0)
; HSA-NOTRAP-GFX900-V3-NEXT: s_endpgm ; HSA-NOTRAP-GFX900-V3-NEXT: s_endpgm
; HSA-NOTRAP-GFX900-V3-NEXT: BB1_2: ; %trap ; HSA-NOTRAP-GFX900-V3-NEXT: .LBB1_2: ; %trap
; HSA-NOTRAP-GFX900-V3-NEXT: s_endpgm ; HSA-NOTRAP-GFX900-V3-NEXT: s_endpgm
; ;
; HSA-NOTRAP-GFX900-V4-LABEL: non_entry_trap: ; HSA-NOTRAP-GFX900-V4-LABEL: non_entry_trap:
; HSA-NOTRAP-GFX900-V4: ; %bb.0: ; %entry ; HSA-NOTRAP-GFX900-V4: ; %bb.0: ; %entry
; HSA-NOTRAP-GFX900-V4-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 ; HSA-NOTRAP-GFX900-V4-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
; HSA-NOTRAP-GFX900-V4-NEXT: v_mov_b32_e32 v0, 0 ; HSA-NOTRAP-GFX900-V4-NEXT: v_mov_b32_e32 v0, 0
; HSA-NOTRAP-GFX900-V4-NEXT: s_waitcnt lgkmcnt(0) ; HSA-NOTRAP-GFX900-V4-NEXT: s_waitcnt lgkmcnt(0)
; HSA-NOTRAP-GFX900-V4-NEXT: global_load_dword v1, v0, s[0:1] glc ; HSA-NOTRAP-GFX900-V4-NEXT: global_load_dword v1, v0, s[0:1] glc
; HSA-NOTRAP-GFX900-V4-NEXT: s_waitcnt vmcnt(0) ; HSA-NOTRAP-GFX900-V4-NEXT: s_waitcnt vmcnt(0)
; HSA-NOTRAP-GFX900-V4-NEXT: v_cmp_eq_u32_e32 vcc, -1, v1 ; HSA-NOTRAP-GFX900-V4-NEXT: v_cmp_eq_u32_e32 vcc, -1, v1
; HSA-NOTRAP-GFX900-V4-NEXT: s_and_b64 vcc, exec, vcc ; HSA-NOTRAP-GFX900-V4-NEXT: s_and_b64 vcc, exec, vcc
; HSA-NOTRAP-GFX900-V4-NEXT: s_cbranch_vccz BB1_2 ; HSA-NOTRAP-GFX900-V4-NEXT: s_cbranch_vccz .LBB1_2
; HSA-NOTRAP-GFX900-V4-NEXT: ; %bb.1: ; %ret ; HSA-NOTRAP-GFX900-V4-NEXT: ; %bb.1: ; %ret
; HSA-NOTRAP-GFX900-V4-NEXT: v_mov_b32_e32 v1, 3 ; HSA-NOTRAP-GFX900-V4-NEXT: v_mov_b32_e32 v1, 3
; HSA-NOTRAP-GFX900-V4-NEXT: global_store_dword v0, v1, s[0:1] ; HSA-NOTRAP-GFX900-V4-NEXT: global_store_dword v0, v1, s[0:1]
; HSA-NOTRAP-GFX900-V4-NEXT: s_waitcnt vmcnt(0) ; HSA-NOTRAP-GFX900-V4-NEXT: s_waitcnt vmcnt(0)
; HSA-NOTRAP-GFX900-V4-NEXT: s_endpgm ; HSA-NOTRAP-GFX900-V4-NEXT: s_endpgm
; HSA-NOTRAP-GFX900-V4-NEXT: BB1_2: ; %trap ; HSA-NOTRAP-GFX900-V4-NEXT: .LBB1_2: ; %trap
; HSA-NOTRAP-GFX900-V4-NEXT: s_endpgm ; HSA-NOTRAP-GFX900-V4-NEXT: s_endpgm
entry: entry:
%tmp29 = load volatile i32, i32 addrspace(1)* %arg0 %tmp29 = load volatile i32, i32 addrspace(1)* %arg0
%cmp = icmp eq i32 %tmp29, -1 %cmp = icmp eq i32 %tmp29, -1
br i1 %cmp, label %ret, label %trap br i1 %cmp, label %ret, label %trap
trap: trap:
call void @llvm.trap() call void @llvm.trap()
▲ Show 20 Lines • Show All 384 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/udiv64.ll

Show First 20 Lines • Show All 142 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: s_subb_u32 s9, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s9, 0, 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[16:17], s[8:9], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[16:17], s[8:9], 63
; GCN-IR-NEXT: s_mov_b32 s11, 0 ; GCN-IR-NEXT: s_mov_b32 s11, 0
; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17] ; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17]
; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[16:17], s[8:9], 63 ; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[16:17], s[8:9], 63
; GCN-IR-NEXT: s_xor_b64 s[18:19], s[14:15], -1 ; GCN-IR-NEXT: s_xor_b64 s[18:19], s[14:15], -1
; GCN-IR-NEXT: s_and_b64 s[16:17], s[18:19], s[16:17] ; GCN-IR-NEXT: s_and_b64 s[16:17], s[18:19], s[16:17]
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[16:17] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[16:17]
; GCN-IR-NEXT: s_cbranch_vccz BB0_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_5
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s14, s8, 1 ; GCN-IR-NEXT: s_add_u32 s14, s8, 1
; GCN-IR-NEXT: v_mov_b32_e32 v0, s8 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s8
; GCN-IR-NEXT: s_addc_u32 s15, s9, 0 ; GCN-IR-NEXT: s_addc_u32 s15, s9, 0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s9 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s9
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[14:15], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[14:15], v[0:1]
; GCN-IR-NEXT: s_sub_i32 s8, 63, s8 ; GCN-IR-NEXT: s_sub_i32 s8, 63, s8
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[6:7], s8 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[6:7], s8
; GCN-IR-NEXT: s_cbranch_vccz BB0_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[14:15], s[6:7], s14 ; GCN-IR-NEXT: s_lshr_b64 s[14:15], s[6:7], s14
; GCN-IR-NEXT: s_add_u32 s16, s0, -1 ; GCN-IR-NEXT: s_add_u32 s16, s0, -1
; GCN-IR-NEXT: s_addc_u32 s17, s1, -1 ; GCN-IR-NEXT: s_addc_u32 s17, s1, -1
; GCN-IR-NEXT: s_not_b64 s[2:3], s[10:11] ; GCN-IR-NEXT: s_not_b64 s[2:3], s[10:11]
; GCN-IR-NEXT: s_add_u32 s6, s2, s12 ; GCN-IR-NEXT: s_add_u32 s6, s2, s12
; GCN-IR-NEXT: s_mov_b32 s13, s11 ; GCN-IR-NEXT: s_mov_b32 s13, s11
; GCN-IR-NEXT: s_addc_u32 s7, s3, s11 ; GCN-IR-NEXT: s_addc_u32 s7, s3, s11
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: s_mov_b32 s3, 0 ; GCN-IR-NEXT: s_mov_b32 s3, 0
; GCN-IR-NEXT: BB0_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB0_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[14:15], 1 ; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[14:15], 1
; GCN-IR-NEXT: s_lshr_b32 s2, s9, 31 ; GCN-IR-NEXT: s_lshr_b32 s2, s9, 31
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1
; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[2:3] ; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[2:3]
; GCN-IR-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9] ; GCN-IR-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9]
; GCN-IR-NEXT: s_sub_u32 s2, s16, s12 ; GCN-IR-NEXT: s_sub_u32 s2, s16, s12
; GCN-IR-NEXT: s_subb_u32 s2, s17, s13 ; GCN-IR-NEXT: s_subb_u32 s2, s17, s13
; GCN-IR-NEXT: s_ashr_i32 s10, s2, 31 ; GCN-IR-NEXT: s_ashr_i32 s10, s2, 31
; GCN-IR-NEXT: s_mov_b32 s11, s10 ; GCN-IR-NEXT: s_mov_b32 s11, s10
; GCN-IR-NEXT: s_and_b32 s2, s10, 1 ; GCN-IR-NEXT: s_and_b32 s2, s10, 1
; GCN-IR-NEXT: s_and_b64 s[14:15], s[10:11], s[0:1] ; GCN-IR-NEXT: s_and_b64 s[14:15], s[10:11], s[0:1]
; GCN-IR-NEXT: s_sub_u32 s14, s12, s14 ; GCN-IR-NEXT: s_sub_u32 s14, s12, s14
; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
; GCN-IR-NEXT: s_subb_u32 s15, s13, s15 ; GCN-IR-NEXT: s_subb_u32 s15, s13, s15
; GCN-IR-NEXT: v_mov_b32_e32 v1, s7 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s7
; GCN-IR-NEXT: s_add_u32 s6, s6, 1 ; GCN-IR-NEXT: s_add_u32 s6, s6, 1
; GCN-IR-NEXT: s_addc_u32 s7, s7, 0 ; GCN-IR-NEXT: s_addc_u32 s7, s7, 0
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[6:7], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[6:7], v[0:1]
; GCN-IR-NEXT: s_mov_b64 s[10:11], s[2:3] ; GCN-IR-NEXT: s_mov_b64 s[10:11], s[2:3]
; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_cbranch_vccz BB0_3 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_3
; GCN-IR-NEXT: BB0_4: ; %Flow6 ; GCN-IR-NEXT: .LBB0_4: ; %Flow6
; GCN-IR-NEXT: s_lshl_b64 s[0:1], s[8:9], 1 ; GCN-IR-NEXT: s_lshl_b64 s[0:1], s[8:9], 1
; GCN-IR-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1] ; GCN-IR-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
; GCN-IR-NEXT: v_mov_b32_e32 v0, s0 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s1 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s1
; GCN-IR-NEXT: s_branch BB0_6 ; GCN-IR-NEXT: s_branch .LBB0_6
; GCN-IR-NEXT: BB0_5: ; GCN-IR-NEXT: .LBB0_5:
; GCN-IR-NEXT: v_mov_b32_e32 v0, s7 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s7
; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[14:15] ; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[14:15]
; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[14:15] ; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[14:15]
; GCN-IR-NEXT: BB0_6: ; %udiv-end ; GCN-IR-NEXT: .LBB0_6: ; %udiv-end
; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: s_mov_b32 s6, -1
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-IR-NEXT: s_endpgm ; GCN-IR-NEXT: s_endpgm
%result = udiv i64 %x, %y %result = udiv i64 %x, %y
store i64 %result, i64 addrspace(1)* %out store i64 %result, i64 addrspace(1)* %out
ret void ret void
} }
▲ Show 20 Lines • Show All 130 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[6:7] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[6:7]
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
; GCN-IR-NEXT: v_mov_b32_e32 v11, v9 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v9
; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v1, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v1, 0, s[4:5]
; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v0, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v0, 0, s[4:5]
; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB1_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB1_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v6 ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v6
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v7, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v6 ; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v6
; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[12:13], v[6:7] ; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[12:13], v[6:7]
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4
; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB1_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB1_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, -1, v2 ; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, -1, v2
; GCN-IR-NEXT: v_lshr_b64 v[12:13], v[0:1], v12 ; GCN-IR-NEXT: v_lshr_b64 v[12:13], v[0:1], v12
; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, -1, v3, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, -1, v3, vcc
; GCN-IR-NEXT: v_not_b32_e32 v0, v8 ; GCN-IR-NEXT: v_not_b32_e32 v0, v8
; GCN-IR-NEXT: v_not_b32_e32 v1, v9 ; GCN-IR-NEXT: v_not_b32_e32 v1, v9
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v10 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v10
; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, v1, v11, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, v1, v11, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: BB1_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB1_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[12:13], 1 ; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[12:13], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5
; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6 ; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v14, v10 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v14, v10
; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v15, v11, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v15, v11, vcc
; GCN-IR-NEXT: v_or_b32_e32 v4, v8, v4 ; GCN-IR-NEXT: v_or_b32_e32 v4, v8, v4
; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v6 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v6
; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v8 ; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v8
; GCN-IR-NEXT: v_and_b32_e32 v13, v8, v3 ; GCN-IR-NEXT: v_and_b32_e32 v13, v8, v3
; GCN-IR-NEXT: v_and_b32_e32 v12, v8, v2 ; GCN-IR-NEXT: v_and_b32_e32 v12, v8, v2
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v0
; GCN-IR-NEXT: v_or_b32_e32 v5, v9, v5 ; GCN-IR-NEXT: v_or_b32_e32 v5, v9, v5
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v1, vcc
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[0:1]
; GCN-IR-NEXT: v_mov_b32_e32 v0, v8 ; GCN-IR-NEXT: v_mov_b32_e32 v0, v8
; GCN-IR-NEXT: v_sub_i32_e64 v12, s[4:5], v10, v12 ; GCN-IR-NEXT: v_sub_i32_e64 v12, s[4:5], v10, v12
; GCN-IR-NEXT: v_mov_b32_e32 v1, v9 ; GCN-IR-NEXT: v_mov_b32_e32 v1, v9
; GCN-IR-NEXT: v_mov_b32_e32 v9, v7 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v7
; GCN-IR-NEXT: v_subb_u32_e64 v13, s[4:5], v11, v13, s[4:5] ; GCN-IR-NEXT: v_subb_u32_e64 v13, s[4:5], v11, v13, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v8, v6 ; GCN-IR-NEXT: v_mov_b32_e32 v8, v6
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execnz BB1_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB1_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: BB1_5: ; %Flow3 ; GCN-IR-NEXT: .LBB1_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[4:5], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[4:5], 1
; GCN-IR-NEXT: v_or_b32_e32 v4, v7, v1 ; GCN-IR-NEXT: v_or_b32_e32 v4, v7, v1
; GCN-IR-NEXT: v_or_b32_e32 v5, v6, v0 ; GCN-IR-NEXT: v_or_b32_e32 v5, v6, v0
; GCN-IR-NEXT: BB1_6: ; %Flow4 ; GCN-IR-NEXT: .LBB1_6: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_mov_b32_e32 v0, v5 ; GCN-IR-NEXT: v_mov_b32_e32 v0, v5
; GCN-IR-NEXT: v_mov_b32_e32 v1, v4 ; GCN-IR-NEXT: v_mov_b32_e32 v1, v4
; GCN-IR-NEXT: s_setpc_b64 s[30:31] ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = udiv i64 %x, %y %result = udiv i64 %x, %y
ret i64 %result ret i64 %result
} }
▲ Show 20 Lines • Show All 415 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: s_subb_u32 s9, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s9, 0, 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[16:17], s[8:9], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[16:17], s[8:9], 63
; GCN-IR-NEXT: s_mov_b32 s11, 0 ; GCN-IR-NEXT: s_mov_b32 s11, 0
; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17] ; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17]
; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[16:17], s[8:9], 63 ; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[16:17], s[8:9], 63
; GCN-IR-NEXT: s_xor_b64 s[18:19], s[14:15], -1 ; GCN-IR-NEXT: s_xor_b64 s[18:19], s[14:15], -1
; GCN-IR-NEXT: s_and_b64 s[16:17], s[18:19], s[16:17] ; GCN-IR-NEXT: s_and_b64 s[16:17], s[18:19], s[16:17]
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[16:17] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[16:17]
; GCN-IR-NEXT: s_cbranch_vccz BB7_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB7_5
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s14, s8, 1 ; GCN-IR-NEXT: s_add_u32 s14, s8, 1
; GCN-IR-NEXT: v_mov_b32_e32 v0, s8 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s8
; GCN-IR-NEXT: s_addc_u32 s15, s9, 0 ; GCN-IR-NEXT: s_addc_u32 s15, s9, 0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s9 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s9
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[14:15], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[14:15], v[0:1]
; GCN-IR-NEXT: s_sub_i32 s8, 63, s8 ; GCN-IR-NEXT: s_sub_i32 s8, 63, s8
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[6:7], s8 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[6:7], s8
; GCN-IR-NEXT: s_cbranch_vccz BB7_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB7_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[14:15], s[6:7], s14 ; GCN-IR-NEXT: s_lshr_b64 s[14:15], s[6:7], s14
; GCN-IR-NEXT: s_add_u32 s16, s2, -1 ; GCN-IR-NEXT: s_add_u32 s16, s2, -1
; GCN-IR-NEXT: s_addc_u32 s17, s3, -1 ; GCN-IR-NEXT: s_addc_u32 s17, s3, -1
; GCN-IR-NEXT: s_not_b64 s[0:1], s[10:11] ; GCN-IR-NEXT: s_not_b64 s[0:1], s[10:11]
; GCN-IR-NEXT: s_add_u32 s6, s0, s12 ; GCN-IR-NEXT: s_add_u32 s6, s0, s12
; GCN-IR-NEXT: s_mov_b32 s13, s11 ; GCN-IR-NEXT: s_mov_b32 s13, s11
; GCN-IR-NEXT: s_addc_u32 s7, s1, s11 ; GCN-IR-NEXT: s_addc_u32 s7, s1, s11
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: s_mov_b32 s1, 0 ; GCN-IR-NEXT: s_mov_b32 s1, 0
; GCN-IR-NEXT: BB7_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB7_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[14:15], 1 ; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[14:15], 1
; GCN-IR-NEXT: s_lshr_b32 s0, s9, 31 ; GCN-IR-NEXT: s_lshr_b32 s0, s9, 31
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1
; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[0:1] ; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[0:1]
; GCN-IR-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9] ; GCN-IR-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9]
; GCN-IR-NEXT: s_sub_u32 s0, s16, s12 ; GCN-IR-NEXT: s_sub_u32 s0, s16, s12
; GCN-IR-NEXT: s_subb_u32 s0, s17, s13 ; GCN-IR-NEXT: s_subb_u32 s0, s17, s13
; GCN-IR-NEXT: s_ashr_i32 s10, s0, 31 ; GCN-IR-NEXT: s_ashr_i32 s10, s0, 31
; GCN-IR-NEXT: s_mov_b32 s11, s10 ; GCN-IR-NEXT: s_mov_b32 s11, s10
; GCN-IR-NEXT: s_and_b32 s0, s10, 1 ; GCN-IR-NEXT: s_and_b32 s0, s10, 1
; GCN-IR-NEXT: s_and_b64 s[14:15], s[10:11], s[2:3] ; GCN-IR-NEXT: s_and_b64 s[14:15], s[10:11], s[2:3]
; GCN-IR-NEXT: s_sub_u32 s14, s12, s14 ; GCN-IR-NEXT: s_sub_u32 s14, s12, s14
; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
; GCN-IR-NEXT: s_subb_u32 s15, s13, s15 ; GCN-IR-NEXT: s_subb_u32 s15, s13, s15
; GCN-IR-NEXT: v_mov_b32_e32 v1, s7 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s7
; GCN-IR-NEXT: s_add_u32 s6, s6, 1 ; GCN-IR-NEXT: s_add_u32 s6, s6, 1
; GCN-IR-NEXT: s_addc_u32 s7, s7, 0 ; GCN-IR-NEXT: s_addc_u32 s7, s7, 0
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[6:7], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[6:7], v[0:1]
; GCN-IR-NEXT: s_mov_b64 s[10:11], s[0:1] ; GCN-IR-NEXT: s_mov_b64 s[10:11], s[0:1]
; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_cbranch_vccz BB7_3 ; GCN-IR-NEXT: s_cbranch_vccz .LBB7_3
; GCN-IR-NEXT: BB7_4: ; %Flow3 ; GCN-IR-NEXT: .LBB7_4: ; %Flow3
; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[8:9], 1 ; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[8:9], 1
; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3] ; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
; GCN-IR-NEXT: v_mov_b32_e32 v0, s0 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s1 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s1
; GCN-IR-NEXT: s_branch BB7_6 ; GCN-IR-NEXT: s_branch .LBB7_6
; GCN-IR-NEXT: BB7_5: ; GCN-IR-NEXT: .LBB7_5:
; GCN-IR-NEXT: v_mov_b32_e32 v0, s7 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s7
; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[14:15] ; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[14:15]
; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[14:15] ; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[14:15]
; GCN-IR-NEXT: BB7_6: ; %udiv-end ; GCN-IR-NEXT: .LBB7_6: ; %udiv-end
; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: s_mov_b32 s6, -1
; GCN-IR-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:4 ; GCN-IR-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:4
; GCN-IR-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GCN-IR-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GCN-IR-NEXT: s_endpgm ; GCN-IR-NEXT: s_endpgm
%1 = lshr i48 %x, 24 %1 = lshr i48 %x, 24
%2 = lshr i48 %y, 24 %2 = lshr i48 %y, 24
%result = udiv i48 %1, %2 %result = udiv i48 %1, %2
▲ Show 20 Lines • Show All 121 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[2:3], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[12:13], s[8:9], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[12:13], s[8:9], 63
; GCN-IR-NEXT: s_mov_b64 s[4:5], 0 ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0
; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13]
; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[12:13], s[8:9], 63 ; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[12:13], s[8:9], 63
; GCN-IR-NEXT: s_xor_b64 s[14:15], s[10:11], -1 ; GCN-IR-NEXT: s_xor_b64 s[14:15], s[10:11], -1
; GCN-IR-NEXT: s_and_b64 s[12:13], s[14:15], s[12:13] ; GCN-IR-NEXT: s_and_b64 s[12:13], s[14:15], s[12:13]
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[12:13] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[12:13]
; GCN-IR-NEXT: s_cbranch_vccz BB8_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB8_5
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s10, s8, 1 ; GCN-IR-NEXT: s_add_u32 s10, s8, 1
; GCN-IR-NEXT: v_mov_b32_e32 v0, s8 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s8
; GCN-IR-NEXT: s_addc_u32 s11, s9, 0 ; GCN-IR-NEXT: s_addc_u32 s11, s9, 0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s9 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s9
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
; GCN-IR-NEXT: s_sub_i32 s7, 63, s8 ; GCN-IR-NEXT: s_sub_i32 s7, 63, s8
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_lshl_b64 s[8:9], 24, s7 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], 24, s7
; GCN-IR-NEXT: s_cbranch_vccz BB8_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB8_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[12:13], 24, s10 ; GCN-IR-NEXT: s_lshr_b64 s[12:13], 24, s10
; GCN-IR-NEXT: s_add_u32 s14, s2, -1 ; GCN-IR-NEXT: s_add_u32 s14, s2, -1
; GCN-IR-NEXT: s_addc_u32 s15, s3, -1 ; GCN-IR-NEXT: s_addc_u32 s15, s3, -1
; GCN-IR-NEXT: s_sub_u32 s6, 58, s6 ; GCN-IR-NEXT: s_sub_u32 s6, 58, s6
; GCN-IR-NEXT: s_subb_u32 s7, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s7, 0, 0
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: s_mov_b32 s5, 0 ; GCN-IR-NEXT: s_mov_b32 s5, 0
; GCN-IR-NEXT: BB8_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB8_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1 ; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1
; GCN-IR-NEXT: s_lshr_b32 s4, s9, 31 ; GCN-IR-NEXT: s_lshr_b32 s4, s9, 31
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1
; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[4:5] ; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[4:5]
; GCN-IR-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9] ; GCN-IR-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9]
; GCN-IR-NEXT: s_sub_u32 s4, s14, s12 ; GCN-IR-NEXT: s_sub_u32 s4, s14, s12
; GCN-IR-NEXT: s_subb_u32 s4, s15, s13 ; GCN-IR-NEXT: s_subb_u32 s4, s15, s13
; GCN-IR-NEXT: s_ashr_i32 s10, s4, 31 ; GCN-IR-NEXT: s_ashr_i32 s10, s4, 31
; GCN-IR-NEXT: s_mov_b32 s11, s10 ; GCN-IR-NEXT: s_mov_b32 s11, s10
; GCN-IR-NEXT: s_and_b32 s4, s10, 1 ; GCN-IR-NEXT: s_and_b32 s4, s10, 1
; GCN-IR-NEXT: s_and_b64 s[16:17], s[10:11], s[2:3] ; GCN-IR-NEXT: s_and_b64 s[16:17], s[10:11], s[2:3]
; GCN-IR-NEXT: s_sub_u32 s12, s12, s16 ; GCN-IR-NEXT: s_sub_u32 s12, s12, s16
; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
; GCN-IR-NEXT: s_subb_u32 s13, s13, s17 ; GCN-IR-NEXT: s_subb_u32 s13, s13, s17
; GCN-IR-NEXT: v_mov_b32_e32 v1, s7 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s7
; GCN-IR-NEXT: s_add_u32 s6, s6, 1 ; GCN-IR-NEXT: s_add_u32 s6, s6, 1
; GCN-IR-NEXT: s_addc_u32 s7, s7, 0 ; GCN-IR-NEXT: s_addc_u32 s7, s7, 0
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[6:7], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[6:7], v[0:1]
; GCN-IR-NEXT: s_mov_b64 s[10:11], s[4:5] ; GCN-IR-NEXT: s_mov_b64 s[10:11], s[4:5]
; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_cbranch_vccz BB8_3 ; GCN-IR-NEXT: s_cbranch_vccz .LBB8_3
; GCN-IR-NEXT: BB8_4: ; %Flow5 ; GCN-IR-NEXT: .LBB8_4: ; %Flow5
; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[8:9], 1 ; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[8:9], 1
; GCN-IR-NEXT: s_or_b64 s[2:3], s[4:5], s[2:3] ; GCN-IR-NEXT: s_or_b64 s[2:3], s[4:5], s[2:3]
; GCN-IR-NEXT: v_mov_b32_e32 v0, s2 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s2
; GCN-IR-NEXT: v_mov_b32_e32 v1, s3 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s3
; GCN-IR-NEXT: s_branch BB8_6 ; GCN-IR-NEXT: s_branch .LBB8_6
; GCN-IR-NEXT: BB8_5: ; GCN-IR-NEXT: .LBB8_5:
; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
; GCN-IR-NEXT: v_cndmask_b32_e64 v0, 24, 0, s[10:11] ; GCN-IR-NEXT: v_cndmask_b32_e64 v0, 24, 0, s[10:11]
; GCN-IR-NEXT: BB8_6: ; %udiv-end ; GCN-IR-NEXT: .LBB8_6: ; %udiv-end
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: s_mov_b32 s2, -1
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-IR-NEXT: s_endpgm ; GCN-IR-NEXT: s_endpgm
%result = udiv i64 24, %x %result = udiv i64 24, %x
store i64 %result, i64 addrspace(1)* %out store i64 %result, i64 addrspace(1)* %out
ret void ret void
} }
▲ Show 20 Lines • Show All 115 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5]
; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1
; GCN-IR-NEXT: v_mov_b32_e32 v3, v7 ; GCN-IR-NEXT: v_mov_b32_e32 v3, v7
; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB9_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB9_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v4 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v4
; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[8:9], v[4:5] ; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[8:9], v[4:5]
; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[8:9], v2 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[8:9], v2
; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB9_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB9_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0
; GCN-IR-NEXT: s_mov_b64 s[4:5], 0x8000 ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0x8000
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc
; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[4:5], v8 ; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[4:5], v8
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 47, v6 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 47, v6
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_subb_u32_e32 v7, vcc, 0, v7, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v7, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: BB9_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB9_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 ; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4 ; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v12, v8 ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v12, v8
; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, v13, v9, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, v13, v9, vcc
; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2 ; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2
; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4
; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10 ; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10
; GCN-IR-NEXT: v_and_b32_e32 v14, v10, v1 ; GCN-IR-NEXT: v_and_b32_e32 v14, v10, v1
; GCN-IR-NEXT: v_and_b32_e32 v15, v10, v0 ; GCN-IR-NEXT: v_and_b32_e32 v15, v10, v0
; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v6 ; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v6
; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3 ; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3
; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v7, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[6:7] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[6:7]
; GCN-IR-NEXT: v_mov_b32_e32 v6, v10 ; GCN-IR-NEXT: v_mov_b32_e32 v6, v10
; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v8, v15 ; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v8, v15
; GCN-IR-NEXT: v_mov_b32_e32 v7, v11 ; GCN-IR-NEXT: v_mov_b32_e32 v7, v11
; GCN-IR-NEXT: v_mov_b32_e32 v11, v5 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v5
; GCN-IR-NEXT: v_subb_u32_e64 v9, s[4:5], v9, v14, s[4:5] ; GCN-IR-NEXT: v_subb_u32_e64 v9, s[4:5], v9, v14, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v10, v4 ; GCN-IR-NEXT: v_mov_b32_e32 v10, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execnz BB9_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB9_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: BB9_5: ; %Flow3 ; GCN-IR-NEXT: .LBB9_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[2:3], 1
; GCN-IR-NEXT: v_or_b32_e32 v3, v5, v1 ; GCN-IR-NEXT: v_or_b32_e32 v3, v5, v1
; GCN-IR-NEXT: v_or_b32_e32 v2, v4, v0 ; GCN-IR-NEXT: v_or_b32_e32 v2, v4, v0
; GCN-IR-NEXT: BB9_6: ; %Flow4 ; GCN-IR-NEXT: .LBB9_6: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_mov_b32_e32 v0, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v0, v2
; GCN-IR-NEXT: v_mov_b32_e32 v1, v3 ; GCN-IR-NEXT: v_mov_b32_e32 v1, v3
; GCN-IR-NEXT: s_setpc_b64 s[30:31] ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = udiv i64 32768, %x %result = udiv i64 32768, %x
ret i64 %result ret i64 %result
} }
Show All 18 Lines
; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[4:5] ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[4:5]
; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5]
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
; GCN-IR-NEXT: v_cndmask_b32_e64 v2, v1, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v2, v1, 0, s[4:5]
; GCN-IR-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5]
; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB10_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB10_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v4 ; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v4
; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v5, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v4 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v4
; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[7:8], v[4:5] ; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[7:8], v[4:5]
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2
; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB10_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB10_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_lshr_b64 v[7:8], v[0:1], v7 ; GCN-IR-NEXT: v_lshr_b64 v[7:8], v[0:1], v7
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffcf, v6 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffcf, v6
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: v_addc_u32_e64 v1, s[4:5], 0, -1, vcc ; GCN-IR-NEXT: v_addc_u32_e64 v1, s[4:5], 0, -1, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff ; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff
; GCN-IR-NEXT: BB10_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB10_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1 ; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
; GCN-IR-NEXT: v_or_b32_e32 v6, v7, v4 ; GCN-IR-NEXT: v_or_b32_e32 v6, v7, v4
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, s12, v6 ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, s12, v6
; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v8, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v8, vcc
; GCN-IR-NEXT: v_or_b32_e32 v2, v9, v2 ; GCN-IR-NEXT: v_or_b32_e32 v2, v9, v2
; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v0
; GCN-IR-NEXT: v_or_b32_e32 v3, v10, v3 ; GCN-IR-NEXT: v_or_b32_e32 v3, v10, v3
; GCN-IR-NEXT: v_ashrrev_i32_e32 v7, 31, v4 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v7, 31, v4
; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v1, vcc
; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v7 ; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v7
; GCN-IR-NEXT: v_and_b32_e32 v7, 0x8000, v7 ; GCN-IR-NEXT: v_and_b32_e32 v7, 0x8000, v7
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[0:1]
; GCN-IR-NEXT: v_mov_b32_e32 v0, v9 ; GCN-IR-NEXT: v_mov_b32_e32 v0, v9
; GCN-IR-NEXT: v_sub_i32_e64 v7, s[4:5], v6, v7 ; GCN-IR-NEXT: v_sub_i32_e64 v7, s[4:5], v6, v7
; GCN-IR-NEXT: v_mov_b32_e32 v1, v10 ; GCN-IR-NEXT: v_mov_b32_e32 v1, v10
; GCN-IR-NEXT: v_mov_b32_e32 v10, v5 ; GCN-IR-NEXT: v_mov_b32_e32 v10, v5
; GCN-IR-NEXT: v_subbrev_u32_e64 v8, s[4:5], 0, v8, s[4:5] ; GCN-IR-NEXT: v_subbrev_u32_e64 v8, s[4:5], 0, v8, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v9, v4 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execnz BB10_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB10_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: BB10_5: ; %Flow3 ; GCN-IR-NEXT: .LBB10_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[2:3], 1
; GCN-IR-NEXT: v_or_b32_e32 v2, v5, v1 ; GCN-IR-NEXT: v_or_b32_e32 v2, v5, v1
; GCN-IR-NEXT: v_or_b32_e32 v3, v4, v0 ; GCN-IR-NEXT: v_or_b32_e32 v3, v4, v0
; GCN-IR-NEXT: BB10_6: ; %Flow4 ; GCN-IR-NEXT: .LBB10_6: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_mov_b32_e32 v0, v3 ; GCN-IR-NEXT: v_mov_b32_e32 v0, v3
; GCN-IR-NEXT: v_mov_b32_e32 v1, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v1, v2
; GCN-IR-NEXT: s_setpc_b64 s[30:31] ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = udiv i64 %x, 32768 %result = udiv i64 %x, 32768
ret i64 %result ret i64 %result
} }
▲ Show 20 Lines • Show All 116 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[2:3], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[12:13], s[6:7], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[12:13], s[6:7], 63
; GCN-IR-NEXT: s_mov_b64 s[4:5], 0 ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0
; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13]
; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[12:13], s[6:7], 63 ; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[12:13], s[6:7], 63
; GCN-IR-NEXT: s_xor_b64 s[14:15], s[10:11], -1 ; GCN-IR-NEXT: s_xor_b64 s[14:15], s[10:11], -1
; GCN-IR-NEXT: s_and_b64 s[12:13], s[14:15], s[12:13] ; GCN-IR-NEXT: s_and_b64 s[12:13], s[14:15], s[12:13]
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[12:13] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[12:13]
; GCN-IR-NEXT: s_cbranch_vccz BB11_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB11_5
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s10, s6, 1 ; GCN-IR-NEXT: s_add_u32 s10, s6, 1
; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
; GCN-IR-NEXT: s_addc_u32 s11, s7, 0 ; GCN-IR-NEXT: s_addc_u32 s11, s7, 0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s7 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s7
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
; GCN-IR-NEXT: s_sub_i32 s6, 63, s6 ; GCN-IR-NEXT: s_sub_i32 s6, 63, s6
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[2:3], s6 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[2:3], s6
; GCN-IR-NEXT: s_cbranch_vccz BB11_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB11_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[10:11], s[2:3], s10 ; GCN-IR-NEXT: s_lshr_b64 s[10:11], s[2:3], s10
; GCN-IR-NEXT: s_add_u32 s2, s8, 0xffffffc4 ; GCN-IR-NEXT: s_add_u32 s2, s8, 0xffffffc4
; GCN-IR-NEXT: s_addc_u32 s3, 0, -1 ; GCN-IR-NEXT: s_addc_u32 s3, 0, -1
; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: s_mov_b32 s5, 0 ; GCN-IR-NEXT: s_mov_b32 s5, 0
; GCN-IR-NEXT: BB11_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB11_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1
; GCN-IR-NEXT: s_lshr_b32 s4, s7, 31 ; GCN-IR-NEXT: s_lshr_b32 s4, s7, 31
; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[4:5] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[4:5]
; GCN-IR-NEXT: s_or_b64 s[6:7], s[8:9], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[6:7], s[8:9], s[6:7]
; GCN-IR-NEXT: s_sub_u32 s4, 23, s10 ; GCN-IR-NEXT: s_sub_u32 s4, 23, s10
; GCN-IR-NEXT: s_subb_u32 s4, 0, s11 ; GCN-IR-NEXT: s_subb_u32 s4, 0, s11
; GCN-IR-NEXT: s_ashr_i32 s8, s4, 31 ; GCN-IR-NEXT: s_ashr_i32 s8, s4, 31
; GCN-IR-NEXT: s_and_b32 s4, s8, 1 ; GCN-IR-NEXT: s_and_b32 s4, s8, 1
; GCN-IR-NEXT: s_and_b32 s8, s8, 24 ; GCN-IR-NEXT: s_and_b32 s8, s8, 24
; GCN-IR-NEXT: s_sub_u32 s10, s10, s8 ; GCN-IR-NEXT: s_sub_u32 s10, s10, s8
; GCN-IR-NEXT: v_mov_b32_e32 v0, s2 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s2
; GCN-IR-NEXT: s_subb_u32 s11, s11, 0 ; GCN-IR-NEXT: s_subb_u32 s11, s11, 0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s3 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s3
; GCN-IR-NEXT: s_add_u32 s2, s2, 1 ; GCN-IR-NEXT: s_add_u32 s2, s2, 1
; GCN-IR-NEXT: s_addc_u32 s3, s3, 0 ; GCN-IR-NEXT: s_addc_u32 s3, s3, 0
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1]
; GCN-IR-NEXT: s_mov_b64 s[8:9], s[4:5] ; GCN-IR-NEXT: s_mov_b64 s[8:9], s[4:5]
; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_cbranch_vccz BB11_3 ; GCN-IR-NEXT: s_cbranch_vccz .LBB11_3
; GCN-IR-NEXT: BB11_4: ; %Flow5 ; GCN-IR-NEXT: .LBB11_4: ; %Flow5
; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[6:7], 1 ; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[6:7], 1
; GCN-IR-NEXT: s_or_b64 s[2:3], s[4:5], s[2:3] ; GCN-IR-NEXT: s_or_b64 s[2:3], s[4:5], s[2:3]
; GCN-IR-NEXT: v_mov_b32_e32 v0, s2 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s2
; GCN-IR-NEXT: v_mov_b32_e32 v1, s3 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s3
; GCN-IR-NEXT: s_branch BB11_6 ; GCN-IR-NEXT: s_branch .LBB11_6
; GCN-IR-NEXT: BB11_5: ; GCN-IR-NEXT: .LBB11_5:
; GCN-IR-NEXT: v_mov_b32_e32 v0, s3 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s3
; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[10:11] ; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v0, s2 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s2
; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[10:11] ; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[10:11]
; GCN-IR-NEXT: BB11_6: ; %udiv-end ; GCN-IR-NEXT: .LBB11_6: ; %udiv-end
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: s_mov_b32 s2, -1
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-IR-NEXT: s_endpgm ; GCN-IR-NEXT: s_endpgm
%result = udiv i64 %x, 24 %result = udiv i64 %x, 24
store i64 %result, i64 addrspace(1)* %out store i64 %result, i64 addrspace(1)* %out
ret void ret void
} }
▲ Show 20 Lines • Show All 110 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[4:5] ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[4:5]
; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5]
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
; GCN-IR-NEXT: v_cndmask_b32_e64 v2, v1, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v2, v1, 0, s[4:5]
; GCN-IR-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5]
; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB12_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB12_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v4 ; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v4
; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v5, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v4 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v4
; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[7:8], v[4:5] ; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[7:8], v[4:5]
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2
; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB12_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB12_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_lshr_b64 v[7:8], v[0:1], v7 ; GCN-IR-NEXT: v_lshr_b64 v[7:8], v[0:1], v7
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc4, v6 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc4, v6
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: v_addc_u32_e64 v1, s[4:5], 0, -1, vcc ; GCN-IR-NEXT: v_addc_u32_e64 v1, s[4:5], 0, -1, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: BB12_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB12_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1 ; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
; GCN-IR-NEXT: v_or_b32_e32 v6, v7, v4 ; GCN-IR-NEXT: v_or_b32_e32 v6, v7, v4
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 23, v6 ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 23, v6
; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v8, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v8, vcc
; GCN-IR-NEXT: v_or_b32_e32 v2, v9, v2 ; GCN-IR-NEXT: v_or_b32_e32 v2, v9, v2
; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v0
; GCN-IR-NEXT: v_or_b32_e32 v3, v10, v3 ; GCN-IR-NEXT: v_or_b32_e32 v3, v10, v3
; GCN-IR-NEXT: v_ashrrev_i32_e32 v7, 31, v4 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v7, 31, v4
; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v1, vcc
; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v7 ; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v7
; GCN-IR-NEXT: v_and_b32_e32 v7, 24, v7 ; GCN-IR-NEXT: v_and_b32_e32 v7, 24, v7
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[0:1]
; GCN-IR-NEXT: v_mov_b32_e32 v0, v9 ; GCN-IR-NEXT: v_mov_b32_e32 v0, v9
; GCN-IR-NEXT: v_sub_i32_e64 v7, s[4:5], v6, v7 ; GCN-IR-NEXT: v_sub_i32_e64 v7, s[4:5], v6, v7
; GCN-IR-NEXT: v_mov_b32_e32 v1, v10 ; GCN-IR-NEXT: v_mov_b32_e32 v1, v10
; GCN-IR-NEXT: v_mov_b32_e32 v10, v5 ; GCN-IR-NEXT: v_mov_b32_e32 v10, v5
; GCN-IR-NEXT: v_subbrev_u32_e64 v8, s[4:5], 0, v8, s[4:5] ; GCN-IR-NEXT: v_subbrev_u32_e64 v8, s[4:5], 0, v8, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v9, v4 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execnz BB12_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB12_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: BB12_5: ; %Flow3 ; GCN-IR-NEXT: .LBB12_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[2:3], 1
; GCN-IR-NEXT: v_or_b32_e32 v2, v5, v1 ; GCN-IR-NEXT: v_or_b32_e32 v2, v5, v1
; GCN-IR-NEXT: v_or_b32_e32 v3, v4, v0 ; GCN-IR-NEXT: v_or_b32_e32 v3, v4, v0
; GCN-IR-NEXT: BB12_6: ; %Flow4 ; GCN-IR-NEXT: .LBB12_6: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_mov_b32_e32 v0, v3 ; GCN-IR-NEXT: v_mov_b32_e32 v0, v3
; GCN-IR-NEXT: v_mov_b32_e32 v1, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v1, v2
; GCN-IR-NEXT: s_setpc_b64 s[30:31] ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = udiv i64 %x, 24 %result = udiv i64 %x, 24
ret i64 %result ret i64 %result
} }
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llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -march=amdgcn -verify-machineinstrs -early-live-intervals < %s | FileCheck %s ; RUN: llc -march=amdgcn -verify-machineinstrs -early-live-intervals < %s | FileCheck %s
; We may have subregister live ranges that are undefined on some paths. The ; We may have subregister live ranges that are undefined on some paths. The
; verifier should not complain about this. ; verifier should not complain about this.
define amdgpu_kernel void @func() #0 { define amdgpu_kernel void @func() #0 {
; CHECK-LABEL: func: ; CHECK-LABEL: func:
; CHECK: ; %bb.0: ; %B0 ; CHECK: ; %bb.0: ; %B0
; CHECK-NEXT: s_mov_b32 s0, 0 ; CHECK-NEXT: s_mov_b32 s0, 0
; CHECK-NEXT: s_cbranch_scc1 BB0_2 ; CHECK-NEXT: s_cbranch_scc1 .LBB0_2
; CHECK-NEXT: ; %bb.1: ; %B30.1 ; CHECK-NEXT: ; %bb.1: ; %B30.1
; CHECK-NEXT: s_mov_b32 s0, 0x7fc00000 ; CHECK-NEXT: s_mov_b32 s0, 0x7fc00000
; CHECK-NEXT: BB0_2: ; %B30.2 ; CHECK-NEXT: .LBB0_2: ; %B30.2
; CHECK-NEXT: v_mov_b32_e32 v0, s0 ; CHECK-NEXT: v_mov_b32_e32 v0, s0
; CHECK-NEXT: s_mov_b32 m0, -1 ; CHECK-NEXT: s_mov_b32 m0, -1
; CHECK-NEXT: ds_write_b32 v0, v0 ; CHECK-NEXT: ds_write_b32 v0, v0
; CHECK-NEXT: s_endpgm ; CHECK-NEXT: s_endpgm
B0: B0:
br i1 undef, label %B1, label %B2 br i1 undef, label %B1, label %B2
B1: B1:
Show All 27 Lines
; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: v_mov_b32_e32 v2, 0x7fc00000 ; CHECK-NEXT: v_mov_b32_e32 v2, 0x7fc00000
; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], 0 ; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], 0
; CHECK-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; CHECK-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
; CHECK-NEXT: s_waitcnt expcnt(0) ; CHECK-NEXT: s_waitcnt expcnt(0)
; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; CHECK-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v1 ; CHECK-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v1
; CHECK-NEXT: BB1_1: ; %bb9 ; CHECK-NEXT: .LBB1_1: ; %bb9
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: s_and_b64 vcc, exec, s[0:1] ; CHECK-NEXT: s_and_b64 vcc, exec, s[0:1]
; CHECK-NEXT: s_cbranch_vccnz BB1_1 ; CHECK-NEXT: s_cbranch_vccnz .LBB1_1
; CHECK-NEXT: ; %bb.2: ; %bb11 ; CHECK-NEXT: ; %bb.2: ; %bb11
; CHECK-NEXT: s_mov_b32 s3, 0xf000 ; CHECK-NEXT: s_mov_b32 s3, 0xf000
; CHECK-NEXT: s_mov_b32 s2, -1 ; CHECK-NEXT: s_mov_b32 s2, -1
; CHECK-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; CHECK-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; CHECK-NEXT: ; return to shader part epilog ; CHECK-NEXT: ; return to shader part epilog
bb: bb:
%tmp = load volatile i32, i32 addrspace(1)* undef, align 4 %tmp = load volatile i32, i32 addrspace(1)* undef, align 4
▲ Show 20 Lines • Show All 59 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/uniform-cfg.ll

; RUN: llc -march=amdgcn -mcpu=verde -amdgpu-early-ifcvt=0 -machine-sink-split-probability-threshold=0 -structurizecfg-skip-uniform-regions -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mcpu=verde -amdgpu-early-ifcvt=0 -machine-sink-split-probability-threshold=0 -structurizecfg-skip-uniform-regions -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-early-ifcvt=0 -machine-sink-split-probability-threshold=0 -structurizecfg-skip-uniform-regions -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-early-ifcvt=0 -machine-sink-split-probability-threshold=0 -structurizecfg-skip-uniform-regions -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
; GCN-LABEL: {{^}}uniform_if_scc: ; GCN-LABEL: {{^}}uniform_if_scc:
; GCN-DAG: s_cmp_eq_u32 s{{[0-9]+}}, 0 ; GCN-DAG: s_cmp_eq_u32 s{{[0-9]+}}, 0
; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0 ; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0
; GCN: s_cbranch_scc1 [[IF_LABEL:[0-9_A-Za-z]+]] ; GCN: s_cbranch_scc1 [[IF_LABEL:.L[0-9_A-Za-z]+]]
; Fall-through to the else ; Fall-through to the else
; GCN: s_mov_b32 [[S_VAL]], 1 ; GCN: s_mov_b32 [[S_VAL]], 1
; GCN: [[IF_LABEL]]: ; GCN: [[IF_LABEL]]:
; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]] ; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]]
; GCN: buffer_store_dword [[V_VAL]] ; GCN: buffer_store_dword [[V_VAL]]
define amdgpu_kernel void @uniform_if_scc(i32 %cond, i32 addrspace(1)* %out) { define amdgpu_kernel void @uniform_if_scc(i32 %cond, i32 addrspace(1)* %out) {
Show All 11 Linesdone:
%value = phi i32 [0, %if], [1, %else] %value = phi i32 [0, %if], [1, %else]
store i32 %value, i32 addrspace(1)* %out store i32 %value, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}uniform_if_vcc: ; GCN-LABEL: {{^}}uniform_if_vcc:
; GCN-DAG: v_cmp_eq_f32_e64 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 0{{$}} ; GCN-DAG: v_cmp_eq_f32_e64 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 0{{$}}
; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0 ; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0
; GCN: s_cbranch_vccnz [[IF_LABEL:[0-9_A-Za-z]+]] ; GCN: s_cbranch_vccnz [[IF_LABEL:.L[0-9_A-Za-z]+]]
; Fall-through to the else ; Fall-through to the else
; GCN: s_mov_b32 [[S_VAL]], 1 ; GCN: s_mov_b32 [[S_VAL]], 1
; GCN: [[IF_LABEL]]: ; GCN: [[IF_LABEL]]:
; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]] ; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]]
; GCN: buffer_store_dword [[V_VAL]] ; GCN: buffer_store_dword [[V_VAL]]
define amdgpu_kernel void @uniform_if_vcc(float %cond, i32 addrspace(1)* %out) { define amdgpu_kernel void @uniform_if_vcc(float %cond, i32 addrspace(1)* %out) {
Show All 11 Linesdone:
%value = phi i32 [0, %if], [1, %else] %value = phi i32 [0, %if], [1, %else]
store i32 %value, i32 addrspace(1)* %out store i32 %value, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}uniform_if_swap_br_targets_scc: ; GCN-LABEL: {{^}}uniform_if_swap_br_targets_scc:
; GCN-DAG: s_cmp_lg_u32 s{{[0-9]+}}, 0 ; GCN-DAG: s_cmp_lg_u32 s{{[0-9]+}}, 0
; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0 ; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0
; GCN: s_cbranch_scc1 [[IF_LABEL:[0-9_A-Za-z]+]] ; GCN: s_cbranch_scc1 [[IF_LABEL:.L[0-9_A-Za-z]+]]
; Fall-through to the else ; Fall-through to the else
; GCN: s_mov_b32 [[S_VAL]], 1 ; GCN: s_mov_b32 [[S_VAL]], 1
; GCN: [[IF_LABEL]]: ; GCN: [[IF_LABEL]]:
; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]] ; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]]
; GCN: buffer_store_dword [[V_VAL]] ; GCN: buffer_store_dword [[V_VAL]]
define amdgpu_kernel void @uniform_if_swap_br_targets_scc(i32 %cond, i32 addrspace(1)* %out) { define amdgpu_kernel void @uniform_if_swap_br_targets_scc(i32 %cond, i32 addrspace(1)* %out) {
Show All 11 Linesdone:
%value = phi i32 [0, %if], [1, %else] %value = phi i32 [0, %if], [1, %else]
store i32 %value, i32 addrspace(1)* %out store i32 %value, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}uniform_if_swap_br_targets_vcc: ; GCN-LABEL: {{^}}uniform_if_swap_br_targets_vcc:
; GCN-DAG: v_cmp_neq_f32_e64 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 0{{$}} ; GCN-DAG: v_cmp_neq_f32_e64 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 0{{$}}
; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0 ; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0
; GCN: s_cbranch_vccnz [[IF_LABEL:[0-9_A-Za-z]+]] ; GCN: s_cbranch_vccnz [[IF_LABEL:.L[0-9_A-Za-z]+]]
; Fall-through to the else ; Fall-through to the else
; GCN: s_mov_b32 [[S_VAL]], 1 ; GCN: s_mov_b32 [[S_VAL]], 1
; GCN: [[IF_LABEL]]: ; GCN: [[IF_LABEL]]:
; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]] ; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]]
; GCN: buffer_store_dword [[V_VAL]] ; GCN: buffer_store_dword [[V_VAL]]
define amdgpu_kernel void @uniform_if_swap_br_targets_vcc(float %cond, i32 addrspace(1)* %out) { define amdgpu_kernel void @uniform_if_swap_br_targets_vcc(float %cond, i32 addrspace(1)* %out) {
Show All 14 Lines
} }
; GCN-LABEL: {{^}}uniform_if_move_valu: ; GCN-LABEL: {{^}}uniform_if_move_valu:
; GCN: v_add_f32_e32 [[CMP:v[0-9]+]] ; GCN: v_add_f32_e32 [[CMP:v[0-9]+]]
; Using a floating-point value in an integer compare will cause the compare to ; Using a floating-point value in an integer compare will cause the compare to
; be selected for the SALU and then later moved to the VALU. ; be selected for the SALU and then later moved to the VALU.
; GCN: v_cmp_ne_u32_e32 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], 5, [[CMP]] ; GCN: v_cmp_ne_u32_e32 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], 5, [[CMP]]
; GCN: s_and_b64 vcc, exec, [[COND]] ; GCN: s_and_b64 vcc, exec, [[COND]]
; GCN: s_cbranch_vccnz [[ENDIF_LABEL:[0-9_A-Za-z]+]] ; GCN: s_cbranch_vccnz [[ENDIF_LABEL:.L[0-9_A-Za-z]+]]
; GCN: buffer_store_dword ; GCN: buffer_store_dword
; GCN: [[ENDIF_LABEL]]: ; GCN: [[ENDIF_LABEL]]:
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @uniform_if_move_valu(i32 addrspace(1)* %out, float %a) { define amdgpu_kernel void @uniform_if_move_valu(i32 addrspace(1)* %out, float %a) {
entry: entry:
%a.0 = fadd float %a, 10.0 %a.0 = fadd float %a, 10.0
%cond = bitcast float %a.0 to i32 %cond = bitcast float %a.0 to i32
%cmp = icmp eq i32 %cond, 5 %cmp = icmp eq i32 %cond, 5
br i1 %cmp, label %if, label %endif br i1 %cmp, label %if, label %endif
if: if:
store i32 0, i32 addrspace(1)* %out store i32 0, i32 addrspace(1)* %out
br label %endif br label %endif
endif: endif:
ret void ret void
} }
; GCN-LABEL: {{^}}uniform_if_move_valu_commute: ; GCN-LABEL: {{^}}uniform_if_move_valu_commute:
; GCN: v_add_f32_e32 [[CMP:v[0-9]+]] ; GCN: v_add_f32_e32 [[CMP:v[0-9]+]]
; Using a floating-point value in an integer compare will cause the compare to ; Using a floating-point value in an integer compare will cause the compare to
; be selected for the SALU and then later moved to the VALU. ; be selected for the SALU and then later moved to the VALU.
; GCN: v_cmp_gt_u32_e32 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], 6, [[CMP]] ; GCN: v_cmp_gt_u32_e32 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], 6, [[CMP]]
; GCN: s_and_b64 vcc, exec, [[COND]] ; GCN: s_and_b64 vcc, exec, [[COND]]
; GCN: s_cbranch_vccnz [[ENDIF_LABEL:[0-9_A-Za-z]+]] ; GCN: s_cbranch_vccnz [[ENDIF_LABEL:.L[0-9_A-Za-z]+]]
; GCN: buffer_store_dword ; GCN: buffer_store_dword
; GCN: [[ENDIF_LABEL]]: ; GCN: [[ENDIF_LABEL]]:
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @uniform_if_move_valu_commute(i32 addrspace(1)* %out, float %a) { define amdgpu_kernel void @uniform_if_move_valu_commute(i32 addrspace(1)* %out, float %a) {
entry: entry:
%a.0 = fadd float %a, 10.0 %a.0 = fadd float %a, 10.0
%cond = bitcast float %a.0 to i32 %cond = bitcast float %a.0 to i32
%cmp = icmp ugt i32 %cond, 5 %cmp = icmp ugt i32 %cond, 5
br i1 %cmp, label %if, label %endif br i1 %cmp, label %if, label %endif
if: if:
store i32 0, i32 addrspace(1)* %out store i32 0, i32 addrspace(1)* %out
br label %endif br label %endif
endif: endif:
ret void ret void
} }
; GCN-LABEL: {{^}}uniform_if_else_ret: ; GCN-LABEL: {{^}}uniform_if_else_ret:
; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 0 ; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 0
; GCN: s_cbranch_scc0 [[IF_LABEL:[0-9_A-Za-z]+]] ; GCN: s_cbranch_scc0 [[IF_LABEL:.L[0-9_A-Za-z]+]]
; GCN: v_mov_b32_e32 [[TWO:v[0-9]+]], 2 ; GCN: v_mov_b32_e32 [[TWO:v[0-9]+]], 2
; GCN: buffer_store_dword [[TWO]] ; GCN: buffer_store_dword [[TWO]]
; GCN: s_endpgm ; GCN: s_endpgm
; GCN: {{^}}[[IF_LABEL]]: ; GCN: {{^}}[[IF_LABEL]]:
; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1 ; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
; GCN: buffer_store_dword [[ONE]] ; GCN: buffer_store_dword [[ONE]]
Show All 12 Linesif.else: ; preds = %entry
br label %if.end br label %if.end
if.end: ; preds = %if.else, %if.then if.end: ; preds = %if.else, %if.then
ret void ret void
} }
; GCN-LABEL: {{^}}uniform_if_else: ; GCN-LABEL: {{^}}uniform_if_else:
; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 0 ; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 0
; GCN: s_cbranch_scc0 [[IF_LABEL:[0-9_A-Za-z]+]] ; GCN: s_cbranch_scc0 [[IF_LABEL:.L[0-9_A-Za-z]+]]
; GCN: v_mov_b32_e32 [[IMM_REG:v[0-9]+]], 2 ; GCN: v_mov_b32_e32 [[IMM_REG:v[0-9]+]], 2
; GCN: s_branch [[ENDIF_LABEL:[0-9_A-Za-z]+]] ; GCN: s_branch [[ENDIF_LABEL:.L[0-9_A-Za-z]+]]
; GCN: [[IF_LABEL]]: ; GCN: [[IF_LABEL]]:
; GCN-NEXT: v_mov_b32_e32 [[IMM_REG]], 1 ; GCN-NEXT: v_mov_b32_e32 [[IMM_REG]], 1
; GCN-NEXT: [[ENDIF_LABEL]]: ; GCN-NEXT: [[ENDIF_LABEL]]:
; GCN: buffer_store_dword [[IMM_REG]] ; GCN: buffer_store_dword [[IMM_REG]]
; GCN: v_mov_b32_e32 [[THREE:v[0-9]+]], 3 ; GCN: v_mov_b32_e32 [[THREE:v[0-9]+]], 3
Show All 14 Lines
if.end: ; preds = %if.else, %if.then if.end: ; preds = %if.else, %if.then
store i32 3, i32 addrspace(1)* %out1 store i32 3, i32 addrspace(1)* %out1
ret void ret void
} }
; GCN-LABEL: {{^}}icmp_2_users: ; GCN-LABEL: {{^}}icmp_2_users:
; GCN: s_cmp_lt_i32 s{{[0-9]+}}, 1 ; GCN: s_cmp_lt_i32 s{{[0-9]+}}, 1
; GCN: s_cbranch_scc1 [[LABEL:[a-zA-Z0-9_]+]] ; GCN: s_cbranch_scc1 [[LABEL:.L[0-9_A-Za-z]+]]
; GCN: buffer_store_dword ; GCN: buffer_store_dword
; GCN: [[LABEL]]: ; GCN: [[LABEL]]:
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @icmp_2_users(i32 addrspace(1)* %out, i32 %cond) { define amdgpu_kernel void @icmp_2_users(i32 addrspace(1)* %out, i32 %cond) {
main_body: main_body:
%0 = icmp sgt i32 %cond, 0 %0 = icmp sgt i32 %cond, 0
%1 = sext i1 %0 to i32 %1 = sext i1 %0 to i32
br i1 %0, label %IF, label %ENDIF br i1 %0, label %IF, label %ENDIF
IF: IF:
store i32 %1, i32 addrspace(1)* %out store i32 %1, i32 addrspace(1)* %out
br label %ENDIF br label %ENDIF
ENDIF: ; preds = %IF, %main_body ENDIF: ; preds = %IF, %main_body
ret void ret void
} }
; GCN-LABEL: {{^}}icmp_users_different_blocks: ; GCN-LABEL: {{^}}icmp_users_different_blocks:
; GCN: s_load_dwordx2 s{{\[}}[[COND0:[0-9]+]]:[[COND1:[0-9]+]]{{\]}} ; GCN: s_load_dwordx2 s{{\[}}[[COND0:[0-9]+]]:[[COND1:[0-9]+]]{{\]}}
; GCN: s_cmp_lt_i32 s[[COND0]], 1 ; GCN: s_cmp_lt_i32 s[[COND0]], 1
; GCN: s_cbranch_scc1 [[EXIT:[A-Za-z0-9_]+]] ; GCN: s_cbranch_scc1 [[EXIT:.L[0-9_A-Za-z]+]]
; GCN: s_cmp_gt_i32 s[[COND1]], 0{{$}} ; GCN: s_cmp_gt_i32 s[[COND1]], 0{{$}}
; GCN: s_cbranch_vccz [[BODY:[A-Za-z0-9_]+]] ; GCN: s_cbranch_vccz [[BODY:.L[0-9_A-Za-z]+]]
; GCN: {{^}}[[EXIT]]: ; GCN: {{^}}[[EXIT]]:
; GCN: s_endpgm ; GCN: s_endpgm
; GCN: {{^}}[[BODY]]: ; GCN: {{^}}[[BODY]]:
; GCN: buffer_store ; GCN: buffer_store
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @icmp_users_different_blocks(i32 %cond0, i32 %cond1, i32 addrspace(1)* %out) { define amdgpu_kernel void @icmp_users_different_blocks(i32 %cond0, i32 %cond1, i32 addrspace(1)* %out) {
bb: bb:
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0
Show All 10 Linesbb7: ; preds = %bb5
store i32 %tmp3, i32 addrspace(1)* %out store i32 %tmp3, i32 addrspace(1)* %out
br label %bb9 br label %bb9
bb9: ; preds = %bb8, %bb4 bb9: ; preds = %bb8, %bb4
ret void ret void
} }
; SI-LABEL: {{^}}uniform_loop: ; SI-LABEL: {{^}}uniform_loop:
; SI: {{^}}[[LOOP_LABEL:[A-Z0-9_a-z]+]]: ; SI: {{^}}[[LOOP_LABEL:.L[0-9_A-Za-z]+]]:
; SI: s_add_i32 [[I:s[0-9]+]], s{{[0-9]+}}, -1 ; SI: s_add_i32 [[I:s[0-9]+]], s{{[0-9]+}}, -1
; SI: s_cmp_lg_u32 [[I]], 0 ; SI: s_cmp_lg_u32 [[I]], 0
; SI: s_cbranch_scc1 [[LOOP_LABEL]] ; SI: s_cbranch_scc1 [[LOOP_LABEL]]
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @uniform_loop(i32 addrspace(1)* %out, i32 %a) { define amdgpu_kernel void @uniform_loop(i32 addrspace(1)* %out, i32 %a) {
entry: entry:
br label %loop br label %loop
loop: loop:
%i = phi i32 [0, %entry], [%i.i, %loop] %i = phi i32 [0, %entry], [%i.i, %loop]
%i.i = add i32 %i, 1 %i.i = add i32 %i, 1
%cmp = icmp eq i32 %a, %i.i %cmp = icmp eq i32 %a, %i.i
br i1 %cmp, label %done, label %loop br i1 %cmp, label %done, label %loop
done: done:
ret void ret void
} }
; Test uniform and divergent. ; Test uniform and divergent.
; GCN-LABEL: {{^}}uniform_inside_divergent: ; GCN-LABEL: {{^}}uniform_inside_divergent:
; GCN: v_cmp_gt_u32_e32 vcc, 16, v{{[0-9]+}} ; GCN: v_cmp_gt_u32_e32 vcc, 16, v{{[0-9]+}}
; GCN: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc ; GCN: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc
; GCN: s_cmp_lg_u32 {{s[0-9]+}}, 0 ; GCN: s_cmp_lg_u32 {{s[0-9]+}}, 0
; GCN: s_cbranch_scc0 [[IF_UNIFORM_LABEL:[A-Z0-9_a-z]+]] ; GCN: s_cbranch_scc0 [[IF_UNIFORM_LABEL:.L[0-9_A-Za-z]+]]
; GCN: s_endpgm ; GCN: s_endpgm
; GCN: {{^}}[[IF_UNIFORM_LABEL]]: ; GCN: {{^}}[[IF_UNIFORM_LABEL]]:
; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1 ; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
; GCN: buffer_store_dword [[ONE]] ; GCN: buffer_store_dword [[ONE]]
define amdgpu_kernel void @uniform_inside_divergent(i32 addrspace(1)* %out, i32 %cond) { define amdgpu_kernel void @uniform_inside_divergent(i32 addrspace(1)* %out, i32 %cond) {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0
%d_cmp = icmp ult i32 %tid, 16 %d_cmp = icmp ult i32 %tid, 16
Show All 9 Linesif_uniform:
br label %endif br label %endif
endif: endif:
ret void ret void
} }
; GCN-LABEL: {{^}}divergent_inside_uniform: ; GCN-LABEL: {{^}}divergent_inside_uniform:
; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 0 ; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 0
; GCN: s_cbranch_scc0 [[IF_LABEL:[0-9_A-Za-z]+]] ; GCN: s_cbranch_scc0 [[IF_LABEL:.L[0-9_A-Za-z]+]]
; GCN: [[ENDIF_LABEL:[0-9_A-Za-z]+]]: ; GCN: [[ENDIF_LABEL:.L[0-9_A-Za-z]+]]:
; GCN: [[IF_LABEL]]: ; GCN: [[IF_LABEL]]:
; GCN: v_cmp_gt_u32_e32 vcc, 16, v{{[0-9]+}} ; GCN: v_cmp_gt_u32_e32 vcc, 16, v{{[0-9]+}}
; GCN: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc ; GCN: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc
; GCN: s_cbranch_execz [[ENDIF_LABEL]] ; GCN: s_cbranch_execz [[ENDIF_LABEL]]
; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1 ; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
; GCN: buffer_store_dword [[ONE]] ; GCN: buffer_store_dword [[ONE]]
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @divergent_inside_uniform(i32 addrspace(1)* %out, i32 %cond) { define amdgpu_kernel void @divergent_inside_uniform(i32 addrspace(1)* %out, i32 %cond) {
Show All 17 Lines
; GCN-LABEL: {{^}}divergent_if_uniform_if: ; GCN-LABEL: {{^}}divergent_if_uniform_if:
; GCN: v_cmp_eq_u32_e32 vcc, 0, v0 ; GCN: v_cmp_eq_u32_e32 vcc, 0, v0
; GCN: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc ; GCN: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc
; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1 ; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
; GCN: buffer_store_dword [[ONE]] ; GCN: buffer_store_dword [[ONE]]
; GCN: s_or_b64 exec, exec, [[MASK]] ; GCN: s_or_b64 exec, exec, [[MASK]]
; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 0 ; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 0
; GCN: s_cbranch_scc0 [[IF_UNIFORM:[A-Z0-9_]+]] ; GCN: s_cbranch_scc0 [[IF_UNIFORM:.L[0-9_A-Za-z]+]]
; GCN: s_endpgm ; GCN: s_endpgm
; GCN: [[IF_UNIFORM]]: ; GCN: [[IF_UNIFORM]]:
; GCN: v_mov_b32_e32 [[TWO:v[0-9]+]], 2 ; GCN: v_mov_b32_e32 [[TWO:v[0-9]+]], 2
; GCN: buffer_store_dword [[TWO]] ; GCN: buffer_store_dword [[TWO]]
define amdgpu_kernel void @divergent_if_uniform_if(i32 addrspace(1)* %out, i32 %cond) { define amdgpu_kernel void @divergent_if_uniform_if(i32 addrspace(1)* %out, i32 %cond) {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0
%d_cmp = icmp eq i32 %tid, 0 %d_cmp = icmp eq i32 %tid, 0
Show All 18 Lines
; The condition of the branches in the two blocks are ; The condition of the branches in the two blocks are
; uniform. MachineCSE replaces the 2nd condition with the inverse of ; uniform. MachineCSE replaces the 2nd condition with the inverse of
; the first, leaving an scc use in a different block than it was ; the first, leaving an scc use in a different block than it was
; defed. ; defed.
; GCN-LABEL: {{^}}cse_uniform_condition_different_blocks: ; GCN-LABEL: {{^}}cse_uniform_condition_different_blocks:
; GCN: s_load_dword [[COND:s[0-9]+]] ; GCN: s_load_dword [[COND:s[0-9]+]]
; GCN: s_cmp_lt_i32 [[COND]], 1 ; GCN: s_cmp_lt_i32 [[COND]], 1
; GCN: s_cbranch_scc1 BB[[FNNUM:[0-9]+]]_3 ; GCN: s_cbranch_scc1 .LBB[[FNNUM:[0-9]+]]_3
; GCN: %bb.1: ; GCN: %bb.1:
; GCN-NOT: cmp ; GCN-NOT: cmp
; GCN: buffer_load_dword ; GCN: buffer_load_dword
; GCN: buffer_store_dword ; GCN: buffer_store_dword
; GCN: s_cbranch_scc1 BB[[FNNUM]]_3 ; GCN: s_cbranch_scc1 .LBB[[FNNUM]]_3
; GCN: BB[[FNNUM]]_3: ; GCN: .LBB[[FNNUM]]_3:
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @cse_uniform_condition_different_blocks(i32 %cond, i32 addrspace(1)* %out) { define amdgpu_kernel void @cse_uniform_condition_different_blocks(i32 %cond, i32 addrspace(1)* %out) {
bb: bb:
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0
%tmp1 = icmp sgt i32 %cond, 0 %tmp1 = icmp sgt i32 %cond, 0
br i1 %tmp1, label %bb2, label %bb9 br i1 %tmp1, label %bb2, label %bb9
bb2: ; preds = %bb bb2: ; preds = %bb
Show All 9 Lines
bb9: ; preds = %bb8, %bb4 bb9: ; preds = %bb8, %bb4
ret void ret void
} }
; GCN-LABEL: {{^}}uniform_if_scc_i64_eq: ; GCN-LABEL: {{^}}uniform_if_scc_i64_eq:
; VI-DAG: s_cmp_eq_u64 s{{\[[0-9]+:[0-9]+\]}}, 0 ; VI-DAG: s_cmp_eq_u64 s{{\[[0-9]+:[0-9]+\]}}, 0
; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0 ; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0
; SI-DAG: v_cmp_eq_u64_e64 ; SI-DAG: v_cmp_eq_u64_e64
; SI: s_cbranch_vccnz [[IF_LABEL:[0-9_A-Za-z]+]] ; SI: s_cbranch_vccnz [[IF_LABEL:.L[0-9_A-Za-z]+]]
; VI: s_cbranch_scc1 [[IF_LABEL:[0-9_A-Za-z]+]] ; VI: s_cbranch_scc1 [[IF_LABEL:.L[0-9_A-Za-z]+]]
; Fall-through to the else ; Fall-through to the else
; GCN: s_mov_b32 [[S_VAL]], 1 ; GCN: s_mov_b32 [[S_VAL]], 1
; GCN: [[IF_LABEL]]: ; GCN: [[IF_LABEL]]:
; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]] ; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]]
; GCN: buffer_store_dword [[V_VAL]] ; GCN: buffer_store_dword [[V_VAL]]
define amdgpu_kernel void @uniform_if_scc_i64_eq(i64 %cond, i32 addrspace(1)* %out) { define amdgpu_kernel void @uniform_if_scc_i64_eq(i64 %cond, i32 addrspace(1)* %out) {
Show All 13 Linesdone:
ret void ret void
} }
; GCN-LABEL: {{^}}uniform_if_scc_i64_ne: ; GCN-LABEL: {{^}}uniform_if_scc_i64_ne:
; VI-DAG: s_cmp_lg_u64 s{{\[[0-9]+:[0-9]+\]}}, 0 ; VI-DAG: s_cmp_lg_u64 s{{\[[0-9]+:[0-9]+\]}}, 0
; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0 ; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0
; SI-DAG: v_cmp_ne_u64_e64 ; SI-DAG: v_cmp_ne_u64_e64
; SI: s_cbranch_vccnz [[IF_LABEL:[0-9_A-Za-z]+]] ; SI: s_cbranch_vccnz [[IF_LABEL:.L[0-9_A-Za-z]+]]
; VI: s_cbranch_scc1 [[IF_LABEL:[0-9_A-Za-z]+]] ; VI: s_cbranch_scc1 [[IF_LABEL:.L[0-9_A-Za-z]+]]
; Fall-through to the else ; Fall-through to the else
; GCN: s_mov_b32 [[S_VAL]], 1 ; GCN: s_mov_b32 [[S_VAL]], 1
; GCN: [[IF_LABEL]]: ; GCN: [[IF_LABEL]]:
; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]] ; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]]
; GCN: buffer_store_dword [[V_VAL]] ; GCN: buffer_store_dword [[V_VAL]]
define amdgpu_kernel void @uniform_if_scc_i64_ne(i64 %cond, i32 addrspace(1)* %out) { define amdgpu_kernel void @uniform_if_scc_i64_ne(i64 %cond, i32 addrspace(1)* %out) {
Show All 11 Linesdone:
%value = phi i32 [0, %if], [1, %else] %value = phi i32 [0, %if], [1, %else]
store i32 %value, i32 addrspace(1)* %out store i32 %value, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}uniform_if_scc_i64_sgt: ; GCN-LABEL: {{^}}uniform_if_scc_i64_sgt:
; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0 ; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0
; GCN-DAG: v_cmp_gt_i64_e64 ; GCN-DAG: v_cmp_gt_i64_e64
; GCN: s_cbranch_vccnz [[IF_LABEL:[0-9_A-Za-z]+]] ; GCN: s_cbranch_vccnz [[IF_LABEL:.L[0-9_A-Za-z]+]]
; Fall-through to the else ; Fall-through to the else
; GCN: s_mov_b32 [[S_VAL]], 1 ; GCN: s_mov_b32 [[S_VAL]], 1
; GCN: [[IF_LABEL]]: ; GCN: [[IF_LABEL]]:
; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]] ; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]]
; GCN: buffer_store_dword [[V_VAL]] ; GCN: buffer_store_dword [[V_VAL]]
define amdgpu_kernel void @uniform_if_scc_i64_sgt(i64 %cond, i32 addrspace(1)* %out) { define amdgpu_kernel void @uniform_if_scc_i64_sgt(i64 %cond, i32 addrspace(1)* %out) {
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llvm/test/CodeGen/AMDGPU/uniform-crash.ll

; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s ; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s
; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s ; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s
; GCN-LABEL: {{^}}icmp_2_users: ; GCN-LABEL: {{^}}icmp_2_users:
; GCN: s_cmp_lt_i32 s{{[0-9]+}}, 1 ; GCN: s_cmp_lt_i32 s{{[0-9]+}}, 1
; GCN: s_cbranch_scc1 [[LABEL:BB[0-9_A-Z]+]] ; GCN: s_cbranch_scc1 [[LABEL:.LBB[0-9_A-Z]+]]
; GCN: [[LABEL]]: ; GCN: [[LABEL]]:
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @icmp_2_users(i32 addrspace(1)* %out, i32 %cond) { define amdgpu_kernel void @icmp_2_users(i32 addrspace(1)* %out, i32 %cond) {
main_body: main_body:
%0 = icmp sgt i32 %cond, 0 %0 = icmp sgt i32 %cond, 0
%1 = sext i1 %0 to i32 %1 = sext i1 %0 to i32
br i1 %0, label %IF, label %ENDIF br i1 %0, label %IF, label %ENDIF
IF: IF:
store i32 %1, i32 addrspace(1)* %out store i32 %1, i32 addrspace(1)* %out
br label %ENDIF br label %ENDIF
ENDIF: ; preds = %IF, %main_body ENDIF: ; preds = %IF, %main_body
ret void ret void
} }
; GCN-LABEL: {{^}}fix_sgpr_live_ranges_crash: ; GCN-LABEL: {{^}}fix_sgpr_live_ranges_crash:
; GCN: s_cbranch_scc1 [[BB0:[A-Z0-9_]+]] ; GCN: s_cbranch_scc1 [[BB0:.L[A-Z0-9_]+]]
; GCN: {{^}}[[LOOP:[A-Z0-9_]+]]: ; GCN: {{^}}[[LOOP:.L[A-Z0-9_]+]]:
; GCN: s_cbranch_scc1 [[LOOP]] ; GCN: s_cbranch_scc1 [[LOOP]]
; GCN: {{^}}[[BB0]]: ; GCN: {{^}}[[BB0]]:
define amdgpu_kernel void @fix_sgpr_live_ranges_crash(i32 %arg, i32 %arg1) { define amdgpu_kernel void @fix_sgpr_live_ranges_crash(i32 %arg, i32 %arg1) {
bb: bb:
%cnd = trunc i32 %arg to i1 %cnd = trunc i32 %arg to i1
br i1 %cnd, label %bb2, label %bb5 br i1 %cnd, label %bb2, label %bb5
bb2: ; preds = %bb bb2: ; preds = %bb
Show All 24 Lines

llvm/test/CodeGen/AMDGPU/uniform-loop-inside-nonuniform.ll

; RUN: llc -march=amdgcn -mcpu=verde < %s | FileCheck %s ; RUN: llc -march=amdgcn -mcpu=verde < %s | FileCheck %s
; Test a simple uniform loop that lives inside non-uniform control flow. ; Test a simple uniform loop that lives inside non-uniform control flow.
; CHECK-LABEL: {{^}}test1: ; CHECK-LABEL: {{^}}test1:
; CHECK: v_cmp_ne_u32_e32 vcc, 0 ; CHECK: v_cmp_ne_u32_e32 vcc, 0
; CHECK: s_and_saveexec_b64 ; CHECK: s_and_saveexec_b64
; CHECK-NEXT: s_cbranch_execz BB{{[0-9]+_[0-9]+}} ; CHECK-NEXT: s_cbranch_execz .LBB{{[0-9]+_[0-9]+}}
; CHECK: [[LOOP_BODY_LABEL:BB[0-9]+_[0-9]+]]: ; %loop_body ; CHECK: [[LOOP_BODY_LABEL:.LBB[0-9]+_[0-9]+]]: ; %loop_body
; CHECK: s_cbranch_scc1 [[LOOP_BODY_LABEL]] ; CHECK: s_cbranch_scc1 [[LOOP_BODY_LABEL]]
; CHECK: s_endpgm ; CHECK: s_endpgm
define amdgpu_ps void @test1(<8 x i32> inreg %rsrc, <2 x i32> %addr.base, i32 %y, i32 %p) { define amdgpu_ps void @test1(<8 x i32> inreg %rsrc, <2 x i32> %addr.base, i32 %y, i32 %p) {
main_body: main_body:
%cc = icmp eq i32 %p, 0 %cc = icmp eq i32 %p, 0
br i1 %cc, label %out, label %loop_body br i1 %cc, label %out, label %loop_body
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llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll

Show All 14 Lines
; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: flat_load_dword v0, v[0:1] ; GCN-NEXT: flat_load_dword v0, v[0:1]
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cmp_gt_i32_e32 vcc, 21, v0 ; GCN-NEXT: v_cmp_gt_i32_e32 vcc, 21, v0
; GCN-NEXT: s_and_b64 vcc, exec, vcc ; GCN-NEXT: s_and_b64 vcc, exec, vcc
; GCN-NEXT: v_writelane_b32 v40, s30, 0 ; GCN-NEXT: v_writelane_b32 v40, s30, 0
; GCN-NEXT: v_writelane_b32 v40, s31, 1 ; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_cbranch_vccz BB0_3 ; GCN-NEXT: s_cbranch_vccz .LBB0_3
; GCN-NEXT: ; %bb.1: ; %bb4 ; GCN-NEXT: ; %bb.1: ; %bb4
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 9, v0 ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 9, v0
; GCN-NEXT: s_and_b64 vcc, exec, vcc ; GCN-NEXT: s_and_b64 vcc, exec, vcc
; GCN-NEXT: s_cbranch_vccnz BB0_4 ; GCN-NEXT: s_cbranch_vccnz .LBB0_4
; GCN-NEXT: ; %bb.2: ; %bb7 ; GCN-NEXT: ; %bb.2: ; %bb7
; GCN-NEXT: s_getpc_b64 s[4:5] ; GCN-NEXT: s_getpc_b64 s[4:5]
; GCN-NEXT: s_add_u32 s4, s4, wibble@rel32@lo+4 ; GCN-NEXT: s_add_u32 s4, s4, wibble@rel32@lo+4
; GCN-NEXT: s_addc_u32 s5, s5, wibble@rel32@hi+12 ; GCN-NEXT: s_addc_u32 s5, s5, wibble@rel32@hi+12
; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GCN-NEXT: s_branch BB0_7 ; GCN-NEXT: s_branch .LBB0_7
; GCN-NEXT: BB0_3: ; %bb2 ; GCN-NEXT: .LBB0_3: ; %bb2
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 21, v0 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 21, v0
; GCN-NEXT: s_and_b64 vcc, exec, vcc ; GCN-NEXT: s_and_b64 vcc, exec, vcc
; GCN-NEXT: s_cbranch_vccnz BB0_6 ; GCN-NEXT: s_cbranch_vccnz .LBB0_6
; GCN-NEXT: BB0_4: ; %bb9 ; GCN-NEXT: .LBB0_4: ; %bb9
; GCN-NEXT: s_getpc_b64 s[4:5] ; GCN-NEXT: s_getpc_b64 s[4:5]
; GCN-NEXT: s_add_u32 s4, s4, wibble@rel32@lo+4 ; GCN-NEXT: s_add_u32 s4, s4, wibble@rel32@lo+4
; GCN-NEXT: s_addc_u32 s5, s5, wibble@rel32@hi+12 ; GCN-NEXT: s_addc_u32 s5, s5, wibble@rel32@hi+12
; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GCN-NEXT: v_cmp_lt_f32_e32 vcc, 0, v0 ; GCN-NEXT: v_cmp_lt_f32_e32 vcc, 0, v0
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_cbranch_execnz BB0_7 ; GCN-NEXT: s_cbranch_execnz .LBB0_7
; GCN-NEXT: ; %bb.5: ; %bb9.bb12_crit_edge ; GCN-NEXT: ; %bb.5: ; %bb9.bb12_crit_edge
; GCN-NEXT: s_or_b64 exec, exec, s[4:5] ; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: BB0_6: ; %bb12 ; GCN-NEXT: .LBB0_6: ; %bb12
; GCN-NEXT: v_mov_b32_e32 v2, 0 ; GCN-NEXT: v_mov_b32_e32 v2, 0
; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: flat_store_dword v[0:1], v2 ; GCN-NEXT: flat_store_dword v[0:1], v2
; GCN-NEXT: BB0_7: ; %UnifiedReturnBlock ; GCN-NEXT: .LBB0_7: ; %UnifiedReturnBlock
; GCN-NEXT: v_readlane_b32 s4, v40, 0 ; GCN-NEXT: v_readlane_b32 s4, v40, 0
; GCN-NEXT: v_readlane_b32 s5, v40, 1 ; GCN-NEXT: v_readlane_b32 s5, v40, 1
; GCN-NEXT: s_addk_i32 s32, 0xfc00 ; GCN-NEXT: s_addk_i32 s32, 0xfc00
; GCN-NEXT: v_readlane_b32 s33, v40, 2 ; GCN-NEXT: v_readlane_b32 s33, v40, 2
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 ; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
; GCN-NEXT: s_mov_b64 exec, s[6:7] ; GCN-NEXT: s_mov_b64 exec, s[6:7]
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: flat_load_dword v43, v[1:2] ; GCN-NEXT: flat_load_dword v43, v[1:2]
; GCN-NEXT: v_mov_b32_e32 v44, 0x7fc00000 ; GCN-NEXT: v_mov_b32_e32 v44, 0x7fc00000
; GCN-NEXT: s_getpc_b64 s[36:37] ; GCN-NEXT: s_getpc_b64 s[36:37]
; GCN-NEXT: s_add_u32 s36, s36, spam@rel32@lo+4 ; GCN-NEXT: s_add_u32 s36, s36, spam@rel32@lo+4
; GCN-NEXT: s_addc_u32 s37, s37, spam@rel32@hi+12 ; GCN-NEXT: s_addc_u32 s37, s37, spam@rel32@hi+12
; GCN-NEXT: v_lshlrev_b32_e32 v41, 2, v0 ; GCN-NEXT: v_lshlrev_b32_e32 v41, 2, v0
; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_eq_f32_e64 s[34:35], 0, v43 ; GCN-NEXT: v_cmp_eq_f32_e64 s[34:35], 0, v43
; GCN-NEXT: s_branch BB1_3 ; GCN-NEXT: s_branch .LBB1_3
; GCN-NEXT: BB1_1: ; %bb10 ; GCN-NEXT: .LBB1_1: ; %bb10
; GCN-NEXT: ; in Loop: Header=BB1_3 Depth=1 ; GCN-NEXT: ; in Loop: Header=BB1_3 Depth=1
; GCN-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-NEXT: buffer_store_dword v44, off, s[0:3], 0 ; GCN-NEXT: buffer_store_dword v44, off, s[0:3], 0
; GCN-NEXT: BB1_2: ; %bb18 ; GCN-NEXT: .LBB1_2: ; %bb18
; GCN-NEXT: ; in Loop: Header=BB1_3 Depth=1 ; GCN-NEXT: ; in Loop: Header=BB1_3 Depth=1
; GCN-NEXT: buffer_store_dword v44, off, s[0:3], 0 ; GCN-NEXT: buffer_store_dword v44, off, s[0:3], 0
; GCN-NEXT: s_mov_b64 s[4:5], 0 ; GCN-NEXT: s_mov_b64 s[4:5], 0
; GCN-NEXT: BB1_3: ; %bb2 ; GCN-NEXT: .LBB1_3: ; %bb2
; GCN-NEXT: ; =>This Loop Header: Depth=1 ; GCN-NEXT: ; =>This Loop Header: Depth=1
; GCN-NEXT: ; Child Loop BB1_4 Depth 2 ; GCN-NEXT: ; Child Loop BB1_4 Depth 2
; GCN-NEXT: s_mov_b64 s[6:7], 0 ; GCN-NEXT: s_mov_b64 s[6:7], 0
; GCN-NEXT: BB1_4: ; %bb2 ; GCN-NEXT: .LBB1_4: ; %bb2
; GCN-NEXT: ; Parent Loop BB1_3 Depth=1 ; GCN-NEXT: ; Parent Loop BB1_3 Depth=1
; GCN-NEXT: ; => This Inner Loop Header: Depth=2 ; GCN-NEXT: ; => This Inner Loop Header: Depth=2
; GCN-NEXT: flat_load_dword v0, v[41:42] ; GCN-NEXT: flat_load_dword v0, v[41:42]
; GCN-NEXT: buffer_store_dword v42, off, s[0:3], 0 ; GCN-NEXT: buffer_store_dword v42, off, s[0:3], 0
; GCN-NEXT: s_waitcnt vmcnt(1) ; GCN-NEXT: s_waitcnt vmcnt(1)
; GCN-NEXT: v_cmp_gt_i32_e32 vcc, 3, v0 ; GCN-NEXT: v_cmp_gt_i32_e32 vcc, 3, v0
; GCN-NEXT: s_and_saveexec_b64 s[8:9], vcc ; GCN-NEXT: s_and_saveexec_b64 s[8:9], vcc
; GCN-NEXT: s_cbranch_execz BB1_6 ; GCN-NEXT: s_cbranch_execz .LBB1_6
; GCN-NEXT: ; %bb.5: ; %bb8 ; GCN-NEXT: ; %bb.5: ; %bb8
; GCN-NEXT: ; in Loop: Header=BB1_4 Depth=2 ; GCN-NEXT: ; in Loop: Header=BB1_4 Depth=2
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GCN-NEXT: s_or_b64 s[6:7], vcc, s[6:7] ; GCN-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
; GCN-NEXT: s_mov_b64 s[4:5], 0 ; GCN-NEXT: s_mov_b64 s[4:5], 0
; GCN-NEXT: s_andn2_b64 exec, exec, s[6:7] ; GCN-NEXT: s_andn2_b64 exec, exec, s[6:7]
; GCN-NEXT: s_cbranch_execnz BB1_4 ; GCN-NEXT: s_cbranch_execnz .LBB1_4
; GCN-NEXT: s_branch BB1_1 ; GCN-NEXT: s_branch .LBB1_1
; GCN-NEXT: BB1_6: ; %bb6 ; GCN-NEXT: .LBB1_6: ; %bb6
; GCN-NEXT: ; in Loop: Header=BB1_4 Depth=2 ; GCN-NEXT: ; in Loop: Header=BB1_4 Depth=2
; GCN-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0
; GCN-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GCN-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GCN-NEXT: s_mov_b64 s[6:7], 0 ; GCN-NEXT: s_mov_b64 s[6:7], 0
; GCN-NEXT: s_andn2_b64 exec, exec, s[4:5] ; GCN-NEXT: s_andn2_b64 exec, exec, s[4:5]
; GCN-NEXT: s_cbranch_execnz BB1_4 ; GCN-NEXT: s_cbranch_execnz .LBB1_4
; GCN-NEXT: ; %bb.7: ; %bb11 ; GCN-NEXT: ; %bb.7: ; %bb11
; GCN-NEXT: ; in Loop: Header=BB1_4 Depth=2 ; GCN-NEXT: ; in Loop: Header=BB1_4 Depth=2
; GCN-NEXT: s_or_b64 exec, exec, s[4:5] ; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_swappc_b64 s[30:31], s[36:37] ; GCN-NEXT: s_swappc_b64 s[30:31], s[36:37]
; GCN-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0 ; GCN-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0
; GCN-NEXT: s_mov_b64 s[4:5], 0 ; GCN-NEXT: s_mov_b64 s[4:5], 0
; GCN-NEXT: s_mov_b64 s[6:7], 0 ; GCN-NEXT: s_mov_b64 s[6:7], 0
; GCN-NEXT: s_and_saveexec_b64 s[8:9], vcc ; GCN-NEXT: s_and_saveexec_b64 s[8:9], vcc
; GCN-NEXT: s_cbranch_execnz BB1_4 ; GCN-NEXT: s_cbranch_execnz .LBB1_4
; GCN-NEXT: ; %bb.8: ; %bb14 ; GCN-NEXT: ; %bb.8: ; %bb14
; GCN-NEXT: ; in Loop: Header=BB1_3 Depth=1 ; GCN-NEXT: ; in Loop: Header=BB1_3 Depth=1
; GCN-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-NEXT: s_and_saveexec_b64 s[4:5], s[34:35] ; GCN-NEXT: s_and_saveexec_b64 s[4:5], s[34:35]
; GCN-NEXT: s_cbranch_execnz BB1_10 ; GCN-NEXT: s_cbranch_execnz .LBB1_10
; GCN-NEXT: ; %bb.9: ; %bb16 ; GCN-NEXT: ; %bb.9: ; %bb16
; GCN-NEXT: ; in Loop: Header=BB1_3 Depth=1 ; GCN-NEXT: ; in Loop: Header=BB1_3 Depth=1
; GCN-NEXT: s_or_b64 exec, exec, s[4:5] ; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: buffer_store_dword v44, off, s[0:3], 0 ; GCN-NEXT: buffer_store_dword v44, off, s[0:3], 0
; GCN-NEXT: BB1_10: ; %bb17 ; GCN-NEXT: .LBB1_10: ; %bb17
; GCN-NEXT: ; in Loop: Header=BB1_3 Depth=1 ; GCN-NEXT: ; in Loop: Header=BB1_3 Depth=1
; GCN-NEXT: buffer_store_dword v43, off, s[0:3], 0 ; GCN-NEXT: buffer_store_dword v43, off, s[0:3], 0
; GCN-NEXT: s_branch BB1_2 ; GCN-NEXT: s_branch .LBB1_2
bb: bb:
%tmp = load float, float* null, align 16 %tmp = load float, float* null, align 16
br label %bb2 br label %bb2
bb1: ; preds = %bb8, %bb6 bb1: ; preds = %bb8, %bb6
br label %bb2 br label %bb2
bb2: bb2:
▲ Show 20 Lines • Show All 47 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/urem64.ll

Show First 20 Lines • Show All 141 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: s_subb_u32 s11, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s11, 0, 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[16:17], s[10:11], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[16:17], s[10:11], 63
; GCN-IR-NEXT: s_mov_b32 s9, 0 ; GCN-IR-NEXT: s_mov_b32 s9, 0
; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17] ; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17]
; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[16:17], s[10:11], 63 ; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[16:17], s[10:11], 63
; GCN-IR-NEXT: s_xor_b64 s[18:19], s[14:15], -1 ; GCN-IR-NEXT: s_xor_b64 s[18:19], s[14:15], -1
; GCN-IR-NEXT: s_and_b64 s[16:17], s[18:19], s[16:17] ; GCN-IR-NEXT: s_and_b64 s[16:17], s[18:19], s[16:17]
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[16:17] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[16:17]
; GCN-IR-NEXT: s_cbranch_vccz BB0_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_5
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s14, s10, 1 ; GCN-IR-NEXT: s_add_u32 s14, s10, 1
; GCN-IR-NEXT: v_mov_b32_e32 v0, s10 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s10
; GCN-IR-NEXT: s_addc_u32 s15, s11, 0 ; GCN-IR-NEXT: s_addc_u32 s15, s11, 0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s11 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s11
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[14:15], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[14:15], v[0:1]
; GCN-IR-NEXT: s_sub_i32 s10, 63, s10 ; GCN-IR-NEXT: s_sub_i32 s10, 63, s10
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[6:7], s10 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[6:7], s10
; GCN-IR-NEXT: s_cbranch_vccz BB0_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[14:15], s[6:7], s14 ; GCN-IR-NEXT: s_lshr_b64 s[14:15], s[6:7], s14
; GCN-IR-NEXT: s_add_u32 s16, s0, -1 ; GCN-IR-NEXT: s_add_u32 s16, s0, -1
; GCN-IR-NEXT: s_addc_u32 s17, s1, -1 ; GCN-IR-NEXT: s_addc_u32 s17, s1, -1
; GCN-IR-NEXT: s_not_b64 s[2:3], s[8:9] ; GCN-IR-NEXT: s_not_b64 s[2:3], s[8:9]
; GCN-IR-NEXT: s_mov_b32 s13, s9 ; GCN-IR-NEXT: s_mov_b32 s13, s9
; GCN-IR-NEXT: s_add_u32 s8, s2, s12 ; GCN-IR-NEXT: s_add_u32 s8, s2, s12
; GCN-IR-NEXT: s_addc_u32 s9, s3, s9 ; GCN-IR-NEXT: s_addc_u32 s9, s3, s9
; GCN-IR-NEXT: s_mov_b64 s[12:13], 0 ; GCN-IR-NEXT: s_mov_b64 s[12:13], 0
; GCN-IR-NEXT: s_mov_b32 s3, 0 ; GCN-IR-NEXT: s_mov_b32 s3, 0
; GCN-IR-NEXT: BB0_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB0_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[14:15], s[14:15], 1 ; GCN-IR-NEXT: s_lshl_b64 s[14:15], s[14:15], 1
; GCN-IR-NEXT: s_lshr_b32 s2, s11, 31 ; GCN-IR-NEXT: s_lshr_b32 s2, s11, 31
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1
; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[2:3] ; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[2:3]
; GCN-IR-NEXT: s_or_b64 s[10:11], s[12:13], s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[12:13], s[10:11]
; GCN-IR-NEXT: s_sub_u32 s2, s16, s14 ; GCN-IR-NEXT: s_sub_u32 s2, s16, s14
; GCN-IR-NEXT: s_subb_u32 s2, s17, s15 ; GCN-IR-NEXT: s_subb_u32 s2, s17, s15
; GCN-IR-NEXT: s_ashr_i32 s12, s2, 31 ; GCN-IR-NEXT: s_ashr_i32 s12, s2, 31
; GCN-IR-NEXT: s_mov_b32 s13, s12 ; GCN-IR-NEXT: s_mov_b32 s13, s12
; GCN-IR-NEXT: s_and_b32 s2, s12, 1 ; GCN-IR-NEXT: s_and_b32 s2, s12, 1
; GCN-IR-NEXT: s_and_b64 s[18:19], s[12:13], s[0:1] ; GCN-IR-NEXT: s_and_b64 s[18:19], s[12:13], s[0:1]
; GCN-IR-NEXT: s_sub_u32 s14, s14, s18 ; GCN-IR-NEXT: s_sub_u32 s14, s14, s18
; GCN-IR-NEXT: v_mov_b32_e32 v0, s8 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s8
; GCN-IR-NEXT: s_subb_u32 s15, s15, s19 ; GCN-IR-NEXT: s_subb_u32 s15, s15, s19
; GCN-IR-NEXT: v_mov_b32_e32 v1, s9 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s9
; GCN-IR-NEXT: s_add_u32 s8, s8, 1 ; GCN-IR-NEXT: s_add_u32 s8, s8, 1
; GCN-IR-NEXT: s_addc_u32 s9, s9, 0 ; GCN-IR-NEXT: s_addc_u32 s9, s9, 0
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
; GCN-IR-NEXT: s_mov_b64 s[12:13], s[2:3] ; GCN-IR-NEXT: s_mov_b64 s[12:13], s[2:3]
; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_cbranch_vccz BB0_3 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_3
; GCN-IR-NEXT: BB0_4: ; %Flow6 ; GCN-IR-NEXT: .LBB0_4: ; %Flow6
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[10:11], 1 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[10:11], 1
; GCN-IR-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] ; GCN-IR-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
; GCN-IR-NEXT: v_mov_b32_e32 v0, s2 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s2
; GCN-IR-NEXT: v_mov_b32_e32 v1, s3 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s3
; GCN-IR-NEXT: s_branch BB0_6 ; GCN-IR-NEXT: s_branch .LBB0_6
; GCN-IR-NEXT: BB0_5: ; GCN-IR-NEXT: .LBB0_5:
; GCN-IR-NEXT: v_mov_b32_e32 v0, s7 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s7
; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[14:15] ; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[14:15]
; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[14:15] ; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[14:15]
; GCN-IR-NEXT: BB0_6: ; %udiv-end ; GCN-IR-NEXT: .LBB0_6: ; %udiv-end
; GCN-IR-NEXT: v_mul_lo_u32 v1, s0, v1 ; GCN-IR-NEXT: v_mul_lo_u32 v1, s0, v1
; GCN-IR-NEXT: v_mul_hi_u32 v2, s0, v0 ; GCN-IR-NEXT: v_mul_hi_u32 v2, s0, v0
; GCN-IR-NEXT: v_mul_lo_u32 v3, s1, v0 ; GCN-IR-NEXT: v_mul_lo_u32 v3, s1, v0
; GCN-IR-NEXT: v_mul_lo_u32 v0, s0, v0 ; GCN-IR-NEXT: v_mul_lo_u32 v0, s0, v0
; GCN-IR-NEXT: s_mov_b32 s11, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s11, 0xf000
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v3 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GCN-IR-NEXT: v_mov_b32_e32 v2, s7 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s7
▲ Show 20 Lines • Show All 140 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[5:6] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[5:6]
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
; GCN-IR-NEXT: v_mov_b32_e32 v11, v9 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v9
; GCN-IR-NEXT: v_cndmask_b32_e64 v7, v1, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v7, v1, 0, s[4:5]
; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v0, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v0, 0, s[4:5]
; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB1_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB1_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v5 ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v5
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v6, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v6, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v5 ; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v5
; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[12:13], v[5:6] ; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[12:13], v[5:6]
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4
; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB1_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB1_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, -1, v2 ; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, -1, v2
; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, -1, v3, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, -1, v3, vcc
; GCN-IR-NEXT: v_not_b32_e32 v6, v8 ; GCN-IR-NEXT: v_not_b32_e32 v6, v8
; GCN-IR-NEXT: v_not_b32_e32 v7, v9 ; GCN-IR-NEXT: v_not_b32_e32 v7, v9
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, v6, v10 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, v6, v10
; GCN-IR-NEXT: v_lshr_b64 v[12:13], v[0:1], v12 ; GCN-IR-NEXT: v_lshr_b64 v[12:13], v[0:1], v12
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, v7, v11, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, v7, v11, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: BB1_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB1_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[12:13], v[12:13], 1 ; GCN-IR-NEXT: v_lshl_b64 v[12:13], v[12:13], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5
; GCN-IR-NEXT: v_or_b32_e32 v12, v12, v6 ; GCN-IR-NEXT: v_or_b32_e32 v12, v12, v6
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v14, v12 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v14, v12
; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v15, v13, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v15, v13, vcc
; GCN-IR-NEXT: v_or_b32_e32 v4, v10, v4 ; GCN-IR-NEXT: v_or_b32_e32 v4, v10, v4
; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v6 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v6
; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v10 ; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v10
; GCN-IR-NEXT: v_and_b32_e32 v16, v10, v3 ; GCN-IR-NEXT: v_and_b32_e32 v16, v10, v3
; GCN-IR-NEXT: v_and_b32_e32 v17, v10, v2 ; GCN-IR-NEXT: v_and_b32_e32 v17, v10, v2
; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v8 ; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v8
; GCN-IR-NEXT: v_or_b32_e32 v5, v11, v5 ; GCN-IR-NEXT: v_or_b32_e32 v5, v11, v5
; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v9, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v9, vcc
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[8:9] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[8:9]
; GCN-IR-NEXT: v_mov_b32_e32 v8, v10 ; GCN-IR-NEXT: v_mov_b32_e32 v8, v10
; GCN-IR-NEXT: v_sub_i32_e64 v12, s[4:5], v12, v17 ; GCN-IR-NEXT: v_sub_i32_e64 v12, s[4:5], v12, v17
; GCN-IR-NEXT: v_mov_b32_e32 v9, v11 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v11
; GCN-IR-NEXT: v_mov_b32_e32 v11, v7 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v7
; GCN-IR-NEXT: v_subb_u32_e64 v13, s[4:5], v13, v16, s[4:5] ; GCN-IR-NEXT: v_subb_u32_e64 v13, s[4:5], v13, v16, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v10, v6 ; GCN-IR-NEXT: v_mov_b32_e32 v10, v6
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execnz BB1_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB1_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: BB1_5: ; %Flow3 ; GCN-IR-NEXT: .LBB1_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v5 ; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v5
; GCN-IR-NEXT: v_or_b32_e32 v4, v6, v4 ; GCN-IR-NEXT: v_or_b32_e32 v4, v6, v4
; GCN-IR-NEXT: BB1_6: ; %Flow4 ; GCN-IR-NEXT: .LBB1_6: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_mul_lo_u32 v5, v2, v7 ; GCN-IR-NEXT: v_mul_lo_u32 v5, v2, v7
; GCN-IR-NEXT: v_mul_hi_u32 v6, v2, v4 ; GCN-IR-NEXT: v_mul_hi_u32 v6, v2, v4
; GCN-IR-NEXT: v_mul_lo_u32 v3, v3, v4 ; GCN-IR-NEXT: v_mul_lo_u32 v3, v3, v4
; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, v4 ; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, v4
; GCN-IR-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GCN-IR-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, v5, v3 ; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, v5, v3
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
▲ Show 20 Lines • Show All 422 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[2:3], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[12:13], s[8:9], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[12:13], s[8:9], 63
; GCN-IR-NEXT: s_mov_b64 s[4:5], 0 ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0
; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13]
; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[12:13], s[8:9], 63 ; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[12:13], s[8:9], 63
; GCN-IR-NEXT: s_xor_b64 s[14:15], s[10:11], -1 ; GCN-IR-NEXT: s_xor_b64 s[14:15], s[10:11], -1
; GCN-IR-NEXT: s_and_b64 s[12:13], s[14:15], s[12:13] ; GCN-IR-NEXT: s_and_b64 s[12:13], s[14:15], s[12:13]
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[12:13] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[12:13]
; GCN-IR-NEXT: s_cbranch_vccz BB6_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB6_5
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s10, s8, 1 ; GCN-IR-NEXT: s_add_u32 s10, s8, 1
; GCN-IR-NEXT: v_mov_b32_e32 v0, s8 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s8
; GCN-IR-NEXT: s_addc_u32 s11, s9, 0 ; GCN-IR-NEXT: s_addc_u32 s11, s9, 0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s9 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s9
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
; GCN-IR-NEXT: s_sub_i32 s7, 63, s8 ; GCN-IR-NEXT: s_sub_i32 s7, 63, s8
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_lshl_b64 s[8:9], 24, s7 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], 24, s7
; GCN-IR-NEXT: s_cbranch_vccz BB6_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB6_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[12:13], 24, s10 ; GCN-IR-NEXT: s_lshr_b64 s[12:13], 24, s10
; GCN-IR-NEXT: s_add_u32 s14, s2, -1 ; GCN-IR-NEXT: s_add_u32 s14, s2, -1
; GCN-IR-NEXT: s_addc_u32 s15, s3, -1 ; GCN-IR-NEXT: s_addc_u32 s15, s3, -1
; GCN-IR-NEXT: s_sub_u32 s6, 58, s6 ; GCN-IR-NEXT: s_sub_u32 s6, 58, s6
; GCN-IR-NEXT: s_subb_u32 s7, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s7, 0, 0
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: s_mov_b32 s5, 0 ; GCN-IR-NEXT: s_mov_b32 s5, 0
; GCN-IR-NEXT: BB6_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB6_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1 ; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1
; GCN-IR-NEXT: s_lshr_b32 s4, s9, 31 ; GCN-IR-NEXT: s_lshr_b32 s4, s9, 31
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1
; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[4:5] ; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[4:5]
; GCN-IR-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9] ; GCN-IR-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9]
; GCN-IR-NEXT: s_sub_u32 s4, s14, s12 ; GCN-IR-NEXT: s_sub_u32 s4, s14, s12
; GCN-IR-NEXT: s_subb_u32 s4, s15, s13 ; GCN-IR-NEXT: s_subb_u32 s4, s15, s13
; GCN-IR-NEXT: s_ashr_i32 s10, s4, 31 ; GCN-IR-NEXT: s_ashr_i32 s10, s4, 31
; GCN-IR-NEXT: s_mov_b32 s11, s10 ; GCN-IR-NEXT: s_mov_b32 s11, s10
; GCN-IR-NEXT: s_and_b32 s4, s10, 1 ; GCN-IR-NEXT: s_and_b32 s4, s10, 1
; GCN-IR-NEXT: s_and_b64 s[16:17], s[10:11], s[2:3] ; GCN-IR-NEXT: s_and_b64 s[16:17], s[10:11], s[2:3]
; GCN-IR-NEXT: s_sub_u32 s12, s12, s16 ; GCN-IR-NEXT: s_sub_u32 s12, s12, s16
; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
; GCN-IR-NEXT: s_subb_u32 s13, s13, s17 ; GCN-IR-NEXT: s_subb_u32 s13, s13, s17
; GCN-IR-NEXT: v_mov_b32_e32 v1, s7 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s7
; GCN-IR-NEXT: s_add_u32 s6, s6, 1 ; GCN-IR-NEXT: s_add_u32 s6, s6, 1
; GCN-IR-NEXT: s_addc_u32 s7, s7, 0 ; GCN-IR-NEXT: s_addc_u32 s7, s7, 0
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[6:7], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[6:7], v[0:1]
; GCN-IR-NEXT: s_mov_b64 s[10:11], s[4:5] ; GCN-IR-NEXT: s_mov_b64 s[10:11], s[4:5]
; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_cbranch_vccz BB6_3 ; GCN-IR-NEXT: s_cbranch_vccz .LBB6_3
; GCN-IR-NEXT: BB6_4: ; %Flow5 ; GCN-IR-NEXT: .LBB6_4: ; %Flow5
; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[8:9], 1 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[8:9], 1
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
; GCN-IR-NEXT: v_mov_b32_e32 v0, s4 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s4
; GCN-IR-NEXT: v_mov_b32_e32 v1, s5 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s5
; GCN-IR-NEXT: s_branch BB6_6 ; GCN-IR-NEXT: s_branch .LBB6_6
; GCN-IR-NEXT: BB6_5: ; GCN-IR-NEXT: .LBB6_5:
; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
; GCN-IR-NEXT: v_cndmask_b32_e64 v0, 24, 0, s[10:11] ; GCN-IR-NEXT: v_cndmask_b32_e64 v0, 24, 0, s[10:11]
; GCN-IR-NEXT: BB6_6: ; %udiv-end ; GCN-IR-NEXT: .LBB6_6: ; %udiv-end
; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v1 ; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v1
; GCN-IR-NEXT: v_mul_hi_u32 v2, s2, v0 ; GCN-IR-NEXT: v_mul_hi_u32 v2, s2, v0
; GCN-IR-NEXT: v_mul_lo_u32 v3, s3, v0 ; GCN-IR-NEXT: v_mul_lo_u32 v3, s3, v0
; GCN-IR-NEXT: v_mul_lo_u32 v0, s2, v0 ; GCN-IR-NEXT: v_mul_lo_u32 v0, s2, v0
; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v3 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 24, v0 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 24, v0
▲ Show 20 Lines • Show All 125 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[2:3], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[12:13], s[8:9], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[12:13], s[8:9], 63
; GCN-IR-NEXT: s_mov_b64 s[4:5], 0 ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0
; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13]
; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[12:13], s[8:9], 63 ; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[12:13], s[8:9], 63
; GCN-IR-NEXT: s_xor_b64 s[14:15], s[10:11], -1 ; GCN-IR-NEXT: s_xor_b64 s[14:15], s[10:11], -1
; GCN-IR-NEXT: s_and_b64 s[12:13], s[14:15], s[12:13] ; GCN-IR-NEXT: s_and_b64 s[12:13], s[14:15], s[12:13]
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[12:13] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[12:13]
; GCN-IR-NEXT: s_cbranch_vccz BB7_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB7_5
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s10, s8, 1 ; GCN-IR-NEXT: s_add_u32 s10, s8, 1
; GCN-IR-NEXT: v_mov_b32_e32 v0, s8 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s8
; GCN-IR-NEXT: s_addc_u32 s11, s9, 0 ; GCN-IR-NEXT: s_addc_u32 s11, s9, 0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s9 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s9
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
; GCN-IR-NEXT: s_sub_i32 s7, 63, s8 ; GCN-IR-NEXT: s_sub_i32 s7, 63, s8
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[2:3], s7 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[2:3], s7
; GCN-IR-NEXT: s_cbranch_vccz BB7_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB7_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[12:13], s[2:3], s10 ; GCN-IR-NEXT: s_lshr_b64 s[12:13], s[2:3], s10
; GCN-IR-NEXT: s_add_u32 s6, s6, 0xffffffc4 ; GCN-IR-NEXT: s_add_u32 s6, s6, 0xffffffc4
; GCN-IR-NEXT: s_addc_u32 s7, 0, -1 ; GCN-IR-NEXT: s_addc_u32 s7, 0, -1
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: s_mov_b32 s5, 0 ; GCN-IR-NEXT: s_mov_b32 s5, 0
; GCN-IR-NEXT: BB7_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB7_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1 ; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1
; GCN-IR-NEXT: s_lshr_b32 s4, s9, 31 ; GCN-IR-NEXT: s_lshr_b32 s4, s9, 31
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1
; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[4:5] ; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[4:5]
; GCN-IR-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9] ; GCN-IR-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9]
; GCN-IR-NEXT: s_sub_u32 s4, 23, s12 ; GCN-IR-NEXT: s_sub_u32 s4, 23, s12
; GCN-IR-NEXT: s_subb_u32 s4, 0, s13 ; GCN-IR-NEXT: s_subb_u32 s4, 0, s13
; GCN-IR-NEXT: s_ashr_i32 s10, s4, 31 ; GCN-IR-NEXT: s_ashr_i32 s10, s4, 31
; GCN-IR-NEXT: s_and_b32 s4, s10, 1 ; GCN-IR-NEXT: s_and_b32 s4, s10, 1
; GCN-IR-NEXT: s_and_b32 s10, s10, 24 ; GCN-IR-NEXT: s_and_b32 s10, s10, 24
; GCN-IR-NEXT: s_sub_u32 s12, s12, s10 ; GCN-IR-NEXT: s_sub_u32 s12, s12, s10
; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
; GCN-IR-NEXT: s_subb_u32 s13, s13, 0 ; GCN-IR-NEXT: s_subb_u32 s13, s13, 0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s7 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s7
; GCN-IR-NEXT: s_add_u32 s6, s6, 1 ; GCN-IR-NEXT: s_add_u32 s6, s6, 1
; GCN-IR-NEXT: s_addc_u32 s7, s7, 0 ; GCN-IR-NEXT: s_addc_u32 s7, s7, 0
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[6:7], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[6:7], v[0:1]
; GCN-IR-NEXT: s_mov_b64 s[10:11], s[4:5] ; GCN-IR-NEXT: s_mov_b64 s[10:11], s[4:5]
; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_cbranch_vccz BB7_3 ; GCN-IR-NEXT: s_cbranch_vccz .LBB7_3
; GCN-IR-NEXT: BB7_4: ; %Flow5 ; GCN-IR-NEXT: .LBB7_4: ; %Flow5
; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[8:9], 1 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[8:9], 1
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
; GCN-IR-NEXT: v_mov_b32_e32 v0, s4 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s4
; GCN-IR-NEXT: v_mov_b32_e32 v1, s5 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s5
; GCN-IR-NEXT: s_branch BB7_6 ; GCN-IR-NEXT: s_branch .LBB7_6
; GCN-IR-NEXT: BB7_5: ; GCN-IR-NEXT: .LBB7_5:
; GCN-IR-NEXT: v_mov_b32_e32 v0, s3 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s3
; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[10:11] ; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v0, s2 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s2
; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[10:11] ; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[10:11]
; GCN-IR-NEXT: BB7_6: ; %udiv-end ; GCN-IR-NEXT: .LBB7_6: ; %udiv-end
; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, 24 ; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, 24
; GCN-IR-NEXT: v_mul_hi_u32 v2, v0, 24 ; GCN-IR-NEXT: v_mul_hi_u32 v2, v0, 24
; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, 24 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, 24
; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: s_mov_b32 s6, -1
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GCN-IR-NEXT: v_mov_b32_e32 v2, s3 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s3
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s2, v0 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
▲ Show 20 Lines • Show All 124 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[2:3] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[2:3]
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[4:5]
; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1
; GCN-IR-NEXT: v_mov_b32_e32 v5, v7 ; GCN-IR-NEXT: v_mov_b32_e32 v5, v7
; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB8_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB8_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v2 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v2
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v3, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v3, vcc
; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[8:9], v[2:3] ; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[8:9], v[2:3]
; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2
; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[8:9], v2 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[8:9], v2
; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB8_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB8_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0
; GCN-IR-NEXT: s_mov_b64 s[4:5], 0x8000 ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0x8000
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc
; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[4:5], v8 ; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[4:5], v8
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 47, v6 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 47, v6
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_subb_u32_e32 v7, vcc, 0, v7, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v7, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: BB8_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB8_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 ; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4 ; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v12, v8 ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v12, v8
; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, v13, v9, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, v13, v9, vcc
; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2 ; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2
; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4
; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10 ; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10
; GCN-IR-NEXT: v_and_b32_e32 v14, v10, v1 ; GCN-IR-NEXT: v_and_b32_e32 v14, v10, v1
; GCN-IR-NEXT: v_and_b32_e32 v15, v10, v0 ; GCN-IR-NEXT: v_and_b32_e32 v15, v10, v0
; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v6 ; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v6
; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3 ; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3
; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v7, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[6:7] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[6:7]
; GCN-IR-NEXT: v_mov_b32_e32 v6, v10 ; GCN-IR-NEXT: v_mov_b32_e32 v6, v10
; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v8, v15 ; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v8, v15
; GCN-IR-NEXT: v_mov_b32_e32 v7, v11 ; GCN-IR-NEXT: v_mov_b32_e32 v7, v11
; GCN-IR-NEXT: v_mov_b32_e32 v11, v5 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v5
; GCN-IR-NEXT: v_subb_u32_e64 v9, s[4:5], v9, v14, s[4:5] ; GCN-IR-NEXT: v_subb_u32_e64 v9, s[4:5], v9, v14, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v10, v4 ; GCN-IR-NEXT: v_mov_b32_e32 v10, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execnz BB8_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB8_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: BB8_5: ; %Flow3 ; GCN-IR-NEXT: .LBB8_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v3 ; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v3
; GCN-IR-NEXT: v_or_b32_e32 v4, v4, v2 ; GCN-IR-NEXT: v_or_b32_e32 v4, v4, v2
; GCN-IR-NEXT: BB8_6: ; %Flow4 ; GCN-IR-NEXT: .LBB8_6: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_mul_lo_u32 v2, v0, v5 ; GCN-IR-NEXT: v_mul_lo_u32 v2, v0, v5
; GCN-IR-NEXT: v_mul_hi_u32 v3, v0, v4 ; GCN-IR-NEXT: v_mul_hi_u32 v3, v0, v4
; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, v4 ; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, v4
; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, v4 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, v4
; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 0x8000, v0 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 0x8000, v0
Show All 24 Lines
; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[2:3] ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[2:3]
; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[2:3] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[2:3]
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v1, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v1, 0, s[4:5]
; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v0, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v0, 0, s[4:5]
; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB9_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB9_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v2 ; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v2
; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v3, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v3, vcc
; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[7:8], v[2:3] ; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[7:8], v[2:3]
; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2
; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB9_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB9_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_lshr_b64 v[8:9], v[0:1], v7 ; GCN-IR-NEXT: v_lshr_b64 v[8:9], v[0:1], v7
; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 0xffffffcf, v6 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 0xffffffcf, v6
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_addc_u32_e64 v7, s[4:5], 0, -1, vcc ; GCN-IR-NEXT: v_addc_u32_e64 v7, s[4:5], 0, -1, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff ; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff
; GCN-IR-NEXT: BB9_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB9_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 ; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4 ; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, s12, v8 ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, s12, v8
; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v9, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v9, vcc
; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2 ; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2
; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4
; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10 ; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10
; GCN-IR-NEXT: v_and_b32_e32 v12, 0x8000, v10 ; GCN-IR-NEXT: v_and_b32_e32 v12, 0x8000, v10
; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v6 ; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v6
; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3 ; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3
; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v7, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[6:7] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[6:7]
; GCN-IR-NEXT: v_mov_b32_e32 v6, v10 ; GCN-IR-NEXT: v_mov_b32_e32 v6, v10
; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v8, v12 ; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v8, v12
; GCN-IR-NEXT: v_mov_b32_e32 v7, v11 ; GCN-IR-NEXT: v_mov_b32_e32 v7, v11
; GCN-IR-NEXT: v_mov_b32_e32 v11, v5 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v5
; GCN-IR-NEXT: v_subbrev_u32_e64 v9, s[4:5], 0, v9, s[4:5] ; GCN-IR-NEXT: v_subbrev_u32_e64 v9, s[4:5], 0, v9, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v10, v4 ; GCN-IR-NEXT: v_mov_b32_e32 v10, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execnz BB9_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB9_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: BB9_5: ; %Flow3 ; GCN-IR-NEXT: .LBB9_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v3 ; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v3
; GCN-IR-NEXT: v_or_b32_e32 v4, v4, v2 ; GCN-IR-NEXT: v_or_b32_e32 v4, v4, v2
; GCN-IR-NEXT: BB9_6: ; %Flow4 ; GCN-IR-NEXT: .LBB9_6: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[4:5], 15 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[4:5], 15
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
; GCN-IR-NEXT: s_setpc_b64 s[30:31] ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = urem i64 %x, 32768 %result = urem i64 %x, 32768
ret i64 %result ret i64 %result
} }
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llvm/test/CodeGen/AMDGPU/valu-i1.ll

; RUN: llc -march=amdgcn -verify-machineinstrs -enable-misched -asm-verbose -disable-block-placement -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -verify-machineinstrs -enable-misched -asm-verbose -disable-block-placement -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=SI %s
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
; SI-LABEL: {{^}}test_if: ; SI-LABEL: {{^}}test_if:
; Make sure the i1 values created by the cfg structurizer pass are ; Make sure the i1 values created by the cfg structurizer pass are
; moved using VALU instructions ; moved using VALU instructions
; waitcnt should be inserted after exec modification ; waitcnt should be inserted after exec modification
; SI: v_cmp_lt_i32_e32 vcc, 1, ; SI: v_cmp_lt_i32_e32 vcc, 1,
; SI-NEXT: s_mov_b64 {{s\[[0-9]+:[0-9]+\]}}, 0 ; SI-NEXT: s_mov_b64 {{s\[[0-9]+:[0-9]+\]}}, 0
; SI-NEXT: s_mov_b64 {{s\[[0-9]+:[0-9]+\]}}, 0 ; SI-NEXT: s_mov_b64 {{s\[[0-9]+:[0-9]+\]}}, 0
; SI-NEXT: s_and_saveexec_b64 [[SAVE1:s\[[0-9]+:[0-9]+\]]], vcc ; SI-NEXT: s_and_saveexec_b64 [[SAVE1:s\[[0-9]+:[0-9]+\]]], vcc
; SI-NEXT: s_xor_b64 [[SAVE2:s\[[0-9]+:[0-9]+\]]], exec, [[SAVE1]] ; SI-NEXT: s_xor_b64 [[SAVE2:s\[[0-9]+:[0-9]+\]]], exec, [[SAVE1]]
; SI-NEXT: s_cbranch_execz [[FLOW_BB:BB[0-9]+_[0-9]+]] ; SI-NEXT: s_cbranch_execz [[FLOW_BB:.LBB[0-9]+_[0-9]+]]
; SI-NEXT: ; %bb.{{[0-9]+}}: ; %LeafBlock3 ; SI-NEXT: ; %bb.{{[0-9]+}}: ; %LeafBlock3
; SI: s_mov_b64 s[{{[0-9]:[0-9]}}], -1 ; SI: s_mov_b64 s[{{[0-9]:[0-9]}}], -1
; SI: s_and_saveexec_b64 ; SI: s_and_saveexec_b64
; SI-NEXT: s_cbranch_execnz ; SI-NEXT: s_cbranch_execnz
; v_mov should be after exec modification ; v_mov should be after exec modification
; SI: [[FLOW_BB]]: ; SI: [[FLOW_BB]]:
Show All 33 Lines
end: end:
ret void ret void
} }
; SI-LABEL: {{^}}simple_test_v_if: ; SI-LABEL: {{^}}simple_test_v_if:
; SI: v_cmp_ne_u32_e32 vcc, 0, v{{[0-9]+}} ; SI: v_cmp_ne_u32_e32 vcc, 0, v{{[0-9]+}}
; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc ; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc
; SI-NEXT: s_cbranch_execz [[EXIT:BB[0-9]+_[0-9]+]] ; SI-NEXT: s_cbranch_execz [[EXIT:.LBB[0-9]+_[0-9]+]]
; SI-NEXT: ; %bb.{{[0-9]+}}: ; SI-NEXT: ; %bb.{{[0-9]+}}:
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI-NEXT: {{^}}[[EXIT]]: ; SI-NEXT: {{^}}[[EXIT]]:
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @simple_test_v_if(i32 addrspace(1)* %dst, i32 addrspace(1)* %src) #1 { define amdgpu_kernel void @simple_test_v_if(i32 addrspace(1)* %dst, i32 addrspace(1)* %src) #1 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
Show All 9 Linesexit:
ret void ret void
} }
; FIXME: It would be better to endpgm in the then block. ; FIXME: It would be better to endpgm in the then block.
; SI-LABEL: {{^}}simple_test_v_if_ret_else_ret: ; SI-LABEL: {{^}}simple_test_v_if_ret_else_ret:
; SI: v_cmp_ne_u32_e32 vcc, 0, v{{[0-9]+}} ; SI: v_cmp_ne_u32_e32 vcc, 0, v{{[0-9]+}}
; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc ; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc
; SI-NEXT: s_cbranch_execz [[EXIT:BB[0-9]+_[0-9]+]] ; SI-NEXT: s_cbranch_execz [[EXIT:.LBB[0-9]+_[0-9]+]]
; SI-NEXT: ; %bb.{{[0-9]+}}: ; SI-NEXT: ; %bb.{{[0-9]+}}:
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI-NEXT: {{^}}[[EXIT]]: ; SI-NEXT: {{^}}[[EXIT]]:
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @simple_test_v_if_ret_else_ret(i32 addrspace(1)* %dst, i32 addrspace(1)* %src) #1 { define amdgpu_kernel void @simple_test_v_if_ret_else_ret(i32 addrspace(1)* %dst, i32 addrspace(1)* %src) #1 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
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; Final block has more than a ret to execute. This was miscompiled ; Final block has more than a ret to execute. This was miscompiled
; before function exit blocks were unified since the endpgm would ; before function exit blocks were unified since the endpgm would
; terminate the then wavefront before reaching the store. ; terminate the then wavefront before reaching the store.
; SI-LABEL: {{^}}simple_test_v_if_ret_else_code_ret: ; SI-LABEL: {{^}}simple_test_v_if_ret_else_code_ret:
; SI: v_cmp_eq_u32_e32 vcc, 0, v{{[0-9]+}} ; SI: v_cmp_eq_u32_e32 vcc, 0, v{{[0-9]+}}
; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc ; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc
; SI: s_xor_b64 [[BR_SREG]], exec, [[BR_SREG]] ; SI: s_xor_b64 [[BR_SREG]], exec, [[BR_SREG]]
; SI: s_cbranch_execnz [[EXIT:BB[0-9]+_[0-9]+]] ; SI: s_cbranch_execnz [[EXIT:.LBB[0-9]+_[0-9]+]]
; SI-NEXT: {{^BB[0-9]+_[0-9]+}}: ; %Flow ; SI-NEXT: {{^.LBB[0-9]+_[0-9]+}}: ; %Flow
; SI-NEXT: s_or_saveexec_b64 ; SI-NEXT: s_or_saveexec_b64
; SI-NEXT: s_xor_b64 exec, exec ; SI-NEXT: s_xor_b64 exec, exec
; SI-NEXT: s_cbranch_execz [[UNIFIED_RETURN:BB[0-9]+_[0-9]+]] ; SI-NEXT: s_cbranch_execz [[UNIFIED_RETURN:.LBB[0-9]+_[0-9]+]]
; SI-NEXT: ; %bb.{{[0-9]+}}: ; %then ; SI-NEXT: ; %bb.{{[0-9]+}}: ; %then
; SI: s_waitcnt ; SI: s_waitcnt
; SI-NEXT: buffer_store_dword ; SI-NEXT: buffer_store_dword
; SI-NEXT: {{^}}[[UNIFIED_RETURN]]: ; %UnifiedReturnBlock ; SI-NEXT: {{^}}[[UNIFIED_RETURN]]: ; %UnifiedReturnBlock
; SI: s_endpgm ; SI: s_endpgm
Show All 12 Lines
exit: exit:
store volatile i32 7, i32 addrspace(3)* undef store volatile i32 7, i32 addrspace(3)* undef
ret void ret void
} }
; SI-LABEL: {{^}}simple_test_v_loop: ; SI-LABEL: {{^}}simple_test_v_loop:
; SI: v_cmp_ne_u32_e32 vcc, 0, v{{[0-9]+}} ; SI: v_cmp_ne_u32_e32 vcc, 0, v{{[0-9]+}}
; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc ; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc
; SI-NEXT: s_cbranch_execz [[LABEL_EXIT:BB[0-9]+_[0-9]+]] ; SI-NEXT: s_cbranch_execz [[LABEL_EXIT:.LBB[0-9]+_[0-9]+]]
; SI: s_mov_b64 {{s\[[0-9]+:[0-9]+\]}}, 0{{$}} ; SI: s_mov_b64 {{s\[[0-9]+:[0-9]+\]}}, 0{{$}}
; SI: [[LABEL_LOOP:BB[0-9]+_[0-9]+]]: ; SI: [[LABEL_LOOP:.LBB[0-9]+_[0-9]+]]:
; SI: buffer_load_dword ; SI: buffer_load_dword
; SI-DAG: buffer_store_dword ; SI-DAG: buffer_store_dword
; SI-DAG: s_cmpk_lg_i32 s{{[0-9]+}}, 0x100 ; SI-DAG: s_cmpk_lg_i32 s{{[0-9]+}}, 0x100
; SI: s_cbranch_scc1 [[LABEL_LOOP]] ; SI: s_cbranch_scc1 [[LABEL_LOOP]]
; SI: [[LABEL_EXIT]]: ; SI: [[LABEL_EXIT]]:
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @simple_test_v_loop(i32 addrspace(1)* %dst, i32 addrspace(1)* %src) #1 { define amdgpu_kernel void @simple_test_v_loop(i32 addrspace(1)* %dst, i32 addrspace(1)* %src) #1 {
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; SI-LABEL: {{^}}multi_vcond_loop: ; SI-LABEL: {{^}}multi_vcond_loop:
; Load loop limit from buffer ; Load loop limit from buffer
; Branch to exit if uniformly not taken ; Branch to exit if uniformly not taken
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI: buffer_load_dword [[VBOUND:v[0-9]+]] ; SI: buffer_load_dword [[VBOUND:v[0-9]+]]
; SI: v_cmp_lt_i32_e32 vcc ; SI: v_cmp_lt_i32_e32 vcc
; SI: s_and_saveexec_b64 [[OUTER_CMP_SREG:s\[[0-9]+:[0-9]+\]]], vcc ; SI: s_and_saveexec_b64 [[OUTER_CMP_SREG:s\[[0-9]+:[0-9]+\]]], vcc
; SI-NEXT: s_cbranch_execz [[LABEL_EXIT:BB[0-9]+_[0-9]+]] ; SI-NEXT: s_cbranch_execz [[LABEL_EXIT:.LBB[0-9]+_[0-9]+]]
; Initialize inner condition to false ; Initialize inner condition to false
; SI: ; %bb.{{[0-9]+}}: ; %bb10.preheader ; SI: ; %bb.{{[0-9]+}}: ; %bb10.preheader
; SI: s_mov_b64 [[COND_STATE:s\[[0-9]+:[0-9]+\]]], 0{{$}} ; SI: s_mov_b64 [[COND_STATE:s\[[0-9]+:[0-9]+\]]], 0{{$}}
; Clear exec bits for workitems that load -1s ; Clear exec bits for workitems that load -1s
; SI: [[LABEL_LOOP:BB[0-9]+_[0-9]+]]: ; SI: .L[[LABEL_LOOP:BB[0-9]+_[0-9]+]]:
; SI: buffer_load_dword [[B:v[0-9]+]] ; SI: buffer_load_dword [[B:v[0-9]+]]
; SI: buffer_load_dword [[A:v[0-9]+]] ; SI: buffer_load_dword [[A:v[0-9]+]]
; SI-DAG: v_cmp_ne_u32_e64 [[NEG1_CHECK_0:s\[[0-9]+:[0-9]+\]]], -1, [[A]] ; SI-DAG: v_cmp_ne_u32_e64 [[NEG1_CHECK_0:s\[[0-9]+:[0-9]+\]]], -1, [[A]]
; SI-DAG: v_cmp_ne_u32_e32 [[NEG1_CHECK_1:vcc]], -1, [[B]] ; SI-DAG: v_cmp_ne_u32_e32 [[NEG1_CHECK_1:vcc]], -1, [[B]]
; SI: s_and_b64 [[ORNEG1:s\[[0-9]+:[0-9]+\]]], [[NEG1_CHECK_1]], [[NEG1_CHECK_0]] ; SI: s_and_b64 [[ORNEG1:s\[[0-9]+:[0-9]+\]]], [[NEG1_CHECK_1]], [[NEG1_CHECK_0]]
; SI: s_and_saveexec_b64 [[ORNEG2:s\[[0-9]+:[0-9]+\]]], [[ORNEG1]] ; SI: s_and_saveexec_b64 [[ORNEG2:s\[[0-9]+:[0-9]+\]]], [[ORNEG1]]
; SI: s_cbranch_execz [[LABEL_FLOW:BB[0-9]+_[0-9]+]] ; SI: s_cbranch_execz [[LABEL_FLOW:.LBB[0-9]+_[0-9]+]]
; SI: ; %bb.{{[0-9]+}}: ; %bb20 ; SI: ; %bb.{{[0-9]+}}: ; %bb20
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: [[LABEL_FLOW]]: ; SI: [[LABEL_FLOW]]:
; SI-NEXT: ; in Loop: Header=[[LABEL_LOOP]] ; SI-NEXT: ; in Loop: Header=[[LABEL_LOOP]]
; SI-NEXT: s_or_b64 exec, exec, [[ORNEG2]] ; SI-NEXT: s_or_b64 exec, exec, [[ORNEG2]]
; SI-NEXT: s_and_b64 [[TMP1:s\[[0-9]+:[0-9]+\]]], ; SI-NEXT: s_and_b64 [[TMP1:s\[[0-9]+:[0-9]+\]]],
; SI-NEXT: s_or_b64 [[COND_STATE]], [[TMP1]], [[COND_STATE]] ; SI-NEXT: s_or_b64 [[COND_STATE]], [[TMP1]], [[COND_STATE]]
; SI-NEXT: s_andn2_b64 exec, exec, [[COND_STATE]] ; SI-NEXT: s_andn2_b64 exec, exec, [[COND_STATE]]
; SI-NEXT: s_cbranch_execnz [[LABEL_LOOP]] ; SI-NEXT: s_cbranch_execnz .L[[LABEL_LOOP]]
; SI: [[LABEL_EXIT]]: ; SI: [[LABEL_EXIT]]:
; SI-NOT: [[COND_STATE]] ; SI-NOT: [[COND_STATE]]
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @multi_vcond_loop(i32 addrspace(1)* noalias nocapture %arg, i32 addrspace(1)* noalias nocapture readonly %arg1, i32 addrspace(1)* noalias nocapture readonly %arg2, i32 addrspace(1)* noalias nocapture readonly %arg3) #1 { define amdgpu_kernel void @multi_vcond_loop(i32 addrspace(1)* noalias nocapture %arg, i32 addrspace(1)* noalias nocapture readonly %arg1, i32 addrspace(1)* noalias nocapture readonly %arg2, i32 addrspace(1)* noalias nocapture readonly %arg3) #1 {
bb: bb:
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0
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llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -march=amdgcn -mcpu=gfx1010 | FileCheck %s --check-prefix=GCN ; RUN: llc < %s -march=amdgcn -mcpu=gfx1010 | FileCheck %s --check-prefix=GCN
define void @vgpr_descriptor_waterfall_loop_idom_update(<4 x i32>* %arg) #0 { define void @vgpr_descriptor_waterfall_loop_idom_update(<4 x i32>* %arg) #0 {
; GCN-LABEL: vgpr_descriptor_waterfall_loop_idom_update: ; GCN-LABEL: vgpr_descriptor_waterfall_loop_idom_update:
; GCN: ; %bb.0: ; %entry ; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_waitcnt_vscnt null, 0x0 ; GCN-NEXT: s_waitcnt_vscnt null, 0x0
; GCN-NEXT: v_add_co_u32 v6, vcc_lo, v0, 8 ; GCN-NEXT: v_add_co_u32 v6, vcc_lo, v0, 8
; GCN-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo ; GCN-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
; GCN-NEXT: BB0_1: ; %bb0 ; GCN-NEXT: .LBB0_1: ; %bb0
; GCN-NEXT: ; =>This Loop Header: Depth=1 ; GCN-NEXT: ; =>This Loop Header: Depth=1
; GCN-NEXT: ; Child Loop BB0_2 Depth 2 ; GCN-NEXT: ; Child Loop BB0_2 Depth 2
; GCN-NEXT: s_clause 0x1 ; GCN-NEXT: s_clause 0x1
; GCN-NEXT: flat_load_dwordx2 v[4:5], v[6:7] ; GCN-NEXT: flat_load_dwordx2 v[4:5], v[6:7]
; GCN-NEXT: flat_load_dwordx2 v[2:3], v[0:1] ; GCN-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
; GCN-NEXT: s_mov_b32 s5, exec_lo ; GCN-NEXT: s_mov_b32 s5, exec_lo
; GCN-NEXT: BB0_2: ; Parent Loop BB0_1 Depth=1 ; GCN-NEXT: .LBB0_2: ; Parent Loop BB0_1 Depth=1
; GCN-NEXT: ; => This Inner Loop Header: Depth=2 ; GCN-NEXT: ; => This Inner Loop Header: Depth=2
; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN-NEXT: v_readfirstlane_b32 s8, v2 ; GCN-NEXT: v_readfirstlane_b32 s8, v2
; GCN-NEXT: v_readfirstlane_b32 s9, v3 ; GCN-NEXT: v_readfirstlane_b32 s9, v3
; GCN-NEXT: v_readfirstlane_b32 s10, v4 ; GCN-NEXT: v_readfirstlane_b32 s10, v4
; GCN-NEXT: v_readfirstlane_b32 s11, v5 ; GCN-NEXT: v_readfirstlane_b32 s11, v5
; GCN-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[8:9], v[2:3] ; GCN-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[8:9], v[2:3]
; GCN-NEXT: v_cmp_eq_u64_e64 s4, s[10:11], v[4:5] ; GCN-NEXT: v_cmp_eq_u64_e64 s4, s[10:11], v[4:5]
; GCN-NEXT: s_and_b32 s4, vcc_lo, s4 ; GCN-NEXT: s_and_b32 s4, vcc_lo, s4
; GCN-NEXT: s_and_saveexec_b32 s4, s4 ; GCN-NEXT: s_and_saveexec_b32 s4, s4
; GCN-NEXT: buffer_store_dword v0, v0, s[8:11], 0 offen ; GCN-NEXT: buffer_store_dword v0, v0, s[8:11], 0 offen
; GCN-NEXT: ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5 ; GCN-NEXT: ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5
; GCN-NEXT: s_waitcnt_depctr 0xffe3 ; GCN-NEXT: s_waitcnt_depctr 0xffe3
; GCN-NEXT: s_xor_b32 exec_lo, exec_lo, s4 ; GCN-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GCN-NEXT: s_cbranch_execnz BB0_2 ; GCN-NEXT: s_cbranch_execnz .LBB0_2
; GCN-NEXT: ; %bb.3: ; in Loop: Header=BB0_1 Depth=1 ; GCN-NEXT: ; %bb.3: ; in Loop: Header=BB0_1 Depth=1
; GCN-NEXT: s_mov_b32 exec_lo, s5 ; GCN-NEXT: s_mov_b32 exec_lo, s5
; GCN-NEXT: s_branch BB0_1 ; GCN-NEXT: s_branch .LBB0_1
entry: entry:
br label %bb0 br label %bb0
bb0: bb0:
%desc = load <4 x i32>, <4 x i32>* %arg, align 8 %desc = load <4 x i32>, <4 x i32>* %arg, align 8
tail call void @llvm.amdgcn.raw.buffer.store.f32(float undef, <4 x i32> %desc, i32 undef, i32 0, i32 0) tail call void @llvm.amdgcn.raw.buffer.store.f32(float undef, <4 x i32> %desc, i32 undef, i32 0, i32 0)
br label %bb0 br label %bb0
} }
declare void @llvm.amdgcn.raw.buffer.store.f32(float, <4 x i32>, i32, i32, i32 immarg) #0 declare void @llvm.amdgcn.raw.buffer.store.f32(float, <4 x i32>, i32, i32, i32 immarg) #0
attributes #0 = { nounwind writeonly } attributes #0 = { nounwind writeonly }

llvm/test/CodeGen/AMDGPU/vgpr-liverange.ll

Show First 20 Lines • Show All 77 Lines • ▼ Show 20 Lines
} }
; if-else inside loop, %x can be optimized, but %v cannot be. ; if-else inside loop, %x can be optimized, but %v cannot be.
define amdgpu_ps float @else3(i32 %z, float %v, i32 inreg %bound, i32 %x0) #0 { define amdgpu_ps float @else3(i32 %z, float %v, i32 inreg %bound, i32 %x0) #0 {
; SI-LABEL: else3: ; SI-LABEL: else3:
; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: v_cmp_gt_i32_e32 vcc_lo, 6, v0 ; SI-NEXT: v_cmp_gt_i32_e32 vcc_lo, 6, v0
; SI-NEXT: s_mov_b32 s1, 0 ; SI-NEXT: s_mov_b32 s1, 0
; SI-NEXT: s_branch BB2_2 ; SI-NEXT: s_branch .LBB2_2
; SI-NEXT: BB2_1: ; %if.end ; SI-NEXT: .LBB2_1: ; %if.end
; SI-NEXT: ; in Loop: Header=BB2_2 Depth=1 ; SI-NEXT: ; in Loop: Header=BB2_2 Depth=1
; SI-NEXT: s_or_b32 exec_lo, exec_lo, s2 ; SI-NEXT: s_or_b32 exec_lo, exec_lo, s2
; SI-NEXT: v_add_nc_u32_e32 v2, 1, v0 ; SI-NEXT: v_add_nc_u32_e32 v2, 1, v0
; SI-NEXT: s_add_i32 s1, s1, 1 ; SI-NEXT: s_add_i32 s1, s1, 1
; SI-NEXT: s_cmp_lt_i32 s1, s0 ; SI-NEXT: s_cmp_lt_i32 s1, s0
; SI-NEXT: s_cbranch_scc0 BB2_6 ; SI-NEXT: s_cbranch_scc0 .LBB2_6
; SI-NEXT: BB2_2: ; %for.body ; SI-NEXT: .LBB2_2: ; %for.body
; SI-NEXT: ; =>This Inner Loop Header: Depth=1 ; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: ; implicit-def: $vgpr0 ; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr3 ; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: s_and_saveexec_b32 s2, vcc_lo ; SI-NEXT: s_and_saveexec_b32 s2, vcc_lo
; SI-NEXT: s_xor_b32 s2, exec_lo, s2 ; SI-NEXT: s_xor_b32 s2, exec_lo, s2
; SI-NEXT: ; %bb.3: ; %else ; SI-NEXT: ; %bb.3: ; %else
; SI-NEXT: ; in Loop: Header=BB2_2 Depth=1 ; SI-NEXT: ; in Loop: Header=BB2_2 Depth=1
; SI-NEXT: v_mul_lo_u32 v0, v2, 3 ; SI-NEXT: v_mul_lo_u32 v0, v2, 3
; SI-NEXT: v_mul_f32_e32 v3, v1, v2 ; SI-NEXT: v_mul_f32_e32 v3, v1, v2
; SI-NEXT: ; implicit-def: $vgpr2 ; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; %bb.4: ; %Flow ; SI-NEXT: ; %bb.4: ; %Flow
; SI-NEXT: ; in Loop: Header=BB2_2 Depth=1 ; SI-NEXT: ; in Loop: Header=BB2_2 Depth=1
; SI-NEXT: s_or_saveexec_b32 s2, s2 ; SI-NEXT: s_or_saveexec_b32 s2, s2
; SI-NEXT: s_xor_b32 exec_lo, exec_lo, s2 ; SI-NEXT: s_xor_b32 exec_lo, exec_lo, s2
; SI-NEXT: s_cbranch_execz BB2_1 ; SI-NEXT: s_cbranch_execz .LBB2_1
; SI-NEXT: ; %bb.5: ; %if ; SI-NEXT: ; %bb.5: ; %if
; SI-NEXT: ; in Loop: Header=BB2_2 Depth=1 ; SI-NEXT: ; in Loop: Header=BB2_2 Depth=1
; SI-NEXT: v_mul_f32_e32 v3, s1, v1 ; SI-NEXT: v_mul_f32_e32 v3, s1, v1
; SI-NEXT: v_add_nc_u32_e32 v0, 1, v2 ; SI-NEXT: v_add_nc_u32_e32 v0, 1, v2
; SI-NEXT: s_branch BB2_1 ; SI-NEXT: s_branch .LBB2_1
; SI-NEXT: BB2_6: ; %for.end ; SI-NEXT: .LBB2_6: ; %for.end
; SI-NEXT: v_add_f32_e32 v0, v0, v3 ; SI-NEXT: v_add_f32_e32 v0, v0, v3
; SI-NEXT: ; return to shader part epilog ; SI-NEXT: ; return to shader part epilog
entry: entry:
; %break = icmp sgt i32 %bound, 0 ; %break = icmp sgt i32 %bound, 0
; br i1 %break, label %for.body, label %for.end ; br i1 %break, label %for.body, label %for.end
br label %for.body br label %for.body
for.body: for.body:
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; SI-NEXT: v_cmp_gt_i32_e32 vcc_lo, 6, v6 ; SI-NEXT: v_cmp_gt_i32_e32 vcc_lo, 6, v6
; SI-NEXT: s_mov_b32 s15, 0x31c16000 ; SI-NEXT: s_mov_b32 s15, 0x31c16000
; SI-NEXT: s_add_u32 s12, s12, s1 ; SI-NEXT: s_add_u32 s12, s12, s1
; SI-NEXT: s_addc_u32 s13, s13, 0 ; SI-NEXT: s_addc_u32 s13, s13, 0
; SI-NEXT: s_mov_b32 s32, 0 ; SI-NEXT: s_mov_b32 s32, 0
; SI-NEXT: ; implicit-def: $vgpr1 ; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: s_and_saveexec_b32 s0, vcc_lo ; SI-NEXT: s_and_saveexec_b32 s0, vcc_lo
; SI-NEXT: s_xor_b32 s4, exec_lo, s0 ; SI-NEXT: s_xor_b32 s4, exec_lo, s0
; SI-NEXT: s_cbranch_execz BB3_4 ; SI-NEXT: s_cbranch_execz .LBB3_4
; SI-NEXT: ; %bb.1: ; %else ; SI-NEXT: ; %bb.1: ; %else
; SI-NEXT: s_mov_b32 s5, exec_lo ; SI-NEXT: s_mov_b32 s5, exec_lo
; SI-NEXT: BB3_2: ; =>This Inner Loop Header: Depth=1 ; SI-NEXT: .LBB3_2: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_readfirstlane_b32 s6, v4 ; SI-NEXT: v_readfirstlane_b32 s6, v4
; SI-NEXT: v_readfirstlane_b32 s7, v5 ; SI-NEXT: v_readfirstlane_b32 s7, v5
; SI-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[6:7], v[4:5] ; SI-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[6:7], v[4:5]
; SI-NEXT: s_and_saveexec_b32 s8, vcc_lo ; SI-NEXT: s_and_saveexec_b32 s8, vcc_lo
; SI-NEXT: s_mov_b64 s[0:1], s[12:13] ; SI-NEXT: s_mov_b64 s[0:1], s[12:13]
; SI-NEXT: s_mov_b64 s[2:3], s[14:15] ; SI-NEXT: s_mov_b64 s[2:3], s[14:15]
; SI-NEXT: s_swappc_b64 s[30:31], s[6:7] ; SI-NEXT: s_swappc_b64 s[30:31], s[6:7]
; SI-NEXT: v_mov_b32_e32 v1, v0 ; SI-NEXT: v_mov_b32_e32 v1, v0
; SI-NEXT: ; implicit-def: $vgpr4_vgpr5 ; SI-NEXT: ; implicit-def: $vgpr4_vgpr5
; SI-NEXT: ; implicit-def: $vgpr0 ; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: s_xor_b32 exec_lo, exec_lo, s8 ; SI-NEXT: s_xor_b32 exec_lo, exec_lo, s8
; SI-NEXT: s_cbranch_execnz BB3_2 ; SI-NEXT: s_cbranch_execnz .LBB3_2
; SI-NEXT: ; %bb.3: ; SI-NEXT: ; %bb.3:
; SI-NEXT: s_mov_b32 exec_lo, s5 ; SI-NEXT: s_mov_b32 exec_lo, s5
; SI-NEXT: ; implicit-def: $vgpr0 ; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr2 ; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: BB3_4: ; %Flow ; SI-NEXT: .LBB3_4: ; %Flow
; SI-NEXT: s_or_saveexec_b32 s4, s4 ; SI-NEXT: s_or_saveexec_b32 s4, s4
; SI-NEXT: s_xor_b32 exec_lo, exec_lo, s4 ; SI-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; SI-NEXT: s_cbranch_execz BB3_8 ; SI-NEXT: s_cbranch_execz .LBB3_8
; SI-NEXT: ; %bb.5: ; %if ; SI-NEXT: ; %bb.5: ; %if
; SI-NEXT: s_mov_b32 s5, exec_lo ; SI-NEXT: s_mov_b32 s5, exec_lo
; SI-NEXT: BB3_6: ; =>This Inner Loop Header: Depth=1 ; SI-NEXT: .LBB3_6: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_readfirstlane_b32 s6, v2 ; SI-NEXT: v_readfirstlane_b32 s6, v2
; SI-NEXT: v_readfirstlane_b32 s7, v3 ; SI-NEXT: v_readfirstlane_b32 s7, v3
; SI-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[6:7], v[2:3] ; SI-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[6:7], v[2:3]
; SI-NEXT: s_and_saveexec_b32 s8, vcc_lo ; SI-NEXT: s_and_saveexec_b32 s8, vcc_lo
; SI-NEXT: s_mov_b64 s[0:1], s[12:13] ; SI-NEXT: s_mov_b64 s[0:1], s[12:13]
; SI-NEXT: s_mov_b64 s[2:3], s[14:15] ; SI-NEXT: s_mov_b64 s[2:3], s[14:15]
; SI-NEXT: s_swappc_b64 s[30:31], s[6:7] ; SI-NEXT: s_swappc_b64 s[30:31], s[6:7]
; SI-NEXT: v_mov_b32_e32 v1, v0 ; SI-NEXT: v_mov_b32_e32 v1, v0
; SI-NEXT: ; implicit-def: $vgpr2_vgpr3 ; SI-NEXT: ; implicit-def: $vgpr2_vgpr3
; SI-NEXT: ; implicit-def: $vgpr0 ; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: s_xor_b32 exec_lo, exec_lo, s8 ; SI-NEXT: s_xor_b32 exec_lo, exec_lo, s8
; SI-NEXT: s_cbranch_execnz BB3_6 ; SI-NEXT: s_cbranch_execnz .LBB3_6
; SI-NEXT: ; %bb.7: ; SI-NEXT: ; %bb.7:
; SI-NEXT: s_mov_b32 exec_lo, s5 ; SI-NEXT: s_mov_b32 exec_lo, s5
; SI-NEXT: BB3_8: ; %end ; SI-NEXT: .LBB3_8: ; %end
; SI-NEXT: s_or_b32 exec_lo, exec_lo, s4 ; SI-NEXT: s_or_b32 exec_lo, exec_lo, s4
; SI-NEXT: v_mov_b32_e32 v0, v1 ; SI-NEXT: v_mov_b32_e32 v0, v1
; SI-NEXT: ; return to shader part epilog ; SI-NEXT: ; return to shader part epilog
main_body: main_body:
%cc = icmp sgt i32 %z, 5 %cc = icmp sgt i32 %z, 5
br i1 %cc, label %if, label %else br i1 %cc, label %if, label %else
if: if:
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; SI-NEXT: v_cmp_gt_i32_e32 vcc_lo, 6, v0 ; SI-NEXT: v_cmp_gt_i32_e32 vcc_lo, 6, v0
; SI-NEXT: s_mov_b32 s15, 0x31c16000 ; SI-NEXT: s_mov_b32 s15, 0x31c16000
; SI-NEXT: s_add_u32 s12, s12, s1 ; SI-NEXT: s_add_u32 s12, s12, s1
; SI-NEXT: s_addc_u32 s13, s13, 0 ; SI-NEXT: s_addc_u32 s13, s13, 0
; SI-NEXT: s_mov_b32 s32, 0 ; SI-NEXT: s_mov_b32 s32, 0
; SI-NEXT: ; implicit-def: $vgpr0 ; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: s_and_saveexec_b32 s0, vcc_lo ; SI-NEXT: s_and_saveexec_b32 s0, vcc_lo
; SI-NEXT: s_xor_b32 s4, exec_lo, s0 ; SI-NEXT: s_xor_b32 s4, exec_lo, s0
; SI-NEXT: s_cbranch_execz BB4_4 ; SI-NEXT: s_cbranch_execz .LBB4_4
; SI-NEXT: ; %bb.1: ; %else ; SI-NEXT: ; %bb.1: ; %else
; SI-NEXT: s_mov_b32 s5, exec_lo ; SI-NEXT: s_mov_b32 s5, exec_lo
; SI-NEXT: BB4_2: ; =>This Inner Loop Header: Depth=1 ; SI-NEXT: .LBB4_2: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_readfirstlane_b32 s6, v4 ; SI-NEXT: v_readfirstlane_b32 s6, v4
; SI-NEXT: v_readfirstlane_b32 s7, v5 ; SI-NEXT: v_readfirstlane_b32 s7, v5
; SI-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[6:7], v[4:5] ; SI-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[6:7], v[4:5]
; SI-NEXT: s_and_saveexec_b32 s8, vcc_lo ; SI-NEXT: s_and_saveexec_b32 s8, vcc_lo
; SI-NEXT: v_mov_b32_e32 v0, v40 ; SI-NEXT: v_mov_b32_e32 v0, v40
; SI-NEXT: s_mov_b64 s[0:1], s[12:13] ; SI-NEXT: s_mov_b64 s[0:1], s[12:13]
; SI-NEXT: s_mov_b64 s[2:3], s[14:15] ; SI-NEXT: s_mov_b64 s[2:3], s[14:15]
; SI-NEXT: s_swappc_b64 s[30:31], s[6:7] ; SI-NEXT: s_swappc_b64 s[30:31], s[6:7]
; SI-NEXT: ; implicit-def: $vgpr4_vgpr5 ; SI-NEXT: ; implicit-def: $vgpr4_vgpr5
; SI-NEXT: s_xor_b32 exec_lo, exec_lo, s8 ; SI-NEXT: s_xor_b32 exec_lo, exec_lo, s8
; SI-NEXT: s_cbranch_execnz BB4_2 ; SI-NEXT: s_cbranch_execnz .LBB4_2
; SI-NEXT: ; %bb.3: ; SI-NEXT: ; %bb.3:
; SI-NEXT: s_mov_b32 exec_lo, s5 ; SI-NEXT: s_mov_b32 exec_lo, s5
; SI-NEXT: ; implicit-def: $vgpr2 ; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: BB4_4: ; %Flow ; SI-NEXT: .LBB4_4: ; %Flow
; SI-NEXT: s_or_saveexec_b32 s4, s4 ; SI-NEXT: s_or_saveexec_b32 s4, s4
; SI-NEXT: s_xor_b32 exec_lo, exec_lo, s4 ; SI-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; SI-NEXT: s_cbranch_execz BB4_8 ; SI-NEXT: s_cbranch_execz .LBB4_8
; SI-NEXT: ; %bb.5: ; %if ; SI-NEXT: ; %bb.5: ; %if
; SI-NEXT: s_mov_b32 s5, exec_lo ; SI-NEXT: s_mov_b32 s5, exec_lo
; SI-NEXT: BB4_6: ; =>This Inner Loop Header: Depth=1 ; SI-NEXT: .LBB4_6: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_readfirstlane_b32 s6, v2 ; SI-NEXT: v_readfirstlane_b32 s6, v2
; SI-NEXT: v_readfirstlane_b32 s7, v3 ; SI-NEXT: v_readfirstlane_b32 s7, v3
; SI-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[6:7], v[2:3] ; SI-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[6:7], v[2:3]
; SI-NEXT: s_and_saveexec_b32 s8, vcc_lo ; SI-NEXT: s_and_saveexec_b32 s8, vcc_lo
; SI-NEXT: v_mov_b32_e32 v0, v40 ; SI-NEXT: v_mov_b32_e32 v0, v40
; SI-NEXT: s_mov_b64 s[0:1], s[12:13] ; SI-NEXT: s_mov_b64 s[0:1], s[12:13]
; SI-NEXT: s_mov_b64 s[2:3], s[14:15] ; SI-NEXT: s_mov_b64 s[2:3], s[14:15]
; SI-NEXT: s_swappc_b64 s[30:31], s[6:7] ; SI-NEXT: s_swappc_b64 s[30:31], s[6:7]
; SI-NEXT: ; implicit-def: $vgpr2_vgpr3 ; SI-NEXT: ; implicit-def: $vgpr2_vgpr3
; SI-NEXT: s_xor_b32 exec_lo, exec_lo, s8 ; SI-NEXT: s_xor_b32 exec_lo, exec_lo, s8
; SI-NEXT: s_cbranch_execnz BB4_6 ; SI-NEXT: s_cbranch_execnz .LBB4_6
; SI-NEXT: ; %bb.7: ; SI-NEXT: ; %bb.7:
; SI-NEXT: s_mov_b32 exec_lo, s5 ; SI-NEXT: s_mov_b32 exec_lo, s5
; SI-NEXT: BB4_8: ; %end ; SI-NEXT: .LBB4_8: ; %end
; SI-NEXT: s_or_b32 exec_lo, exec_lo, s4 ; SI-NEXT: s_or_b32 exec_lo, exec_lo, s4
; SI-NEXT: v_add_f32_e32 v0, v0, v40 ; SI-NEXT: v_add_f32_e32 v0, v0, v40
; SI-NEXT: ; return to shader part epilog ; SI-NEXT: ; return to shader part epilog
main_body: main_body:
%cc = icmp sgt i32 %z, 5 %cc = icmp sgt i32 %z, 5
br i1 %cc, label %if, label %else br i1 %cc, label %if, label %else
if: if:
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llvm/test/CodeGen/AMDGPU/wave32.ll

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} }
; GCN-LABEL: {{^}}test_loop_with_if: ; GCN-LABEL: {{^}}test_loop_with_if:
; GFX1032: s_or_b32 s{{[0-9]+}}, vcc_lo, s{{[0-9]+}} ; GFX1032: s_or_b32 s{{[0-9]+}}, vcc_lo, s{{[0-9]+}}
; GFX1032: s_andn2_b32 exec_lo, exec_lo, s{{[0-9]+}} ; GFX1032: s_andn2_b32 exec_lo, exec_lo, s{{[0-9]+}}
; GFX1064: s_or_b64 s[{{[0-9:]+}}], vcc, s[{{[0-9:]+}}] ; GFX1064: s_or_b64 s[{{[0-9:]+}}], vcc, s[{{[0-9:]+}}]
; GFX1064: s_andn2_b64 exec, exec, s[{{[0-9:]+}}] ; GFX1064: s_andn2_b64 exec, exec, s[{{[0-9:]+}}]
; GCN: s_cbranch_execz ; GCN: s_cbranch_execz
; GCN: BB{{.*}}: ; GCN: .LBB{{.*}}:
; GFX1032: s_and_saveexec_b32 s{{[0-9]+}}, vcc_lo ; GFX1032: s_and_saveexec_b32 s{{[0-9]+}}, vcc_lo
; GFX1064: s_and_saveexec_b64 s[{{[0-9:]+}}], vcc{{$}} ; GFX1064: s_and_saveexec_b64 s[{{[0-9:]+}}], vcc{{$}}
; GCN: s_cbranch_execz ; GCN: s_cbranch_execz
; GCN: ; %bb.{{[0-9]+}}: ; GCN: ; %bb.{{[0-9]+}}:
; GCN: BB{{.*}}: ; GCN: .LBB{{.*}}:
; GFX1032: s_xor_b32 s{{[0-9]+}}, exec_lo, s{{[0-9]+}} ; GFX1032: s_xor_b32 s{{[0-9]+}}, exec_lo, s{{[0-9]+}}
; GFX1064: s_xor_b64 s[{{[0-9:]+}}], exec, s[{{[0-9:]+}}] ; GFX1064: s_xor_b64 s[{{[0-9:]+}}], exec, s[{{[0-9:]+}}]
; GCN: ; %bb.{{[0-9]+}}: ; GCN: ; %bb.{{[0-9]+}}:
; GCN: ; %bb.{{[0-9]+}}: ; GCN: ; %bb.{{[0-9]+}}:
; GFX1032: s_or_b32 exec_lo, exec_lo, s{{[0-9]+}} ; GFX1032: s_or_b32 exec_lo, exec_lo, s{{[0-9]+}}
; GFX1032: s_and_saveexec_b32 s{{[0-9]+}}, s{{[0-9]+}} ; GFX1032: s_and_saveexec_b32 s{{[0-9]+}}, s{{[0-9]+}}
; GFX1064: s_or_b64 exec, exec, s[{{[0-9:]+}}] ; GFX1064: s_or_b64 exec, exec, s[{{[0-9:]+}}]
; GFX1064: s_and_saveexec_b64 s[{{[0-9:]+}}], s[{{[0-9:]+}}]{{$}} ; GFX1064: s_and_saveexec_b64 s[{{[0-9:]+}}], s[{{[0-9:]+}}]{{$}}
; GCN: s_cbranch_execz BB ; GCN: s_cbranch_execz .LBB
; GCN: ; %bb.{{[0-9]+}}: ; GCN: ; %bb.{{[0-9]+}}:
; GCN: BB{{.*}}: ; GCN: .LBB{{.*}}:
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @test_loop_with_if(i32 addrspace(1)* %arg) #0 { define amdgpu_kernel void @test_loop_with_if(i32 addrspace(1)* %arg) #0 {
bb: bb:
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x() %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
br label %bb2 br label %bb2
bb1: bb1:
ret void ret void
Show All 25 Linesbb13:
br i1 %tmp16, label %bb2, label %bb1 br i1 %tmp16, label %bb2, label %bb1
} }
; GCN-LABEL: {{^}}test_loop_with_if_else_break: ; GCN-LABEL: {{^}}test_loop_with_if_else_break:
; GFX1032: s_and_saveexec_b32 s{{[0-9]+}}, vcc_lo ; GFX1032: s_and_saveexec_b32 s{{[0-9]+}}, vcc_lo
; GFX1064: s_and_saveexec_b64 s[{{[0-9:]+}}], vcc{{$}} ; GFX1064: s_and_saveexec_b64 s[{{[0-9:]+}}], vcc{{$}}
; GCN: s_cbranch_execz ; GCN: s_cbranch_execz
; GCN: ; %bb.{{[0-9]+}}: ; %.preheader ; GCN: ; %bb.{{[0-9]+}}: ; %.preheader
; GCN: BB{{.*}}: ; GCN: .LBB{{.*}}:
; GCN: global_store_dword ; GCN: global_store_dword
; GFX1032: s_or_b32 [[MASK0:s[0-9]+]], [[MASK0]], vcc_lo ; GFX1032: s_or_b32 [[MASK0:s[0-9]+]], [[MASK0]], vcc_lo
; GFX1064: s_or_b64 [[MASK0:s\[[0-9:]+\]]], [[MASK0]], vcc ; GFX1064: s_or_b64 [[MASK0:s\[[0-9:]+\]]], [[MASK0]], vcc
; GFX1032: s_andn2_b32 [[MASK1:s[0-9]+]], [[MASK1]], exec_lo ; GFX1032: s_andn2_b32 [[MASK1:s[0-9]+]], [[MASK1]], exec_lo
; GFX1064: s_andn2_b64 [[MASK1:s\[[0-9:]+\]]], [[MASK1]], exec ; GFX1064: s_andn2_b64 [[MASK1:s\[[0-9:]+\]]], [[MASK1]], exec
; GFX1032: s_and_b32 [[MASK0]], [[MASK0]], exec_lo ; GFX1032: s_and_b32 [[MASK0]], [[MASK0]], exec_lo
; GFX1064: s_and_b64 [[MASK0]], [[MASK0]], exec ; GFX1064: s_and_b64 [[MASK0]], [[MASK0]], exec
; GFX1032: s_or_b32 [[MASK1]], [[MASK1]], [[MASK0]] ; GFX1032: s_or_b32 [[MASK1]], [[MASK1]], [[MASK0]]
; GFX1064: s_or_b64 [[MASK1]], [[MASK1]], [[MASK0]] ; GFX1064: s_or_b64 [[MASK1]], [[MASK1]], [[MASK0]]
; GCN: BB{{.*}}: ; %Flow ; GCN: .LBB{{.*}}: ; %Flow
; GFX1032: s_and_b32 [[TMP0:s[0-9]+]], exec_lo, [[MASK1]] ; GFX1032: s_and_b32 [[TMP0:s[0-9]+]], exec_lo, [[MASK1]]
; GFX1064: s_and_b64 [[TMP0:s\[[0-9:]+\]]], exec, [[MASK1]] ; GFX1064: s_and_b64 [[TMP0:s\[[0-9:]+\]]], exec, [[MASK1]]
; GFX1032: s_or_b32 [[ACC:s[0-9]+]], [[TMP0]], [[ACC]] ; GFX1032: s_or_b32 [[ACC:s[0-9]+]], [[TMP0]], [[ACC]]
; GFX1064: s_or_b64 [[ACC:s\[[0-9:]+\]]], [[TMP0]], [[ACC]] ; GFX1064: s_or_b64 [[ACC:s\[[0-9:]+\]]], [[TMP0]], [[ACC]]
; GFX1032: s_andn2_b32 exec_lo, exec_lo, [[ACC]] ; GFX1032: s_andn2_b32 exec_lo, exec_lo, [[ACC]]
; GFX1064: s_andn2_b64 exec, exec, [[ACC]] ; GFX1064: s_andn2_b64 exec, exec, [[ACC]]
; GCN: s_cbranch_execz ; GCN: s_cbranch_execz
; GCN: BB{{.*}}: ; GCN: .LBB{{.*}}:
; GFX1032-DAG: s_or_b32 [[MASK1]], [[MASK1]], exec_lo ; GFX1032-DAG: s_or_b32 [[MASK1]], [[MASK1]], exec_lo
; GFX1064-DAG: s_or_b64 [[MASK1]], [[MASK1]], exec ; GFX1064-DAG: s_or_b64 [[MASK1]], [[MASK1]], exec
; GCN-DAG: global_load_dword [[LOAD:v[0-9]+]] ; GCN-DAG: global_load_dword [[LOAD:v[0-9]+]]
; GFX1032: v_cmp_gt_i32_e32 vcc_lo, 11, [[LOAD]] ; GFX1032: v_cmp_gt_i32_e32 vcc_lo, 11, [[LOAD]]
; GFX1064: v_cmp_gt_i32_e32 vcc, 11, [[LOAD]] ; GFX1064: v_cmp_gt_i32_e32 vcc, 11, [[LOAD]]
define amdgpu_kernel void @test_loop_with_if_else_break(i32 addrspace(1)* %arg) #0 { define amdgpu_kernel void @test_loop_with_if_else_break(i32 addrspace(1)* %arg) #0 {
bb: bb:
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; GFX1032: s_mov_b32 [[VCC:vcc_lo]], 0{{$}} ; GFX1032: s_mov_b32 [[VCC:vcc_lo]], 0{{$}}
; GFX1064: s_mov_b64 [[VCC:vcc]], 0{{$}} ; GFX1064: s_mov_b64 [[VCC:vcc]], 0{{$}}
; GFX1032: s_and_saveexec_b32 [[SAVE:s[0-9]+]], s{{[0-9]+}}{{$}} ; GFX1032: s_and_saveexec_b32 [[SAVE:s[0-9]+]], s{{[0-9]+}}{{$}}
; GFX1064: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], s[{{[0-9:]+}}]{{$}} ; GFX1064: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], s[{{[0-9:]+}}]{{$}}
; GCN: load_dword [[LOAD:v[0-9]+]] ; GCN: load_dword [[LOAD:v[0-9]+]]
; GCN: v_cmp_ne_u32_e32 [[VCC]], 0, [[LOAD]] ; GCN: v_cmp_ne_u32_e32 [[VCC]], 0, [[LOAD]]
; GCN: BB{{[0-9_]+}}: ; GCN: .LBB{{[0-9_]+}}:
; GFX1032: s_or_b32 exec_lo, exec_lo, [[SAVE]] ; GFX1032: s_or_b32 exec_lo, exec_lo, [[SAVE]]
; GFX1064: s_or_b64 exec, exec, [[SAVE]] ; GFX1064: s_or_b64 exec, exec, [[SAVE]]
; GCN: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} ; GCN: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
define amdgpu_kernel void @test_div_fmas_f32_i1_phi_vcc(float addrspace(1)* %out, float addrspace(1)* %in, i32 addrspace(1)* %dummy) #0 { define amdgpu_kernel void @test_div_fmas_f32_i1_phi_vcc(float addrspace(1)* %out, float addrspace(1)* %in, i32 addrspace(1)* %dummy) #0 {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
%gep.out = getelementptr float, float addrspace(1)* %out, i32 2 %gep.out = getelementptr float, float addrspace(1)* %out, i32 2
%gep.a = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.a = getelementptr float, float addrspace(1)* %in, i32 %tid
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llvm/test/CodeGen/AMDGPU/wqm.ll

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;CHECK: %IF ;CHECK: %IF
;CHECK: image_sample ;CHECK: image_sample
;CHECK: image_sample ;CHECK: image_sample
;CHECK: %Flow ;CHECK: %Flow
;CHECK-NEXT: s_or_saveexec_b64 [[SAVED:s\[[0-9]+:[0-9]+\]]], ;CHECK-NEXT: s_or_saveexec_b64 [[SAVED:s\[[0-9]+:[0-9]+\]]],
;CHECK-NEXT: s_and_b64 exec, exec, [[ORIG]] ;CHECK-NEXT: s_and_b64 exec, exec, [[ORIG]]
;CHECK-NEXT: s_and_b64 [[SAVED]], exec, [[SAVED]] ;CHECK-NEXT: s_and_b64 [[SAVED]], exec, [[SAVED]]
;CHECK-NEXT: s_xor_b64 exec, exec, [[SAVED]] ;CHECK-NEXT: s_xor_b64 exec, exec, [[SAVED]]
;CHECK-NEXT: s_cbranch_execz [[END_BB:BB[0-9]+_[0-9]+]] ;CHECK-NEXT: s_cbranch_execz [[END_BB:.LBB[0-9]+_[0-9]+]]
;CHECK-NEXT: ; %bb.{{[0-9]+}}: ; %ELSE ;CHECK-NEXT: ; %bb.{{[0-9]+}}: ; %ELSE
;CHECK: store_dword ;CHECK: store_dword
;CHECK: [[END_BB]]: ; %END ;CHECK: [[END_BB]]: ; %END
;CHECK: s_or_b64 exec, exec, ;CHECK: s_or_b64 exec, exec,
;CHECK: v_mov_b32_e32 v0 ;CHECK: v_mov_b32_e32 v0
;CHECK: ; return ;CHECK: ; return
define amdgpu_ps float @test_control_flow_1(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, i32 %c, i32 %z, float %data) { define amdgpu_ps float @test_control_flow_1(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, i32 %c, i32 %z, float %data) {
main_body: main_body:
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; CHECK: v_mov ; CHECK: v_mov
; CHECK: v_mov ; CHECK: v_mov
; CHECK: s_and_b64 exec, exec, [[LIVE]] ; CHECK: s_and_b64 exec, exec, [[LIVE]]
; CHECK: image_store ; CHECK: image_store
; CHECK: s_wqm_b64 exec, exec ; CHECK: s_wqm_b64 exec, exec
; CHECK-DAG: v_mov_b32_e32 [[CTR:v[0-9]+]], 0 ; CHECK-DAG: v_mov_b32_e32 [[CTR:v[0-9]+]], 0
; CHECK-DAG: s_mov_b32 [[SEVEN:s[0-9]+]], 0x40e00000 ; CHECK-DAG: s_mov_b32 [[SEVEN:s[0-9]+]], 0x40e00000
; CHECK: [[LOOPHDR:BB[0-9]+_[0-9]+]]: ; %body ; CHECK: [[LOOPHDR:.LBB[0-9]+_[0-9]+]]: ; %body
; CHECK: v_add_f32_e32 [[CTR]], 2.0, [[CTR]] ; CHECK: v_add_f32_e32 [[CTR]], 2.0, [[CTR]]
; CHECK: [[LOOP:BB[0-9]+_[0-9]+]]: ; %loop ; CHECK: [[LOOP:.LBB[0-9]+_[0-9]+]]: ; %loop
; CHECK: v_cmp_lt_f32_e32 vcc, [[SEVEN]], [[CTR]] ; CHECK: v_cmp_lt_f32_e32 vcc, [[SEVEN]], [[CTR]]
; CHECK: s_cbranch_vccz [[LOOPHDR]] ; CHECK: s_cbranch_vccz [[LOOPHDR]]
; CHECK: ; %break ; CHECK: ; %break
; CHECK: ; return ; CHECK: ; return
define amdgpu_ps <4 x float> @test_loop_vcc(<4 x float> %in) nounwind { define amdgpu_ps <4 x float> @test_loop_vcc(<4 x float> %in) nounwind {
entry: entry:
call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %in, i32 15, i32 undef, <8 x i32> undef, i32 0, i32 0) call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %in, i32 15, i32 undef, <8 x i32> undef, i32 0, i32 0)
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llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll

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; GFX9-O0-NEXT: v_cmp_eq_u32_e64 s[34:35], v0, s30 ; GFX9-O0-NEXT: v_cmp_eq_u32_e64 s[34:35], v0, s30
; GFX9-O0-NEXT: v_mov_b32_e32 v0, s30 ; GFX9-O0-NEXT: v_mov_b32_e32 v0, s30
; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-O0-NEXT: s_mov_b64 s[30:31], exec ; GFX9-O0-NEXT: s_mov_b64 s[30:31], exec
; GFX9-O0-NEXT: v_writelane_b32 v5, s30, 6 ; GFX9-O0-NEXT: v_writelane_b32 v5, s30, 6
; GFX9-O0-NEXT: v_writelane_b32 v5, s31, 7 ; GFX9-O0-NEXT: v_writelane_b32 v5, s31, 7
; GFX9-O0-NEXT: s_and_b64 s[30:31], s[30:31], s[34:35] ; GFX9-O0-NEXT: s_and_b64 s[30:31], s[30:31], s[34:35]
; GFX9-O0-NEXT: s_mov_b64 exec, s[30:31] ; GFX9-O0-NEXT: s_mov_b64 exec, s[30:31]
; GFX9-O0-NEXT: s_cbranch_execz BB1_2 ; GFX9-O0-NEXT: s_cbranch_execz .LBB1_2
; GFX9-O0-NEXT: ; %bb.1: ; %if ; GFX9-O0-NEXT: ; %bb.1: ; %if
; GFX9-O0-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; GFX9-O0-NEXT: s_nop 0 ; GFX9-O0-NEXT: s_nop 0
; GFX9-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
; GFX9-O0-NEXT: s_waitcnt vmcnt(0) ; GFX9-O0-NEXT: s_waitcnt vmcnt(0)
; GFX9-O0-NEXT: v_mov_b32_e32 v0, v4 ; GFX9-O0-NEXT: v_mov_b32_e32 v0, v4
; GFX9-O0-NEXT: s_or_saveexec_b64 s[30:31], -1 ; GFX9-O0-NEXT: s_or_saveexec_b64 s[30:31], -1
; GFX9-O0-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-O0-NEXT: v_mov_b32_e32 v1, 0
; GFX9-O0-NEXT: s_mov_b64 exec, s[30:31] ; GFX9-O0-NEXT: s_mov_b64 exec, s[30:31]
; GFX9-O0-NEXT: v_mov_b32_e32 v2, v0 ; GFX9-O0-NEXT: v_mov_b32_e32 v2, v0
; GFX9-O0-NEXT: s_not_b64 exec, exec ; GFX9-O0-NEXT: s_not_b64 exec, exec
; GFX9-O0-NEXT: v_mov_b32_e32 v2, v1 ; GFX9-O0-NEXT: v_mov_b32_e32 v2, v1
; GFX9-O0-NEXT: s_not_b64 exec, exec ; GFX9-O0-NEXT: s_not_b64 exec, exec
; GFX9-O0-NEXT: s_or_saveexec_b64 s[30:31], -1 ; GFX9-O0-NEXT: s_or_saveexec_b64 s[30:31], -1
; GFX9-O0-NEXT: v_mov_b32_dpp v1, v2 row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX9-O0-NEXT: v_mov_b32_dpp v1, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9-O0-NEXT: v_add_u32_e64 v1, v2, v1 ; GFX9-O0-NEXT: v_add_u32_e64 v1, v2, v1
; GFX9-O0-NEXT: s_mov_b64 exec, s[30:31] ; GFX9-O0-NEXT: s_mov_b64 exec, s[30:31]
; GFX9-O0-NEXT: v_mov_b32_e32 v0, v1 ; GFX9-O0-NEXT: v_mov_b32_e32 v0, v1
; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-O0-NEXT: BB1_2: ; %merge ; GFX9-O0-NEXT: .LBB1_2: ; %merge
; GFX9-O0-NEXT: v_readlane_b32 s34, v5, 6 ; GFX9-O0-NEXT: v_readlane_b32 s34, v5, 6
; GFX9-O0-NEXT: v_readlane_b32 s35, v5, 7 ; GFX9-O0-NEXT: v_readlane_b32 s35, v5, 7
; GFX9-O0-NEXT: s_or_b64 exec, exec, s[34:35] ; GFX9-O0-NEXT: s_or_b64 exec, exec, s[34:35]
; GFX9-O0-NEXT: v_readlane_b32 s30, v5, 0 ; GFX9-O0-NEXT: v_readlane_b32 s30, v5, 0
; GFX9-O0-NEXT: v_readlane_b32 s31, v5, 1 ; GFX9-O0-NEXT: v_readlane_b32 s31, v5, 1
; GFX9-O0-NEXT: v_readlane_b32 s36, v5, 2 ; GFX9-O0-NEXT: v_readlane_b32 s36, v5, 2
; GFX9-O0-NEXT: v_readlane_b32 s37, v5, 3 ; GFX9-O0-NEXT: v_readlane_b32 s37, v5, 3
; GFX9-O0-NEXT: v_readlane_b32 s38, v5, 4 ; GFX9-O0-NEXT: v_readlane_b32 s38, v5, 4
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llvm/test/Transforms/LoopStrengthReduce/AMDGPU/different-addrspace-crash.ll

; RUN: llc < %s | FileCheck %s ; RUN: llc < %s | FileCheck %s
target triple = "amdgcn--" target triple = "amdgcn--"
; We need to compile this for a target where we have different address spaces, ; We need to compile this for a target where we have different address spaces,
; and where pointers in those address spaces have different size. ; and where pointers in those address spaces have different size.
; E.g. for amdgcn-- pointers in address space 0 are 32 bits and pointers in ; E.g. for amdgcn-- pointers in address space 0 are 32 bits and pointers in
; address space 1 are 64 bits. ; address space 1 are 64 bits.
; We shouldn't crash. Check that we get a loop with the two stores. ; We shouldn't crash. Check that we get a loop with the two stores.
;CHECK-LABEL: foo: ;CHECK-LABEL: foo:
;CHECK: [[LOOP_LABEL:BB[0-9]+_[0-9]+]]: ;CHECK: [[LOOP_LABEL:.LBB[0-9]+_[0-9]+]]:
;CHECK: buffer_store_dword ;CHECK: buffer_store_dword
;CHECK: buffer_store_dword ;CHECK: buffer_store_dword
;CHECK: s_branch [[LOOP_LABEL]] ;CHECK: s_branch [[LOOP_LABEL]]
define amdgpu_kernel void @foo() { define amdgpu_kernel void @foo() {
entry: entry:
br label %loop br label %loop
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