diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -626,16 +626,6 @@
     }
   }
 
-  // TODO: This should probably be a combine somewhere
-  // (build_vector_trunc $src0, undef -> copy $src0
-  MachineInstr *Src1Def = getDefIgnoringCopies(Src1, *MRI);
-  if (Src1Def && Src1Def->getOpcode() == AMDGPU::G_IMPLICIT_DEF) {
-    MI.setDesc(TII.get(AMDGPU::COPY));
-    MI.RemoveOperand(2);
-    return RBI.constrainGenericRegister(Dst, AMDGPU::SReg_32RegClass, *MRI) &&
-           RBI.constrainGenericRegister(Src0, AMDGPU::SReg_32RegClass, *MRI);
-  }
-
   Register ShiftSrc0;
   Register ShiftSrc1;
 
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir
@@ -144,26 +144,6 @@
     S_ENDPGM 0, implicit %2
 ...
 
----
-name: test_build_vector_trunc_s_v2s16_s_s32_s_undef_s32
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-
-body: |
-  bb.0:
-    liveins: $sgpr0
-
-    ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_s_undef_s32
-    ; GFX9: liveins: $sgpr0
-    ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; GFX9: S_ENDPGM 0, implicit [[COPY]]
-    %0:sgpr(s32) = COPY $sgpr0
-    %1:sgpr(s32) = G_IMPLICIT_DEF
-    %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
-    S_ENDPGM 0, implicit %2
-...
-
 ---
 name: test_build_vector_trunc_s_v2s16_s_undef_s32_s_s32
 legalized:       true
@@ -208,26 +188,6 @@
     S_ENDPGM 0, implicit %2
 ...
 
----
-name: test_build_vector_trunc_s_v2s16_s_s32_undef
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-
-body: |
-  bb.0:
-    liveins: $sgpr0
-
-    ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_undef
-    ; GFX9: liveins: $sgpr0
-    ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; GFX9: S_ENDPGM 0, implicit [[COPY]]
-    %0:sgpr(s32) = COPY $sgpr0
-    %1:sgpr(s32) = G_IMPLICIT_DEF
-    %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
-    S_ENDPGM 0, implicit %2
-...
-
 ---
 name: test_build_vector_trunc_s_v2s16_s_zero_s_s32
 legalized:       true
@@ -449,24 +409,6 @@
     S_ENDPGM 0, implicit %2
 ...
 
----
-name: test_build_vector_trunc_s_v2s16_constant_impdef
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-
-body: |
-  bb.0:
-
-    ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_constant_impdef
-    ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123
-    ; GFX9: S_ENDPGM 0, implicit [[S_MOV_B32_]]
-    %0:sgpr(s32) = G_CONSTANT i32 123
-    %1:sgpr(s32) = G_IMPLICIT_DEF
-    %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
-    S_ENDPGM 0, implicit %2
-...
-
 ---
 name: test_build_vector_trunc_s_v2s16_impdef_constant
 legalized:       true
@@ -487,24 +429,6 @@
     S_ENDPGM 0, implicit %2
 ...
 
----
-name: test_build_vector_trunc_s_v2s16_impdef_impdef
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-
-body: |
-  bb.0:
-
-    ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_impdef_impdef
-    ; GFX9: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
-    ; GFX9: S_ENDPGM 0, implicit [[DEF]]
-    %0:sgpr(s32) = G_IMPLICIT_DEF
-    %1:sgpr(s32) = G_IMPLICIT_DEF
-    %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
-    S_ENDPGM 0, implicit %2
-...
-
 ---
 name: test_build_vector_trunc_s_v2s16_zext_constant_zext_constant
 legalized:       true