[SelectionDAG] Add pattern to haveNoCommonBitsSet.

[OmerAviram]

Summary

Correctly identify the following pattern, which has no common bits: (X & ~M) op (Y & M).

[lebedev.ri]

Tests?

[OmerAviram]

Added ll test for X86 Target.
prior to the patch, the ir included an or instruction:

; CHECK-NEXT:    andl %esi, %edx
; CHECK-NEXT:    notl %esi
; CHECK-NEXT:    andl %edi, %esi
; CHECK-NEXT:    orl %edx, %esi
; CHECK-NEXT:    leal 1(%rsi), %eax

After the patch, the or instruction can be combined into an add, since the operands have no common bits.

[RKSimon]

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

4552

Maybe better to pull this into haveNoCommonBitsSet as lambda?

4554

You need to try and ensure we have test coverage for all of these permutations.

llvm/test/CodeGen/X86/or-lea.ll

155

Once you have more test coverage, we should add these tests to trunk with current codegen so you can rebase and the patch shows the diff.

[OmerAviram]

Added tests for the different pattern permutations as a separate patch (https://reviews.llvm.org/D114078) and rebased on it.

[OmerAviram]

Updated diff with i32 and i64 tests.

[RKSimon]

Please can you rebase - I've added BMI test coverage as well which might affect some tests

[spatel]

Do we expect all vector types/targets to bypass this in some way? If yes, it's worth adding a comment to the patch description and/or code. If no, can we find a test that shows an asm difference?

[OmerAviram]

In D113970#3151343, @spatel wrote:

Do we expect all vector types/targets to bypass this in some way? If yes, it's worth adding a comment to the patch description and/or code. If no, can we find a test that shows an asm difference?

What exactly do you mean by bypass it? This addition to haveNoCommonBitsSet works for vector types as well. Do you mean add another lit test for vector types?

[spatel]

In D113970#3151642, @OmerAviram wrote:

In D113970#3151343, @spatel wrote:

Do we expect all vector types/targets to bypass this in some way? If yes, it's worth adding a comment to the patch description and/or code. If no, can we find a test that shows an asm difference?

What exactly do you mean by bypass it? This addition to haveNoCommonBitsSet works for vector types as well. Do you mean add another lit test for vector types?

I mean are there TLI hooks (for example hasAndNot) or other transforms that will trigger before or after this such that vector instructions are never affected?
It sounds like the answer is 'no'. Therefore, yes we should have another lit test with vector types, so we can see the difference from this patch.

[OmerAviram]

Added tests for vector types.

[spatel]

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

4550

I prefer that we not reuse/shadow the variable names in here.
How about matching the variable names to the code comment, so something like this:

auto MatchNoCommonBitsPattern = [&](SDValue NotM, SDValue And) {
  if (isBitwiseNot(NotM, true)) {
    SDValue M = NotM->getOperand(0);

[RKSimon]

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

4554

(style) Remove the unnecessary brackets

[spatel]

LGTM - will wait at least a day to commit in case there's any other feedback.

[OmerAviram]

In D113970#3158588, @spatel wrote:

LGTM - will wait at least a day to commit in case there's any other feedback.

Thanks, Could you please commit on my behalf?

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

if (const ConstantFPSDNode *CA = dyn_cast<ConstantFPSDNode>(A))
     if (const ConstantFPSDNode *CB = dyn_cast<ConstantFPSDNode>(B))
       if (CA->isZero() && CB->isZero()) return true;
 
   // Otherwise they may not be equal.
   return false;
 }
 
 // FIXME: unify with llvm::haveNoCommonBitsSet.
-// FIXME: could also handle masked merge pattern (X & ~M) op (Y & M)
 bool SelectionDAG::haveNoCommonBitsSet(SDValue A, SDValue B) const {
   assert(A.getValueType() == B.getValueType() &&
          "Values must have the same type");
+  // Match masked merge pattern (X & ~M) op (Y & M)
+  if (A->getOpcode() == ISD::AND && B->getOpcode() == ISD::AND) {
+    auto MatchNoCommonBitsPattern = [&](SDValue NotM, SDValue And) {
+      if (isBitwiseNot(NotM, true)) {
+        SDValue NotOperand = NotM->getOperand(0);
+        return NotOperand == And->getOperand(0) ||
+               NotOperand == And->getOperand(1);
+      }
+      return false;
+    };
+    if (MatchNoCommonBitsPattern(A->getOperand(0), B) ||
+        MatchNoCommonBitsPattern(A->getOperand(1), B) ||
+        MatchNoCommonBitsPattern(B->getOperand(0), A) ||
+        MatchNoCommonBitsPattern(B->getOperand(1), A))
+      return true;
+  }
   return KnownBits::haveNoCommonBitsSet(computeKnownBits(A),
                                         computeKnownBits(B));
 }
 
 static SDValue FoldSTEP_VECTOR(const SDLoc &DL, EVT VT, SDValue Step,
                                SelectionDAG &DAG) {
   if (cast<ConstantSDNode>(Step)->isZero())
     return DAG.getConstant(0, DL, VT);

llvm/test/CodeGen/X86/or-lea.ll

 ; NOBMI-NEXT:    xorl %edi, %edx
 ; NOBMI-NEXT:    andl %esi, %edx
 ; NOBMI-NEXT:    xorl %edi, %edx
 ; NOBMI-NEXT:    leal 1(%rdx), %eax
 ; NOBMI-NEXT:    retq
 ;
 ; BMI-LABEL: or_and_and_rhs_neg_i32:
 ; BMI:       # %bb.0: # %entry
+; BMI-NEXT:    # kill: def $edx killed $edx def $rdx
 ; BMI-NEXT:    andl %esi, %edx
 ; BMI-NEXT:    andnl %edi, %esi, %eax
-; BMI-NEXT:    orl %edx, %eax
-; BMI-NEXT:    incl %eax
+; BMI-NEXT:    leal 1(%rdx,%rax), %eax
 ; BMI-NEXT:    retq
 entry:
   %and1 = and i32 %z, %y
   %xor = xor i32 %y, -1
   %and2 = and i32 %x, %xor
   %or = or i32 %and1, %and2
   %inc = add i32 %or, 1
   ret i32 %inc
 }
 
 define i32 @or_and_and_lhs_neg_i32(i32 %x, i32 %y, i32 %z) {
 ; NOBMI-LABEL: or_and_and_lhs_neg_i32:
 ; NOBMI:       # %bb.0: # %entry
 ; NOBMI-NEXT:    # kill: def $edx killed $edx def $rdx
 ; NOBMI-NEXT:    xorl %edi, %edx
 ; NOBMI-NEXT:    andl %esi, %edx
 ; NOBMI-NEXT:    xorl %edi, %edx
 ; NOBMI-NEXT:    leal 1(%rdx), %eax
 ; NOBMI-NEXT:    retq
 ;
 ; BMI-LABEL: or_and_and_lhs_neg_i32:
 ; BMI:       # %bb.0: # %entry
+; BMI-NEXT:    # kill: def $edx killed $edx def $rdx
 ; BMI-NEXT:    andl %esi, %edx
 ; BMI-NEXT:    andnl %edi, %esi, %eax
-; BMI-NEXT:    orl %edx, %eax
-; BMI-NEXT:    incl %eax
+; BMI-NEXT:    leal 1(%rdx,%rax), %eax
 ; BMI-NEXT:    retq
 entry:
   %and1 = and i32 %z, %y
   %xor = xor i32 %y, -1
   %and2 = and i32 %xor, %x
   %or = or i32 %and1, %and2
   %inc = add i32 %or, 1
   ret i32 %inc
 }
 
 define i32 @or_and_rhs_neg_and_i32(i32 %x, i32 %y, i32 %z) {
 ; NOBMI-LABEL: or_and_rhs_neg_and_i32:
 ; NOBMI:       # %bb.0: # %entry
 ; NOBMI-NEXT:    # kill: def $edi killed $edi def $rdi
 ; NOBMI-NEXT:    xorl %edx, %edi
 ; NOBMI-NEXT:    andl %esi, %edi
 ; NOBMI-NEXT:    xorl %edx, %edi
 ; NOBMI-NEXT:    leal 1(%rdi), %eax
 ; NOBMI-NEXT:    retq
 ;
 ; BMI-LABEL: or_and_rhs_neg_and_i32:
 ; BMI:       # %bb.0: # %entry
+; BMI-NEXT:    # kill: def $edi killed $edi def $rdi
 ; BMI-NEXT:    andnl %edx, %esi, %eax
 ; BMI-NEXT:    andl %esi, %edi
-; BMI-NEXT:    orl %edi, %eax
-; BMI-NEXT:    incl %eax
+; BMI-NEXT:    leal 1(%rax,%rdi), %eax
 ; BMI-NEXT:    retq
 entry:
   %xor = xor i32 %y, -1
   %and1 = and i32 %z, %xor
   %and2 = and i32 %x, %y
   %or = or i32 %and1, %and2
   %inc = add i32 %or, 1
   ret i32 %inc
 }
 
 define i32 @or_and_lhs_neg_and_i32(i32 %x, i32 %y, i32 %z) {
 ; NOBMI-LABEL: or_and_lhs_neg_and_i32:
 ; NOBMI:       # %bb.0: # %entry
 ; NOBMI-NEXT:    # kill: def $edi killed $edi def $rdi
 ; NOBMI-NEXT:    xorl %edx, %edi
 ; NOBMI-NEXT:    andl %esi, %edi
 ; NOBMI-NEXT:    xorl %edx, %edi
 ; NOBMI-NEXT:    leal 1(%rdi), %eax
 ; NOBMI-NEXT:    retq
 ;
 ; BMI-LABEL: or_and_lhs_neg_and_i32:
 ; BMI:       # %bb.0: # %entry
+; BMI-NEXT:    # kill: def $edi killed $edi def $rdi
 ; BMI-NEXT:    andnl %edx, %esi, %eax
 ; BMI-NEXT:    andl %esi, %edi
-; BMI-NEXT:    orl %edi, %eax
-; BMI-NEXT:    incl %eax
+; BMI-NEXT:    leal 1(%rax,%rdi), %eax
 ; BMI-NEXT:    retq
 entry:
   %xor = xor i32 %y, -1
   %and1 = and i32 %xor, %z
   %and2 = and i32 %x, %y
   %or = or i32 %and1, %and2
   %inc = add i32 %or, 1
   ret i32 %inc
 }
 
 define i64 @or_and_and_rhs_neg_i64(i64 %x, i64 %y, i64 %z) {
 ; NOBMI-LABEL: or_and_and_rhs_neg_i64:
 ; NOBMI:       # %bb.0: # %entry
 ; NOBMI-NEXT:    xorq %rdi, %rdx
 ; NOBMI-NEXT:    andq %rsi, %rdx
 ; NOBMI-NEXT:    xorq %rdi, %rdx
 ; NOBMI-NEXT:    leaq 1(%rdx), %rax
 ; NOBMI-NEXT:    retq
 ;
 ; BMI-LABEL: or_and_and_rhs_neg_i64:
 ; BMI:       # %bb.0: # %entry
 ; BMI-NEXT:    andq %rsi, %rdx
 ; BMI-NEXT:    andnq %rdi, %rsi, %rax
-; BMI-NEXT:    orq %rdx, %rax
-; BMI-NEXT:    incq %rax
+; BMI-NEXT:    leaq 1(%rdx,%rax), %rax
 ; BMI-NEXT:    retq
 entry:
   %and1 = and i64 %z, %y
   %xor = xor i64 %y, -1
   %and2 = and i64 %x, %xor
   %or = or i64 %and1, %and2
   %inc = add i64 %or, 1
   ret i64 %inc
 }
 
 define i64 @or_and_and_lhs_neg_i64(i64 %x, i64 %y, i64 %z) {
 ; NOBMI-LABEL: or_and_and_lhs_neg_i64:
 ; NOBMI:       # %bb.0: # %entry
 ; NOBMI-NEXT:    xorq %rdi, %rdx
 ; NOBMI-NEXT:    andq %rsi, %rdx
 ; NOBMI-NEXT:    xorq %rdi, %rdx
 ; NOBMI-NEXT:    leaq 1(%rdx), %rax
 ; NOBMI-NEXT:    retq
 ;
 ; BMI-LABEL: or_and_and_lhs_neg_i64:
 ; BMI:       # %bb.0: # %entry
 ; BMI-NEXT:    andq %rsi, %rdx
 ; BMI-NEXT:    andnq %rdi, %rsi, %rax
-; BMI-NEXT:    orq %rdx, %rax
-; BMI-NEXT:    incq %rax
+; BMI-NEXT:    leaq 1(%rdx,%rax), %rax
 ; BMI-NEXT:    retq
 entry:
   %and1 = and i64 %z, %y
   %xor = xor i64 %y, -1
   %and2 = and i64 %xor, %x
   %or = or i64 %and1, %and2
   %inc = add i64 %or, 1
   ret i64 %inc
 }
 
 define i64 @or_and_rhs_neg_and_i64(i64 %x, i64 %y, i64 %z) {
 ; NOBMI-LABEL: or_and_rhs_neg_and_i64:
 ; NOBMI:       # %bb.0: # %entry
 ; NOBMI-NEXT:    xorq %rdx, %rdi
 ; NOBMI-NEXT:    andq %rsi, %rdi
 ; NOBMI-NEXT:    xorq %rdx, %rdi
 ; NOBMI-NEXT:    leaq 1(%rdi), %rax
 ; NOBMI-NEXT:    retq
 ;
 ; BMI-LABEL: or_and_rhs_neg_and_i64:
 ; BMI:       # %bb.0: # %entry
 ; BMI-NEXT:    andnq %rdx, %rsi, %rax
 ; BMI-NEXT:    andq %rsi, %rdi
-; BMI-NEXT:    orq %rdi, %rax
-; BMI-NEXT:    incq %rax
+; BMI-NEXT:    leaq 1(%rax,%rdi), %rax
 ; BMI-NEXT:    retq
 entry:
   %xor = xor i64 %y, -1
   %and1 = and i64 %z, %xor
   %and2 = and i64 %x, %y
   %or = or i64 %and1, %and2
   %inc = add i64 %or, 1
   ret i64 %inc
 }
 
 define i64 @or_and_lhs_neg_and_i64(i64 %x, i64 %y, i64 %z) {
 ; NOBMI-LABEL: or_and_lhs_neg_and_i64:
 ; NOBMI:       # %bb.0: # %entry
 ; NOBMI-NEXT:    xorq %rdx, %rdi
 ; NOBMI-NEXT:    andq %rsi, %rdi
 ; NOBMI-NEXT:    xorq %rdx, %rdi
 ; NOBMI-NEXT:    leaq 1(%rdi), %rax
 ; NOBMI-NEXT:    retq
 ;
 ; BMI-LABEL: or_and_lhs_neg_and_i64:
 ; BMI:       # %bb.0: # %entry
 ; BMI-NEXT:    andnq %rdx, %rsi, %rax
 ; BMI-NEXT:    andq %rsi, %rdi
-; BMI-NEXT:    orq %rdi, %rax
-; BMI-NEXT:    incq %rax
+; BMI-NEXT:    leaq 1(%rax,%rdi), %rax
 ; BMI-NEXT:    retq
 entry:
   %xor = xor i64 %y, -1
   %and1 = and i64 %xor, %z
   %and2 = and i64 %x, %y
   %or = or i64 %and1, %and2
   %inc = add i64 %or, 1
   ret i64 %inc
 }

llvm/test/CodeGen/X86/vec_no-common-bits.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK
 
 ; In the following patterns, lhs and rhs of the or instruction have no common bits.
 ; Therefore, "add" and "or" instructions are equal.
 
 define <2 x i32> @or_and_and_rhs_neg_vec_i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z) {
 ; CHECK-LABEL: or_and_and_rhs_neg_vec_i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    pand %xmm1, %xmm2
-; CHECK-NEXT:    pandn %xmm0, %xmm1
-; CHECK-NEXT:    movdqa %xmm2, %xmm0
-; CHECK-NEXT:    por %xmm1, %xmm0
-; CHECK-NEXT:    paddd %xmm2, %xmm1
-; CHECK-NEXT:    psubd %xmm1, %xmm0
+; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %and1 = and <2 x i32> %z, %y
   %xor = xor <2 x i32> %y, <i32 -1, i32 -1>
   %and2 = and <2 x i32> %x, %xor
   %or = or <2 x i32> %and1, %and2
   %add = add <2 x i32> %and1, %and2
   %sub = sub <2 x i32> %or, %add
   ret <2 x i32> %sub
 }
 
 define <2 x i32> @or_and_and_lhs_neg_vec_i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z) {
 ; CHECK-LABEL: or_and_and_lhs_neg_vec_i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    pand %xmm1, %xmm2
-; CHECK-NEXT:    pandn %xmm0, %xmm1
-; CHECK-NEXT:    movdqa %xmm2, %xmm0
-; CHECK-NEXT:    por %xmm1, %xmm0
-; CHECK-NEXT:    paddd %xmm2, %xmm1
-; CHECK-NEXT:    psubd %xmm1, %xmm0
+; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %and1 = and <2 x i32> %z, %y
   %xor = xor <2 x i32> %y, <i32 -1, i32 -1>
   %and2 = and <2 x i32> %xor, %x
   %or = or <2 x i32> %and1, %and2
   %add = add <2 x i32> %and1, %and2
   %sub = sub <2 x i32> %or, %add
   ret <2 x i32> %sub
 }
 
 define <2 x i32> @or_and_rhs_neg_and_vec_i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z) {
 ; CHECK-LABEL: or_and_rhs_neg_and_vec_i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    pand %xmm1, %xmm0
-; CHECK-NEXT:    pandn %xmm2, %xmm1
-; CHECK-NEXT:    movdqa %xmm1, %xmm2
-; CHECK-NEXT:    por %xmm0, %xmm2
-; CHECK-NEXT:    paddd %xmm0, %xmm1
-; CHECK-NEXT:    psubd %xmm1, %xmm2
-; CHECK-NEXT:    movdqa %xmm2, %xmm0
+; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %xor = xor <2 x i32> %y, <i32 -1, i32 -1>
   %and1 = and <2 x i32> %z, %xor
   %and2 = and <2 x i32> %x, %y
   %or = or <2 x i32> %and1, %and2
   %add = add <2 x i32> %and1, %and2
   %sub = sub <2 x i32> %or, %add
   ret <2 x i32> %sub
 }
 
 define <2 x i32> @or_and_lhs_neg_and_vec_i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z) {
 ; CHECK-LABEL: or_and_lhs_neg_and_vec_i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    pand %xmm1, %xmm0
-; CHECK-NEXT:    pandn %xmm2, %xmm1
-; CHECK-NEXT:    movdqa %xmm1, %xmm2
-; CHECK-NEXT:    por %xmm0, %xmm2
-; CHECK-NEXT:    paddd %xmm0, %xmm1
-; CHECK-NEXT:    psubd %xmm1, %xmm2
-; CHECK-NEXT:    movdqa %xmm2, %xmm0
+; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %xor = xor <2 x i32> %y, <i32 -1, i32 -1>
   %and1 = and <2 x i32> %xor, %z
   %and2 = and <2 x i32> %x, %y
   %or = or <2 x i32> %and1, %and2
   %add = add <2 x i32> %and1, %and2
   %sub = sub <2 x i32> %or, %add
   ret <2 x i32> %sub
 }
 
 define <2 x i64> @or_and_and_rhs_neg_vec_i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %z) {
 ; CHECK-LABEL: or_and_and_rhs_neg_vec_i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    pand %xmm1, %xmm2
-; CHECK-NEXT:    pandn %xmm0, %xmm1
-; CHECK-NEXT:    movdqa %xmm2, %xmm0
-; CHECK-NEXT:    por %xmm1, %xmm0
-; CHECK-NEXT:    paddq %xmm2, %xmm1
-; CHECK-NEXT:    psubq %xmm1, %xmm0
+; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %and1 = and <2 x i64> %z, %y
   %xor = xor <2 x i64> %y, <i64 -1, i64 -1>
   %and2 = and <2 x i64> %x, %xor
   %or = or <2 x i64> %and1, %and2
   %add = add <2 x i64> %and1, %and2
   %sub = sub <2 x i64> %or, %add
   ret <2 x i64> %sub
 }
 
 define <2 x i64> @or_and_and_lhs_neg_vec_i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %z) {
 ; CHECK-LABEL: or_and_and_lhs_neg_vec_i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    pand %xmm1, %xmm2
-; CHECK-NEXT:    pandn %xmm0, %xmm1
-; CHECK-NEXT:    movdqa %xmm2, %xmm0
-; CHECK-NEXT:    por %xmm1, %xmm0
-; CHECK-NEXT:    paddq %xmm2, %xmm1
-; CHECK-NEXT:    psubq %xmm1, %xmm0
+; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %and1 = and <2 x i64> %z, %y
   %xor = xor <2 x i64> %y, <i64 -1, i64 -1>
   %and2 = and <2 x i64> %xor, %x
   %or = or <2 x i64> %and1, %and2
   %add = add <2 x i64> %and1, %and2
   %sub = sub <2 x i64> %or, %add
   ret <2 x i64> %sub
 }
 
 define <2 x i64> @or_and_rhs_neg_and_vec_i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %z) {
 ; CHECK-LABEL: or_and_rhs_neg_and_vec_i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    pand %xmm1, %xmm0
-; CHECK-NEXT:    pandn %xmm2, %xmm1
-; CHECK-NEXT:    movdqa %xmm1, %xmm2
-; CHECK-NEXT:    por %xmm0, %xmm2
-; CHECK-NEXT:    paddq %xmm0, %xmm1
-; CHECK-NEXT:    psubq %xmm1, %xmm2
-; CHECK-NEXT:    movdqa %xmm2, %xmm0
+; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %xor = xor <2 x i64> %y, <i64 -1, i64 -1>
   %and1 = and <2 x i64> %z, %xor
   %and2 = and <2 x i64> %x, %y
   %or = or <2 x i64> %and1, %and2
   %add = add <2 x i64> %and1, %and2
   %sub = sub <2 x i64> %or, %add
   ret <2 x i64> %sub
 }
 
 define <2 x i64> @or_and_lhs_neg_and_vec_i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %z) {
 ; CHECK-LABEL: or_and_lhs_neg_and_vec_i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    pand %xmm1, %xmm0
-; CHECK-NEXT:    pandn %xmm2, %xmm1
-; CHECK-NEXT:    movdqa %xmm1, %xmm2
-; CHECK-NEXT:    por %xmm0, %xmm2
-; CHECK-NEXT:    paddq %xmm0, %xmm1
-; CHECK-NEXT:    psubq %xmm1, %xmm2
-; CHECK-NEXT:    movdqa %xmm2, %xmm0
+; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %xor = xor <2 x i64> %y, <i64 -1, i64 -1>
   %and1 = and <2 x i64> %xor, %z
   %and2 = and <2 x i64> %x, %y
   %or = or <2 x i64> %and1, %and2
   %add = add <2 x i64> %and1, %and2
   %sub = sub <2 x i64> %or, %add
   ret <2 x i64> %sub
 }