diff --git a/llvm/lib/Target/AMDGPU/GCNPreRAOptimizations.cpp b/llvm/lib/Target/AMDGPU/GCNPreRAOptimizations.cpp
--- a/llvm/lib/Target/AMDGPU/GCNPreRAOptimizations.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNPreRAOptimizations.cpp
@@ -100,8 +100,9 @@
       // Some subtargets cannot do an AGPR to AGPR copy directly, and need an
       // intermdiate temporary VGPR register. Try to find the defining
       // accvgpr_write to avoid temporary registers.
+
       if (!IsAGPRDst)
-        break;
+        return false;
 
       Register SrcReg = I.getOperand(1).getReg();
 
diff --git a/llvm/test/CodeGen/AMDGPU/agpr-to-agpr-copy.mir b/llvm/test/CodeGen/AMDGPU/agpr-to-agpr-copy.mir
--- a/llvm/test/CodeGen/AMDGPU/agpr-to-agpr-copy.mir
+++ b/llvm/test/CodeGen/AMDGPU/agpr-to-agpr-copy.mir
@@ -10,20 +10,21 @@
     liveins: $sgpr0_sgpr1
     ; GFX908-LABEL: name: test_mfma_f32_4x4x1f32_propagate_vgpr
     ; GFX908: liveins: $sgpr0_sgpr1
-    ; GFX908: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr0_sgpr1
-    ; GFX908: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 36, 0 :: (dereferenceable invariant load (s64), align 4, addrspace 4)
-    ; GFX908: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-    ; GFX908: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1123418112, implicit $exec
-    ; GFX908: undef %4.sub0:areg_128 = V_ACCVGPR_WRITE_B32_e64 [[V_MOV_B32_e32_1]], implicit $exec
-    ; GFX908: %4.sub1:areg_128 = COPY [[V_MOV_B32_e32_1]]
-    ; GFX908: %4.sub2:areg_128 = COPY [[V_MOV_B32_e32_1]]
-    ; GFX908: %4.sub3:areg_128 = COPY [[V_MOV_B32_e32_1]]
-    ; GFX908: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
-    ; GFX908: [[V_MOV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
-    ; GFX908: [[V_MFMA_F32_4X4X1F32_e64_:%[0-9]+]]:areg_128 = V_MFMA_F32_4X4X1F32_e64 [[V_MOV_B32_e32_3]], [[V_MOV_B32_e32_2]], %4, 0, 0, 0, implicit $mode, implicit $exec
-    ; GFX908: [[COPY1:%[0-9]+]]:vreg_128 = COPY [[V_MFMA_F32_4X4X1F32_e64_]]
-    ; GFX908: GLOBAL_STORE_DWORDX4_SADDR [[V_MOV_B32_e32_]], [[COPY1]], [[S_LOAD_DWORDX2_IMM]], 0, 0, implicit $exec :: (store (s128), addrspace 1)
-    ; GFX908: S_ENDPGM 0
+    ; GFX908-NEXT: {{  $}}
+    ; GFX908-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr0_sgpr1
+    ; GFX908-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 36, 0 :: (dereferenceable invariant load (s64), align 4, addrspace 4)
+    ; GFX908-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; GFX908-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1123418112, implicit $exec
+    ; GFX908-NEXT: undef %4.sub0:areg_128 = V_ACCVGPR_WRITE_B32_e64 [[V_MOV_B32_e32_1]], implicit $exec
+    ; GFX908-NEXT: %4.sub1:areg_128 = COPY [[V_MOV_B32_e32_1]]
+    ; GFX908-NEXT: %4.sub2:areg_128 = COPY [[V_MOV_B32_e32_1]]
+    ; GFX908-NEXT: %4.sub3:areg_128 = COPY [[V_MOV_B32_e32_1]]
+    ; GFX908-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
+    ; GFX908-NEXT: [[V_MOV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
+    ; GFX908-NEXT: [[V_MFMA_F32_4X4X1F32_e64_:%[0-9]+]]:areg_128 = V_MFMA_F32_4X4X1F32_e64 [[V_MOV_B32_e32_3]], [[V_MOV_B32_e32_2]], %4, 0, 0, 0, implicit $mode, implicit $exec
+    ; GFX908-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY [[V_MFMA_F32_4X4X1F32_e64_]]
+    ; GFX908-NEXT: GLOBAL_STORE_DWORDX4_SADDR [[V_MOV_B32_e32_]], [[COPY1]], [[S_LOAD_DWORDX2_IMM]], 0, 0, implicit $exec :: (store (s128), addrspace 1)
+    ; GFX908-NEXT: S_ENDPGM 0
     %1:sgpr_64(p4) = COPY $sgpr0_sgpr1
     %4:sreg_64_xexec = S_LOAD_DWORDX2_IMM %1:sgpr_64(p4), 36, 0 :: (dereferenceable invariant load (s64), align 4, addrspace 4)
     %5:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
@@ -48,19 +49,20 @@
     liveins: $sgpr0_sgpr1
     ; GFX908-LABEL: name: test_mfma_f32_4x4x1f32_no_propagate_imm
     ; GFX908: liveins: $sgpr0_sgpr1
-    ; GFX908: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr0_sgpr1
-    ; GFX908: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 36, 0 :: (dereferenceable invariant load (s64), align 4, addrspace 4)
-    ; GFX908: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-    ; GFX908: undef %3.sub0:areg_128 = V_ACCVGPR_WRITE_B32_e64 1073741824, implicit $exec
-    ; GFX908: %3.sub1:areg_128 = COPY %3.sub0
-    ; GFX908: %3.sub2:areg_128 = COPY %3.sub0
-    ; GFX908: %3.sub3:areg_128 = COPY %3.sub0
-    ; GFX908: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
-    ; GFX908: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
-    ; GFX908: [[V_MFMA_F32_4X4X1F32_e64_:%[0-9]+]]:areg_128 = V_MFMA_F32_4X4X1F32_e64 [[V_MOV_B32_e32_2]], [[V_MOV_B32_e32_1]], %3, 0, 0, 0, implicit $mode, implicit $exec
-    ; GFX908: [[COPY1:%[0-9]+]]:vreg_128 = COPY [[V_MFMA_F32_4X4X1F32_e64_]]
-    ; GFX908: GLOBAL_STORE_DWORDX4_SADDR [[V_MOV_B32_e32_]], [[COPY1]], [[S_LOAD_DWORDX2_IMM]], 0, 0, implicit $exec :: (store (s128), addrspace 1)
-    ; GFX908: S_ENDPGM 0
+    ; GFX908-NEXT: {{  $}}
+    ; GFX908-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr0_sgpr1
+    ; GFX908-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 36, 0 :: (dereferenceable invariant load (s64), align 4, addrspace 4)
+    ; GFX908-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; GFX908-NEXT: undef %3.sub0:areg_128 = V_ACCVGPR_WRITE_B32_e64 1073741824, implicit $exec
+    ; GFX908-NEXT: %3.sub1:areg_128 = COPY %3.sub0
+    ; GFX908-NEXT: %3.sub2:areg_128 = COPY %3.sub0
+    ; GFX908-NEXT: %3.sub3:areg_128 = COPY %3.sub0
+    ; GFX908-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
+    ; GFX908-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
+    ; GFX908-NEXT: [[V_MFMA_F32_4X4X1F32_e64_:%[0-9]+]]:areg_128 = V_MFMA_F32_4X4X1F32_e64 [[V_MOV_B32_e32_2]], [[V_MOV_B32_e32_1]], %3, 0, 0, 0, implicit $mode, implicit $exec
+    ; GFX908-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY [[V_MFMA_F32_4X4X1F32_e64_]]
+    ; GFX908-NEXT: GLOBAL_STORE_DWORDX4_SADDR [[V_MOV_B32_e32_]], [[COPY1]], [[S_LOAD_DWORDX2_IMM]], 0, 0, implicit $exec :: (store (s128), addrspace 1)
+    ; GFX908-NEXT: S_ENDPGM 0
     %1:sgpr_64(p4) = COPY $sgpr0_sgpr1
     %4:sreg_64_xexec = S_LOAD_DWORDX2_IMM %1:sgpr_64(p4), 36, 0 :: (dereferenceable invariant load (s64), align 4, addrspace 4)
     %5:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
@@ -84,12 +86,13 @@
     liveins: $vgpr0_vgpr1_vgpr2_vgpr3
     ; GFX908-LABEL: name: test_vgpr_subreg_propagate
     ; GFX908: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
-    ; GFX908: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3, implicit $exec
-    ; GFX908: undef %1.sub0:areg_128 = V_ACCVGPR_WRITE_B32_e64 [[COPY]].sub0, implicit $exec
-    ; GFX908: %1.sub1:areg_128 = COPY [[COPY]].sub0
-    ; GFX908: %1.sub2:areg_128 = COPY [[COPY]].sub0
-    ; GFX908: %1.sub3:areg_128 = COPY [[COPY]].sub0
-    ; GFX908: S_ENDPGM 0, implicit [[COPY]], implicit %1
+    ; GFX908-NEXT: {{  $}}
+    ; GFX908-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3, implicit $exec
+    ; GFX908-NEXT: undef %1.sub0:areg_128 = V_ACCVGPR_WRITE_B32_e64 [[COPY]].sub0, implicit $exec
+    ; GFX908-NEXT: %1.sub1:areg_128 = COPY [[COPY]].sub0
+    ; GFX908-NEXT: %1.sub2:areg_128 = COPY [[COPY]].sub0
+    ; GFX908-NEXT: %1.sub3:areg_128 = COPY [[COPY]].sub0
+    ; GFX908-NEXT: S_ENDPGM 0, implicit [[COPY]], implicit %1
     %0:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3, implicit $exec
     undef %1.sub0:areg_128 = V_ACCVGPR_WRITE_B32_e64 %0.sub0, implicit $exec
     %1.sub1:areg_128 = COPY %1.sub0:areg_128
@@ -106,11 +109,12 @@
     liveins: $vgpr0_vgpr1
     ; GFX908-LABEL: name: test_nonmatching_agpr_subreg_no_propagate
     ; GFX908: liveins: $vgpr0_vgpr1
-    ; GFX908: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1, implicit $exec
-    ; GFX908: undef %1.sub0:areg_64 = V_ACCVGPR_WRITE_B32_e64 [[COPY]].sub0, implicit $exec
-    ; GFX908: %1.sub1:areg_64 = V_ACCVGPR_WRITE_B32_e64 [[COPY]].sub1, implicit $exec
-    ; GFX908: [[COPY1:%[0-9]+]]:areg_64 = COPY %1
-    ; GFX908: S_ENDPGM 0, implicit [[COPY]], implicit %1, implicit [[COPY1]]
+    ; GFX908-NEXT: {{  $}}
+    ; GFX908-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1, implicit $exec
+    ; GFX908-NEXT: undef %1.sub0:areg_64 = V_ACCVGPR_WRITE_B32_e64 [[COPY]].sub0, implicit $exec
+    ; GFX908-NEXT: %1.sub1:areg_64 = V_ACCVGPR_WRITE_B32_e64 [[COPY]].sub1, implicit $exec
+    ; GFX908-NEXT: [[COPY1:%[0-9]+]]:areg_64 = COPY %1
+    ; GFX908-NEXT: S_ENDPGM 0, implicit [[COPY]], implicit %1, implicit [[COPY1]]
     %0:vreg_64 = COPY $vgpr0_vgpr1, implicit $exec
     undef %1.sub0:areg_64 = V_ACCVGPR_WRITE_B32_e64 %0.sub0, implicit $exec
     %1.sub1:areg_64 = V_ACCVGPR_WRITE_B32_e64 %0.sub1, implicit $exec
@@ -126,11 +130,12 @@
     liveins: $vgpr0_vgpr1
     ; GFX908-LABEL: name: test_subreg_to_single_agpr_reg_propagate
     ; GFX908: liveins: $vgpr0_vgpr1
-    ; GFX908: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1, implicit $exec
-    ; GFX908: undef %1.sub0:areg_64 = V_ACCVGPR_WRITE_B32_e64 [[COPY]].sub0, implicit $exec
-    ; GFX908: %1.sub1:areg_64 = V_ACCVGPR_WRITE_B32_e64 [[COPY]].sub1, implicit $exec
-    ; GFX908: [[COPY1:%[0-9]+]]:agpr_32 = COPY [[COPY]].sub1
-    ; GFX908: S_ENDPGM 0, implicit [[COPY]], implicit %1, implicit [[COPY1]]
+    ; GFX908-NEXT: {{  $}}
+    ; GFX908-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1, implicit $exec
+    ; GFX908-NEXT: undef %1.sub0:areg_64 = V_ACCVGPR_WRITE_B32_e64 [[COPY]].sub0, implicit $exec
+    ; GFX908-NEXT: %1.sub1:areg_64 = V_ACCVGPR_WRITE_B32_e64 [[COPY]].sub1, implicit $exec
+    ; GFX908-NEXT: [[COPY1:%[0-9]+]]:agpr_32 = COPY [[COPY]].sub1
+    ; GFX908-NEXT: S_ENDPGM 0, implicit [[COPY]], implicit %1, implicit [[COPY1]]
     %0:vreg_64 = COPY $vgpr0_vgpr1, implicit $exec
     undef %1.sub0:areg_64 = V_ACCVGPR_WRITE_B32_e64 %0.sub0, implicit $exec
     %1.sub1:areg_64 = V_ACCVGPR_WRITE_B32_e64 %0.sub1, implicit $exec
diff --git a/llvm/test/CodeGen/AMDGPU/combine-sreg64-inits.mir b/llvm/test/CodeGen/AMDGPU/combine-sreg64-inits.mir
--- a/llvm/test/CodeGen/AMDGPU/combine-sreg64-inits.mir
+++ b/llvm/test/CodeGen/AMDGPU/combine-sreg64-inits.mir
@@ -1,36 +1,87 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -march=amdgcn -verify-machineinstrs -run-pass=liveintervals,amdgpu-pre-ra-optimizations %s -o - | FileCheck -check-prefix=GCN %s
 
 ---
-# GCN-LABEL: name: combine_sreg64_inits
-# GCN: %0:sgpr_64 = S_MOV_B64_IMM_PSEUDO 8589934593
-# GCN: S_NOP 0
 name:            combine_sreg64_inits
 tracksRegLiveness: true
 body:             |
   bb.0:
+    ; GCN-LABEL: name: combine_sreg64_inits
+    ; GCN: dead %0:sgpr_64 = S_MOV_B64_IMM_PSEUDO 8589934593
+    ; GCN-NEXT: S_NOP 0
     undef %0.sub0:sgpr_64 = S_MOV_B32 1
     S_NOP 0
     %0.sub1:sgpr_64 = S_MOV_B32 2
 ...
 ---
-# GCN-LABEL: name: combine_sreg64_inits_swap
-# GCN: %0:sgpr_64 = S_MOV_B64_IMM_PSEUDO 8589934593
-# GCN: S_NOP 0
 name:            combine_sreg64_inits_swap
 tracksRegLiveness: true
 body:             |
   bb.0:
+    ; GCN-LABEL: name: combine_sreg64_inits_swap
+    ; GCN: dead %0:sgpr_64 = S_MOV_B64_IMM_PSEUDO 8589934593
+    ; GCN-NEXT: S_NOP 0
     undef %0.sub1:sgpr_64 = S_MOV_B32 2
     S_NOP 0
     %0.sub0:sgpr_64 = S_MOV_B32 1
 ...
 ---
-# GCN-LABEL: name: sreg64_inits_different_blocks
-# GCN: undef %0.sub0:sgpr_64 = S_MOV_B32 1
-# GCN: %0.sub1:sgpr_64 = S_MOV_B32 2
+name: sreg64_subreg_copy_0
+tracksRegLiveness: true
+body: |
+  bb.0:
+    ; GCN-LABEL: name: sreg64_subreg_copy_0
+    ; GCN: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
+    ; GCN-NEXT: undef %1.sub0:sgpr_64 = COPY [[DEF]]
+    ; GCN-NEXT: %1.sub0:sgpr_64 = S_MOV_B32 1
+    ; GCN-NEXT: dead %1.sub1:sgpr_64 = S_MOV_B32 2
+    %0:sgpr_32 = IMPLICIT_DEF
+    undef %1.sub0:sgpr_64 = COPY %0:sgpr_32
+    %1.sub0:sgpr_64 = S_MOV_B32 1
+    %1.sub1:sgpr_64 = S_MOV_B32 2
+...
+---
+name: sreg64_subreg_copy_1
+tracksRegLiveness: true
+body: |
+  bb.0:
+    ; GCN-LABEL: name: sreg64_subreg_copy_1
+    ; GCN: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
+    ; GCN-NEXT: undef %1.sub0:sgpr_64 = S_MOV_B32 1
+    ; GCN-NEXT: %1.sub1:sgpr_64 = COPY [[DEF]]
+    ; GCN-NEXT: dead %1.sub1:sgpr_64 = S_MOV_B32 2
+    %0:sgpr_32 = IMPLICIT_DEF
+    undef %1.sub0:sgpr_64 = S_MOV_B32 1
+    %1.sub1:sgpr_64 = COPY %0:sgpr_32
+    %1.sub1:sgpr_64 = S_MOV_B32 2
+...
+---
+name: sreg64_subreg_copy_2
+tracksRegLiveness: true
+body: |
+  bb.0:
+    ; GCN-LABEL: name: sreg64_subreg_copy_2
+    ; GCN: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
+    ; GCN-NEXT: undef %1.sub0:sgpr_64 = S_MOV_B32 1
+    ; GCN-NEXT: %1.sub1:sgpr_64 = S_MOV_B32 2
+    ; GCN-NEXT: dead %1.sub0:sgpr_64 = COPY [[DEF]]
+    %0:sgpr_32 = IMPLICIT_DEF
+    undef %1.sub0:sgpr_64 = S_MOV_B32 1
+    %1.sub1:sgpr_64 = S_MOV_B32 2
+    %1.sub0:sgpr_64 = COPY %0:sgpr_32
+...
+---
 name:            sreg64_inits_different_blocks
 tracksRegLiveness: true
 body:             |
+  ; GCN-LABEL: name: sreg64_inits_different_blocks
+  ; GCN: bb.0:
+  ; GCN-NEXT:   successors: %bb.1(0x80000000)
+  ; GCN-NEXT: {{  $}}
+  ; GCN-NEXT:   undef %0.sub0:sgpr_64 = S_MOV_B32 1
+  ; GCN-NEXT: {{  $}}
+  ; GCN-NEXT: bb.1:
+  ; GCN-NEXT:   dead %0.sub1:sgpr_64 = S_MOV_B32 2
   bb.0:
     undef %0.sub0:sgpr_64 = S_MOV_B32 1
 
@@ -38,61 +89,61 @@
     %0.sub1:sgpr_64 = S_MOV_B32 2
 ...
 ---
-# GCN-LABEL: name: sreg64_inits_two_defs_sub1
-# GCN: undef %0.sub0:sgpr_64 = S_MOV_B32 1
-# GCN: %0.sub1:sgpr_64 = S_MOV_B32 2
-# GCN: %0.sub1:sgpr_64 = S_MOV_B32 3
 name:            sreg64_inits_two_defs_sub1
 tracksRegLiveness: true
 body:             |
   bb.0:
+    ; GCN-LABEL: name: sreg64_inits_two_defs_sub1
+    ; GCN: undef %0.sub0:sgpr_64 = S_MOV_B32 1
+    ; GCN-NEXT: %0.sub1:sgpr_64 = S_MOV_B32 2
+    ; GCN-NEXT: dead %0.sub1:sgpr_64 = S_MOV_B32 3
     undef %0.sub0:sgpr_64 = S_MOV_B32 1
     %0.sub1:sgpr_64 = S_MOV_B32 2
     %0.sub1:sgpr_64 = S_MOV_B32 3
 ...
 ---
-# GCN-LABEL: name: sreg64_inits_two_defs_sub0
-# GCN: undef %0.sub0:sgpr_64 = S_MOV_B32 1
-# GCN: %0.sub1:sgpr_64 = S_MOV_B32 2
-# GCN: %0.sub0:sgpr_64 = S_MOV_B32 3
 name:            sreg64_inits_two_defs_sub0
 tracksRegLiveness: true
 body:             |
   bb.0:
+    ; GCN-LABEL: name: sreg64_inits_two_defs_sub0
+    ; GCN: undef %0.sub0:sgpr_64 = S_MOV_B32 1
+    ; GCN-NEXT: %0.sub1:sgpr_64 = S_MOV_B32 2
+    ; GCN-NEXT: dead %0.sub0:sgpr_64 = S_MOV_B32 3
     undef %0.sub0:sgpr_64 = S_MOV_B32 1
     %0.sub1:sgpr_64 = S_MOV_B32 2
     %0.sub0:sgpr_64 = S_MOV_B32 3
 ...
 ---
-# GCN-LABEL: name: sreg64_inits_full_def
-# GCN: undef %1.sub0:sgpr_64 = S_MOV_B32 1
-# GCN: %0:sgpr_64 = S_MOV_B64 3
 name:            sreg64_inits_full_def
 tracksRegLiveness: true
 body:             |
   bb.0:
+    ; GCN-LABEL: name: sreg64_inits_full_def
+    ; GCN: dead undef %1.sub0:sgpr_64 = S_MOV_B32 1
+    ; GCN-NEXT: dead %0:sgpr_64 = S_MOV_B64 3
     undef %0.sub0:sgpr_64 = S_MOV_B32 1
     %0:sgpr_64 = S_MOV_B64 3
 ...
 ---
-# GCN-LABEL: name: sreg64_inits_imp_use
-# GCN: %0.sub0:sgpr_64 = S_MOV_B32 1, implicit $m0
-# GCN: %0.sub1:sgpr_64 = S_MOV_B32 2
 name:            sreg64_inits_imp_use
 tracksRegLiveness: true
 body:             |
   bb.0:
+    ; GCN-LABEL: name: sreg64_inits_imp_use
+    ; GCN: undef %0.sub0:sgpr_64 = S_MOV_B32 1, implicit $m0
+    ; GCN-NEXT: dead %0.sub1:sgpr_64 = S_MOV_B32 2
     undef %0.sub0:sgpr_64 = S_MOV_B32 1, implicit $m0
     %0.sub1:sgpr_64 = S_MOV_B32 2
 ...
 ---
-# GCN-LABEL: name: sreg64_inits_imp_def
-# GCN: %0.sub0:sgpr_64 = S_MOV_B32 1, implicit-def $scc
-# GCN: %0.sub1:sgpr_64 = S_MOV_B32 2
 name:            sreg64_inits_imp_def
 tracksRegLiveness: true
 body:             |
   bb.0:
+    ; GCN-LABEL: name: sreg64_inits_imp_def
+    ; GCN: undef %0.sub0:sgpr_64 = S_MOV_B32 1, implicit-def $scc
+    ; GCN-NEXT: dead %0.sub1:sgpr_64 = S_MOV_B32 2
     undef %0.sub0:sgpr_64 = S_MOV_B32 1, implicit-def $scc
     %0.sub1:sgpr_64 = S_MOV_B32 2
 ...