diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -1619,6 +1619,8 @@
     setLibcallName(RTLIB::SRA_I128, nullptr);
   }
 
+  setLibcallName(RTLIB::MULO_I128, nullptr);
+
   if (!Subtarget->isV9()) {
     // SparcV8 does not have FNEGD and FABSD.
     setOperationAction(ISD::FNEG, MVT::f64, Custom);
diff --git a/llvm/test/CodeGen/SPARC/overflow-intrinsic-optimizations.ll b/llvm/test/CodeGen/SPARC/overflow-intrinsic-optimizations.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/SPARC/overflow-intrinsic-optimizations.ll
@@ -0,0 +1,15 @@
+; RUN: llc %s -mtriple=sparc -o - | FileCheck %s
+; RUN: llc %s -mtriple=sparc64 -o - | FileCheck %s
+declare { i128, i1 } @llvm.smul.with.overflow.i128(i128, i128)
+
+define i32 @mul(i128 %a, i128 %b, i128* %r) {
+; CHECK-LABEL: mul
+; CHECK-NOT: call __muloti4
+  %mul4 = tail call { i128, i1 } @llvm.smul.with.overflow.i128(i128 %a, i128 %b)
+  %mul.val = extractvalue { i128, i1 } %mul4, 0
+  %mul.ov = extractvalue { i128, i1 } %mul4, 1
+  %mul.not.ov = xor i1 %mul.ov, true
+  store i128 %mul.val, i128* %r, align 16
+  %conv = zext i1 %mul.not.ov to i32
+  ret i32 %conv
+}