[MIPS] Detect MIPS application specific extensions like micromips

[jaydeep]

Summary

The patch detects MIPS application specific extensions (ASE) like micromips by reading ELF header.e_flags and SHT_MIPS_ABIFLAGS section. MIPS triple does not contain ASE information like micromips, mips16, DSP, MSA etc. These can be read from header.e_flags or SHT_MIPS_ABIFLAGS section.

[clayborg]

A few changes as noted in inlined comments.

source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp

418

Make "features_str" a "const char *". No need to construct a std::string just to pass a string argument. Or we can use llvm::StringRef objects for triple, cpu and features_str.

693

pass features_str.c_str() if we switch to "const char *" as mentioned above, else it will make an llvm::StringRef implicitly.

source/Plugins/Disassembler/llvm/DisassemblerLLVMC.h

44

Make "features_str" a "const char *". No need to construct a std::string just to pass a string argument. Or we can use llvm::StringRef objects for triple, cpu and features_str.

[jaydeep]

Addressed review comments.

[clayborg]

Looks good.

[jaydeep]

Closed by commit rL242381

include/lldb/Core/ArchSpec.h

enum MIPSSubType
         eMIPSSubType_mips32r6el,
         eMIPSSubType_mips64,
         eMIPSSubType_mips64r2,
         eMIPSSubType_mips64r6,
         eMIPSSubType_mips64el,
         eMIPSSubType_mips64r2el,
         eMIPSSubType_mips64r6el,
     };
-    
+    // Masks for the ases word of an ABI flags structure.
+    enum MIPSASE
+    {
+        eMIPSAse_dsp        = 0x00000001,   // DSP ASE
+        eMIPSAse_dspr2      = 0x00000002,   // DSP R2 ASE
+        eMIPSAse_eva        = 0x00000004,   // Enhanced VA Scheme
+        eMIPSAse_mcu        = 0x00000008,   // MCU (MicroController) ASE
+        eMIPSAse_mdmx       = 0x00000010,   // MDMX ASE
+        eMIPSAse_mips3d     = 0x00000020,   // MIPS-3D ASE
+        eMIPSAse_mt         = 0x00000040,   // MT ASE
+        eMIPSAse_smartmips  = 0x00000080,   // SmartMIPS ASE
+        eMIPSAse_virt       = 0x00000100,   // VZ ASE
+        eMIPSAse_msa        = 0x00000200,   // MSA ASE
+        eMIPSAse_mips16     = 0x00000400,   // MIPS16 ASE
+        eMIPSAse_micromips  = 0x00000800,   // MICROMIPS ASE
+        eMIPSAse_xpa        = 0x00001000,   // XPA ASE
+        eMIPSAse_mask       = 0x00001fff
+    };
+
     enum Core
     {
         eCore_arm_generic,
         eCore_arm_armv4,
         eCore_arm_armv4t,
         eCore_arm_armv5,
         eCore_arm_armv5e,
         eCore_arm_armv5t,
public:
     /// ARM CPUs.
     ///
     /// @return NULL or a valid stop info override callback for the
     ///     current architecture.
     //------------------------------------------------------------------
     StopInfoOverrideCallbackType
     GetStopInfoOverrideCallback () const;
 
+    uint32_t
+    GetFlags () const
+    {
+        return m_flags;
+    }
+
+    void
+    SetFlags (uint32_t flags)
+    {
+        m_flags = flags;
+    }
+
 protected:
     bool
     IsEqualTo (const ArchSpec& rhs, bool exact_match) const;
 
     llvm::Triple m_triple;
     Core m_core;
     lldb::ByteOrder m_byte_order;
 
+    // Additional arch flags which we cannot get from triple and core
+    // For MIPS these are application specific extensions like 
+    // micromips, mips16 etc.
+    uint32_t m_flags;
+
     ConstString m_distribution_id;
 
     // Called when m_def or m_entry are changed.  Fills in all remaining
     // members with default values.
     void
     CoreUpdated (bool update_triple);
 };
 

source/Core/ArchSpec.cpp

static const CoreDefinition g_core_definitions[] =
     { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb  , ArchSpec::eCore_thumbv7k        , "thumbv7k"  },
     { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb  , ArchSpec::eCore_thumbv7m        , "thumbv7m"  },
     { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb  , ArchSpec::eCore_thumbv7em       , "thumbv7em" },
     { eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, ArchSpec::eCore_arm_arm64       , "arm64"     },
     { eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, ArchSpec::eCore_arm_armv8       , "armv8"     },
     { eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, ArchSpec::eCore_arm_aarch64     , "aarch64"   },
 
     // mips32, mips32r2, mips32r3, mips32r5, mips32r6
-    { eByteOrderBig   , 4, 4, 4, llvm::Triple::mips  , ArchSpec::eCore_mips32         , "mips"      },
-    { eByteOrderBig   , 4, 4, 4, llvm::Triple::mips  , ArchSpec::eCore_mips32r2       , "mipsr2"    },
-    { eByteOrderBig   , 4, 4, 4, llvm::Triple::mips  , ArchSpec::eCore_mips32r3       , "mipsr3"    },
-    { eByteOrderBig   , 4, 4, 4, llvm::Triple::mips  , ArchSpec::eCore_mips32r5       , "mipsr5"    },
-    { eByteOrderBig   , 4, 4, 4, llvm::Triple::mips  , ArchSpec::eCore_mips32r6       , "mipsr6"    },
-    { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el       , "mipsel"    },
-    { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r2el     , "mipsr2el"  },
-    { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r3el     , "mipsr3el"  },
-    { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r5el     , "mipsr5el"  },
-    { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r6el     , "mipsr6el"  },
+    { eByteOrderBig   , 4, 2, 4, llvm::Triple::mips  , ArchSpec::eCore_mips32         , "mips"      },
+    { eByteOrderBig   , 4, 2, 4, llvm::Triple::mips  , ArchSpec::eCore_mips32r2       , "mipsr2"    },
+    { eByteOrderBig   , 4, 2, 4, llvm::Triple::mips  , ArchSpec::eCore_mips32r3       , "mipsr3"    },
+    { eByteOrderBig   , 4, 2, 4, llvm::Triple::mips  , ArchSpec::eCore_mips32r5       , "mipsr5"    },
+    { eByteOrderBig   , 4, 2, 4, llvm::Triple::mips  , ArchSpec::eCore_mips32r6       , "mipsr6"    },
+    { eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el       , "mipsel"    },
+    { eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r2el     , "mipsr2el"  },
+    { eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r3el     , "mipsr3el"  },
+    { eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r5el     , "mipsr5el"  },
+    { eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r6el     , "mipsr6el"  },
     
     // mips64, mips64r2, mips64r3, mips64r5, mips64r6
-    { eByteOrderBig   , 8, 4, 4, llvm::Triple::mips64  , ArchSpec::eCore_mips64         , "mips64"      },
-    { eByteOrderBig   , 8, 4, 4, llvm::Triple::mips64  , ArchSpec::eCore_mips64r2       , "mips64r2"    },
-    { eByteOrderBig   , 8, 4, 4, llvm::Triple::mips64  , ArchSpec::eCore_mips64r3       , "mips64r3"    },
-    { eByteOrderBig   , 8, 4, 4, llvm::Triple::mips64  , ArchSpec::eCore_mips64r5       , "mips64r5"    },
-    { eByteOrderBig   , 8, 4, 4, llvm::Triple::mips64  , ArchSpec::eCore_mips64r6       , "mips64r6"    },
-    { eByteOrderLittle, 8, 4, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64el       , "mips64el"    },
-    { eByteOrderLittle, 8, 4, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r2el     , "mips64r2el"  },
-    { eByteOrderLittle, 8, 4, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r3el     , "mips64r3el"  },
-    { eByteOrderLittle, 8, 4, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r5el     , "mips64r5el"  },
-    { eByteOrderLittle, 8, 4, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r6el     , "mips64r6el"  },
+    { eByteOrderBig   , 8, 2, 4, llvm::Triple::mips64  , ArchSpec::eCore_mips64         , "mips64"      },
+    { eByteOrderBig   , 8, 2, 4, llvm::Triple::mips64  , ArchSpec::eCore_mips64r2       , "mips64r2"    },
+    { eByteOrderBig   , 8, 2, 4, llvm::Triple::mips64  , ArchSpec::eCore_mips64r3       , "mips64r3"    },
+    { eByteOrderBig   , 8, 2, 4, llvm::Triple::mips64  , ArchSpec::eCore_mips64r5       , "mips64r5"    },
+    { eByteOrderBig   , 8, 2, 4, llvm::Triple::mips64  , ArchSpec::eCore_mips64r6       , "mips64r6"    },
+    { eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64el       , "mips64el"    },
+    { eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r2el     , "mips64r2el"  },
+    { eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r3el     , "mips64r3el"  },
+    { eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r5el     , "mips64r5el"  },
+    { eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r6el     , "mips64r6el"  },
     
     { eByteOrderBig   , 4, 4, 4, llvm::Triple::ppc    , ArchSpec::eCore_ppc_generic     , "powerpc"   },
     { eByteOrderBig   , 4, 4, 4, llvm::Triple::ppc    , ArchSpec::eCore_ppc_ppc601      , "ppc601"    },
     { eByteOrderBig   , 4, 4, 4, llvm::Triple::ppc    , ArchSpec::eCore_ppc_ppc602      , "ppc602"    },
     { eByteOrderBig   , 4, 4, 4, llvm::Triple::ppc    , ArchSpec::eCore_ppc_ppc603      , "ppc603"    },
     { eByteOrderBig   , 4, 4, 4, llvm::Triple::ppc    , ArchSpec::eCore_ppc_ppc603e     , "ppc603e"   },
     { eByteOrderBig   , 4, 4, 4, llvm::Triple::ppc    , ArchSpec::eCore_ppc_ppc603ev    , "ppc603ev"  },
     { eByteOrderBig   , 4, 4, 4, llvm::Triple::ppc    , ArchSpec::eCore_ppc_ppc604      , "ppc604"    },

 
 //===----------------------------------------------------------------------===//
 // Constructors and destructors.
 
 ArchSpec::ArchSpec() :
     m_triple (),
     m_core (kCore_invalid),
     m_byte_order (eByteOrderInvalid),
-    m_distribution_id ()
+    m_distribution_id (),
+    m_flags (0)
 {
 }
 
 ArchSpec::ArchSpec (const char *triple_cstr, Platform *platform) :
     m_triple (),
     m_core (kCore_invalid),
     m_byte_order (eByteOrderInvalid),
-    m_distribution_id ()
+    m_distribution_id (),
+    m_flags (0)
 {
     if (triple_cstr)
         SetTriple(triple_cstr, platform);
 }
 
 
 ArchSpec::ArchSpec (const char *triple_cstr) :
     m_triple (),
     m_core (kCore_invalid),
     m_byte_order (eByteOrderInvalid),
-    m_distribution_id ()
+    m_distribution_id (),
+    m_flags (0)
 {
     if (triple_cstr)
         SetTriple(triple_cstr);
 }
 
 ArchSpec::ArchSpec(const llvm::Triple &triple) :
     m_triple (),
     m_core (kCore_invalid),
     m_byte_order (eByteOrderInvalid),
-    m_distribution_id ()
+    m_distribution_id (),
+    m_flags (0)
 {
     SetTriple(triple);
 }
 
 ArchSpec::ArchSpec (ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) :
     m_triple (),
     m_core (kCore_invalid),
     m_byte_order (eByteOrderInvalid),
-    m_distribution_id ()
+    m_distribution_id (),
+    m_flags (0)
 {
     SetArchitecture (arch_type, cpu, subtype);
 }
 
 ArchSpec::~ArchSpec()
 {
 }
 
 //===----------------------------------------------------------------------===//
 // Assignment and initialization.
 
 const ArchSpec&
 ArchSpec::operator= (const ArchSpec& rhs)
 {
     if (this != &rhs)
     {
         m_triple = rhs.m_triple;
         m_core = rhs.m_core;
         m_byte_order = rhs.m_byte_order;
         m_distribution_id = rhs.m_distribution_id;
+        m_flags = rhs.m_flags;
     }
     return *this;
 }
 
 void
 ArchSpec::Clear()
 {
     m_triple = llvm::Triple();
     m_core = kCore_invalid;
     m_byte_order = eByteOrderInvalid;
     m_distribution_id.Clear ();
+    m_flags = 0;
 }
 
 //===----------------------------------------------------------------------===//
 // Predicates.
 
 
 const char *
 ArchSpec::GetArchitectureName () const

source/Plugins/Disassembler/llvm/DisassemblerLLVMC.h

 
 class DisassemblerLLVMC : public lldb_private::Disassembler
 {
     // Since we need to make two actual MC Disassemblers for ARM (ARM & THUMB), and there's a bit of goo to set up and own
     // in the MC disassembler world, I added this class to manage the actual disassemblers.
     class LLVMCDisassembler
     {
     public:
-        LLVMCDisassembler (const char *triple, const char *cpu, unsigned flavor, DisassemblerLLVMC &owner);
+        LLVMCDisassembler (const char *triple, const char *cpu, const char *features_str, unsigned flavor, DisassemblerLLVMC &owner);
 
         ~LLVMCDisassembler();
 
         uint64_t GetMCInst (const uint8_t *opcode_data, size_t opcode_data_len, lldb::addr_t pc, llvm::MCInst &mc_inst);
         uint64_t PrintMCInst (llvm::MCInst &mc_inst, char *output_buffer, size_t out_buffer_len);
         void     SetStyle (bool use_hex_immed, HexImmediateStyle hex_style);
         bool     CanBranch (llvm::MCInst &mc_inst);
         bool     IsValid()

source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp

protected:
     DisassemblerSP          m_disasm_sp; // for ownership
     LazyBool                m_does_branch;
     bool                    m_is_valid;
     bool                    m_using_file_addr;
 };
 
 
 
-DisassemblerLLVMC::LLVMCDisassembler::LLVMCDisassembler (const char *triple, const char *cpu, unsigned flavor, DisassemblerLLVMC &owner):
+DisassemblerLLVMC::LLVMCDisassembler::LLVMCDisassembler (const char *triple, const char *cpu, const char *features_str, unsigned flavor, DisassemblerLLVMC &owner):
     m_is_valid(true)
 {
     std::string Error;
     const llvm::Target *curr_target = llvm::TargetRegistry::lookupTarget(triple, Error);
     if (!curr_target)
     {
         m_is_valid = false;
         return;
     }
 
     m_instr_info_ap.reset(curr_target->createMCInstrInfo());
     m_reg_info_ap.reset (curr_target->createMCRegInfo(triple));
 
-    std::string features_str;
-
     m_subtarget_info_ap.reset(curr_target->createMCSubtargetInfo(triple, cpu,
                                                                 features_str));
 
     std::unique_ptr<llvm::MCRegisterInfo> reg_info(curr_target->createMCRegInfo(triple));
     m_asm_info_ap.reset(curr_target->createMCAsmInfo(*reg_info, triple));
 
     if (m_instr_info_ap.get() == NULL || m_reg_info_ap.get() == NULL || m_subtarget_info_ap.get() == NULL || m_asm_info_ap.get() == NULL)
     {
switch (arch.GetCore())
         case ArchSpec::eCore_mips64r5el:
             cpu = "mips64r5"; break;
         case ArchSpec::eCore_mips64r6:
         case ArchSpec::eCore_mips64r6el:
             cpu = "mips64r6"; break;
         default:
             cpu = ""; break;
     }
-    
-    m_disasm_ap.reset (new LLVMCDisassembler(triple, cpu, flavor, *this));
+    std::string features_str = "";
+    if (arch.GetTriple().getArch() == llvm::Triple::mips || arch.GetTriple().getArch() == llvm::Triple::mipsel
+        || arch.GetTriple().getArch() == llvm::Triple::mips64 || arch.GetTriple().getArch() == llvm::Triple::mips64el)
+    {
+        uint32_t arch_flags = arch.GetFlags ();
+        if (arch_flags & ArchSpec::eMIPSAse_msa)
+            features_str += "+msa,";
+        if (arch_flags & ArchSpec::eMIPSAse_dsp)
+            features_str += "+dsp,";
+        if (arch_flags & ArchSpec::eMIPSAse_dspr2)
+            features_str += "+dspr2,";
+        if (arch_flags & ArchSpec::eMIPSAse_mips16)
+            features_str += "+mips16,";
+        if (arch_flags & ArchSpec::eMIPSAse_micromips)
+            features_str += "+micromips,";
+    }
+    
+    m_disasm_ap.reset (new LLVMCDisassembler(triple, cpu, features_str.c_str(), flavor, *this));
     if (!m_disasm_ap->IsValid())
     {
         // We use m_disasm_ap.get() to tell whether we are valid or not, so if this isn't good for some reason,
         // we reset it, and then we won't be valid and FindPlugin will fail and we won't get used.
         m_disasm_ap.reset();
     }
 
     // For arm CPUs that can execute arm or thumb instructions, also create a thumb instruction disassembler.
     if (arch.GetTriple().getArch() == llvm::Triple::arm)
     {
         std::string thumb_triple(thumb_arch.GetTriple().getTriple());
-        m_alternate_disasm_ap.reset(new LLVMCDisassembler(thumb_triple.c_str(), "", flavor, *this));
+        m_alternate_disasm_ap.reset(new LLVMCDisassembler(thumb_triple.c_str(), "", "", flavor, *this));
         if (!m_alternate_disasm_ap->IsValid())
         {
             m_disasm_ap.reset();
             m_alternate_disasm_ap.reset();
         }
     }
 }
 

source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp

switch (arch.GetCore())
             cpu = "mips64r5"; break;
         case ArchSpec::eCore_mips64r6:
         case ArchSpec::eCore_mips64r6el:
             cpu = "mips64r6"; break;
         default:
             cpu = "generic"; break;
     }
 
+    std::string features = "";
+    uint32_t arch_flags = arch.GetFlags ();
+    if (arch_flags & ArchSpec::eMIPSAse_msa)
+        features += "+msa,";
+    if (arch_flags & ArchSpec::eMIPSAse_dsp)
+        features += "+dsp,";
+    if (arch_flags & ArchSpec::eMIPSAse_dspr2)
+        features += "+dspr2,";
+    if (arch_flags & ArchSpec::eMIPSAse_mips16)
+        features += "+mips16,";
+    if (arch_flags & ArchSpec::eMIPSAse_micromips)
+        features += "+micromips,";
+
     m_reg_info.reset (target->createMCRegInfo (triple.getTriple()));
     assert (m_reg_info.get());
 
     m_insn_info.reset (target->createMCInstrInfo());
     assert (m_insn_info.get());
 
     m_asm_info.reset (target->createMCAsmInfo (*m_reg_info, triple.getTriple()));
-    m_subtype_info.reset (target->createMCSubtargetInfo (triple.getTriple(), cpu, ""));
+    m_subtype_info.reset (target->createMCSubtargetInfo (triple.getTriple(), cpu, features));
     assert (m_asm_info.get() && m_subtype_info.get());
 
     m_context.reset (new llvm::MCContext (m_asm_info.get(), m_reg_info.get(), nullptr));
     assert (m_context.get());
 
     m_disasm.reset (target->createMCDisassembler (*m_subtype_info, *m_context));
     assert (m_disasm.get());
 }

source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp

switch (arch.GetCore())
             cpu = "mips64r5"; break;
         case ArchSpec::eCore_mips64r6:
         case ArchSpec::eCore_mips64r6el:
             cpu = "mips64r6"; break;
         default:
             cpu = "generic"; break;
     }
 
+    std::string features = "";
+    uint32_t arch_flags = arch.GetFlags ();
+    if (arch_flags & ArchSpec::eMIPSAse_msa)
+        features += "+msa,";
+    if (arch_flags & ArchSpec::eMIPSAse_dsp)
+        features += "+dsp,";
+    if (arch_flags & ArchSpec::eMIPSAse_dspr2)
+        features += "+dspr2,";
+    if (arch_flags & ArchSpec::eMIPSAse_mips16)
+        features += "+mips16,";
+    if (arch_flags & ArchSpec::eMIPSAse_micromips)
+        features += "+micromips,";
+
     m_reg_info.reset (target->createMCRegInfo (triple.getTriple()));
     assert (m_reg_info.get());
 
     m_insn_info.reset (target->createMCInstrInfo());
     assert (m_insn_info.get());
 
     m_asm_info.reset (target->createMCAsmInfo (*m_reg_info, triple.getTriple()));
-    m_subtype_info.reset (target->createMCSubtargetInfo (triple.getTriple(), cpu, ""));
+    m_subtype_info.reset (target->createMCSubtargetInfo (triple.getTriple(), cpu, features));
     assert (m_asm_info.get() && m_subtype_info.get());
 
     m_context.reset (new llvm::MCContext (m_asm_info.get(), m_reg_info.get(), nullptr));
     assert (m_context.get());
 
     m_disasm.reset (target->createMCDisassembler (*m_subtype_info, *m_context));
     assert (m_disasm.get());
 }

source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp

if (arch_spec.GetTriple ().getOS () == llvm::Triple::OSType::UnknownOS)
         arch_spec.SetArchitecture (eArchTypeELF, header.e_machine, sub_type, header.e_ident[EI_OSABI]);
         //
         // Validate if it is ok to remove GetOsFromOSABI
         GetOsFromOSABI (header.e_ident[EI_OSABI], ostype);
         spec_ostype = arch_spec.GetTriple ().getOS ();
         assert(spec_ostype == ostype);
     }
 
+    if (arch_spec.GetMachine() == llvm::Triple::mips || arch_spec.GetMachine() == llvm::Triple::mipsel
+        || arch_spec.GetMachine() == llvm::Triple::mips64 || arch_spec.GetMachine() == llvm::Triple::mips64el)
+    {
+        switch (header.e_flags & llvm::ELF::EF_MIPS_ARCH_ASE)
+        {
+            case llvm::ELF::EF_MIPS_MICROMIPS:  
+                arch_spec.SetFlags (ArchSpec::eMIPSAse_micromips); 
+                break;
+            case llvm::ELF::EF_MIPS_ARCH_ASE_M16: 
+                arch_spec.SetFlags (ArchSpec::eMIPSAse_mips16); 
+                break;
+            case llvm::ELF::EF_MIPS_ARCH_ASE_MDMX: 
+                arch_spec.SetFlags (ArchSpec::eMIPSAse_mdmx); 
+                break;
+            default: 
+                break;
+        }
+    }
+
     // If there are no section headers we are done.
     if (header.e_shnum == 0)
         return 0;
 
     Log *log(lldb_private::GetLogIfAllCategoriesSet (LIBLLDB_LOG_MODULES));
 
     section_headers.resize(header.e_shnum);
     if (section_headers.size() != header.e_shnum)
if (strtab_idx && strtab_idx < section_headers.size())
             {
                 static ConstString g_sect_name_gnu_debuglink (".gnu_debuglink");
                 const ELFSectionHeaderInfo &header = *I;
                 const uint64_t section_size = header.sh_type == SHT_NOBITS ? 0 : header.sh_size;
                 ConstString name(shstr_data.PeekCStr(I->sh_name));
 
                 I->section_name = name;
 
+                if (arch_spec.GetMachine() == llvm::Triple::mips || arch_spec.GetMachine() == llvm::Triple::mipsel
+                    || arch_spec.GetMachine() == llvm::Triple::mips64 || arch_spec.GetMachine() == llvm::Triple::mips64el)
+                {
+                    if (header.sh_type == SHT_MIPS_ABIFLAGS)
+                    {
+                        DataExtractor data;
+                        if (section_size && (data.SetData (object_data, header.sh_offset, section_size) == section_size))
+                        {
+                            lldb::offset_t ase_offset = 12; // MIPS ABI Flags Version: 0
+                            uint32_t arch_flags = arch_spec.GetFlags ();
+                            arch_flags |= data.GetU32 (&ase_offset);
+                            arch_spec.SetFlags (arch_flags);
+                        }
+                    }
+                }
+
                 if (name == g_sect_name_gnu_debuglink)
                 {
                     DataExtractor data;
                     if (section_size && (data.SetData (object_data, header.sh_offset, section_size) == section_size))
                     {
                         lldb::offset_t gnu_debuglink_offset = 0;
                         gnu_debuglink_file = data.GetCStr (&gnu_debuglink_offset);
                         gnu_debuglink_offset = llvm::RoundUpToAlignment (gnu_debuglink_offset, 4);