Index: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp =================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -5477,18 +5477,21 @@ if (Operands.size() != 6) return; - ARMOperand &Op3 = static_cast(*Operands[3]); - ARMOperand &Op4 = static_cast(*Operands[4]); + const auto &Op3 = static_cast(*Operands[3]); + auto &Op4 = static_cast(*Operands[4]); if (!Op3.isReg() || !Op4.isReg()) return; + auto Op3Reg = Op3.getReg(); + auto Op4Reg = Op4.getReg(); + // For most Thumb2 cases we just generate the 3 operand form and reduce // it in processInstruction(), but for ADD involving PC the the 3 operand // form won't accept PC so we do the transformation here. - ARMOperand &Op5 = static_cast(*Operands[5]); + auto &Op5 = static_cast(*Operands[5]); if (isThumbTwo()) { if (Mnemonic != "add" || - !(Op3.getReg() == ARM::PC || Op4.getReg() == ARM::PC || + !(Op3Reg == ARM::PC || Op4Reg == ARM::PC || (Op5.isReg() && Op5.getReg() == ARM::PC))) return; } else if (!isThumbOne()) @@ -5503,15 +5506,15 @@ // If first 2 operands of a 3 operand instruction are the same // then transform to 2 operand version of the same instruction // e.g. 'adds r0, r0, #1' transforms to 'adds r0, #1' - bool Transform = Op3.getReg() == Op4.getReg(); + bool Transform = Op3Reg == Op4Reg; // For communtative operations, we might be able to transform if we swap // Op4 and Op5. The 'ADD Rdm, SP, Rdm' form is already handled specially // as tADDrsp. const ARMOperand *LastOp = &Op5; bool Swap = false; - if (!Transform && Op5.isReg() && Op3.getReg() == Op5.getReg() && - ((Mnemonic == "add" && Op4.getReg() != ARM::SP) || + if (!Transform && Op5.isReg() && Op3Reg == Op5.getReg() && + ((Mnemonic == "add" && Op4Reg != ARM::SP) || Mnemonic == "and" || Mnemonic == "eor" || Mnemonic == "adc" || Mnemonic == "orr")) { Swap = true; Index: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s =================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s +++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s @@ -49,7 +49,6 @@ adcs r0, r1, r3, lsl #7 adc.w r0, r1, r3, lsr #31 adcs.w r0, r1, r3, asr #32 - add r2, sp, ip @ CHECK: adc.w r4, r5, r6 @ encoding: [0x45,0xeb,0x06,0x04] @ CHECK: adcs.w r4, r5, r6 @ encoding: [0x55,0xeb,0x06,0x04] @@ -59,7 +58,6 @@ @ CHECK: adcs.w r0, r1, r3, lsl #7 @ encoding: [0x51,0xeb,0xc3,0x10] @ CHECK: adc.w r0, r1, r3, lsr #31 @ encoding: [0x41,0xeb,0xd3,0x70] @ CHECK: adcs.w r0, r1, r3, asr #32 @ encoding: [0x51,0xeb,0x23,0x00] -@ CHECK: add.w r2, sp, r12 @ encoding: [0x0d,0xeb,0x0c,0x02] @------------------------------------------------------------------------------ @@ -115,23 +113,99 @@ @------------------------------------------------------------------------------ -@ ADD (register) +@ ADD (register, not SP) A8.8.6 @------------------------------------------------------------------------------ add r1, r2, r8 add r5, r9, r2, asr #32 adds r7, r3, r1, lsl #31 adds.w r0, r3, r6, lsr #25 add.w r4, r8, r1, ror #12 + adds r1, r1, r7 // T1 + it eq + addeq r1, r3, r5 // T1 + it eq + addeq r1, r1, r5 // T1 + it eq + addseq r1, r3, r5 // T3 + it eq + addseq r1, r1, r5 // T3 add r10, r8 add r10, r10, r8 + it eq + addeq r1, r10 // T2 + it eq + addseq r1, r10 // T3 @ CHECK: add.w r1, r2, r8 @ encoding: [0x02,0xeb,0x08,0x01] @ CHECK: add.w r5, r9, r2, asr #32 @ encoding: [0x09,0xeb,0x22,0x05] @ CHECK: adds.w r7, r3, r1, lsl #31 @ encoding: [0x13,0xeb,0xc1,0x77] @ CHECK: adds.w r0, r3, r6, lsr #25 @ encoding: [0x13,0xeb,0x56,0x60] @ CHECK: add.w r4, r8, r1, ror #12 @ encoding: [0x08,0xeb,0x31,0x34] +@ CHECK: adds r1, r1, r7 @ encoding: [0xc9,0x19] +@ CHECK: it eq @ encoding: [0x08,0xbf] +@ CHECK: addeq r1, r3, r5 @ encoding: [0x59,0x19] +@ CHECK: it eq @ encoding: [0x08,0xbf] +@ CHECK: addeq r1, r1, r5 @ encoding: [0x49,0x19] +@ CHECK: it eq @ encoding: [0x08,0xbf] +@ CHECK: addseq.w r1, r3, r5 @ encoding: [0x13,0xeb,0x05,0x01] +@ CHECK: it eq @ encoding: [0x08,0xbf] +@ CHECK: addseq.w r1, r1, r5 @ encoding: [0x11,0xeb,0x05,0x01] @ CHECK: add r10, r8 @ encoding: [0xc2,0x44] @ CHECK: add r10, r8 @ encoding: [0xc2,0x44] +@ CHECK: it eq @ encoding: [0x08,0xbf] +@ CHECK: addeq r1, r10 @ encoding: [0x51,0x44] +@ CHECK: it eq @ encoding: [0x08,0xbf] +@ CHECK: addseq.w r1, r1, r10 @ encoding: [0x11,0xeb,0x0a,0x01] + +@------------------------------------------------------------------------------ +@ ADD (SP plus immediate) A8.8.9 +@------------------------------------------------------------------------------ + it eq +@ CHECK: it eq @ encoding: [0x08,0xbf] + addeq r7, sp, #1020 // T1 +@ CHECK: addeq r7, sp, #1020 @ encoding: [0xff,0xaf] + + it eq +@ CHECK: it eq @ encoding: [0x08,0xbf] + addeq sp, sp, #508 // T2 +@ FIXME: ARMARM says 'addeq sp, sp, #508' +@ CHECK: addeq sp, #508 @ encoding: [0x7f,0xb0] + + add r7, sp, #15 // T3 +@ CHECK: add.w r7, sp, #15 @ encoding: [0x0d,0xf1,0x0f,0x07] + adds r7, sp, #16 // T3 +@ CHECK: adds.w r7, sp, #16 @ encoding: [0x1d,0xf1,0x10,0x07] + add r8, sp, #16 // T3 +@ CHECK: add.w r8, sp, #16 @ encoding: [0x0d,0xf1,0x10,0x08] + + addw r6, sp, #1020 // T4 +@ CHECK: addw r6, sp, #1020 @ encoding: [0x0d,0xf2,0xfc,0x36] + add r6, sp, #1019 // T4 +@ CHECK: addw r6, sp, #1019 @ encoding: [0x0d,0xf2,0xfb,0x36] + +@------------------------------------------------------------------------------ +@ ADD (SP plus register) A8.8.10 +@------------------------------------------------------------------------------ + it eq +@ CHECK: it eq @ encoding: [0x08,0xbf] + addeq r8, sp, r8 // T1 +@ CHECK: addeq r8, sp, r8 @ encoding: [0xe8,0x44] + it eq +@ CHECK: it eq @ encoding: [0x08,0xbf] + addeq r8, sp // T1 +@ CHECK: addeq r8, sp @ encoding: [0xe8,0x44] + + it eq +@ CHECK: it eq @ encoding: [0x08,0xbf] + addeq sp, r9 // T2 +@ CHECK: addeq sp, r9 @ encoding: [0xcd,0x44] + + add r2, sp, ip // T3 +@ CHECK: add.w r2, sp, r12 @ encoding: [0x0d,0xeb,0x0c,0x02] + it eq +@ CHECK: it eq @ encoding: [0x08,0xbf] + addeq r2, sp, ip // T3 +@ CHECK: addeq.w r2, sp, r12 @ encoding: [0x0d,0xeb,0x0c,0x02] @------------------------------------------------------------------------------