diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir b/llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir
@@ -0,0 +1,289 @@
+# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+# RUN: llc -mtriple riscv32 -mattr=+zve64x -start-before=prologepilog -o - \
+# RUN:     -verify-machineinstrs %s | FileCheck %s --check-prefix=RV32
+# RUN: llc -mtriple riscv32 -mattr=+v -start-before=prologepilog -o - \
+# RUN:     -verify-machineinstrs %s | FileCheck %s --check-prefix=RV32
+# RUN: llc -mtriple riscv64 -mattr=+zve64x -start-before=prologepilog -o - \
+# RUN:     -verify-machineinstrs %s | FileCheck %s --check-prefix=RV64
+# RUN: llc -mtriple riscv64 -mattr=+v -start-before=prologepilog -o - \
+# RUN:     -verify-machineinstrs %s | FileCheck %s --check-prefix=RV64
+--- |
+  target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
+  target triple = "riscv64"
+
+  declare void @extern(<vscale x 4 x i32>*)
+
+  define void @rvv_stack_align8() #0 {
+  ; RV32-LABEL: rvv_stack_align8:
+  ; RV32:       # %bb.0:
+  ; RV32-NEXT:    addi sp, sp, -48
+  ; RV32-NEXT:    sw ra, 44(sp) # 4-byte Folded Spill
+  ; RV32-NEXT:    csrr a0, vlenb
+  ; RV32-NEXT:    slli a0, a0, 1
+  ; RV32-NEXT:    sub sp, sp, a0
+  ; RV32-NEXT:    addi a0, sp, 32
+  ; RV32-NEXT:    addi a1, sp, 16
+  ; RV32-NEXT:    addi a2, sp, 8
+  ; RV32-NEXT:    call extern@plt
+  ; RV32-NEXT:    csrr a0, vlenb
+  ; RV32-NEXT:    slli a0, a0, 1
+  ; RV32-NEXT:    add sp, sp, a0
+  ; RV32-NEXT:    lw ra, 44(sp) # 4-byte Folded Reload
+  ; RV32-NEXT:    addi sp, sp, 48
+  ; RV32-NEXT:    ret
+  ;
+  ; RV64-LABEL: rvv_stack_align8:
+  ; RV64:       # %bb.0:
+  ; RV64-NEXT:    addi sp, sp, -32
+  ; RV64-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+  ; RV64-NEXT:    csrr a0, vlenb
+  ; RV64-NEXT:    slli a0, a0, 1
+  ; RV64-NEXT:    sub sp, sp, a0
+  ; RV64-NEXT:    addi a0, sp, 24
+  ; RV64-NEXT:    addi a1, sp, 16
+  ; RV64-NEXT:    addi a2, sp, 8
+  ; RV64-NEXT:    call extern@plt
+  ; RV64-NEXT:    csrr a0, vlenb
+  ; RV64-NEXT:    slli a0, a0, 1
+  ; RV64-NEXT:    add sp, sp, a0
+  ; RV64-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+  ; RV64-NEXT:    addi sp, sp, 32
+  ; RV64-NEXT:    ret
+    %a = alloca <vscale x 4 x i32>, align 8
+    %b = alloca i64
+    %c = alloca i64
+    call void @extern(<vscale x 4 x i32>* %a)
+    ret void
+  }
+
+  ; FIXME: The alloca is not correctly aligned to 16 bytes.
+
+  define void @rvv_stack_align16() #0 {
+  ; RV32-LABEL: rvv_stack_align16:
+  ; RV32:       # %bb.0:
+  ; RV32-NEXT:    addi sp, sp, -48
+  ; RV32-NEXT:    sw ra, 44(sp) # 4-byte Folded Spill
+  ; RV32-NEXT:    csrr a0, vlenb
+  ; RV32-NEXT:    slli a0, a0, 1
+  ; RV32-NEXT:    sub sp, sp, a0
+  ; RV32-NEXT:    addi a0, sp, 32
+  ; RV32-NEXT:    addi a1, sp, 16
+  ; RV32-NEXT:    addi a2, sp, 8
+  ; RV32-NEXT:    call extern@plt
+  ; RV32-NEXT:    csrr a0, vlenb
+  ; RV32-NEXT:    slli a0, a0, 1
+  ; RV32-NEXT:    add sp, sp, a0
+  ; RV32-NEXT:    lw ra, 44(sp) # 4-byte Folded Reload
+  ; RV32-NEXT:    addi sp, sp, 48
+  ; RV32-NEXT:    ret
+  ;
+  ; RV64-LABEL: rvv_stack_align16:
+  ; RV64:       # %bb.0:
+  ; RV64-NEXT:    addi sp, sp, -32
+  ; RV64-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+  ; RV64-NEXT:    csrr a0, vlenb
+  ; RV64-NEXT:    slli a0, a0, 1
+  ; RV64-NEXT:    sub sp, sp, a0
+  ; RV64-NEXT:    addi a0, sp, 24
+  ; RV64-NEXT:    addi a1, sp, 16
+  ; RV64-NEXT:    addi a2, sp, 8
+  ; RV64-NEXT:    call extern@plt
+  ; RV64-NEXT:    csrr a0, vlenb
+  ; RV64-NEXT:    slli a0, a0, 1
+  ; RV64-NEXT:    add sp, sp, a0
+  ; RV64-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+  ; RV64-NEXT:    addi sp, sp, 32
+  ; RV64-NEXT:    ret
+    %a = alloca <vscale x 4 x i32>, align 16
+    %b = alloca i64
+    %c = alloca i64
+    call void @extern(<vscale x 4 x i32>* %a)
+    ret void
+  }
+
+  ; FIXME: The alloca is not correctly aligned to 32 bytes.
+
+  define void @rvv_stack_align32() #0 {
+  ; RV32-LABEL: rvv_stack_align32:
+  ; RV32:       # %bb.0:
+  ; RV32-NEXT:    addi sp, sp, -32
+  ; RV32-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
+  ; RV32-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
+  ; RV32-NEXT:    addi s0, sp, 32
+  ; RV32-NEXT:    csrr a0, vlenb
+  ; RV32-NEXT:    slli a0, a0, 1
+  ; RV32-NEXT:    sub sp, sp, a0
+  ; RV32-NEXT:    andi sp, sp, -32
+  ; RV32-NEXT:    addi a0, sp, 24
+  ; RV32-NEXT:    addi a1, sp, 16
+  ; RV32-NEXT:    addi a2, sp, 8
+  ; RV32-NEXT:    call extern@plt
+  ; RV32-NEXT:    addi sp, s0, -32
+  ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
+  ; RV32-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
+  ; RV32-NEXT:    addi sp, sp, 32
+  ; RV32-NEXT:    ret
+  ;
+  ; RV64-LABEL: rvv_stack_align32:
+  ; RV64:       # %bb.0:
+  ; RV64-NEXT:    addi sp, sp, -32
+  ; RV64-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+  ; RV64-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+  ; RV64-NEXT:    addi s0, sp, 32
+  ; RV64-NEXT:    csrr a0, vlenb
+  ; RV64-NEXT:    slli a0, a0, 1
+  ; RV64-NEXT:    sub sp, sp, a0
+  ; RV64-NEXT:    andi sp, sp, -32
+  ; RV64-NEXT:    addi a0, sp, 16
+  ; RV64-NEXT:    addi a1, sp, 8
+  ; RV64-NEXT:    mv a2, sp
+  ; RV64-NEXT:    call extern@plt
+  ; RV64-NEXT:    addi sp, s0, -32
+  ; RV64-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+  ; RV64-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+  ; RV64-NEXT:    addi sp, sp, 32
+  ; RV64-NEXT:    ret
+    %a = alloca <vscale x 4 x i32>, align 32
+    %b = alloca i64
+    %c = alloca i64
+    call void @extern(<vscale x 4 x i32>* %a)
+    ret void
+  }
+
+  attributes #0 = { nounwind nofree nosync }
+...
+---
+name:            rvv_stack_align8
+alignment:       4
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    8
+  adjustsStack:    false
+  hasCalls:        true
+  stackProtector:  ''
+  maxCallFrameSize: 4294967295
+  cvBytesOfCalleeSavedRegisters: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  hasTailCall:     false
+  localFrameSize:  0
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      []
+stack:
+  - { id: 0, name: a, type: default, offset: 0, size: 16, alignment: 8,
+      stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 1, name: b, type: default, offset: 0, size: 8, alignment: 8,
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 2, name: c, type: default, offset: 0, size: 8, alignment: 8,
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+body:             |
+  bb.0 (%ir-block.0):
+    ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2
+    $x10 = ADDI %stack.0.a, 0
+    $x11 = ADDI %stack.1.b, 0
+    $x12 = ADDI %stack.2.c, 0
+    PseudoCALL target-flags(riscv-plt) @extern, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2
+    ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2
+    PseudoRET
+
+...
+---
+name:            rvv_stack_align16
+alignment:       4
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    16
+  adjustsStack:    false
+  hasCalls:        true
+  stackProtector:  ''
+  maxCallFrameSize: 4294967295
+  cvBytesOfCalleeSavedRegisters: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  hasTailCall:     false
+  localFrameSize:  0
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      []
+stack:
+  - { id: 0, name: a, type: default, offset: 0, size: 16, alignment: 16,
+      stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 1, name: b, type: default, offset: 0, size: 8, alignment: 8,
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 2, name: c, type: default, offset: 0, size: 8, alignment: 8,
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+body:             |
+  bb.0 (%ir-block.0):
+    ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2
+    $x10 = ADDI %stack.0.a, 0
+    $x11 = ADDI %stack.1.b, 0
+    $x12 = ADDI %stack.2.c, 0
+    PseudoCALL target-flags(riscv-plt) @extern, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2
+    ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2
+    PseudoRET
+
+...
+---
+name:            rvv_stack_align32
+alignment:       4
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    32
+  adjustsStack:    false
+  hasCalls:        true
+  stackProtector:  ''
+  maxCallFrameSize: 4294967295
+  cvBytesOfCalleeSavedRegisters: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  hasTailCall:     false
+  localFrameSize:  0
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      []
+stack:
+  - { id: 0, name: a, type: default, offset: 0, size: 16, alignment: 32,
+      stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 1, name: b, type: default, offset: 0, size: 8, alignment: 8,
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 2, name: c, type: default, offset: 0, size: 8, alignment: 8,
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+body:             |
+  bb.0 (%ir-block.0):
+    ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2
+    $x10 = ADDI %stack.0.a, 0
+    $x11 = ADDI %stack.1.b, 0
+    $x12 = ADDI %stack.2.c, 0
+    PseudoCALL target-flags(riscv-plt) @extern, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2
+    ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2
+    PseudoRET
+
+...