[InlineAsm, SystemZ] Handle inline assembly address operands.

[jonpa]

Summary

Handle ZQ, ZR, ZS, ZT and p inline assembly operand constraints. These represent address operands on SystemZ as used by the Load Address instruction.

These have most things in common with memory operands in the way they need to be handled, except that the instruction using the address does not actually touch memory.

Just like with memory operands, the address can be folded into the using instruction to various degrees. For example, ZT and p allow Base + Index + 20-bit displacement, while ZS does not allow the index register.

In order to handle address operands I made them a subclass of the possible memory operands. They are recognized by their memory constraint codes and a new method isAddress() returns true for these. That way a memory operand can be recognized to actually touch memory or not. I first experimented with a new ConstraintType C_Address (like C_Memory), but it seemed simpler to let them be a type of memory operands instead.

There is still the general/default handling of 'p' which seems to be to treat it as a register. Currently it would be up to each target to handle addresses differently (per this patch).

Todo: CodeGenPrepare could also optimize for address folding for these just like for memory operands, I think.

Feedback most welcome!

[uweigand]

Finally getting back to this patch - sorry for the long delay.

I think it would be worthwhile to explore using a dedicated C_Address constraint type - these constraints are different from memory. In particular, memory constraints usually require the front-end to also use the "indirect" flag since the asm statement requires the address as argument. For actual address operands, these are already addresses at the source level, so they are not indirect.

Using different C_Address and C_Memory types would also force all places that treat constaints to be explicitly updated to handle address constraints, requiring deliberate choices. This seems preferable since the constraint types frequently do require different treatment.

As an aside, in addition to SelectionDAGBuilder, which this patch updates, there is also inline asm constraint handling in GlobalISel/InlineAsmLowering which needs similar changes.

Finally, I tried to play with address constraints on Intel, and the "p" constraint as currently implemented on Intel seems to be actually incorrect. For example, compiling the following code:

void *test (void *ptr)
{
        void *ret;
        asm ("lea %1, %0" : "=r" (ret) : "p" (ptr));
        return ret;
}

with GCC results in:

lea %rdi, %rax
ret

while with clang we get instead:

movq    %rdi, -8(%rsp)
leaq    -8(%rsp), %rax
retq

(i.e. we get the address of a stack slot where ptr was stored, rather than the value of ptr)

So it might make sense to have two patches instead, a first patch that introduces the C_Address mechanism, and uses it to implement the "p" constraint in a platform-independent manner, fixing in particular this bug on Intel. And then in a second patch add the SystemZ-specific address constraints.

[jonpa]

Patch updated per review...

Using different C_Address and C_Memory types would also force all places that treat constaints to be explicitly updated to handle address constraints, requiring deliberate choices. This seems preferable since the constraint types frequently do require different treatment.

Ok - I tried this at https://reviews.llvm.org/D122220.

So it might make sense to have two patches instead, a first patch that introduces the C_Address mechanism, and uses it to implement the "p" constraint in a platform-independent manner, fixing in particular this bug on Intel. And then in a second patch add the SystemZ-specific address constraints.

This patch here is now the SystemZ specific address constraints, on top of the patch for "p" (see above).

[jonpa]

Formatting.

[uweigand]

LGTM, thanks!

clang/lib/Basic/Targets/SystemZ.h

public:
 
   bool validateAsmConstraint(const char *&Name,
                              TargetInfo::ConstraintInfo &info) const override;
 
   std::string convertConstraint(const char *&Constraint) const override {
     switch (Constraint[0]) {
     case 'p': // Keep 'p' constraint.
       return std::string("p");
+    case 'Z':
+      switch (Constraint[1]) {
+      case 'Q': // Address with base and unsigned 12-bit displacement
+      case 'R': // Likewise, plus an index
+      case 'S': // Address with base and signed 20-bit displacement
+      case 'T': // Likewise, plus an index
+        // "^" hints llvm that this is a 2 letter constraint.
+        // "Constraint++" is used to promote the string iterator
+        // to the next constraint.
+        return std::string("^") + std::string(Constraint++, 2);
+      default:
+        break;
+      }
+      break;
     default:
       break;
     }
     return TargetInfo::convertConstraint(Constraint);
   }
 
   const char *getClobbers() const override {
     // FIXME: Is this really right?

clang/lib/Basic/Targets/SystemZ.cpp

 }
 
 bool SystemZTargetInfo::validateAsmConstraint(
     const char *&Name, TargetInfo::ConstraintInfo &Info) const {
   switch (*Name) {
   default:
     return false;
 
+  case 'Z':
+    switch (Name[1]) {
+    default:
+      return false;
+    case 'Q': // Address with base and unsigned 12-bit displacement
+    case 'R': // Likewise, plus an index
+    case 'S': // Address with base and signed 20-bit displacement
+    case 'T': // Likewise, plus an index
+      break;
+    }
+    LLVM_FALLTHROUGH;
   case 'a': // Address register
   case 'd': // Data register (equivalent to 'r')
   case 'f': // Floating-point register
   case 'v': // Vector register
     Info.setAllowsRegister();
     return true;
 
   case 'I': // Unsigned 8-bit constant

clang/test/CodeGen/SystemZ/systemz-inline-asm-03.c

 // RUN: %clang_cc1 -no-opaque-pointers -triple s390x-linux-gnu -O2 -emit-llvm \
 // RUN:   -o - %s 2>&1 | FileCheck %s
 // REQUIRES: systemz-registered-target
 
 long *A;
 long Idx;
 unsigned long Addr;
 
+unsigned long fun_BD12_Q() {
+// CHECK-LABEL: define{{.*}} i64 @fun_BD12_Q()
+// CHECK: call i64 asm "lay $0, $1", "=r,^ZQ"(i64* nonnull %arrayidx)
+  asm("lay %0, %1" : "=r" (Addr) : "ZQ" (&A[100]));
+  return Addr;
+}
+
+unsigned long fun_BD12_R() {
+// CHECK-LABEL: define{{.*}} i64 @fun_BD12_R()
+// CHECK: call i64 asm "lay $0, $1", "=r,^ZR"(i64* nonnull %arrayidx)
+  asm("lay %0, %1" : "=r" (Addr) : "ZR" (&A[100]));
+  return Addr;
+}
+
+unsigned long fun_BD12_S() {
+// CHECK-LABEL: define{{.*}} i64 @fun_BD12_S()
+// CHECK: call i64 asm "lay $0, $1", "=r,^ZS"(i64* nonnull %arrayidx)
+  asm("lay %0, %1" : "=r" (Addr) : "ZS" (&A[100]));
+  return Addr;
+}
+
+unsigned long fun_BD12_T() {
+// CHECK-LABEL: define{{.*}} i64 @fun_BD12_T()
+// CHECK: call i64 asm "lay $0, $1", "=r,^ZT"(i64* nonnull %arrayidx)
+  asm("lay %0, %1" : "=r" (Addr) : "ZT" (&A[100]));
+  return Addr;
+}
+
 unsigned long fun_BD12_p() {
 // CHECK-LABEL: define{{.*}} i64 @fun_BD12_p()
 // CHECK: call i64 asm "lay $0, $1", "=r,p"(i64* nonnull %arrayidx)
   asm("lay %0, %1" : "=r" (Addr) : "p" (&A[100]));
   return Addr;
 }
 
+unsigned long fun_BDX12_Q() {
+// CHECK-LABEL: define{{.*}} i64 @fun_BDX12_Q()
+// CHECK: call i64 asm "lay $0, $1", "=r,^ZQ"(i64* %arrayidx)
+  asm("lay %0, %1" : "=r" (Addr) : "ZQ" (&A[Idx + 100]));
+  return Addr;
+}
+
+unsigned long fun_BDX12_R() {
+// CHECK-LABEL: define{{.*}} i64 @fun_BDX12_R()
+// CHECK: call i64 asm "lay $0, $1", "=r,^ZR"(i64* %arrayidx)
+  asm("lay %0, %1" : "=r" (Addr) : "ZR" (&A[Idx + 100]));
+  return Addr;
+}
+
+unsigned long fun_BDX12_S() {
+// CHECK-LABEL: define{{.*}} i64 @fun_BDX12_S()
+// CHECK: call i64 asm "lay $0, $1", "=r,^ZS"(i64* %arrayidx)
+  asm("lay %0, %1" : "=r" (Addr) : "ZS" (&A[Idx + 100]));
+  return Addr;
+}
+
+unsigned long fun_BDX12_T() {
+// CHECK-LABEL: define{{.*}} i64 @fun_BDX12_T()
+// CHECK: call i64 asm "lay $0, $1", "=r,^ZT"(i64* %arrayidx)
+  asm("lay %0, %1" : "=r" (Addr) : "ZT" (&A[Idx + 100]));
+  return Addr;
+}
+
 unsigned long fun_BDX12_p() {
 // CHECK-LABEL: define{{.*}} i64 @fun_BDX12_p()
 // CHECK: call i64 asm "lay $0, $1", "=r,p"(i64* %arrayidx)
   asm("lay %0, %1" : "=r" (Addr) : "p" (&A[Idx + 100]));
   return Addr;
 }
 
+unsigned long fun_BD20_Q() {
+// CHECK-LABEL: define{{.*}} i64 @fun_BD20_Q()
+// CHECK: call i64 asm "lay $0, $1", "=r,^ZQ"(i64* nonnull %arrayidx)
+  asm("lay %0, %1" : "=r" (Addr) : "ZQ" (&A[1000]));
+  return Addr;
+}
+
+unsigned long fun_BD20_R() {
+// CHECK-LABEL: define{{.*}} i64 @fun_BD20_R()
+// CHECK: call i64 asm "lay $0, $1", "=r,^ZR"(i64* nonnull %arrayidx)
+  asm("lay %0, %1" : "=r" (Addr) : "ZR" (&A[1000]));
+  return Addr;
+}
+
+unsigned long fun_BD20_S() {
+// CHECK-LABEL: define{{.*}} i64 @fun_BD20_S()
+// CHECK: call i64 asm "lay $0, $1", "=r,^ZS"(i64* nonnull %arrayidx)
+  asm("lay %0, %1" : "=r" (Addr) : "ZS" (&A[1000]));
+  return Addr;
+}
+
+unsigned long fun_BD20_T() {
+// CHECK-LABEL: define{{.*}} i64 @fun_BD20_T()
+// CHECK: call i64 asm "lay $0, $1", "=r,^ZT"(i64* nonnull %arrayidx)
+  asm("lay %0, %1" : "=r" (Addr) : "ZT" (&A[1000]));
+  return Addr;
+}
+
 unsigned long fun_BD20_p() {
 // CHECK-LABEL: define{{.*}} i64 @fun_BD20_p()
 // CHECK: call i64 asm "lay $0, $1", "=r,p"(i64* nonnull %arrayidx)
   asm("lay %0, %1" : "=r" (Addr) : "p" (&A[1000]));
   return Addr;
 }
 
+unsigned long fun_BDX20_Q() {
+// CHECK-LABEL: define{{.*}} i64 @fun_BDX20_Q()
+// CHECK: call i64 asm "lay $0, $1", "=r,^ZQ"(i64* %arrayidx)
+  asm("lay %0, %1" : "=r" (Addr) : "ZQ" (&A[Idx + 1000]));
+  return Addr;
+}
+
+unsigned long fun_BDX20_R() {
+// CHECK-LABEL: define{{.*}} i64 @fun_BDX20_R()
+// CHECK: call i64 asm "lay $0, $1", "=r,^ZR"(i64* %arrayidx)
+  asm("lay %0, %1" : "=r" (Addr) : "ZR" (&A[Idx + 1000]));
+  return Addr;
+}
+
+unsigned long fun_BDX20_S() {
+// CHECK-LABEL: define{{.*}} i64 @fun_BDX20_S()
+// CHECK: call i64 asm "lay $0, $1", "=r,^ZS"(i64* %arrayidx)
+  asm("lay %0, %1" : "=r" (Addr) : "ZS" (&A[Idx + 1000]));
+  return Addr;
+}
+
+unsigned long fun_BDX20_T() {
+// CHECK-LABEL: define{{.*}} i64 @fun_BDX20_T()
+// CHECK: call i64 asm "lay $0, $1", "=r,^ZT"(i64* %arrayidx)
+  asm("lay %0, %1" : "=r" (Addr) : "ZT" (&A[Idx + 1000]));
+  return Addr;
+}
+
 unsigned long fun_BDX20_p() {
 // CHECK-LABEL: define{{.*}} i64 @fun_BDX20_p()
 // CHECK: call i64 asm "lay $0, $1", "=r,p"(i64* %arrayidx)
   asm("lay %0, %1" : "=r" (Addr) : "p" (&A[Idx + 1000]));
   return Addr;
 }

llvm/include/llvm/IR/InlineAsm.h

enum : uint32_t {
     Constraint_Uy,
     Constraint_X,
     Constraint_Z,
     Constraint_ZC,
     Constraint_Zy,
 
     // Address constraints
     Constraint_p,
+    Constraint_ZQ,
+    Constraint_ZR,
+    Constraint_ZS,
+    Constraint_ZT,
 
-    Constraints_Max = Constraint_p,
+    Constraints_Max = Constraint_ZT,
     Constraints_ShiftAmount = 16,
 
     Flag_MatchingOperand = 0x80000000
   };
 
   static unsigned getFlagWord(unsigned Kind, unsigned NumOps) {
     assert(((NumOps << 3) & ~0xffff) == 0 && "Too many inline asm operands!");
     assert(Kind >= Kind_RegUse && Kind <= Kind_Mem && "Invalid Kind");
static StringRef getMemConstraintName(unsigned Constraint) {
     case InlineAsm::Constraint_Z:
       return "Z";
     case InlineAsm::Constraint_ZC:
       return "ZC";
     case InlineAsm::Constraint_Zy:
       return "Zy";
     case InlineAsm::Constraint_p:
       return "p";
+    case InlineAsm::Constraint_ZQ:
+      return "ZQ";
+    case InlineAsm::Constraint_ZR:
+      return "ZR";
+    case InlineAsm::Constraint_ZS:
+      return "ZS";
+    case InlineAsm::Constraint_ZT:
+      return "ZT";
     default:
       llvm_unreachable("Unknown memory constraint");
     }
   }
 };
 
 } // end namespace llvm
 
 #endif // LLVM_IR_INLINEASM_H

llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp

SelectInlineAsmMemoryOperand(const SDValue &Op,
   SystemZAddressingMode::DispRange DispRange;
   SDValue Base, Disp, Index;
 
   switch(ConstraintID) {
   default:
     llvm_unreachable("Unexpected asm memory constraint");
   case InlineAsm::Constraint_i:
   case InlineAsm::Constraint_Q:
+  case InlineAsm::Constraint_ZQ:
     // Accept an address with a short displacement, but no index.
     Form = SystemZAddressingMode::FormBD;
     DispRange = SystemZAddressingMode::Disp12Only;
     break;
   case InlineAsm::Constraint_R:
+  case InlineAsm::Constraint_ZR:
     // Accept an address with a short displacement and an index.
     Form = SystemZAddressingMode::FormBDXNormal;
     DispRange = SystemZAddressingMode::Disp12Only;
     break;
   case InlineAsm::Constraint_S:
+  case InlineAsm::Constraint_ZS:
     // Accept an address with a long displacement, but no index.
     Form = SystemZAddressingMode::FormBD;
     DispRange = SystemZAddressingMode::Disp20Only;
     break;
   case InlineAsm::Constraint_T:
   case InlineAsm::Constraint_m:
   case InlineAsm::Constraint_o:
   case InlineAsm::Constraint_p:
+  case InlineAsm::Constraint_ZT:
     // Accept an address with a long displacement and an index.
     // m works the same as T, as this is the most general case.
     // We don't really have any special handling of "offsettable"
     // memory addresses, so just treat o the same as m.
     Form = SystemZAddressingMode::FormBDXNormal;
     DispRange = SystemZAddressingMode::Disp20Only;
     break;
   }

llvm/lib/Target/SystemZ/SystemZISelLowering.h

if (ConstraintCode.size() == 1) {
         return InlineAsm::Constraint_Q;
       case 'R':
         return InlineAsm::Constraint_R;
       case 'S':
         return InlineAsm::Constraint_S;
       case 'T':
         return InlineAsm::Constraint_T;
       }
+    } else if (ConstraintCode.size() == 2 && ConstraintCode[0] == 'Z') {
+      switch (ConstraintCode[1]) {
+      default:
+        break;
+      case 'Q':
+        return InlineAsm::Constraint_ZQ;
+      case 'R':
+        return InlineAsm::Constraint_ZR;
+      case 'S':
+        return InlineAsm::Constraint_ZS;
+      case 'T':
+        return InlineAsm::Constraint_ZT;
+      }
     }
     return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
   }
 
   Register getRegisterByName(const char *RegName, LLT VT,
                              const MachineFunction &MF) const override;
 
   /// If a physical register, this returns the register that receives the

llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

if (Constraint.size() == 1) {
     case 'K': // Signed 16-bit constant
     case 'L': // Signed 20-bit displacement (on all targets we support)
     case 'M': // 0x7fffffff
       return C_Immediate;
 
     default:
       break;
     }
+  } else if (Constraint.size() == 2 && Constraint[0] == 'Z') {
+    switch (Constraint[1]) {
+    case 'Q': // Address with base and unsigned 12-bit displacement
+    case 'R': // Likewise, plus an index
+    case 'S': // Address with base and signed 20-bit displacement
+    case 'T': // Likewise, plus an index
+      return C_Address;
+
+    default:
+      break;
+    }
   }
   return TargetLowering::getConstraintType(Constraint);
 }
 
 TargetLowering::ConstraintWeight SystemZTargetLowering::
 getSingleConstraintMatchWeight(AsmOperandInfo &info,
                                const char *constraint) const {
   ConstraintWeight weight = CW_Invalid;

llvm/test/CodeGen/SystemZ/inline-asm-addr.ll

 ; RUN: llc -mtriple=s390x-linux-gnu < %s | FileCheck %s
 
 @Addr = global i64 0, align 8
 @A = global i64* null, align 8
 @Idx = global i64 0, align 8
 
+define i64 @fun_BD12_Q() {
+; CHECK-LABEL: fun_BD12_Q:
+; CHECK: #APP
+; CHECK: lay  %r2, 800(%r1)
+entry:
+  %0 = load i64*, i64** @A
+  %arrayidx = getelementptr inbounds i64, i64* %0, i64 100
+  %1 = tail call i64 asm "lay $0, $1", "=r,^ZQ"(i64* nonnull %arrayidx)
+  store i64 %1, i64* @Addr
+  ret i64 %1
+}
+
+define i64 @fun_BD12_R() {
+; CHECK-LABEL: fun_BD12_R:
+; CHECK: #APP
+; CHECK: lay  %r2, 800(%r1)
+entry:
+  %0 = load i64*, i64** @A
+  %arrayidx = getelementptr inbounds i64, i64* %0, i64 100
+  %1 = tail call i64 asm "lay $0, $1", "=r,^ZR"(i64* nonnull %arrayidx)
+  store i64 %1, i64* @Addr
+  ret i64 %1
+}
+
+define i64 @fun_BD12_S() {
+; CHECK-LABEL: fun_BD12_S:
+; CHECK: #APP
+; CHECK: lay  %r2, 800(%r1)
+entry:
+  %0 = load i64*, i64** @A
+  %arrayidx = getelementptr inbounds i64, i64* %0, i64 100
+  %1 = tail call i64 asm "lay $0, $1", "=r,^ZS"(i64* nonnull %arrayidx)
+  store i64 %1, i64* @Addr
+  ret i64 %1
+}
+
+define i64 @fun_BD12_T() {
+; CHECK-LABEL: fun_BD12_T:
+; CHECK: #APP
+; CHECK: lay  %r2, 800(%r1)
+entry:
+  %0 = load i64*, i64** @A
+  %arrayidx = getelementptr inbounds i64, i64* %0, i64 100
+  %1 = tail call i64 asm "lay $0, $1", "=r,^ZT"(i64* nonnull %arrayidx)
+  store i64 %1, i64* @Addr
+  ret i64 %1
+}
+
 define i64 @fun_BD12_p() {
 ; CHECK-LABEL: fun_BD12_p:
 ; CHECK: #APP
 ; CHECK: lay  %r2, 800(%r1)
 entry:
   %0 = load i64*, i64** @A
   %arrayidx = getelementptr inbounds i64, i64* %0, i64 100
   %1 = tail call i64 asm "lay $0, $1", "=r,p"(i64* nonnull %arrayidx)
   store i64 %1, i64* @Addr
   ret i64 %1
 }
 
+define i64 @fun_BDX12_Q() {
+; CHECK-LABEL: fun_BDX12_Q:
+; CHECK: #APP
+; CHECK: lay  %r2, 800(%r2)
+entry:
+  %0 = load i64*, i64** @A
+  %1 = load i64, i64* @Idx
+  %add = add nsw i64 %1, 100
+  %arrayidx = getelementptr inbounds i64, i64* %0, i64 %add
+  %2 = tail call i64 asm "lay $0, $1", "=r,^ZQ"(i64* %arrayidx)
+  store i64 %2, i64* @Addr
+  ret i64 %2
+}
+
+define i64 @fun_BDX12_R() {
+; CHECK-LABEL: fun_BDX12_R:
+; CHECK: #APP
+; CHECK: lay  %r2, 800(%r1,%r2)
+entry:
+  %0 = load i64*, i64** @A
+  %1 = load i64, i64* @Idx
+  %add = add nsw i64 %1, 100
+  %arrayidx = getelementptr inbounds i64, i64* %0, i64 %add
+  %2 = tail call i64 asm "lay $0, $1", "=r,^ZR"(i64* %arrayidx)
+  store i64 %2, i64* @Addr
+  ret i64 %2
+}
+
+define i64 @fun_BDX12_S() {
+; CHECK-LABEL: fun_BDX12_S:
+; CHECK: #APP
+; CHECK: lay  %r2, 800(%r2)
+entry:
+  %0 = load i64*, i64** @A
+  %1 = load i64, i64* @Idx
+  %add = add nsw i64 %1, 100
+  %arrayidx = getelementptr inbounds i64, i64* %0, i64 %add
+  %2 = tail call i64 asm "lay $0, $1", "=r,^ZS"(i64* %arrayidx)
+  store i64 %2, i64* @Addr
+  ret i64 %2
+}
+
+define i64 @fun_BDX12_T() {
+; CHECK-LABEL: fun_BDX12_T:
+; CHECK: #APP
+; CHECK: lay  %r2, 800(%r1,%r2)
+entry:
+  %0 = load i64*, i64** @A
+  %1 = load i64, i64* @Idx
+  %add = add nsw i64 %1, 100
+  %arrayidx = getelementptr inbounds i64, i64* %0, i64 %add
+  %2 = tail call i64 asm "lay $0, $1", "=r,^ZT"(i64* %arrayidx)
+  store i64 %2, i64* @Addr
+  ret i64 %2
+}
+
 define i64 @fun_BDX12_p() {
 ; CHECK-LABEL: fun_BDX12_p:
 ; CHECK: #APP
 ; CHECK: lay  %r2, 800(%r1,%r2)
 entry:
   %0 = load i64*, i64** @A
   %1 = load i64, i64* @Idx
   %add = add nsw i64 %1, 100
   %arrayidx = getelementptr inbounds i64, i64* %0, i64 %add
   %2 = tail call i64 asm "lay $0, $1", "=r,p"(i64* %arrayidx)
   store i64 %2, i64* @Addr
   ret i64 %2
 }
 
+define i64 @fun_BD20_Q() {
+; CHECK-LABEL: fun_BD20_Q:
+; CHECK: #APP
+; CHECK: lay  %r2, 0(%r2)
+entry:
+  %0 = load i64*, i64** @A
+  %arrayidx = getelementptr inbounds i64, i64* %0, i64 1000
+  %1 = tail call i64 asm "lay $0, $1", "=r,^ZQ"(i64* nonnull %arrayidx)
+  store i64 %1, i64* @Addr
+  ret i64 %1
+}
+
+define i64 @fun_BD20_R() {
+; CHECK-LABEL: fun_BD20_R:
+; CHECK: #APP
+; CHECK: lay  %r2, 0(%r2)
+entry:
+  %0 = load i64*, i64** @A
+  %arrayidx = getelementptr inbounds i64, i64* %0, i64 1000
+  %1 = tail call i64 asm "lay $0, $1", "=r,^ZR"(i64* nonnull %arrayidx)
+  store i64 %1, i64* @Addr
+  ret i64 %1
+}
+
+define i64 @fun_BD20_S() {
+; CHECK-LABEL: fun_BD20_S:
+; CHECK: #APP
+; CHECK: lay  %r2, 8000(%r1)
+entry:
+  %0 = load i64*, i64** @A
+  %arrayidx = getelementptr inbounds i64, i64* %0, i64 1000
+  %1 = tail call i64 asm "lay $0, $1", "=r,^ZS"(i64* nonnull %arrayidx)
+  store i64 %1, i64* @Addr
+  ret i64 %1
+}
+
+define i64 @fun_BD20_T() {
+; CHECK-LABEL: fun_BD20_T:
+; CHECK: #APP
+; CHECK: lay  %r2, 8000(%r1)
+entry:
+  %0 = load i64*, i64** @A
+  %arrayidx = getelementptr inbounds i64, i64* %0, i64 1000
+  %1 = tail call i64 asm "lay $0, $1", "=r,^ZT"(i64* nonnull %arrayidx)
+  store i64 %1, i64* @Addr
+  ret i64 %1
+}
+
 define i64 @fun_BD20_p() {
 ; CHECK-LABEL: fun_BD20_p:
 ; CHECK: #APP
 ; CHECK: lay  %r2, 8000(%r1)
 entry:
   %0 = load i64*, i64** @A
   %arrayidx = getelementptr inbounds i64, i64* %0, i64 1000
   %1 = tail call i64 asm "lay $0, $1", "=r,p"(i64* nonnull %arrayidx)
   store i64 %1, i64* @Addr
   ret i64 %1
 }
 
+define i64 @fun_BDX20_Q() {
+; CHECK-LABEL: fun_BDX20_Q:
+; CHECK: #APP
+; CHECK: lay  %r2, 0(%r1)
+entry:
+  %0 = load i64*, i64** @A
+  %1 = load i64, i64* @Idx
+  %add = add nsw i64 %1, 1000
+  %arrayidx = getelementptr inbounds i64, i64* %0, i64 %add
+  %2 = tail call i64 asm "lay $0, $1", "=r,^ZQ"(i64* %arrayidx)
+  store i64 %2, i64* @Addr
+  ret i64 %2
+}
+
+define i64 @fun_BDX20_R() {
+; CHECK-LABEL: fun_BDX20_R:
+; CHECK: #APP
+; CHECK: lay  %r2, 0(%r1)
+entry:
+  %0 = load i64*, i64** @A
+  %1 = load i64, i64* @Idx
+  %add = add nsw i64 %1, 1000
+  %arrayidx = getelementptr inbounds i64, i64* %0, i64 %add
+  %2 = tail call i64 asm "lay $0, $1", "=r,^ZR"(i64* %arrayidx)
+  store i64 %2, i64* @Addr
+  ret i64 %2
+}
+
+define i64 @fun_BDX20_S() {
+; CHECK-LABEL: fun_BDX20_S:
+; CHECK: #APP
+; CHECK: lay  %r2, 8000(%r2)
+entry:
+  %0 = load i64*, i64** @A
+  %1 = load i64, i64* @Idx
+  %add = add nsw i64 %1, 1000
+  %arrayidx = getelementptr inbounds i64, i64* %0, i64 %add
+  %2 = tail call i64 asm "lay $0, $1", "=r,^ZS"(i64* %arrayidx)
+  store i64 %2, i64* @Addr
+  ret i64 %2
+}
+
+define i64 @fun_BDX20_T() {
+; CHECK-LABEL: fun_BDX20_T:
+; CHECK: #APP
+; CHECK: lay  %r2, 8000(%r1,%r2)
+entry:
+  %0 = load i64*, i64** @A
+  %1 = load i64, i64* @Idx
+  %add = add nsw i64 %1, 1000
+  %arrayidx = getelementptr inbounds i64, i64* %0, i64 %add
+  %2 = tail call i64 asm "lay $0, $1", "=r,^ZT"(i64* %arrayidx)
+  store i64 %2, i64* @Addr
+  ret i64 %2
+}
+
 define i64 @fun_BDX20_p() {
 ; CHECK-LABEL: fun_BDX20_p:
 ; CHECK: #APP
 ; CHECK: lay  %r2, 8000(%r1,%r2)
 entry:
   %0 = load i64*, i64** @A
   %1 = load i64, i64* @Idx
   %add = add nsw i64 %1, 1000
   %arrayidx = getelementptr inbounds i64, i64* %0, i64 %add
   %2 = tail call i64 asm "lay $0, $1", "=r,p"(i64* %arrayidx)
   store i64 %2, i64* @Addr
   ret i64 %2
 }