Implement SystemZIselLowering::hasAndNot

[MatzeB]

Summary

• SystemZ appears to have the vnc instruction producing an "and-not" effect. Therefore SystemZIselLowering::hasAndNot can return true.
• This led to different patterns generated for abs which are added here as well.

This change improves SystemZ codegen and will avoid code generation regressions with https://reviews.llvm.org/D109194

[uweigand]

llvm/lib/Target/SystemZ/SystemZInstrVector.td

933

Are you sure these are right? Unless I'm missing something, they appear to be swapped:

Looking at the first pattern, if x is positive then the shift value will be 0, therefore the and will be 0, therefore the xor will be a no-op and the return is -x. If x is negative, the shift value will be -1, so the and is a no-op, and the result is -x ^ x ^ -x, which is x. So in summary the pattern matches x >= 0 ? -x : x, which is the *negated* absolute value, while the pattern resolves to lp, which compute the absolute value.

Also, I think these patterns would be more readable if broken up into multiple lines like the other patterns in this group - the indentation shows more easily how the operations are grouped.

[MatzeB]

I abandoned D109194 in favor of a SelectionDAG/X86 solution in D112754 so this is not necessary anymore to avoid regressions. Abandoning.

llvm/lib/Target/SystemZ/SystemZISelLowering.h

public:
   }
   bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override {
     ConstantInt* Mask = dyn_cast<ConstantInt>(AndI.getOperand(1));
     return Mask && Mask->getValue().isIntN(16);
   }
   bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
     return VT.isScalarInteger();
   }
+  bool hasAndNot(SDValue V) const override {
+    return V.getValueType().isVector();
+  }
   EVT getSetCCResultType(const DataLayout &DL, LLVMContext &,
                          EVT) const override;
   bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
                                   EVT VT) const override;
   bool isFPImmLegal(const APFloat &Imm, EVT VT,
                     bool ForCodeSize) const override;
   bool hasInlineStackProbe(MachineFunction &MF) const override;
   bool isLegalICmpImmediate(int64_t Imm) const override;

llvm/lib/Target/SystemZ/SystemZInstrVector.td

def : Pat<(type (or (and (z_vsra_by_scalar VR128:$x, (i32 shift)),
                         (and (z_vnot (z_vsra_by_scalar VR128:$x, (i32 shift))),
                              VR128:$x))),
               (lp VR128:$x)>;
     def : Pat<(type (or (and (z_vsra_by_scalar VR128:$x, (i32 shift)),
                              VR128:$x),
                         (and (z_vnot (z_vsra_by_scalar VR128:$x, (i32 shift))),
                              (z_vneg VR128:$x)))),
               (lc (lp VR128:$x))>;
+    def : Pat<(type (xor (and (xor (z_vneg VR128:$x), VR128:$x), (z_vsra_by_scalar VR128:$x, (i32 shift))), (z_vneg VR128:$x))),
+              (lp VR128:$x)>;
+    def : Pat<(type (xor (and (xor VR128:$x, (z_vneg VR128:$x)), (z_vsra_by_scalar VR128:$x, (i32 shift))), VR128:$x)),
+              (lc (lp VR128:$x))>;
   }
 }
 
 defm : IntegerAbsoluteVectorOps<v16i8, VLCB, VLPB, 7>;
 defm : IntegerAbsoluteVectorOps<v8i16, VLCH, VLPH, 15>;
 defm : IntegerAbsoluteVectorOps<v4i32, VLCF, VLPF, 31>;
 defm : IntegerAbsoluteVectorOps<v2i64, VLCG, VLPG, 63>;
 

llvm/test/CodeGen/SystemZ/vec-abs-01.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; Test v16i8 absolute.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
 
 ; Test with slt.
 define <16 x i8> @f1(<16 x i8> %val) {
 ; CHECK-LABEL: f1:
-; CHECK: vlpb %v24, %v24
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vlpb %v24, %v24
+; CHECK-NEXT:    br %r14
   %cmp = icmp slt <16 x i8> %val, zeroinitializer
   %neg = sub <16 x i8> zeroinitializer, %val
   %ret = select <16 x i1> %cmp, <16 x i8> %neg, <16 x i8> %val
   ret <16 x i8> %ret
 }
 
 ; Test with sle.
 define <16 x i8> @f2(<16 x i8> %val) {
 ; CHECK-LABEL: f2:
-; CHECK: vlpb %v24, %v24
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vlpb %v24, %v24
+; CHECK-NEXT:    br %r14
   %cmp = icmp sle <16 x i8> %val, zeroinitializer
   %neg = sub <16 x i8> zeroinitializer, %val
   %ret = select <16 x i1> %cmp, <16 x i8> %neg, <16 x i8> %val
   ret <16 x i8> %ret
 }
 
 ; Test with sgt.
 define <16 x i8> @f3(<16 x i8> %val) {
 ; CHECK-LABEL: f3:
-; CHECK: vlpb %v24, %v24
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vlpb %v24, %v24
+; CHECK-NEXT:    br %r14
   %cmp = icmp sgt <16 x i8> %val, zeroinitializer
   %neg = sub <16 x i8> zeroinitializer, %val
   %ret = select <16 x i1> %cmp, <16 x i8> %val, <16 x i8> %neg
   ret <16 x i8> %ret
 }
 
 ; Test with sge.
 define <16 x i8> @f4(<16 x i8> %val) {
 ; CHECK-LABEL: f4:
-; CHECK: vlpb %v24, %v24
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vlpb %v24, %v24
+; CHECK-NEXT:    br %r14
   %cmp = icmp sge <16 x i8> %val, zeroinitializer
   %neg = sub <16 x i8> zeroinitializer, %val
   %ret = select <16 x i1> %cmp, <16 x i8> %val, <16 x i8> %neg
   ret <16 x i8> %ret
 }
 
 ; Test that negative absolute uses VLPB too.  There is no vector equivalent
 ; of LOAD NEGATIVE.
 define <16 x i8> @f5(<16 x i8> %val) {
 ; CHECK-LABEL: f5:
-; CHECK: vlpb [[REG:%v[0-9]+]], %v24
-; CHECK: vlcb %v24, [[REG]]
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vlpb %v0, %v24
+; CHECK-NEXT:    vlcb %v24, %v0
+; CHECK-NEXT:    br %r14
   %cmp = icmp slt <16 x i8> %val, zeroinitializer
   %neg = sub <16 x i8> zeroinitializer, %val
   %abs = select <16 x i1> %cmp, <16 x i8> %neg, <16 x i8> %val
   %ret = sub <16 x i8> zeroinitializer, %abs
   ret <16 x i8> %ret
 }
 
 ; Try another form of negative absolute (slt version).
 define <16 x i8> @f6(<16 x i8> %val) {
 ; CHECK-LABEL: f6:
-; CHECK: vlpb [[REG:%v[0-9]+]], %v24
-; CHECK: vlcb %v24, [[REG]]
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vlpb %v0, %v24
+; CHECK-NEXT:    vlcb %v24, %v0
+; CHECK-NEXT:    br %r14
   %cmp = icmp slt <16 x i8> %val, zeroinitializer
   %neg = sub <16 x i8> zeroinitializer, %val
   %ret = select <16 x i1> %cmp, <16 x i8> %val, <16 x i8> %neg
   ret <16 x i8> %ret
 }
 
 ; Test with sle.
 define <16 x i8> @f7(<16 x i8> %val) {
 ; CHECK-LABEL: f7:
-; CHECK: vlpb [[REG:%v[0-9]+]], %v24
-; CHECK: vlcb %v24, [[REG]]
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vlpb %v0, %v24
+; CHECK-NEXT:    vlcb %v24, %v0
+; CHECK-NEXT:    br %r14
   %cmp = icmp sle <16 x i8> %val, zeroinitializer
   %neg = sub <16 x i8> zeroinitializer, %val
   %ret = select <16 x i1> %cmp, <16 x i8> %val, <16 x i8> %neg
   ret <16 x i8> %ret
 }
 
 ; Test with sgt.
 define <16 x i8> @f8(<16 x i8> %val) {
 ; CHECK-LABEL: f8:
-; CHECK: vlpb [[REG:%v[0-9]+]], %v24
-; CHECK: vlcb %v24, [[REG]]
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vlpb %v0, %v24
+; CHECK-NEXT:    vlcb %v24, %v0
+; CHECK-NEXT:    br %r14
   %cmp = icmp sgt <16 x i8> %val, zeroinitializer
   %neg = sub <16 x i8> zeroinitializer, %val
   %ret = select <16 x i1> %cmp, <16 x i8> %neg, <16 x i8> %val
   ret <16 x i8> %ret
 }
 
 ; Test with sge.
 define <16 x i8> @f9(<16 x i8> %val) {
 ; CHECK-LABEL: f9:
-; CHECK: vlpb [[REG:%v[0-9]+]], %v24
-; CHECK: vlcb %v24, [[REG]]
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vlpb %v0, %v24
+; CHECK-NEXT:    vlcb %v24, %v0
+; CHECK-NEXT:    br %r14
   %cmp = icmp sge <16 x i8> %val, zeroinitializer
   %neg = sub <16 x i8> zeroinitializer, %val
   %ret = select <16 x i1> %cmp, <16 x i8> %neg, <16 x i8> %val
   ret <16 x i8> %ret
 }
 
 ; Test with an SRA-based boolean vector.
 define <16 x i8> @f10(<16 x i8> %val) {
 ; CHECK-LABEL: f10:
-; CHECK: vlpb %v24, %v24
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vlpb %v24, %v24
+; CHECK-NEXT:    br %r14
   %shr = ashr <16 x i8> %val,
               <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,
                i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
   %neg = sub <16 x i8> zeroinitializer, %val
   %and1 = and <16 x i8> %shr, %neg
   %not = xor <16 x i8> %shr,
              <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
               i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
   %and2 = and <16 x i8> %not, %val
   %ret = or <16 x i8> %and1, %and2
   ret <16 x i8> %ret
 }
 
 ; ...and again in reverse
 define <16 x i8> @f11(<16 x i8> %val) {
 ; CHECK-LABEL: f11:
-; CHECK: vlpb [[REG:%v[0-9]+]], %v24
-; CHECK: vlcb %v24, [[REG]]
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vlpb %v0, %v24
+; CHECK-NEXT:    vlcb %v24, %v0
+; CHECK-NEXT:    br %r14
   %shr = ashr <16 x i8> %val,
               <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,
                i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
   %and1 = and <16 x i8> %shr, %val
   %not = xor <16 x i8> %shr,
              <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
               i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
   %neg = sub <16 x i8> zeroinitializer, %val
   %and2 = and <16 x i8> %not, %neg
   %ret = or <16 x i8> %and1, %and2
   ret <16 x i8> %ret
 }
+
+; Test using xor masked-merge pattern.
+define <16 x i8> @f12(<16 x i8> %val) {
+; CHECK-LABEL: f12:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vlpb %v24, %v24
+; CHECK-NEXT:    br %r14
+  %shr = ashr <16 x i8> %val,
+              <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,
+               i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
+  %neg = sub <16 x i8> zeroinitializer, %val
+  %xor0 = xor <16 x i8> %neg, %val
+  %and = and <16 x i8> %xor0, %shr
+  %xor1 = xor <16 x i8> %and, %val
+  ret <16 x i8> %xor1
+}
+
+; Test using xor masked-merge pattern in reverse.
+define <16 x i8> @f13(<16 x i8> %val) {
+; CHECK-LABEL: f13:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vlpb %v0, %v24
+; CHECK-NEXT:    vlcb %v24, %v0
+; CHECK-NEXT:    br %r14
+  %shr = ashr <16 x i8> %val,
+              <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,
+               i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
+  %neg = sub <16 x i8> zeroinitializer, %val
+  %xor0 = xor <16 x i8> %neg, %val
+  %and = and <16 x i8> %xor0, %shr
+  %xor1 = xor <16 x i8> %and, %neg
+  ret <16 x i8> %xor1
+}

llvm/test/CodeGen/SystemZ/vec-masked-merge.ll

+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+define <2 x i64> @masked_merge0(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> %a2) {
+; CHECK-LABEL: masked_merge0
+; CHECK: vsel %v24, %v26, %v28, %v24
+; CHECK: br %r14
+  %and0 = and <2 x i64> %a0, %a1
+  %not = xor <2 x i64> %a0, <i64 -1, i64 -1>
+  %and1 = and <2 x i64> %not, %a2
+  %or = or <2 x i64> %and0, %and1
+  ret <2 x i64> %or
+}
+
+define <2 x i64> @masked_merge1(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> %a2) {
+; CHECK-LABEL: masked_merge1
+; CHECK: vsel %v24, %v26, %v28, %v24
+; CHECK: br %r14
+  %xor0 = xor <2 x i64> %a1, %a2
+  %and = and <2 x i64> %xor0, %a0
+  %xor1 = xor <2 x i64> %and, %a2
+  ret <2 x i64> %xor1
+}