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[RISCV] Transform unaligned RVV vector loads/stores to aligned ones
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Authored by frasercrmck on Jun 10 2021, 7:31 AM.

Details

Summary

This patch adds support for loading and storing unaligned vectors via an
equivalently-sized i8 vector type, which has support in the RVV
specification for byte-aligned access.

This offers a more optimal path for handling of unaligned fixed-length
vector accesses, which are currently scalarized. It also prevents
crashing when LegalizeDAG sees an unaligned scalable-vector load/store
operation.

Future work could be to investigate loading/storing via the largest
vector element type for the given alignment, in case that would be more
optimal on hardware. For instance, a 4-byte-aligned nxv2i64 vector load
could loaded as nxv4i32 instead of as nxv16i8.

Diff Detail

Event Timeline

frasercrmck created this revision.Jun 10 2021, 7:31 AM
frasercrmck requested review of this revision.Jun 10 2021, 7:31 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 10 2021, 7:31 AM
craig.topper added inline comments.Jun 14 2021, 9:01 AM
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
1906

cast instead of dyn_cast?

1935

cast

  • rebase
  • use cast over dyn_cast
frasercrmck marked 2 inline comments as done.Jun 14 2021, 9:22 AM
frasercrmck added inline comments.
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
1906

Good catch, thanks.

This revision is now accepted and ready to land.Jun 14 2021, 9:28 AM
This revision was automatically updated to reflect the committed changes.
frasercrmck marked an inline comment as done.